STM32F401 1.1 STM32F401 CM4 r1p0 little false false 3 false 8 32 0x20 0x0 0xFFFFFFFF ADC_Common ADC common registers ADC 0x40012300 0x0 0x9 registers FPU FPU interrupt 81 CSR CSR ADC Common status register 0x0 0x20 read-only 0x00000000 OVR3 Overrun flag of ADC3 21 1 STRT3 Regular channel Start flag of ADC 3 20 1 JSTRT3 Injected channel Start flag of ADC 3 19 1 JEOC3 Injected channel end of conversion of ADC 3 18 1 EOC3 End of conversion of ADC 3 17 1 AWD3 Analog watchdog flag of ADC 3 16 1 OVR2 Overrun flag of ADC 2 13 1 STRT2 Regular channel Start flag of ADC 2 12 1 JSTRT2 Injected channel Start flag of ADC 2 11 1 JEOC2 Injected channel end of conversion of ADC 2 10 1 EOC2 End of conversion of ADC 2 9 1 AWD2 Analog watchdog flag of ADC 2 8 1 OVR1 Overrun flag of ADC 1 5 1 STRT1 Regular channel Start flag of ADC 1 4 1 JSTRT1 Injected channel Start flag of ADC 1 3 1 JEOC1 Injected channel end of conversion of ADC 1 2 1 EOC1 End of conversion of ADC 1 1 1 AWD1 Analog watchdog flag of ADC 1 0 1 CCR CCR ADC common control register 0x4 0x20 read-write 0x00000000 TSVREFE Temperature sensor and VREFINT enable 23 1 VBATE VBAT enable 22 1 ADCPRE ADC prescaler 16 2 DMA Direct memory access mode for multi ADC mode 14 2 DDS DMA disable selection for multi-ADC mode 13 1 DELAY Delay between 2 sampling phases 8 4 ADC1 Analog-to-digital converter ADC 0x40012000 0x0 0x51 registers ADC ADC1 global interrupt 18 SR SR status register 0x0 0x20 read-write 0x00000000 OVR Overrun 5 1 STRT Regular channel start flag 4 1 JSTRT Injected channel start flag 3 1 JEOC Injected channel end of conversion 2 1 EOC Regular channel end of conversion 1 1 AWD Analog watchdog flag 0 1 CR1 CR1 control register 1 0x4 0x20 read-write 0x00000000 OVRIE Overrun interrupt enable 26 1 RES Resolution 24 2 AWDEN Analog watchdog enable on regular channels 23 1 JAWDEN Analog watchdog enable on injected channels 22 1 DISCNUM Discontinuous mode channel count 13 3 JDISCEN Discontinuous mode on injected channels 12 1 DISCEN Discontinuous mode on regular channels 11 1 JAUTO Automatic injected group conversion 10 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 SCAN Scan mode 8 1 JEOCIE Interrupt enable for injected channels 7 1 AWDIE Analog watchdog interrupt enable 6 1 EOCIE Interrupt enable for EOC 5 1 AWDCH Analog watchdog channel select bits 0 5 CR2 CR2 control register 2 0x8 0x20 read-write 0x00000000 SWSTART Start conversion of regular channels 30 1 EXTEN External trigger enable for regular channels 28 2 EXTSEL External event select for regular group 24 4 JSWSTART Start conversion of injected channels 22 1 JEXTEN External trigger enable for injected channels 20 2 JEXTSEL External event select for injected group 16 4 ALIGN Data alignment 11 1 EOCS End of conversion selection 10 1 DDS DMA disable selection (for single ADC mode) 9 1 DMA Direct memory access mode (for single ADC mode) 8 1 CONT Continuous conversion 1 1 ADON A/D Converter ON / OFF 0 1 SMPR1 SMPR1 sample time register 1 0xC 0x20 read-write 0x00000000 SMPx_x Sample time bits 0 32 SMPR2 SMPR2 sample time register 2 0x10 0x20 read-write 0x00000000 SMPx_x Sample time bits 0 32 JOFR1 JOFR1 injected channel data offset register x 0x14 0x20 read-write 0x00000000 JOFFSET1 Data offset for injected channel x 0 12 JOFR2 JOFR2 injected channel data offset register x 0x18 0x20 read-write 0x00000000 JOFFSET2 Data offset for injected channel x 0 12 JOFR3 JOFR3 injected channel data offset register x 0x1C 0x20 read-write 0x00000000 JOFFSET3 Data offset for injected channel x 0 12 JOFR4 JOFR4 injected channel data offset register x 0x20 0x20 read-write 0x00000000 JOFFSET4 Data offset for injected channel x 0 12 HTR HTR watchdog higher threshold register 0x24 0x20 read-write 0x00000FFF HT Analog watchdog higher threshold 0 12 LTR LTR watchdog lower threshold register 0x28 0x20 read-write 0x00000000 LT Analog watchdog lower threshold 0 12 SQR1 SQR1 regular sequence register 1 0x2C 0x20 read-write 0x00000000 L Regular channel sequence length 20 4 SQ16 16th conversion in regular sequence 15 5 SQ15 15th conversion in regular sequence 10 5 SQ14 14th conversion in regular sequence 5 5 SQ13 13th conversion in regular sequence 0 5 SQR2 SQR2 regular sequence register 2 0x30 0x20 read-write 0x00000000 SQ12 12th conversion in regular sequence 25 5 SQ11 11th conversion in regular sequence 20 5 SQ10 10th conversion in regular sequence 15 5 SQ9 9th conversion in regular sequence 10 5 SQ8 8th conversion in regular sequence 5 5 SQ7 7th conversion in regular sequence 0 5 SQR3 SQR3 regular sequence register 3 0x34 0x20 read-write 0x00000000 SQ6 6th conversion in regular sequence 25 5 SQ5 5th conversion in regular sequence 20 5 SQ4 4th conversion in regular sequence 15 5 SQ3 3rd conversion in regular sequence 10 5 SQ2 2nd conversion in regular sequence 5 5 SQ1 1st conversion in regular sequence 0 5 JSQR JSQR injected sequence register 0x38 0x20 read-write 0x00000000 JL Injected sequence length 20 2 JSQ4 4th conversion in injected sequence 15 5 JSQ3 3rd conversion in injected sequence 10 5 JSQ2 2nd conversion in injected sequence 5 5 JSQ1 1st conversion in injected sequence 0 5 JDR1 JDR1 injected data register x 0x3C 0x20 read-only 0x00000000 JDATA Injected data 0 16 JDR2 JDR2 injected data register x 0x40 0x20 read-only 0x00000000 JDATA Injected data 0 16 JDR3 JDR3 injected data register x 0x44 0x20 read-only 0x00000000 JDATA Injected data 0 16 JDR4 JDR4 injected data register x 0x48 0x20 read-only 0x00000000 JDATA Injected data 0 16 DR DR regular data register 0x4C 0x20 read-only 0x00000000 DATA Regular data 0 16 CRC Cryptographic processor CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data Register 0 32 IDR IDR Independent Data register 0x4 0x20 read-write 0x00000000 IDR Independent Data register 0 8 CR CR Control register 0x8 0x20 write-only 0x00000000 CR Control regidter 0 1 DBG Debug support DBG 0xE0042000 0x0 0x400 registers DBGMCU_IDCODE DBGMCU_IDCODE IDCODE 0x0 0x20 read-only 0x10006411 DEV_ID DEV_ID 0 12 REV_ID REV_ID 16 16 DBGMCU_CR DBGMCU_CR Control Register 0x4 0x20 read-write 0x00000000 DBG_SLEEP DBG_SLEEP 0 1 DBG_STOP DBG_STOP 1 1 DBG_STANDBY DBG_STANDBY 2 1 TRACE_IOEN TRACE_IOEN 5 1 TRACE_MODE TRACE_MODE 6 2 DBGMCU_APB1_FZ DBGMCU_APB1_FZ Debug MCU APB1 Freeze registe 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP DBG_TIM2_STOP 0 1 DBG_TIM3_STOP DBG_TIM3 _STOP 1 1 DBG_TIM4_STOP DBG_TIM4_STOP 2 1 DBG_TIM5_STOP DBG_TIM5_STOP 3 1 DBG_RTC_Stop RTC stopped when Core is halted 10 1 DBG_WWDG_STOP DBG_WWDG_STOP 11 1 DBG_IWDEG_STOP DBG_IWDEG_STOP 12 1 DBG_I2C1_SMBUS_TIMEOUT DBG_J2C1_SMBUS_TIMEOUT 21 1 DBG_I2C2_SMBUS_TIMEOUT DBG_J2C2_SMBUS_TIMEOUT 22 1 DBG_I2C3SMBUS_TIMEOUT DBG_J2C3SMBUS_TIMEOUT 23 1 DBGMCU_APB2_FZ DBGMCU_APB2_FZ Debug MCU APB2 Freeze registe 0xC 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 0 1 DBG_TIM9_STOP TIM9 counter stopped when core is halted 16 1 DBG_TIM10_STOP TIM10 counter stopped when core is halted 17 1 DBG_TIM11_STOP TIM11 counter stopped when core is halted 18 1 EXTI External interrupt/event controller EXTI 0x40013C00 0x0 0x400 registers TAMP_STAMP Tamper and TimeStamp interrupts through the EXTI line 2 EXTI0 EXTI Line0 interrupt 6 EXTI1 EXTI Line1 interrupt 7 EXTI2 EXTI Line2 interrupt 8 EXTI3 EXTI Line3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 EXTI9_5 EXTI Line[9:5] interrupts 23 EXTI15_10 EXTI Line[15:10] interrupts 40 IMR IMR Interrupt mask register (EXTI_IMR) 0x0 0x20 read-write 0x00000000 MR0 Interrupt Mask on line 0 0 1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR20 Interrupt Mask on line 20 20 1 MR21 Interrupt Mask on line 21 21 1 MR22 Interrupt Mask on line 22 22 1 EMR EMR Event mask register (EXTI_EMR) 0x4 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR20 Event Mask on line 20 20 1 MR21 Event Mask on line 21 21 1 MR22 Event Mask on line 22 22 1 RTSR RTSR Rising Trigger selection register (EXTI_RTSR) 0x8 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR17 Rising trigger event configuration of line 17 17 1 TR18 Rising trigger event configuration of line 18 18 1 TR19 Rising trigger event configuration of line 19 19 1 TR20 Rising trigger event configuration of line 20 20 1 TR21 Rising trigger event configuration of line 21 21 1 TR22 Rising trigger event configuration of line 22 22 1 FTSR FTSR Falling Trigger selection register (EXTI_FTSR) 0xC 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR17 Falling trigger event configuration of line 17 17 1 TR18 Falling trigger event configuration of line 18 18 1 TR19 Falling trigger event configuration of line 19 19 1 TR20 Falling trigger event configuration of line 20 20 1 TR21 Falling trigger event configuration of line 21 21 1 TR22 Falling trigger event configuration of line 22 22 1 SWIER SWIER Software interrupt event register (EXTI_SWIER) 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER17 Software Interrupt on line 17 17 1 SWIER18 Software Interrupt on line 18 18 1 SWIER19 Software Interrupt on line 19 19 1 SWIER20 Software Interrupt on line 20 20 1 SWIER21 Software Interrupt on line 21 21 1 SWIER22 Software Interrupt on line 22 22 1 PR PR Pending register (EXTI_PR) 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 PR1 Pending bit 1 1 1 PR2 Pending bit 2 2 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 PR10 Pending bit 10 10 1 PR11 Pending bit 11 11 1 PR12 Pending bit 12 12 1 PR13 Pending bit 13 13 1 PR14 Pending bit 14 14 1 PR15 Pending bit 15 15 1 PR16 Pending bit 16 16 1 PR17 Pending bit 17 17 1 PR18 Pending bit 18 18 1 PR19 Pending bit 19 19 1 PR20 Pending bit 20 20 1 PR21 Pending bit 21 21 1 PR22 Pending bit 22 22 1 FLASH FLASH FLASH 0x40023C00 0x0 0x400 registers FLASH FLASH global interrupt 4 ACR ACR Flash access control register 0x0 0x20 0x00000000 LATENCY Latency 0 3 read-write PRFTEN Prefetch enable 8 1 read-write ICEN Instruction cache enable 9 1 read-write DCEN Data cache enable 10 1 read-write ICRST Instruction cache reset 11 1 write-only DCRST Data cache reset 12 1 read-write KEYR KEYR Flash key register 0x4 0x20 write-only 0x00000000 KEY FPEC key 0 32 OPTKEYR OPTKEYR Flash option key register 0x8 0x20 write-only 0x00000000 OPTKEY Option byte key 0 32 SR SR Status register 0xC 0x20 0x00000000 EOP End of operation 0 1 read-write OPERR Operation error 1 1 read-write WRPERR Write protection error 4 1 read-write PGAERR Programming alignment error 5 1 read-write PGPERR Programming parallelism error 6 1 read-write PGSERR Programming sequence error 7 1 read-write BSY Busy 16 1 read-only CR CR Control register 0x10 0x20 read-write 0x80000000 PG Programming 0 1 SER Sector Erase 1 1 MER Mass Erase 2 1 SNB Sector number 3 4 PSIZE Program size 8 2 STRT Start 16 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 LOCK Lock 31 1 OPTCR OPTCR Flash option control register 0x14 0x20 read-write 0x00000014 OPTLOCK Option lock 0 1 OPTSTRT Option start 1 1 BOR_LEV BOR reset Level 2 2 WDG_SW WDG_SW User option bytes 5 1 nRST_STOP nRST_STOP User option bytes 6 1 nRST_STDBY nRST_STDBY User option bytes 7 1 RDP Read protect 8 8 nWRP Not write protect 16 12 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 OTG_FS_DEVICE USB on the go full speed USB_OTG_FS 0x50000800 0x0 0x400 registers FS_DCFG FS_DCFG OTG_FS device configuration register (OTG_FS_DCFG) 0x0 0x20 read-write 0x02200000 DSPD Device speed 0 2 NZLSOHSK Non-zero-length status OUT handshake 2 1 DAD Device address 4 7 PFIVL Periodic frame interval 11 2 FS_DCTL FS_DCTL OTG_FS device control register (OTG_FS_DCTL) 0x4 0x20 0x00000000 RWUSIG Remote wakeup signaling 0 1 read-write SDIS Soft disconnect 1 1 read-write GINSTS Global IN NAK status 2 1 read-only GONSTS Global OUT NAK status 3 1 read-only TCTL Test control 4 3 read-write SGINAK Set global IN NAK 7 1 read-write CGINAK Clear global IN NAK 8 1 read-write SGONAK Set global OUT NAK 9 1 read-write CGONAK Clear global OUT NAK 10 1 read-write POPRGDNE Power-on programming done 11 1 read-write FS_DSTS FS_DSTS OTG_FS device status register (OTG_FS_DSTS) 0x8 0x20 read-only 0x00000010 SUSPSTS Suspend status 0 1 ENUMSPD Enumerated speed 1 2 EERR Erratic error 3 1 FNSOF Frame number of the received SOF 8 14 FS_DIEPMSK FS_DIEPMSK OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) 0x10 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 TOM Timeout condition mask (Non-isochronous endpoints) 3 1 ITTXFEMSK IN token received when TxFIFO empty mask 4 1 INEPNMM IN token received with EP mismatch mask 5 1 INEPNEM IN endpoint NAK effective mask 6 1 FS_DOEPMSK FS_DOEPMSK OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) 0x14 0x20 read-write 0x00000000 XFRCM Transfer completed interrupt mask 0 1 EPDM Endpoint disabled interrupt mask 1 1 STUPM SETUP phase done mask 3 1 OTEPDM OUT token received when endpoint disabled mask 4 1 FS_DAINT FS_DAINT OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) 0x18 0x20 read-only 0x00000000 IEPINT IN endpoint interrupt bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 FS_DAINTMSK FS_DAINTMSK OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) 0x1C 0x20 read-write 0x00000000 IEPM IN EP interrupt mask bits 0 16 OEPINT OUT endpoint interrupt bits 16 16 DVBUSDIS DVBUSDIS OTG_FS device VBUS discharge time register 0x28 0x20 read-write 0x000017D7 VBUSDT Device VBUS discharge time 0 16 DVBUSPULSE DVBUSPULSE OTG_FS device VBUS pulsing time register 0x2C 0x20 read-write 0x000005B8 DVBUSP Device VBUS pulsing time 0 12 DIEPEMPMSK DIEPEMPMSK OTG_FS device IN endpoint FIFO empty interrupt mask register 0x34 0x20 read-write 0x00000000 INEPTXFEM IN EP Tx FIFO empty interrupt mask bits 0 16 FS_DIEPCTL0 FS_DIEPCTL0 OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) 0x100 0x20 0x00000000 MPSIZ Maximum packet size 0 2 read-write USBAEP USB active endpoint 15 1 read-only NAKSTS NAK status 17 1 read-only EPTYP Endpoint type 18 2 read-only STALL STALL handshake 21 1 read-write TXFNUM TxFIFO number 22 4 read-write CNAK Clear NAK 26 1 write-only SNAK Set NAK 27 1 write-only EPDIS Endpoint disable 30 1 read-only EPENA Endpoint enable 31 1 read-only DIEPCTL1 DIEPCTL1 OTG device endpoint-1 control register 0x120 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM_SD1PID SODDFRM/SD1PID 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only TXFNUM TXFNUM 22 4 read-write Stall Stall 21 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DIEPCTL2 DIEPCTL2 OTG device endpoint-2 control register 0x140 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only TXFNUM TXFNUM 22 4 read-write Stall Stall 21 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DIEPCTL3 DIEPCTL3 OTG device endpoint-3 control register 0x160 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only TXFNUM TXFNUM 22 4 read-write Stall Stall 21 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DOEPCTL0 DOEPCTL0 device endpoint-0 control register 0x300 0x20 0x00008000 EPENA EPENA 31 1 write-only EPDIS EPDIS 30 1 read-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only Stall Stall 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-only NAKSTS NAKSTS 17 1 read-only USBAEP USBAEP 15 1 read-only MPSIZ MPSIZ 0 2 read-only DOEPCTL1 DOEPCTL1 device endpoint-1 control register 0x320 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only Stall Stall 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DOEPCTL2 DOEPCTL2 device endpoint-2 control register 0x340 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only Stall Stall 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DOEPCTL3 DOEPCTL3 device endpoint-3 control register 0x360 0x20 0x00000000 EPENA EPENA 31 1 read-write EPDIS EPDIS 30 1 read-write SODDFRM SODDFRM 29 1 write-only SD0PID_SEVNFRM SD0PID/SEVNFRM 28 1 write-only SNAK SNAK 27 1 write-only CNAK CNAK 26 1 write-only Stall Stall 21 1 read-write SNPM SNPM 20 1 read-write EPTYP EPTYP 18 2 read-write NAKSTS NAKSTS 17 1 read-only EONUM_DPID EONUM/DPID 16 1 read-only USBAEP USBAEP 15 1 read-write MPSIZ MPSIZ 0 11 read-write DIEPINT0 DIEPINT0 device endpoint-x interrupt register 0x108 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DIEPINT1 DIEPINT1 device endpoint-1 interrupt register 0x128 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DIEPINT2 DIEPINT2 device endpoint-2 interrupt register 0x148 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DIEPINT3 DIEPINT3 device endpoint-3 interrupt register 0x168 0x20 0x00000080 TXFE TXFE 7 1 read-only INEPNE INEPNE 6 1 read-write ITTXFE ITTXFE 4 1 read-write TOC TOC 3 1 read-write EPDISD EPDISD 1 1 read-write XFRC XFRC 0 1 read-write DOEPINT0 DOEPINT0 device endpoint-0 interrupt register 0x308 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DOEPINT1 DOEPINT1 device endpoint-1 interrupt register 0x328 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DOEPINT2 DOEPINT2 device endpoint-2 interrupt register 0x348 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DOEPINT3 DOEPINT3 device endpoint-3 interrupt register 0x368 0x20 read-write 0x00000080 B2BSTUP B2BSTUP 6 1 OTEPDIS OTEPDIS 4 1 STUP STUP 3 1 EPDISD EPDISD 1 1 XFRC XFRC 0 1 DIEPTSIZ0 DIEPTSIZ0 device endpoint-0 transfer size register 0x110 0x20 read-write 0x00000000 PKTCNT Packet count 19 2 XFRSIZ Transfer size 0 7 DOEPTSIZ0 DOEPTSIZ0 device OUT endpoint-0 transfer size register 0x310 0x20 read-write 0x00000000 STUPCNT SETUP packet count 29 2 PKTCNT Packet count 19 1 XFRSIZ Transfer size 0 7 DIEPTSIZ1 DIEPTSIZ1 device endpoint-1 transfer size register 0x130 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DIEPTSIZ2 DIEPTSIZ2 device endpoint-2 transfer size register 0x150 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DIEPTSIZ3 DIEPTSIZ3 device endpoint-3 transfer size register 0x170 0x20 read-write 0x00000000 MCNT Multi count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DTXFSTS0 DTXFSTS0 OTG_FS device IN endpoint transmit FIFO status register 0x118 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS1 DTXFSTS1 OTG_FS device IN endpoint transmit FIFO status register 0x138 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS2 DTXFSTS2 OTG_FS device IN endpoint transmit FIFO status register 0x158 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DTXFSTS3 DTXFSTS3 OTG_FS device IN endpoint transmit FIFO status register 0x178 0x20 read-only 0x00000000 INEPTFSAV IN endpoint TxFIFO space available 0 16 DOEPTSIZ1 DOEPTSIZ1 device OUT endpoint-1 transfer size register 0x330 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DOEPTSIZ2 DOEPTSIZ2 device OUT endpoint-2 transfer size register 0x350 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 DOEPTSIZ3 DOEPTSIZ3 device OUT endpoint-3 transfer size register 0x370 0x20 read-write 0x00000000 RXDPID_STUPCNT Received data PID/SETUP packet count 29 2 PKTCNT Packet count 19 10 XFRSIZ Transfer size 0 19 OTG_FS_GLOBAL USB on the go full speed USB_OTG_FS 0x50000000 0x0 0x400 registers FS_GOTGCTL FS_GOTGCTL OTG_FS control and status register (OTG_FS_GOTGCTL) 0x0 0x20 0x00000800 SRQSCS Session request success 0 1 read-only SRQ Session request 1 1 read-write HNGSCS Host negotiation success 8 1 read-only HNPRQ HNP request 9 1 read-write HSHNPEN Host set HNP enable 10 1 read-write DHNPEN Device HNP enabled 11 1 read-write CIDSTS Connector ID status 16 1 read-only DBCT Long/short debounce time 17 1 read-only ASVLD A-session valid 18 1 read-only BSVLD B-session valid 19 1 read-only FS_GOTGINT FS_GOTGINT OTG_FS interrupt register (OTG_FS_GOTGINT) 0x4 0x20 read-write 0x00000000 SEDET Session end detected 2 1 SRSSCHG Session request success status change 8 1 HNSSCHG Host negotiation success status change 9 1 HNGDET Host negotiation detected 17 1 ADTOCHG A-device timeout change 18 1 DBCDNE Debounce done 19 1 FS_GAHBCFG FS_GAHBCFG OTG_FS AHB configuration register (OTG_FS_GAHBCFG) 0x8 0x20 read-write 0x00000000 GINT Global interrupt mask 0 1 TXFELVL TxFIFO empty level 7 1 PTXFELVL Periodic TxFIFO empty level 8 1 FS_GUSBCFG FS_GUSBCFG OTG_FS USB configuration register (OTG_FS_GUSBCFG) 0xC 0x20 0x00000A00 TOCAL FS timeout calibration 0 3 read-write PHYSEL Full Speed serial transceiver select 6 1 write-only SRPCAP SRP-capable 8 1 read-write HNPCAP HNP-capable 9 1 read-write TRDT USB turnaround time 10 4 read-write FHMOD Force host mode 29 1 read-write FDMOD Force device mode 30 1 read-write CTXPKT Corrupt Tx packet 31 1 read-write FS_GRSTCTL FS_GRSTCTL OTG_FS reset register (OTG_FS_GRSTCTL) 0x10 0x20 0x20000000 CSRST Core soft reset 0 1 read-write HSRST HCLK soft reset 1 1 read-write FCRST Host frame counter reset 2 1 read-write RXFFLSH RxFIFO flush 4 1 read-write TXFFLSH TxFIFO flush 5 1 read-write TXFNUM TxFIFO number 6 5 read-write AHBIDL AHB master idle 31 1 read-only FS_GINTSTS FS_GINTSTS OTG_FS core interrupt register (OTG_FS_GINTSTS) 0x14 0x20 0x04000020 CMOD Current mode of operation 0 1 read-only MMIS Mode mismatch interrupt 1 1 read-write OTGINT OTG interrupt 2 1 read-only SOF Start of frame 3 1 read-write RXFLVL RxFIFO non-empty 4 1 read-only NPTXFE Non-periodic TxFIFO empty 5 1 read-only GINAKEFF Global IN non-periodic NAK effective 6 1 read-only GOUTNAKEFF Global OUT NAK effective 7 1 read-only ESUSP Early suspend 10 1 read-write USBSUSP USB suspend 11 1 read-write USBRST USB reset 12 1 read-write ENUMDNE Enumeration done 13 1 read-write ISOODRP Isochronous OUT packet dropped interrupt 14 1 read-write EOPF End of periodic frame interrupt 15 1 read-write IEPINT IN endpoint interrupt 18 1 read-only OEPINT OUT endpoint interrupt 19 1 read-only IISOIXFR Incomplete isochronous IN transfer 20 1 read-write IPXFR_INCOMPISOOUT Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode) 21 1 read-write HPRTINT Host port interrupt 24 1 read-only HCINT Host channels interrupt 25 1 read-only PTXFE Periodic TxFIFO empty 26 1 read-only CIDSCHG Connector ID status change 28 1 read-write DISCINT Disconnect detected interrupt 29 1 read-write SRQINT Session request/new session detected interrupt 30 1 read-write WKUPINT Resume/remote wakeup detected interrupt 31 1 read-write FS_GINTMSK FS_GINTMSK OTG_FS interrupt mask register (OTG_FS_GINTMSK) 0x18 0x20 0x00000000 MMISM Mode mismatch interrupt mask 1 1 read-write OTGINT OTG interrupt mask 2 1 read-write SOFM Start of frame mask 3 1 read-write RXFLVLM Receive FIFO non-empty mask 4 1 read-write NPTXFEM Non-periodic TxFIFO empty mask 5 1 read-write GINAKEFFM Global non-periodic IN NAK effective mask 6 1 read-write GONAKEFFM Global OUT NAK effective mask 7 1 read-write ESUSPM Early suspend mask 10 1 read-write USBSUSPM USB suspend mask 11 1 read-write USBRST USB reset mask 12 1 read-write ENUMDNEM Enumeration done mask 13 1 read-write ISOODRPM Isochronous OUT packet dropped interrupt mask 14 1 read-write EOPFM End of periodic frame interrupt mask 15 1 read-write EPMISM Endpoint mismatch interrupt mask 17 1 read-write IEPINT IN endpoints interrupt mask 18 1 read-write OEPINT OUT endpoints interrupt mask 19 1 read-write IISOIXFRM Incomplete isochronous IN transfer mask 20 1 read-write IPXFRM_IISOOXFRM Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode) 21 1 read-write PRTIM Host port interrupt mask 24 1 read-only HCIM Host channels interrupt mask 25 1 read-write PTXFEM Periodic TxFIFO empty mask 26 1 read-write CIDSCHGM Connector ID status change mask 28 1 read-write DISCINT Disconnect detected interrupt mask 29 1 read-write SRQIM Session request/new session detected interrupt mask 30 1 read-write WUIM Resume/remote wakeup detected interrupt mask 31 1 read-write FS_GRXSTSR_Device FS_GRXSTSR_Device OTG_FS Receive status debug read(Device mode) 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 FS_GRXSTSR_Host FS_GRXSTSR_Host OTG_FS Receive status debug read(Host mode) FS_GRXSTSR_Device 0x1C 0x20 read-only 0x00000000 EPNUM Endpoint number 0 4 BCNT Byte count 4 11 DPID Data PID 15 2 PKTSTS Packet status 17 4 FRMNUM Frame number 21 4 FS_GRXFSIZ FS_GRXFSIZ OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) 0x24 0x20 read-write 0x00000200 RXFD RxFIFO depth 0 16 FS_GNPTXFSIZ_Device FS_GNPTXFSIZ_Device OTG_FS non-periodic transmit FIFO size register (Device mode) 0x28 0x20 read-write 0x00000200 TX0FSA Endpoint 0 transmit RAM start address 0 16 TX0FD Endpoint 0 TxFIFO depth 16 16 FS_GNPTXFSIZ_Host FS_GNPTXFSIZ_Host OTG_FS non-periodic transmit FIFO size register (Host mode) FS_GNPTXFSIZ_Device 0x28 0x20 read-write 0x00000200 NPTXFSA Non-periodic transmit RAM start address 0 16 NPTXFD Non-periodic TxFIFO depth 16 16 FS_GNPTXSTS FS_GNPTXSTS OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS) 0x2C 0x20 read-only 0x00080200 NPTXFSAV Non-periodic TxFIFO space available 0 16 NPTQXSAV Non-periodic transmit request queue space available 16 8 NPTXQTOP Top of the non-periodic transmit request queue 24 7 FS_GCCFG FS_GCCFG OTG_FS general core configuration register (OTG_FS_GCCFG) 0x38 0x20 read-write 0x00000000 PWRDWN Power down 16 1 VBUSASEN Enable the VBUS sensing device 18 1 VBUSBSEN Enable the VBUS sensing device 19 1 SOFOUTEN SOF output enable 20 1 FS_CID FS_CID core ID register 0x3C 0x20 read-write 0x00001000 PRODUCT_ID Product ID field 0 32 FS_HPTXFSIZ FS_HPTXFSIZ OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) 0x100 0x20 read-write 0x02000600 PTXSA Host periodic TxFIFO start address 0 16 PTXFSIZ Host periodic TxFIFO depth 16 16 FS_DIEPTXF1 FS_DIEPTXF1 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2) 0x104 0x20 read-write 0x02000400 INEPTXSA IN endpoint FIFO2 transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 FS_DIEPTXF2 FS_DIEPTXF2 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3) 0x108 0x20 read-write 0x02000400 INEPTXSA IN endpoint FIFO3 transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 FS_DIEPTXF3 FS_DIEPTXF3 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4) 0x10C 0x20 read-write 0x02000400 INEPTXSA IN endpoint FIFO4 transmit RAM start address 0 16 INEPTXFD IN endpoint TxFIFO depth 16 16 OTG_FS_HOST USB on the go full speed USB_OTG_FS 0x50000400 0x0 0x400 registers FS_HCFG FS_HCFG OTG_FS host configuration register (OTG_FS_HCFG) 0x0 0x20 0x00000000 FSLSPCS FS/LS PHY clock select 0 2 read-write FSLSS FS- and LS-only support 2 1 read-only HFIR HFIR OTG_FS Host frame interval register 0x4 0x20 read-write 0x0000EA60 FRIVL Frame interval 0 16 FS_HFNUM FS_HFNUM OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM) 0x8 0x20 read-only 0x00003FFF FRNUM Frame number 0 16 FTREM Frame time remaining 16 16 FS_HPTXSTS FS_HPTXSTS OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) 0x10 0x20 0x00080100 PTXFSAVL Periodic transmit data FIFO space available 0 16 read-write PTXQSAV Periodic transmit request queue space available 16 8 read-only PTXQTOP Top of the periodic transmit request queue 24 8 read-only HAINT HAINT OTG_FS Host all channels interrupt register 0x14 0x20 read-only 0x00000000 HAINT Channel interrupts 0 16 HAINTMSK HAINTMSK OTG_FS host all channels interrupt mask register 0x18 0x20 read-write 0x00000000 HAINTM Channel interrupt mask 0 16 FS_HPRT FS_HPRT OTG_FS host port control and status register (OTG_FS_HPRT) 0x40 0x20 0x00000000 PCSTS Port connect status 0 1 read-only PCDET Port connect detected 1 1 read-write PENA Port enable 2 1 read-write PENCHNG Port enable/disable change 3 1 read-write POCA Port overcurrent active 4 1 read-only POCCHNG Port overcurrent change 5 1 read-write PRES Port resume 6 1 read-write PSUSP Port suspend 7 1 read-write PRST Port reset 8 1 read-write PLSTS Port line status 10 2 read-only PPWR Port power 12 1 read-write PTCTL Port test control 13 4 read-write PSPD Port speed 17 2 read-only FS_HCCHAR0 FS_HCCHAR0 OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0) 0x100 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCCHAR1 FS_HCCHAR1 OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1) 0x120 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCCHAR2 FS_HCCHAR2 OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2) 0x140 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCCHAR3 FS_HCCHAR3 OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3) 0x160 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCCHAR4 FS_HCCHAR4 OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4) 0x180 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCCHAR5 FS_HCCHAR5 OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5) 0x1A0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCCHAR6 FS_HCCHAR6 OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6) 0x1C0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCCHAR7 FS_HCCHAR7 OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7) 0x1E0 0x20 read-write 0x00000000 MPSIZ Maximum packet size 0 11 EPNUM Endpoint number 11 4 EPDIR Endpoint direction 15 1 LSDEV Low-speed device 17 1 EPTYP Endpoint type 18 2 MCNT Multicount 20 2 DAD Device address 22 7 ODDFRM Odd frame 29 1 CHDIS Channel disable 30 1 CHENA Channel enable 31 1 FS_HCINT0 FS_HCINT0 OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0) 0x108 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINT1 FS_HCINT1 OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1) 0x128 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINT2 FS_HCINT2 OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2) 0x148 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINT3 FS_HCINT3 OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3) 0x168 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINT4 FS_HCINT4 OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4) 0x188 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINT5 FS_HCINT5 OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5) 0x1A8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINT6 FS_HCINT6 OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6) 0x1C8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINT7 FS_HCINT7 OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7) 0x1E8 0x20 read-write 0x00000000 XFRC Transfer completed 0 1 CHH Channel halted 1 1 STALL STALL response received interrupt 3 1 NAK NAK response received interrupt 4 1 ACK ACK response received/transmitted interrupt 5 1 TXERR Transaction error 7 1 BBERR Babble error 8 1 FRMOR Frame overrun 9 1 DTERR Data toggle error 10 1 FS_HCINTMSK0 FS_HCINTMSK0 OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0) 0x10C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCINTMSK1 FS_HCINTMSK1 OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1) 0x12C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCINTMSK2 FS_HCINTMSK2 OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2) 0x14C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCINTMSK3 FS_HCINTMSK3 OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3) 0x16C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCINTMSK4 FS_HCINTMSK4 OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4) 0x18C 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCINTMSK5 FS_HCINTMSK5 OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5) 0x1AC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCINTMSK6 FS_HCINTMSK6 OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6) 0x1CC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCINTMSK7 FS_HCINTMSK7 OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7) 0x1EC 0x20 read-write 0x00000000 XFRCM Transfer completed mask 0 1 CHHM Channel halted mask 1 1 STALLM STALL response received interrupt mask 3 1 NAKM NAK response received interrupt mask 4 1 ACKM ACK response received/transmitted interrupt mask 5 1 NYET response received interrupt mask 6 1 TXERRM Transaction error mask 7 1 BBERRM Babble error mask 8 1 FRMORM Frame overrun mask 9 1 DTERRM Data toggle error mask 10 1 FS_HCTSIZ0 FS_HCTSIZ0 OTG_FS host channel-0 transfer size register 0x110 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 FS_HCTSIZ1 FS_HCTSIZ1 OTG_FS host channel-1 transfer size register 0x130 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 FS_HCTSIZ2 FS_HCTSIZ2 OTG_FS host channel-2 transfer size register 0x150 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 FS_HCTSIZ3 FS_HCTSIZ3 OTG_FS host channel-3 transfer size register 0x170 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 FS_HCTSIZ4 FS_HCTSIZ4 OTG_FS host channel-x transfer size register 0x190 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 FS_HCTSIZ5 FS_HCTSIZ5 OTG_FS host channel-5 transfer size register 0x1B0 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 FS_HCTSIZ6 FS_HCTSIZ6 OTG_FS host channel-6 transfer size register 0x1D0 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 FS_HCTSIZ7 FS_HCTSIZ7 OTG_FS host channel-7 transfer size register 0x1F0 0x20 read-write 0x00000000 XFRSIZ Transfer size 0 19 PKTCNT Packet count 19 10 DPID Data PID 29 2 OTG_FS_PWRCLK USB on the go full speed USB_OTG_FS 0x50000E00 0x0 0x400 registers FS_PCGCCTL FS_PCGCCTL OTG_FS power and clock gating control register 0x0 0x20 read-write 0x00000000 STPPCLK Stop PHY clock 0 1 GATEHCLK Gate HCLK 1 1 PHYSUSP PHY Suspended 4 1 PWR Power control PWR 0x40007000 0x0 0x400 registers CR CR power control register 0x0 0x20 read-write 0x00000000 VOS Regulator voltage scaling output selection 14 2 ADCDC1 ADCDC1 13 1 FPDS Flash power down in Stop mode 9 1 DBP Disable backup domain write protection 8 1 PLS PVD level selection 5 3 PVDE Power voltage detector enable 4 1 CSBF Clear standby flag 3 1 CWUF Clear wakeup flag 2 1 PDDS Power down deepsleep 1 1 LPDS Low-power deep sleep 0 1 CSR CSR power control/status register 0x4 0x20 0x00000000 WUF Wakeup flag 0 1 read-only SBF Standby flag 1 1 read-only PVDO PVD output 2 1 read-only BRR Backup regulator ready 3 1 read-only EWUP Enable WKUP pin 8 1 read-write BRE Backup regulator enable 9 1 read-write VOSRDY Regulator voltage scaling output selection ready bit 14 1 read-write RCC Reset and clock control RCC 0x40023800 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR CR clock control register 0x0 0x20 0x00000083 PLLI2SRDY PLLI2S clock ready flag 27 1 read-only PLLI2SON PLLI2S enable 26 1 read-write PLLRDY Main PLL (PLL) clock ready flag 25 1 read-only PLLON Main PLL (PLL) enable 24 1 read-write CSSON Clock security system enable 19 1 read-write HSEBYP HSE clock bypass 18 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable 16 1 read-write HSICAL Internal high-speed clock calibration 8 8 read-only HSITRIM Internal high-speed clock trimming 3 5 read-write HSIRDY Internal high-speed clock ready flag 1 1 read-only HSION Internal high-speed clock enable 0 1 read-write PLLCFGR PLLCFGR PLL configuration register 0x4 0x20 read-write 0x24003010 PLLQ3 Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks 27 1 PLLQ2 Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks 26 1 PLLQ1 Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks 25 1 PLLQ0 Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks 24 1 PLLSRC Main PLL(PLL) and audio PLL (PLLI2S) entry clock source 22 1 PLLP1 Main PLL (PLL) division factor for main system clock 17 1 PLLP0 Main PLL (PLL) division factor for main system clock 16 1 PLLN8 Main PLL (PLL) multiplication factor for VCO 14 1 PLLN7 Main PLL (PLL) multiplication factor for VCO 13 1 PLLN6 Main PLL (PLL) multiplication factor for VCO 12 1 PLLN5 Main PLL (PLL) multiplication factor for VCO 11 1 PLLN4 Main PLL (PLL) multiplication factor for VCO 10 1 PLLN3 Main PLL (PLL) multiplication factor for VCO 9 1 PLLN2 Main PLL (PLL) multiplication factor for VCO 8 1 PLLN1 Main PLL (PLL) multiplication factor for VCO 7 1 PLLN0 Main PLL (PLL) multiplication factor for VCO 6 1 PLLM5 Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock 5 1 PLLM4 Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock 4 1 PLLM3 Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock 3 1 PLLM2 Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock 2 1 PLLM1 Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock 1 1 PLLM0 Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock 0 1 CFGR CFGR clock configuration register 0x8 0x20 0x00000000 MCO2 Microcontroller clock output 2 30 2 read-write MCO2PRE MCO2 prescaler 27 3 read-write MCO1PRE MCO1 prescaler 24 3 read-write I2SSRC I2S clock selection 23 1 read-write MCO1 Microcontroller clock output 1 21 2 read-write RTCPRE HSE division factor for RTC clock 16 5 read-write PPRE2 APB high-speed prescaler (APB2) 13 3 read-write PPRE1 APB Low speed prescaler (APB1) 10 3 read-write HPRE AHB prescaler 4 4 read-write SWS1 System clock switch status 3 1 read-only SWS0 System clock switch status 2 1 read-only SW1 System clock switch 1 1 read-write SW0 System clock switch 0 1 read-write CIR CIR clock interrupt register 0xC 0x20 0x00000000 CSSC Clock security system interrupt clear 23 1 write-only PLLI2SRDYC PLLI2S ready interrupt clear 21 1 write-only PLLRDYC Main PLL(PLL) ready interrupt clear 20 1 write-only HSERDYC HSE ready interrupt clear 19 1 write-only HSIRDYC HSI ready interrupt clear 18 1 write-only LSERDYC LSE ready interrupt clear 17 1 write-only LSIRDYC LSI ready interrupt clear 16 1 write-only PLLI2SRDYIE PLLI2S ready interrupt enable 13 1 read-write PLLRDYIE Main PLL (PLL) ready interrupt enable 12 1 read-write HSERDYIE HSE ready interrupt enable 11 1 read-write HSIRDYIE HSI ready interrupt enable 10 1 read-write LSERDYIE LSE ready interrupt enable 9 1 read-write LSIRDYIE LSI ready interrupt enable 8 1 read-write CSSF Clock security system interrupt flag 7 1 read-only PLLI2SRDYF PLLI2S ready interrupt flag 5 1 read-only PLLRDYF Main PLL (PLL) ready interrupt flag 4 1 read-only HSERDYF HSE ready interrupt flag 3 1 read-only HSIRDYF HSI ready interrupt flag 2 1 read-only LSERDYF LSE ready interrupt flag 1 1 read-only LSIRDYF LSI ready interrupt flag 0 1 read-only AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x10 0x20 read-write 0x00000000 DMA2RST DMA2 reset 22 1 DMA1RST DMA2 reset 21 1 CRCRST CRC reset 12 1 GPIOHRST IO port H reset 7 1 GPIOERST IO port E reset 4 1 GPIODRST IO port D reset 3 1 GPIOCRST IO port C reset 2 1 GPIOBRST IO port B reset 1 1 GPIOARST IO port A reset 0 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x14 0x20 read-write 0x00000000 OTGFSRST USB OTG FS module reset 7 1 APB1RSTR APB1RSTR APB1 peripheral reset register 0x20 0x20 read-write 0x00000000 PWRRST Power interface reset 28 1 I2C3RST I2C3 reset 23 1 I2C2RST I2C 2 reset 22 1 I2C1RST I2C 1 reset 21 1 UART2RST USART 2 reset 17 1 SPI3RST SPI 3 reset 15 1 SPI2RST SPI 2 reset 14 1 WWDGRST Window watchdog reset 11 1 TIM5RST TIM5 reset 3 1 TIM4RST TIM4 reset 2 1 TIM3RST TIM3 reset 1 1 TIM2RST TIM2 reset 0 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x24 0x20 read-write 0x00000000 TIM11RST TIM11 reset 18 1 TIM10RST TIM10 reset 17 1 TIM9RST TIM9 reset 16 1 SYSCFGRST System configuration controller reset 14 1 SPI1RST SPI 1 reset 12 1 SDIORST SDIO reset 11 1 ADCRST ADC interface reset (common to all ADCs) 8 1 USART6RST USART6 reset 5 1 USART1RST USART1 reset 4 1 TIM1RST TIM1 reset 0 1 AHB1ENR AHB1ENR AHB1 peripheral clock register 0x30 0x20 read-write 0x00100000 DMA2EN DMA2 clock enable 22 1 DMA1EN DMA1 clock enable 21 1 CRCEN CRC clock enable 12 1 GPIOHEN IO port H clock enable 7 1 GPIOEEN IO port E clock enable 4 1 GPIODEN IO port D clock enable 3 1 GPIOCEN IO port C clock enable 2 1 GPIOBEN IO port B clock enable 1 1 GPIOAEN IO port A clock enable 0 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x34 0x20 read-write 0x00000000 OTGFSEN USB OTG FS clock enable 7 1 APB1ENR APB1ENR APB1 peripheral clock enable register 0x40 0x20 read-write 0x00000000 PWREN Power interface clock enable 28 1 I2C3EN I2C3 clock enable 23 1 I2C2EN I2C2 clock enable 22 1 I2C1EN I2C1 clock enable 21 1 USART2EN USART 2 clock enable 17 1 SPI3EN SPI3 clock enable 15 1 SPI2EN SPI2 clock enable 14 1 WWDGEN Window watchdog clock enable 11 1 TIM5EN TIM5 clock enable 3 1 TIM4EN TIM4 clock enable 2 1 TIM3EN TIM3 clock enable 1 1 TIM2EN TIM2 clock enable 0 1 APB2ENR APB2ENR APB2 peripheral clock enable register 0x44 0x20 read-write 0x00000000 TIM11EN TIM11 clock enable 18 1 TIM10EN TIM10 clock enable 17 1 TIM9EN TIM9 clock enable 16 1 SYSCFGEN System configuration controller clock enable 14 1 SPI1EN SPI1 clock enable 12 1 SDIOEN SDIO clock enable 11 1 ADC1EN ADC1 clock enable 8 1 USART6EN USART6 clock enable 5 1 USART1EN USART1 clock enable 4 1 TIM1EN TIM1 clock enable 0 1 AHB1LPENR AHB1LPENR AHB1 peripheral clock enable in low power mode register 0x50 0x20 read-write 0x7E6791FF DMA2LPEN DMA2 clock enable during Sleep mode 22 1 DMA1LPEN DMA1 clock enable during Sleep mode 21 1 SRAM1LPEN SRAM 1interface clock enable during Sleep mode 16 1 FLITFLPEN Flash interface clock enable during Sleep mode 15 1 CRCLPEN CRC clock enable during Sleep mode 12 1 GPIOHLPEN IO port H clock enable during Sleep mode 7 1 GPIOELPEN IO port E clock enable during Sleep mode 4 1 GPIODLPEN IO port D clock enable during Sleep mode 3 1 GPIOCLPEN IO port C clock enable during Sleep mode 2 1 GPIOBLPEN IO port B clock enable during Sleep mode 1 1 GPIOALPEN IO port A clock enable during sleep mode 0 1 AHB2LPENR AHB2LPENR AHB2 peripheral clock enable in low power mode register 0x54 0x20 read-write 0x000000F1 OTGFSLPEN USB OTG FS clock enable during Sleep mode 7 1 APB1LPENR APB1LPENR APB1 peripheral clock enable in low power mode register 0x60 0x20 read-write 0x36FEC9FF PWRLPEN Power interface clock enable during Sleep mode 28 1 I2C3LPEN I2C3 clock enable during Sleep mode 23 1 I2C2LPEN I2C2 clock enable during Sleep mode 22 1 I2C1LPEN I2C1 clock enable during Sleep mode 21 1 USART2LPEN USART2 clock enable during Sleep mode 17 1 SPI3LPEN SPI3 clock enable during Sleep mode 15 1 SPI2LPEN SPI2 clock enable during Sleep mode 14 1 WWDGLPEN Window watchdog clock enable during Sleep mode 11 1 TIM5LPEN TIM5 clock enable during Sleep mode 3 1 TIM4LPEN TIM4 clock enable during Sleep mode 2 1 TIM3LPEN TIM3 clock enable during Sleep mode 1 1 TIM2LPEN TIM2 clock enable during Sleep mode 0 1 APB2LPENR APB2LPENR APB2 peripheral clock enabled in low power mode register 0x64 0x20 read-write 0x00075F33 TIM11LPEN TIM11 clock enable during Sleep mode 18 1 TIM10LPEN TIM10 clock enable during Sleep mode 17 1 TIM9LPEN TIM9 clock enable during sleep mode 16 1 SYSCFGLPEN System configuration controller clock enable during Sleep mode 14 1 SPI1LPEN SPI 1 clock enable during Sleep mode 12 1 SDIOLPEN SDIO clock enable during Sleep mode 11 1 ADC1LPEN ADC1 clock enable during Sleep mode 8 1 USART6LPEN USART6 clock enable during Sleep mode 5 1 USART1LPEN USART1 clock enable during Sleep mode 4 1 TIM1LPEN TIM1 clock enable during Sleep mode 0 1 BDCR BDCR Backup domain control register 0x70 0x20 0x00000000 BDRST Backup domain software reset 16 1 read-write RTCEN RTC clock enable 15 1 read-write RTCSEL1 RTC clock source selection 9 1 read-write RTCSEL0 RTC clock source selection 8 1 read-write LSEBYP External low-speed oscillator bypass 2 1 read-write LSERDY External low-speed oscillator ready 1 1 read-only LSEON External low-speed oscillator enable 0 1 read-write CSR CSR clock control & status register 0x74 0x20 0x0E000000 LPWRRSTF Low-power reset flag 31 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write WDGRSTF Independent watchdog reset flag 29 1 read-write SFTRSTF Software reset flag 28 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write PADRSTF PIN reset flag 26 1 read-write BORRSTF BOR reset flag 25 1 read-write RMVF Remove reset flag 24 1 read-write LSIRDY Internal low-speed oscillator ready 1 1 read-only LSION Internal low-speed oscillator enable 0 1 read-write SSCGR SSCGR spread spectrum clock generation register 0x80 0x20 read-write 0x00000000 SSCGEN Spread spectrum modulation enable 31 1 SPREADSEL Spread Select 30 1 INCSTEP Incrementation step 13 15 MODPER Modulation period 0 13 PLLI2SCFGR PLLI2SCFGR PLLI2S configuration register 0x84 0x20 read-write 0x20003000 PLLI2SRx PLLI2S division factor for I2S clocks 28 3 PLLI2SNx PLLI2S multiplication factor for VCO 6 9 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 CR CR control register 0x8 0x20 read-write 0x00000000 COE Calibration output enable 23 1 OSEL Output selection 21 2 POL Output polarity 20 1 COSEL Calibration Output selection 19 1 BKP Backup 18 1 SUB1H Subtract 1 hour (winter time change) 17 1 ADD1H Add 1 hour (summer time change) 16 1 TSIE Time-stamp interrupt enable 15 1 WUTIE Wakeup timer interrupt enable 14 1 ALRBIE Alarm B interrupt enable 13 1 ALRAIE Alarm A interrupt enable 12 1 TSE Time stamp enable 11 1 WUTE Wakeup timer enable 10 1 ALRBE Alarm B enable 9 1 ALRAE Alarm A enable 8 1 DCE Coarse digital calibration enable 7 1 FMT Hour format 6 1 BYPSHAD Bypass the shadow registers 5 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 TSEDGE Time-stamp event active edge 3 1 WCKSEL Wakeup clock selection 0 3 ISR ISR initialization and status register 0xC 0x20 0x00000007 ALRAWF Alarm A write flag 0 1 read-only ALRBWF Alarm B write flag 1 1 read-only WUTWF Wakeup timer write flag 2 1 read-only SHPF Shift operation pending 3 1 read-write INITS Initialization status flag 4 1 read-only RSF Registers synchronization flag 5 1 read-write INITF Initialization flag 6 1 read-only INIT Initialization mode 7 1 read-write ALRAF Alarm A flag 8 1 read-write ALRBF Alarm B flag 9 1 read-write WUTF Wakeup timer flag 10 1 read-write TSF Time-stamp flag 11 1 read-write TSOVF Time-stamp overflow flag 12 1 read-write TAMP1F Tamper detection flag 13 1 read-write TAMP2F TAMPER2 detection flag 14 1 read-write RECALPF Recalibration pending Flag 16 1 read-only PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 CALIBR CALIBR calibration register 0x18 0x20 read-write 0x00000000 DCS Digital calibration sign 7 1 DC Digital calibration 0 5 ALRMAR ALRMAR alarm A register 0x1C 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMBR ALRMBR alarm B register 0x20 0x20 read-write 0x00000000 MSK4 Alarm B date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm B hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm B minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 TSTR TSTR time stamp time register 0x30 0x20 read-only 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 TSDR TSDR time stamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 16 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW16 Use a 16-second calibration cycle period 13 1 CALM Calibration minus 0 9 TAFCR TAFCR tamper and alternate function configuration register 0x40 0x20 read-write 0x00000000 ALARMOUTTYPE AFO_ALARM output type 18 1 TSINSEL TIMESTAMP mapping 17 1 TAMP1INSEL TAMPER1 mapping 16 1 TAMPPUDIS TAMPER pull-up disable 15 1 TAMPPRCH Tamper precharge duration 13 2 TAMPFLT Tamper filter count 11 2 TAMPFREQ Tamper sampling frequency 8 3 TAMPTS Activate timestamp on tamper detection event 7 1 TAMP2TRG Active level for tamper 2 4 1 TAMP2E Tamper 2 detection enable 3 1 TAMPIE Tamper interrupt enable 2 1 TAMP1TRG Active level for tamper 1 1 1 TAMP1E Tamper 1 detection enable 0 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBSSR ALRMBSSR alarm B sub second register 0x48 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 BKP0R BKP0R backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 BKP1R BKP1R backup register 0x54 0x20 read-write 0x00000000 BKP BKP 0 32 BKP2R BKP2R backup register 0x58 0x20 read-write 0x00000000 BKP BKP 0 32 BKP3R BKP3R backup register 0x5C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP4R BKP4R backup register 0x60 0x20 read-write 0x00000000 BKP BKP 0 32 BKP5R BKP5R backup register 0x64 0x20 read-write 0x00000000 BKP BKP 0 32 BKP6R BKP6R backup register 0x68 0x20 read-write 0x00000000 BKP BKP 0 32 BKP7R BKP7R backup register 0x6C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP8R BKP8R backup register 0x70 0x20 read-write 0x00000000 BKP BKP 0 32 BKP9R BKP9R backup register 0x74 0x20 read-write 0x00000000 BKP BKP 0 32 BKP10R BKP10R backup register 0x78 0x20 read-write 0x00000000 BKP BKP 0 32 BKP11R BKP11R backup register 0x7C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP12R BKP12R backup register 0x80 0x20 read-write 0x00000000 BKP BKP 0 32 BKP13R BKP13R backup register 0x84 0x20 read-write 0x00000000 BKP BKP 0 32 BKP14R BKP14R backup register 0x88 0x20 read-write 0x00000000 BKP BKP 0 32 BKP15R BKP15R backup register 0x8C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP16R BKP16R backup register 0x90 0x20 read-write 0x00000000 BKP BKP 0 32 BKP17R BKP17R backup register 0x94 0x20 read-write 0x00000000 BKP BKP 0 32 BKP18R BKP18R backup register 0x98 0x20 read-write 0x00000000 BKP BKP 0 32 BKP19R BKP19R backup register 0x9C 0x20 read-write 0x00000000 BKP BKP 0 32 SDIO Secure digital input/output interface SDIO 0x40012C00 0x0 0x400 registers I2C3_EV I2C3 event interrupt 72 I2C3_ER I2C3 error interrupt 73 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL PWRCTRL 0 2 CLKCR CLKCR SDI clock control register 0x4 0x20 read-write 0x00000000 HWFC_EN HW Flow Control enable 14 1 NEGEDGE SDIO_CK dephasing selection bit 13 1 WIDBUS Wide bus mode enable bit 11 2 BYPASS Clock divider bypass enable bit 10 1 PWRSAV Power saving configuration bit 9 1 CLKEN Clock enable bit 8 1 CLKDIV Clock divide factor 0 8 ARG ARG argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 CMD CMD command register 0xC 0x20 read-write 0x00000000 CE_ATACMD CE-ATA command 14 1 nIEN not Interrupt Enable 13 1 ENCMDcompl Enable CMD completion 12 1 SDIOSuspend SD I/O suspend command 11 1 CPSMEN Command path state machine (CPSM) Enable bit 10 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal). 9 1 WAITINT CPSM waits for interrupt request 8 1 WAITRESP Wait for response bits 6 2 CMDINDEX Command index 0 6 RESPCMD RESPCMD command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 RESP1 RESP1 response 1..4 register 0x14 0x20 read-only 0x00000000 CARDSTATUS1 Card Status 0 32 RESP2 RESP2 response 1..4 register 0x18 0x20 read-only 0x00000000 CARDSTATUS2 Card Status 0 32 RESP3 RESP3 response 1..4 register 0x1C 0x20 read-only 0x00000000 CARDSTATUS3 Card Status 0 32 RESP4 RESP4 response 1..4 register 0x20 0x20 read-only 0x00000000 CARDSTATUS4 Card Status 0 32 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data timeout period 0 32 DLEN DLEN data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 SDIOEN SD I/O enable functions 11 1 RWMOD Read wait mode 10 1 RWSTOP Read wait stop 9 1 RWSTART Read wait start 8 1 DBLOCKSIZE Data block size 4 4 DMAEN DMA enable bit 3 1 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 2 1 DTDIR Data transfer direction selection 1 1 DTEN DTEN 0 1 DCOUNT DCOUNT data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 STA STA status register 0x34 0x20 read-only 0x00000000 CEATAEND CE-ATA command completion signal received for CMD61 23 1 SDIOIT SDIO interrupt received 22 1 RXDAVL Data available in receive FIFO 21 1 TXDAVL Data available in transmit FIFO 20 1 RXFIFOE Receive FIFO empty 19 1 TXFIFOE Transmit FIFO empty 18 1 RXFIFOF Receive FIFO full 17 1 TXFIFOF Transmit FIFO full 16 1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 RXACT Data receive in progress 13 1 TXACT Data transmit in progress 12 1 CMDACT Command transfer in progress 11 1 DBCKEND Data block sent/received (CRC check passed) 10 1 STBITERR Start bit not detected on all data signals in wide bus mode 9 1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 CMDSENT Command sent (no response required) 7 1 CMDREND Command response received (CRC check passed) 6 1 RXOVERR Received FIFO overrun error 5 1 TXUNDERR Transmit FIFO underrun error 4 1 DTIMEOUT Data timeout 3 1 CTIMEOUT Command response timeout 2 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 CCRCFAIL Command response received (CRC check failed) 0 1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 CEATAENDC CEATAEND flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 DBCKENDC DBCKEND flag clear bit 10 1 STBITERRC STBITERR flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 CCRCFAILC CCRCFAIL flag clear bit 0 1 MASK MASK mask register 0x3C 0x20 read-write 0x00000000 CEATAENDIE CE-ATA command completion signal received interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 RXDAVLIE Data available in Rx FIFO interrupt enable 21 1 TXDAVLIE Data available in Tx FIFO interrupt enable 20 1 RXFIFOEIE Rx FIFO empty interrupt enable 19 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 TXFIFOFIE Tx FIFO full interrupt enable 16 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 RXACTIE Data receive acting interrupt enable 13 1 TXACTIE Data transmit acting interrupt enable 12 1 CMDACTIE Command acting interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 STBITERRIE Start bit error interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 CCRCFAILIE Command CRC fail interrupt enable 0 1 FIFOCNT FIFOCNT FIFO counter register 0x48 0x20 read-only 0x00000000 FIFOCOUNT Remaining number of words to be written to or read from the FIFO. 0 24 FIFO FIFO data FIFO register 0x80 0x20 read-write 0x00000000 FIFOData Receive and transmit FIFO data 0 32 SYSCFG System configuration controller SYSCFG 0x40013800 0x0 0x400 registers MEMRM MEMRM memory remap register 0x0 0x20 read-write 0x00000000 MEM_MODE MEM_MODE 0 2 PMC PMC peripheral mode configuration register 0x4 0x20 read-write 0x00000000 ADC1DC2 ADC1DC2 16 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x0000 EXTI3 EXTI x configuration (x = 0 to 3) 12 4 EXTI2 EXTI x configuration (x = 0 to 3) 8 4 EXTI1 EXTI x configuration (x = 0 to 3) 4 4 EXTI0 EXTI x configuration (x = 0 to 3) 0 4 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x0000 EXTI7 EXTI x configuration (x = 4 to 7) 12 4 EXTI6 EXTI x configuration (x = 4 to 7) 8 4 EXTI5 EXTI x configuration (x = 4 to 7) 4 4 EXTI4 EXTI x configuration (x = 4 to 7) 0 4 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x0000 EXTI11 EXTI x configuration (x = 8 to 11) 12 4 EXTI10 EXTI10 8 4 EXTI9 EXTI x configuration (x = 8 to 11) 4 4 EXTI8 EXTI x configuration (x = 8 to 11) 0 4 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x0000 EXTI15 EXTI x configuration (x = 12 to 15) 12 4 EXTI14 EXTI x configuration (x = 12 to 15) 8 4 EXTI13 EXTI x configuration (x = 12 to 15) 4 4 EXTI12 EXTI x configuration (x = 12 to 15) 0 4 CMPCR CMPCR Compensation cell control register 0x20 0x20 read-only 0x00000000 READY READY 8 1 CMP_PD Compensation cell power-down 0 1 TIM1 Advanced-timers TIM 0x40010000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 TIM8 0x40010400 TIM10 General-purpose-timers TIM 0x40014400 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 TIM11 General-purpose-timers TIM 0x40014800 0x0 0x400 registers SPI2 SPI2 global interrupt 36 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 OR OR option register 0x50 0x20 read-write 0x00000000 RMP Input 1 remapping capability 0 2 TIM2 General purpose timers TIM 0x40000000 0x0 0x400 registers SPI3 SPI3 global interrupt 51 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE OC2CE 15 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 OC2FE OC2FE 10 1 CC2S CC2S 8 2 OC1CE OC1CE 7 1 OC1M OC1M 4 3 OC1PE OC1PE 3 1 OC1FE OC1FE 2 1 CC1S CC1S 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 O24CE O24CE 15 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 OC4FE OC4FE 10 1 CC4S CC4S 8 2 OC3CE OC3CE 7 1 OC3M OC3M 4 3 OC3PE OC3PE 3 1 OC3FE OC3FE 2 1 CC3S CC3S 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value 16 16 CNT_L Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR_H High Auto-reload value 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR OR TIM5 option register 0x50 0x20 read-write 0x0000 ITR1_RMP Timer Input 4 remap 10 2 TIM3 General purpose timers TIM 0x40000400 0x0 0x400 registers SPI4 SPI4 global interrupt 84 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE OC2CE 15 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 OC2FE OC2FE 10 1 CC2S CC2S 8 2 OC1CE OC1CE 7 1 OC1M OC1M 4 3 OC1PE OC1PE 3 1 OC1FE OC1FE 2 1 CC1S CC1S 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 O24CE O24CE 15 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 OC4FE OC4FE 10 1 CC4S CC4S 8 2 OC3CE OC3CE 7 1 OC3M OC3M 4 3 OC3PE OC3PE 3 1 OC3FE OC3FE 2 1 CC3S CC3S 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value 16 16 CNT_L Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR_H High Auto-reload value 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM4 0x40000800 TIM5 General-purpose-timers TIM 0x40000C00 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE OC2CE 15 1 OC2M OC2M 12 3 OC2PE OC2PE 11 1 OC2FE OC2FE 10 1 CC2S CC2S 8 2 OC1CE OC1CE 7 1 OC1M OC1M 4 3 OC1PE OC1PE 3 1 OC1FE OC1FE 2 1 CC1S CC1S 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 O24CE O24CE 15 1 OC4M OC4M 12 3 OC4PE OC4PE 11 1 OC4FE OC4FE 10 1 CC4S CC4S 8 2 OC3CE OC3CE 7 1 OC3M OC3M 4 3 OC3PE OC3PE 3 1 OC3FE OC3FE 2 1 CC3S CC3S 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value 16 16 CNT_L Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR_H High Auto-reload value 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR OR TIM5 option register 0x50 0x20 read-write 0x0000 IT4_RMP Timer Input 4 remap 6 2 TIM9 General purpose timers TIM 0x40014000 0x0 0x400 registers CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TIE Trigger interrupt enable 6 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 3 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 3 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40011000 0x0 0x400 registers OTG_FS_WKUP USB On-The-Go FS Wakeup through EXTI line interrupt 42 OTG_FS USB On The Go FS global interrupt 67 SR SR Status register 0x0 0x20 0x00C00000 CTS CTS flag 9 1 read-write LBD LIN break detection flag 8 1 read-write TXE Transmit data register empty 7 1 read-only TC Transmission complete 6 1 read-write RXNE Read data register not empty 5 1 read-write IDLE IDLE line detected 4 1 read-only ORE Overrun error 3 1 read-only NF Noise detected flag 2 1 read-only FE Framing error 1 1 read-only PE Parity error 0 1 read-only DR DR Data register 0x4 0x20 read-write 0x00000000 DR Data value 0 9 BRR BRR Baud rate register 0x8 0x20 read-write 0x0000 DIV_Mantissa mantissa of USARTDIV 4 12 DIV_Fraction fraction of USARTDIV 0 4 CR1 CR1 Control register 1 0xC 0x20 read-write 0x0000 OVER8 Oversampling mode 15 1 UE USART enable 13 1 M Word length 12 1 WAKE Wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE TXE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 SBK Send break 0 1 CR2 CR2 Control register 2 0x10 0x20 read-write 0x0000 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 ADD Address of the USART node 0 4 CR3 CR3 Control register 3 0x14 0x20 read-write 0x0000 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 EIE Error interrupt enable 0 1 GTPR GTPR Guard time and prescaler register 0x18 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 USART2 0x40004400 USART6 0x40011400 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers PVD PVD through EXTI line detection interrupt 1 CR CR Control register 0x0 0x20 read-write 0x7F WDGA Activation bit 7 1 T 7-bit counter (MSB to LSB) 0 7 CFR CFR Configuration register 0x4 0x20 read-write 0x7F EWI Early wakeup interrupt 9 1 WDGTB1 Timer base 8 1 WDGTB0 Timer base 7 1 W 7-bit window value 0 7 SR SR Status register 0x8 0x20 read-write 0x00 EWIF Early wakeup interrupt flag 0 1 DMA2 DMA controller DMA 0x40026400 0x0 0x400 registers RCC RCC global interrupt 5 LISR LISR low interrupt status register 0x0 0x20 read-only 0x00000000 TCIF3 Stream x transfer complete interrupt flag (x = 3..0) 27 1 HTIF3 Stream x half transfer interrupt flag (x=3..0) 26 1 TEIF3 Stream x transfer error interrupt flag (x=3..0) 25 1 DMEIF3 Stream x direct mode error interrupt flag (x=3..0) 24 1 FEIF3 Stream x FIFO error interrupt flag (x=3..0) 22 1 TCIF2 Stream x transfer complete interrupt flag (x = 3..0) 21 1 HTIF2 Stream x half transfer interrupt flag (x=3..0) 20 1 TEIF2 Stream x transfer error interrupt flag (x=3..0) 19 1 DMEIF2 Stream x direct mode error interrupt flag (x=3..0) 18 1 FEIF2 Stream x FIFO error interrupt flag (x=3..0) 16 1 TCIF1 Stream x transfer complete interrupt flag (x = 3..0) 11 1 HTIF1 Stream x half transfer interrupt flag (x=3..0) 10 1 TEIF1 Stream x transfer error interrupt flag (x=3..0) 9 1 DMEIF1 Stream x direct mode error interrupt flag (x=3..0) 8 1 FEIF1 Stream x FIFO error interrupt flag (x=3..0) 6 1 TCIF0 Stream x transfer complete interrupt flag (x = 3..0) 5 1 HTIF0 Stream x half transfer interrupt flag (x=3..0) 4 1 TEIF0 Stream x transfer error interrupt flag (x=3..0) 3 1 DMEIF0 Stream x direct mode error interrupt flag (x=3..0) 2 1 FEIF0 Stream x FIFO error interrupt flag (x=3..0) 0 1 HISR HISR high interrupt status register 0x4 0x20 read-only 0x00000000 TCIF7 Stream x transfer complete interrupt flag (x=7..4) 27 1 HTIF7 Stream x half transfer interrupt flag (x=7..4) 26 1 TEIF7 Stream x transfer error interrupt flag (x=7..4) 25 1 DMEIF7 Stream x direct mode error interrupt flag (x=7..4) 24 1 FEIF7 Stream x FIFO error interrupt flag (x=7..4) 22 1 TCIF6 Stream x transfer complete interrupt flag (x=7..4) 21 1 HTIF6 Stream x half transfer interrupt flag (x=7..4) 20 1 TEIF6 Stream x transfer error interrupt flag (x=7..4) 19 1 DMEIF6 Stream x direct mode error interrupt flag (x=7..4) 18 1 FEIF6 Stream x FIFO error interrupt flag (x=7..4) 16 1 TCIF5 Stream x transfer complete interrupt flag (x=7..4) 11 1 HTIF5 Stream x half transfer interrupt flag (x=7..4) 10 1 TEIF5 Stream x transfer error interrupt flag (x=7..4) 9 1 DMEIF5 Stream x direct mode error interrupt flag (x=7..4) 8 1 FEIF5 Stream x FIFO error interrupt flag (x=7..4) 6 1 TCIF4 Stream x transfer complete interrupt flag (x=7..4) 5 1 HTIF4 Stream x half transfer interrupt flag (x=7..4) 4 1 TEIF4 Stream x transfer error interrupt flag (x=7..4) 3 1 DMEIF4 Stream x direct mode error interrupt flag (x=7..4) 2 1 FEIF4 Stream x FIFO error interrupt flag (x=7..4) 0 1 LIFCR LIFCR low interrupt flag clear register 0x8 0x20 write-only 0x00000000 CTCIF3 Stream x clear transfer complete interrupt flag (x = 3..0) 27 1 CHTIF3 Stream x clear half transfer interrupt flag (x = 3..0) 26 1 CTEIF3 Stream x clear transfer error interrupt flag (x = 3..0) 25 1 CDMEIF3 Stream x clear direct mode error interrupt flag (x = 3..0) 24 1 CFEIF3 Stream x clear FIFO error interrupt flag (x = 3..0) 22 1 CTCIF2 Stream x clear transfer complete interrupt flag (x = 3..0) 21 1 CHTIF2 Stream x clear half transfer interrupt flag (x = 3..0) 20 1 CTEIF2 Stream x clear transfer error interrupt flag (x = 3..0) 19 1 CDMEIF2 Stream x clear direct mode error interrupt flag (x = 3..0) 18 1 CFEIF2 Stream x clear FIFO error interrupt flag (x = 3..0) 16 1 CTCIF1 Stream x clear transfer complete interrupt flag (x = 3..0) 11 1 CHTIF1 Stream x clear half transfer interrupt flag (x = 3..0) 10 1 CTEIF1 Stream x clear transfer error interrupt flag (x = 3..0) 9 1 CDMEIF1 Stream x clear direct mode error interrupt flag (x = 3..0) 8 1 CFEIF1 Stream x clear FIFO error interrupt flag (x = 3..0) 6 1 CTCIF0 Stream x clear transfer complete interrupt flag (x = 3..0) 5 1 CHTIF0 Stream x clear half transfer interrupt flag (x = 3..0) 4 1 CTEIF0 Stream x clear transfer error interrupt flag (x = 3..0) 3 1 CDMEIF0 Stream x clear direct mode error interrupt flag (x = 3..0) 2 1 CFEIF0 Stream x clear FIFO error interrupt flag (x = 3..0) 0 1 HIFCR HIFCR high interrupt flag clear register 0xC 0x20 write-only 0x00000000 CTCIF7 Stream x clear transfer complete interrupt flag (x = 7..4) 27 1 CHTIF7 Stream x clear half transfer interrupt flag (x = 7..4) 26 1 CTEIF7 Stream x clear transfer error interrupt flag (x = 7..4) 25 1 CDMEIF7 Stream x clear direct mode error interrupt flag (x = 7..4) 24 1 CFEIF7 Stream x clear FIFO error interrupt flag (x = 7..4) 22 1 CTCIF6 Stream x clear transfer complete interrupt flag (x = 7..4) 21 1 CHTIF6 Stream x clear half transfer interrupt flag (x = 7..4) 20 1 CTEIF6 Stream x clear transfer error interrupt flag (x = 7..4) 19 1 CDMEIF6 Stream x clear direct mode error interrupt flag (x = 7..4) 18 1 CFEIF6 Stream x clear FIFO error interrupt flag (x = 7..4) 16 1 CTCIF5 Stream x clear transfer complete interrupt flag (x = 7..4) 11 1 CHTIF5 Stream x clear half transfer interrupt flag (x = 7..4) 10 1 CTEIF5 Stream x clear transfer error interrupt flag (x = 7..4) 9 1 CDMEIF5 Stream x clear direct mode error interrupt flag (x = 7..4) 8 1 CFEIF5 Stream x clear FIFO error interrupt flag (x = 7..4) 6 1 CTCIF4 Stream x clear transfer complete interrupt flag (x = 7..4) 5 1 CHTIF4 Stream x clear half transfer interrupt flag (x = 7..4) 4 1 CTEIF4 Stream x clear transfer error interrupt flag (x = 7..4) 3 1 CDMEIF4 Stream x clear direct mode error interrupt flag (x = 7..4) 2 1 CFEIF4 Stream x clear FIFO error interrupt flag (x = 7..4) 0 1 S0CR S0CR stream x configuration register 0x10 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S0NDTR S0NDTR stream x number of data register 0x14 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S0PAR S0PAR stream x peripheral address register 0x18 0x20 read-write 0x00000000 PA Peripheral address 0 32 S0M0AR S0M0AR stream x memory 0 address register 0x1C 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S0M1AR S0M1AR stream x memory 1 address register 0x20 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S0FCR S0FCR stream x FIFO control register 0x24 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write S1CR S1CR stream x configuration register 0x28 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 ACK ACK 20 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S1NDTR S1NDTR stream x number of data register 0x2C 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S1PAR S1PAR stream x peripheral address register 0x30 0x20 read-write 0x00000000 PA Peripheral address 0 32 S1M0AR S1M0AR stream x memory 0 address register 0x34 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S1M1AR S1M1AR stream x memory 1 address register 0x38 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S1FCR S1FCR stream x FIFO control register 0x3C 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write S2CR S2CR stream x configuration register 0x40 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 ACK ACK 20 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S2NDTR S2NDTR stream x number of data register 0x44 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S2PAR S2PAR stream x peripheral address register 0x48 0x20 read-write 0x00000000 PA Peripheral address 0 32 S2M0AR S2M0AR stream x memory 0 address register 0x4C 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S2M1AR S2M1AR stream x memory 1 address register 0x50 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S2FCR S2FCR stream x FIFO control register 0x54 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write S3CR S3CR stream x configuration register 0x58 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 ACK ACK 20 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S3NDTR S3NDTR stream x number of data register 0x5C 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S3PAR S3PAR stream x peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 S3M0AR S3M0AR stream x memory 0 address register 0x64 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S3M1AR S3M1AR stream x memory 1 address register 0x68 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S3FCR S3FCR stream x FIFO control register 0x6C 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write S4CR S4CR stream x configuration register 0x70 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 ACK ACK 20 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S4NDTR S4NDTR stream x number of data register 0x74 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S4PAR S4PAR stream x peripheral address register 0x78 0x20 read-write 0x00000000 PA Peripheral address 0 32 S4M0AR S4M0AR stream x memory 0 address register 0x7C 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S4M1AR S4M1AR stream x memory 1 address register 0x80 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S4FCR S4FCR stream x FIFO control register 0x84 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write S5CR S5CR stream x configuration register 0x88 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 ACK ACK 20 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S5NDTR S5NDTR stream x number of data register 0x8C 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S5PAR S5PAR stream x peripheral address register 0x90 0x20 read-write 0x00000000 PA Peripheral address 0 32 S5M0AR S5M0AR stream x memory 0 address register 0x94 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S5M1AR S5M1AR stream x memory 1 address register 0x98 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S5FCR S5FCR stream x FIFO control register 0x9C 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write S6CR S6CR stream x configuration register 0xA0 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 ACK ACK 20 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S6NDTR S6NDTR stream x number of data register 0xA4 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S6PAR S6PAR stream x peripheral address register 0xA8 0x20 read-write 0x00000000 PA Peripheral address 0 32 S6M0AR S6M0AR stream x memory 0 address register 0xAC 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S6M1AR S6M1AR stream x memory 1 address register 0xB0 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S6FCR S6FCR stream x FIFO control register 0xB4 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write S7CR S7CR stream x configuration register 0xB8 0x20 read-write 0x00000000 CHSEL Channel selection 25 3 MBURST Memory burst transfer configuration 23 2 PBURST Peripheral burst transfer configuration 21 2 ACK ACK 20 1 CT Current target (only in double buffer mode) 19 1 DBM Double buffer mode 18 1 PL Priority level 16 2 PINCOS Peripheral increment offset size 15 1 MSIZE Memory data size 13 2 PSIZE Peripheral data size 11 2 MINC Memory increment mode 10 1 PINC Peripheral increment mode 9 1 CIRC Circular mode 8 1 DIR Data transfer direction 6 2 PFCTRL Peripheral flow controller 5 1 TCIE Transfer complete interrupt enable 4 1 HTIE Half transfer interrupt enable 3 1 TEIE Transfer error interrupt enable 2 1 DMEIE Direct mode error interrupt enable 1 1 EN Stream enable / flag stream ready when read low 0 1 S7NDTR S7NDTR stream x number of data register 0xBC 0x20 read-write 0x00000000 NDT Number of data items to transfer 0 16 S7PAR S7PAR stream x peripheral address register 0xC0 0x20 read-write 0x00000000 PA Peripheral address 0 32 S7M0AR S7M0AR stream x memory 0 address register 0xC4 0x20 read-write 0x00000000 M0A Memory 0 address 0 32 S7M1AR S7M1AR stream x memory 1 address register 0xC8 0x20 read-write 0x00000000 M1A Memory 1 address (used in case of Double buffer mode) 0 32 S7FCR S7FCR stream x FIFO control register 0xCC 0x20 0x00000021 FEIE FIFO error interrupt enable 7 1 read-write FS FIFO status 3 3 read-only DMDIS Direct mode disable 2 1 read-write FTH FIFO threshold selection 0 2 read-write DMA1 0x40026000 RTC_WKUP RTC Wakeup interrupt through the EXTI line 3 RTC_Alarm RTC Alarms (A and B) through EXTI line interrupt 41 GPIOH General-purpose I/Os GPIO 0x40021C00 0x0 0x400 registers SDIO SDIO global interrupt 49 MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOE 0x40021000 GPIOD 0X40020C00 TIM1_BRK_TIM9 TIM1 Break interrupt and TIM9 global interrupt 24 TIM1_UP_TIM10 TIM1 Update interrupt and TIM10 global interrupt 25 TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 26 TIM1_CC TIM1 Capture Compare interrupt 27 GPIOC 0x40020800 TIM1_UP_TIM10 TIM1 Update interrupt and TIM10 global interrupt 25 GPIOB General-purpose I/Os GPIO 0x40020400 0x0 0x400 registers TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 26 MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000280 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOA General-purpose I/Os GPIO 0x40020000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 MODER MODER GPIO port mode register 0x0 0x20 read-write 0xA8000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 I2C3 Inter-integrated circuit I2C 0x40005C00 0x0 0x400 registers TIM3 TIM3 global interrupt 29 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 SWRST Software reset 15 1 ALERT SMBus alert 13 1 PEC Packet error checking 12 1 POS Acknowledge/PEC Position (for data reception) 11 1 ACK Acknowledge enable 10 1 STOP Stop generation 9 1 START Start generation 8 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 ENGC General call enable 6 1 ENPEC PEC enable 5 1 ENARP ARP enable 4 1 SMBTYPE SMBus type 3 1 SMBUS SMBus mode 1 1 PE Peripheral enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 LAST DMA last transfer 12 1 DMAEN DMA requests enable 11 1 ITBUFEN Buffer interrupt enable 10 1 ITEVTEN Event interrupt enable 9 1 ITERREN Error interrupt enable 8 1 FREQ Peripheral clock frequency 0 6 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x0000 ADDMODE Addressing mode (slave mode) 15 1 ADD10 Interface address 8 2 ADD7 Interface address 1 7 ADD0 Interface address 0 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x0000 ADD2 Interface address 1 7 ENDUAL Dual addressing mode enable 0 1 DR DR Data register 0x10 0x20 read-write 0x0000 DR 8-bit data register 0 8 SR1 SR1 Status register 1 0x14 0x20 0x0000 SMBALERT SMBus alert 15 1 read-write TIMEOUT Timeout or Tlow error 14 1 read-write PECERR PEC Error in reception 12 1 read-write OVR Overrun/Underrun 11 1 read-write AF Acknowledge failure 10 1 read-write ARLO Arbitration lost (master mode) 9 1 read-write BERR Bus error 8 1 read-write TxE Data register empty (transmitters) 7 1 read-only RxNE Data register not empty (receivers) 6 1 read-only STOPF Stop detection (slave mode) 4 1 read-only ADD10 10-bit header sent (Master mode) 3 1 read-only BTF Byte transfer finished 2 1 read-only ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only SB Start bit (Master mode) 0 1 read-only SR2 SR2 Status register 2 0x18 0x20 read-only 0x0000 PEC acket error checking register 8 8 DUALF Dual flag (Slave mode) 7 1 SMBHOST SMBus host header (Slave mode) 6 1 SMBDEFAULT SMBus device default address (Slave mode) 5 1 GENCALL General call address (Slave mode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CCR CCR Clock control register 0x1C 0x20 read-write 0x0000 F_S I2C master mode selection 15 1 DUTY Fast mode duty cycle 14 1 CCR Clock control register in Fast/Standard mode (Master mode) 0 12 TRISE TRISE TRISE register 0x20 0x20 read-write 0x0002 TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 I2C2 0x40005800 I2C3_EV I2C3 event interrupt 72 I2C3_ER I2C3 error interrupt 73 I2C1 0x40005400 I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 I2S2ext Serial peripheral interface SPI 0x40003400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TXEIE Tx buffer empty interrupt enable 7 1 RXNEIE RX buffer not empty interrupt enable 6 1 ERRIE Error interrupt enable 5 1 FRF Frame format 4 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 RXDMAEN Rx buffer DMA enable 0 1 SR SR status register 0x8 0x20 0x0002 TIFRFE TI frame format error 8 1 read-only BSY Busy flag 7 1 read-only OVR Overrun flag 6 1 read-only MODF Mode fault 5 1 read-only CRCERR CRC error flag 4 1 read-write UDR Underrun flag 3 1 read-only CHSIDE Channel side 2 1 read-only TXE Transmit buffer empty 1 1 read-only RXNE Receive buffer not empty 0 1 read-only DR DR data register 0xC 0x20 read-write 0x0000 DR Data register 0 16 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x20 read-write 0x0000 I2SMOD I2S mode selection 11 1 I2SE I2S Enable 10 1 I2SCFG I2S configuration mode 8 2 PCMSYNC PCM frame synchronization 7 1 I2SSTD I2S standard selection 4 2 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 CHLEN Channel length (number of bits per audio channel) 0 1 I2SPR I2SPR I2S prescaler register 0x20 0x20 read-write 00000010 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 I2SDIV I2S Linear prescaler 0 8 I2S3ext 0x40004000 SPI1 0x40013000 SPI2 0x40003800 SPI1 SPI1 global interrupt 35 SPI3 0x40003C00 SPI2 SPI2 global interrupt 36 SPI4 0x40013400 SPI3 SPI3 global interrupt 51 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x351 registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 FPU Floting point unit FPU 0xE000EF34 0x0 0xD registers FPU Floating point unit interrupt 81 FPU Floating point interrupt 81 FPCCR FPCCR Floating-point context control register 0x0 0x20 read-write 0x00000000 LSPACT LSPACT 0 1 USER USER 1 1 THREAD THREAD 3 1 HFRDY HFRDY 4 1 MMRDY MMRDY 5 1 BFRDY BFRDY 6 1 MONRDY MONRDY 8 1 LSPEN LSPEN 30 1 ASPEN ASPEN 31 1 FPCAR FPCAR Floating-point context address register 0x4 0x20 read-write 0x00000000 ADDRESS Location of unpopulated floating-point 3 29 FPSCR FPSCR Floating-point status control register 0x8 0x20 read-write 0x00000000 IOC Invalid operation cumulative exception bit 0 1 DZC Division by zero cumulative exception bit. 1 1 OFC Overflow cumulative exception bit 2 1 UFC Underflow cumulative exception bit 3 1 IXC Inexact cumulative exception bit 4 1 IDC Input denormal cumulative exception bit. 7 1 RMode Rounding Mode control field 22 2 FZ Flush-to-zero mode control bit: 24 1 DN Default NaN mode control bit 25 1 AHP Alternative half-precision control bit 26 1 V Overflow condition code flag 28 1 C Carry condition code flag 29 1 Z Zero condition code flag 30 1 N Negative condition code flag 31 1 MPU Memory protection unit MPU 0xE000ED90 0x0 0x15 registers MPU_TYPER MPU_TYPER MPU type register 0x0 0x20 read-only 0X00000800 SEPARATE Separate flag 0 1 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 MPU_CTRL MPU_CTRL MPU control register 0x4 0x20 read-only 0X00000000 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 MPU_RNR MPU_RNR MPU region number register 0x8 0x20 read-write 0X00000000 REGION MPU region 0 8 MPU_RBAR MPU_RBAR MPU region base address register 0xC 0x20 read-write 0X00000000 REGION MPU region field 0 4 VALID MPU region number valid 4 1 ADDR Region base address field 5 27 MPU_RASR MPU_RASR MPU region attribute and size register 0x10 0x20 read-write 0X00000000 ENABLE Region enable bit. 0 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 B memory attribute 16 1 C memory attribute 17 1 S Shareable memory attribute 18 1 TEX memory attribute 19 3 AP Access permission 24 3 XN Instruction access disable bit 28 1 STK SysTick timer STK 0xE000E010 0x0 0x11 registers CTRL CTRL SysTick control and status register 0x0 0x20 read-write 0X00000000 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 LOAD LOAD SysTick reload value register 0x4 0x20 read-write 0X00000000 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 0x20 read-write 0X00000000 CURRENT Current counter value 0 24 CALIB CALIB SysTick calibration value register 0xC 0x20 read-write 0X00000000 TENMS Calibration value 0 24 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 NOREF NOREF flag. Reads as zero 31 1 SCB System control block SCB 0xE000ED00 0x0 0x41 registers CPUID CPUID CPUID base register 0x0 0x20 read-only 0x410FC241 Revision Revision number 0 4 PartNo Part number of the processor 4 12 Constant Reads as 0xF 16 4 Variant Variant number 20 4 Implementer Implementer code 24 8 ICSR ICSR Interrupt control and state register 0x4 0x20 read-write 0x00000000 VECTACTIVE Active vector 0 9 RETTOBASE Return to base level 11 1 VECTPENDING Pending vector 12 7 ISRPENDING Interrupt pending flag 22 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 NMIPENDSET NMI set-pending bit. 31 1 VTOR VTOR Vector table offset register 0x8 0x20 read-write 0x00000000 TBLOFF Vector table base offset field 9 21 AIRCR AIRCR Application interrupt and reset control register 0xC 0x20 read-write 0x00000000 VECTRESET VECTRESET 0 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 SYSRESETREQ SYSRESETREQ 2 1 PRIGROUP PRIGROUP 8 3 ENDIANESS ENDIANESS 15 1 VECTKEYSTAT Register key 16 16 SCR SCR System control register 0x10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 SEVEONPEND Send Event on Pending bit 4 1 CCR CCR Configuration and control register 0x14 0x20 read-write 0x00000000 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 USERSETMPEND USERSETMPEND 1 1 UNALIGN__TRP UNALIGN_ TRP 3 1 DIV_0_TRP DIV_0_TRP 4 1 BFHFNMIGN BFHFNMIGN 8 1 STKALIGN STKALIGN 9 1 SHPR1 SHPR1 System handler priority registers 0x18 0x20 read-write 0x00000000 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 0x20 read-write 0x00000000 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 0x20 read-write 0x00000000 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 SHCRS SHCRS System handler control and state register 0x24 0x20 read-write 0x00000000 MEMFAULTACT Memory management fault exception active bit 0 1 BUSFAULTACT Bus fault exception active bit 1 1 USGFAULTACT Usage fault exception active bit 3 1 SVCALLACT SVC call active bit 7 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTPENDED Usage fault exception pending bit 12 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 SVCALLPENDED SVC call pending bit 15 1 MEMFAULTENA Memory management fault enable bit 16 1 BUSFAULTENA Bus fault enable bit 17 1 USGFAULTENA Usage fault enable bit 18 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 0x20 read-write 0x00000000 IACCVIOL Instruction access violation flag 1 1 MUNSTKERR Memory manager fault on unstacking for a return from exception 3 1 MSTKERR Memory manager fault on stacking for exception entry. 4 1 MLSPERR MLSPERR 5 1 MMARVALID Memory Management Fault Address Register (MMAR) valid flag 7 1 IBUSERR Instruction bus error 8 1 PRECISERR Precise data bus error 9 1 IMPRECISERR Imprecise data bus error 10 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 STKERR Bus fault on stacking for exception entry 12 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 UNDEFINSTR Undefined instruction usage fault 16 1 INVSTATE Invalid state usage fault 17 1 INVPC Invalid PC load usage fault 18 1 NOCP No coprocessor usage fault. 19 1 UNALIGNED Unaligned access usage fault 24 1 DIVBYZERO Divide by zero usage fault 25 1 HFSR HFSR Hard fault status register 0x2C 0x20 read-write 0x00000000 VECTTBL Vector table hard fault 1 1 FORCED Forced hard fault 30 1 DEBUG_VT Reserved for Debug use 31 1 MMFAR MMFAR Memory management fault address register 0x34 0x20 read-write 0x00000000 MMFAR Memory management fault address 0 32 BFAR BFAR Bus fault address register 0x38 0x20 read-write 0x00000000 BFAR Bus fault address 0 32 AFSR AFSR Auxiliary fault status register 0x3C 0x20 read-write 0x00000000 IMPDEF Implementation defined 0 32 NVIC_STIR Nested vectored interrupt controller NVIC 0xE000EF00 0x0 0x5 registers STIR STIR Software trigger interrupt register 0x0 0x20 read-write 0x00000000 INTID Software generated interrupt ID 0 9 FPU_CPACR Floating point unit CPACR FPU 0xE000ED88 0x0 0x5 registers CPACR CPACR Coprocessor access control register 0x0 0x20 read-write 0x0000000 CP CP 20 4 SCB_ACTRL System control block ACTLR SCB 0xE000E008 0x0 0x5 registers ACTRL ACTRL Auxiliary control register 0x0 0x20 read-write 0x00000000 DISMCYCINT DISMCYCINT 0 1 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISOOFP DISOOFP 9 1