<?xml version="1.0" encoding="utf-8" standalone="no"?> <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> <name>STM32F427</name> <version>1.2</version> <description>STM32F427</description> <!-- details about the cpu embedded in the device --> <cpu> <name>CM4</name> <revision>r1p0</revision> <endian>little</endian> <mpuPresent>false</mpuPresent> <fpuPresent>false</fpuPresent> <nvicPrioBits>3</nvicPrioBits> <vendorSystickConfig>false</vendorSystickConfig> </cpu> <!--Bus Interface Properties--> <!--Cortex-M4 is byte addressable--> <addressUnitBits>8</addressUnitBits> <!--the maximum data bit width accessible within a single transfer--> <width>32</width> <!--Register Default Properties--> <size>0x20</size> <resetValue>0x0</resetValue> <resetMask>0xFFFFFFFF</resetMask> <peripherals> <peripheral> <name>RNG</name> <description>Random number generator</description> <groupName>RNG</groupName> <baseAddress>0x50060800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>FPU</name> <description>FPU interrupt</description> <value>81</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IE</name> <description>Interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGEN</name> <description>Random number generator enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>SEIS</name> <description>Seed error interrupt status</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CEIS</name> <description>Clock error interrupt status</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SECS</name> <description>Seed error current status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CECS</name> <description>Clock error current status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>DRDY</name> <description>Data ready</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>data register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RNDATA</name> <description>Random data</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>HASH</name> <description>Hash processor</description> <groupName>HASH</groupName> <baseAddress>0x50060400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>HASH_RNG</name> <description>Hash and Rng global interrupt</description> <value>80</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>INIT</name> <description>Initialize message digest calculation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>DMAE</name> <description>DMA enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DATATYPE</name> <description>Data type selection</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>MODE</name> <description>Mode selection</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALGO0</name> <description>Algorithm selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NBW</name> <description>Number of words already pushed</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> <access>read-only</access> </field> <field> <name>DINNE</name> <description>DIN not empty</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MDMAT</name> <description>Multiple DMA Transfers</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LKEY</name> <description>Long key selection</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALGO1</name> <description>ALGO</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIN</name> <displayName>DIN</displayName> <description>data input register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATAIN</name> <description>Data input</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>STR</name> <displayName>STR</displayName> <description>start register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>DCAL</name> <description>Digest calculation</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>NBLW</name> <description>Number of valid bits in the last word of the message</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>HR0</name> <displayName>HR0</displayName> <description>digest registers</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H0</name> <description>H0</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HR1</name> <displayName>HR1</displayName> <description>digest registers</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H1</name> <description>H1</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HR2</name> <displayName>HR2</displayName> <description>digest registers</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H2</name> <description>H2</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HR3</name> <displayName>HR3</displayName> <description>digest registers</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H3</name> <description>H3</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HR4</name> <displayName>HR4</displayName> <description>digest registers</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H4</name> <description>H4</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IMR</name> <displayName>IMR</displayName> <description>interrupt enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DCIE</name> <description>Digest calculation completion interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DINIE</name> <description>Data input interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <resetValue>0x00000001</resetValue> <fields> <field> <name>BUSY</name> <description>Busy bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>DMAS</name> <description>DMA Status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>DCIS</name> <description>Digest calculation completion interrupt status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DINIS</name> <description>Data input interrupt status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>CSR0</name> <displayName>CSR0</displayName> <description>context swap registers</description> <addressOffset>0xF8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR0</name> <description>CSR0</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR1</name> <displayName>CSR1</displayName> <description>context swap registers</description> <addressOffset>0xFC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR1</name> <description>CSR1</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR2</name> <displayName>CSR2</displayName> <description>context swap registers</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR2</name> <description>CSR2</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR3</name> <displayName>CSR3</displayName> <description>context swap registers</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR3</name> <description>CSR3</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR4</name> <displayName>CSR4</displayName> <description>context swap registers</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR4</name> <description>CSR4</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR5</name> <displayName>CSR5</displayName> <description>context swap registers</description> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR5</name> <description>CSR5</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR6</name> <displayName>CSR6</displayName> <description>context swap registers</description> <addressOffset>0x110</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR6</name> <description>CSR6</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR7</name> <displayName>CSR7</displayName> <description>context swap registers</description> <addressOffset>0x114</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR7</name> <description>CSR7</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR8</name> <displayName>CSR8</displayName> <description>context swap registers</description> <addressOffset>0x118</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR8</name> <description>CSR8</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR9</name> <displayName>CSR9</displayName> <description>context swap registers</description> <addressOffset>0x11C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR9</name> <description>CSR9</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR10</name> <displayName>CSR10</displayName> <description>context swap registers</description> <addressOffset>0x120</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR10</name> <description>CSR10</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR11</name> <displayName>CSR11</displayName> <description>context swap registers</description> <addressOffset>0x124</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR11</name> <description>CSR11</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR12</name> <displayName>CSR12</displayName> <description>context swap registers</description> <addressOffset>0x128</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR12</name> <description>CSR12</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR13</name> <displayName>CSR13</displayName> <description>context swap registers</description> <addressOffset>0x12C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR13</name> <description>CSR13</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR14</name> <displayName>CSR14</displayName> <description>context swap registers</description> <addressOffset>0x130</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR14</name> <description>CSR14</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR15</name> <displayName>CSR15</displayName> <description>context swap registers</description> <addressOffset>0x134</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR15</name> <description>CSR15</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR16</name> <displayName>CSR16</displayName> <description>context swap registers</description> <addressOffset>0x138</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR16</name> <description>CSR16</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR17</name> <displayName>CSR17</displayName> <description>context swap registers</description> <addressOffset>0x13C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR17</name> <description>CSR17</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR18</name> <displayName>CSR18</displayName> <description>context swap registers</description> <addressOffset>0x140</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR18</name> <description>CSR18</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR19</name> <displayName>CSR19</displayName> <description>context swap registers</description> <addressOffset>0x144</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR19</name> <description>CSR19</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR20</name> <displayName>CSR20</displayName> <description>context swap registers</description> <addressOffset>0x148</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR20</name> <description>CSR20</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR21</name> <displayName>CSR21</displayName> <description>context swap registers</description> <addressOffset>0x14C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR21</name> <description>CSR21</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR22</name> <displayName>CSR22</displayName> <description>context swap registers</description> <addressOffset>0x150</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR22</name> <description>CSR22</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR23</name> <displayName>CSR23</displayName> <description>context swap registers</description> <addressOffset>0x154</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR23</name> <description>CSR23</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR24</name> <displayName>CSR24</displayName> <description>context swap registers</description> <addressOffset>0x158</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR24</name> <description>CSR24</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR25</name> <displayName>CSR25</displayName> <description>context swap registers</description> <addressOffset>0x15C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR25</name> <description>CSR25</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR26</name> <displayName>CSR26</displayName> <description>context swap registers</description> <addressOffset>0x160</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR26</name> <description>CSR26</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR27</name> <displayName>CSR27</displayName> <description>context swap registers</description> <addressOffset>0x164</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR27</name> <description>CSR27</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR28</name> <displayName>CSR28</displayName> <description>context swap registers</description> <addressOffset>0x168</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR28</name> <description>CSR28</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR29</name> <displayName>CSR29</displayName> <description>context swap registers</description> <addressOffset>0x16C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR29</name> <description>CSR29</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR30</name> <displayName>CSR30</displayName> <description>context swap registers</description> <addressOffset>0x170</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR30</name> <description>CSR30</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR31</name> <displayName>CSR31</displayName> <description>context swap registers</description> <addressOffset>0x174</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR31</name> <description>CSR31</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR32</name> <displayName>CSR32</displayName> <description>context swap registers</description> <addressOffset>0x178</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR32</name> <description>CSR32</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR33</name> <displayName>CSR33</displayName> <description>context swap registers</description> <addressOffset>0x17C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR33</name> <description>CSR33</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR34</name> <displayName>CSR34</displayName> <description>context swap registers</description> <addressOffset>0x180</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR34</name> <description>CSR34</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR35</name> <displayName>CSR35</displayName> <description>context swap registers</description> <addressOffset>0x184</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR35</name> <description>CSR35</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR36</name> <displayName>CSR36</displayName> <description>context swap registers</description> <addressOffset>0x188</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR36</name> <description>CSR36</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR37</name> <displayName>CSR37</displayName> <description>context swap registers</description> <addressOffset>0x18C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR37</name> <description>CSR37</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR38</name> <displayName>CSR38</displayName> <description>context swap registers</description> <addressOffset>0x190</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR38</name> <description>CSR38</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR39</name> <displayName>CSR39</displayName> <description>context swap registers</description> <addressOffset>0x194</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR39</name> <description>CSR39</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR40</name> <displayName>CSR40</displayName> <description>context swap registers</description> <addressOffset>0x198</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR40</name> <description>CSR40</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR41</name> <displayName>CSR41</displayName> <description>context swap registers</description> <addressOffset>0x19C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR41</name> <description>CSR41</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR42</name> <displayName>CSR42</displayName> <description>context swap registers</description> <addressOffset>0x1A0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR42</name> <description>CSR42</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR43</name> <displayName>CSR43</displayName> <description>context swap registers</description> <addressOffset>0x1A4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR43</name> <description>CSR43</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR44</name> <displayName>CSR44</displayName> <description>context swap registers</description> <addressOffset>0x1A8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR44</name> <description>CSR44</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR45</name> <displayName>CSR45</displayName> <description>context swap registers</description> <addressOffset>0x1AC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR45</name> <description>CSR45</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR46</name> <displayName>CSR46</displayName> <description>context swap registers</description> <addressOffset>0x1B0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR46</name> <description>CSR46</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR47</name> <displayName>CSR47</displayName> <description>context swap registers</description> <addressOffset>0x1B4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR47</name> <description>CSR47</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR48</name> <displayName>CSR48</displayName> <description>context swap registers</description> <addressOffset>0x1B8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR48</name> <description>CSR48</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR49</name> <displayName>CSR49</displayName> <description>context swap registers</description> <addressOffset>0x1BC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR49</name> <description>CSR49</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR50</name> <displayName>CSR50</displayName> <description>context swap registers</description> <addressOffset>0x1C0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR50</name> <description>CSR50</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR51</name> <displayName>CSR51</displayName> <description>context swap registers</description> <addressOffset>0x1C4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR51</name> <description>CSR51</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR52</name> <displayName>CSR52</displayName> <description>context swap registers</description> <addressOffset>0x1C8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR52</name> <description>CSR52</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSR53</name> <displayName>CSR53</displayName> <description>context swap registers</description> <addressOffset>0x1CC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSR53</name> <description>CSR53</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR0</name> <displayName>HASH_HR0</displayName> <description>HASH digest register</description> <addressOffset>0x310</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H0</name> <description>H0</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR1</name> <displayName>HASH_HR1</displayName> <description>read-only</description> <addressOffset>0x314</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H1</name> <description>H1</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR2</name> <displayName>HASH_HR2</displayName> <description>read-only</description> <addressOffset>0x318</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H2</name> <description>H2</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR3</name> <displayName>HASH_HR3</displayName> <description>read-only</description> <addressOffset>0x31C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H3</name> <description>H3</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR4</name> <displayName>HASH_HR4</displayName> <description>read-only</description> <addressOffset>0x320</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H4</name> <description>H4</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR5</name> <displayName>HASH_HR5</displayName> <description>read-only</description> <addressOffset>0x324</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H5</name> <description>H5</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR6</name> <displayName>HASH_HR6</displayName> <description>read-only</description> <addressOffset>0x328</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H6</name> <description>H6</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>HASH_HR7</name> <displayName>HASH_HR7</displayName> <description>read-only</description> <addressOffset>0x32C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>H7</name> <description>H7</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>CRYP</name> <description>Cryptographic processor</description> <groupName>CRYP</groupName> <baseAddress>0x50060000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>CRYP</name> <description>CRYP crypto global interrupt</description> <value>79</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALGODIR</name> <description>Algorithm direction</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALGOMODE0</name> <description>Algorithm mode</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>DATATYPE</name> <description>Data type selection</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>KEYSIZE</name> <description>Key size selection (AES mode only)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>FFLUSH</name> <description>FIFO flush</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CRYPEN</name> <description>Cryptographic processor enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>GCM_CCMPH</name> <description>GCM_CCMPH</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>ALGOMODE3</name> <description>ALGOMODE</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000003</resetValue> <fields> <field> <name>BUSY</name> <description>Busy bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OFFU</name> <description>Output FIFO full</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OFNE</name> <description>Output FIFO not empty</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IFNF</name> <description>Input FIFO not full</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IFEM</name> <description>Input FIFO empty</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DIN</name> <displayName>DIN</displayName> <description>data input register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATAIN</name> <description>Data input</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DOUT</name> <displayName>DOUT</displayName> <description>data output register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATAOUT</name> <description>Data output</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMACR</name> <displayName>DMACR</displayName> <description>DMA control register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DOEN</name> <description>DMA output enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIEN</name> <description>DMA input enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IMSCR</name> <displayName>IMSCR</displayName> <description>interrupt mask set/clear register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OUTIM</name> <description>Output FIFO service interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INIM</name> <description>Input FIFO service interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RISR</name> <displayName>RISR</displayName> <description>raw interrupt status register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000001</resetValue> <fields> <field> <name>OUTRIS</name> <description>Output FIFO service raw interrupt status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INRIS</name> <description>Input FIFO service raw interrupt status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MISR</name> <displayName>MISR</displayName> <description>masked interrupt status register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OUTMIS</name> <description>Output FIFO service masked interrupt status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INMIS</name> <description>Input FIFO service masked interrupt status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K0LR</name> <displayName>K0LR</displayName> <description>key registers</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b224</name> <description>b224</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b225</name> <description>b225</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b226</name> <description>b226</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b227</name> <description>b227</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b228</name> <description>b228</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b229</name> <description>b229</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b230</name> <description>b230</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b231</name> <description>b231</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b232</name> <description>b232</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b233</name> <description>b233</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b234</name> <description>b234</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b235</name> <description>b235</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b236</name> <description>b236</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b237</name> <description>b237</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b238</name> <description>b238</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b239</name> <description>b239</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b240</name> <description>b240</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b241</name> <description>b241</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b242</name> <description>b242</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b243</name> <description>b243</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b244</name> <description>b244</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b245</name> <description>b245</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b246</name> <description>b246</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b247</name> <description>b247</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b248</name> <description>b248</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b249</name> <description>b249</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b250</name> <description>b250</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b251</name> <description>b251</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b252</name> <description>b252</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b253</name> <description>b253</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b254</name> <description>b254</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b255</name> <description>b255</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K0RR</name> <displayName>K0RR</displayName> <description>key registers</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b192</name> <description>b192</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b193</name> <description>b193</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b194</name> <description>b194</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b195</name> <description>b195</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b196</name> <description>b196</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b197</name> <description>b197</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b198</name> <description>b198</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b199</name> <description>b199</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b200</name> <description>b200</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b201</name> <description>b201</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b202</name> <description>b202</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b203</name> <description>b203</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b204</name> <description>b204</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b205</name> <description>b205</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b206</name> <description>b206</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b207</name> <description>b207</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b208</name> <description>b208</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b209</name> <description>b209</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b210</name> <description>b210</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b211</name> <description>b211</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b212</name> <description>b212</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b213</name> <description>b213</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b214</name> <description>b214</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b215</name> <description>b215</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b216</name> <description>b216</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b217</name> <description>b217</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b218</name> <description>b218</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b219</name> <description>b219</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b220</name> <description>b220</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b221</name> <description>b221</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b222</name> <description>b222</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b223</name> <description>b223</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K1LR</name> <displayName>K1LR</displayName> <description>key registers</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b160</name> <description>b160</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b161</name> <description>b161</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b162</name> <description>b162</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b163</name> <description>b163</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b164</name> <description>b164</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b165</name> <description>b165</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b166</name> <description>b166</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b167</name> <description>b167</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b168</name> <description>b168</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b169</name> <description>b169</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b170</name> <description>b170</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b171</name> <description>b171</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b172</name> <description>b172</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b173</name> <description>b173</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b174</name> <description>b174</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b175</name> <description>b175</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b176</name> <description>b176</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b177</name> <description>b177</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b178</name> <description>b178</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b179</name> <description>b179</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b180</name> <description>b180</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b181</name> <description>b181</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b182</name> <description>b182</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b183</name> <description>b183</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b184</name> <description>b184</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b185</name> <description>b185</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b186</name> <description>b186</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b187</name> <description>b187</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b188</name> <description>b188</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b189</name> <description>b189</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b190</name> <description>b190</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b191</name> <description>b191</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K1RR</name> <displayName>K1RR</displayName> <description>key registers</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b128</name> <description>b128</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b129</name> <description>b129</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b130</name> <description>b130</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b131</name> <description>b131</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b132</name> <description>b132</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b133</name> <description>b133</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b134</name> <description>b134</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b135</name> <description>b135</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b136</name> <description>b136</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b137</name> <description>b137</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b138</name> <description>b138</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b139</name> <description>b139</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b140</name> <description>b140</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b141</name> <description>b141</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b142</name> <description>b142</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b143</name> <description>b143</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b144</name> <description>b144</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b145</name> <description>b145</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b146</name> <description>b146</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b147</name> <description>b147</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b148</name> <description>b148</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b149</name> <description>b149</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b150</name> <description>b150</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b151</name> <description>b151</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b152</name> <description>b152</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b153</name> <description>b153</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b154</name> <description>b154</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b155</name> <description>b155</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b156</name> <description>b156</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b157</name> <description>b157</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b158</name> <description>b158</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b159</name> <description>b159</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K2LR</name> <displayName>K2LR</displayName> <description>key registers</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b96</name> <description>b96</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b97</name> <description>b97</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b98</name> <description>b98</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b99</name> <description>b99</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b100</name> <description>b100</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b101</name> <description>b101</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b102</name> <description>b102</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b103</name> <description>b103</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b104</name> <description>b104</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b105</name> <description>b105</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b106</name> <description>b106</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b107</name> <description>b107</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b108</name> <description>b108</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b109</name> <description>b109</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b110</name> <description>b110</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b111</name> <description>b111</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b112</name> <description>b112</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b113</name> <description>b113</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b114</name> <description>b114</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b115</name> <description>b115</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b116</name> <description>b116</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b117</name> <description>b117</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b118</name> <description>b118</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b119</name> <description>b119</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b120</name> <description>b120</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b121</name> <description>b121</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b122</name> <description>b122</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b123</name> <description>b123</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b124</name> <description>b124</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b125</name> <description>b125</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b126</name> <description>b126</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b127</name> <description>b127</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K2RR</name> <displayName>K2RR</displayName> <description>key registers</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b64</name> <description>b64</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b65</name> <description>b65</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b66</name> <description>b66</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b67</name> <description>b67</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b68</name> <description>b68</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b69</name> <description>b69</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b70</name> <description>b70</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b71</name> <description>b71</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b72</name> <description>b72</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b73</name> <description>b73</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b74</name> <description>b74</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b75</name> <description>b75</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b76</name> <description>b76</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b77</name> <description>b77</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b78</name> <description>b78</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b79</name> <description>b79</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b80</name> <description>b80</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b81</name> <description>b81</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b82</name> <description>b82</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b83</name> <description>b83</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b84</name> <description>b84</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b85</name> <description>b85</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b86</name> <description>b86</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b87</name> <description>b87</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b88</name> <description>b88</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b89</name> <description>b89</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b90</name> <description>b90</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b91</name> <description>b91</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b92</name> <description>b92</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b93</name> <description>b93</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b94</name> <description>b94</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b95</name> <description>b95</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K3LR</name> <displayName>K3LR</displayName> <description>key registers</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b32</name> <description>b32</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b33</name> <description>b33</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b34</name> <description>b34</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b35</name> <description>b35</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b36</name> <description>b36</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b37</name> <description>b37</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b38</name> <description>b38</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b39</name> <description>b39</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b40</name> <description>b40</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b41</name> <description>b41</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b42</name> <description>b42</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b43</name> <description>b43</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b44</name> <description>b44</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b45</name> <description>b45</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b46</name> <description>b46</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b47</name> <description>b47</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b48</name> <description>b48</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b49</name> <description>b49</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b50</name> <description>b50</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b51</name> <description>b51</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b52</name> <description>b52</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b53</name> <description>b53</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b54</name> <description>b54</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b55</name> <description>b55</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b56</name> <description>b56</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b57</name> <description>b57</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b58</name> <description>b58</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b59</name> <description>b59</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b60</name> <description>b60</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b61</name> <description>b61</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b62</name> <description>b62</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b63</name> <description>b63</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>K3RR</name> <displayName>K3RR</displayName> <description>key registers</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>b0</name> <description>b0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b1</name> <description>b1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b2</name> <description>b2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b3</name> <description>b3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b4</name> <description>b4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b5</name> <description>b5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b6</name> <description>b6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b7</name> <description>b7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b8</name> <description>b8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b9</name> <description>b9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b10</name> <description>b10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b11</name> <description>b11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b12</name> <description>b12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b13</name> <description>b13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b14</name> <description>b14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b15</name> <description>b15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b16</name> <description>b16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b17</name> <description>b17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b18</name> <description>b18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b19</name> <description>b19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b20</name> <description>b20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b21</name> <description>b21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b22</name> <description>b22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b23</name> <description>b23</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b24</name> <description>b24</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b25</name> <description>b25</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b26</name> <description>b26</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b27</name> <description>b27</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b28</name> <description>b28</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b29</name> <description>b29</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b30</name> <description>b30</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>b31</name> <description>b31</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IV0LR</name> <displayName>IV0LR</displayName> <description>initialization vector registers</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IV31</name> <description>IV31</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV30</name> <description>IV30</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV29</name> <description>IV29</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV28</name> <description>IV28</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV27</name> <description>IV27</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV26</name> <description>IV26</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV25</name> <description>IV25</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV24</name> <description>IV24</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV23</name> <description>IV23</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV22</name> <description>IV22</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV21</name> <description>IV21</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV20</name> <description>IV20</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV19</name> <description>IV19</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV18</name> <description>IV18</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV17</name> <description>IV17</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV16</name> <description>IV16</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV15</name> <description>IV15</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV14</name> <description>IV14</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV13</name> <description>IV13</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV12</name> <description>IV12</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV11</name> <description>IV11</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV10</name> <description>IV10</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV9</name> <description>IV9</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV8</name> <description>IV8</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV7</name> <description>IV7</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV6</name> <description>IV6</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV5</name> <description>IV5</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV4</name> <description>IV4</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV3</name> <description>IV3</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV2</name> <description>IV2</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV1</name> <description>IV1</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV0</name> <description>IV0</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IV0RR</name> <displayName>IV0RR</displayName> <description>initialization vector registers</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IV63</name> <description>IV63</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV62</name> <description>IV62</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV61</name> <description>IV61</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV60</name> <description>IV60</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV59</name> <description>IV59</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV58</name> <description>IV58</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV57</name> <description>IV57</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV56</name> <description>IV56</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV55</name> <description>IV55</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV54</name> <description>IV54</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV53</name> <description>IV53</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV52</name> <description>IV52</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV51</name> <description>IV51</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV50</name> <description>IV50</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV49</name> <description>IV49</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV48</name> <description>IV48</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV47</name> <description>IV47</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV46</name> <description>IV46</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV45</name> <description>IV45</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV44</name> <description>IV44</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV43</name> <description>IV43</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV42</name> <description>IV42</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV41</name> <description>IV41</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV40</name> <description>IV40</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV39</name> <description>IV39</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV38</name> <description>IV38</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV37</name> <description>IV37</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV36</name> <description>IV36</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV35</name> <description>IV35</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV34</name> <description>IV34</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV33</name> <description>IV33</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV32</name> <description>IV32</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IV1LR</name> <displayName>IV1LR</displayName> <description>initialization vector registers</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IV95</name> <description>IV95</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV94</name> <description>IV94</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV93</name> <description>IV93</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV92</name> <description>IV92</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV91</name> <description>IV91</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV90</name> <description>IV90</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV89</name> <description>IV89</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV88</name> <description>IV88</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV87</name> <description>IV87</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV86</name> <description>IV86</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV85</name> <description>IV85</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV84</name> <description>IV84</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV83</name> <description>IV83</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV82</name> <description>IV82</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV81</name> <description>IV81</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV80</name> <description>IV80</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV79</name> <description>IV79</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV78</name> <description>IV78</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV77</name> <description>IV77</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV76</name> <description>IV76</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV75</name> <description>IV75</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV74</name> <description>IV74</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV73</name> <description>IV73</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV72</name> <description>IV72</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV71</name> <description>IV71</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV70</name> <description>IV70</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV69</name> <description>IV69</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV68</name> <description>IV68</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV67</name> <description>IV67</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV66</name> <description>IV66</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV65</name> <description>IV65</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV64</name> <description>IV64</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IV1RR</name> <displayName>IV1RR</displayName> <description>initialization vector registers</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IV127</name> <description>IV127</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV126</name> <description>IV126</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV125</name> <description>IV125</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV124</name> <description>IV124</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV123</name> <description>IV123</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV122</name> <description>IV122</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV121</name> <description>IV121</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV120</name> <description>IV120</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV119</name> <description>IV119</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV118</name> <description>IV118</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV117</name> <description>IV117</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV116</name> <description>IV116</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV115</name> <description>IV115</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV114</name> <description>IV114</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV113</name> <description>IV113</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV112</name> <description>IV112</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV111</name> <description>IV111</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV110</name> <description>IV110</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV109</name> <description>IV109</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV108</name> <description>IV108</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV107</name> <description>IV107</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV106</name> <description>IV106</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV105</name> <description>IV105</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV104</name> <description>IV104</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV103</name> <description>IV103</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV102</name> <description>IV102</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV101</name> <description>IV101</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV100</name> <description>IV100</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV99</name> <description>IV99</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV98</name> <description>IV98</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV97</name> <description>IV97</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IV96</name> <description>IV96</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM0R</name> <displayName>CSGCMCCM0R</displayName> <description>context swap register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM0R</name> <description>CSGCMCCM0R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM1R</name> <displayName>CSGCMCCM1R</displayName> <description>context swap register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM1R</name> <description>CSGCMCCM1R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM2R</name> <displayName>CSGCMCCM2R</displayName> <description>context swap register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM2R</name> <description>CSGCMCCM2R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM3R</name> <displayName>CSGCMCCM3R</displayName> <description>context swap register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM3R</name> <description>CSGCMCCM3R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM4R</name> <displayName>CSGCMCCM4R</displayName> <description>context swap register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM4R</name> <description>CSGCMCCM4R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM5R</name> <displayName>CSGCMCCM5R</displayName> <description>context swap register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM5R</name> <description>CSGCMCCM5R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM6R</name> <displayName>CSGCMCCM6R</displayName> <description>context swap register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM6R</name> <description>CSGCMCCM6R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCMCCM7R</name> <displayName>CSGCMCCM7R</displayName> <description>context swap register</description> <addressOffset>0x6C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCMCCM7R</name> <description>CSGCMCCM7R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM0R</name> <displayName>CSGCM0R</displayName> <description>context swap register</description> <addressOffset>0x70</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM0R</name> <description>CSGCM0R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM1R</name> <displayName>CSGCM1R</displayName> <description>context swap register</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM1R</name> <description>CSGCM1R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM2R</name> <displayName>CSGCM2R</displayName> <description>context swap register</description> <addressOffset>0x78</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM2R</name> <description>CSGCM2R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM3R</name> <displayName>CSGCM3R</displayName> <description>context swap register</description> <addressOffset>0x7C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM3R</name> <description>CSGCM3R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM4R</name> <displayName>CSGCM4R</displayName> <description>context swap register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM4R</name> <description>CSGCM4R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM5R</name> <displayName>CSGCM5R</displayName> <description>context swap register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM5R</name> <description>CSGCM5R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM6R</name> <displayName>CSGCM6R</displayName> <description>context swap register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM6R</name> <description>CSGCM6R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CSGCM7R</name> <displayName>CSGCM7R</displayName> <description>context swap register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSGCM7R</name> <description>CSGCM7R</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DCMI</name> <description>Digital camera interface</description> <groupName>DCMI</groupName> <baseAddress>0x50050000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>DCMI</name> <description>DCMI global interrupt</description> <value>78</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ENABLE</name> <description>DCMI enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EDM</name> <description>Extended data mode</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FCRC</name> <description>Frame capture rate control</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>VSPOL</name> <description>Vertical synchronization polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSPOL</name> <description>Horizontal synchronization polarity</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PCKPOL</name> <description>Pixel clock polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ESS</name> <description>Embedded synchronization select</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JPEG</name> <description>JPEG format</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CROP</name> <description>Crop feature</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CM</name> <description>Capture mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAPTURE</name> <description>Capture enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>FNE</name> <description>FIFO not empty</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VSYNC</name> <description>VSYNC</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSYNC</name> <description>HSYNC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RIS</name> <displayName>RIS</displayName> <description>raw interrupt status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LINE_RIS</name> <description>Line raw interrupt status</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VSYNC_RIS</name> <description>VSYNC raw interrupt status</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERR_RIS</name> <description>Synchronization error raw interrupt status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR_RIS</name> <description>Overrun raw interrupt status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRAME_RIS</name> <description>Capture complete raw interrupt status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>IER</name> <displayName>IER</displayName> <description>interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LINE_IE</name> <description>Line interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VSYNC_IE</name> <description>VSYNC interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERR_IE</name> <description>Synchronization error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR_IE</name> <description>Overrun interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRAME_IE</name> <description>Capture complete interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MIS</name> <displayName>MIS</displayName> <description>masked interrupt status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LINE_MIS</name> <description>Line masked interrupt status</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VSYNC_MIS</name> <description>VSYNC masked interrupt status</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERR_MIS</name> <description>Synchronization error masked interrupt status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR_MIS</name> <description>Overrun masked interrupt status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRAME_MIS</name> <description>Capture complete masked interrupt status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ICR</name> <displayName>ICR</displayName> <description>interrupt clear register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LINE_ISC</name> <description>line interrupt status clear</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VSYNC_ISC</name> <description>Vertical synch interrupt status clear</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERR_ISC</name> <description>Synchronization error interrupt status clear</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR_ISC</name> <description>Overrun interrupt status clear</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRAME_ISC</name> <description>Capture complete interrupt status clear</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ESCR</name> <displayName>ESCR</displayName> <description>embedded synchronization code register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>FEC</name> <description>Frame end delimiter code</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>LEC</name> <description>Line end delimiter code</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>LSC</name> <description>Line start delimiter code</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>FSC</name> <description>Frame start delimiter code</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ESUR</name> <displayName>ESUR</displayName> <description>embedded synchronization unmask register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>FEU</name> <description>Frame end delimiter unmask</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>LEU</name> <description>Line end delimiter unmask</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>LSU</name> <description>Line start delimiter unmask</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>FSU</name> <description>Frame start delimiter unmask</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>CWSTRT</name> <displayName>CWSTRT</displayName> <description>crop window start</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>VST</name> <description>Vertical start line count</description> <bitOffset>16</bitOffset> <bitWidth>13</bitWidth> </field> <field> <name>HOFFCNT</name> <description>Horizontal offset count</description> <bitOffset>0</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>CWSIZE</name> <displayName>CWSIZE</displayName> <description>crop window size</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>VLINE</name> <description>Vertical line count</description> <bitOffset>16</bitOffset> <bitWidth>14</bitWidth> </field> <field> <name>CAPCNT</name> <description>Capture count</description> <bitOffset>0</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>data register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>Byte3</name> <description>Data byte 3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>Byte2</name> <description>Data byte 2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>Byte1</name> <description>Data byte 1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>Byte0</name> <description>Data byte 0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DBG</name> <description>Debug support</description> <groupName>DBG</groupName> <baseAddress>0xE0042000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DBGMCU_IDCODE</name> <displayName>DBGMCU_IDCODE</displayName> <description>IDCODE</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x10006411</resetValue> <fields> <field> <name>DEV_ID</name> <description>DEV_ID</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>REV_ID</name> <description>REV_ID</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DBGMCU_CR</name> <displayName>DBGMCU_CR</displayName> <description>Control Register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_SLEEP</name> <description>DBG_SLEEP</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_STOP</name> <description>DBG_STOP</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_STANDBY</name> <description>DBG_STANDBY</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRACE_IOEN</name> <description>TRACE_IOEN</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRACE_MODE</name> <description>TRACE_MODE</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>DBGMCU_APB1_FZ</name> <displayName>DBGMCU_APB1_FZ</displayName> <description>Debug MCU APB1 Freeze registe</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_TIM2_STOP</name> <description>DBG_TIM2_STOP</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM3_STOP</name> <description>DBG_TIM3 _STOP</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM4_STOP</name> <description>DBG_TIM4_STOP</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM5_STOP</name> <description>DBG_TIM5_STOP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM6_STOP</name> <description>DBG_TIM6_STOP</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM7_STOP</name> <description>DBG_TIM7_STOP</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM12_STOP</name> <description>DBG_TIM12_STOP</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM13_STOP</name> <description>DBG_TIM13_STOP</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM14_STOP</name> <description>DBG_TIM14_STOP</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_WWDG_STOP</name> <description>DBG_WWDG_STOP</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_IWDEG_STOP</name> <description>DBG_IWDEG_STOP</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_J2C1_SMBUS_TIMEOUT</name> <description>DBG_J2C1_SMBUS_TIMEOUT</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_J2C2_SMBUS_TIMEOUT</name> <description>DBG_J2C2_SMBUS_TIMEOUT</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_J2C3SMBUS_TIMEOUT</name> <description>DBG_J2C3SMBUS_TIMEOUT</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_CAN1_STOP</name> <description>DBG_CAN1_STOP</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_CAN2_STOP</name> <description>DBG_CAN2_STOP</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DBGMCU_APB2_FZ</name> <displayName>DBGMCU_APB2_FZ</displayName> <description>Debug MCU APB2 Freeze registe</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DBG_TIM1_STOP</name> <description>TIM1 counter stopped when core is halted</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM8_STOP</name> <description>TIM8 counter stopped when core is halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM9_STOP</name> <description>TIM9 counter stopped when core is halted</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM10_STOP</name> <description>TIM10 counter stopped when core is halted</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBG_TIM11_STOP</name> <description>TIM11 counter stopped when core is halted</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DMA2</name> <description>DMA controller</description> <groupName>DMA</groupName> <baseAddress>0x40026400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>DMA2_Stream0</name> <description>DMA2 Stream0 global interrupt</description> <value>56</value> </interrupt> <interrupt> <name>DMA2_Stream1</name> <description>DMA2 Stream1 global interrupt</description> <value>57</value> </interrupt> <interrupt> <name>DMA2_Stream2</name> <description>DMA2 Stream2 global interrupt</description> <value>58</value> </interrupt> <interrupt> <name>DMA2_Stream3</name> <description>DMA2 Stream3 global interrupt</description> <value>59</value> </interrupt> <interrupt> <name>DMA2_Stream4</name> <description>DMA2 Stream4 global interrupt</description> <value>60</value> </interrupt> <interrupt> <name>DMA2_Stream5</name> <description>DMA2 Stream5 global interrupt</description> <value>68</value> </interrupt> <interrupt> <name>DMA2_Stream6</name> <description>DMA2 Stream6 global interrupt</description> <value>69</value> </interrupt> <interrupt> <name>DMA2_Stream7</name> <description>DMA2 Stream7 global interrupt</description> <value>70</value> </interrupt> <registers> <register> <name>LISR</name> <displayName>LISR</displayName> <description>low interrupt status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TCIF3</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF3</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF3</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF3</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF3</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF2</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF2</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF2</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF2</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF2</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF1</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF1</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF1</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF1</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF1</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF0</name> <description>Stream x transfer complete interrupt flag (x = 3..0)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF0</name> <description>Stream x half transfer interrupt flag (x=3..0)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF0</name> <description>Stream x transfer error interrupt flag (x=3..0)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF0</name> <description>Stream x direct mode error interrupt flag (x=3..0)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF0</name> <description>Stream x FIFO error interrupt flag (x=3..0)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>HISR</name> <displayName>HISR</displayName> <description>high interrupt status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TCIF7</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF7</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF7</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF7</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF7</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF6</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF6</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF6</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF6</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF6</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF5</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF5</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF5</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF5</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF5</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF4</name> <description>Stream x transfer complete interrupt flag (x=7..4)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIF4</name> <description>Stream x half transfer interrupt flag (x=7..4)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIF4</name> <description>Stream x transfer error interrupt flag (x=7..4)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIF4</name> <description>Stream x direct mode error interrupt flag (x=7..4)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEIF4</name> <description>Stream x FIFO error interrupt flag (x=7..4)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LIFCR</name> <displayName>LIFCR</displayName> <description>low interrupt flag clear register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CTCIF3</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF3</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF3</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF3</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF3</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF2</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF2</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF2</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF2</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF2</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF1</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF1</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF1</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF1</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF1</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF0</name> <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF0</name> <description>Stream x clear half transfer interrupt flag (x = 3..0)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF0</name> <description>Stream x clear transfer error interrupt flag (x = 3..0)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF0</name> <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF0</name> <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>HIFCR</name> <displayName>HIFCR</displayName> <description>high interrupt flag clear register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CTCIF7</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF7</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF7</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF7</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF7</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF6</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF6</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF6</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF6</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF6</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF5</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF5</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF5</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF5</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF5</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF4</name> <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHTIF4</name> <description>Stream x clear half transfer interrupt flag (x = 7..4)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTEIF4</name> <description>Stream x clear transfer error interrupt flag (x = 7..4)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CDMEIF4</name> <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFEIF4</name> <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S0CR</name> <displayName>S0CR</displayName> <description>stream x configuration register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S0NDTR</name> <displayName>S0NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S0PAR</name> <displayName>S0PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S0M0AR</name> <displayName>S0M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S0M1AR</name> <displayName>S0M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S0FCR</name> <displayName>S0FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S1CR</name> <displayName>S1CR</displayName> <description>stream x configuration register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S1NDTR</name> <displayName>S1NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S1PAR</name> <displayName>S1PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S1M0AR</name> <displayName>S1M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S1M1AR</name> <displayName>S1M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S1FCR</name> <displayName>S1FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S2CR</name> <displayName>S2CR</displayName> <description>stream x configuration register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S2NDTR</name> <displayName>S2NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S2PAR</name> <displayName>S2PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S2M0AR</name> <displayName>S2M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S2M1AR</name> <displayName>S2M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S2FCR</name> <displayName>S2FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S3CR</name> <displayName>S3CR</displayName> <description>stream x configuration register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S3NDTR</name> <displayName>S3NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S3PAR</name> <displayName>S3PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S3M0AR</name> <displayName>S3M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S3M1AR</name> <displayName>S3M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S3FCR</name> <displayName>S3FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x6C</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S4CR</name> <displayName>S4CR</displayName> <description>stream x configuration register</description> <addressOffset>0x70</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S4NDTR</name> <displayName>S4NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S4PAR</name> <displayName>S4PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x78</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S4M0AR</name> <displayName>S4M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x7C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S4M1AR</name> <displayName>S4M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S4FCR</name> <displayName>S4FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S5CR</name> <displayName>S5CR</displayName> <description>stream x configuration register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S5NDTR</name> <displayName>S5NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S5PAR</name> <displayName>S5PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0x90</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S5M0AR</name> <displayName>S5M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S5M1AR</name> <displayName>S5M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0x98</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S5FCR</name> <displayName>S5FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0x9C</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S6CR</name> <displayName>S6CR</displayName> <description>stream x configuration register</description> <addressOffset>0xA0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S6NDTR</name> <displayName>S6NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0xA4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S6PAR</name> <displayName>S6PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0xA8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S6M0AR</name> <displayName>S6M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0xAC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S6M1AR</name> <displayName>S6M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0xB0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S6FCR</name> <displayName>S6FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0xB4</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>S7CR</name> <displayName>S7CR</displayName> <description>stream x configuration register</description> <addressOffset>0xB8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CHSEL</name> <description>Channel selection</description> <bitOffset>25</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MBURST</name> <description>Memory burst transfer configuration</description> <bitOffset>23</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PBURST</name> <description>Peripheral burst transfer configuration</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ACK</name> <description>ACK</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CT</name> <description>Current target (only in double buffer mode)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBM</name> <description>Double buffer mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PL</name> <description>Priority level</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PINCOS</name> <description>Peripheral increment offset size</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSIZE</name> <description>Memory data size</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PSIZE</name> <description>Peripheral data size</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MINC</name> <description>Memory increment mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PINC</name> <description>Peripheral increment mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CIRC</name> <description>Circular mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIR</name> <description>Data transfer direction</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PFCTRL</name> <description>Peripheral flow controller</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HTIE</name> <description>Half transfer interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMEIE</name> <description>Direct mode error interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN</name> <description>Stream enable / flag stream ready when read low</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>S7NDTR</name> <displayName>S7NDTR</displayName> <description>stream x number of data register</description> <addressOffset>0xBC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NDT</name> <description>Number of data items to transfer</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>S7PAR</name> <displayName>S7PAR</displayName> <description>stream x peripheral address register</description> <addressOffset>0xC0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PA</name> <description>Peripheral address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S7M0AR</name> <displayName>S7M0AR</displayName> <description>stream x memory 0 address register</description> <addressOffset>0xC4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M0A</name> <description>Memory 0 address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S7M1AR</name> <displayName>S7M1AR</displayName> <description>stream x memory 1 address register</description> <addressOffset>0xC8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>M1A</name> <description>Memory 1 address (used in case of Double buffer mode)</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>S7FCR</name> <displayName>S7FCR</displayName> <description>stream x FIFO control register</description> <addressOffset>0xCC</addressOffset> <size>0x20</size> <resetValue>0x00000021</resetValue> <fields> <field> <name>FEIE</name> <description>FIFO error interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FS</name> <description>FIFO status</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DMDIS</name> <description>Direct mode disable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FTH</name> <description>FIFO threshold selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="DMA2"> <name>DMA1</name> <baseAddress>0x40026000</baseAddress> <interrupt> <name>DMA1_Stream0</name> <description>DMA1 Stream0 global interrupt</description> <value>11</value> </interrupt> <interrupt> <name>DMA1_Stream1</name> <description>DMA1 Stream1 global interrupt</description> <value>12</value> </interrupt> <interrupt> <name>DMA1_Stream2</name> <description>DMA1 Stream2 global interrupt</description> <value>13</value> </interrupt> <interrupt> <name>DMA1_Stream3</name> <description>DMA1 Stream3 global interrupt</description> <value>14</value> </interrupt> <interrupt> <name>DMA1_Stream4</name> <description>DMA1 Stream4 global interrupt</description> <value>15</value> </interrupt> <interrupt> <name>DMA1_Stream5</name> <description>DMA1 Stream5 global interrupt</description> <value>16</value> </interrupt> <interrupt> <name>DMA1_Stream6</name> <description>DMA1 Stream6 global interrupt</description> <value>17</value> </interrupt> <interrupt> <name>DMA1_Stream7</name> <description>DMA1 Stream7 global interrupt</description> <value>47</value> </interrupt> </peripheral> <peripheral> <name>RCC</name> <description>Reset and clock control</description> <groupName>RCC</groupName> <baseAddress>0x40023800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>RCC</name> <description>RCC global interrupt</description> <value>5</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>clock control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000083</resetValue> <fields> <field> <name>PLLI2SRDY</name> <description>PLLI2S clock ready flag</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PLLI2SON</name> <description>PLLI2S enable</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PLLRDY</name> <description>Main PLL (PLL) clock ready flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PLLON</name> <description>Main PLL (PLL) enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CSSON</name> <description>Clock security system enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSEBYP</name> <description>HSE clock bypass</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSERDY</name> <description>HSE clock ready flag</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSEON</name> <description>HSE clock enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSICAL</name> <description>Internal high-speed clock calibration</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> <field> <name>HSITRIM</name> <description>Internal high-speed clock trimming</description> <bitOffset>3</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> <name>HSIRDY</name> <description>Internal high-speed clock ready flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSION</name> <description>Internal high-speed clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>PLLCFGR</name> <displayName>PLLCFGR</displayName> <description>PLL configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x24003010</resetValue> <fields> <field> <name>PLLQ3</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ2</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ1</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLQ0</name> <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLSRC</name> <description>Main PLL(PLL) and audio PLL (PLLI2S) entry clock source</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLP1</name> <description>Main PLL (PLL) division factor for main system clock</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLP0</name> <description>Main PLL (PLL) division factor for main system clock</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN8</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN7</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN6</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN5</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN4</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN3</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN2</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN1</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLN0</name> <description>Main PLL (PLL) multiplication factor for VCO</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM5</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM4</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM3</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM2</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM1</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLLM0</name> <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFGR</name> <displayName>CFGR</displayName> <description>clock configuration register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>MCO2</name> <description>Microcontroller clock output 2</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>MCO2PRE</name> <description>MCO2 prescaler</description> <bitOffset>27</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>MCO1PRE</name> <description>MCO1 prescaler</description> <bitOffset>24</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>I2SSRC</name> <description>I2S clock selection</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MCO1</name> <description>Microcontroller clock output 1</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>RTCPRE</name> <description>HSE division factor for RTC clock</description> <bitOffset>16</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> <name>PPRE2</name> <description>APB high-speed prescaler (APB2)</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>PPRE1</name> <description>APB Low speed prescaler (APB1)</description> <bitOffset>10</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>HPRE</name> <description>AHB prescaler</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>SWS1</name> <description>System clock switch status</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SWS0</name> <description>System clock switch status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SW1</name> <description>System clock switch</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SW0</name> <description>System clock switch</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>CIR</name> <displayName>CIR</displayName> <description>clock interrupt register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>CSSC</name> <description>Clock security system interrupt clear</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>PLLI2SRDYC</name> <description>PLLI2S ready interrupt clear</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>PLLRDYC</name> <description>Main PLL(PLL) ready interrupt clear</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>HSERDYC</name> <description>HSE ready interrupt clear</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>HSIRDYC</name> <description>HSI ready interrupt clear</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>LSERDYC</name> <description>LSE ready interrupt clear</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>LSIRDYC</name> <description>LSI ready interrupt clear</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>PLLI2SRDYIE</name> <description>PLLI2S ready interrupt enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PLLRDYIE</name> <description>Main PLL (PLL) ready interrupt enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSERDYIE</name> <description>HSE ready interrupt enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSIRDYIE</name> <description>HSI ready interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSERDYIE</name> <description>LSE ready interrupt enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSIRDYIE</name> <description>LSI ready interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CSSF</name> <description>Clock security system interrupt flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PLLI2SRDYF</name> <description>PLLI2S ready interrupt flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PLLRDYF</name> <description>Main PLL (PLL) ready interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSERDYF</name> <description>HSE ready interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HSIRDYF</name> <description>HSI ready interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSERDYF</name> <description>LSE ready interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSIRDYF</name> <description>LSI ready interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>AHB1RSTR</name> <displayName>AHB1RSTR</displayName> <description>AHB1 peripheral reset register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OTGHSRST</name> <description>USB OTG HS module reset</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACRST</name> <description>Ethernet MAC reset</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA2RST</name> <description>DMA2 reset</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1RST</name> <description>DMA2 reset</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCRST</name> <description>CRC reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOIRST</name> <description>IO port I reset</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOHRST</name> <description>IO port H reset</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOGRST</name> <description>IO port G reset</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOFRST</name> <description>IO port F reset</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOERST</name> <description>IO port E reset</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIODRST</name> <description>IO port D reset</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOCRST</name> <description>IO port C reset</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOBRST</name> <description>IO port B reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOARST</name> <description>IO port A reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB2RSTR</name> <displayName>AHB2RSTR</displayName> <description>AHB2 peripheral reset register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OTGFSRST</name> <description>USB OTG FS module reset</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGRST</name> <description>Random number generator module reset</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HSAHRST</name> <description>Hash module reset</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRYPRST</name> <description>Cryptographic module reset</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCMIRST</name> <description>Camera interface reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB3RSTR</name> <displayName>AHB3RSTR</displayName> <description>AHB3 peripheral reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FMCRST</name> <description>Flexible static memory controller module reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB1RSTR</name> <displayName>APB1RSTR</displayName> <description>APB1 peripheral reset register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM2RST</name> <description>TIM2 reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM3RST</name> <description>TIM3 reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM4RST</name> <description>TIM4 reset</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM5RST</name> <description>TIM5 reset</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM6RST</name> <description>TIM6 reset</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM7RST</name> <description>TIM7 reset</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM12RST</name> <description>TIM12 reset</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM13RST</name> <description>TIM13 reset</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM14RST</name> <description>TIM14 reset</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGRST</name> <description>Window watchdog reset</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2RST</name> <description>SPI 2 reset</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI3RST</name> <description>SPI 3 reset</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART2RST</name> <description>USART 2 reset</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART3RST</name> <description>USART 3 reset</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART4RST</name> <description>USART 4 reset</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART5RST</name> <description>USART 5 reset</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1RST</name> <description>I2C 1 reset</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2RST</name> <description>I2C 2 reset</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C3RST</name> <description>I2C3 reset</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAN1RST</name> <description>CAN1 reset</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAN2RST</name> <description>CAN2 reset</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRRST</name> <description>Power interface reset</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DACRST</name> <description>DAC reset</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART7RST</name> <description>UART7 reset</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART8RST</name> <description>UART8 reset</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB2RSTR</name> <displayName>APB2RSTR</displayName> <description>APB2 peripheral reset register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM1RST</name> <description>TIM1 reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM8RST</name> <description>TIM8 reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1RST</name> <description>USART1 reset</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART6RST</name> <description>USART6 reset</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCRST</name> <description>ADC interface reset (common to all ADCs)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIORST</name> <description>SDIO reset</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1RST</name> <description>SPI 1 reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI4RST</name> <description>SPI4 reset</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSCFGRST</name> <description>System configuration controller reset</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM9RST</name> <description>TIM9 reset</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM10RST</name> <description>TIM10 reset</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM11RST</name> <description>TIM11 reset</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI5RST</name> <description>SPI5 reset</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI6RST</name> <description>SPI6 reset</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB1ENR</name> <displayName>AHB1ENR</displayName> <description>AHB1 peripheral clock register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00100000</resetValue> <fields> <field> <name>OTGHSULPIEN</name> <description>USB OTG HSULPI clock enable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTGHSEN</name> <description>USB OTG HS clock enable</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACPTPEN</name> <description>Ethernet PTP clock enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACRXEN</name> <description>Ethernet Reception clock enable</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACTXEN</name> <description>Ethernet Transmission clock enable</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACEN</name> <description>Ethernet MAC clock enable</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA2EN</name> <description>DMA2 clock enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1EN</name> <description>DMA1 clock enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKPSRAMEN</name> <description>Backup SRAM interface clock enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCEN</name> <description>CRC clock enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOIEN</name> <description>IO port I clock enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOHEN</name> <description>IO port H clock enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOGEN</name> <description>IO port G clock enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOFEN</name> <description>IO port F clock enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOEEN</name> <description>IO port E clock enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIODEN</name> <description>IO port D clock enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOCEN</name> <description>IO port C clock enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOBEN</name> <description>IO port B clock enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOAEN</name> <description>IO port A clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB2ENR</name> <displayName>AHB2ENR</displayName> <description>AHB2 peripheral clock enable register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OTGFSEN</name> <description>USB OTG FS clock enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGEN</name> <description>Random number generator clock enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HASHEN</name> <description>Hash modules clock enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRYPEN</name> <description>Cryptographic modules clock enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCMIEN</name> <description>Camera interface enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB3ENR</name> <displayName>AHB3ENR</displayName> <description>AHB3 peripheral clock enable register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FMCEN</name> <description>Flexible static memory controller module clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB1ENR</name> <displayName>APB1ENR</displayName> <description>APB1 peripheral clock enable register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM2EN</name> <description>TIM2 clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM3EN</name> <description>TIM3 clock enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM4EN</name> <description>TIM4 clock enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM5EN</name> <description>TIM5 clock enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM6EN</name> <description>TIM6 clock enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM7EN</name> <description>TIM7 clock enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM12EN</name> <description>TIM12 clock enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM13EN</name> <description>TIM13 clock enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM14EN</name> <description>TIM14 clock enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGEN</name> <description>Window watchdog clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2EN</name> <description>SPI2 clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI3EN</name> <description>SPI3 clock enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART2EN</name> <description>USART 2 clock enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART3EN</name> <description>USART3 clock enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART4EN</name> <description>UART4 clock enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART5EN</name> <description>UART5 clock enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1EN</name> <description>I2C1 clock enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2EN</name> <description>I2C2 clock enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C3EN</name> <description>I2C3 clock enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAN1EN</name> <description>CAN 1 clock enable</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAN2EN</name> <description>CAN 2 clock enable</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWREN</name> <description>Power interface clock enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DACEN</name> <description>DAC interface clock enable</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART7ENR</name> <description>UART7 clock enable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART8ENR</name> <description>UART8 clock enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB2ENR</name> <displayName>APB2ENR</displayName> <description>APB2 peripheral clock enable register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIM1EN</name> <description>TIM1 clock enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM8EN</name> <description>TIM8 clock enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1EN</name> <description>USART1 clock enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART6EN</name> <description>USART6 clock enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC1EN</name> <description>ADC1 clock enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC2EN</name> <description>ADC2 clock enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC3EN</name> <description>ADC3 clock enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIOEN</name> <description>SDIO clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1EN</name> <description>SPI1 clock enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI4ENR</name> <description>SPI4 clock enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSCFGEN</name> <description>System configuration controller clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM9EN</name> <description>TIM9 clock enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM10EN</name> <description>TIM10 clock enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM11EN</name> <description>TIM11 clock enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI5ENR</name> <description>SPI5 clock enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI6ENR</name> <description>SPI6 clock enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB1LPENR</name> <displayName>AHB1LPENR</displayName> <description>AHB1 peripheral clock enable in low power mode register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7E6791FF</resetValue> <fields> <field> <name>GPIOALPEN</name> <description>IO port A clock enable during sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOBLPEN</name> <description>IO port B clock enable during Sleep mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOCLPEN</name> <description>IO port C clock enable during Sleep mode</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIODLPEN</name> <description>IO port D clock enable during Sleep mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOELPEN</name> <description>IO port E clock enable during Sleep mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOFLPEN</name> <description>IO port F clock enable during Sleep mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOGLPEN</name> <description>IO port G clock enable during Sleep mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOHLPEN</name> <description>IO port H clock enable during Sleep mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GPIOILPEN</name> <description>IO port I clock enable during Sleep mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCLPEN</name> <description>CRC clock enable during Sleep mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FLITFLPEN</name> <description>Flash interface clock enable during Sleep mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRAM1LPEN</name> <description>SRAM 1interface clock enable during Sleep mode</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRAM2LPEN</name> <description>SRAM 2 interface clock enable during Sleep mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKPSRAMLPEN</name> <description>Backup SRAM interface clock enable during Sleep mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRAM3LPEN</name> <description>SRAM 3 interface clock enable during Sleep mode</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA1LPEN</name> <description>DMA1 clock enable during Sleep mode</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA2LPEN</name> <description>DMA2 clock enable during Sleep mode</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACLPEN</name> <description>Ethernet MAC clock enable during Sleep mode</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACTXLPEN</name> <description>Ethernet transmission clock enable during Sleep mode</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACRXLPEN</name> <description>Ethernet reception clock enable during Sleep mode</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETHMACPTPLPEN</name> <description>Ethernet PTP clock enable during Sleep mode</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTGHSLPEN</name> <description>USB OTG HS clock enable during Sleep mode</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTGHSULPILPEN</name> <description>USB OTG HS ULPI clock enable during Sleep mode</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB2LPENR</name> <displayName>AHB2LPENR</displayName> <description>AHB2 peripheral clock enable in low power mode register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000000F1</resetValue> <fields> <field> <name>OTGFSLPEN</name> <description>USB OTG FS clock enable during Sleep mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RNGLPEN</name> <description>Random number generator clock enable during Sleep mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HASHLPEN</name> <description>Hash modules clock enable during Sleep mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRYPLPEN</name> <description>Cryptography modules clock enable during Sleep mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCMILPEN</name> <description>Camera interface enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AHB3LPENR</name> <displayName>AHB3LPENR</displayName> <description>AHB3 peripheral clock enable in low power mode register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000001</resetValue> <fields> <field> <name>FMCLPEN</name> <description>Flexible static memory controller module clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB1LPENR</name> <displayName>APB1LPENR</displayName> <description>APB1 peripheral clock enable in low power mode register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x36FEC9FF</resetValue> <fields> <field> <name>TIM2LPEN</name> <description>TIM2 clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM3LPEN</name> <description>TIM3 clock enable during Sleep mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM4LPEN</name> <description>TIM4 clock enable during Sleep mode</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM5LPEN</name> <description>TIM5 clock enable during Sleep mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM6LPEN</name> <description>TIM6 clock enable during Sleep mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM7LPEN</name> <description>TIM7 clock enable during Sleep mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM12LPEN</name> <description>TIM12 clock enable during Sleep mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM13LPEN</name> <description>TIM13 clock enable during Sleep mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM14LPEN</name> <description>TIM14 clock enable during Sleep mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WWDGLPEN</name> <description>Window watchdog clock enable during Sleep mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI2LPEN</name> <description>SPI2 clock enable during Sleep mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI3LPEN</name> <description>SPI3 clock enable during Sleep mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART2LPEN</name> <description>USART2 clock enable during Sleep mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART3LPEN</name> <description>USART3 clock enable during Sleep mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART4LPEN</name> <description>UART4 clock enable during Sleep mode</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART5LPEN</name> <description>UART5 clock enable during Sleep mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C1LPEN</name> <description>I2C1 clock enable during Sleep mode</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C2LPEN</name> <description>I2C2 clock enable during Sleep mode</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2C3LPEN</name> <description>I2C3 clock enable during Sleep mode</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAN1LPEN</name> <description>CAN 1 clock enable during Sleep mode</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAN2LPEN</name> <description>CAN 2 clock enable during Sleep mode</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRLPEN</name> <description>Power interface clock enable during Sleep mode</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DACLPEN</name> <description>DAC interface clock enable during Sleep mode</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART7LPEN</name> <description>UART7 clock enable during Sleep mode</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UART8LPEN</name> <description>UART8 clock enable during Sleep mode</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>APB2LPENR</name> <displayName>APB2LPENR</displayName> <description>APB2 peripheral clock enabled in low power mode register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00075F33</resetValue> <fields> <field> <name>TIM1LPEN</name> <description>TIM1 clock enable during Sleep mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM8LPEN</name> <description>TIM8 clock enable during Sleep mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART1LPEN</name> <description>USART1 clock enable during Sleep mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USART6LPEN</name> <description>USART6 clock enable during Sleep mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC1LPEN</name> <description>ADC1 clock enable during Sleep mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC2LPEN</name> <description>ADC2 clock enable during Sleep mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC3LPEN</name> <description>ADC 3 clock enable during Sleep mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIOLPEN</name> <description>SDIO clock enable during Sleep mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI1LPEN</name> <description>SPI 1 clock enable during Sleep mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI4LPEN</name> <description>SPI 4 clock enable during Sleep mode</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSCFGLPEN</name> <description>System configuration controller clock enable during Sleep mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM9LPEN</name> <description>TIM9 clock enable during sleep mode</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM10LPEN</name> <description>TIM10 clock enable during Sleep mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIM11LPEN</name> <description>TIM11 clock enable during Sleep mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI5LPEN</name> <description>SPI 5 clock enable during Sleep mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPI6LPEN</name> <description>SPI 6 clock enable during Sleep mode</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BDCR</name> <displayName>BDCR</displayName> <description>Backup domain control register</description> <addressOffset>0x70</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>BDRST</name> <description>Backup domain software reset</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RTCEN</name> <description>RTC clock enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RTCSEL1</name> <description>RTC clock source selection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RTCSEL0</name> <description>RTC clock source selection</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSEBYP</name> <description>External low-speed oscillator bypass</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSERDY</name> <description>External low-speed oscillator ready</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSEON</name> <description>External low-speed oscillator enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>CSR</name> <displayName>CSR</displayName> <description>clock control & status register</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <resetValue>0x0E000000</resetValue> <fields> <field> <name>LPWRRSTF</name> <description>Low-power reset flag</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WWDGRSTF</name> <description>Window watchdog reset flag</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WDGRSTF</name> <description>Independent watchdog reset flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SFTRSTF</name> <description>Software reset flag</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PORRSTF</name> <description>POR/PDR reset flag</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PADRSTF</name> <description>PIN reset flag</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BORRSTF</name> <description>BOR reset flag</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RMVF</name> <description>Remove reset flag</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LSIRDY</name> <description>Internal low-speed oscillator ready</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LSION</name> <description>Internal low-speed oscillator enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SSCGR</name> <displayName>SSCGR</displayName> <description>spread spectrum clock generation register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SSCGEN</name> <description>Spread spectrum modulation enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPREADSEL</name> <description>Spread Select</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INCSTEP</name> <description>Incrementation step</description> <bitOffset>13</bitOffset> <bitWidth>15</bitWidth> </field> <field> <name>MODPER</name> <description>Modulation period</description> <bitOffset>0</bitOffset> <bitWidth>13</bitWidth> </field> </fields> </register> <register> <name>PLLI2SCFGR</name> <displayName>PLLI2SCFGR</displayName> <description>PLLI2S configuration register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x20003000</resetValue> <fields> <field> <name>PLLI2SRx</name> <description>PLLI2S division factor for I2S clocks</description> <bitOffset>28</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PLLI2SNx</name> <description>PLLI2S multiplication factor for VCO</description> <bitOffset>6</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>GPIOI</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x40022000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRH15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOH</name> <baseAddress>0x40021C00</baseAddress> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOG</name> <baseAddress>0x40021800</baseAddress> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOF</name> <baseAddress>0x40021400</baseAddress> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOE</name> <baseAddress>0x40021000</baseAddress> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOD</name> <baseAddress>0X40020C00</baseAddress> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOC</name> <baseAddress>0x40020800</baseAddress> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOJ</name> <baseAddress>0x40022400</baseAddress> </peripheral> <peripheral derivedFrom="GPIOI"> <name>GPIOK</name> <baseAddress>0x40022800</baseAddress> </peripheral> <peripheral> <name>GPIOB</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x40020400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000280</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000000C0</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000100</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRH15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>GPIOA</name> <description>General-purpose I/Os</description> <groupName>GPIO</groupName> <baseAddress>0x40020000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MODER</name> <displayName>MODER</displayName> <description>GPIO port mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xA8000000</resetValue> <fields> <field> <name>MODER15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODER0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTYPER</name> <displayName>OTYPER</displayName> <description>GPIO port output type register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OT15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OT0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OSPEEDR</name> <displayName>OSPEEDR</displayName> <description>GPIO port output speed register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OSPEEDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OSPEEDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PUPDR</name> <displayName>PUPDR</displayName> <description>GPIO port pull-up/pull-down register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x64000000</resetValue> <fields> <field> <name>PUPDR15</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR14</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR13</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR12</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR11</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR10</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR9</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR8</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR7</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR6</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR5</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR4</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR3</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR2</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR1</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PUPDR0</name> <description>Port x configuration bits (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>GPIO port input data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR15</name> <description>Port input data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR14</name> <description>Port input data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR13</name> <description>Port input data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR12</name> <description>Port input data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR11</name> <description>Port input data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR10</name> <description>Port input data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR9</name> <description>Port input data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR8</name> <description>Port input data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR7</name> <description>Port input data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR6</name> <description>Port input data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR5</name> <description>Port input data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR4</name> <description>Port input data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR3</name> <description>Port input data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR2</name> <description>Port input data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR1</name> <description>Port input data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDR0</name> <description>Port input data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ODR</name> <displayName>ODR</displayName> <description>GPIO port output data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ODR15</name> <description>Port output data (y = 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR14</name> <description>Port output data (y = 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR13</name> <description>Port output data (y = 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR12</name> <description>Port output data (y = 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR11</name> <description>Port output data (y = 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR10</name> <description>Port output data (y = 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR9</name> <description>Port output data (y = 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR8</name> <description>Port output data (y = 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR7</name> <description>Port output data (y = 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR6</name> <description>Port output data (y = 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR5</name> <description>Port output data (y = 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR4</name> <description>Port output data (y = 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR3</name> <description>Port output data (y = 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR2</name> <description>Port output data (y = 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR1</name> <description>Port output data (y = 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODR0</name> <description>Port output data (y = 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSRR</name> <displayName>BSRR</displayName> <description>GPIO port bit set/reset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BR15</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR14</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR13</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR12</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR11</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR10</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR9</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR8</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR7</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR6</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR5</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR4</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR3</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR2</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR1</name> <description>Port x reset bit y (y = 0..15)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS15</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS14</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS13</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS12</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS11</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS10</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS9</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS8</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS7</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS6</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS5</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS4</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS3</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS2</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS1</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BS0</name> <description>Port x set bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LCKR</name> <displayName>LCKR</displayName> <description>GPIO port configuration lock register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LCKK</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK15</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK14</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK13</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK12</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK11</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK10</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK9</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK8</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK7</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK6</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK5</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK4</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK3</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK2</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK1</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LCK0</name> <description>Port x lock bit y (y= 0..15)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>AFRL</name> <displayName>AFRL</displayName> <description>GPIO alternate function low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRL7</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL6</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL5</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL4</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL3</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL2</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL1</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRL0</name> <description>Alternate function selection for port x bit y (y = 0..7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>AFRH</name> <displayName>AFRH</displayName> <description>GPIO alternate function high register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AFRH15</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>28</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH14</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH13</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH12</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH11</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH10</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH9</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>AFRH8</name> <description>Alternate function selection for port x bit y (y = 8..15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SYSCFG</name> <description>System configuration controller</description> <groupName>SYSCFG</groupName> <baseAddress>0x40013800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MEMRM</name> <displayName>MEMRM</displayName> <description>memory remap register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MEM_MODE</name> <description>MEM_MODE</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>PMC</name> <displayName>PMC</displayName> <description>peripheral mode configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MII_RMII_SEL</name> <description>Ethernet PHY interface selection</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC1DC2</name> <description>ADC1DC2</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC2DC2</name> <description>ADC2DC2</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADC3DC2</name> <description>ADC3DC2</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EXTICR1</name> <displayName>EXTICR1</displayName> <description>external interrupt configuration register 1</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI3</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI2</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI1</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI0</name> <description>EXTI x configuration (x = 0 to 3)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>EXTICR2</name> <displayName>EXTICR2</displayName> <description>external interrupt configuration register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI7</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI6</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI5</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI4</name> <description>EXTI x configuration (x = 4 to 7)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>EXTICR3</name> <displayName>EXTICR3</displayName> <description>external interrupt configuration register 3</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI11</name> <description>EXTI x configuration (x = 8 to 11)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI10</name> <description>EXTI10</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI9</name> <description>EXTI x configuration (x = 8 to 11)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI8</name> <description>EXTI x configuration (x = 8 to 11)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>EXTICR4</name> <displayName>EXTICR4</displayName> <description>external interrupt configuration register 4</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>EXTI15</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI14</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI13</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EXTI12</name> <description>EXTI x configuration (x = 12 to 15)</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CMPCR</name> <displayName>CMPCR</displayName> <description>Compensation cell control register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>READY</name> <description>READY</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMP_PD</name> <description>Compensation cell power-down</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SPI1</name> <description>Serial peripheral interface</description> <groupName>SPI</groupName> <baseAddress>0x40013000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>SPI1</name> <description>SPI1 global interrupt</description> <value>35</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BIDIMODE</name> <description>Bidirectional data mode enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIDIOE</name> <description>Output enable in bidirectional mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCEN</name> <description>Hardware CRC calculation enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CRCNEXT</name> <description>CRC transfer next</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DFF</name> <description>Data frame format</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXONLY</name> <description>Receive only</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSM</name> <description>Software slave management</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSI</name> <description>Internal slave select</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSBFIRST</name> <description>Frame format</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPE</name> <description>SPI enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BR</name> <description>Baud rate control</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MSTR</name> <description>Master selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPOL</name> <description>Clock polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPHA</name> <description>Clock phase</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TXEIE</name> <description>Tx buffer empty interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNEIE</name> <description>RX buffer not empty interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRF</name> <description>Frame format</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SSOE</name> <description>SS output enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXDMAEN</name> <description>Tx buffer DMA enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXDMAEN</name> <description>Rx buffer DMA enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x0002</resetValue> <fields> <field> <name>TIFRFE</name> <description>TI frame format error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BSY</name> <description>Busy flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>OVR</name> <description>Overrun flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MODF</name> <description>Mode fault</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CRCERR</name> <description>CRC error flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>UDR</name> <description>Underrun flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CHSIDE</name> <description>Channel side</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXE</name> <description>Transmit buffer empty</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RXNE</name> <description>Receive buffer not empty</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>data register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DR</name> <description>Data register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CRCPR</name> <displayName>CRCPR</displayName> <description>CRC polynomial register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0007</resetValue> <fields> <field> <name>CRCPOLY</name> <description>CRC polynomial register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>RXCRCR</name> <displayName>RXCRCR</displayName> <description>RX CRC register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>RxCRC</name> <description>Rx CRC register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>TXCRCR</name> <displayName>TXCRCR</displayName> <description>TX CRC register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TxCRC</name> <description>Tx CRC register</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>I2SCFGR</name> <displayName>I2SCFGR</displayName> <description>I2S configuration register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>I2SMOD</name> <description>I2S mode selection</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SE</name> <description>I2S Enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SCFG</name> <description>I2S configuration mode</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PCMSYNC</name> <description>PCM frame synchronization</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SSTD</name> <description>I2S standard selection</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKPOL</name> <description>Steady state clock polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DATLEN</name> <description>Data length to be transferred</description> <bitOffset>1</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CHLEN</name> <description>Channel length (number of bits per audio channel)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>I2SPR</name> <displayName>I2SPR</displayName> <description>I2S prescaler register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>00000010</resetValue> <fields> <field> <name>MCKOE</name> <description>Master clock output enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODD</name> <description>Odd factor for the prescaler</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2SDIV</name> <description>I2S Linear prescaler</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI2</name> <baseAddress>0x40003800</baseAddress> <interrupt> <name>SPI2</name> <description>SPI2 global interrupt</description> <value>36</value> </interrupt> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI3</name> <baseAddress>0x40003C00</baseAddress> <interrupt> <name>SPI3</name> <description>SPI3 global interrupt</description> <value>51</value> </interrupt> </peripheral> <peripheral derivedFrom="SPI1"> <name>I2S2ext</name> <baseAddress>0x40003400</baseAddress> </peripheral> <peripheral derivedFrom="SPI1"> <name>I2S3ext</name> <baseAddress>0x40004000</baseAddress> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI4</name> <baseAddress>0x40013400</baseAddress> <interrupt> <name>SPI4</name> <description>SPI 4 global interrupt</description> <value>84</value> </interrupt> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI5</name> <baseAddress>0x40015000</baseAddress> <interrupt> <name>SPI5</name> <description>SPI 5 global interrupt</description> <value>85</value> </interrupt> </peripheral> <peripheral derivedFrom="SPI1"> <name>SPI6</name> <baseAddress>0x40015400</baseAddress> <interrupt> <name>SPI6</name> <description>SPI 6 global interrupt</description> <value>86</value> </interrupt> </peripheral> <peripheral> <name>SDIO</name> <description>Secure digital input/output interface</description> <groupName>SDIO</groupName> <baseAddress>0x40012C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>SDIO</name> <description>SDIO global interrupt</description> <value>49</value> </interrupt> <registers> <register> <name>POWER</name> <displayName>POWER</displayName> <description>power control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PWRCTRL</name> <description>PWRCTRL</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CLKCR</name> <displayName>CLKCR</displayName> <description>SDI clock control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HWFC_EN</name> <description>HW Flow Control enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NEGEDGE</name> <description>SDIO_CK dephasing selection bit</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WIDBUS</name> <description>Wide bus mode enable bit</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>BYPASS</name> <description>Clock divider bypass enable bit</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWRSAV</name> <description>Power saving configuration bit</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CLKEN</name> <description>Clock enable bit</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CLKDIV</name> <description>Clock divide factor</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ARG</name> <displayName>ARG</displayName> <description>argument register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CMDARG</name> <description>Command argument</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>CMD</name> <displayName>CMD</displayName> <description>command register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CE_ATACMD</name> <description>CE-ATA command</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nIEN</name> <description>not Interrupt Enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENCMDcompl</name> <description>Enable CMD completion</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIOSuspend</name> <description>SD I/O suspend command</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPSMEN</name> <description>Command path state machine (CPSM) Enable bit</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITPEND</name> <description>CPSM Waits for ends of data transfer (CmdPend internal signal).</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITINT</name> <description>CPSM waits for interrupt request</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITRESP</name> <description>Wait for response bits</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CMDINDEX</name> <description>Command index</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> <register> <name>RESPCMD</name> <displayName>RESPCMD</displayName> <description>command response register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RESPCMD</name> <description>Response command index</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> <register> <name>RESP1</name> <displayName>RESP1</displayName> <description>response 1..4 register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CARDSTATUS1</name> <description>see Table 132.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>RESP2</name> <displayName>RESP2</displayName> <description>response 1..4 register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CARDSTATUS2</name> <description>see Table 132.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>RESP3</name> <displayName>RESP3</displayName> <description>response 1..4 register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CARDSTATUS3</name> <description>see Table 132.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>RESP4</name> <displayName>RESP4</displayName> <description>response 1..4 register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CARDSTATUS4</name> <description>see Table 132.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DTIMER</name> <displayName>DTIMER</displayName> <description>data timer register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATATIME</name> <description>Data timeout period</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DLEN</name> <displayName>DLEN</displayName> <description>data length register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATALENGTH</name> <description>Data length value</description> <bitOffset>0</bitOffset> <bitWidth>25</bitWidth> </field> </fields> </register> <register> <name>DCTRL</name> <displayName>DCTRL</displayName> <description>data control register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SDIOEN</name> <description>SD I/O enable functions</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWMOD</name> <description>Read wait mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWSTOP</name> <description>Read wait stop</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWSTART</name> <description>Read wait start</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBLOCKSIZE</name> <description>Data block size</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DMAEN</name> <description>DMA enable bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTMODE</name> <description>Data transfer mode selection 1: Stream or SDIO multibyte data transfer.</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTDIR</name> <description>Data transfer direction selection</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTEN</name> <description>DTEN</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DCOUNT</name> <displayName>DCOUNT</displayName> <description>data counter register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATACOUNT</name> <description>Data count value</description> <bitOffset>0</bitOffset> <bitWidth>25</bitWidth> </field> </fields> </register> <register> <name>STA</name> <displayName>STA</displayName> <description>status register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CEATAEND</name> <description>CE-ATA command completion signal received for CMD61</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIOIT</name> <description>SDIO interrupt received</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXDAVL</name> <description>Data available in receive FIFO</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXDAVL</name> <description>Data available in transmit FIFO</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFIFOE</name> <description>Receive FIFO empty</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFIFOE</name> <description>Transmit FIFO empty</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFIFOF</name> <description>Receive FIFO full</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFIFOF</name> <description>Transmit FIFO full</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFIFOHF</name> <description>Receive FIFO half full: there are at least 8 words in the FIFO</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFIFOHE</name> <description>Transmit FIFO half empty: at least 8 words can be written into the FIFO</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXACT</name> <description>Data receive in progress</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXACT</name> <description>Data transmit in progress</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDACT</name> <description>Command transfer in progress</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBCKEND</name> <description>Data block sent/received (CRC check passed)</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STBITERR</name> <description>Start bit not detected on all data signals in wide bus mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DATAEND</name> <description>Data end (data counter, SDIDCOUNT, is zero)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDSENT</name> <description>Command sent (no response required)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDREND</name> <description>Command response received (CRC check passed)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXOVERR</name> <description>Received FIFO overrun error</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXUNDERR</name> <description>Transmit FIFO underrun error</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTIMEOUT</name> <description>Data timeout</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTIMEOUT</name> <description>Command response timeout</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCRCFAIL</name> <description>Data block sent/received (CRC check failed)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCRCFAIL</name> <description>Command response received (CRC check failed)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ICR</name> <displayName>ICR</displayName> <description>interrupt clear register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CEATAENDC</name> <description>CEATAEND flag clear bit</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIOITC</name> <description>SDIOIT flag clear bit</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBCKENDC</name> <description>DBCKEND flag clear bit</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STBITERRC</name> <description>STBITERR flag clear bit</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DATAENDC</name> <description>DATAEND flag clear bit</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDSENTC</name> <description>CMDSENT flag clear bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDRENDC</name> <description>CMDREND flag clear bit</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXOVERRC</name> <description>RXOVERR flag clear bit</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXUNDERRC</name> <description>TXUNDERR flag clear bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTIMEOUTC</name> <description>DTIMEOUT flag clear bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTIMEOUTC</name> <description>CTIMEOUT flag clear bit</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCRCFAILC</name> <description>DCRCFAIL flag clear bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCRCFAILC</name> <description>CCRCFAIL flag clear bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MASK</name> <displayName>MASK</displayName> <description>mask register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CEATAENDIE</name> <description>CE-ATA command completion signal received interrupt enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDIOITIE</name> <description>SDIO mode interrupt received interrupt enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXDAVLIE</name> <description>Data available in Rx FIFO interrupt enable</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXDAVLIE</name> <description>Data available in Tx FIFO interrupt enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFIFOEIE</name> <description>Rx FIFO empty interrupt enable</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFIFOEIE</name> <description>Tx FIFO empty interrupt enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFIFOFIE</name> <description>Rx FIFO full interrupt enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFIFOFIE</name> <description>Tx FIFO full interrupt enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXFIFOHFIE</name> <description>Rx FIFO half full interrupt enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFIFOHEIE</name> <description>Tx FIFO half empty interrupt enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXACTIE</name> <description>Data receive acting interrupt enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXACTIE</name> <description>Data transmit acting interrupt enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDACTIE</name> <description>Command acting interrupt enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBCKENDIE</name> <description>Data block end interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STBITERRIE</name> <description>Start bit error interrupt enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DATAENDIE</name> <description>Data end interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDSENTIE</name> <description>Command sent interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMDRENDIE</name> <description>Command response received interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXOVERRIE</name> <description>Rx FIFO overrun error interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXUNDERRIE</name> <description>Tx FIFO underrun error interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTIMEOUTIE</name> <description>Data timeout interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTIMEOUTIE</name> <description>Command timeout interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCRCFAILIE</name> <description>Data CRC fail interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCRCFAILIE</name> <description>Command CRC fail interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FIFOCNT</name> <displayName>FIFOCNT</displayName> <description>FIFO counter register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FIFOCOUNT</name> <description>Remaining number of words to be written to or read from the FIFO.</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>FIFO</name> <displayName>FIFO</displayName> <description>data FIFO register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FIFOData</name> <description>Receive and transmit FIFO data</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>ADC1</name> <description>Analog-to-digital converter</description> <groupName>ADC</groupName> <baseAddress>0x40012000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x51</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OVR</name> <description>Overrun</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT</name> <description>Regular channel start flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT</name> <description>Injected channel start flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC</name> <description>Injected channel end of conversion</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC</name> <description>Regular channel end of conversion</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD</name> <description>Analog watchdog flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OVRIE</name> <description>Overrun interrupt enable</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RES</name> <description>Resolution</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>AWDEN</name> <description>Analog watchdog enable on regular channels</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JAWDEN</name> <description>Analog watchdog enable on injected channels</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISCNUM</name> <description>Discontinuous mode channel count</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>JDISCEN</name> <description>Discontinuous mode on injected channels</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISCEN</name> <description>Discontinuous mode on regular channels</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JAUTO</name> <description>Automatic injected group conversion</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWDSGL</name> <description>Enable the watchdog on a single channel in scan mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SCAN</name> <description>Scan mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOCIE</name> <description>Interrupt enable for injected channels</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWDIE</name> <description>Analog watchdog interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOCIE</name> <description>Interrupt enable for EOC</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWDCH</name> <description>Analog watchdog channel select bits</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SWSTART</name> <description>Start conversion of regular channels</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTEN</name> <description>External trigger enable for regular channels</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>EXTSEL</name> <description>External event select for regular group</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>JSWSTART</name> <description>Start conversion of injected channels</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEXTEN</name> <description>External trigger enable for injected channels</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>JEXTSEL</name> <description>External event select for injected group</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ALIGN</name> <description>Data alignment</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOCS</name> <description>End of conversion selection</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DDS</name> <description>DMA disable selection (for single ADC mode)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMA</name> <description>Direct memory access mode (for single ADC mode)</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CONT</name> <description>Continuous conversion</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADON</name> <description>A/D Converter ON / OFF</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMPR1</name> <displayName>SMPR1</displayName> <description>sample time register 1</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SMPx_x</name> <description>Sample time bits</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>SMPR2</name> <displayName>SMPR2</displayName> <description>sample time register 2</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SMPx_x</name> <description>Sample time bits</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>JOFR1</name> <displayName>JOFR1</displayName> <description>injected channel data offset register x</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET1</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>JOFR2</name> <displayName>JOFR2</displayName> <description>injected channel data offset register x</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET2</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>JOFR3</name> <displayName>JOFR3</displayName> <description>injected channel data offset register x</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET3</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>JOFR4</name> <displayName>JOFR4</displayName> <description>injected channel data offset register x</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JOFFSET4</name> <description>Data offset for injected channel x</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>HTR</name> <displayName>HTR</displayName> <description>watchdog higher threshold register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000FFF</resetValue> <fields> <field> <name>HT</name> <description>Analog watchdog higher threshold</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>LTR</name> <displayName>LTR</displayName> <description>watchdog lower threshold register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LT</name> <description>Analog watchdog lower threshold</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>SQR1</name> <displayName>SQR1</displayName> <description>regular sequence register 1</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>L</name> <description>Regular channel sequence length</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SQ16</name> <description>16th conversion in regular sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ15</name> <description>15th conversion in regular sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ14</name> <description>14th conversion in regular sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ13</name> <description>13th conversion in regular sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>SQR2</name> <displayName>SQR2</displayName> <description>regular sequence register 2</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SQ12</name> <description>12th conversion in regular sequence</description> <bitOffset>25</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ11</name> <description>11th conversion in regular sequence</description> <bitOffset>20</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ10</name> <description>10th conversion in regular sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ9</name> <description>9th conversion in regular sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ8</name> <description>8th conversion in regular sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ7</name> <description>7th conversion in regular sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>SQR3</name> <displayName>SQR3</displayName> <description>regular sequence register 3</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SQ6</name> <description>6th conversion in regular sequence</description> <bitOffset>25</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ5</name> <description>5th conversion in regular sequence</description> <bitOffset>20</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ4</name> <description>4th conversion in regular sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ3</name> <description>3rd conversion in regular sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ2</name> <description>2nd conversion in regular sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SQ1</name> <description>1st conversion in regular sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>JSQR</name> <displayName>JSQR</displayName> <description>injected sequence register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JL</name> <description>Injected sequence length</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>JSQ4</name> <description>4th conversion in injected sequence</description> <bitOffset>15</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>JSQ3</name> <description>3rd conversion in injected sequence</description> <bitOffset>10</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>JSQ2</name> <description>2nd conversion in injected sequence</description> <bitOffset>5</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>JSQ1</name> <description>1st conversion in injected sequence</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>JDR1</name> <displayName>JDR1</displayName> <description>injected data register x</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>JDR2</name> <displayName>JDR2</displayName> <description>injected data register x</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>JDR3</name> <displayName>JDR3</displayName> <description>injected data register x</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>JDR4</name> <displayName>JDR4</displayName> <description>injected data register x</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>JDATA</name> <description>Injected data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>regular data register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA</name> <description>Regular data</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="ADC1"> <name>ADC2</name> <baseAddress>0x40012100</baseAddress> </peripheral> <peripheral derivedFrom="ADC1"> <name>ADC3</name> <baseAddress>0x40012200</baseAddress> <interrupt> <name>ADC</name> <description>ADC3 global interrupts</description> <value>18</value> </interrupt> </peripheral> <peripheral> <name>USART6</name> <description>Universal synchronous asynchronous receiver transmitter</description> <groupName>USART</groupName> <baseAddress>0x40011400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>USART6</name> <description>USART6 global interrupt</description> <value>71</value> </interrupt> <registers> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00C00000</resetValue> <fields> <field> <name>CTS</name> <description>CTS flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>LBD</name> <description>LIN break detection flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXE</name> <description>Transmit data register empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TC</name> <description>Transmission complete</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXNE</name> <description>Read data register not empty</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IDLE</name> <description>IDLE line detected</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ORE</name> <description>Overrun error</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NF</name> <description>Noise detected flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>FE</name> <description>Framing error</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PE</name> <description>Parity error</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DR</name> <description>Data value</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>BRR</name> <displayName>BRR</displayName> <description>Baud rate register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DIV_Mantissa</name> <description>mantissa of USARTDIV</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>DIV_Fraction</name> <description>fraction of USARTDIV</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>OVER8</name> <description>Oversampling mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UE</name> <description>USART enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>M</name> <description>Word length</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAKE</name> <description>Wakeup method</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PCE</name> <description>Parity control enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PS</name> <description>Parity selection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PEIE</name> <description>PE interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXEIE</name> <description>TXE interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transmission complete interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNEIE</name> <description>RXNE interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDLEIE</name> <description>IDLE interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TE</name> <description>Transmitter enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RE</name> <description>Receiver enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWU</name> <description>Receiver wakeup</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBK</name> <description>Send break</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LINEN</name> <description>LIN mode enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>STOP bits</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CLKEN</name> <description>Clock enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPOL</name> <description>Clock polarity</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPHA</name> <description>Clock phase</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBCL</name> <description>Last bit clock pulse</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDIE</name> <description>LIN break detection interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDL</name> <description>lin break detection length</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD</name> <description>Address of the USART node</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR3</name> <displayName>CR3</displayName> <description>Control register 3</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ONEBIT</name> <description>One sample bit method enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSIE</name> <description>CTS interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTSE</name> <description>CTS enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTSE</name> <description>RTS enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAT</name> <description>DMA enable transmitter</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAR</name> <description>DMA enable receiver</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SCEN</name> <description>Smartcard mode enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NACK</name> <description>Smartcard NACK enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HDSEL</name> <description>Half-duplex selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IRLP</name> <description>IrDA low-power</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IREN</name> <description>IrDA mode enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EIE</name> <description>Error interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>GTPR</name> <displayName>GTPR</displayName> <description>Guard time and prescaler register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>GT</name> <description>Guard time value</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="USART6"> <name>USART1</name> <baseAddress>0x40011000</baseAddress> <interrupt> <name>USART1</name> <description>USART1 global interrupt</description> <value>37</value> </interrupt> </peripheral> <peripheral derivedFrom="USART6"> <name>USART2</name> <baseAddress>0x40004400</baseAddress> <interrupt> <name>USART2</name> <description>USART2 global interrupt</description> <value>38</value> </interrupt> </peripheral> <peripheral derivedFrom="USART6"> <name>USART3</name> <baseAddress>0x40004800</baseAddress> <interrupt> <name>USART3</name> <description>USART3 global interrupt</description> <value>39</value> </interrupt> </peripheral> <peripheral derivedFrom="USART6"> <name>UART7</name> <baseAddress>0x40007800</baseAddress> <interrupt> <name>UART7</name> <description>UART 7 global interrupt</description> <value>82</value> </interrupt> </peripheral> <peripheral derivedFrom="USART6"> <name>UART8</name> <baseAddress>0x40007C00</baseAddress> <interrupt> <name>UART8</name> <description>UART 8 global interrupt</description> <value>83</value> </interrupt> </peripheral> <peripheral> <name>DAC</name> <description>Digital-to-analog converter</description> <groupName>DAC</groupName> <baseAddress>0x40007400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM6_DAC</name> <description>TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt</description> <value>54</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAUDRIE2</name> <description>DAC channel2 DMA underrun interrupt enable</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN2</name> <description>DAC channel2 DMA enable</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MAMP2</name> <description>DAC channel2 mask/amplitude selector</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>WAVE2</name> <description>DAC channel2 noise/triangle wave generation enable</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TSEL2</name> <description>DAC channel2 trigger selection</description> <bitOffset>19</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TEN2</name> <description>DAC channel2 trigger enable</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOFF2</name> <description>DAC channel2 output buffer disable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN2</name> <description>DAC channel2 enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAUDRIE1</name> <description>DAC channel1 DMA Underrun Interrupt enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN1</name> <description>DAC channel1 DMA enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MAMP1</name> <description>DAC channel1 mask/amplitude selector</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>WAVE1</name> <description>DAC channel1 noise/triangle wave generation enable</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TSEL1</name> <description>DAC channel1 trigger selection</description> <bitOffset>3</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TEN1</name> <description>DAC channel1 trigger enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOFF1</name> <description>DAC channel1 output buffer disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EN1</name> <description>DAC channel1 enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SWTRIGR</name> <displayName>SWTRIGR</displayName> <description>software trigger register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SWTRIG2</name> <description>DAC channel2 software trigger</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWTRIG1</name> <description>DAC channel1 software trigger</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DHR12R1</name> <displayName>DHR12R1</displayName> <description>channel1 12-bit right-aligned data holding register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR12L1</name> <displayName>DHR12L1</displayName> <description>channel1 12-bit left aligned data holding register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit left-aligned data</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR8R1</name> <displayName>DHR8R1</displayName> <description>channel1 8-bit right aligned data holding register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DHR</name> <description>DAC channel1 8-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DHR12R2</name> <displayName>DHR12R2</displayName> <description>channel2 12-bit right aligned data holding register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR12L2</name> <displayName>DHR12L2</displayName> <description>channel2 12-bit left aligned data holding register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit left-aligned data</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR8R2</name> <displayName>DHR8R2</displayName> <description>channel2 8-bit right-aligned data holding register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 8-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DHR12RD</name> <displayName>DHR12RD</displayName> <description>Dual DAC 12-bit right-aligned data holding register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit right-aligned data</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR12LD</name> <displayName>DHR12LD</displayName> <description>DUAL DAC 12-bit left aligned data holding register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 12-bit left-aligned data</description> <bitOffset>20</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>DACC1DHR</name> <description>DAC channel1 12-bit left-aligned data</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DHR8RD</name> <displayName>DHR8RD</displayName> <description>DUAL DAC 8-bit right aligned data holding register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DHR</name> <description>DAC channel2 8-bit right-aligned data</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DACC1DHR</name> <description>DAC channel1 8-bit right-aligned data</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DOR1</name> <displayName>DOR1</displayName> <description>channel1 data output register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC1DOR</name> <description>DAC channel1 data output</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DOR2</name> <displayName>DOR2</displayName> <description>channel2 data output register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DACC2DOR</name> <description>DAC channel2 data output</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DMAUDR2</name> <description>DAC channel2 DMA underrun flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAUDR1</name> <description>DAC channel1 DMA underrun flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>IWDG</name> <description>Independent watchdog</description> <groupName>IWDG</groupName> <baseAddress>0x40003000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>KR</name> <displayName>KR</displayName> <description>Key register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>Key value (write only, read 0000h)</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PR</name> <displayName>PR</displayName> <description>Prescaler register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PR</name> <description>Prescaler divider</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>RLR</name> <displayName>RLR</displayName> <description>Reload register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000FFF</resetValue> <fields> <field> <name>RL</name> <description>Watchdog counter reload value</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RVU</name> <description>Watchdog counter reload value update</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PVU</name> <description>Watchdog prescaler value update</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>WWDG</name> <description>Window watchdog</description> <groupName>WWDG</groupName> <baseAddress>0x40002C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>WWDG</name> <description>Window Watchdog interrupt</description> <value>0</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7F</resetValue> <fields> <field> <name>WDGA</name> <description>Activation bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>T</name> <description>7-bit counter (MSB to LSB)</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>CFR</name> <displayName>CFR</displayName> <description>Configuration register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x7F</resetValue> <fields> <field> <name>EWI</name> <description>Early wakeup interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDGTB1</name> <description>Timer base</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDGTB0</name> <description>Timer base</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>W</name> <description>7-bit window value</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00</resetValue> <fields> <field> <name>EWIF</name> <description>Early wakeup interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>RTC</name> <description>Real-time clock</description> <groupName>RTC</groupName> <baseAddress>0x40002800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>RTC_WKUP</name> <description>RTC Wakeup interrupt through the EXTI line</description> <value>3</value> </interrupt> <interrupt> <name>RTC_Alarm</name> <description>RTC Alarms (A and B) through EXTI line interrupt</description> <value>41</value> </interrupt> <registers> <register> <name>TR</name> <displayName>TR</displayName> <description>time register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>date register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00002101</resetValue> <fields> <field> <name>YT</name> <description>Year tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>YU</name> <description>Year units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>WDU</name> <description>Week day units</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MT</name> <description>Month tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MU</name> <description>Month units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>COE</name> <description>Calibration output enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSEL</name> <description>Output selection</description> <bitOffset>21</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>POL</name> <description>Output polarity</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKP</name> <description>Backup</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SUB1H</name> <description>Subtract 1 hour (winter time change)</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD1H</name> <description>Add 1 hour (summer time change)</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSIE</name> <description>Time-stamp interrupt enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTIE</name> <description>Wakeup timer interrupt enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBIE</name> <description>Alarm B interrupt enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRAIE</name> <description>Alarm A interrupt enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSE</name> <description>Time stamp enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WUTE</name> <description>Wakeup timer enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRBE</name> <description>Alarm B enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALRAE</name> <description>Alarm A enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DCE</name> <description>Coarse digital calibration enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FMT</name> <description>Hour format</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>REFCKON</name> <description>Reference clock detection enable (50 or 60 Hz)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSEDGE</name> <description>Time-stamp event active edge</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKSEL</name> <description>Wakeup clock selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>ISR</name> <displayName>ISR</displayName> <description>initialization and status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000007</resetValue> <fields> <field> <name>ALRAWF</name> <description>Alarm A write flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ALRBWF</name> <description>Alarm B write flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>WUTWF</name> <description>Wakeup timer write flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SHPF</name> <description>Shift operation pending</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INITS</name> <description>Initialization status flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RSF</name> <description>Registers synchronization flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INITF</name> <description>Initialization flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INIT</name> <description>Initialization mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALRAF</name> <description>Alarm A flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALRBF</name> <description>Alarm B flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WUTF</name> <description>Wakeup timer flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TSF</name> <description>Time-stamp flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TSOVF</name> <description>Time-stamp overflow flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TAMP1F</name> <description>Tamper detection flag</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TAMP2F</name> <description>TAMPER2 detection flag</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RECALPF</name> <description>Recalibration pending Flag</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>PRER</name> <displayName>PRER</displayName> <description>prescaler register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x007F00FF</resetValue> <fields> <field> <name>PREDIV_A</name> <description>Asynchronous prescaler factor</description> <bitOffset>16</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PREDIV_S</name> <description>Synchronous prescaler factor</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>WUTR</name> <displayName>WUTR</displayName> <description>wakeup timer register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000FFFF</resetValue> <fields> <field> <name>WUT</name> <description>Wakeup auto-reload value bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CALIBR</name> <displayName>CALIBR</displayName> <description>calibration register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DCS</name> <description>Digital calibration sign</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DC</name> <description>Digital calibration</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>ALRMAR</name> <displayName>ALRMAR</displayName> <description>alarm A register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MSK4</name> <description>Alarm A date mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDSEL</name> <description>Week day selection</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units or day in BCD format</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK3</name> <description>Alarm A hours mask</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK2</name> <description>Alarm A minutes mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK1</name> <description>Alarm A seconds mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>ALRMBR</name> <displayName>ALRMBR</displayName> <description>alarm B register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MSK4</name> <description>Alarm B date mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WDSEL</name> <description>Week day selection</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units or day in BCD format</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK3</name> <description>Alarm B hours mask</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PM</name> <description>AM/PM notation</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HT</name> <description>Hour tens in BCD format</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>HU</name> <description>Hour units in BCD format</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK2</name> <description>Alarm B minutes mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MNT</name> <description>Minute tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MNU</name> <description>Minute units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSK1</name> <description>Alarm B seconds mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ST</name> <description>Second tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SU</name> <description>Second units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>WPR</name> <displayName>WPR</displayName> <description>write protection register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>Write protection key</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SSR</name> <displayName>SSR</displayName> <description>sub second register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SS</name> <description>Sub second value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>SHIFTR</name> <displayName>SHIFTR</displayName> <description>shift control register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADD1S</name> <description>Add one second</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SUBFS</name> <description>Subtract a fraction of a second</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>TSTR</name> <displayName>TSTR</displayName> <description>time stamp time register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALARMOUTTYPE</name> <description>AFO_ALARM output type</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSINSEL</name> <description>TIMESTAMP mapping</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1INSEL</name> <description>TAMPER1 mapping</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPIE</name> <description>Tamper interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1TRG</name> <description>Active level for tamper 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1E</name> <description>Tamper 1 detection enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TSDR</name> <displayName>TSDR</displayName> <description>time stamp date register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WDU</name> <description>Week day units</description> <bitOffset>13</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MT</name> <description>Month tens in BCD format</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MU</name> <description>Month units in BCD format</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DT</name> <description>Date tens in BCD format</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DU</name> <description>Date units in BCD format</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TSSSR</name> <displayName>TSSSR</displayName> <description>timestamp sub second register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SS</name> <description>Sub second value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CALR</name> <displayName>CALR</displayName> <description>calibration register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CALP</name> <description>Increase frequency of RTC by 488.5 ppm</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALW8</name> <description>Use an 8-second calibration cycle period</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALW16</name> <description>Use a 16-second calibration cycle period</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CALM</name> <description>Calibration minus</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>TAFCR</name> <displayName>TAFCR</displayName> <description>tamper and alternate function configuration register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ALARMOUTTYPE</name> <description>AFO_ALARM output type</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSINSEL</name> <description>TIMESTAMP mapping</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1INSEL</name> <description>TAMPER1 mapping</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPPUDIS</name> <description>TAMPER pull-up disable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPPRCH</name> <description>Tamper precharge duration</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TAMPFLT</name> <description>Tamper filter count</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TAMPFREQ</name> <description>Tamper sampling frequency</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TAMPTS</name> <description>Activate timestamp on tamper detection event</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2TRG</name> <description>Active level for tamper 2</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP2E</name> <description>Tamper 2 detection enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMPIE</name> <description>Tamper interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1TRG</name> <description>Active level for tamper 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TAMP1E</name> <description>Tamper 1 detection enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ALRMASSR</name> <displayName>ALRMASSR</displayName> <description>alarm A sub second register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MASKSS</name> <description>Mask the most-significant bits starting at this bit</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SS</name> <description>Sub seconds value</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>ALRMBSSR</name> <displayName>ALRMBSSR</displayName> <description>alarm B sub second register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MASKSS</name> <description>Mask the most-significant bits starting at this bit</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SS</name> <description>Sub seconds value</description> <bitOffset>0</bitOffset> <bitWidth>15</bitWidth> </field> </fields> </register> <register> <name>BKP0R</name> <displayName>BKP0R</displayName> <description>backup register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP1R</name> <displayName>BKP1R</displayName> <description>backup register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP2R</name> <displayName>BKP2R</displayName> <description>backup register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP3R</name> <displayName>BKP3R</displayName> <description>backup register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP4R</name> <displayName>BKP4R</displayName> <description>backup register</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP5R</name> <displayName>BKP5R</displayName> <description>backup register</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP6R</name> <displayName>BKP6R</displayName> <description>backup register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP7R</name> <displayName>BKP7R</displayName> <description>backup register</description> <addressOffset>0x6C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP8R</name> <displayName>BKP8R</displayName> <description>backup register</description> <addressOffset>0x70</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP9R</name> <displayName>BKP9R</displayName> <description>backup register</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP10R</name> <displayName>BKP10R</displayName> <description>backup register</description> <addressOffset>0x78</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP11R</name> <displayName>BKP11R</displayName> <description>backup register</description> <addressOffset>0x7C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP12R</name> <displayName>BKP12R</displayName> <description>backup register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP13R</name> <displayName>BKP13R</displayName> <description>backup register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP14R</name> <displayName>BKP14R</displayName> <description>backup register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP15R</name> <displayName>BKP15R</displayName> <description>backup register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP16R</name> <displayName>BKP16R</displayName> <description>backup register</description> <addressOffset>0x90</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP17R</name> <displayName>BKP17R</displayName> <description>backup register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP18R</name> <displayName>BKP18R</displayName> <description>backup register</description> <addressOffset>0x98</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BKP19R</name> <displayName>BKP19R</displayName> <description>backup register</description> <addressOffset>0x9C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BKP</name> <description>BKP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>UART4</name> <description>Universal synchronous asynchronous receiver transmitter</description> <groupName>USART</groupName> <baseAddress>0x40004C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>UART4</name> <description>UART4 global interrupt</description> <value>52</value> </interrupt> <registers> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00C00000</resetValue> <fields> <field> <name>LBD</name> <description>LIN break detection flag</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXE</name> <description>Transmit data register empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TC</name> <description>Transmission complete</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXNE</name> <description>Read data register not empty</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IDLE</name> <description>IDLE line detected</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ORE</name> <description>Overrun error</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NF</name> <description>Noise detected flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>FE</name> <description>Framing error</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PE</name> <description>Parity error</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DR</name> <description>Data value</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> <register> <name>BRR</name> <displayName>BRR</displayName> <description>Baud rate register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DIV_Mantissa</name> <description>mantissa of USARTDIV</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>DIV_Fraction</name> <description>fraction of USARTDIV</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>OVER8</name> <description>Oversampling mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UE</name> <description>USART enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>M</name> <description>Word length</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAKE</name> <description>Wakeup method</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PCE</name> <description>Parity control enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PS</name> <description>Parity selection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PEIE</name> <description>PE interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXEIE</name> <description>TXE interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transmission complete interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXNEIE</name> <description>RXNE interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDLEIE</name> <description>IDLE interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TE</name> <description>Transmitter enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RE</name> <description>Receiver enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWU</name> <description>Receiver wakeup</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SBK</name> <description>Send break</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LINEN</name> <description>LIN mode enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>STOP bits</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>LBDIE</name> <description>LIN break detection interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBDL</name> <description>lin break detection length</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD</name> <description>Address of the USART node</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>CR3</name> <displayName>CR3</displayName> <description>Control register 3</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ONEBIT</name> <description>One sample bit method enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAT</name> <description>DMA enable transmitter</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAR</name> <description>DMA enable receiver</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HDSEL</name> <description>Half-duplex selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IRLP</name> <description>IrDA low-power</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IREN</name> <description>IrDA mode enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EIE</name> <description>Error interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="UART4"> <name>UART5</name> <baseAddress>0x40005000</baseAddress> <interrupt> <name>UART5</name> <description>UART5 global interrupt</description> <value>53</value> </interrupt> </peripheral> <peripheral> <name>C_ADC</name> <description>Common ADC registers</description> <groupName>ADC</groupName> <baseAddress>0x40012300</baseAddress> <addressBlock> <offset>0x0</offset> <size>0xD</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CSR</name> <displayName>CSR</displayName> <description>ADC Common status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OVR3</name> <description>Overrun flag of ADC3</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT3</name> <description>Regular channel Start flag of ADC 3</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT3</name> <description>Injected channel Start flag of ADC 3</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC3</name> <description>Injected channel end of conversion of ADC 3</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC3</name> <description>End of conversion of ADC 3</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD3</name> <description>Analog watchdog flag of ADC 3</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR2</name> <description>Overrun flag of ADC 2</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT2</name> <description>Regular channel Start flag of ADC 2</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT2</name> <description>Injected channel Start flag of ADC 2</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC2</name> <description>Injected channel end of conversion of ADC 2</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC2</name> <description>End of conversion of ADC 2</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD2</name> <description>Analog watchdog flag of ADC 2</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVR1</name> <description>Overrun flag of ADC 1</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT1</name> <description>Regular channel Start flag of ADC 1</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JSTRT1</name> <description>Injected channel Start flag of ADC 1</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>JEOC1</name> <description>Injected channel end of conversion of ADC 1</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOC1</name> <description>End of conversion of ADC 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWD1</name> <description>Analog watchdog flag of ADC 1</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>ADC common control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TSVREFE</name> <description>Temperature sensor and VREFINT enable</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBATE</name> <description>VBAT enable</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCPRE</name> <description>ADC prescaler</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DMA</name> <description>Direct memory access mode for multi ADC mode</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DDS</name> <description>DMA disable selection for multi-ADC mode</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DELAY</name> <description>Delay between 2 sampling phases</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MULT</name> <description>Multi ADC mode selection</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>CDR</name> <displayName>CDR</displayName> <description>ADC common regular data register for dual and triple modes</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA2</name> <description>2nd data item of a pair of regular conversions</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>DATA1</name> <description>1st data item of a pair of regular conversions</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM1</name> <description>Advanced-timers</description> <groupName>TIM</groupName> <baseAddress>0x40010000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM1_BRK_TIM9</name> <description>TIM1 Break interrupt and TIM9 global interrupt</description> <value>24</value> </interrupt> <interrupt> <name>TIM1_UP_TIM10</name> <description>TIM1 Update interrupt and TIM10 global interrupt</description> <value>25</value> </interrupt> <interrupt> <name>TIM1_TRG_COM_TIM11</name> <description>TIM1 Trigger and Commutation interrupts and TIM11 global interrupt</description> <value>26</value> </interrupt> <interrupt> <name>TIM1_CC</name> <description>TIM1 Capture Compare interrupt</description> <value>27</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>OIS4</name> <description>Output Idle state 4</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS3N</name> <description>Output Idle state 3</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS3</name> <description>Output Idle state 3</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS2N</name> <description>Output Idle state 2</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS2</name> <description>Output Idle state 2</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS1N</name> <description>Output Idle state 1</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OIS1</name> <description>Output Idle state 1</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCUS</name> <description>Capture/compare control update selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCPC</name> <description>Capture/compare preloaded control</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMDE</name> <description>COM DMA request enable</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIE</name> <description>Break interrupt enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIE</name> <description>COM interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIF</name> <description>Break interrupt flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMIF</name> <description>COM interrupt flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>BG</name> <description>Break generation</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COMG</name> <description>Capture/Compare control update generation</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2CE</name> <description>Output Compare 2 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>Output Compare 2 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>Output Compare 2 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>Output Compare 2 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1CE</name> <description>Output Compare 1 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC4CE</name> <description>Output compare 4 clear enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>Output compare 4 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4PE</name> <description>Output compare 4 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4FE</name> <description>Output compare 4 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3CE</name> <description>Output compare 3 clear enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>Output compare 3 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3PE</name> <description>Output compare 3 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3FE</name> <description>Output compare 3 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/Compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (input mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC4F</name> <description>Input capture 4 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC4PSC</name> <description>Input capture 4 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC3F</name> <description>Input capture 3 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC3PSC</name> <description>Input capture 3 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NE</name> <description>Capture/Compare 3 complementary output enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NE</name> <description>Capture/Compare 2 complementary output enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NE</name> <description>Capture/Compare 1 complementary output enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2</name> <description>Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4</name> <description>Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>RCR</name> <displayName>RCR</displayName> <description>repetition counter register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>REP</name> <description>Repetition counter value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>BDTR</name> <displayName>BDTR</displayName> <description>break and dead-time register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MOE</name> <description>Main output enable</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AOE</name> <description>Automatic output enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKP</name> <description>Break polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BKE</name> <description>Break enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSSR</name> <description>Off-state selection for Run mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSSI</name> <description>Off-state selection for Idle mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LOCK</name> <description>Lock configuration</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DTG</name> <description>Dead-time generator setup</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM1"> <name>TIM8</name> <baseAddress>0x40010400</baseAddress> <interrupt> <name>TIM8_BRK_TIM12</name> <description>TIM8 Break interrupt and TIM12 global interrupt</description> <value>43</value> </interrupt> <interrupt> <name>TIM8_CC</name> <description>TIM8 Capture Compare interrupt</description> <value>46</value> </interrupt> </peripheral> <peripheral> <name>TIM2</name> <description>General purpose timers</description> <groupName>TIM</groupName> <baseAddress>0x40000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM2</name> <description>TIM2 global interrupt</description> <value>28</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2CE</name> <description>OC2CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>OC2M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>OC2PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>OC2FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>CC2S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1CE</name> <description>OC1CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>OC1M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>OC1PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>OC1FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>CC1S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>O24CE</name> <description>O24CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>OC4M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4PE</name> <description>OC4PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4FE</name> <description>OC4FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>CC4S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3CE</name> <description>OC3CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>OC3M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3PE</name> <description>OC3PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3FE</name> <description>OC3FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3S</name> <description>CC3S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (input mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC4F</name> <description>Input capture 4 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC4PSC</name> <description>Input capture 4 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC3F</name> <description>Input capture 3 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC3PSC</name> <description>Input capture 3 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4NP</name> <description>Capture/Compare 4 output Polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT_H</name> <description>High counter value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CNT_L</name> <description>Low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR_H</name> <description>High Auto-reload value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>ARR_L</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1_H</name> <description>High Capture/Compare 1 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR1_L</name> <description>Low Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2_H</name> <description>High Capture/Compare 2 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR2_L</name> <description>Low Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR3_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR4_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OR</name> <displayName>OR</displayName> <description>TIM5 option register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ITR1_RMP</name> <description>Timer Input 4 remap</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM3</name> <description>General purpose timers</description> <groupName>TIM</groupName> <baseAddress>0x40000400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM3</name> <description>TIM3 global interrupt</description> <value>29</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2CE</name> <description>OC2CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>OC2M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>OC2PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>OC2FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>CC2S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1CE</name> <description>OC1CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>OC1M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>OC1PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>OC1FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>CC1S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>O24CE</name> <description>O24CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>OC4M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4PE</name> <description>OC4PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4FE</name> <description>OC4FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>CC4S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3CE</name> <description>OC3CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>OC3M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3PE</name> <description>OC3PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3FE</name> <description>OC3FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3S</name> <description>CC3S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (input mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC4F</name> <description>Input capture 4 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC4PSC</name> <description>Input capture 4 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC3F</name> <description>Input capture 3 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC3PSC</name> <description>Input capture 3 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4NP</name> <description>Capture/Compare 4 output Polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT_H</name> <description>High counter value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CNT_L</name> <description>Low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR_H</name> <description>High Auto-reload value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>ARR_L</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1_H</name> <description>High Capture/Compare 1 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR1_L</name> <description>Low Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2_H</name> <description>High Capture/Compare 2 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR2_L</name> <description>Low Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR3_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR4_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM3"> <name>TIM4</name> <baseAddress>0x40000800</baseAddress> <interrupt> <name>TIM4</name> <description>TIM4 global interrupt</description> <value>30</value> </interrupt> </peripheral> <peripheral> <name>TIM5</name> <description>General-purpose-timers</description> <groupName>TIM</groupName> <baseAddress>0x40000C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TIM5</name> <description>TIM5 global interrupt</description> <value>50</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CMS</name> <description>Center-aligned mode selection</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DIR</name> <description>Direction</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TI1S</name> <description>TI1 selection</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>CCDS</name> <description>Capture/compare DMA selection</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ETP</name> <description>External trigger polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ECE</name> <description>External clock enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETPS</name> <description>External trigger prescaler</description> <bitOffset>12</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ETF</name> <description>External trigger filter</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TDE</name> <description>Trigger DMA request enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4DE</name> <description>Capture/Compare 4 DMA request enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3DE</name> <description>Capture/Compare 3 DMA request enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2DE</name> <description>Capture/Compare 2 DMA request enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1DE</name> <description>Capture/Compare 1 DMA request enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IE</name> <description>Capture/Compare 4 interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IE</name> <description>Capture/Compare 3 interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4OF</name> <description>Capture/Compare 4 overcapture flag</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3OF</name> <description>Capture/Compare 3 overcapture flag</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4IF</name> <description>Capture/Compare 4 interrupt flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3IF</name> <description>Capture/Compare 3 interrupt flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4G</name> <description>Capture/compare 4 generation</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3G</name> <description>Capture/compare 3 generation</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2CE</name> <description>OC2CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2M</name> <description>OC2M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>OC2PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>OC2FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>CC2S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1CE</name> <description>OC1CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1M</name> <description>OC1M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>OC1PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>OC1FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>CC1S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Output</name> <displayName>CCMR2_Output</displayName> <description>capture/compare mode register 2 (output mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>O24CE</name> <description>O24CE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4M</name> <description>OC4M</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC4PE</name> <description>OC4PE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC4FE</name> <description>OC4FE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4S</name> <description>CC4S</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC3CE</name> <description>OC3CE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3M</name> <description>OC3M</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC3PE</name> <description>OC3PE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC3FE</name> <description>OC3FE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3S</name> <description>CC3S</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR2_Input</name> <displayName>CCMR2_Input</displayName> <description>capture/compare mode register 2 (input mode)</description> <alternateRegister>CCMR2_Output</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC4F</name> <description>Input capture 4 filter</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC4PSC</name> <description>Input capture 4 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC4S</name> <description>Capture/Compare 4 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC3F</name> <description>Input capture 3 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>IC3PSC</name> <description>Input capture 3 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC3S</name> <description>Capture/compare 3 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC4NP</name> <description>Capture/Compare 4 output Polarity</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC4E</name> <description>Capture/Compare 4 output enable</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3NP</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3P</name> <description>Capture/Compare 3 output Polarity</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC3E</name> <description>Capture/Compare 3 output enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT_H</name> <description>High counter value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CNT_L</name> <description>Low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR_H</name> <description>High Auto-reload value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>ARR_L</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1_H</name> <description>High Capture/Compare 1 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR1_L</name> <description>Low Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2_H</name> <description>High Capture/Compare 2 value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR2_L</name> <description>Low Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR3</name> <displayName>CCR3</displayName> <description>capture/compare register 3</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR3_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR3_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR4</name> <displayName>CCR4</displayName> <description>capture/compare register 4</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR4_H</name> <description>High Capture/Compare value</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CCR4_L</name> <description>Low Capture/Compare value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DCR</name> <displayName>DCR</displayName> <description>DMA control register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DBL</name> <description>DMA burst length</description> <bitOffset>8</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>DBA</name> <description>DMA base address</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>DMAR</name> <displayName>DMAR</displayName> <description>DMA address for full transfer</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DMAB</name> <description>DMA register for burst accesses</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OR</name> <displayName>OR</displayName> <description>TIM5 option register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>IT4_RMP</name> <description>Timer Input 4 remap</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM9</name> <description>General purpose timers</description> <groupName>TIM</groupName> <baseAddress>0x40014000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>SMCR</name> <displayName>SMCR</displayName> <description>slave mode control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MSM</name> <description>Master/Slave mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TS</name> <description>Trigger selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>SMS</name> <description>Slave mode selection</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TIE</name> <description>Trigger interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IE</name> <description>Capture/Compare 2 interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC2OF</name> <description>Capture/compare 2 overcapture flag</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TIF</name> <description>Trigger interrupt flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2IF</name> <description>Capture/Compare 2 interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>TG</name> <description>Trigger generation</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2G</name> <description>Capture/compare 2 generation</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC2M</name> <description>Output Compare 2 mode</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC2PE</name> <description>Output Compare 2 preload enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC2FE</name> <description>Output Compare 2 fast enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC2F</name> <description>Input capture 2 filter</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>IC2PCS</name> <description>Input capture 2 prescaler</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC2S</name> <description>Capture/Compare 2 selection</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC2NP</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2P</name> <description>Capture/Compare 2 output Polarity</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC2E</name> <description>Capture/Compare 2 output enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR2</name> <displayName>CCR2</displayName> <description>capture/compare register 2</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR2</name> <description>Capture/Compare 2 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM9"> <name>TIM12</name> <baseAddress>0x40001800</baseAddress> </peripheral> <peripheral> <name>TIM10</name> <description>General-purpose-timers</description> <groupName>TIM</groupName> <baseAddress>0x40014400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (input mode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM10"> <name>TIM13</name> <baseAddress>0x40001C00</baseAddress> <interrupt> <name>TIM8_UP_TIM13</name> <description>TIM8 Update interrupt and TIM13 global interrupt</description> <value>44</value> </interrupt> </peripheral> <peripheral derivedFrom="TIM10"> <name>TIM14</name> <baseAddress>0x40002000</baseAddress> <interrupt> <name>TIM8_TRG_COM_TIM14</name> <description>TIM8 Trigger and Commutation interrupts and TIM14 global interrupt</description> <value>45</value> </interrupt> </peripheral> <peripheral> <name>TIM11</name> <description>General-purpose-timers</description> <groupName>TIM</groupName> <baseAddress>0x40014800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CKD</name> <description>Clock division</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1IE</name> <description>Capture/Compare 1 interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1OF</name> <description>Capture/Compare 1 overcapture flag</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1IF</name> <description>Capture/compare 1 interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1G</name> <description>Capture/compare 1 generation</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Output</name> <displayName>CCMR1_Output</displayName> <description>capture/compare mode register 1 (output mode)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OC1M</name> <description>Output Compare 1 mode</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>OC1PE</name> <description>Output Compare 1 preload enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OC1FE</name> <description>Output Compare 1 fast enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCMR1_Input</name> <displayName>CCMR1_Input</displayName> <description>capture/compare mode register 1 (inputmode)</description> <alternateRegister>CCMR1_Output</alternateRegister> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IC1F</name> <description>Input capture 1 filter</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ICPCS</name> <description>Input capture 1 prescaler</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CC1S</name> <description>Capture/Compare 1 selection</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CCER</name> <displayName>CCER</displayName> <description>capture/compare enable register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>CC1NP</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1P</name> <description>Capture/Compare 1 output Polarity</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CC1E</name> <description>Capture/Compare 1 output enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CCR1</name> <displayName>CCR1</displayName> <description>capture/compare register 1</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CCR1</name> <description>Capture/Compare 1 value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OR</name> <displayName>OR</displayName> <description>option register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RMP</name> <description>Input 1 remapping capability</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>TIM6</name> <description>Basic timers</description> <groupName>TIM</groupName> <baseAddress>0x40001000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ARPE</name> <description>Auto-reload preload enable</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPM</name> <description>One-pulse mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>URS</name> <description>Update request source</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDIS</name> <description>Update disable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEN</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>MMS</name> <description>Master mode selection</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>DIER</name> <displayName>DIER</displayName> <description>DMA/Interrupt enable register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UDE</name> <description>Update DMA request enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UIE</name> <description>Update interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>status register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UIF</name> <description>Update interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EGR</name> <displayName>EGR</displayName> <description>event generation register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>UG</name> <description>Update generation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CNT</name> <displayName>CNT</displayName> <description>counter</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CNT</name> <description>Low counter value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>PSC</name> <displayName>PSC</displayName> <description>prescaler</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PSC</name> <description>Prescaler value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>ARR</name> <displayName>ARR</displayName> <description>auto-reload register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ARR</name> <description>Low Auto-reload value</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="TIM6"> <name>TIM7</name> <baseAddress>0x40001400</baseAddress> <interrupt> <name>TIM7</name> <description>TIM7 global interrupt</description> <value>55</value> </interrupt> </peripheral> <peripheral> <name>Ethernet_MAC</name> <description>Ethernet: media access control (MAC)</description> <groupName>Ethernet</groupName> <baseAddress>0x40028000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x61</size> <usage>registers</usage> </addressBlock> <interrupt> <name>ETH</name> <description>Ethernet global interrupt</description> <value>61</value> </interrupt> <interrupt> <name>ETH_WKUP</name> <description>Ethernet Wakeup through EXTI line interrupt</description> <value>62</value> </interrupt> <registers> <register> <name>MACCR</name> <displayName>MACCR</displayName> <description>Ethernet MAC configuration register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0008000</resetValue> <fields> <field> <name>RE</name> <description>RE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TE</name> <description>TE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DC</name> <description>DC</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BL</name> <description>BL</description> <bitOffset>5</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>APCS</name> <description>APCS</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RD</name> <description>RD</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IPCO</name> <description>IPCO</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DM</name> <description>DM</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LM</name> <description>LM</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ROD</name> <description>ROD</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FES</name> <description>FES</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSD</name> <description>CSD</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IFG</name> <description>IFG</description> <bitOffset>17</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>JD</name> <description>JD</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WD</name> <description>WD</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSTF</name> <description>CSTF</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACFFR</name> <displayName>MACFFR</displayName> <description>Ethernet MAC frame filter register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PM</name> <description>PM</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HU</name> <description>HU</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HM</name> <description>HM</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DAIF</name> <description>DAIF</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RAM</name> <description>RAM</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFD</name> <description>BFD</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PCF</name> <description>PCF</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SAIF</name> <description>SAIF</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SAF</name> <description>SAF</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HPF</name> <description>HPF</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RA</name> <description>RA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACHTHR</name> <displayName>MACHTHR</displayName> <description>Ethernet MAC hash table high register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HTH</name> <description>HTH</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MACHTLR</name> <displayName>MACHTLR</displayName> <description>Ethernet MAC hash table low register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HTL</name> <description>HTL</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MACMIIAR</name> <displayName>MACMIIAR</displayName> <description>Ethernet MAC MII address register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MB</name> <description>MB</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MW</name> <description>MW</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CR</name> <description>CR</description> <bitOffset>2</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>MR</name> <description>MR</description> <bitOffset>6</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>PA</name> <description>PA</description> <bitOffset>11</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>MACMIIDR</name> <displayName>MACMIIDR</displayName> <description>Ethernet MAC MII data register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TD</name> <description>TD</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>MACFCR</name> <displayName>MACFCR</displayName> <description>Ethernet MAC flow control register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FCB</name> <description>FCB</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TFCE</name> <description>TFCE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RFCE</name> <description>RFCE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UPFD</name> <description>UPFD</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLT</name> <description>PLT</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ZQPD</name> <description>ZQPD</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PT</name> <description>PT</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>MACVLANTR</name> <displayName>MACVLANTR</displayName> <description>Ethernet MAC VLAN tag register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VLANTI</name> <description>VLANTI</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>VLANTC</name> <description>VLANTC</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACPMTCSR</name> <displayName>MACPMTCSR</displayName> <description>Ethernet MAC PMT control and status register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PD</name> <description>PD</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MPE</name> <description>MPE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WFE</name> <description>WFE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MPR</name> <description>MPR</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WFR</name> <description>WFR</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GU</name> <description>GU</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WFFRPR</name> <description>WFFRPR</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACDBGR</name> <displayName>MACDBGR</displayName> <description>Ethernet MAC debug register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CR</name> <description>CR</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSR</name> <description>CSR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ROR</name> <description>ROR</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MCF</name> <description>MCF</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MCP</name> <description>MCP</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MCFHP</name> <description>MCFHP</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACSR</name> <displayName>MACSR</displayName> <description>Ethernet MAC interrupt status register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>PMTS</name> <description>PMTS</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MMCS</name> <description>MMCS</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MMCRS</name> <description>MMCRS</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MMCTS</name> <description>MMCTS</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TSTS</name> <description>TSTS</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>MACIMR</name> <displayName>MACIMR</displayName> <description>Ethernet MAC interrupt mask register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PMTIM</name> <description>PMTIM</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSTIM</name> <description>TSTIM</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACA0HR</name> <displayName>MACA0HR</displayName> <description>Ethernet MAC address 0 high register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <resetValue>0x0010FFFF</resetValue> <fields> <field> <name>MACA0H</name> <description>MAC address0 high</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> <name>MO</name> <description>Always 1</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>MACA0LR</name> <displayName>MACA0LR</displayName> <description>Ethernet MAC address 0 low register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>MACA0L</name> <description>0</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MACA1HR</name> <displayName>MACA1HR</displayName> <description>Ethernet MAC address 1 high register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000FFFF</resetValue> <fields> <field> <name>MACA1H</name> <description>MACA1H</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>MBC</name> <description>MBC</description> <bitOffset>24</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>SA</name> <description>SA</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AE</name> <description>AE</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACA1LR</name> <displayName>MACA1LR</displayName> <description>Ethernet MAC address1 low register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>MACA1LR</name> <description>MACA1LR</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MACA2HR</name> <displayName>MACA2HR</displayName> <description>Ethernet MAC address 2 high register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000FFFF</resetValue> <fields> <field> <name>MAC2AH</name> <description>MAC2AH</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>MBC</name> <description>MBC</description> <bitOffset>24</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>SA</name> <description>SA</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AE</name> <description>AE</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACA2LR</name> <displayName>MACA2LR</displayName> <description>Ethernet MAC address 2 low register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>MACA2L</name> <description>MACA2L</description> <bitOffset>0</bitOffset> <bitWidth>31</bitWidth> </field> </fields> </register> <register> <name>MACA3HR</name> <displayName>MACA3HR</displayName> <description>Ethernet MAC address 3 high register</description> <addressOffset>0x58</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000FFFF</resetValue> <fields> <field> <name>MACA3H</name> <description>MACA3H</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>MBC</name> <description>MBC</description> <bitOffset>24</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>SA</name> <description>SA</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AE</name> <description>AE</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MACA3LR</name> <displayName>MACA3LR</displayName> <description>Ethernet MAC address 3 low register</description> <addressOffset>0x5C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>MBCA3L</name> <description>MBCA3L</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>Ethernet_MMC</name> <description>Ethernet: MAC management counters</description> <groupName>Ethernet</groupName> <baseAddress>0x40028100</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MMCCR</name> <displayName>MMCCR</displayName> <description>Ethernet MMC control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CR</name> <description>CR</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSR</name> <description>CSR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ROR</name> <description>ROR</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MCF</name> <description>MCF</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MCP</name> <description>MCP</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MCFHP</name> <description>MCFHP</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MMCRIR</name> <displayName>MMCRIR</displayName> <description>Ethernet MMC receive interrupt register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RFCES</name> <description>RFCES</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RFAES</name> <description>RFAES</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RGUFS</name> <description>RGUFS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MMCTIR</name> <displayName>MMCTIR</displayName> <description>Ethernet MMC transmit interrupt register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TGFSCS</name> <description>TGFSCS</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TGFMSCS</name> <description>TGFMSCS</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TGFS</name> <description>TGFS</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MMCRIMR</name> <displayName>MMCRIMR</displayName> <description>Ethernet MMC receive interrupt mask register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RFCEM</name> <description>RFCEM</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RFAEM</name> <description>RFAEM</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RGUFM</name> <description>RGUFM</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MMCTIMR</name> <displayName>MMCTIMR</displayName> <description>Ethernet MMC transmit interrupt mask register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TGFSCM</name> <description>TGFSCM</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TGFMSCM</name> <description>TGFMSCM</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TGFM</name> <description>TGFM</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MMCTGFSCCR</name> <displayName>MMCTGFSCCR</displayName> <description>Ethernet MMC transmitted good frames after a single collision counter</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TGFSCC</name> <description>TGFSCC</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MMCTGFMSCCR</name> <displayName>MMCTGFMSCCR</displayName> <description>Ethernet MMC transmitted good frames after more than a single collision</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TGFMSCC</name> <description>TGFMSCC</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MMCTGFCR</name> <displayName>MMCTGFCR</displayName> <description>Ethernet MMC transmitted good frames counter register</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TGFC</name> <description>HTL</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MMCRFCECR</name> <displayName>MMCRFCECR</displayName> <description>Ethernet MMC received frames with CRC error counter register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RFCFC</name> <description>RFCFC</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MMCRFAECR</name> <displayName>MMCRFAECR</displayName> <description>Ethernet MMC received frames with alignment error counter register</description> <addressOffset>0x98</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RFAEC</name> <description>RFAEC</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>MMCRGUFCR</name> <displayName>MMCRGUFCR</displayName> <description>MMC received good unicast frames counter register</description> <addressOffset>0xC4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RGUFC</name> <description>RGUFC</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>Ethernet_PTP</name> <description>Ethernet: Precision time protocol</description> <groupName>Ethernet</groupName> <baseAddress>0x40028700</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>PTPTSCR</name> <displayName>PTPTSCR</displayName> <description>Ethernet PTP time stamp control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00002000</resetValue> <fields> <field> <name>TSE</name> <description>TSE</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSFCU</name> <description>TSFCU</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSPTPPSV2E</name> <description>TSPTPPSV2E</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSPTPOEFE</name> <description>TSSPTPOEFE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSIPV6FE</name> <description>TSSIPV6FE</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSIPV4FE</name> <description>TSSIPV4FE</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSEME</name> <description>TSSEME</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSMRME</name> <description>TSSMRME</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSCNT</name> <description>TSCNT</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TSPFFMAE</name> <description>TSPFFMAE</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSTI</name> <description>TSSTI</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSTU</name> <description>TSSTU</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSITE</name> <description>TSITE</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TTSARU</name> <description>TTSARU</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSARFE</name> <description>TSSARFE</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSSSR</name> <description>TSSSR</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PTPSSIR</name> <displayName>PTPSSIR</displayName> <description>Ethernet PTP subsecond increment register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STSSI</name> <description>STSSI</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>PTPTSHR</name> <displayName>PTPTSHR</displayName> <description>Ethernet PTP time stamp high register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STS</name> <description>STS</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>PTPTSLR</name> <displayName>PTPTSLR</displayName> <description>Ethernet PTP time stamp low register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STSS</name> <description>STSS</description> <bitOffset>0</bitOffset> <bitWidth>31</bitWidth> </field> <field> <name>STPNS</name> <description>STPNS</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PTPTSHUR</name> <displayName>PTPTSHUR</displayName> <description>Ethernet PTP time stamp high update register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TSUS</name> <description>TSUS</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>PTPTSLUR</name> <displayName>PTPTSLUR</displayName> <description>Ethernet PTP time stamp low update register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TSUSS</name> <description>TSUSS</description> <bitOffset>0</bitOffset> <bitWidth>31</bitWidth> </field> <field> <name>TSUPNS</name> <description>TSUPNS</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PTPTSAR</name> <displayName>PTPTSAR</displayName> <description>Ethernet PTP time stamp addend register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TSA</name> <description>TSA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>PTPTTHR</name> <displayName>PTPTTHR</displayName> <description>Ethernet PTP target time high register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TTSH</name> <description>0</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>PTPTTLR</name> <displayName>PTPTTLR</displayName> <description>Ethernet PTP target time low register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TTSL</name> <description>TTSL</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>PTPTSSR</name> <displayName>PTPTSSR</displayName> <description>Ethernet PTP time stamp status register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TSSO</name> <description>TSSO</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSTTR</name> <description>TSTTR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PTPPPSCR</name> <displayName>PTPPPSCR</displayName> <description>Ethernet PTP PPS control register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TSSO</name> <description>TSSO</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSTTR</name> <description>TSTTR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>Ethernet_DMA</name> <description>Ethernet: DMA controller operation</description> <groupName>Ethernet</groupName> <baseAddress>0x40029000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DMABMR</name> <displayName>DMABMR</displayName> <description>Ethernet DMA bus mode register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00002101</resetValue> <fields> <field> <name>SR</name> <description>SR</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DA</name> <description>DA</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DSL</name> <description>DSL</description> <bitOffset>2</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>EDFE</name> <description>EDFE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PBL</name> <description>PBL</description> <bitOffset>8</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>RTPR</name> <description>RTPR</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FB</name> <description>FB</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RDP</name> <description>RDP</description> <bitOffset>17</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>USP</name> <description>USP</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPM</name> <description>FPM</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AAB</name> <description>AAB</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MB</name> <description>MB</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DMATPDR</name> <displayName>DMATPDR</displayName> <description>Ethernet DMA transmit poll demand register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TPD</name> <description>TPD</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMARPDR</name> <displayName>DMARPDR</displayName> <description>EHERNET DMA receive poll demand register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RPD</name> <description>RPD</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMARDLAR</name> <displayName>DMARDLAR</displayName> <description>Ethernet DMA receive descriptor list address register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SRL</name> <description>SRL</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMATDLAR</name> <displayName>DMATDLAR</displayName> <description>Ethernet DMA transmit descriptor list address register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STL</name> <description>STL</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMASR</name> <displayName>DMASR</displayName> <description>Ethernet DMA status register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>TS</name> <description>TS</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TPSS</name> <description>TPSS</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TBUS</name> <description>TBUS</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TJTS</name> <description>TJTS</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ROS</name> <description>ROS</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TUS</name> <description>TUS</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RS</name> <description>RS</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RBUS</name> <description>RBUS</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RPSS</name> <description>RPSS</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PWTS</name> <description>PWTS</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ETS</name> <description>ETS</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FBES</name> <description>FBES</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ERS</name> <description>ERS</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>AIS</name> <description>AIS</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NIS</name> <description>NIS</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RPS</name> <description>RPS</description> <bitOffset>17</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>TPS</name> <description>TPS</description> <bitOffset>20</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>EBS</name> <description>EBS</description> <bitOffset>23</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>MMCS</name> <description>MMCS</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PMTS</name> <description>PMTS</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TSTS</name> <description>TSTS</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DMAOMR</name> <displayName>DMAOMR</displayName> <description>Ethernet DMA operation mode register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SR</name> <description>SR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OSF</name> <description>OSF</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTC</name> <description>RTC</description> <bitOffset>3</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FUGF</name> <description>FUGF</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FEF</name> <description>FEF</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ST</name> <description>ST</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TTC</name> <description>TTC</description> <bitOffset>14</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>FTF</name> <description>FTF</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TSF</name> <description>TSF</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DFRF</name> <description>DFRF</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RSF</name> <description>RSF</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTCEFD</name> <description>DTCEFD</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DMAIER</name> <displayName>DMAIER</displayName> <description>Ethernet DMA interrupt enable register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIE</name> <description>TIE</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TPSIE</name> <description>TPSIE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TBUIE</name> <description>TBUIE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TJTIE</name> <description>TJTIE</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ROIE</name> <description>ROIE</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TUIE</name> <description>TUIE</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RIE</name> <description>RIE</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RBUIE</name> <description>RBUIE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPSIE</name> <description>RPSIE</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RWTIE</name> <description>RWTIE</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ETIE</name> <description>ETIE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBEIE</name> <description>FBEIE</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERIE</name> <description>ERIE</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AISE</name> <description>AISE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NISE</name> <description>NISE</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DMAMFBOCR</name> <displayName>DMAMFBOCR</displayName> <description>Ethernet DMA missed frame and buffer overflow counter register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MFC</name> <description>MFC</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>OMFC</name> <description>OMFC</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MFA</name> <description>MFA</description> <bitOffset>17</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>OFOC</name> <description>OFOC</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DMARSWTR</name> <displayName>DMARSWTR</displayName> <description>Ethernet DMA receive status watchdog timer register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RSWTC</name> <description>RSWTC</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DMACHTDR</name> <displayName>DMACHTDR</displayName> <description>Ethernet DMA current host transmit descriptor register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HTDAP</name> <description>HTDAP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMACHRDR</name> <displayName>DMACHRDR</displayName> <description>Ethernet DMA current host receive descriptor register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HRDAP</name> <description>HRDAP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMACHTBAR</name> <displayName>DMACHTBAR</displayName> <description>Ethernet DMA current host transmit buffer address register</description> <addressOffset>0x50</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HTBAP</name> <description>HTBAP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMACHRBAR</name> <displayName>DMACHRBAR</displayName> <description>Ethernet DMA current host receive buffer address register</description> <addressOffset>0x54</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HRBAP</name> <description>HRBAP</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>CRC</name> <description>Cryptographic processor</description> <groupName>CRC</groupName> <baseAddress>0x40023000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>DR</name> <description>Data Register</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IDR</name> <displayName>IDR</displayName> <description>Independent Data register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IDR</name> <description>Independent Data register</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CR</name> <description>Control regidter</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_FS_GLOBAL</name> <description>USB on the go full speed</description> <groupName>USB_OTG_FS</groupName> <baseAddress>0x50000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>OTG_FS_WKUP</name> <description>USB On-The-Go FS Wakeup through EXTI line interrupt</description> <value>42</value> </interrupt> <interrupt> <name>OTG_FS</name> <description>USB On The Go FS global interrupt</description> <value>67</value> </interrupt> <registers> <register> <name>FS_GOTGCTL</name> <displayName>FS_GOTGCTL</displayName> <description>OTG_FS control and status register (OTG_FS_GOTGCTL)</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000800</resetValue> <fields> <field> <name>SRQSCS</name> <description>Session request success</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SRQ</name> <description>Session request</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HNGSCS</name> <description>Host negotiation success</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HNPRQ</name> <description>HNP request</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSHNPEN</name> <description>Host set HNP enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DHNPEN</name> <description>Device HNP enabled</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CIDSTS</name> <description>Connector ID status</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>DBCT</name> <description>Long/short debounce time</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ASVLD</name> <description>A-session valid</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BSVLD</name> <description>B-session valid</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>FS_GOTGINT</name> <displayName>FS_GOTGINT</displayName> <description>OTG_FS interrupt register (OTG_FS_GOTGINT)</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SEDET</name> <description>Session end detected</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRSSCHG</name> <description>Session request success status change</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HNSSCHG</name> <description>Host negotiation success status change</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HNGDET</name> <description>Host negotiation detected</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADTOCHG</name> <description>A-device timeout change</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBCDNE</name> <description>Debounce done</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_GAHBCFG</name> <displayName>FS_GAHBCFG</displayName> <description>OTG_FS AHB configuration register (OTG_FS_GAHBCFG)</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>GINT</name> <description>Global interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFELVL</name> <description>TxFIFO empty level</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PTXFELVL</name> <description>Periodic TxFIFO empty level</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_GUSBCFG</name> <displayName>FS_GUSBCFG</displayName> <description>OTG_FS USB configuration register (OTG_FS_GUSBCFG)</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000A00</resetValue> <fields> <field> <name>TOCAL</name> <description>FS timeout calibration</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>PHYSEL</name> <description>Full Speed serial transceiver select</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SRPCAP</name> <description>SRP-capable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HNPCAP</name> <description>HNP-capable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TRDT</name> <description>USB turnaround time</description> <bitOffset>10</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>FHMOD</name> <description>Force host mode</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FDMOD</name> <description>Force device mode</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CTXPKT</name> <description>Corrupt Tx packet</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>FS_GRSTCTL</name> <displayName>FS_GRSTCTL</displayName> <description>OTG_FS reset register (OTG_FS_GRSTCTL)</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <resetValue>0x20000000</resetValue> <fields> <field> <name>CSRST</name> <description>Core soft reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSRST</name> <description>HCLK soft reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FCRST</name> <description>Host frame counter reset</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXFFLSH</name> <description>RxFIFO flush</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFFLSH</name> <description>TxFIFO flush</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>6</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> <name>AHBIDL</name> <description>AHB master idle</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>FS_GINTSTS</name> <displayName>FS_GINTSTS</displayName> <description>OTG_FS core interrupt register (OTG_FS_GINTSTS)</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <resetValue>0x04000020</resetValue> <fields> <field> <name>CMOD</name> <description>Current mode of operation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MMIS</name> <description>Mode mismatch interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OTGINT</name> <description>OTG interrupt</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SOF</name> <description>Start of frame</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXFLVL</name> <description>RxFIFO non-empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NPTXFE</name> <description>Non-periodic TxFIFO empty</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>GINAKEFF</name> <description>Global IN non-periodic NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>GOUTNAKEFF</name> <description>Global OUT NAK effective</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ESUSP</name> <description>Early suspend</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBSUSP</name> <description>USB suspend</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBRST</name> <description>USB reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ENUMDNE</name> <description>Enumeration done</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ISOODRP</name> <description>Isochronous OUT packet dropped interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EOPF</name> <description>End of periodic frame interrupt</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IEPINT</name> <description>IN endpoint interrupt</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>OEPINT</name> <description>OUT endpoint interrupt</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>IISOIXFR</name> <description>Incomplete isochronous IN transfer</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IPXFR_INCOMPISOOUT</name> <description>Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HPRTINT</name> <description>Host port interrupt</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HCINT</name> <description>Host channels interrupt</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PTXFE</name> <description>Periodic TxFIFO empty</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CIDSCHG</name> <description>Connector ID status change</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DISCINT</name> <description>Disconnect detected interrupt</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SRQINT</name> <description>Session request/new session detected interrupt</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WKUPINT</name> <description>Resume/remote wakeup detected interrupt</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>FS_GINTMSK</name> <displayName>FS_GINTMSK</displayName> <description>OTG_FS interrupt mask register (OTG_FS_GINTMSK)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>MMISM</name> <description>Mode mismatch interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OTGINT</name> <description>OTG interrupt mask</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SOFM</name> <description>Start of frame mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXFLVLM</name> <description>Receive FIFO non-empty mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NPTXFEM</name> <description>Non-periodic TxFIFO empty mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>GINAKEFFM</name> <description>Global non-periodic IN NAK effective mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>GONAKEFFM</name> <description>Global OUT NAK effective mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ESUSPM</name> <description>Early suspend mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBSUSPM</name> <description>USB suspend mask</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBRST</name> <description>USB reset mask</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ENUMDNEM</name> <description>Enumeration done mask</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ISOODRPM</name> <description>Isochronous OUT packet dropped interrupt mask</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EOPFM</name> <description>End of periodic frame interrupt mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPMISM</name> <description>Endpoint mismatch interrupt mask</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IEPINT</name> <description>IN endpoints interrupt mask</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OEPINT</name> <description>OUT endpoints interrupt mask</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IISOIXFRM</name> <description>Incomplete isochronous IN transfer mask</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IPXFRM_IISOOXFRM</name> <description>Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PRTIM</name> <description>Host port interrupt mask</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HCIM</name> <description>Host channels interrupt mask</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PTXFEM</name> <description>Periodic TxFIFO empty mask</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CIDSCHGM</name> <description>Connector ID status change mask</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DISCINT</name> <description>Disconnect detected interrupt mask</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SRQIM</name> <description>Session request/new session detected interrupt mask</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WUIM</name> <description>Resume/remote wakeup detected interrupt mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>FS_GRXSTSR_Device</name> <displayName>FS_GRXSTSR_Device</displayName> <description>OTG_FS Receive status debug read(Device mode)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BCNT</name> <description>Byte count</description> <bitOffset>4</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>15</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTSTS</name> <description>Packet status</description> <bitOffset>17</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>FRMNUM</name> <description>Frame number</description> <bitOffset>21</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>FS_GRXSTSR_Host</name> <displayName>FS_GRXSTSR_Host</displayName> <description>OTG_FS Receive status debug read(Host mode)</description> <alternateRegister>FS_GRXSTSR_Device</alternateRegister> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BCNT</name> <description>Byte count</description> <bitOffset>4</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>15</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTSTS</name> <description>Packet status</description> <bitOffset>17</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>FRMNUM</name> <description>Frame number</description> <bitOffset>21</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>FS_GRXFSIZ</name> <displayName>FS_GRXFSIZ</displayName> <description>OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000200</resetValue> <fields> <field> <name>RXFD</name> <description>RxFIFO depth</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_GNPTXFSIZ_Device</name> <displayName>FS_GNPTXFSIZ_Device</displayName> <description>OTG_FS non-periodic transmit FIFO size register (Device mode)</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000200</resetValue> <fields> <field> <name>TX0FSA</name> <description>Endpoint 0 transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>TX0FD</name> <description>Endpoint 0 TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_GNPTXFSIZ_Host</name> <displayName>FS_GNPTXFSIZ_Host</displayName> <description>OTG_FS non-periodic transmit FIFO size register (Host mode)</description> <alternateRegister>FS_GNPTXFSIZ_Device</alternateRegister> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000200</resetValue> <fields> <field> <name>NPTXFSA</name> <description>Non-periodic transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>NPTXFD</name> <description>Non-periodic TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_GNPTXSTS</name> <displayName>FS_GNPTXSTS</displayName> <description>OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00080200</resetValue> <fields> <field> <name>NPTXFSAV</name> <description>Non-periodic TxFIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>NPTQXSAV</name> <description>Non-periodic transmit request queue space available</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>NPTXQTOP</name> <description>Top of the non-periodic transmit request queue</description> <bitOffset>24</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>FS_GCCFG</name> <displayName>FS_GCCFG</displayName> <description>OTG_FS general core configuration register (OTG_FS_GCCFG)</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PWRDWN</name> <description>Power down</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBUSASEN</name> <description>Enable the VBUS sensing device</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBUSBSEN</name> <description>Enable the VBUS sensing device</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SOFOUTEN</name> <description>SOF output enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_CID</name> <displayName>FS_CID</displayName> <description>core ID register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00001000</resetValue> <fields> <field> <name>PRODUCT_ID</name> <description>Product ID field</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>FS_HPTXFSIZ</name> <displayName>FS_HPTXFSIZ</displayName> <description>OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x02000600</resetValue> <fields> <field> <name>PTXSA</name> <description>Host periodic TxFIFO start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>PTXFSIZ</name> <description>Host periodic TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_DIEPTXF1</name> <displayName>FS_DIEPTXF1</displayName> <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFO2 transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_DIEPTXF2</name> <displayName>FS_DIEPTXF2</displayName> <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFO3 transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_DIEPTXF3</name> <displayName>FS_DIEPTXF3</displayName> <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)</description> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFO4 transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_FS_HOST</name> <description>USB on the go full speed</description> <groupName>USB_OTG_FS</groupName> <baseAddress>0x50000400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>FS_HCFG</name> <displayName>FS_HCFG</displayName> <description>OTG_FS host configuration register (OTG_FS_HCFG)</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>FSLSPCS</name> <description>FS/LS PHY clock select</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>FSLSS</name> <description>FS- and LS-only support</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>HFIR</name> <displayName>HFIR</displayName> <description>OTG_FS Host frame interval register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000EA60</resetValue> <fields> <field> <name>FRIVL</name> <description>Frame interval</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_HFNUM</name> <displayName>FS_HFNUM</displayName> <description>OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00003FFF</resetValue> <fields> <field> <name>FRNUM</name> <description>Frame number</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>FTREM</name> <description>Frame time remaining</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_HPTXSTS</name> <displayName>FS_HPTXSTS</displayName> <description>OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <resetValue>0x00080100</resetValue> <fields> <field> <name>PTXFSAVL</name> <description>Periodic transmit data FIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> <name>PTXQSAV</name> <description>Periodic transmit request queue space available</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> <field> <name>PTXQTOP</name> <description>Top of the periodic transmit request queue</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>HAINT</name> <displayName>HAINT</displayName> <description>OTG_FS Host all channels interrupt register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HAINT</name> <description>Channel interrupts</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>HAINTMSK</name> <displayName>HAINTMSK</displayName> <description>OTG_FS host all channels interrupt mask register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HAINTM</name> <description>Channel interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_HPRT</name> <displayName>FS_HPRT</displayName> <description>OTG_FS host port control and status register (OTG_FS_HPRT)</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>PCSTS</name> <description>Port connect status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PCDET</name> <description>Port connect detected</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PENA</name> <description>Port enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PENCHNG</name> <description>Port enable/disable change</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>POCA</name> <description>Port overcurrent active</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>POCCHNG</name> <description>Port overcurrent change</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PRES</name> <description>Port resume</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PSUSP</name> <description>Port suspend</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PRST</name> <description>Port reset</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PLSTS</name> <description>Port line status</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>PPWR</name> <description>Port power</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PTCTL</name> <description>Port test control</description> <bitOffset>13</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>PSPD</name> <description>Port speed</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>FS_HCCHAR0</name> <displayName>FS_HCCHAR0</displayName> <description>OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCCHAR1</name> <displayName>FS_HCCHAR1</displayName> <description>OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)</description> <addressOffset>0x120</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCCHAR2</name> <displayName>FS_HCCHAR2</displayName> <description>OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)</description> <addressOffset>0x140</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCCHAR3</name> <displayName>FS_HCCHAR3</displayName> <description>OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)</description> <addressOffset>0x160</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCCHAR4</name> <displayName>FS_HCCHAR4</displayName> <description>OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)</description> <addressOffset>0x180</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCCHAR5</name> <displayName>FS_HCCHAR5</displayName> <description>OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)</description> <addressOffset>0x1A0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCCHAR6</name> <displayName>FS_HCCHAR6</displayName> <description>OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)</description> <addressOffset>0x1C0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCCHAR7</name> <displayName>FS_HCCHAR7</displayName> <description>OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)</description> <addressOffset>0x1E0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MCNT</name> <description>Multicount</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT0</name> <displayName>FS_HCINT0</displayName> <description>OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT1</name> <displayName>FS_HCINT1</displayName> <description>OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)</description> <addressOffset>0x128</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT2</name> <displayName>FS_HCINT2</displayName> <description>OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)</description> <addressOffset>0x148</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT3</name> <displayName>FS_HCINT3</displayName> <description>OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)</description> <addressOffset>0x168</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT4</name> <displayName>FS_HCINT4</displayName> <description>OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)</description> <addressOffset>0x188</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT5</name> <displayName>FS_HCINT5</displayName> <description>OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)</description> <addressOffset>0x1A8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT6</name> <displayName>FS_HCINT6</displayName> <description>OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)</description> <addressOffset>0x1C8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINT7</name> <displayName>FS_HCINT7</displayName> <description>OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)</description> <addressOffset>0x1E8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK0</name> <displayName>FS_HCINTMSK0</displayName> <description>OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)</description> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK1</name> <displayName>FS_HCINTMSK1</displayName> <description>OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)</description> <addressOffset>0x12C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK2</name> <displayName>FS_HCINTMSK2</displayName> <description>OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)</description> <addressOffset>0x14C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK3</name> <displayName>FS_HCINTMSK3</displayName> <description>OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)</description> <addressOffset>0x16C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK4</name> <displayName>FS_HCINTMSK4</displayName> <description>OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)</description> <addressOffset>0x18C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK5</name> <displayName>FS_HCINTMSK5</displayName> <description>OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)</description> <addressOffset>0x1AC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK6</name> <displayName>FS_HCINTMSK6</displayName> <description>OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)</description> <addressOffset>0x1CC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCINTMSK7</name> <displayName>FS_HCINTMSK7</displayName> <description>OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)</description> <addressOffset>0x1EC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ0</name> <displayName>FS_HCTSIZ0</displayName> <description>OTG_FS host channel-0 transfer size register</description> <addressOffset>0x110</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ1</name> <displayName>FS_HCTSIZ1</displayName> <description>OTG_FS host channel-1 transfer size register</description> <addressOffset>0x130</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ2</name> <displayName>FS_HCTSIZ2</displayName> <description>OTG_FS host channel-2 transfer size register</description> <addressOffset>0x150</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ3</name> <displayName>FS_HCTSIZ3</displayName> <description>OTG_FS host channel-3 transfer size register</description> <addressOffset>0x170</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ4</name> <displayName>FS_HCTSIZ4</displayName> <description>OTG_FS host channel-x transfer size register</description> <addressOffset>0x190</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ5</name> <displayName>FS_HCTSIZ5</displayName> <description>OTG_FS host channel-5 transfer size register</description> <addressOffset>0x1B0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ6</name> <displayName>FS_HCTSIZ6</displayName> <description>OTG_FS host channel-6 transfer size register</description> <addressOffset>0x1D0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_HCTSIZ7</name> <displayName>FS_HCTSIZ7</displayName> <description>OTG_FS host channel-7 transfer size register</description> <addressOffset>0x1F0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_FS_DEVICE</name> <description>USB on the go full speed</description> <groupName>USB_OTG_FS</groupName> <baseAddress>0x50000800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>FS_DCFG</name> <displayName>FS_DCFG</displayName> <description>OTG_FS device configuration register (OTG_FS_DCFG)</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x02200000</resetValue> <fields> <field> <name>DSPD</name> <description>Device speed</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NZLSOHSK</name> <description>Non-zero-length status OUT handshake</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>4</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PFIVL</name> <description>Periodic frame interval</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>FS_DCTL</name> <displayName>FS_DCTL</displayName> <description>OTG_FS device control register (OTG_FS_DCTL)</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>RWUSIG</name> <description>Remote wakeup signaling</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SDIS</name> <description>Soft disconnect</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>GINSTS</name> <description>Global IN NAK status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>GONSTS</name> <description>Global OUT NAK status</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TCTL</name> <description>Test control</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>SGINAK</name> <description>Set global IN NAK</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CGINAK</name> <description>Clear global IN NAK</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SGONAK</name> <description>Set global OUT NAK</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CGONAK</name> <description>Clear global OUT NAK</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>POPRGDNE</name> <description>Power-on programming done</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>FS_DSTS</name> <displayName>FS_DSTS</displayName> <description>OTG_FS device status register (OTG_FS_DSTS)</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000010</resetValue> <fields> <field> <name>SUSPSTS</name> <description>Suspend status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENUMSPD</name> <description>Enumerated speed</description> <bitOffset>1</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>EERR</name> <description>Erratic error</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FNSOF</name> <description>Frame number of the received SOF</description> <bitOffset>8</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>FS_DIEPMSK</name> <displayName>FS_DIEPMSK</displayName> <description>OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDM</name> <description>Endpoint disabled interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TOM</name> <description>Timeout condition mask (Non-isochronous endpoints)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITTXFEMSK</name> <description>IN token received when TxFIFO empty mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNMM</name> <description>IN token received with EP mismatch mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNEM</name> <description>IN endpoint NAK effective mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_DOEPMSK</name> <displayName>FS_DOEPMSK</displayName> <description>OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDM</name> <description>Endpoint disabled interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUPM</name> <description>SETUP phase done mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDM</name> <description>OUT token received when endpoint disabled mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS_DAINT</name> <displayName>FS_DAINT</displayName> <description>OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IEPINT</name> <description>IN endpoint interrupt bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>OEPINT</name> <description>OUT endpoint interrupt bits</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_DAINTMSK</name> <displayName>FS_DAINTMSK</displayName> <description>OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IEPM</name> <description>IN EP interrupt mask bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>OEPINT</name> <description>OUT endpoint interrupt bits</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DVBUSDIS</name> <displayName>DVBUSDIS</displayName> <description>OTG_FS device VBUS discharge time register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000017D7</resetValue> <fields> <field> <name>VBUSDT</name> <description>Device VBUS discharge time</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DVBUSPULSE</name> <displayName>DVBUSPULSE</displayName> <description>OTG_FS device VBUS pulsing time register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000005B8</resetValue> <fields> <field> <name>DVBUSP</name> <description>Device VBUS pulsing time</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>DIEPEMPMSK</name> <displayName>DIEPEMPMSK</displayName> <description>OTG_FS device IN endpoint FIFO empty interrupt mask register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INEPTXFEM</name> <description>IN EP Tx FIFO empty interrupt mask bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>FS_DIEPCTL0</name> <displayName>FS_DIEPCTL0</displayName> <description>OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>STALL</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DIEPCTL1</name> <displayName>DIEPCTL1</displayName> <description>OTG device endpoint-1 control register</description> <addressOffset>0x120</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPENA</name> <description>EPENA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDIS</name> <description>EPDIS</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SODDFRM_SD1PID</name> <description>SODDFRM/SD1PID</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>SD0PID/SEVNFRM</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>SNAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNAK</name> <description>CNAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>TXFNUM</name> <description>TXFNUM</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>Stall</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPTYP</name> <description>EPTYP</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>NAKSTS</name> <description>NAKSTS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EONUM_DPID</name> <description>EONUM/DPID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USBAEP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MPSIZ</name> <description>MPSIZ</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIEPCTL2</name> <displayName>DIEPCTL2</displayName> <description>OTG device endpoint-2 control register</description> <addressOffset>0x140</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPENA</name> <description>EPENA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDIS</name> <description>EPDIS</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SODDFRM</name> <description>SODDFRM</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>SD0PID/SEVNFRM</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>SNAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNAK</name> <description>CNAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>TXFNUM</name> <description>TXFNUM</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>Stall</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPTYP</name> <description>EPTYP</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>NAKSTS</name> <description>NAKSTS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EONUM_DPID</name> <description>EONUM/DPID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USBAEP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MPSIZ</name> <description>MPSIZ</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIEPCTL3</name> <displayName>DIEPCTL3</displayName> <description>OTG device endpoint-3 control register</description> <addressOffset>0x160</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPENA</name> <description>EPENA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDIS</name> <description>EPDIS</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SODDFRM</name> <description>SODDFRM</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>SD0PID/SEVNFRM</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>SNAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNAK</name> <description>CNAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>TXFNUM</name> <description>TXFNUM</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>Stall</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPTYP</name> <description>EPTYP</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>NAKSTS</name> <description>NAKSTS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EONUM_DPID</name> <description>EONUM/DPID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USBAEP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MPSIZ</name> <description>MPSIZ</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DOEPCTL0</name> <displayName>DOEPCTL0</displayName> <description>device endpoint-0 control register</description> <addressOffset>0x300</addressOffset> <size>0x20</size> <resetValue>0x00008000</resetValue> <fields> <field> <name>EPENA</name> <description>EPENA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>EPDIS</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SNAK</name> <description>SNAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNAK</name> <description>CNAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>Stall</name> <description>Stall</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SNPM</name> <description>SNPM</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPTYP</name> <description>EPTYP</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAKSTS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USBAEP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MPSIZ</name> <description>MPSIZ</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>DOEPCTL1</name> <displayName>DOEPCTL1</displayName> <description>device endpoint-1 control register</description> <addressOffset>0x320</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPENA</name> <description>EPENA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDIS</name> <description>EPDIS</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SODDFRM</name> <description>SODDFRM</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>SD0PID/SEVNFRM</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>SNAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNAK</name> <description>CNAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>Stall</name> <description>Stall</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SNPM</name> <description>SNPM</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPTYP</name> <description>EPTYP</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>NAKSTS</name> <description>NAKSTS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EONUM_DPID</name> <description>EONUM/DPID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USBAEP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MPSIZ</name> <description>MPSIZ</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DOEPCTL2</name> <displayName>DOEPCTL2</displayName> <description>device endpoint-2 control register</description> <addressOffset>0x340</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPENA</name> <description>EPENA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDIS</name> <description>EPDIS</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SODDFRM</name> <description>SODDFRM</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>SD0PID/SEVNFRM</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>SNAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNAK</name> <description>CNAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>Stall</name> <description>Stall</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SNPM</name> <description>SNPM</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPTYP</name> <description>EPTYP</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>NAKSTS</name> <description>NAKSTS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EONUM_DPID</name> <description>EONUM/DPID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USBAEP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MPSIZ</name> <description>MPSIZ</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DOEPCTL3</name> <displayName>DOEPCTL3</displayName> <description>device endpoint-3 control register</description> <addressOffset>0x360</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EPENA</name> <description>EPENA</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDIS</name> <description>EPDIS</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SODDFRM</name> <description>SODDFRM</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>SD0PID/SEVNFRM</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>SNAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CNAK</name> <description>CNAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>Stall</name> <description>Stall</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SNPM</name> <description>SNPM</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPTYP</name> <description>EPTYP</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>NAKSTS</name> <description>NAKSTS</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EONUM_DPID</name> <description>EONUM/DPID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USBAEP</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>MPSIZ</name> <description>MPSIZ</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIEPINT0</name> <displayName>DIEPINT0</displayName> <description>device endpoint-x interrupt register</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <resetValue>0x00000080</resetValue> <fields> <field> <name>TXFE</name> <description>TXFE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INEPNE</name> <description>INEPNE</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>ITTXFE</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>TOC</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIEPINT1</name> <displayName>DIEPINT1</displayName> <description>device endpoint-1 interrupt register</description> <addressOffset>0x128</addressOffset> <size>0x20</size> <resetValue>0x00000080</resetValue> <fields> <field> <name>TXFE</name> <description>TXFE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INEPNE</name> <description>INEPNE</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>ITTXFE</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>TOC</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIEPINT2</name> <displayName>DIEPINT2</displayName> <description>device endpoint-2 interrupt register</description> <addressOffset>0x148</addressOffset> <size>0x20</size> <resetValue>0x00000080</resetValue> <fields> <field> <name>TXFE</name> <description>TXFE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INEPNE</name> <description>INEPNE</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>ITTXFE</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>TOC</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DIEPINT3</name> <displayName>DIEPINT3</displayName> <description>device endpoint-3 interrupt register</description> <addressOffset>0x168</addressOffset> <size>0x20</size> <resetValue>0x00000080</resetValue> <fields> <field> <name>TXFE</name> <description>TXFE</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INEPNE</name> <description>INEPNE</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>ITTXFE</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>TOC</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>DOEPINT0</name> <displayName>DOEPINT0</displayName> <description>device endpoint-0 interrupt register</description> <addressOffset>0x308</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000080</resetValue> <fields> <field> <name>B2BSTUP</name> <description>B2BSTUP</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OTEPDIS</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>STUP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DOEPINT1</name> <displayName>DOEPINT1</displayName> <description>device endpoint-1 interrupt register</description> <addressOffset>0x328</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000080</resetValue> <fields> <field> <name>B2BSTUP</name> <description>B2BSTUP</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OTEPDIS</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>STUP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DOEPINT2</name> <displayName>DOEPINT2</displayName> <description>device endpoint-2 interrupt register</description> <addressOffset>0x348</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000080</resetValue> <fields> <field> <name>B2BSTUP</name> <description>B2BSTUP</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OTEPDIS</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>STUP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DOEPINT3</name> <displayName>DOEPINT3</displayName> <description>device endpoint-3 interrupt register</description> <addressOffset>0x368</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000080</resetValue> <fields> <field> <name>B2BSTUP</name> <description>B2BSTUP</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OTEPDIS</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>STUP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>EPDISD</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>XFRC</name> <description>XFRC</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DIEPTSIZ0</name> <displayName>DIEPTSIZ0</displayName> <description>device endpoint-0 transfer size register</description> <addressOffset>0x110</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>DOEPTSIZ0</name> <displayName>DOEPTSIZ0</displayName> <description>device OUT endpoint-0 transfer size register</description> <addressOffset>0x310</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STUPCNT</name> <description>SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>DIEPTSIZ1</name> <displayName>DIEPTSIZ1</displayName> <description>device endpoint-1 transfer size register</description> <addressOffset>0x130</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>DIEPTSIZ2</name> <displayName>DIEPTSIZ2</displayName> <description>device endpoint-2 transfer size register</description> <addressOffset>0x150</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>DIEPTSIZ3</name> <displayName>DIEPTSIZ3</displayName> <description>device endpoint-3 transfer size register</description> <addressOffset>0x170</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>DTXFSTS0</name> <displayName>DTXFSTS0</displayName> <description>OTG_FS device IN endpoint transmit FIFO status register</description> <addressOffset>0x118</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DTXFSTS1</name> <displayName>DTXFSTS1</displayName> <description>OTG_FS device IN endpoint transmit FIFO status register</description> <addressOffset>0x138</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DTXFSTS2</name> <displayName>DTXFSTS2</displayName> <description>OTG_FS device IN endpoint transmit FIFO status register</description> <addressOffset>0x158</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DTXFSTS3</name> <displayName>DTXFSTS3</displayName> <description>OTG_FS device IN endpoint transmit FIFO status register</description> <addressOffset>0x178</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DOEPTSIZ1</name> <displayName>DOEPTSIZ1</displayName> <description>device OUT endpoint-1 transfer size register</description> <addressOffset>0x330</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RXDPID_STUPCNT</name> <description>Received data PID/SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>DOEPTSIZ2</name> <displayName>DOEPTSIZ2</displayName> <description>device OUT endpoint-2 transfer size register</description> <addressOffset>0x350</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RXDPID_STUPCNT</name> <description>Received data PID/SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> <register> <name>DOEPTSIZ3</name> <displayName>DOEPTSIZ3</displayName> <description>device OUT endpoint-3 transfer size register</description> <addressOffset>0x370</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RXDPID_STUPCNT</name> <description>Received data PID/SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_FS_PWRCLK</name> <description>USB on the go full speed</description> <groupName>USB_OTG_FS</groupName> <baseAddress>0x50000E00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>FS_PCGCCTL</name> <displayName>FS_PCGCCTL</displayName> <description>OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STPPCLK</name> <description>Stop PHY clock</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GATEHCLK</name> <description>Gate HCLK</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PHYSUSP</name> <description>PHY Suspended</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>CAN1</name> <description>Controller area network</description> <groupName>CAN</groupName> <baseAddress>0x40006400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>CAN1_TX</name> <description>CAN1 TX interrupts</description> <value>19</value> </interrupt> <interrupt> <name>CAN1_RX0</name> <description>CAN1 RX0 interrupts</description> <value>20</value> </interrupt> <interrupt> <name>CAN1_RX1</name> <description>CAN1 RX1 interrupts</description> <value>21</value> </interrupt> <interrupt> <name>CAN1_SCE</name> <description>CAN1 SCE interrupt</description> <value>22</value> </interrupt> <registers> <register> <name>MCR</name> <displayName>MCR</displayName> <description>master control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00010002</resetValue> <fields> <field> <name>DBF</name> <description>DBF</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RESET</name> <description>RESET</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TTCM</name> <description>TTCM</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ABOM</name> <description>ABOM</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AWUM</name> <description>AWUM</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NART</name> <description>NART</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RFLM</name> <description>RFLM</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFP</name> <description>TXFP</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SLEEP</name> <description>SLEEP</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INRQ</name> <description>INRQ</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MSR</name> <displayName>MSR</displayName> <description>master status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <resetValue>0x00000C02</resetValue> <fields> <field> <name>RX</name> <description>RX</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SAMP</name> <description>SAMP</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RXM</name> <description>RXM</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXM</name> <description>TXM</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SLAKI</name> <description>SLAKI</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WKUI</name> <description>WKUI</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ERRI</name> <description>ERRI</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SLAK</name> <description>SLAK</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>INAK</name> <description>INAK</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>TSR</name> <displayName>TSR</displayName> <description>transmit status register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <resetValue>0x1C000000</resetValue> <fields> <field> <name>LOW2</name> <description>Lowest priority flag for mailbox 2</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LOW1</name> <description>Lowest priority flag for mailbox 1</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>LOW0</name> <description>Lowest priority flag for mailbox 0</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TME2</name> <description>Lowest priority flag for mailbox 2</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TME1</name> <description>Lowest priority flag for mailbox 1</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TME0</name> <description>Lowest priority flag for mailbox 0</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CODE</name> <description>CODE</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>ABRQ2</name> <description>ABRQ2</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TERR2</name> <description>TERR2</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALST2</name> <description>ALST2</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXOK2</name> <description>TXOK2</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RQCP2</name> <description>RQCP2</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ABRQ1</name> <description>ABRQ1</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TERR1</name> <description>TERR1</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALST1</name> <description>ALST1</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXOK1</name> <description>TXOK1</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RQCP1</name> <description>RQCP1</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ABRQ0</name> <description>ABRQ0</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TERR0</name> <description>TERR0</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ALST0</name> <description>ALST0</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXOK0</name> <description>TXOK0</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RQCP0</name> <description>RQCP0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>RF0R</name> <displayName>RF0R</displayName> <description>receive FIFO 0 register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>RFOM0</name> <description>RFOM0</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FOVR0</name> <description>FOVR0</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FULL0</name> <description>FULL0</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FMP0</name> <description>FMP0</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>RF1R</name> <displayName>RF1R</displayName> <description>receive FIFO 1 register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>RFOM1</name> <description>RFOM1</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FOVR1</name> <description>FOVR1</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FULL1</name> <description>FULL1</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FMP1</name> <description>FMP1</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>IER</name> <displayName>IER</displayName> <description>interrupt enable register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SLKIE</name> <description>SLKIE</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WKUIE</name> <description>WKUIE</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>ERRIE</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LECIE</name> <description>LECIE</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOFIE</name> <description>BOFIE</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPVIE</name> <description>EPVIE</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EWGIE</name> <description>EWGIE</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FOVIE1</name> <description>FOVIE1</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFIE1</name> <description>FFIE1</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FMPIE1</name> <description>FMPIE1</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FOVIE0</name> <description>FOVIE0</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFIE0</name> <description>FFIE0</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FMPIE0</name> <description>FMPIE0</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TMEIE</name> <description>TMEIE</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ESR</name> <displayName>ESR</displayName> <description>interrupt enable register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>REC</name> <description>REC</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> <field> <name>TEC</name> <description>TEC</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> <field> <name>LEC</name> <description>LEC</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>BOFF</name> <description>BOFF</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPVF</name> <description>EPVF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EWGF</name> <description>EWGF</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>BTR</name> <displayName>BTR</displayName> <description>bit timing register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SILM</name> <description>SILM</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LBKM</name> <description>LBKM</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SJW</name> <description>SJW</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>TS2</name> <description>TS2</description> <bitOffset>20</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TS1</name> <description>TS1</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BRP</name> <description>BRP</description> <bitOffset>0</bitOffset> <bitWidth>10</bitWidth> </field> </fields> </register> <register> <name>TI0R</name> <displayName>TI0R</displayName> <description>TX mailbox identifier register</description> <addressOffset>0x180</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STID</name> <description>STID</description> <bitOffset>21</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EXID</name> <description>EXID</description> <bitOffset>3</bitOffset> <bitWidth>18</bitWidth> </field> <field> <name>IDE</name> <description>IDE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTR</name> <description>RTR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXRQ</name> <description>TXRQ</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TDT0R</name> <displayName>TDT0R</displayName> <description>mailbox data length control and time stamp register</description> <addressOffset>0x184</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIME</name> <description>TIME</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>TGT</name> <description>TGT</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DLC</name> <description>DLC</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TDL0R</name> <displayName>TDL0R</displayName> <description>mailbox data low register</description> <addressOffset>0x188</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA3</name> <description>DATA3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA2</name> <description>DATA2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA1</name> <description>DATA1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA0</name> <description>DATA0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>TDH0R</name> <displayName>TDH0R</displayName> <description>mailbox data high register</description> <addressOffset>0x18C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA7</name> <description>DATA7</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA6</name> <description>DATA6</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA5</name> <description>DATA5</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA4</name> <description>DATA4</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>TI1R</name> <displayName>TI1R</displayName> <description>mailbox identifier register</description> <addressOffset>0x190</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STID</name> <description>STID</description> <bitOffset>21</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EXID</name> <description>EXID</description> <bitOffset>3</bitOffset> <bitWidth>18</bitWidth> </field> <field> <name>IDE</name> <description>IDE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTR</name> <description>RTR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXRQ</name> <description>TXRQ</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TDT1R</name> <displayName>TDT1R</displayName> <description>mailbox data length control and time stamp register</description> <addressOffset>0x194</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIME</name> <description>TIME</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>TGT</name> <description>TGT</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DLC</name> <description>DLC</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TDL1R</name> <displayName>TDL1R</displayName> <description>mailbox data low register</description> <addressOffset>0x198</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA3</name> <description>DATA3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA2</name> <description>DATA2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA1</name> <description>DATA1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA0</name> <description>DATA0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>TDH1R</name> <displayName>TDH1R</displayName> <description>mailbox data high register</description> <addressOffset>0x19C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA7</name> <description>DATA7</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA6</name> <description>DATA6</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA5</name> <description>DATA5</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA4</name> <description>DATA4</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>TI2R</name> <displayName>TI2R</displayName> <description>mailbox identifier register</description> <addressOffset>0x1A0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STID</name> <description>STID</description> <bitOffset>21</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EXID</name> <description>EXID</description> <bitOffset>3</bitOffset> <bitWidth>18</bitWidth> </field> <field> <name>IDE</name> <description>IDE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTR</name> <description>RTR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXRQ</name> <description>TXRQ</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>TDT2R</name> <displayName>TDT2R</displayName> <description>mailbox data length control and time stamp register</description> <addressOffset>0x1A4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIME</name> <description>TIME</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>TGT</name> <description>TGT</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DLC</name> <description>DLC</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>TDL2R</name> <displayName>TDL2R</displayName> <description>mailbox data low register</description> <addressOffset>0x1A8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA3</name> <description>DATA3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA2</name> <description>DATA2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA1</name> <description>DATA1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA0</name> <description>DATA0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>TDH2R</name> <displayName>TDH2R</displayName> <description>mailbox data high register</description> <addressOffset>0x1AC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA7</name> <description>DATA7</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA6</name> <description>DATA6</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA5</name> <description>DATA5</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA4</name> <description>DATA4</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>RI0R</name> <displayName>RI0R</displayName> <description>receive FIFO mailbox identifier register</description> <addressOffset>0x1B0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STID</name> <description>STID</description> <bitOffset>21</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EXID</name> <description>EXID</description> <bitOffset>3</bitOffset> <bitWidth>18</bitWidth> </field> <field> <name>IDE</name> <description>IDE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTR</name> <description>RTR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RDT0R</name> <displayName>RDT0R</displayName> <description>mailbox data high register</description> <addressOffset>0x1B4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIME</name> <description>TIME</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>FMI</name> <description>FMI</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DLC</name> <description>DLC</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>RDL0R</name> <displayName>RDL0R</displayName> <description>mailbox data high register</description> <addressOffset>0x1B8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA3</name> <description>DATA3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA2</name> <description>DATA2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA1</name> <description>DATA1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA0</name> <description>DATA0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>RDH0R</name> <displayName>RDH0R</displayName> <description>receive FIFO mailbox data high register</description> <addressOffset>0x1BC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA7</name> <description>DATA7</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA6</name> <description>DATA6</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA5</name> <description>DATA5</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA4</name> <description>DATA4</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>RI1R</name> <displayName>RI1R</displayName> <description>mailbox data high register</description> <addressOffset>0x1C0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>STID</name> <description>STID</description> <bitOffset>21</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EXID</name> <description>EXID</description> <bitOffset>3</bitOffset> <bitWidth>18</bitWidth> </field> <field> <name>IDE</name> <description>IDE</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RTR</name> <description>RTR</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RDT1R</name> <displayName>RDT1R</displayName> <description>mailbox data high register</description> <addressOffset>0x1C4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TIME</name> <description>TIME</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>FMI</name> <description>FMI</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DLC</name> <description>DLC</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>RDL1R</name> <displayName>RDL1R</displayName> <description>mailbox data high register</description> <addressOffset>0x1C8</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA3</name> <description>DATA3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA2</name> <description>DATA2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA1</name> <description>DATA1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA0</name> <description>DATA0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>RDH1R</name> <displayName>RDH1R</displayName> <description>mailbox data high register</description> <addressOffset>0x1CC</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA7</name> <description>DATA7</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA6</name> <description>DATA6</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA5</name> <description>DATA5</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DATA4</name> <description>DATA4</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>FMR</name> <displayName>FMR</displayName> <description>filter master register</description> <addressOffset>0x200</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x2A1C0E01</resetValue> <fields> <field> <name>CAN2SB</name> <description>CAN2SB</description> <bitOffset>8</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>FINIT</name> <description>FINIT</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FM1R</name> <displayName>FM1R</displayName> <description>filter mode register</description> <addressOffset>0x204</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FBM0</name> <description>Filter mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM1</name> <description>Filter mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM2</name> <description>Filter mode</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM3</name> <description>Filter mode</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM4</name> <description>Filter mode</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM5</name> <description>Filter mode</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM6</name> <description>Filter mode</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM7</name> <description>Filter mode</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM8</name> <description>Filter mode</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM9</name> <description>Filter mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM10</name> <description>Filter mode</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM11</name> <description>Filter mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM12</name> <description>Filter mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM13</name> <description>Filter mode</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM14</name> <description>Filter mode</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM15</name> <description>Filter mode</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM16</name> <description>Filter mode</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM17</name> <description>Filter mode</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM18</name> <description>Filter mode</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM19</name> <description>Filter mode</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM20</name> <description>Filter mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM21</name> <description>Filter mode</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM22</name> <description>Filter mode</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM23</name> <description>Filter mode</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM24</name> <description>Filter mode</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM25</name> <description>Filter mode</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM26</name> <description>Filter mode</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FBM27</name> <description>Filter mode</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FS1R</name> <displayName>FS1R</displayName> <description>filter scale register</description> <addressOffset>0x20C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FSC0</name> <description>Filter scale configuration</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC1</name> <description>Filter scale configuration</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC2</name> <description>Filter scale configuration</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC3</name> <description>Filter scale configuration</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC4</name> <description>Filter scale configuration</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC5</name> <description>Filter scale configuration</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC6</name> <description>Filter scale configuration</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC7</name> <description>Filter scale configuration</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC8</name> <description>Filter scale configuration</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC9</name> <description>Filter scale configuration</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC10</name> <description>Filter scale configuration</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC11</name> <description>Filter scale configuration</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC12</name> <description>Filter scale configuration</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC13</name> <description>Filter scale configuration</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC14</name> <description>Filter scale configuration</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC15</name> <description>Filter scale configuration</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC16</name> <description>Filter scale configuration</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC17</name> <description>Filter scale configuration</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC18</name> <description>Filter scale configuration</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC19</name> <description>Filter scale configuration</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC20</name> <description>Filter scale configuration</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC21</name> <description>Filter scale configuration</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC22</name> <description>Filter scale configuration</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC23</name> <description>Filter scale configuration</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC24</name> <description>Filter scale configuration</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC25</name> <description>Filter scale configuration</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC26</name> <description>Filter scale configuration</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSC27</name> <description>Filter scale configuration</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FFA1R</name> <displayName>FFA1R</displayName> <description>filter FIFO assignment register</description> <addressOffset>0x214</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FFA0</name> <description>Filter FIFO assignment for filter 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA1</name> <description>Filter FIFO assignment for filter 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA2</name> <description>Filter FIFO assignment for filter 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA3</name> <description>Filter FIFO assignment for filter 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA4</name> <description>Filter FIFO assignment for filter 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA5</name> <description>Filter FIFO assignment for filter 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA6</name> <description>Filter FIFO assignment for filter 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA7</name> <description>Filter FIFO assignment for filter 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA8</name> <description>Filter FIFO assignment for filter 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA9</name> <description>Filter FIFO assignment for filter 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA10</name> <description>Filter FIFO assignment for filter 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA11</name> <description>Filter FIFO assignment for filter 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA12</name> <description>Filter FIFO assignment for filter 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA13</name> <description>Filter FIFO assignment for filter 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA14</name> <description>Filter FIFO assignment for filter 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA15</name> <description>Filter FIFO assignment for filter 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA16</name> <description>Filter FIFO assignment for filter 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA17</name> <description>Filter FIFO assignment for filter 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA18</name> <description>Filter FIFO assignment for filter 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA19</name> <description>Filter FIFO assignment for filter 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA20</name> <description>Filter FIFO assignment for filter 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA21</name> <description>Filter FIFO assignment for filter 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA22</name> <description>Filter FIFO assignment for filter 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA23</name> <description>Filter FIFO assignment for filter 23</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA24</name> <description>Filter FIFO assignment for filter 24</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA25</name> <description>Filter FIFO assignment for filter 25</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA26</name> <description>Filter FIFO assignment for filter 26</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFA27</name> <description>Filter FIFO assignment for filter 27</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FA1R</name> <displayName>FA1R</displayName> <description>filter activation register</description> <addressOffset>0x21C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FACT0</name> <description>Filter active</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT1</name> <description>Filter active</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT2</name> <description>Filter active</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT3</name> <description>Filter active</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT4</name> <description>Filter active</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT5</name> <description>Filter active</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT6</name> <description>Filter active</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT7</name> <description>Filter active</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT8</name> <description>Filter active</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT9</name> <description>Filter active</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT10</name> <description>Filter active</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT11</name> <description>Filter active</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT12</name> <description>Filter active</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT13</name> <description>Filter active</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT14</name> <description>Filter active</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT15</name> <description>Filter active</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT16</name> <description>Filter active</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT17</name> <description>Filter active</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT18</name> <description>Filter active</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT19</name> <description>Filter active</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT20</name> <description>Filter active</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT21</name> <description>Filter active</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT22</name> <description>Filter active</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT23</name> <description>Filter active</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT24</name> <description>Filter active</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT25</name> <description>Filter active</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT26</name> <description>Filter active</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACT27</name> <description>Filter active</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F0R1</name> <displayName>F0R1</displayName> <description>Filter bank 0 register 1</description> <addressOffset>0x240</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F0R2</name> <displayName>F0R2</displayName> <description>Filter bank 0 register 2</description> <addressOffset>0x244</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F1R1</name> <displayName>F1R1</displayName> <description>Filter bank 1 register 1</description> <addressOffset>0x248</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F1R2</name> <displayName>F1R2</displayName> <description>Filter bank 1 register 2</description> <addressOffset>0x24C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F2R1</name> <displayName>F2R1</displayName> <description>Filter bank 2 register 1</description> <addressOffset>0x250</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F2R2</name> <displayName>F2R2</displayName> <description>Filter bank 2 register 2</description> <addressOffset>0x254</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F3R1</name> <displayName>F3R1</displayName> <description>Filter bank 3 register 1</description> <addressOffset>0x258</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F3R2</name> <displayName>F3R2</displayName> <description>Filter bank 3 register 2</description> <addressOffset>0x25C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F4R1</name> <displayName>F4R1</displayName> <description>Filter bank 4 register 1</description> <addressOffset>0x260</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F4R2</name> <displayName>F4R2</displayName> <description>Filter bank 4 register 2</description> <addressOffset>0x264</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F5R1</name> <displayName>F5R1</displayName> <description>Filter bank 5 register 1</description> <addressOffset>0x268</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F5R2</name> <displayName>F5R2</displayName> <description>Filter bank 5 register 2</description> <addressOffset>0x26C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F6R1</name> <displayName>F6R1</displayName> <description>Filter bank 6 register 1</description> <addressOffset>0x270</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F6R2</name> <displayName>F6R2</displayName> <description>Filter bank 6 register 2</description> <addressOffset>0x274</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F7R1</name> <displayName>F7R1</displayName> <description>Filter bank 7 register 1</description> <addressOffset>0x278</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F7R2</name> <displayName>F7R2</displayName> <description>Filter bank 7 register 2</description> <addressOffset>0x27C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F8R1</name> <displayName>F8R1</displayName> <description>Filter bank 8 register 1</description> <addressOffset>0x280</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F8R2</name> <displayName>F8R2</displayName> <description>Filter bank 8 register 2</description> <addressOffset>0x284</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F9R1</name> <displayName>F9R1</displayName> <description>Filter bank 9 register 1</description> <addressOffset>0x288</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F9R2</name> <displayName>F9R2</displayName> <description>Filter bank 9 register 2</description> <addressOffset>0x28C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F10R1</name> <displayName>F10R1</displayName> <description>Filter bank 10 register 1</description> <addressOffset>0x290</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F10R2</name> <displayName>F10R2</displayName> <description>Filter bank 10 register 2</description> <addressOffset>0x294</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F11R1</name> <displayName>F11R1</displayName> <description>Filter bank 11 register 1</description> <addressOffset>0x298</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F11R2</name> <displayName>F11R2</displayName> <description>Filter bank 11 register 2</description> <addressOffset>0x29C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F12R1</name> <displayName>F12R1</displayName> <description>Filter bank 4 register 1</description> <addressOffset>0x2A0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F12R2</name> <displayName>F12R2</displayName> <description>Filter bank 12 register 2</description> <addressOffset>0x2A4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F13R1</name> <displayName>F13R1</displayName> <description>Filter bank 13 register 1</description> <addressOffset>0x2A8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F13R2</name> <displayName>F13R2</displayName> <description>Filter bank 13 register 2</description> <addressOffset>0x2AC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F14R1</name> <displayName>F14R1</displayName> <description>Filter bank 14 register 1</description> <addressOffset>0x2B0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F14R2</name> <displayName>F14R2</displayName> <description>Filter bank 14 register 2</description> <addressOffset>0x2B4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F15R1</name> <displayName>F15R1</displayName> <description>Filter bank 15 register 1</description> <addressOffset>0x2B8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F15R2</name> <displayName>F15R2</displayName> <description>Filter bank 15 register 2</description> <addressOffset>0x2BC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F16R1</name> <displayName>F16R1</displayName> <description>Filter bank 16 register 1</description> <addressOffset>0x2C0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F16R2</name> <displayName>F16R2</displayName> <description>Filter bank 16 register 2</description> <addressOffset>0x2C4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F17R1</name> <displayName>F17R1</displayName> <description>Filter bank 17 register 1</description> <addressOffset>0x2C8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F17R2</name> <displayName>F17R2</displayName> <description>Filter bank 17 register 2</description> <addressOffset>0x2CC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F18R1</name> <displayName>F18R1</displayName> <description>Filter bank 18 register 1</description> <addressOffset>0x2D0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F18R2</name> <displayName>F18R2</displayName> <description>Filter bank 18 register 2</description> <addressOffset>0x2D4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F19R1</name> <displayName>F19R1</displayName> <description>Filter bank 19 register 1</description> <addressOffset>0x2D8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F19R2</name> <displayName>F19R2</displayName> <description>Filter bank 19 register 2</description> <addressOffset>0x2DC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F20R1</name> <displayName>F20R1</displayName> <description>Filter bank 20 register 1</description> <addressOffset>0x2E0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F20R2</name> <displayName>F20R2</displayName> <description>Filter bank 20 register 2</description> <addressOffset>0x2E4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F21R1</name> <displayName>F21R1</displayName> <description>Filter bank 21 register 1</description> <addressOffset>0x2E8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F21R2</name> <displayName>F21R2</displayName> <description>Filter bank 21 register 2</description> <addressOffset>0x2EC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F22R1</name> <displayName>F22R1</displayName> <description>Filter bank 22 register 1</description> <addressOffset>0x2F0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F22R2</name> <displayName>F22R2</displayName> <description>Filter bank 22 register 2</description> <addressOffset>0x2F4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F23R1</name> <displayName>F23R1</displayName> <description>Filter bank 23 register 1</description> <addressOffset>0x2F8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F23R2</name> <displayName>F23R2</displayName> <description>Filter bank 23 register 2</description> <addressOffset>0x2FC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F24R1</name> <displayName>F24R1</displayName> <description>Filter bank 24 register 1</description> <addressOffset>0x300</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F24R2</name> <displayName>F24R2</displayName> <description>Filter bank 24 register 2</description> <addressOffset>0x304</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F25R1</name> <displayName>F25R1</displayName> <description>Filter bank 25 register 1</description> <addressOffset>0x308</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F25R2</name> <displayName>F25R2</displayName> <description>Filter bank 25 register 2</description> <addressOffset>0x30C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F26R1</name> <displayName>F26R1</displayName> <description>Filter bank 26 register 1</description> <addressOffset>0x310</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F26R2</name> <displayName>F26R2</displayName> <description>Filter bank 26 register 2</description> <addressOffset>0x314</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F27R1</name> <displayName>F27R1</displayName> <description>Filter bank 27 register 1</description> <addressOffset>0x318</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>F27R2</name> <displayName>F27R2</displayName> <description>Filter bank 27 register 2</description> <addressOffset>0x31C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FB0</name> <description>Filter bits</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB1</name> <description>Filter bits</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB2</name> <description>Filter bits</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB3</name> <description>Filter bits</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB4</name> <description>Filter bits</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB5</name> <description>Filter bits</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB6</name> <description>Filter bits</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB7</name> <description>Filter bits</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB8</name> <description>Filter bits</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB9</name> <description>Filter bits</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB10</name> <description>Filter bits</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB11</name> <description>Filter bits</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB12</name> <description>Filter bits</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB13</name> <description>Filter bits</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB14</name> <description>Filter bits</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB15</name> <description>Filter bits</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB16</name> <description>Filter bits</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB17</name> <description>Filter bits</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB18</name> <description>Filter bits</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB19</name> <description>Filter bits</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB20</name> <description>Filter bits</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB21</name> <description>Filter bits</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB22</name> <description>Filter bits</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB23</name> <description>Filter bits</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB24</name> <description>Filter bits</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB25</name> <description>Filter bits</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB26</name> <description>Filter bits</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB27</name> <description>Filter bits</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB28</name> <description>Filter bits</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB29</name> <description>Filter bits</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB30</name> <description>Filter bits</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FB31</name> <description>Filter bits</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="CAN1"> <name>CAN2</name> <baseAddress>0x40006800</baseAddress> <interrupt> <name>CAN2_TX</name> <description>CAN2 TX interrupts</description> <value>63</value> </interrupt> <interrupt> <name>CAN2_RX0</name> <description>CAN2 RX0 interrupts</description> <value>64</value> </interrupt> <interrupt> <name>CAN2_RX1</name> <description>CAN2 RX1 interrupts</description> <value>65</value> </interrupt> <interrupt> <name>CAN2_SCE</name> <description>CAN2 SCE interrupt</description> <value>66</value> </interrupt> </peripheral> <peripheral> <name>NVIC</name> <description>Nested Vectored Interrupt Controller</description> <groupName>NVIC</groupName> <baseAddress>0xE000E100</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x355</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ISER0</name> <displayName>ISER0</displayName> <description>Interrupt Set-Enable Register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETENA</name> <description>SETENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISER1</name> <displayName>ISER1</displayName> <description>Interrupt Set-Enable Register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETENA</name> <description>SETENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISER2</name> <displayName>ISER2</displayName> <description>Interrupt Set-Enable Register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETENA</name> <description>SETENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICER0</name> <displayName>ICER0</displayName> <description>Interrupt Clear-Enable Register</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRENA</name> <description>CLRENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICER1</name> <displayName>ICER1</displayName> <description>Interrupt Clear-Enable Register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRENA</name> <description>CLRENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICER2</name> <displayName>ICER2</displayName> <description>Interrupt Clear-Enable Register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRENA</name> <description>CLRENA</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISPR0</name> <displayName>ISPR0</displayName> <description>Interrupt Set-Pending Register</description> <addressOffset>0x100</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETPEND</name> <description>SETPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISPR1</name> <displayName>ISPR1</displayName> <description>Interrupt Set-Pending Register</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETPEND</name> <description>SETPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ISPR2</name> <displayName>ISPR2</displayName> <description>Interrupt Set-Pending Register</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SETPEND</name> <description>SETPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICPR0</name> <displayName>ICPR0</displayName> <description>Interrupt Clear-Pending Register</description> <addressOffset>0x180</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRPEND</name> <description>CLRPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICPR1</name> <displayName>ICPR1</displayName> <description>Interrupt Clear-Pending Register</description> <addressOffset>0x184</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRPEND</name> <description>CLRPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ICPR2</name> <displayName>ICPR2</displayName> <description>Interrupt Clear-Pending Register</description> <addressOffset>0x188</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLRPEND</name> <description>CLRPEND</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IABR0</name> <displayName>IABR0</displayName> <description>Interrupt Active Bit Register</description> <addressOffset>0x200</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ACTIVE</name> <description>ACTIVE</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IABR1</name> <displayName>IABR1</displayName> <description>Interrupt Active Bit Register</description> <addressOffset>0x204</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ACTIVE</name> <description>ACTIVE</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IABR2</name> <displayName>IABR2</displayName> <description>Interrupt Active Bit Register</description> <addressOffset>0x208</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ACTIVE</name> <description>ACTIVE</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>IPR0</name> <displayName>IPR0</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x300</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR1</name> <displayName>IPR1</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x304</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR2</name> <displayName>IPR2</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x308</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR3</name> <displayName>IPR3</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x30C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR4</name> <displayName>IPR4</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x310</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR5</name> <displayName>IPR5</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x314</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR6</name> <displayName>IPR6</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x318</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR7</name> <displayName>IPR7</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x31C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR8</name> <displayName>IPR8</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x320</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR9</name> <displayName>IPR9</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x324</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR10</name> <displayName>IPR10</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x328</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR11</name> <displayName>IPR11</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x32C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR12</name> <displayName>IPR12</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x330</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR13</name> <displayName>IPR13</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x334</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR14</name> <displayName>IPR14</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x338</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR15</name> <displayName>IPR15</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x33C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR16</name> <displayName>IPR16</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x340</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR17</name> <displayName>IPR17</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x344</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR18</name> <displayName>IPR18</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x348</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR19</name> <displayName>IPR19</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x34C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>IPR20</name> <displayName>IPR20</displayName> <description>Interrupt Priority Register</description> <addressOffset>0x350</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IPR_N0</name> <description>IPR_N0</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N1</name> <description>IPR_N1</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N2</name> <description>IPR_N2</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IPR_N3</name> <description>IPR_N3</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FLASH</name> <description>FLASH</description> <groupName>FLASH</groupName> <baseAddress>0x40023C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>FLASH</name> <description>Flash global interrupt</description> <value>4</value> </interrupt> <registers> <register> <name>ACR</name> <displayName>ACR</displayName> <description>Flash access control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>LATENCY</name> <description>Latency</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>PRFTEN</name> <description>Prefetch enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ICEN</name> <description>Instruction cache enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DCEN</name> <description>Data cache enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ICRST</name> <description>Instruction cache reset</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>DCRST</name> <description>Data cache reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>KEYR</name> <displayName>KEYR</displayName> <description>Flash key register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>KEY</name> <description>FPEC key</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OPTKEYR</name> <displayName>OPTKEYR</displayName> <description>Flash option key register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>OPTKEY</name> <description>Option byte key</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>SR</name> <displayName>SR</displayName> <description>Status register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>EOP</name> <description>End of operation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OPERR</name> <description>Operation error</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WRPERR</name> <description>Write protection error</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PGAERR</name> <description>Programming alignment error</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PGPERR</name> <description>Programming parallelism error</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PGSERR</name> <description>Programming sequence error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BSY</name> <description>Busy</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>CR</name> <displayName>CR</displayName> <description>Control register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x80000000</resetValue> <fields> <field> <name>PG</name> <description>Programming</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SER</name> <description>Sector Erase</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MER</name> <description>Mass Erase of sectors 0 to 11</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SNB</name> <description>Sector number</description> <bitOffset>3</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>PSIZE</name> <description>Program size</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MER1</name> <description>Mass Erase of sectors 12 to 23</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STRT</name> <description>Start</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EOPIE</name> <description>End of operation interrupt enable</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ERRIE</name> <description>Error interrupt enable</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LOCK</name> <description>Lock</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OPTCR</name> <displayName>OPTCR</displayName> <description>Flash option control register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFFAAED</resetValue> <fields> <field> <name>OPTLOCK</name> <description>Option lock</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPTSTRT</name> <description>Option start</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOR_LEV</name> <description>BOR reset Level</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>WDG_SW</name> <description>WDG_SW User option bytes</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nRST_STOP</name> <description>nRST_STOP User option bytes</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>nRST_STDBY</name> <description>nRST_STDBY User option bytes</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RDP</name> <description>Read protect</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>nWRP</name> <description>Not write protect</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>OPTCR1</name> <displayName>OPTCR1</displayName> <description>Flash option control register 1</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFF0000</resetValue> <fields> <field> <name>nWRP</name> <description>Not write protect</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>EXTI</name> <description>External interrupt/event controller</description> <groupName>EXTI</groupName> <baseAddress>0x40013C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>TAMP_STAMP</name> <description>Tamper and TimeStamp interrupts through the EXTI line</description> <value>2</value> </interrupt> <interrupt> <name>EXTI0</name> <description>EXTI Line0 interrupt</description> <value>6</value> </interrupt> <interrupt> <name>EXTI1</name> <description>EXTI Line1 interrupt</description> <value>7</value> </interrupt> <interrupt> <name>EXTI2</name> <description>EXTI Line2 interrupt</description> <value>8</value> </interrupt> <interrupt> <name>EXTI3</name> <description>EXTI Line3 interrupt</description> <value>9</value> </interrupt> <interrupt> <name>EXTI4</name> <description>EXTI Line4 interrupt</description> <value>10</value> </interrupt> <interrupt> <name>EXTI9_5</name> <description>EXTI Line[9:5] interrupts</description> <value>23</value> </interrupt> <interrupt> <name>EXTI15_10</name> <description>EXTI Line[15:10] interrupts</description> <value>40</value> </interrupt> <registers> <register> <name>IMR</name> <displayName>IMR</displayName> <description>Interrupt mask register (EXTI_IMR)</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MR0</name> <description>Interrupt Mask on line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR1</name> <description>Interrupt Mask on line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR2</name> <description>Interrupt Mask on line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR3</name> <description>Interrupt Mask on line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR4</name> <description>Interrupt Mask on line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR5</name> <description>Interrupt Mask on line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR6</name> <description>Interrupt Mask on line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR7</name> <description>Interrupt Mask on line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR8</name> <description>Interrupt Mask on line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR9</name> <description>Interrupt Mask on line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR10</name> <description>Interrupt Mask on line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR11</name> <description>Interrupt Mask on line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR12</name> <description>Interrupt Mask on line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR13</name> <description>Interrupt Mask on line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR14</name> <description>Interrupt Mask on line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR15</name> <description>Interrupt Mask on line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR16</name> <description>Interrupt Mask on line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR17</name> <description>Interrupt Mask on line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR18</name> <description>Interrupt Mask on line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR19</name> <description>Interrupt Mask on line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR20</name> <description>Interrupt Mask on line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR21</name> <description>Interrupt Mask on line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR22</name> <description>Interrupt Mask on line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>EMR</name> <displayName>EMR</displayName> <description>Event mask register (EXTI_EMR)</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MR0</name> <description>Event Mask on line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR1</name> <description>Event Mask on line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR2</name> <description>Event Mask on line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR3</name> <description>Event Mask on line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR4</name> <description>Event Mask on line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR5</name> <description>Event Mask on line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR6</name> <description>Event Mask on line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR7</name> <description>Event Mask on line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR8</name> <description>Event Mask on line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR9</name> <description>Event Mask on line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR10</name> <description>Event Mask on line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR11</name> <description>Event Mask on line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR12</name> <description>Event Mask on line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR13</name> <description>Event Mask on line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR14</name> <description>Event Mask on line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR15</name> <description>Event Mask on line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR16</name> <description>Event Mask on line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR17</name> <description>Event Mask on line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR18</name> <description>Event Mask on line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR19</name> <description>Event Mask on line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR20</name> <description>Event Mask on line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR21</name> <description>Event Mask on line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MR22</name> <description>Event Mask on line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>RTSR</name> <displayName>RTSR</displayName> <description>Rising Trigger selection register (EXTI_RTSR)</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TR0</name> <description>Rising trigger event configuration of line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR1</name> <description>Rising trigger event configuration of line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR2</name> <description>Rising trigger event configuration of line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR3</name> <description>Rising trigger event configuration of line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR4</name> <description>Rising trigger event configuration of line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR5</name> <description>Rising trigger event configuration of line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR6</name> <description>Rising trigger event configuration of line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR7</name> <description>Rising trigger event configuration of line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR8</name> <description>Rising trigger event configuration of line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR9</name> <description>Rising trigger event configuration of line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR10</name> <description>Rising trigger event configuration of line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR11</name> <description>Rising trigger event configuration of line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR12</name> <description>Rising trigger event configuration of line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR13</name> <description>Rising trigger event configuration of line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR14</name> <description>Rising trigger event configuration of line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR15</name> <description>Rising trigger event configuration of line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR16</name> <description>Rising trigger event configuration of line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR17</name> <description>Rising trigger event configuration of line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR18</name> <description>Rising trigger event configuration of line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR19</name> <description>Rising trigger event configuration of line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR20</name> <description>Rising trigger event configuration of line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR21</name> <description>Rising trigger event configuration of line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR22</name> <description>Rising trigger event configuration of line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FTSR</name> <displayName>FTSR</displayName> <description>Falling Trigger selection register (EXTI_FTSR)</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TR0</name> <description>Falling trigger event configuration of line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR1</name> <description>Falling trigger event configuration of line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR2</name> <description>Falling trigger event configuration of line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR3</name> <description>Falling trigger event configuration of line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR4</name> <description>Falling trigger event configuration of line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR5</name> <description>Falling trigger event configuration of line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR6</name> <description>Falling trigger event configuration of line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR7</name> <description>Falling trigger event configuration of line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR8</name> <description>Falling trigger event configuration of line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR9</name> <description>Falling trigger event configuration of line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR10</name> <description>Falling trigger event configuration of line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR11</name> <description>Falling trigger event configuration of line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR12</name> <description>Falling trigger event configuration of line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR13</name> <description>Falling trigger event configuration of line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR14</name> <description>Falling trigger event configuration of line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR15</name> <description>Falling trigger event configuration of line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR16</name> <description>Falling trigger event configuration of line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR17</name> <description>Falling trigger event configuration of line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR18</name> <description>Falling trigger event configuration of line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR19</name> <description>Falling trigger event configuration of line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR20</name> <description>Falling trigger event configuration of line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR21</name> <description>Falling trigger event configuration of line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TR22</name> <description>Falling trigger event configuration of line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SWIER</name> <displayName>SWIER</displayName> <description>Software interrupt event register (EXTI_SWIER)</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SWIER0</name> <description>Software Interrupt on line 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER1</name> <description>Software Interrupt on line 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER2</name> <description>Software Interrupt on line 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER3</name> <description>Software Interrupt on line 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER4</name> <description>Software Interrupt on line 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER5</name> <description>Software Interrupt on line 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER6</name> <description>Software Interrupt on line 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER7</name> <description>Software Interrupt on line 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER8</name> <description>Software Interrupt on line 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER9</name> <description>Software Interrupt on line 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER10</name> <description>Software Interrupt on line 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER11</name> <description>Software Interrupt on line 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER12</name> <description>Software Interrupt on line 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER13</name> <description>Software Interrupt on line 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER14</name> <description>Software Interrupt on line 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER15</name> <description>Software Interrupt on line 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER16</name> <description>Software Interrupt on line 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER17</name> <description>Software Interrupt on line 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER18</name> <description>Software Interrupt on line 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER19</name> <description>Software Interrupt on line 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER20</name> <description>Software Interrupt on line 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER21</name> <description>Software Interrupt on line 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SWIER22</name> <description>Software Interrupt on line 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>PR</name> <displayName>PR</displayName> <description>Pending register (EXTI_PR)</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PR0</name> <description>Pending bit 0</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR1</name> <description>Pending bit 1</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR2</name> <description>Pending bit 2</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR3</name> <description>Pending bit 3</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR4</name> <description>Pending bit 4</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR5</name> <description>Pending bit 5</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR6</name> <description>Pending bit 6</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR7</name> <description>Pending bit 7</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR8</name> <description>Pending bit 8</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR9</name> <description>Pending bit 9</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR10</name> <description>Pending bit 10</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR11</name> <description>Pending bit 11</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR12</name> <description>Pending bit 12</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR13</name> <description>Pending bit 13</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR14</name> <description>Pending bit 14</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR15</name> <description>Pending bit 15</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR16</name> <description>Pending bit 16</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR17</name> <description>Pending bit 17</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR18</name> <description>Pending bit 18</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR19</name> <description>Pending bit 19</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR20</name> <description>Pending bit 20</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR21</name> <description>Pending bit 21</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PR22</name> <description>Pending bit 22</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_HS_GLOBAL</name> <description>USB on the go high speed</description> <groupName>USB_OTG_HS</groupName> <baseAddress>0x40040000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>OTG_HS_EP1_OUT</name> <description>USB On The Go HS End Point 1 Out global interrupt</description> <value>74</value> </interrupt> <interrupt> <name>OTG_HS_EP1_IN</name> <description>USB On The Go HS End Point 1 In global interrupt</description> <value>75</value> </interrupt> <interrupt> <name>OTG_HS_WKUP</name> <description>USB On The Go HS Wakeup through EXTI interrupt</description> <value>76</value> </interrupt> <interrupt> <name>OTG_HS</name> <description>USB On The Go HS global interrupt</description> <value>77</value> </interrupt> <registers> <register> <name>OTG_HS_GOTGCTL</name> <displayName>OTG_HS_GOTGCTL</displayName> <description>OTG_HS control and status register</description> <addressOffset>0x0</addressOffset> <size>32</size> <resetValue>0x00000800</resetValue> <fields> <field> <name>SRQSCS</name> <description>Session request success</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SRQ</name> <description>Session request</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HNGSCS</name> <description>Host negotiation success</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HNPRQ</name> <description>HNP request</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSHNPEN</name> <description>Host set HNP enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DHNPEN</name> <description>Device HNP enabled</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CIDSTS</name> <description>Connector ID status</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>DBCT</name> <description>Long/short debounce time</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ASVLD</name> <description>A-session valid</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BSVLD</name> <description>B-session valid</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>OTG_HS_GOTGINT</name> <displayName>OTG_HS_GOTGINT</displayName> <description>OTG_HS interrupt register</description> <addressOffset>0x4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>SEDET</name> <description>Session end detected</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SRSSCHG</name> <description>Session request success status change</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HNSSCHG</name> <description>Host negotiation success status change</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HNGDET</name> <description>Host negotiation detected</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADTOCHG</name> <description>A-device timeout change</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DBCDNE</name> <description>Debounce done</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GAHBCFG</name> <displayName>OTG_HS_GAHBCFG</displayName> <description>OTG_HS AHB configuration register</description> <addressOffset>0x8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>GINT</name> <description>Global interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HBSTLEN</name> <description>Burst length/type</description> <bitOffset>1</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DMAEN</name> <description>DMA enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFELVL</name> <description>TxFIFO empty level</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PTXFELVL</name> <description>Periodic TxFIFO empty level</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GUSBCFG</name> <displayName>OTG_HS_GUSBCFG</displayName> <description>OTG_HS USB configuration register</description> <addressOffset>0xC</addressOffset> <size>32</size> <resetValue>0x00000A00</resetValue> <fields> <field> <name>TOCAL</name> <description>FS timeout calibration</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>PHYSEL</name> <description>USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SRPCAP</name> <description>SRP-capable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HNPCAP</name> <description>HNP-capable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TRDT</name> <description>USB turnaround time</description> <bitOffset>10</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>PHYLPCS</name> <description>PHY Low-power clock select</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ULPIFSLS</name> <description>ULPI FS/LS select</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ULPIAR</name> <description>ULPI Auto-resume</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ULPICSM</name> <description>ULPI Clock SuspendM</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ULPIEVBUSD</name> <description>ULPI External VBUS Drive</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ULPIEVBUSI</name> <description>ULPI external VBUS indicator</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TSDPS</name> <description>TermSel DLine pulsing selection</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PCCI</name> <description>Indicator complement</description> <bitOffset>23</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PTCI</name> <description>Indicator pass through</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ULPIIPD</name> <description>ULPI interface protect disable</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FHMOD</name> <description>Forced host mode</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FDMOD</name> <description>Forced peripheral mode</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CTXPKT</name> <description>Corrupt Tx packet</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_GRSTCTL</name> <displayName>OTG_HS_GRSTCTL</displayName> <description>OTG_HS reset register</description> <addressOffset>0x10</addressOffset> <size>32</size> <resetValue>0x20000000</resetValue> <fields> <field> <name>CSRST</name> <description>Core soft reset</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HSRST</name> <description>HCLK soft reset</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FCRST</name> <description>Host frame counter reset</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXFFLSH</name> <description>RxFIFO flush</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFFLSH</name> <description>TxFIFO flush</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>6</bitOffset> <bitWidth>5</bitWidth> <access>read-write</access> </field> <field> <name>DMAREQ</name> <description>DMA request signal</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>AHBIDL</name> <description>AHB master idle</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>OTG_HS_GINTSTS</name> <displayName>OTG_HS_GINTSTS</displayName> <description>OTG_HS core interrupt register</description> <addressOffset>0x14</addressOffset> <size>32</size> <resetValue>0x04000020</resetValue> <fields> <field> <name>CMOD</name> <description>Current mode of operation</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>MMIS</name> <description>Mode mismatch interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OTGINT</name> <description>OTG interrupt</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SOF</name> <description>Start of frame</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXFLVL</name> <description>RxFIFO nonempty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NPTXFE</name> <description>Nonperiodic TxFIFO empty</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>GINAKEFF</name> <description>Global IN nonperiodic NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BOUTNAKEFF</name> <description>Global OUT NAK effective</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ESUSP</name> <description>Early suspend</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBSUSP</name> <description>USB suspend</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBRST</name> <description>USB reset</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ENUMDNE</name> <description>Enumeration done</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ISOODRP</name> <description>Isochronous OUT packet dropped interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EOPF</name> <description>End of periodic frame interrupt</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IEPINT</name> <description>IN endpoint interrupt</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>OEPINT</name> <description>OUT endpoint interrupt</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>IISOIXFR</name> <description>Incomplete isochronous IN transfer</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PXFR_INCOMPISOOUT</name> <description>Incomplete periodic transfer</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DATAFSUSP</name> <description>Data fetch suspended</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>HPRTINT</name> <description>Host port interrupt</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HCINT</name> <description>Host channels interrupt</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PTXFE</name> <description>Periodic TxFIFO empty</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>CIDSCHG</name> <description>Connector ID status change</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DISCINT</name> <description>Disconnect detected interrupt</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SRQINT</name> <description>Session request/new session detected interrupt</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WKUINT</name> <description>Resume/remote wakeup detected interrupt</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_GINTMSK</name> <displayName>OTG_HS_GINTMSK</displayName> <description>OTG_HS interrupt mask register</description> <addressOffset>0x18</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MMISM</name> <description>Mode mismatch interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OTGINT</name> <description>OTG interrupt mask</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SOFM</name> <description>Start of frame mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>RXFLVLM</name> <description>Receive FIFO nonempty mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NPTXFEM</name> <description>Nonperiodic TxFIFO empty mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>GINAKEFFM</name> <description>Global nonperiodic IN NAK effective mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>GONAKEFFM</name> <description>Global OUT NAK effective mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ESUSPM</name> <description>Early suspend mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBSUSPM</name> <description>USB suspend mask</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>USBRST</name> <description>USB reset mask</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ENUMDNEM</name> <description>Enumeration done mask</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ISOODRPM</name> <description>Isochronous OUT packet dropped interrupt mask</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EOPFM</name> <description>End of periodic frame interrupt mask</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPMISM</name> <description>Endpoint mismatch interrupt mask</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IEPINT</name> <description>IN endpoints interrupt mask</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OEPINT</name> <description>OUT endpoints interrupt mask</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IISOIXFRM</name> <description>Incomplete isochronous IN transfer mask</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PXFRM_IISOOXFRM</name> <description>Incomplete periodic transfer mask</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>FSUSPM</name> <description>Data fetch suspended mask</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PRTIM</name> <description>Host port interrupt mask</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>HCIM</name> <description>Host channels interrupt mask</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PTXFEM</name> <description>Periodic TxFIFO empty mask</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CIDSCHGM</name> <description>Connector ID status change mask</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DISCINT</name> <description>Disconnect detected interrupt mask</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SRQIM</name> <description>Session request/new session detected interrupt mask</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>WUIM</name> <description>Resume/remote wakeup detected interrupt mask</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_GRXSTSR_Host</name> <displayName>OTG_HS_GRXSTSR_Host</displayName> <description>OTG_HS Receive status debug read register (host mode)</description> <addressOffset>0x1C</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>CHNUM</name> <description>Channel number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BCNT</name> <description>Byte count</description> <bitOffset>4</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>15</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTSTS</name> <description>Packet status</description> <bitOffset>17</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GRXSTSP_Host</name> <displayName>OTG_HS_GRXSTSP_Host</displayName> <description>OTG_HS status read and pop register (host mode)</description> <addressOffset>0x20</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>CHNUM</name> <description>Channel number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BCNT</name> <description>Byte count</description> <bitOffset>4</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>15</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTSTS</name> <description>Packet status</description> <bitOffset>17</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GRXFSIZ</name> <displayName>OTG_HS_GRXFSIZ</displayName> <description>OTG_HS Receive FIFO size register</description> <addressOffset>0x24</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x00000200</resetValue> <fields> <field> <name>RXFD</name> <description>RxFIFO depth</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GNPTXFSIZ_Host</name> <displayName>OTG_HS_GNPTXFSIZ_Host</displayName> <description>OTG_HS nonperiodic transmit FIFO size register (host mode)</description> <addressOffset>0x28</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x00000200</resetValue> <fields> <field> <name>NPTXFSA</name> <description>Nonperiodic transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>NPTXFD</name> <description>Nonperiodic TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_TX0FSIZ_Peripheral</name> <displayName>OTG_HS_TX0FSIZ_Peripheral</displayName> <description>Endpoint 0 transmit FIFO size (peripheral mode)</description> <alternateRegister>OTG_HS_GNPTXFSIZ_Host</alternateRegister> <addressOffset>0x28</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x00000200</resetValue> <fields> <field> <name>TX0FSA</name> <description>Endpoint 0 transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>TX0FD</name> <description>Endpoint 0 TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GNPTXSTS</name> <displayName>OTG_HS_GNPTXSTS</displayName> <description>OTG_HS nonperiodic transmit FIFO/queue status register</description> <addressOffset>0x2C</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x00080200</resetValue> <fields> <field> <name>NPTXFSAV</name> <description>Nonperiodic TxFIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>NPTQXSAV</name> <description>Nonperiodic transmit request queue space available</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>NPTXQTOP</name> <description>Top of the nonperiodic transmit request queue</description> <bitOffset>24</bitOffset> <bitWidth>7</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GCCFG</name> <displayName>OTG_HS_GCCFG</displayName> <description>OTG_HS general core configuration register</description> <addressOffset>0x38</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PWRDWN</name> <description>Power down</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>I2CPADEN</name> <description>Enable I2C bus connection for the external I2C PHY interface</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBUSASEN</name> <description>Enable the VBUS sensing device</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VBUSBSEN</name> <description>Enable the VBUS sensing device</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SOFOUTEN</name> <description>SOF output enable</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOVBUSSENS</name> <description>VBUS sensing disable option</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_CID</name> <displayName>OTG_HS_CID</displayName> <description>OTG_HS core ID register</description> <addressOffset>0x3C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x00001200</resetValue> <fields> <field> <name>PRODUCT_ID</name> <description>Product ID field</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HPTXFSIZ</name> <displayName>OTG_HS_HPTXFSIZ</displayName> <description>OTG_HS Host periodic transmit FIFO size register</description> <addressOffset>0x100</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000600</resetValue> <fields> <field> <name>PTXSA</name> <description>Host periodic TxFIFO start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>PTXFD</name> <description>Host periodic TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTXF1</name> <displayName>OTG_HS_DIEPTXF1</displayName> <description>OTG_HS device IN endpoint transmit FIFO size register</description> <addressOffset>0x104</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFOx transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTXF2</name> <displayName>OTG_HS_DIEPTXF2</displayName> <description>OTG_HS device IN endpoint transmit FIFO size register</description> <addressOffset>0x108</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFOx transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTXF3</name> <displayName>OTG_HS_DIEPTXF3</displayName> <description>OTG_HS device IN endpoint transmit FIFO size register</description> <addressOffset>0x11C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFOx transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTXF4</name> <displayName>OTG_HS_DIEPTXF4</displayName> <description>OTG_HS device IN endpoint transmit FIFO size register</description> <addressOffset>0x120</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFOx transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTXF5</name> <displayName>OTG_HS_DIEPTXF5</displayName> <description>OTG_HS device IN endpoint transmit FIFO size register</description> <addressOffset>0x124</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFOx transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTXF6</name> <displayName>OTG_HS_DIEPTXF6</displayName> <description>OTG_HS device IN endpoint transmit FIFO size register</description> <addressOffset>0x128</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFOx transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTXF7</name> <displayName>OTG_HS_DIEPTXF7</displayName> <description>OTG_HS device IN endpoint transmit FIFO size register</description> <addressOffset>0x12C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02000400</resetValue> <fields> <field> <name>INEPTXSA</name> <description>IN endpoint FIFOx transmit RAM start address</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>INEPTXFD</name> <description>IN endpoint TxFIFO depth</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GRXSTSR_Peripheral</name> <displayName>OTG_HS_GRXSTSR_Peripheral</displayName> <description>OTG_HS Receive status debug read register (peripheral mode mode)</description> <alternateRegister>OTG_HS_GRXSTSR_Host</alternateRegister> <addressOffset>0x1C</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BCNT</name> <description>Byte count</description> <bitOffset>4</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>15</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTSTS</name> <description>Packet status</description> <bitOffset>17</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>FRMNUM</name> <description>Frame number</description> <bitOffset>21</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_GRXSTSP_Peripheral</name> <displayName>OTG_HS_GRXSTSP_Peripheral</displayName> <description>OTG_HS status read and pop register (peripheral mode)</description> <alternateRegister>OTG_HS_GRXSTSP_Host</alternateRegister> <addressOffset>0x20</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BCNT</name> <description>Byte count</description> <bitOffset>4</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>15</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PKTSTS</name> <description>Packet status</description> <bitOffset>17</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>FRMNUM</name> <description>Frame number</description> <bitOffset>21</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_HS_HOST</name> <description>USB on the go high speed</description> <groupName>USB_OTG_HS</groupName> <baseAddress>0x40040400</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>OTG_HS_HCFG</name> <displayName>OTG_HS_HCFG</displayName> <description>OTG_HS host configuration register</description> <addressOffset>0x0</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>FSLSPCS</name> <description>FS/LS PHY clock select</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>FSLSS</name> <description>FS- and LS-only support</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>OTG_HS_HFIR</name> <displayName>OTG_HS_HFIR</displayName> <description>OTG_HS Host frame interval register</description> <addressOffset>0x4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0000EA60</resetValue> <fields> <field> <name>FRIVL</name> <description>Frame interval</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HFNUM</name> <displayName>OTG_HS_HFNUM</displayName> <description>OTG_HS host frame number/frame time remaining register</description> <addressOffset>0x8</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x00003FFF</resetValue> <fields> <field> <name>FRNUM</name> <description>Frame number</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>FTREM</name> <description>Frame time remaining</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HPTXSTS</name> <displayName>OTG_HS_HPTXSTS</displayName> <description>OTG_HS_Host periodic transmit FIFO/queue status register</description> <addressOffset>0x10</addressOffset> <size>32</size> <resetValue>0x00080100</resetValue> <fields> <field> <name>PTXFSAVL</name> <description>Periodic transmit data FIFO space available</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> <access>read-write</access> </field> <field> <name>PTXQSAV</name> <description>Periodic transmit request queue space available</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> <field> <name>PTXQTOP</name> <description>Top of the periodic transmit request queue</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>OTG_HS_HAINT</name> <displayName>OTG_HS_HAINT</displayName> <description>OTG_HS Host all channels interrupt register</description> <addressOffset>0x14</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>HAINT</name> <description>Channel interrupts</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HAINTMSK</name> <displayName>OTG_HS_HAINTMSK</displayName> <description>OTG_HS host all channels interrupt mask register</description> <addressOffset>0x18</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>HAINTM</name> <description>Channel interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HPRT</name> <displayName>OTG_HS_HPRT</displayName> <description>OTG_HS host port control and status register</description> <addressOffset>0x40</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>PCSTS</name> <description>Port connect status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PCDET</name> <description>Port connect detected</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PENA</name> <description>Port enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PENCHNG</name> <description>Port enable/disable change</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>POCA</name> <description>Port overcurrent active</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>POCCHNG</name> <description>Port overcurrent change</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PRES</name> <description>Port resume</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PSUSP</name> <description>Port suspend</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PRST</name> <description>Port reset</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PLSTS</name> <description>Port line status</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>PPWR</name> <description>Port power</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PTCTL</name> <description>Port test control</description> <bitOffset>13</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>PSPD</name> <description>Port speed</description> <bitOffset>17</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR0</name> <displayName>OTG_HS_HCCHAR0</displayName> <description>OTG_HS host channel-0 characteristics register</description> <addressOffset>0x100</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR1</name> <displayName>OTG_HS_HCCHAR1</displayName> <description>OTG_HS host channel-1 characteristics register</description> <addressOffset>0x120</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR2</name> <displayName>OTG_HS_HCCHAR2</displayName> <description>OTG_HS host channel-2 characteristics register</description> <addressOffset>0x140</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR3</name> <displayName>OTG_HS_HCCHAR3</displayName> <description>OTG_HS host channel-3 characteristics register</description> <addressOffset>0x160</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR4</name> <displayName>OTG_HS_HCCHAR4</displayName> <description>OTG_HS host channel-4 characteristics register</description> <addressOffset>0x180</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR5</name> <displayName>OTG_HS_HCCHAR5</displayName> <description>OTG_HS host channel-5 characteristics register</description> <addressOffset>0x1A0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR6</name> <displayName>OTG_HS_HCCHAR6</displayName> <description>OTG_HS host channel-6 characteristics register</description> <addressOffset>0x1C0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR7</name> <displayName>OTG_HS_HCCHAR7</displayName> <description>OTG_HS host channel-7 characteristics register</description> <addressOffset>0x1E0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR8</name> <displayName>OTG_HS_HCCHAR8</displayName> <description>OTG_HS host channel-8 characteristics register</description> <addressOffset>0x200</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR9</name> <displayName>OTG_HS_HCCHAR9</displayName> <description>OTG_HS host channel-9 characteristics register</description> <addressOffset>0x220</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR10</name> <displayName>OTG_HS_HCCHAR10</displayName> <description>OTG_HS host channel-10 characteristics register</description> <addressOffset>0x240</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCCHAR11</name> <displayName>OTG_HS_HCCHAR11</displayName> <description>OTG_HS host channel-11 characteristics register</description> <addressOffset>0x260</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>EPNUM</name> <description>Endpoint number</description> <bitOffset>11</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>EPDIR</name> <description>Endpoint direction</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSDEV</name> <description>Low-speed device</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MC</name> <description>Multi Count (MC) / Error Count (EC)</description> <bitOffset>20</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>22</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ODDFRM</name> <description>Odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHDIS</name> <description>Channel disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHENA</name> <description>Channel enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT0</name> <displayName>OTG_HS_HCSPLT0</displayName> <description>OTG_HS host channel-0 split control register</description> <addressOffset>0x104</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT1</name> <displayName>OTG_HS_HCSPLT1</displayName> <description>OTG_HS host channel-1 split control register</description> <addressOffset>0x124</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT2</name> <displayName>OTG_HS_HCSPLT2</displayName> <description>OTG_HS host channel-2 split control register</description> <addressOffset>0x144</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT3</name> <displayName>OTG_HS_HCSPLT3</displayName> <description>OTG_HS host channel-3 split control register</description> <addressOffset>0x164</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT4</name> <displayName>OTG_HS_HCSPLT4</displayName> <description>OTG_HS host channel-4 split control register</description> <addressOffset>0x184</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT5</name> <displayName>OTG_HS_HCSPLT5</displayName> <description>OTG_HS host channel-5 split control register</description> <addressOffset>0x1A4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT6</name> <displayName>OTG_HS_HCSPLT6</displayName> <description>OTG_HS host channel-6 split control register</description> <addressOffset>0x1C4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT7</name> <displayName>OTG_HS_HCSPLT7</displayName> <description>OTG_HS host channel-7 split control register</description> <addressOffset>0x1E4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT8</name> <displayName>OTG_HS_HCSPLT8</displayName> <description>OTG_HS host channel-8 split control register</description> <addressOffset>0x204</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT9</name> <displayName>OTG_HS_HCSPLT9</displayName> <description>OTG_HS host channel-9 split control register</description> <addressOffset>0x224</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT10</name> <displayName>OTG_HS_HCSPLT10</displayName> <description>OTG_HS host channel-10 split control register</description> <addressOffset>0x244</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCSPLT11</name> <displayName>OTG_HS_HCSPLT11</displayName> <description>OTG_HS host channel-11 split control register</description> <addressOffset>0x264</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>PRTADDR</name> <description>Port address</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>HUBADDR</name> <description>Hub address</description> <bitOffset>7</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>XACTPOS</name> <description>XACTPOS</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>COMPLSPLT</name> <description>Do complete split</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SPLITEN</name> <description>Split enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT0</name> <displayName>OTG_HS_HCINT0</displayName> <description>OTG_HS host channel-11 interrupt register</description> <addressOffset>0x108</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT1</name> <displayName>OTG_HS_HCINT1</displayName> <description>OTG_HS host channel-1 interrupt register</description> <addressOffset>0x128</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT2</name> <displayName>OTG_HS_HCINT2</displayName> <description>OTG_HS host channel-2 interrupt register</description> <addressOffset>0x148</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT3</name> <displayName>OTG_HS_HCINT3</displayName> <description>OTG_HS host channel-3 interrupt register</description> <addressOffset>0x168</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT4</name> <displayName>OTG_HS_HCINT4</displayName> <description>OTG_HS host channel-4 interrupt register</description> <addressOffset>0x188</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT5</name> <displayName>OTG_HS_HCINT5</displayName> <description>OTG_HS host channel-5 interrupt register</description> <addressOffset>0x1A8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT6</name> <displayName>OTG_HS_HCINT6</displayName> <description>OTG_HS host channel-6 interrupt register</description> <addressOffset>0x1C8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT7</name> <displayName>OTG_HS_HCINT7</displayName> <description>OTG_HS host channel-7 interrupt register</description> <addressOffset>0x1E8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT8</name> <displayName>OTG_HS_HCINT8</displayName> <description>OTG_HS host channel-8 interrupt register</description> <addressOffset>0x208</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT9</name> <displayName>OTG_HS_HCINT9</displayName> <description>OTG_HS host channel-9 interrupt register</description> <addressOffset>0x228</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT10</name> <displayName>OTG_HS_HCINT10</displayName> <description>OTG_HS host channel-10 interrupt register</description> <addressOffset>0x248</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINT11</name> <displayName>OTG_HS_HCINT11</displayName> <description>OTG_HS host channel-11 interrupt register</description> <addressOffset>0x268</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHH</name> <description>Channel halted</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALL</name> <description>STALL response received interrupt</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAK</name> <description>NAK response received interrupt</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>ACK response received/transmitted interrupt</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>Response received interrupt</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERR</name> <description>Transaction error</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERR</name> <description>Babble error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMOR</name> <description>Frame overrun</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERR</name> <description>Data toggle error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK0</name> <displayName>OTG_HS_HCINTMSK0</displayName> <description>OTG_HS host channel-11 interrupt mask register</description> <addressOffset>0x10C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK1</name> <displayName>OTG_HS_HCINTMSK1</displayName> <description>OTG_HS host channel-1 interrupt mask register</description> <addressOffset>0x12C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK2</name> <displayName>OTG_HS_HCINTMSK2</displayName> <description>OTG_HS host channel-2 interrupt mask register</description> <addressOffset>0x14C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK3</name> <displayName>OTG_HS_HCINTMSK3</displayName> <description>OTG_HS host channel-3 interrupt mask register</description> <addressOffset>0x16C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK4</name> <displayName>OTG_HS_HCINTMSK4</displayName> <description>OTG_HS host channel-4 interrupt mask register</description> <addressOffset>0x18C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK5</name> <displayName>OTG_HS_HCINTMSK5</displayName> <description>OTG_HS host channel-5 interrupt mask register</description> <addressOffset>0x1AC</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK6</name> <displayName>OTG_HS_HCINTMSK6</displayName> <description>OTG_HS host channel-6 interrupt mask register</description> <addressOffset>0x1CC</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK7</name> <displayName>OTG_HS_HCINTMSK7</displayName> <description>OTG_HS host channel-7 interrupt mask register</description> <addressOffset>0x1EC</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK8</name> <displayName>OTG_HS_HCINTMSK8</displayName> <description>OTG_HS host channel-8 interrupt mask register</description> <addressOffset>0x20C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK9</name> <displayName>OTG_HS_HCINTMSK9</displayName> <description>OTG_HS host channel-9 interrupt mask register</description> <addressOffset>0x22C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK10</name> <displayName>OTG_HS_HCINTMSK10</displayName> <description>OTG_HS host channel-10 interrupt mask register</description> <addressOffset>0x24C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCINTMSK11</name> <displayName>OTG_HS_HCINTMSK11</displayName> <description>OTG_HS host channel-11 interrupt mask register</description> <addressOffset>0x26C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CHHM</name> <description>Channel halted mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHBERR</name> <description>AHB error</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STALLM</name> <description>STALL response received interrupt mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK response received interrupt mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACKM</name> <description>ACK response received/transmitted interrupt mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>response received interrupt mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXERRM</name> <description>Transaction error mask</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BBERRM</name> <description>Babble error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FRMORM</name> <description>Frame overrun mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DTERRM</name> <description>Data toggle error mask</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ0</name> <displayName>OTG_HS_HCTSIZ0</displayName> <description>OTG_HS host channel-11 transfer size register</description> <addressOffset>0x110</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ1</name> <displayName>OTG_HS_HCTSIZ1</displayName> <description>OTG_HS host channel-1 transfer size register</description> <addressOffset>0x130</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ2</name> <displayName>OTG_HS_HCTSIZ2</displayName> <description>OTG_HS host channel-2 transfer size register</description> <addressOffset>0x150</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ3</name> <displayName>OTG_HS_HCTSIZ3</displayName> <description>OTG_HS host channel-3 transfer size register</description> <addressOffset>0x170</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ4</name> <displayName>OTG_HS_HCTSIZ4</displayName> <description>OTG_HS host channel-4 transfer size register</description> <addressOffset>0x190</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ5</name> <displayName>OTG_HS_HCTSIZ5</displayName> <description>OTG_HS host channel-5 transfer size register</description> <addressOffset>0x1B0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ6</name> <displayName>OTG_HS_HCTSIZ6</displayName> <description>OTG_HS host channel-6 transfer size register</description> <addressOffset>0x1D0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ7</name> <displayName>OTG_HS_HCTSIZ7</displayName> <description>OTG_HS host channel-7 transfer size register</description> <addressOffset>0x1F0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ8</name> <displayName>OTG_HS_HCTSIZ8</displayName> <description>OTG_HS host channel-8 transfer size register</description> <addressOffset>0x210</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ9</name> <displayName>OTG_HS_HCTSIZ9</displayName> <description>OTG_HS host channel-9 transfer size register</description> <addressOffset>0x230</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ10</name> <displayName>OTG_HS_HCTSIZ10</displayName> <description>OTG_HS host channel-10 transfer size register</description> <addressOffset>0x250</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCTSIZ11</name> <displayName>OTG_HS_HCTSIZ11</displayName> <description>OTG_HS host channel-11 transfer size register</description> <addressOffset>0x270</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>DPID</name> <description>Data PID</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA0</name> <displayName>OTG_HS_HCDMA0</displayName> <description>OTG_HS host channel-0 DMA address register</description> <addressOffset>0x114</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA1</name> <displayName>OTG_HS_HCDMA1</displayName> <description>OTG_HS host channel-1 DMA address register</description> <addressOffset>0x134</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA2</name> <displayName>OTG_HS_HCDMA2</displayName> <description>OTG_HS host channel-2 DMA address register</description> <addressOffset>0x154</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA3</name> <displayName>OTG_HS_HCDMA3</displayName> <description>OTG_HS host channel-3 DMA address register</description> <addressOffset>0x174</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA4</name> <displayName>OTG_HS_HCDMA4</displayName> <description>OTG_HS host channel-4 DMA address register</description> <addressOffset>0x194</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA5</name> <displayName>OTG_HS_HCDMA5</displayName> <description>OTG_HS host channel-5 DMA address register</description> <addressOffset>0x1B4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA6</name> <displayName>OTG_HS_HCDMA6</displayName> <description>OTG_HS host channel-6 DMA address register</description> <addressOffset>0x1D4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA7</name> <displayName>OTG_HS_HCDMA7</displayName> <description>OTG_HS host channel-7 DMA address register</description> <addressOffset>0x1F4</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA8</name> <displayName>OTG_HS_HCDMA8</displayName> <description>OTG_HS host channel-8 DMA address register</description> <addressOffset>0x214</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA9</name> <displayName>OTG_HS_HCDMA9</displayName> <description>OTG_HS host channel-9 DMA address register</description> <addressOffset>0x234</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA10</name> <displayName>OTG_HS_HCDMA10</displayName> <description>OTG_HS host channel-10 DMA address register</description> <addressOffset>0x254</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_HCDMA11</name> <displayName>OTG_HS_HCDMA11</displayName> <description>OTG_HS host channel-11 DMA address register</description> <addressOffset>0x274</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_HS_DEVICE</name> <description>USB on the go high speed</description> <groupName>USB_OTG_HS</groupName> <baseAddress>0x40040800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>OTG_HS_DCFG</name> <displayName>OTG_HS_DCFG</displayName> <description>OTG_HS device configuration register</description> <addressOffset>0x0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x02200000</resetValue> <fields> <field> <name>DSPD</name> <description>Device speed</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NZLSOHSK</name> <description>Nonzero-length status OUT handshake</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DAD</name> <description>Device address</description> <bitOffset>4</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PFIVL</name> <description>Periodic (micro)frame interval</description> <bitOffset>11</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PERSCHIVL</name> <description>Periodic scheduling interval</description> <bitOffset>24</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DCTL</name> <displayName>OTG_HS_DCTL</displayName> <description>OTG_HS device control register</description> <addressOffset>0x4</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>RWUSIG</name> <description>Remote wakeup signaling</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>SDIS</name> <description>Soft disconnect</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>GINSTS</name> <description>Global IN NAK status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>GONSTS</name> <description>Global OUT NAK status</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TCTL</name> <description>Test control</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> <access>read-write</access> </field> <field> <name>SGINAK</name> <description>Set global IN NAK</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CGINAK</name> <description>Clear global IN NAK</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SGONAK</name> <description>Set global OUT NAK</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CGONAK</name> <description>Clear global OUT NAK</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>POPRGDNE</name> <description>Power-on programming done</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DSTS</name> <displayName>OTG_HS_DSTS</displayName> <description>OTG_HS device status register</description> <addressOffset>0x8</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x00000010</resetValue> <fields> <field> <name>SUSPSTS</name> <description>Suspend status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENUMSPD</name> <description>Enumerated speed</description> <bitOffset>1</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>EERR</name> <description>Erratic error</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FNSOF</name> <description>Frame number of the received SOF</description> <bitOffset>8</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPMSK</name> <displayName>OTG_HS_DIEPMSK</displayName> <description>OTG_HS device IN endpoint common interrupt mask register</description> <addressOffset>0x10</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDM</name> <description>Endpoint disabled interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TOM</name> <description>Timeout condition mask (nonisochronous endpoints)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITTXFEMSK</name> <description>IN token received when TxFIFO empty mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNMM</name> <description>IN token received with EP mismatch mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNEM</name> <description>IN endpoint NAK effective mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFURM</name> <description>FIFO underrun mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIM</name> <description>BNA interrupt mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPMSK</name> <displayName>OTG_HS_DOEPMSK</displayName> <description>OTG_HS device OUT endpoint common interrupt mask register</description> <addressOffset>0x14</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDM</name> <description>Endpoint disabled interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUPM</name> <description>SETUP phase done mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDM</name> <description>OUT token received when endpoint disabled mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OPEM</name> <description>OUT packet error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BOIM</name> <description>BNA interrupt mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DAINT</name> <displayName>OTG_HS_DAINT</displayName> <description>OTG_HS device all endpoints interrupt register</description> <addressOffset>0x18</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>IEPINT</name> <description>IN endpoint interrupt bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>OEPINT</name> <description>OUT endpoint interrupt bits</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DAINTMSK</name> <displayName>OTG_HS_DAINTMSK</displayName> <description>OTG_HS all endpoints interrupt mask register</description> <addressOffset>0x1C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>IEPM</name> <description>IN EP interrupt mask bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>OEPM</name> <description>OUT EP interrupt mask bits</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DVBUSDIS</name> <displayName>OTG_HS_DVBUSDIS</displayName> <description>OTG_HS device VBUS discharge time register</description> <addressOffset>0x28</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x000017D7</resetValue> <fields> <field> <name>VBUSDT</name> <description>Device VBUS discharge time</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DVBUSPULSE</name> <displayName>OTG_HS_DVBUSPULSE</displayName> <description>OTG_HS device VBUS pulsing time register</description> <addressOffset>0x2C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x000005B8</resetValue> <fields> <field> <name>DVBUSP</name> <description>Device VBUS pulsing time</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DTHRCTL</name> <displayName>OTG_HS_DTHRCTL</displayName> <description>OTG_HS Device threshold control register</description> <addressOffset>0x30</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>NONISOTHREN</name> <description>Nonisochronous IN endpoints threshold enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ISOTHREN</name> <description>ISO IN endpoint threshold enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXTHRLEN</name> <description>Transmit threshold length</description> <bitOffset>2</bitOffset> <bitWidth>9</bitWidth> </field> <field> <name>RXTHREN</name> <description>Receive threshold enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RXTHRLEN</name> <description>Receive threshold length</description> <bitOffset>17</bitOffset> <bitWidth>9</bitWidth> </field> <field> <name>ARPEN</name> <description>Arbiter parking enable</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPEMPMSK</name> <displayName>OTG_HS_DIEPEMPMSK</displayName> <description>OTG_HS device IN endpoint FIFO empty interrupt mask register</description> <addressOffset>0x34</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>INEPTXFEM</name> <description>IN EP Tx FIFO empty interrupt mask bits</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DEACHINT</name> <displayName>OTG_HS_DEACHINT</displayName> <description>OTG_HS device each endpoint interrupt register</description> <addressOffset>0x38</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>IEP1INT</name> <description>IN endpoint 1interrupt bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OEP1INT</name> <description>OUT endpoint 1 interrupt bit</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DEACHINTMSK</name> <displayName>OTG_HS_DEACHINTMSK</displayName> <description>OTG_HS device each endpoint interrupt register mask</description> <addressOffset>0x3C</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>IEP1INTM</name> <description>IN Endpoint 1 interrupt mask bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OEP1INTM</name> <description>OUT Endpoint 1 interrupt mask bit</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPEACHMSK1</name> <displayName>OTG_HS_DIEPEACHMSK1</displayName> <description>OTG_HS device each in endpoint-1 interrupt register</description> <addressOffset>0x40</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDM</name> <description>Endpoint disabled interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TOM</name> <description>Timeout condition mask (nonisochronous endpoints)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITTXFEMSK</name> <description>IN token received when TxFIFO empty mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNMM</name> <description>IN token received with EP mismatch mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNEM</name> <description>IN endpoint NAK effective mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFURM</name> <description>FIFO underrun mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIM</name> <description>BNA interrupt mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK interrupt mask</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPEACHMSK1</name> <displayName>OTG_HS_DOEPEACHMSK1</displayName> <description>OTG_HS device each OUT endpoint-1 interrupt register</description> <addressOffset>0x80</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRCM</name> <description>Transfer completed interrupt mask</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDM</name> <description>Endpoint disabled interrupt mask</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TOM</name> <description>Timeout condition mask</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITTXFEMSK</name> <description>IN token received when TxFIFO empty mask</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNMM</name> <description>IN token received with EP mismatch mask</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INEPNEM</name> <description>IN endpoint NAK effective mask</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TXFURM</name> <description>OUT packet error mask</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BIM</name> <description>BNA interrupt mask</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BERRM</name> <description>Bubble error interrupt mask</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NAKM</name> <description>NAK interrupt mask</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYETM</name> <description>NYET interrupt mask</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL0</name> <displayName>OTG_HS_DIEPCTL0</displayName> <description>OTG device endpoint-0 control register</description> <addressOffset>0x100</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL1</name> <displayName>OTG_HS_DIEPCTL1</displayName> <description>OTG device endpoint-1 control register</description> <addressOffset>0x120</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL2</name> <displayName>OTG_HS_DIEPCTL2</displayName> <description>OTG device endpoint-2 control register</description> <addressOffset>0x140</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL3</name> <displayName>OTG_HS_DIEPCTL3</displayName> <description>OTG device endpoint-3 control register</description> <addressOffset>0x160</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL4</name> <displayName>OTG_HS_DIEPCTL4</displayName> <description>OTG device endpoint-4 control register</description> <addressOffset>0x180</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL5</name> <displayName>OTG_HS_DIEPCTL5</displayName> <description>OTG device endpoint-5 control register</description> <addressOffset>0x1A0</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL6</name> <displayName>OTG_HS_DIEPCTL6</displayName> <description>OTG device endpoint-6 control register</description> <addressOffset>0x1C0</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPCTL7</name> <displayName>OTG_HS_DIEPCTL7</displayName> <description>OTG device endpoint-7 control register</description> <addressOffset>0x1E0</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even/odd frame</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFNUM</name> <description>TxFIFO number</description> <bitOffset>22</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT0</name> <displayName>OTG_HS_DIEPINT0</displayName> <description>OTG device endpoint-0 interrupt register</description> <addressOffset>0x108</addressOffset> <size>32</size> <resetValue>0x00000080</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT1</name> <displayName>OTG_HS_DIEPINT1</displayName> <description>OTG device endpoint-1 interrupt register</description> <addressOffset>0x128</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT2</name> <displayName>OTG_HS_DIEPINT2</displayName> <description>OTG device endpoint-2 interrupt register</description> <addressOffset>0x148</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT3</name> <displayName>OTG_HS_DIEPINT3</displayName> <description>OTG device endpoint-3 interrupt register</description> <addressOffset>0x168</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT4</name> <displayName>OTG_HS_DIEPINT4</displayName> <description>OTG device endpoint-4 interrupt register</description> <addressOffset>0x188</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT5</name> <displayName>OTG_HS_DIEPINT5</displayName> <description>OTG device endpoint-5 interrupt register</description> <addressOffset>0x1A8</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT6</name> <displayName>OTG_HS_DIEPINT6</displayName> <description>OTG device endpoint-6 interrupt register</description> <addressOffset>0x1C8</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPINT7</name> <displayName>OTG_HS_DIEPINT7</displayName> <description>OTG device endpoint-7 interrupt register</description> <addressOffset>0x1E8</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TOC</name> <description>Timeout condition</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ITTXFE</name> <description>IN token received when TxFIFO is empty</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>INEPNE</name> <description>IN endpoint NAK effective</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TXFE</name> <description>Transmit FIFO empty</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>TXFIFOUDRN</name> <description>Transmit Fifo Underrun</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BNA</name> <description>Buffer not available interrupt</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PKTDRPSTS</name> <description>Packet dropped status</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Babble error interrupt</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>NAK</name> <description>NAK interrupt</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DIEPTSIZ0</name> <displayName>OTG_HS_DIEPTSIZ0</displayName> <description>OTG_HS device IN endpoint 0 transfer size register</description> <addressOffset>0x110</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPDMA1</name> <displayName>OTG_HS_DIEPDMA1</displayName> <description>OTG_HS device endpoint-1 DMA address register</description> <addressOffset>0x114</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPDMA2</name> <displayName>OTG_HS_DIEPDMA2</displayName> <description>OTG_HS device endpoint-2 DMA address register</description> <addressOffset>0x134</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPDMA3</name> <displayName>OTG_HS_DIEPDMA3</displayName> <description>OTG_HS device endpoint-3 DMA address register</description> <addressOffset>0x154</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPDMA4</name> <displayName>OTG_HS_DIEPDMA4</displayName> <description>OTG_HS device endpoint-4 DMA address register</description> <addressOffset>0x174</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPDMA5</name> <displayName>OTG_HS_DIEPDMA5</displayName> <description>OTG_HS device endpoint-5 DMA address register</description> <addressOffset>0x194</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>DMAADDR</name> <description>DMA address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DTXFSTS0</name> <displayName>OTG_HS_DTXFSTS0</displayName> <description>OTG_HS device IN endpoint transmit FIFO status register</description> <addressOffset>0x118</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space avail</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DTXFSTS1</name> <displayName>OTG_HS_DTXFSTS1</displayName> <description>OTG_HS device IN endpoint transmit FIFO status register</description> <addressOffset>0x138</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space avail</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DTXFSTS2</name> <displayName>OTG_HS_DTXFSTS2</displayName> <description>OTG_HS device IN endpoint transmit FIFO status register</description> <addressOffset>0x158</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space avail</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DTXFSTS3</name> <displayName>OTG_HS_DTXFSTS3</displayName> <description>OTG_HS device IN endpoint transmit FIFO status register</description> <addressOffset>0x178</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space avail</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DTXFSTS4</name> <displayName>OTG_HS_DTXFSTS4</displayName> <description>OTG_HS device IN endpoint transmit FIFO status register</description> <addressOffset>0x198</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space avail</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DTXFSTS5</name> <displayName>OTG_HS_DTXFSTS5</displayName> <description>OTG_HS device IN endpoint transmit FIFO status register</description> <addressOffset>0x1B8</addressOffset> <size>32</size> <access>read-only</access> <resetValue>0x0</resetValue> <fields> <field> <name>INEPTFSAV</name> <description>IN endpoint TxFIFO space avail</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTSIZ1</name> <displayName>OTG_HS_DIEPTSIZ1</displayName> <description>OTG_HS device endpoint transfer size register</description> <addressOffset>0x130</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTSIZ2</name> <displayName>OTG_HS_DIEPTSIZ2</displayName> <description>OTG_HS device endpoint transfer size register</description> <addressOffset>0x150</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTSIZ3</name> <displayName>OTG_HS_DIEPTSIZ3</displayName> <description>OTG_HS device endpoint transfer size register</description> <addressOffset>0x170</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTSIZ4</name> <displayName>OTG_HS_DIEPTSIZ4</displayName> <description>OTG_HS device endpoint transfer size register</description> <addressOffset>0x190</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DIEPTSIZ5</name> <displayName>OTG_HS_DIEPTSIZ5</displayName> <description>OTG_HS device endpoint transfer size register</description> <addressOffset>0x1B0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>MCNT</name> <description>Multi count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPCTL0</name> <displayName>OTG_HS_DOEPCTL0</displayName> <description>OTG_HS device control OUT endpoint 0 control register</description> <addressOffset>0x300</addressOffset> <size>32</size> <resetValue>0x00008000</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-only</access> </field> <field> <name>SNPM</name> <description>Snoop mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> </fields> </register> <register> <name>OTG_HS_DOEPCTL1</name> <displayName>OTG_HS_DOEPCTL1</displayName> <description>OTG device endpoint-1 control register</description> <addressOffset>0x320</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even odd frame/Endpoint data PID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>SNPM</name> <description>Snoop mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID/Set even frame</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DOEPCTL2</name> <displayName>OTG_HS_DOEPCTL2</displayName> <description>OTG device endpoint-2 control register</description> <addressOffset>0x340</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even odd frame/Endpoint data PID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>SNPM</name> <description>Snoop mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID/Set even frame</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DOEPCTL3</name> <displayName>OTG_HS_DOEPCTL3</displayName> <description>OTG device endpoint-3 control register</description> <addressOffset>0x360</addressOffset> <size>32</size> <resetValue>0x0</resetValue> <fields> <field> <name>MPSIZ</name> <description>Maximum packet size</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> <access>read-write</access> </field> <field> <name>USBAEP</name> <description>USB active endpoint</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EONUM_DPID</name> <description>Even odd frame/Endpoint data PID</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>NAKSTS</name> <description>NAK status</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EPTYP</name> <description>Endpoint type</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> <field> <name>SNPM</name> <description>Snoop mode</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>Stall</name> <description>STALL handshake</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>CNAK</name> <description>Clear NAK</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SNAK</name> <description>Set NAK</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SD0PID_SEVNFRM</name> <description>Set DATA0 PID/Set even frame</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>SODDFRM</name> <description>Set odd frame</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>EPDIS</name> <description>Endpoint disable</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>EPENA</name> <description>Endpoint enable</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT0</name> <displayName>OTG_HS_DOEPINT0</displayName> <description>OTG_HS device endpoint-0 interrupt register</description> <addressOffset>0x308</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x00000080</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT1</name> <displayName>OTG_HS_DOEPINT1</displayName> <description>OTG_HS device endpoint-1 interrupt register</description> <addressOffset>0x328</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT2</name> <displayName>OTG_HS_DOEPINT2</displayName> <description>OTG_HS device endpoint-2 interrupt register</description> <addressOffset>0x348</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT3</name> <displayName>OTG_HS_DOEPINT3</displayName> <description>OTG_HS device endpoint-3 interrupt register</description> <addressOffset>0x368</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT4</name> <displayName>OTG_HS_DOEPINT4</displayName> <description>OTG_HS device endpoint-4 interrupt register</description> <addressOffset>0x388</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT5</name> <displayName>OTG_HS_DOEPINT5</displayName> <description>OTG_HS device endpoint-5 interrupt register</description> <addressOffset>0x3A8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT6</name> <displayName>OTG_HS_DOEPINT6</displayName> <description>OTG_HS device endpoint-6 interrupt register</description> <addressOffset>0x3C8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPINT7</name> <displayName>OTG_HS_DOEPINT7</displayName> <description>OTG_HS device endpoint-7 interrupt register</description> <addressOffset>0x3E8</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRC</name> <description>Transfer completed interrupt</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EPDISD</name> <description>Endpoint disabled interrupt</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUP</name> <description>SETUP phase done</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OTEPDIS</name> <description>OUT token received when endpoint disabled</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>B2BSTUP</name> <description>Back-to-back SETUP packets received</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NYET</name> <description>NYET interrupt</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPTSIZ0</name> <displayName>OTG_HS_DOEPTSIZ0</displayName> <description>OTG_HS device endpoint-1 transfer size register</description> <addressOffset>0x310</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STUPCNT</name> <description>SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPTSIZ1</name> <displayName>OTG_HS_DOEPTSIZ1</displayName> <description>OTG_HS device endpoint-2 transfer size register</description> <addressOffset>0x330</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>RXDPID_STUPCNT</name> <description>Received data PID/SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPTSIZ2</name> <displayName>OTG_HS_DOEPTSIZ2</displayName> <description>OTG_HS device endpoint-3 transfer size register</description> <addressOffset>0x350</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>RXDPID_STUPCNT</name> <description>Received data PID/SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPTSIZ3</name> <displayName>OTG_HS_DOEPTSIZ3</displayName> <description>OTG_HS device endpoint-4 transfer size register</description> <addressOffset>0x370</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>RXDPID_STUPCNT</name> <description>Received data PID/SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>OTG_HS_DOEPTSIZ4</name> <displayName>OTG_HS_DOEPTSIZ4</displayName> <description>OTG_HS device endpoint-5 transfer size register</description> <addressOffset>0x390</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>XFRSIZ</name> <description>Transfer size</description> <bitOffset>0</bitOffset> <bitWidth>19</bitWidth> </field> <field> <name>PKTCNT</name> <description>Packet count</description> <bitOffset>19</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>RXDPID_STUPCNT</name> <description>Received data PID/SETUP packet count</description> <bitOffset>29</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>OTG_HS_PWRCLK</name> <description>USB on the go high speed</description> <groupName>USB_OTG_HS</groupName> <baseAddress>0x40040E00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x3F200</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>OTG_HS_PCGCR</name> <displayName>OTG_HS_PCGCR</displayName> <description>Power and clock gating control register</description> <addressOffset>0x0</addressOffset> <size>32</size> <access>read-write</access> <resetValue>0x0</resetValue> <fields> <field> <name>STPPCLK</name> <description>Stop PHY clock</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GATEHCLK</name> <description>Gate HCLK</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PHYSUSP</name> <description>PHY suspended</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FMC</name> <description>Flexible memory controller</description> <groupName>FSMC</groupName> <baseAddress>0xA0000000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>FMC</name> <description>FSMC global interrupt</description> <value>48</value> </interrupt> <registers> <register> <name>BCR1</name> <displayName>BCR1</displayName> <description>SRAM/NOR-Flash chip-select control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000030D0</resetValue> <fields> <field> <name>CCLKEN</name> <description>CCLKEN</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CBURSTRW</name> <description>CBURSTRW</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPSIZE</name> <description>CPSIZE</description> <bitOffset>16</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ASYNCWAIT</name> <description>ASYNCWAIT</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTMOD</name> <description>EXTMOD</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITEN</name> <description>WAITEN</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WREN</name> <description>WREN</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITCFG</name> <description>WAITCFG</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WRAPMOD</name> <description>WRAPMOD</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITPOL</name> <description>WAITPOL</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BURSTEN</name> <description>BURSTEN</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACCEN</name> <description>FACCEN</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MWID</name> <description>MWID</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MTYP</name> <description>MTYP</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MUXEN</name> <description>MUXEN</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MBKEN</name> <description>MBKEN</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BTR1</name> <displayName>BTR1</displayName> <description>SRAM/NOR-Flash chip-select timing register 1</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DATLAT</name> <description>DATLAT</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>CLKDIV</name> <description>CLKDIV</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DATAST</name> <description>DATAST</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BCR2</name> <displayName>BCR2</displayName> <description>SRAM/NOR-Flash chip-select control register 2</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000030D0</resetValue> <fields> <field> <name>CBURSTRW</name> <description>CBURSTRW</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPSIZE</name> <description>CPSIZE</description> <bitOffset>16</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ASYNCWAIT</name> <description>ASYNCWAIT</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTMOD</name> <description>EXTMOD</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITEN</name> <description>WAITEN</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WREN</name> <description>WREN</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITCFG</name> <description>WAITCFG</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WRAPMOD</name> <description>WRAPMOD</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITPOL</name> <description>WAITPOL</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BURSTEN</name> <description>BURSTEN</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACCEN</name> <description>FACCEN</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MWID</name> <description>MWID</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MTYP</name> <description>MTYP</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MUXEN</name> <description>MUXEN</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MBKEN</name> <description>MBKEN</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BTR2</name> <displayName>BTR2</displayName> <description>SRAM/NOR-Flash chip-select timing register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DATLAT</name> <description>DATLAT</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>CLKDIV</name> <description>CLKDIV</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DATAST</name> <description>DATAST</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BCR3</name> <displayName>BCR3</displayName> <description>SRAM/NOR-Flash chip-select control register 3</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000030D0</resetValue> <fields> <field> <name>CBURSTRW</name> <description>CBURSTRW</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPSIZE</name> <description>CPSIZE</description> <bitOffset>16</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ASYNCWAIT</name> <description>ASYNCWAIT</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTMOD</name> <description>EXTMOD</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITEN</name> <description>WAITEN</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WREN</name> <description>WREN</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITCFG</name> <description>WAITCFG</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WRAPMOD</name> <description>WRAPMOD</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITPOL</name> <description>WAITPOL</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BURSTEN</name> <description>BURSTEN</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACCEN</name> <description>FACCEN</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MWID</name> <description>MWID</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MTYP</name> <description>MTYP</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MUXEN</name> <description>MUXEN</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MBKEN</name> <description>MBKEN</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BTR3</name> <displayName>BTR3</displayName> <description>SRAM/NOR-Flash chip-select timing register 3</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DATLAT</name> <description>DATLAT</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>CLKDIV</name> <description>CLKDIV</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DATAST</name> <description>DATAST</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BCR4</name> <displayName>BCR4</displayName> <description>SRAM/NOR-Flash chip-select control register 4</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000030D0</resetValue> <fields> <field> <name>CBURSTRW</name> <description>CBURSTRW</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CPSIZE</name> <description>CPSIZE</description> <bitOffset>16</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ASYNCWAIT</name> <description>ASYNCWAIT</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>EXTMOD</name> <description>EXTMOD</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITEN</name> <description>WAITEN</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WREN</name> <description>WREN</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITCFG</name> <description>WAITCFG</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WRAPMOD</name> <description>WRAPMOD</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WAITPOL</name> <description>WAITPOL</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BURSTEN</name> <description>BURSTEN</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FACCEN</name> <description>FACCEN</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MWID</name> <description>MWID</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MTYP</name> <description>MTYP</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MUXEN</name> <description>MUXEN</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MBKEN</name> <description>MBKEN</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BTR4</name> <displayName>BTR4</displayName> <description>SRAM/NOR-Flash chip-select timing register 4</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFFFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>DATLAT</name> <description>DATLAT</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>CLKDIV</name> <description>CLKDIV</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>DATAST</name> <description>DATAST</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>PCR2</name> <displayName>PCR2</displayName> <description>PC Card/NAND Flash control register 2</description> <addressOffset>0x60</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000018</resetValue> <fields> <field> <name>ECCPS</name> <description>ECCPS</description> <bitOffset>17</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TAR</name> <description>TAR</description> <bitOffset>13</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TCLR</name> <description>TCLR</description> <bitOffset>9</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ECCEN</name> <description>ECCEN</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWID</name> <description>PWID</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PTYP</name> <description>PTYP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PBKEN</name> <description>PBKEN</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWAITEN</name> <description>PWAITEN</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR2</name> <displayName>SR2</displayName> <description>FIFO status and interrupt register 2</description> <addressOffset>0x64</addressOffset> <size>0x20</size> <resetValue>0x00000040</resetValue> <fields> <field> <name>FEMPT</name> <description>FEMPT</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>IFEN</name> <description>IFEN</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ILEN</name> <description>ILEN</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IREN</name> <description>IREN</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IFS</name> <description>IFS</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ILS</name> <description>ILS</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IRS</name> <description>IRS</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>PMEM2</name> <displayName>PMEM2</displayName> <description>Common memory space timing register 2</description> <addressOffset>0x68</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFCFCFCFC</resetValue> <fields> <field> <name>MEMHIZx</name> <description>MEMHIZx</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMHOLDx</name> <description>MEMHOLDx</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMWAITx</name> <description>MEMWAITx</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMSETx</name> <description>MEMSETx</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>PATT2</name> <displayName>PATT2</displayName> <description>Attribute memory space timing register 2</description> <addressOffset>0x6C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFCFCFCFC</resetValue> <fields> <field> <name>ATTHIZx</name> <description>ATTHIZx</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTHOLDx</name> <description>ATTHOLDx</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTWAITx</name> <description>ATTWAITx</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTSETx</name> <description>ATTSETx</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ECCR2</name> <displayName>ECCR2</displayName> <description>ECC result register 2</description> <addressOffset>0x74</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ECCx</name> <description>ECCx</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>PCR3</name> <displayName>PCR3</displayName> <description>PC Card/NAND Flash control register 3</description> <addressOffset>0x80</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000018</resetValue> <fields> <field> <name>ECCPS</name> <description>ECCPS</description> <bitOffset>17</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TAR</name> <description>TAR</description> <bitOffset>13</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TCLR</name> <description>TCLR</description> <bitOffset>9</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ECCEN</name> <description>ECCEN</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWID</name> <description>PWID</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PTYP</name> <description>PTYP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PBKEN</name> <description>PBKEN</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWAITEN</name> <description>PWAITEN</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR3</name> <displayName>SR3</displayName> <description>FIFO status and interrupt register 3</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <resetValue>0x00000040</resetValue> <fields> <field> <name>FEMPT</name> <description>FEMPT</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>IFEN</name> <description>IFEN</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ILEN</name> <description>ILEN</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IREN</name> <description>IREN</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IFS</name> <description>IFS</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ILS</name> <description>ILS</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IRS</name> <description>IRS</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>PMEM3</name> <displayName>PMEM3</displayName> <description>Common memory space timing register 3</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFCFCFCFC</resetValue> <fields> <field> <name>MEMHIZx</name> <description>MEMHIZx</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMHOLDx</name> <description>MEMHOLDx</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMWAITx</name> <description>MEMWAITx</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMSETx</name> <description>MEMSETx</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>PATT3</name> <displayName>PATT3</displayName> <description>Attribute memory space timing register 3</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFCFCFCFC</resetValue> <fields> <field> <name>ATTHIZx</name> <description>ATTHIZx</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTHOLDx</name> <description>ATTHOLDx</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTWAITx</name> <description>ATTWAITx</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTSETx</name> <description>ATTSETx</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ECCR3</name> <displayName>ECCR3</displayName> <description>ECC result register 3</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ECCx</name> <description>ECCx</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>PCR4</name> <displayName>PCR4</displayName> <description>PC Card/NAND Flash control register 4</description> <addressOffset>0xA0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000018</resetValue> <fields> <field> <name>ECCPS</name> <description>ECCPS</description> <bitOffset>17</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>TAR</name> <description>TAR</description> <bitOffset>13</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TCLR</name> <description>TCLR</description> <bitOffset>9</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ECCEN</name> <description>ECCEN</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWID</name> <description>PWID</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>PTYP</name> <description>PTYP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PBKEN</name> <description>PBKEN</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PWAITEN</name> <description>PWAITEN</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SR4</name> <displayName>SR4</displayName> <description>FIFO status and interrupt register 4</description> <addressOffset>0xA4</addressOffset> <size>0x20</size> <resetValue>0x00000040</resetValue> <fields> <field> <name>FEMPT</name> <description>FEMPT</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>IFEN</name> <description>IFEN</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ILEN</name> <description>ILEN</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IREN</name> <description>IREN</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IFS</name> <description>IFS</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ILS</name> <description>ILS</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>IRS</name> <description>IRS</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>PMEM4</name> <displayName>PMEM4</displayName> <description>Common memory space timing register 4</description> <addressOffset>0xA8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFCFCFCFC</resetValue> <fields> <field> <name>MEMHIZx</name> <description>MEMHIZx</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMHOLDx</name> <description>MEMHOLDx</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMWAITx</name> <description>MEMWAITx</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>MEMSETx</name> <description>MEMSETx</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>PATT4</name> <displayName>PATT4</displayName> <description>Attribute memory space timing register 4</description> <addressOffset>0xAC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFCFCFCFC</resetValue> <fields> <field> <name>ATTHIZx</name> <description>ATTHIZx</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTHOLDx</name> <description>ATTHOLDx</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTWAITx</name> <description>ATTWAITx</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ATTSETx</name> <description>ATTSETx</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>PIO4</name> <displayName>PIO4</displayName> <description>I/O space timing register 4</description> <addressOffset>0xB0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0xFCFCFCFC</resetValue> <fields> <field> <name>IOHIZx</name> <description>IOHIZx</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IOHOLDx</name> <description>IOHOLDx</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IOWAITx</name> <description>IOWAITx</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IOSETx</name> <description>IOSETx</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>BWTR1</name> <displayName>BWTR1</displayName> <description>SRAM/NOR-Flash write timing registers 1</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BWTR2</name> <displayName>BWTR2</displayName> <description>SRAM/NOR-Flash write timing registers 2</description> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BWTR3</name> <displayName>BWTR3</displayName> <description>SRAM/NOR-Flash write timing registers 3</description> <alternateRegister>BWTR1</alternateRegister> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>BWTR4</name> <displayName>BWTR4</displayName> <description>SRAM/NOR-Flash write timing registers 4</description> <alternateRegister>BWTR2</alternateRegister> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFFFFFF</resetValue> <fields> <field> <name>ACCMOD</name> <description>ACCMOD</description> <bitOffset>28</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>BUSTURN</name> <description>BUSTURN</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDHLD</name> <description>ADDHLD</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ADDSET</name> <description>ADDSET</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>SDCR1</name> <displayName>SDCR1</displayName> <description>SDRAM Control Register 1</description> <addressOffset>0x140</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000002D0</resetValue> <fields> <field> <name>NC</name> <description>Number of column address bits</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NR</name> <description>Number of row address bits</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MWID</name> <description>Memory data bus width</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NB</name> <description>Number of internal banks</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAS</name> <description>CAS latency</description> <bitOffset>7</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>WP</name> <description>Write protection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDCLK</name> <description>SDRAM clock configuration</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>RBURST</name> <description>Burst read</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RPIPE</name> <description>Read pipe</description> <bitOffset>13</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>SDCR2</name> <displayName>SDCR2</displayName> <description>SDRAM Control Register 2</description> <addressOffset>0x144</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x000002D0</resetValue> <fields> <field> <name>NC</name> <description>Number of column address bits</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NR</name> <description>Number of row address bits</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MWID</name> <description>Memory data bus width</description> <bitOffset>4</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>NB</name> <description>Number of internal banks</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAS</name> <description>CAS latency</description> <bitOffset>7</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>WP</name> <description>Write protection</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SDCLK</name> <description>SDRAM clock configuration</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>SDTR1</name> <displayName>SDTR1</displayName> <description>SDRAM Timing register 1</description> <addressOffset>0x148</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFFFFFF</resetValue> <fields> <field> <name>TMRD</name> <description>Load Mode Register to Active</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TXSR</name> <description>Exit self-refresh delay</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRAS</name> <description>Self refresh time</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRC</name> <description>Row cycle delay</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TWR</name> <description>Recovery delay</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRP</name> <description>Row precharge delay</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRCD</name> <description>Row to column delay</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>SDTR2</name> <displayName>SDTR2</displayName> <description>SDRAM Timing register 2</description> <addressOffset>0x14C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0FFFFFFF</resetValue> <fields> <field> <name>TMRD</name> <description>Load Mode Register to Active</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TXSR</name> <description>Exit self-refresh delay</description> <bitOffset>4</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRAS</name> <description>Self refresh time</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRC</name> <description>Row cycle delay</description> <bitOffset>12</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TWR</name> <description>Recovery delay</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRP</name> <description>Row precharge delay</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>TRCD</name> <description>Row to column delay</description> <bitOffset>24</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> <register> <name>SDCMR</name> <displayName>SDCMR</displayName> <description>SDRAM Command Mode register</description> <addressOffset>0x150</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>MODE</name> <description>Command mode</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> <access>write-only</access> </field> <field> <name>CTB2</name> <description>Command target bank 2</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>CTB1</name> <description>Command target bank 1</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>NRFS</name> <description>Number of Auto-refresh</description> <bitOffset>5</bitOffset> <bitWidth>4</bitWidth> <access>read-write</access> </field> <field> <name>MRD</name> <description>Mode Register definition</description> <bitOffset>9</bitOffset> <bitWidth>13</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SDRTR</name> <displayName>SDRTR</displayName> <description>SDRAM Refresh Timer register</description> <addressOffset>0x154</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>CRE</name> <description>Clear Refresh error flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>write-only</access> </field> <field> <name>COUNT</name> <description>Refresh Timer Count</description> <bitOffset>1</bitOffset> <bitWidth>13</bitWidth> <access>read-write</access> </field> <field> <name>REIE</name> <description>RES Interrupt Enable</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SDSR</name> <displayName>SDSR</displayName> <description>SDRAM Status register</description> <addressOffset>0x158</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RE</name> <description>Refresh error flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MODES1</name> <description>Status Mode for Bank 1</description> <bitOffset>1</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODES2</name> <description>Status Mode for Bank 2</description> <bitOffset>3</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>BUSY</name> <description>Busy status</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>I2C3</name> <description>Inter-integrated circuit</description> <groupName>I2C</groupName> <baseAddress>0x40005C00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>I2C3_EV</name> <description>I2C3 event interrupt</description> <value>72</value> </interrupt> <interrupt> <name>I2C3_ER</name> <description>I2C3 error interrupt</description> <value>73</value> </interrupt> <registers> <register> <name>CR1</name> <displayName>CR1</displayName> <description>Control register 1</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>SWRST</name> <description>Software reset</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALERT</name> <description>SMBus alert</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PEC</name> <description>Packet error checking</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>POS</name> <description>Acknowledge/PEC Position (for data reception)</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ACK</name> <description>Acknowledge enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STOP</name> <description>Stop generation</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>START</name> <description>Start generation</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOSTRETCH</name> <description>Clock stretching disable (Slave mode)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENGC</name> <description>General call enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENPEC</name> <description>PEC enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ENARP</name> <description>ARP enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBTYPE</name> <description>SMBus type</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBUS</name> <description>SMBus mode</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PE</name> <description>Peripheral enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CR2</name> <displayName>CR2</displayName> <description>Control register 2</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>LAST</name> <description>DMA last transfer</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN</name> <description>DMA requests enable</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITBUFEN</name> <description>Buffer interrupt enable</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITEVTEN</name> <description>Event interrupt enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ITERREN</name> <description>Error interrupt enable</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FREQ</name> <description>Peripheral clock frequency</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> <register> <name>OAR1</name> <displayName>OAR1</displayName> <description>Own address register 1</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ADDMODE</name> <description>Addressing mode (slave mode)</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADD10</name> <description>Interface address</description> <bitOffset>8</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ADD7</name> <description>Interface address</description> <bitOffset>1</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ADD0</name> <description>Interface address</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>OAR2</name> <displayName>OAR2</displayName> <description>Own address register 2</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>ADD2</name> <description>Interface address</description> <bitOffset>1</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ENDUAL</name> <description>Dual addressing mode enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DR</name> <displayName>DR</displayName> <description>Data register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DR</name> <description>8-bit data register</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SR1</name> <displayName>SR1</displayName> <description>Status register 1</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <resetValue>0x0000</resetValue> <fields> <field> <name>SMBALERT</name> <description>SMBus alert</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TIMEOUT</name> <description>Timeout or Tlow error</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PECERR</name> <description>PEC Error in reception</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>OVR</name> <description>Overrun/Underrun</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>AF</name> <description>Acknowledge failure</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ARLO</name> <description>Arbitration lost (master mode)</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BERR</name> <description>Bus error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>TxE</name> <description>Data register empty (transmitters)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>RxNE</name> <description>Data register not empty (receivers)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>STOPF</name> <description>Stop detection (slave mode)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ADD10</name> <description>10-bit header sent (Master mode)</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BTF</name> <description>Byte transfer finished</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ADDR</name> <description>Address sent (master mode)/matched (slave mode)</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SB</name> <description>Start bit (Master mode)</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> </fields> </register> <register> <name>SR2</name> <displayName>SR2</displayName> <description>Status register 2</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000</resetValue> <fields> <field> <name>PEC</name> <description>acket error checking register</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DUALF</name> <description>Dual flag (Slave mode)</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBHOST</name> <description>SMBus host header (Slave mode)</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SMBDEFAULT</name> <description>SMBus device default address (Slave mode)</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>GENCALL</name> <description>General call address (Slave mode)</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRA</name> <description>Transmitter/receiver</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSY</name> <description>Bus busy</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSL</name> <description>Master/slave</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>Clock control register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>F_S</name> <description>I2C master mode selection</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DUTY</name> <description>Fast mode duty cycle</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCR</name> <description>Clock control register in Fast/Standard mode (Master mode)</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>TRISE</name> <displayName>TRISE</displayName> <description>TRISE register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0002</resetValue> <fields> <field> <name>TRISE</name> <description>Maximum rise time in Fast/Standard mode (Master mode)</description> <bitOffset>0</bitOffset> <bitWidth>6</bitWidth> </field> </fields> </register> <register> <name>FLTR</name> <displayName>FLTR</displayName> <description>I2C FLTR register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000</resetValue> <fields> <field> <name>DNF</name> <description>Digital noise filter</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>ANOFF</name> <description>Analog noise filter OFF</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral derivedFrom="I2C3"> <name>I2C2</name> <baseAddress>0x40005800</baseAddress> <interrupt> <name>I2C2_EV</name> <description>I2C2 event interrupt</description> <value>33</value> </interrupt> <interrupt> <name>I2C2_ER</name> <description>I2C2 error interrupt</description> <value>34</value> </interrupt> </peripheral> <peripheral derivedFrom="I2C3"> <name>I2C1</name> <baseAddress>0x40005400</baseAddress> <interrupt> <name>I2C1_EV</name> <description>I2C1 event interrupt</description> <value>31</value> </interrupt> <interrupt> <name>I2C1_ER</name> <description>I2C1 error interrupt</description> <value>32</value> </interrupt> </peripheral> <peripheral> <name>PWR</name> <description>Power control</description> <groupName>PWR</groupName> <baseAddress>0x40007000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>PVD</name> <description>PVD through EXTI line detection interrupt</description> <value>1</value> </interrupt> <registers> <register> <name>CR</name> <displayName>CR</displayName> <description>power control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000C000</resetValue> <fields> <field> <name>LPDS</name> <description>Low-power deep sleep</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PDDS</name> <description>Power down deepsleep</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CWUF</name> <description>Clear wakeup flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CSBF</name> <description>Clear standby flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PVDE</name> <description>Power voltage detector enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PLS</name> <description>PVD level selection</description> <bitOffset>5</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>DBP</name> <description>Disable backup domain write protection</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FPDS</name> <description>Flash power down in Stop mode</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LPLVDS</name> <description>Low-Power Regulator Low Voltage in deepsleep</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MRLVDS</name> <description>Main regulator low voltage in deepsleep mode</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADCDC1</name> <description>Main regulator low voltage in deepsleep mode</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VOS</name> <description>Regulator voltage scaling output selection</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>ODEN</name> <description>Over-drive enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ODSWEN</name> <description>Over-drive switching enabled</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UDEN</name> <description>Under-drive enable in stop mode</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>CSR</name> <displayName>CSR</displayName> <description>power control/status register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <resetValue>0x00000000</resetValue> <fields> <field> <name>WUF</name> <description>Wakeup flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>SBF</name> <description>Standby flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>PVDO</name> <description>PVD output</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>BRR</name> <description>Backup regulator ready</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>EWUP</name> <description>Enable WKUP pin</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>BRE</name> <description>Backup regulator enable</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>VOSRDY</name> <description>Regulator voltage scaling output selection ready bit</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>ODRDY</name> <description>Over-drive mode ready</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>ODSWRDY</name> <description>Over-drive mode switching ready</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> <access>read-only</access> </field> <field> <name>UDRDY</name> <description>Under-drive ready flag</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> <access>read-write</access> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SAI1</name> <description>Serial audio interface</description> <groupName>SAI</groupName> <baseAddress>0x40015800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>BCR1</name> <displayName>BCR1</displayName> <description>BConfiguration register 1</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000040</resetValue> <fields> <field> <name>MCJDIV</name> <description>Master clock divider</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>NODIV</name> <description>No divider</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN</name> <description>DMA enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SAIBEN</name> <description>Audio block B enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OutDri</name> <description>Output drive</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MONO</name> <description>Mono mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYNCEN</name> <description>Synchronization enable</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKSTR</name> <description>Clock strobing edge</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSBFIRST</name> <description>Least significant bit first</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DS</name> <description>Data size</description> <bitOffset>5</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PRTCFG</name> <description>Protocol configuration</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODE</name> <description>Audio block mode</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>BCR2</name> <displayName>BCR2</displayName> <description>BConfiguration register 2</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>COMP</name> <description>Companding mode</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CPL</name> <description>Complement bit</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTECN</name> <description>Mute counter</description> <bitOffset>7</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>MUTEVAL</name> <description>Mute value</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTE</name> <description>Mute</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRIS</name> <description>Tristate management on data line</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFLUS</name> <description>FIFO flush</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FTH</name> <description>FIFO threshold</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>BFRCR</name> <displayName>BFRCR</displayName> <description>BFRCR</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000007</resetValue> <fields> <field> <name>FSOFF</name> <description>Frame synchronization offset</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSPOL</name> <description>Frame synchronization polarity</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSDEF</name> <description>Frame synchronization definition</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSALL</name> <description>Frame synchronization active level length</description> <bitOffset>8</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>FRL</name> <description>Frame length</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>BSLOTR</name> <displayName>BSLOTR</displayName> <description>BSlot register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SLOTEN</name> <description>Slot enable</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>NBSLOT</name> <description>Number of slots in an audio frame</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SLOTSZ</name> <description>Slot size</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FBOFF</name> <description>First bit offset</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>BIM</name> <displayName>BIM</displayName> <description>BInterrupt mask register2</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LFSDETIE</name> <description>Late frame synchronization detection interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AFSDETIE</name> <description>Anticipated frame synchronization detection interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CNRDYIE</name> <description>Codec not ready interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FREQIE</name> <description>FIFO request interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKCFG</name> <description>Wrong clock configuration interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTEDET</name> <description>Mute detection interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRUDRIE</name> <description>Overrun/underrun interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BSR</name> <displayName>BSR</displayName> <description>BStatus register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FLVL</name> <description>FIFO level threshold</description> <bitOffset>16</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>LFSDET</name> <description>Late frame synchronization detection</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AFSDET</name> <description>Anticipated frame synchronization detection</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CNRDY</name> <description>Codec not ready</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FREQ</name> <description>FIFO request</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKCFG</name> <description>Wrong clock configuration flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTEDET</name> <description>Mute detection</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRUDR</name> <description>Overrun / underrun</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BCLRFR</name> <displayName>BCLRFR</displayName> <description>BClear flag register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LFSDET</name> <description>Clear late frame synchronization detection flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAFSDET</name> <description>Clear anticipated frame synchronization detection flag</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CNRDY</name> <description>Clear codec not ready flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKCFG</name> <description>Clear wrong clock configuration flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTEDET</name> <description>Mute detection flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRUDR</name> <description>Clear overrun / underrun</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BDR</name> <displayName>BDR</displayName> <description>BData register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA</name> <description>Data</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>ACR1</name> <displayName>ACR1</displayName> <description>AConfiguration register 1</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000040</resetValue> <fields> <field> <name>MCJDIV</name> <description>Master clock divider</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>NODIV</name> <description>No divider</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DMAEN</name> <description>DMA enable</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SAIAEN</name> <description>Audio block A enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OutDri</name> <description>Output drive</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MONO</name> <description>Mono mode</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYNCEN</name> <description>Synchronization enable</description> <bitOffset>10</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CKSTR</name> <description>Clock strobing edge</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSBFIRST</name> <description>Least significant bit first</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DS</name> <description>Data size</description> <bitOffset>5</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>PRTCFG</name> <description>Protocol configuration</description> <bitOffset>2</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>MODE</name> <description>Audio block mode</description> <bitOffset>0</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>ACR2</name> <displayName>ACR2</displayName> <description>AConfiguration register 2</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>COMP</name> <description>Companding mode</description> <bitOffset>14</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CPL</name> <description>Complement bit</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTECN</name> <description>Mute counter</description> <bitOffset>7</bitOffset> <bitWidth>6</bitWidth> </field> <field> <name>MUTEVAL</name> <description>Mute value</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTE</name> <description>Mute</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TRIS</name> <description>Tristate management on data line</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FFLUS</name> <description>FIFO flush</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FTH</name> <description>FIFO threshold</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>AFRCR</name> <displayName>AFRCR</displayName> <description>AFRCR</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000007</resetValue> <fields> <field> <name>FSOFF</name> <description>Frame synchronization offset</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSPOL</name> <description>Frame synchronization polarity</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSDEF</name> <description>Frame synchronization definition</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FSALL</name> <description>Frame synchronization active level length</description> <bitOffset>8</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>FRL</name> <description>Frame length</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ASLOTR</name> <displayName>ASLOTR</displayName> <description>ASlot register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SLOTEN</name> <description>Slot enable</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>NBSLOT</name> <description>Number of slots in an audio frame</description> <bitOffset>8</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>SLOTSZ</name> <description>Slot size</description> <bitOffset>6</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FBOFF</name> <description>First bit offset</description> <bitOffset>0</bitOffset> <bitWidth>5</bitWidth> </field> </fields> </register> <register> <name>AIM</name> <displayName>AIM</displayName> <description>AInterrupt mask register2</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LFSDET</name> <description>Late frame synchronization detection interrupt enable</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AFSDETIE</name> <description>Anticipated frame synchronization detection interrupt enable</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CNRDYIE</name> <description>Codec not ready interrupt enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FREQIE</name> <description>FIFO request interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKCFG</name> <description>Wrong clock configuration interrupt enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTEDET</name> <description>Mute detection interrupt enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRUDRIE</name> <description>Overrun/underrun interrupt enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ASR</name> <displayName>ASR</displayName> <description>AStatus register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>FLVL</name> <description>FIFO level threshold</description> <bitOffset>16</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>LFSDET</name> <description>Late frame synchronization detection</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AFSDET</name> <description>Anticipated frame synchronization detection</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CNRDY</name> <description>Codec not ready</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FREQ</name> <description>FIFO request</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKCFG</name> <description>Wrong clock configuration flag. This bit is read only.</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTEDET</name> <description>Mute detection</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRUDR</name> <description>Overrun / underrun</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ACLRFR</name> <displayName>ACLRFR</displayName> <description>AClear flag register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LFSDET</name> <description>Clear late frame synchronization detection flag</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAFSDET</name> <description>Clear anticipated frame synchronization detection flag.</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CNRDY</name> <description>Clear codec not ready flag</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>WCKCFG</name> <description>Clear wrong clock configuration flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUTEDET</name> <description>Mute detection flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OVRUDR</name> <description>Clear overrun / underrun</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ADR</name> <displayName>ADR</displayName> <description>AData register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DATA</name> <description>Data</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>LTDC</name> <description>LCD-TFT Controller</description> <groupName>LTDC</groupName> <baseAddress>0x40016800</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x400</size> <usage>registers</usage> </addressBlock> <interrupt> <name>LCD_TFT</name> <description>LTDC global interrupt</description> <value>88</value> </interrupt> <interrupt> <name>LCD_TFT_1</name> <description>LTDC global error interrupt</description> <value>89</value> </interrupt> <registers> <register> <name>SSCR</name> <displayName>SSCR</displayName> <description>Synchronization Size Configuration Register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>HSW</name> <description>Horizontal Synchronization Width (in units of pixel clock period)</description> <bitOffset>16</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>VSH</name> <description>Vertical Synchronization Height (in units of horizontal scan line)</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>BPCR</name> <displayName>BPCR</displayName> <description>Back Porch Configuration Register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AHBP</name> <description>Accumulated Horizontal back porch (in units of pixel clock period)</description> <bitOffset>16</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>AVBP</name> <description>Accumulated Vertical back porch (in units of horizontal scan line)</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>AWCR</name> <displayName>AWCR</displayName> <description>Active Width Configuration Register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>AAV</name> <description>AAV</description> <bitOffset>16</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>AAH</name> <description>Accumulated Active Height (in units of horizontal scan line)</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>TWCR</name> <displayName>TWCR</displayName> <description>Total Width Configuration Register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TOTALW</name> <description>Total Width (in units of pixel clock period)</description> <bitOffset>16</bitOffset> <bitWidth>10</bitWidth> </field> <field> <name>TOTALH</name> <description>Total Height (in units of horizontal scan line)</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>GCR</name> <displayName>GCR</displayName> <description>Global Control Register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <resetValue>0x00002220</resetValue> <fields> <field> <name>HSPOL</name> <description>Horizontal Synchronization Polarity</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>VSPOL</name> <description>Vertical Synchronization Polarity</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DEPOL</name> <description>Data Enable Polarity</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>PCPOL</name> <description>Pixel Clock Polarity</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DEN</name> <description>Dither Enable</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> <field> <name>DRW</name> <description>Dither Red Width</description> <bitOffset>12</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DGW</name> <description>Dither Green Width</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>DBW</name> <description>Dither Blue Width</description> <bitOffset>4</bitOffset> <bitWidth>3</bitWidth> <access>read-only</access> </field> <field> <name>LTDCEN</name> <description>LCD-TFT controller enable bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> <access>read-write</access> </field> </fields> </register> <register> <name>SRCR</name> <displayName>SRCR</displayName> <description>Shadow Reload Configuration Register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VBR</name> <description>Vertical Blanking Reload</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IMR</name> <description>Immediate Reload</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>BCCR</name> <displayName>BCCR</displayName> <description>Background Color Configuration Register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BC</name> <description>Background Color Red value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>IER</name> <displayName>IER</displayName> <description>Interrupt Enable Register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RRIE</name> <description>Register Reload interrupt enable</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TERRIE</name> <description>Transfer Error Interrupt Enable</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FUIE</name> <description>FIFO Underrun Interrupt Enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LIE</name> <description>Line Interrupt Enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ISR</name> <displayName>ISR</displayName> <description>Interrupt Status Register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>RRIF</name> <description>Register Reload Interrupt Flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TERRIF</name> <description>Transfer Error interrupt flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FUIF</name> <description>FIFO Underrun Interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LIF</name> <description>Line Interrupt flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>ICR</name> <displayName>ICR</displayName> <description>Interrupt Clear Register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CRRIF</name> <description>Clears Register Reload Interrupt Flag</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTERRIF</name> <description>Clears the Transfer Error Interrupt Flag</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CFUIF</name> <description>Clears the FIFO Underrun Interrupt flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CLIF</name> <description>Clears the Line Interrupt Flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LIPCR</name> <displayName>LIPCR</displayName> <description>Line Interrupt Position Configuration Register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LIPOS</name> <description>Line Interrupt Position</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>CPSR</name> <displayName>CPSR</displayName> <description>Current Position Status Register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CXPOS</name> <description>Current X Position</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>CYPOS</name> <description>Current Y Position</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>CDSR</name> <displayName>CDSR</displayName> <description>Current Display Status Register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x0000000F</resetValue> <fields> <field> <name>HSYNCS</name> <description>Horizontal Synchronization display Status</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VSYNCS</name> <description>Vertical Synchronization display Status</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HDES</name> <description>Horizontal Data Enable display Status</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VDES</name> <description>Vertical Data Enable display Status</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>L1CR</name> <displayName>L1CR</displayName> <description>Layerx Control Register</description> <addressOffset>0x84</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLUTEN</name> <description>Color Look-Up Table Enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COLKEN</name> <description>Color Keying Enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LEN</name> <description>Layer Enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>L1WHPCR</name> <displayName>L1WHPCR</displayName> <description>Layerx Window Horizontal Position Configuration Register</description> <addressOffset>0x88</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WHSPPOS</name> <description>Window Horizontal Stop Position</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>WHSTPOS</name> <description>Window Horizontal Start Position</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>L1WVPCR</name> <displayName>L1WVPCR</displayName> <description>Layerx Window Vertical Position Configuration Register</description> <addressOffset>0x8C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WVSPPOS</name> <description>Window Vertical Stop Position</description> <bitOffset>16</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>WVSTPOS</name> <description>Window Vertical Start Position</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>L1CKCR</name> <displayName>L1CKCR</displayName> <description>Layerx Color Keying Configuration Register</description> <addressOffset>0x90</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CKRED</name> <description>Color Key Red value</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>CKGREEN</name> <description>Color Key Green value</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>CKBLUE</name> <description>Color Key Blue value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>L1PFCR</name> <displayName>L1PFCR</displayName> <description>Layerx Pixel Format Configuration Register</description> <addressOffset>0x94</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PF</name> <description>Pixel Format</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>L1CACR</name> <displayName>L1CACR</displayName> <description>Layerx Constant Alpha Configuration Register</description> <addressOffset>0x98</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CONSTA</name> <description>Constant Alpha</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>L1DCCR</name> <displayName>L1DCCR</displayName> <description>Layerx Default Color Configuration Register</description> <addressOffset>0x9C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DCALPHA</name> <description>Default Color Alpha</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DCRED</name> <description>Default Color Red</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DCGREEN</name> <description>Default Color Green</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DCBLUE</name> <description>Default Color Blue</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>L1BFCR</name> <displayName>L1BFCR</displayName> <description>Layerx Blending Factors Configuration Register</description> <addressOffset>0xA0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000607</resetValue> <fields> <field> <name>BF1</name> <description>Blending Factor 1</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>BF2</name> <description>Blending Factor 2</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>L1CFBAR</name> <displayName>L1CFBAR</displayName> <description>Layerx Color Frame Buffer Address Register</description> <addressOffset>0xAC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CFBADD</name> <description>Color Frame Buffer Start Address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>L1CFBLR</name> <displayName>L1CFBLR</displayName> <description>Layerx Color Frame Buffer Length Register</description> <addressOffset>0xB0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CFBP</name> <description>Color Frame Buffer Pitch in bytes</description> <bitOffset>16</bitOffset> <bitWidth>13</bitWidth> </field> <field> <name>CFBLL</name> <description>Color Frame Buffer Line Length</description> <bitOffset>0</bitOffset> <bitWidth>13</bitWidth> </field> </fields> </register> <register> <name>L1CFBLNR</name> <displayName>L1CFBLNR</displayName> <description>Layerx ColorFrame Buffer Line Number Register</description> <addressOffset>0xB4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CFBLNBR</name> <description>Frame Buffer Line Number</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>L1CLUTWR</name> <displayName>L1CLUTWR</displayName> <description>Layerx CLUT Write Register</description> <addressOffset>0xC4</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLUTADD</name> <description>CLUT Address</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>RED</name> <description>Red value</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>GREEN</name> <description>Green value</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>BLUE</name> <description>Blue value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>L2CR</name> <displayName>L2CR</displayName> <description>Layerx Control Register</description> <addressOffset>0x104</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLUTEN</name> <description>Color Look-Up Table Enable</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COLKEN</name> <description>Color Keying Enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LEN</name> <description>Layer Enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>L2WHPCR</name> <displayName>L2WHPCR</displayName> <description>Layerx Window Horizontal Position Configuration Register</description> <addressOffset>0x108</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WHSPPOS</name> <description>Window Horizontal Stop Position</description> <bitOffset>16</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>WHSTPOS</name> <description>Window Horizontal Start Position</description> <bitOffset>0</bitOffset> <bitWidth>12</bitWidth> </field> </fields> </register> <register> <name>L2WVPCR</name> <displayName>L2WVPCR</displayName> <description>Layerx Window Vertical Position Configuration Register</description> <addressOffset>0x10C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>WVSPPOS</name> <description>Window Vertical Stop Position</description> <bitOffset>16</bitOffset> <bitWidth>11</bitWidth> </field> <field> <name>WVSTPOS</name> <description>Window Vertical Start Position</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>L2CKCR</name> <displayName>L2CKCR</displayName> <description>Layerx Color Keying Configuration Register</description> <addressOffset>0x110</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CKRED</name> <description>Color Key Red value</description> <bitOffset>15</bitOffset> <bitWidth>9</bitWidth> </field> <field> <name>CKGREEN</name> <description>Color Key Green value</description> <bitOffset>8</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>CKBLUE</name> <description>Color Key Blue value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>L2PFCR</name> <displayName>L2PFCR</displayName> <description>Layerx Pixel Format Configuration Register</description> <addressOffset>0x114</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PF</name> <description>Pixel Format</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>L2CACR</name> <displayName>L2CACR</displayName> <description>Layerx Constant Alpha Configuration Register</description> <addressOffset>0x118</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CONSTA</name> <description>Constant Alpha</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>L2DCCR</name> <displayName>L2DCCR</displayName> <description>Layerx Default Color Configuration Register</description> <addressOffset>0x11C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DCALPHA</name> <description>Default Color Alpha</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DCRED</name> <description>Default Color Red</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DCGREEN</name> <description>Default Color Green</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>DCBLUE</name> <description>Default Color Blue</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>L2BFCR</name> <displayName>L2BFCR</displayName> <description>Layerx Blending Factors Configuration Register</description> <addressOffset>0x120</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000607</resetValue> <fields> <field> <name>BF1</name> <description>Blending Factor 1</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>BF2</name> <description>Blending Factor 2</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> </fields> </register> <register> <name>L2CFBAR</name> <displayName>L2CFBAR</displayName> <description>Layerx Color Frame Buffer Address Register</description> <addressOffset>0x12C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CFBADD</name> <description>Color Frame Buffer Start Address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>L2CFBLR</name> <displayName>L2CFBLR</displayName> <description>Layerx Color Frame Buffer Length Register</description> <addressOffset>0x130</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CFBP</name> <description>Color Frame Buffer Pitch in bytes</description> <bitOffset>16</bitOffset> <bitWidth>13</bitWidth> </field> <field> <name>CFBLL</name> <description>Color Frame Buffer Line Length</description> <bitOffset>0</bitOffset> <bitWidth>13</bitWidth> </field> </fields> </register> <register> <name>L2CFBLNR</name> <displayName>L2CFBLNR</displayName> <description>Layerx ColorFrame Buffer Line Number Register</description> <addressOffset>0x134</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CFBLNBR</name> <description>Frame Buffer Line Number</description> <bitOffset>0</bitOffset> <bitWidth>11</bitWidth> </field> </fields> </register> <register> <name>L2CLUTWR</name> <displayName>L2CLUTWR</displayName> <description>Layerx CLUT Write Register</description> <addressOffset>0x144</addressOffset> <size>0x20</size> <access>write-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CLUTADD</name> <description>CLUT Address</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>RED</name> <description>Red value</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>GREEN</name> <description>Green value</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>BLUE</name> <description>Blue value</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>DMA2D</name> <description>DMA2D</description> <groupName>DMA2D</groupName> <baseAddress>0x4002B000</baseAddress> <addressBlock> <offset>0x0</offset> <size>0xC00</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>DMA2D_CR</name> <displayName>DMA2D_CR</displayName> <description>DMA2D control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>START</name> <description>Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers. This bit is automatically reset by the following events: ** At the end of the transfer ** When the data transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** When a data transfer error occurs ** When the data transfer has not started due to a configuration error or another transfer operation already ongoing (automatic CLUT loading).</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SUSP</name> <description>Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ABORT</name> <description>Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset.</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEIE</name> <description>Transfer error interrupt enable This bit is set and cleared by software.</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIE</name> <description>Transfer complete interrupt enable This bit is set and cleared by software.</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TWIE</name> <description>Transfer watermark interrupt enable This bit is set and cleared by software.</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAEIE</name> <description>CLUT access error interrupt enable This bit is set and cleared by software.</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIE</name> <description>CLUT transfer complete interrupt enable This bit is set and cleared by software.</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEIE</name> <description>Configuration Error Interrupt Enable This bit is set and cleared by software.</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MODE</name> <description>DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing.</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> </fields> </register> <register> <name>DMA2D_ISR</name> <displayName>DMA2D_ISR</displayName> <description>DMA2D Interrupt Status Register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TEIF</name> <description>Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading).</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TCIF</name> <description>Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only).</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TWIF</name> <description>Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred.</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAEIF</name> <description>CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D.</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF</name> <description>CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CEIF</name> <description>Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed.</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DMA2D_IFCR</name> <displayName>DMA2D_IFCR</displayName> <description>DMA2D interrupt flag clear register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CTEIF</name> <description>Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTCIF</name> <description>Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CTWIF</name> <description>Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CAECIF</name> <description>Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCTCIF</name> <description>Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CCEIF</name> <description>Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DMA2D_FGMAR</name> <displayName>DMA2D_FGMAR</displayName> <description>DMA2D foreground memory address register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMA2D_FGOR</name> <displayName>DMA2D_FGOR</displayName> <description>DMA2D foreground offset register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LO</name> <description>Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.</description> <bitOffset>0</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>DMA2D_BGMAR</name> <displayName>DMA2D_BGMAR</displayName> <description>DMA2D background memory address register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMA2D_BGOR</name> <displayName>DMA2D_BGOR</displayName> <description>DMA2D background offset register</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LO</name> <description>Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even.</description> <bitOffset>0</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>DMA2D_FGPFCCR</name> <displayName>DMA2D_FGPFCCR</displayName> <description>DMA2D foreground PFC control register</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CM</name> <description>Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>CCM</name> <description>CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>START</name> <description>Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer).</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CS</name> <description>CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>AM</name> <description>Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>CSS</name> <description>Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless</description> <bitOffset>18</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>AI</name> <description>Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RBS</name> <description>Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALPHA</name> <description>Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DMA2D_FGCOLR</name> <displayName>DMA2D_FGCOLR</displayName> <description>DMA2D foreground color register</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BLUE</name> <description>Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>GREEN</name> <description>Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>RED</name> <description>Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DMA2D_BGPFCCR</name> <displayName>DMA2D_BGPFCCR</displayName> <description>DMA2D background PFC control register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CM</name> <description>Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>CCM</name> <description>CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>START</name> <description>Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer).</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CS</name> <description>CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>AM</name> <description>Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless</description> <bitOffset>16</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>AI</name> <description>Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RBS</name> <description>Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ALPHA</name> <description>Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DMA2D_BGCOLR</name> <displayName>DMA2D_BGCOLR</displayName> <description>DMA2D background color register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BLUE</name> <description>Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>GREEN</name> <description>Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>RED</name> <description>Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DMA2D_FGCMAR</name> <displayName>DMA2D_FGCMAR</displayName> <description>DMA2D foreground CLUT memory address register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMA2D_BGCMAR</name> <displayName>DMA2D_BGCMAR</displayName> <description>DMA2D background CLUT memory address register</description> <addressOffset>0x30</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMA2D_OPFCCR</name> <displayName>DMA2D_OPFCCR</displayName> <description>DMA2D output PFC control register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>CM</name> <description>Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless</description> <bitOffset>0</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>AI</name> <description>Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only.</description> <bitOffset>20</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RBS</name> <description>Red Blue Swap This bit allows to swap the R &amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only.</description> <bitOffset>21</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>DMA2D_OCOLR</name> <displayName>DMA2D_OCOLR</displayName> <description>DMA2D output color register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BLUE</name> <description>Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>GREEN</name> <description>Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>RED</name> <description>Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>ALPHA</name> <description>Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>DMA2D_OMAR</name> <displayName>DMA2D_OMAR</displayName> <description>DMA2D output memory address register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MA</name> <description>Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>DMA2D_OOR</name> <displayName>DMA2D_OOR</displayName> <description>DMA2D output offset register</description> <addressOffset>0x40</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LO</name> <description>Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>0</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>DMA2D_NLR</name> <displayName>DMA2D_NLR</displayName> <description>DMA2D number of line register</description> <addressOffset>0x44</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NL</name> <description>Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> <field> <name>PL</name> <description>Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even.</description> <bitOffset>16</bitOffset> <bitWidth>14</bitWidth> </field> </fields> </register> <register> <name>DMA2D_LWR</name> <displayName>DMA2D_LWR</displayName> <description>DMA2D line watermark register</description> <addressOffset>0x48</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LW</name> <description>Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only.</description> <bitOffset>0</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>DMA2D_AMTCR</name> <displayName>DMA2D_AMTCR</displayName> <description>DMA2D AXI master timer configuration register</description> <addressOffset>0x4C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>EN</name> <description>Enable Enables the dead time functionality.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DT</name> <description>Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses.</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FPU</name> <description>Floting point unit</description> <groupName>FPU</groupName> <baseAddress>0xE000EF34</baseAddress> <addressBlock> <offset>0x0</offset> <size>0xD</size> <usage>registers</usage> </addressBlock> <interrupt> <name>FPU</name> <description>Floating point unit interrupt</description> <value>81</value> </interrupt> <interrupt> <name>FPU</name> <description>Floating point interrupt</description> <value>81</value> </interrupt> <registers> <register> <name>FPCCR</name> <displayName>FPCCR</displayName> <description>Floating-point context control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>LSPACT</name> <description>LSPACT</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USER</name> <description>USER</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>THREAD</name> <description>THREAD</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HFRDY</name> <description>HFRDY</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMRDY</name> <description>MMRDY</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFRDY</name> <description>BFRDY</description> <bitOffset>6</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MONRDY</name> <description>MONRDY</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSPEN</name> <description>LSPEN</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ASPEN</name> <description>ASPEN</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>FPCAR</name> <displayName>FPCAR</displayName> <description>Floating-point context address register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>ADDRESS</name> <description>Location of unpopulated floating-point</description> <bitOffset>3</bitOffset> <bitWidth>29</bitWidth> </field> </fields> </register> <register> <name>FPSCR</name> <displayName>FPSCR</displayName> <description>Floating-point status control register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IOC</name> <description>Invalid operation cumulative exception bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DZC</name> <description>Division by zero cumulative exception bit.</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>OFC</name> <description>Overflow cumulative exception bit</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UFC</name> <description>Underflow cumulative exception bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IXC</name> <description>Inexact cumulative exception bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IDC</name> <description>Input denormal cumulative exception bit.</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>RMode</name> <description>Rounding Mode control field</description> <bitOffset>22</bitOffset> <bitWidth>2</bitWidth> </field> <field> <name>FZ</name> <description>Flush-to-zero mode control bit:</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DN</name> <description>Default NaN mode control bit</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>AHP</name> <description>Alternative half-precision control bit</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>V</name> <description>Overflow condition code flag</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>C</name> <description>Carry condition code flag</description> <bitOffset>29</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>Z</name> <description>Zero condition code flag</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>N</name> <description>Negative condition code flag</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>MPU</name> <description>Memory protection unit</description> <groupName>MPU</groupName> <baseAddress>0xE000ED90</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x15</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>MPU_TYPER</name> <displayName>MPU_TYPER</displayName> <description>MPU type register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0X00000800</resetValue> <fields> <field> <name>SEPARATE</name> <description>Separate flag</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DREGION</name> <description>Number of MPU data regions</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>IREGION</name> <description>Number of MPU instruction regions</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>MPU_CTRL</name> <displayName>MPU_CTRL</displayName> <description>MPU control register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Enables the MPU</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>HFNMIENA</name> <description>Enables the operation of MPU during hard fault</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRIVDEFENA</name> <description>Enable priviliged software access to default memory map</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MPU_RNR</name> <displayName>MPU_RNR</displayName> <description>MPU region number register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>REGION</name> <description>MPU region</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>MPU_RBAR</name> <displayName>MPU_RBAR</displayName> <description>MPU region base address register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>REGION</name> <description>MPU region field</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>VALID</name> <description>MPU region number valid</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>ADDR</name> <description>Region base address field</description> <bitOffset>5</bitOffset> <bitWidth>27</bitWidth> </field> </fields> </register> <register> <name>MPU_RASR</name> <displayName>MPU_RASR</displayName> <description>MPU region attribute and size register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Region enable bit.</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SIZE</name> <description>Size of the MPU protection region</description> <bitOffset>1</bitOffset> <bitWidth>5</bitWidth> </field> <field> <name>SRD</name> <description>Subregion disable bits</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>B</name> <description>memory attribute</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>C</name> <description>memory attribute</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>S</name> <description>Shareable memory attribute</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TEX</name> <description>memory attribute</description> <bitOffset>19</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>AP</name> <description>Access permission</description> <bitOffset>24</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>XN</name> <description>Instruction access disable bit</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>STK</name> <description>SysTick timer</description> <groupName>STK</groupName> <baseAddress>0xE000E010</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x11</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CTRL</name> <displayName>CTRL</displayName> <description>SysTick control and status register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>ENABLE</name> <description>Counter enable</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>TICKINT</name> <description>SysTick exception request enable</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>CLKSOURCE</name> <description>Clock source selection</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>COUNTFLAG</name> <description>COUNTFLAG</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>LOAD</name> <displayName>LOAD</displayName> <description>SysTick reload value register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>RELOAD</name> <description>RELOAD value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>VAL</name> <displayName>VAL</displayName> <description>SysTick current value register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>CURRENT</name> <description>Current counter value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> </fields> </register> <register> <name>CALIB</name> <displayName>CALIB</displayName> <description>SysTick calibration value register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0X00000000</resetValue> <fields> <field> <name>TENMS</name> <description>Calibration value</description> <bitOffset>0</bitOffset> <bitWidth>24</bitWidth> </field> <field> <name>SKEW</name> <description>SKEW flag: Indicates whether the TENMS value is exact</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOREF</name> <description>NOREF flag. Reads as zero</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SCB</name> <description>System control block</description> <groupName>SCB</groupName> <baseAddress>0xE000ED00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x41</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CPUID</name> <displayName>CPUID</displayName> <description>CPUID base register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-only</access> <resetValue>0x410FC241</resetValue> <fields> <field> <name>Revision</name> <description>Revision number</description> <bitOffset>0</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>PartNo</name> <description>Part number of the processor</description> <bitOffset>4</bitOffset> <bitWidth>12</bitWidth> </field> <field> <name>Constant</name> <description>Reads as 0xF</description> <bitOffset>16</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>Variant</name> <description>Variant number</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> <field> <name>Implementer</name> <description>Implementer code</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>ICSR</name> <displayName>ICSR</displayName> <description>Interrupt control and state register</description> <addressOffset>0x4</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTACTIVE</name> <description>Active vector</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> <field> <name>RETTOBASE</name> <description>Return to base level</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTPENDING</name> <description>Pending vector</description> <bitOffset>12</bitOffset> <bitWidth>7</bitWidth> </field> <field> <name>ISRPENDING</name> <description>Interrupt pending flag</description> <bitOffset>22</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSTCLR</name> <description>SysTick exception clear-pending bit</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSTSET</name> <description>SysTick exception set-pending bit</description> <bitOffset>26</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVCLR</name> <description>PendSV clear-pending bit</description> <bitOffset>27</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVSET</name> <description>PendSV set-pending bit</description> <bitOffset>28</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NMIPENDSET</name> <description>NMI set-pending bit.</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>VTOR</name> <displayName>VTOR</displayName> <description>Vector table offset register</description> <addressOffset>0x8</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>TBLOFF</name> <description>Vector table base offset field</description> <bitOffset>9</bitOffset> <bitWidth>21</bitWidth> </field> </fields> </register> <register> <name>AIRCR</name> <displayName>AIRCR</displayName> <description>Application interrupt and reset control register</description> <addressOffset>0xC</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTRESET</name> <description>VECTRESET</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTCLRACTIVE</name> <description>VECTCLRACTIVE</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSRESETREQ</name> <description>SYSRESETREQ</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRIGROUP</name> <description>PRIGROUP</description> <bitOffset>8</bitOffset> <bitWidth>3</bitWidth> </field> <field> <name>ENDIANESS</name> <description>ENDIANESS</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>VECTKEYSTAT</name> <description>Register key</description> <bitOffset>16</bitOffset> <bitWidth>16</bitWidth> </field> </fields> </register> <register> <name>SCR</name> <displayName>SCR</displayName> <description>System control register</description> <addressOffset>0x10</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>SLEEPONEXIT</name> <description>SLEEPONEXIT</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SLEEPDEEP</name> <description>SLEEPDEEP</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SEVEONPEND</name> <description>Send Event on Pending bit</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CCR</name> <displayName>CCR</displayName> <description>Configuration and control register</description> <addressOffset>0x14</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>NONBASETHRDENA</name> <description>Configures how the processor enters Thread mode</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USERSETMPEND</name> <description>USERSETMPEND</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNALIGN__TRP</name> <description>UNALIGN_ TRP</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIV_0_TRP</name> <description>DIV_0_TRP</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFHFNMIGN</name> <description>BFHFNMIGN</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STKALIGN</name> <description>STKALIGN</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>SHPR1</name> <displayName>SHPR1</displayName> <description>System handler priority registers</description> <addressOffset>0x18</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_4</name> <description>Priority of system handler 4</description> <bitOffset>0</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_5</name> <description>Priority of system handler 5</description> <bitOffset>8</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_6</name> <description>Priority of system handler 6</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SHPR2</name> <displayName>SHPR2</displayName> <description>System handler priority registers</description> <addressOffset>0x1C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_11</name> <description>Priority of system handler 11</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SHPR3</name> <displayName>SHPR3</displayName> <description>System handler priority registers</description> <addressOffset>0x20</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>PRI_14</name> <description>Priority of system handler 14</description> <bitOffset>16</bitOffset> <bitWidth>8</bitWidth> </field> <field> <name>PRI_15</name> <description>Priority of system handler 15</description> <bitOffset>24</bitOffset> <bitWidth>8</bitWidth> </field> </fields> </register> <register> <name>SHCRS</name> <displayName>SHCRS</displayName> <description>System handler control and state register</description> <addressOffset>0x24</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MEMFAULTACT</name> <description>Memory management fault exception active bit</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSFAULTACT</name> <description>Bus fault exception active bit</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USGFAULTACT</name> <description>Usage fault exception active bit</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SVCALLACT</name> <description>SVC call active bit</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MONITORACT</name> <description>Debug monitor active bit</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PENDSVACT</name> <description>PendSV exception active bit</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SYSTICKACT</name> <description>SysTick exception active bit</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USGFAULTPENDED</name> <description>Usage fault exception pending bit</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MEMFAULTPENDED</name> <description>Memory management fault exception pending bit</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSFAULTPENDED</name> <description>Bus fault exception pending bit</description> <bitOffset>14</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>SVCALLPENDED</name> <description>SVC call pending bit</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MEMFAULTENA</name> <description>Memory management fault enable bit</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BUSFAULTENA</name> <description>Bus fault enable bit</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>USGFAULTENA</name> <description>Usage fault enable bit</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>CFSR_UFSR_BFSR_MMFSR</name> <displayName>CFSR_UFSR_BFSR_MMFSR</displayName> <description>Configurable fault status register</description> <addressOffset>0x28</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IACCVIOL</name> <description>Instruction access violation flag</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MUNSTKERR</name> <description>Memory manager fault on unstacking for a return from exception</description> <bitOffset>3</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MSTKERR</name> <description>Memory manager fault on stacking for exception entry.</description> <bitOffset>4</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MLSPERR</name> <description>MLSPERR</description> <bitOffset>5</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>MMARVALID</name> <description>Memory Management Fault Address Register (MMAR) valid flag</description> <bitOffset>7</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IBUSERR</name> <description>Instruction bus error</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>PRECISERR</name> <description>Precise data bus error</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>IMPRECISERR</name> <description>Imprecise data bus error</description> <bitOffset>10</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNSTKERR</name> <description>Bus fault on unstacking for a return from exception</description> <bitOffset>11</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>STKERR</name> <description>Bus fault on stacking for exception entry</description> <bitOffset>12</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>LSPERR</name> <description>Bus fault on floating-point lazy state preservation</description> <bitOffset>13</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>BFARVALID</name> <description>Bus Fault Address Register (BFAR) valid flag</description> <bitOffset>15</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNDEFINSTR</name> <description>Undefined instruction usage fault</description> <bitOffset>16</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INVSTATE</name> <description>Invalid state usage fault</description> <bitOffset>17</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>INVPC</name> <description>Invalid PC load usage fault</description> <bitOffset>18</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>NOCP</name> <description>No coprocessor usage fault.</description> <bitOffset>19</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>UNALIGNED</name> <description>Unaligned access usage fault</description> <bitOffset>24</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DIVBYZERO</name> <description>Divide by zero usage fault</description> <bitOffset>25</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>HFSR</name> <displayName>HFSR</displayName> <description>Hard fault status register</description> <addressOffset>0x2C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>VECTTBL</name> <description>Vector table hard fault</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>FORCED</name> <description>Forced hard fault</description> <bitOffset>30</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DEBUG_VT</name> <description>Reserved for Debug use</description> <bitOffset>31</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> <register> <name>MMFAR</name> <displayName>MMFAR</displayName> <description>Memory management fault address register</description> <addressOffset>0x34</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>MMFAR</name> <description>Memory management fault address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>BFAR</name> <displayName>BFAR</displayName> <description>Bus fault address register</description> <addressOffset>0x38</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>BFAR</name> <description>Bus fault address</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> <register> <name>AFSR</name> <displayName>AFSR</displayName> <description>Auxiliary fault status register</description> <addressOffset>0x3C</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>IMPDEF</name> <description>Implementation defined</description> <bitOffset>0</bitOffset> <bitWidth>32</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>NVIC_STIR</name> <description>Nested vectored interrupt controller</description> <groupName>NVIC</groupName> <baseAddress>0xE000EF00</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>STIR</name> <displayName>STIR</displayName> <description>Software trigger interrupt register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>INTID</name> <description>Software generated interrupt ID</description> <bitOffset>0</bitOffset> <bitWidth>9</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>FPU_CPACR</name> <description>Floating point unit CPACR</description> <groupName>FPU</groupName> <baseAddress>0xE000ED88</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>CPACR</name> <displayName>CPACR</displayName> <description>Coprocessor access control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x0000000</resetValue> <fields> <field> <name>CP</name> <description>CP</description> <bitOffset>20</bitOffset> <bitWidth>4</bitWidth> </field> </fields> </register> </registers> </peripheral> <peripheral> <name>SCB_ACTRL</name> <description>System control block ACTLR</description> <groupName>SCB</groupName> <baseAddress>0xE000E008</baseAddress> <addressBlock> <offset>0x0</offset> <size>0x5</size> <usage>registers</usage> </addressBlock> <registers> <register> <name>ACTRL</name> <displayName>ACTRL</displayName> <description>Auxiliary control register</description> <addressOffset>0x0</addressOffset> <size>0x20</size> <access>read-write</access> <resetValue>0x00000000</resetValue> <fields> <field> <name>DISMCYCINT</name> <description>DISMCYCINT</description> <bitOffset>0</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISDEFWBUF</name> <description>DISDEFWBUF</description> <bitOffset>1</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISFOLD</name> <description>DISFOLD</description> <bitOffset>2</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISFPCA</name> <description>DISFPCA</description> <bitOffset>8</bitOffset> <bitWidth>1</bitWidth> </field> <field> <name>DISOOFP</name> <description>DISOOFP</description> <bitOffset>9</bitOffset> <bitWidth>1</bitWidth> </field> </fields> </register> </registers> </peripheral> </peripherals> </device>