STM32L4x2 1.6 STM32L4x2 CM4 r1p0 little false false 3 false 8 32 0x20 0x0 0xFFFFFFFF DAC1 Digital-to-analog converter DAC 0x40007400 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00000000 EN1 DAC channel1 enable 0 1 TEN1 DAC channel1 trigger enable 2 1 TSEL1 DAC channel1 trigger selection 3 3 WAVE1 DAC channel1 noise/triangle wave generation enable 6 2 MAMP1 DAC channel1 mask/amplitude selector 8 4 DMAEN1 DAC channel1 DMA enable 12 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable 13 1 CEN1 DAC Channel 1 calibration enable 14 1 EN2 DAC channel2 enable 16 1 TEN2 DAC channel2 trigger enable 18 1 TSEL2 DAC channel2 trigger selection 19 3 WAVE2 DAC channel2 noise/triangle wave generation enable 22 2 MAMP2 DAC channel2 mask/amplitude selector 24 4 DMAEN2 DAC channel2 DMA enable 28 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable 29 1 CEN2 DAC Channel 2 calibration enable 30 1 SWTRIGR SWTRIGR software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG1 DAC channel1 software trigger 0 1 SWTRIG2 DAC channel2 software trigger 1 1 DHR12R1 DHR12R1 channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DHR12L1 DHR12L1 channel1 12-bit left-aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DHR8R1 DHR8R1 channel1 8-bit right-aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DHR12R2 DHR12R2 channel2 12-bit right aligned data holding register 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data 0 12 DHR12L2 DHR12L2 channel2 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data 4 12 DHR8R2 DHR8R2 channel2 8-bit right-aligned data holding register 0x1C 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data 0 8 DHR12RD DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DACC2DHR DAC channel2 12-bit right-aligned data 16 12 DHR12LD DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DACC2DHR DAC channel2 12-bit left-aligned data 20 12 DHR8RD DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DACC2DHR DAC channel2 8-bit right-aligned data 8 8 DOR1 DOR1 channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output 0 12 DOR2 DOR2 channel2 data output register 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output 0 12 SR SR status register 0x34 0x20 0x00000000 DMAUDR1 DAC channel1 DMA underrun flag 13 1 read-write CAL_FLAG1 DAC Channel 1 calibration offset status 14 1 read-only BWST1 DAC Channel 1 busy writing sample time flag 15 1 read-only DMAUDR2 DAC channel2 DMA underrun flag 29 1 read-write CAL_FLAG2 DAC Channel 2 calibration offset status 30 1 read-only BWST2 DAC Channel 2 busy writing sample time flag 31 1 read-only CCR CCR calibration control register 0x38 0x20 read-write 0x00000000 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 MCR MCR mode control register 0x3C 0x20 read-write 0x00000000 MODE1 DAC Channel 1 mode 0 3 MODE2 DAC Channel 2 mode 16 3 SHSR1 SHSR1 Sample and Hold sample time register 1 0x40 0x20 read-write 0x00000000 TSAMPLE1 DAC Channel 1 sample Time 0 10 SHSR2 SHSR2 Sample and Hold sample time register 2 0x44 0x20 read-write 0x00000000 TSAMPLE2 DAC Channel 2 sample Time 0 10 SHHR SHHR Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 THOLD1 DAC Channel 1 hold Time 0 10 THOLD2 DAC Channel 2 hold time 16 10 SHRR SHRR Sample and Hold refresh time register 0x4C 0x20 read-write 0x00000001 TREFRESH1 DAC Channel 1 refresh Time 0 8 TREFRESH2 DAC Channel 2 refresh Time 16 8 DMA1 Direct memory access controller DMA 0x40020000 0x0 0x400 registers DMA1_CH1 DMA1 Channel1 global interrupt 11 DMA1_CH2 DMA1 Channel2 global interrupt 12 DMA1_CH3 DMA1 Channel3 interrupt 13 DMA1_CH4 DMA1 Channel4 interrupt 14 DMA1_CH5 DMA1 Channel5 interrupt 15 DMA1_CH6 DMA1 Channel6 interrupt 16 DMA1_CH7 DMA1 Channel 7 interrupt 17 ISR ISR interrupt status register 0x0 0x20 read-only 0x00000000 TEIF7 Channel x transfer error flag (x = 1 ..7) 27 1 HTIF7 Channel x half transfer flag (x = 1 ..7) 26 1 TCIF7 Channel x transfer complete flag (x = 1 ..7) 25 1 GIF7 Channel x global interrupt flag (x = 1 ..7) 24 1 TEIF6 Channel x transfer error flag (x = 1 ..7) 23 1 HTIF6 Channel x half transfer flag (x = 1 ..7) 22 1 TCIF6 Channel x transfer complete flag (x = 1 ..7) 21 1 GIF6 Channel x global interrupt flag (x = 1 ..7) 20 1 TEIF5 Channel x transfer error flag (x = 1 ..7) 19 1 HTIF5 Channel x half transfer flag (x = 1 ..7) 18 1 TCIF5 Channel x transfer complete flag (x = 1 ..7) 17 1 GIF5 Channel x global interrupt flag (x = 1 ..7) 16 1 TEIF4 Channel x transfer error flag (x = 1 ..7) 15 1 HTIF4 Channel x half transfer flag (x = 1 ..7) 14 1 TCIF4 Channel x transfer complete flag (x = 1 ..7) 13 1 GIF4 Channel x global interrupt flag (x = 1 ..7) 12 1 TEIF3 Channel x transfer error flag (x = 1 ..7) 11 1 HTIF3 Channel x half transfer flag (x = 1 ..7) 10 1 TCIF3 Channel x transfer complete flag (x = 1 ..7) 9 1 GIF3 Channel x global interrupt flag (x = 1 ..7) 8 1 TEIF2 Channel x transfer error flag (x = 1 ..7) 7 1 HTIF2 Channel x half transfer flag (x = 1 ..7) 6 1 TCIF2 Channel x transfer complete flag (x = 1 ..7) 5 1 GIF2 Channel x global interrupt flag (x = 1 ..7) 4 1 TEIF1 Channel x transfer error flag (x = 1 ..7) 3 1 HTIF1 Channel x half transfer flag (x = 1 ..7) 2 1 TCIF1 Channel x transfer complete flag (x = 1 ..7) 1 1 GIF1 Channel x global interrupt flag (x = 1 ..7) 0 1 IFCR IFCR interrupt flag clear register 0x4 0x20 write-only 0x00000000 CTEIF7 Channel x transfer error clear (x = 1 ..7) 27 1 CHTIF7 Channel x half transfer clear (x = 1 ..7) 26 1 CTCIF7 Channel x transfer complete clear (x = 1 ..7) 25 1 CGIF7 Channel x global interrupt clear (x = 1 ..7) 24 1 CTEIF6 Channel x transfer error clear (x = 1 ..7) 23 1 CHTIF6 Channel x half transfer clear (x = 1 ..7) 22 1 CTCIF6 Channel x transfer complete clear (x = 1 ..7) 21 1 CGIF6 Channel x global interrupt clear (x = 1 ..7) 20 1 CTEIF5 Channel x transfer error clear (x = 1 ..7) 19 1 CHTIF5 Channel x half transfer clear (x = 1 ..7) 18 1 CTCIF5 Channel x transfer complete clear (x = 1 ..7) 17 1 CGIF5 Channel x global interrupt clear (x = 1 ..7) 16 1 CTEIF4 Channel x transfer error clear (x = 1 ..7) 15 1 CHTIF4 Channel x half transfer clear (x = 1 ..7) 14 1 CTCIF4 Channel x transfer complete clear (x = 1 ..7) 13 1 CGIF4 Channel x global interrupt clear (x = 1 ..7) 12 1 CTEIF3 Channel x transfer error clear (x = 1 ..7) 11 1 CHTIF3 Channel x half transfer clear (x = 1 ..7) 10 1 CTCIF3 Channel x transfer complete clear (x = 1 ..7) 9 1 CGIF3 Channel x global interrupt clear (x = 1 ..7) 8 1 CTEIF2 Channel x transfer error clear (x = 1 ..7) 7 1 CHTIF2 Channel x half transfer clear (x = 1 ..7) 6 1 CTCIF2 Channel x transfer complete clear (x = 1 ..7) 5 1 CGIF2 Channel x global interrupt clear (x = 1 ..7) 4 1 CTEIF1 Channel x transfer error clear (x = 1 ..7) 3 1 CHTIF1 Channel x half transfer clear (x = 1 ..7) 2 1 CTCIF1 Channel x transfer complete clear (x = 1 ..7) 1 1 CGIF1 Channel x global interrupt clear (x = 1 ..7) 0 1 CCR1 CCR1 channel x configuration register 0x8 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR1 CNDTR1 channel x number of data register 0xC 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR1 CPAR1 channel x peripheral address register 0x10 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR1 CMAR1 channel x memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 CCR2 CCR2 channel x configuration register 0x1C 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR2 CNDTR2 channel x number of data register 0x20 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR2 CPAR2 channel x peripheral address register 0x24 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR2 CMAR2 channel x memory address register 0x28 0x20 read-write 0x00000000 MA Memory address 0 32 CCR3 CCR3 channel x configuration register 0x30 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR3 CNDTR3 channel x number of data register 0x34 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR3 CPAR3 channel x peripheral address register 0x38 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR3 CMAR3 channel x memory address register 0x3C 0x20 read-write 0x00000000 MA Memory address 0 32 CCR4 CCR4 channel x configuration register 0x44 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR4 CNDTR4 channel x number of data register 0x48 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR4 CPAR4 channel x peripheral address register 0x4C 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR4 CMAR4 channel x memory address register 0x50 0x20 read-write 0x00000000 MA Memory address 0 32 CCR5 CCR5 channel x configuration register 0x58 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR5 CNDTR5 channel x number of data register 0x5C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR5 CPAR5 channel x peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR5 CMAR5 channel x memory address register 0x64 0x20 read-write 0x00000000 MA Memory address 0 32 CCR6 CCR6 channel x configuration register 0x6C 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR6 CNDTR6 channel x number of data register 0x70 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR6 CPAR6 channel x peripheral address register 0x74 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR6 CMAR6 channel x memory address register 0x78 0x20 read-write 0x00000000 MA Memory address 0 32 CCR7 CCR7 channel x configuration register 0x80 0x20 read-write 0x00000000 MEM2MEM Memory to memory mode 14 1 PL Channel priority level 12 2 MSIZE Memory size 10 2 PSIZE Peripheral size 8 2 MINC Memory increment mode 7 1 PINC Peripheral increment mode 6 1 CIRC Circular mode 5 1 DIR Data transfer direction 4 1 TEIE Transfer error interrupt enable 3 1 HTIE Half transfer interrupt enable 2 1 TCIE Transfer complete interrupt enable 1 1 EN Channel enable 0 1 CNDTR7 CNDTR7 channel x number of data register 0x84 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 CPAR7 CPAR7 channel x peripheral address register 0x88 0x20 read-write 0x00000000 PA Peripheral address 0 32 CMAR7 CMAR7 channel x memory address register 0x8C 0x20 read-write 0x00000000 MA Memory address 0 32 CSELR CSELR channel selection register 0xA8 0x20 read-write 0x00000000 C7S DMA channel 7 selection 24 4 C6S DMA channel 6 selection 20 4 C5S DMA channel 5 selection 16 4 C4S DMA channel 4 selection 12 4 C3S DMA channel 3 selection 8 4 C2S DMA channel 2 selection 4 4 C1S DMA channel 1 selection 0 4 DMA2 0x40020400 DMA2_CH1 DMA2 Channel 1 global Interrupt 56 DMA2_CH2 DMA2 Channel 2 global Interrupt 57 DMA2_CH3 DMA2 Channel 3 global Interrupt 58 DMA2_CH4 DMA2 Channel 4 global Interrupt 59 DMA2_CH5 DMA2 Channel 5 global Interrupt 60 DMA2_CH6 DMA2 Channel 6 global Interrupt 68 DMA2_CH7 DMA2 Channel 7 global Interrupt 69 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 8 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_IN Reverse input data 5 2 read-write POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 write-only INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 Polynomialcoefficients Programmable polynomial 0 32 LCD Liquid crystal display controller LCD 0x40002400 0x0 0x400 registers LCD LCD global interrupt 78 CR CR control register 0x0 0x20 read-write 0x00000000 BIAS Bias selector 5 2 DUTY Duty selection 2 3 VSEL Voltage source selection 1 1 LCDEN LCD controller enable 0 1 MUX_SEG Mux segment enable 7 1 BUFEN Voltage output buffer enable 8 1 FCR FCR frame control register 0x4 0x20 read-write 0x00000000 PS PS 16-bit prescaler 22 4 DIV DIV clock divider 18 4 BLINK Blink mode selection 16 2 BLINKF Blink frequency selection 13 3 CC Contrast control 10 3 DEAD Dead time duration 7 3 PON Pulse ON duration 4 3 UDDIE Update display done interrupt enable 3 1 SOFIE Start of frame interrupt enable 1 1 HD High drive enable 0 1 SR SR status register 0x8 0x20 0x00000020 FCRSF LCD Frame Control Register Synchronization flag 5 1 read-only RDY Ready flag 4 1 read-only UDD Update Display Done 3 1 read-only UDR Update display request 2 1 write-only SOF Start of frame flag 1 1 read-only ENS ENS 0 1 read-only CLR CLR clear register 0xC 0x20 write-only 0x00000000 UDDC Update display done clear 3 1 SOFC Start of frame flag clear 1 1 RAM_COM0 RAM_COM0 display memory 0x14 0x20 read-write 0x00000000 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM1 RAM_COM1 display memory 0x1C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM2 RAM_COM2 display memory 0x24 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM3 RAM_COM3 display memory 0x2C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM4 RAM_COM4 display memory 0x34 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM5 RAM_COM5 display memory 0x3C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM6 RAM_COM6 display memory 0x44 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 RAM_COM7 RAM_COM7 display memory 0x4C 0x20 read-write 0x00000000 S31 S31 31 1 S30 S30 30 1 S29 S29 29 1 S28 S28 28 1 S27 S27 27 1 S26 S26 26 1 S25 S25 25 1 S24 S24 24 1 S23 S23 23 1 S22 S22 22 1 S21 S21 21 1 S20 S20 20 1 S19 S19 19 1 S18 S18 18 1 S17 S17 17 1 S16 S16 16 1 S15 S15 15 1 S14 S14 14 1 S13 S13 13 1 S12 S12 12 1 S11 S11 11 1 S10 S10 10 1 S09 S09 9 1 S08 S08 8 1 S07 S07 7 1 S06 S06 6 1 S05 S05 5 1 S04 S04 4 1 S03 S03 3 1 S02 S02 2 1 S01 S01 1 1 S00 S00 0 1 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 77 CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 SYNCPOL Synchronization pin polarity 3 1 AM Acquisition mode 2 1 START Start a new acquisition 1 1 TSCE Touch sensing controller enable 0 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 EOAIE End of acquisition interrupt enable 0 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-write 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 G8S Analog I/O group x status 23 1 read-only G7S Analog I/O group x status 22 1 read-only G6S Analog I/O group x status 21 1 read-only G5S Analog I/O group x status 20 1 read-only G4S Analog I/O group x status 19 1 read-only G3S Analog I/O group x status 18 1 read-only G2S Analog I/O group x status 17 1 read-only G1S Analog I/O group x status 16 1 read-only G8E Analog I/O group x enable 7 1 read-write G7E Analog I/O group x enable 6 1 read-write G6E Analog I/O group x enable 5 1 read-write G5E Analog I/O group x enable 4 1 read-write G4E Analog I/O group x enable 3 1 read-write G3E Analog I/O group x enable 2 1 read-write G2E Analog I/O group x enable 1 1 read-write G1E Analog I/O group x enable 0 1 read-write IOG1CR IOG1CR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG2CR IOG2CR I/O group x counter register 0x38 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG3CR IOG3CR I/O group x counter register 0x3C 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG4CR IOG4CR I/O group x counter register 0x40 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG5CR IOG5CR I/O group x counter register 0x44 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG6CR IOG6CR I/O group x counter register 0x48 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG7CR IOG7CR I/O group x counter register 0x4C 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG8CR IOG8CR I/O group x counter register 0x50 0x20 read-only 0x00000000 CNT Counter value 0 14 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x20 read-write 0x00000FFF WIN Watchdog counter window value 0 12 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 0 CR CR Control register 0x0 0x20 read-write 0x0000007F WDGA Activation bit 7 1 T 7-bit counter (MSB to LSB) 0 7 CFR CFR Configuration register 0x4 0x20 read-write 0x0000007F EWI Early wakeup interrupt 9 1 WDGTB Timer base 7 2 W 7-bit window value 0 7 SR SR Status register 0x8 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 COMP Comparator COMP 0x40010200 0x0 0x200 registers COMP COMP1 and COMP2 interrupts 64 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 0x20 0x0 COMP1_EN Comparator 1 enable bit 0 1 read-write COMP1_PWRMODE Power Mode of the comparator 1 2 2 read-write COMP1_INMSEL Comparator 1 Input Minus connection configuration bit 4 3 read-write COMP1_INPSEL Comparator1 input plus selection bit 7 2 read-write COMP1_POLARITY Comparator 1 polarity selection bit 15 1 read-write COMP1_HYST Comparator 1 hysteresis selection bits 16 2 read-write COMP1_BLANKING Comparator 1 blanking source selection bits 18 3 read-write COMP1_BRGEN Scaler bridge enable 22 1 read-write COMP1_SCALEN Voltage scaler enable bit 23 1 read-write COMP1_INMESEL comparator 1 input minus extended selection bits 25 2 read-write COMP1_VALUE Comparator 1 output status bit 30 1 read-only COMP1_LOCK COMP1_CSR register lock bit 31 1 write-only COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 0x0 COMP2_EN Comparator 2 enable bit 0 1 read-write COMP2_PWRMODE Power Mode of the comparator 2 2 2 read-write COMP2_INMSEL Comparator 2 Input Minus connection configuration bit 4 3 read-write COMP2_INPSEL Comparator 2 Input Plus connection configuration bit 7 2 read-write COMP2_WINMODE Windows mode selection bit 9 1 read-write COMP2_POLARITY Comparator 2 polarity selection bit 15 1 read-write COMP2_HYST Comparator 2 hysteresis selection bits 16 2 read-write COMP2_BLANKING Comparator 2 blanking source selection bits 18 3 read-write COMP2_BRGEN Scaler bridge enable 22 1 read-write COMP2_SCALEN Voltage scaler enable bit 23 1 read-write COMP2_INMESEL comparator 2 input minus extended selection bits 25 2 read-write COMP2_VALUE Comparator 2 output status bit 30 1 read-only COMP2_LOCK COMP2_CSR register lock bit 31 1 write-only FIREWALL Firewall Firewall 0x40011C00 0x0 0x400 registers CSSA CSSA Code segment start address 0x0 0x20 read-write 0x00000000 ADD code segment start address 8 16 CSL CSL Code segment length 0x4 0x20 read-write 0x00000000 LENG code segment length 8 14 NVDSSA NVDSSA Non-volatile data segment start address 0x8 0x20 read-write 0x00000000 ADD Non-volatile data segment start address 8 16 NVDSL NVDSL Non-volatile data segment length 0xC 0x20 read-write 0x00000000 LENG Non-volatile data segment length 8 14 VDSSA VDSSA Volatile data segment start address 0x10 0x20 read-write 0x00000000 ADD Volatile data segment start address 6 10 VDSL VDSL Volatile data segment length 0x14 0x20 read-write 0x00000000 LENG Non-volatile data segment length 6 10 CR CR Configuration register 0x20 0x20 read-write 0x00000000 VDE Volatile data execution 2 1 VDS Volatile data shared 1 1 FPA Firewall pre alarm 0 1 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 31 I2C1_ER I2C1 error interrupt 32 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 TXIE TX Interrupt enable 1 1 RXIE RX Interrupt enable 2 1 ADDRIE Address match interrupt enable (slave only) 3 1 NACKIE Not acknowledge received interrupt enable 4 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 ERRIE Error interrupts enable 7 1 DNF Digital noise filter 8 4 ANFOFF Analog noise filter OFF 12 1 TXDMAEN DMA transmission requests enable 14 1 RXDMAEN DMA reception requests enable 15 1 SBC Slave byte control 16 1 NOSTRETCH Clock stretching disable 17 1 WUPEN Wakeup from STOP enable 18 1 GCEN General call enable 19 1 SMBHEN SMBus Host address enable 20 1 SMBDEN SMBus Device Default address enable 21 1 ALERTEN SMBUS alert enable 22 1 PECEN PEC enable 23 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 AUTOEND Automatic end mode (master mode) 25 1 RELOAD NBYTES reload mode 24 1 NBYTES Number of bytes 16 8 NACK NACK generation (slave mode) 15 1 STOP Stop generation (master mode) 14 1 START Start generation 13 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 ADD10 10-bit addressing mode (master mode) 11 1 RD_WRN Transfer direction (master mode) 10 1 SADD Slave address bit (master mode) 0 10 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 OA1MODE Own Address 1 10-bit mode 10 1 OA1EN Own Address 1 enable 15 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 OA2MSK Own Address 2 masks 8 3 OA2EN Own Address 2 enable 15 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 TIDLE Idle clock timeout detection 12 1 TIMOUTEN Clock timeout enable 15 1 TIMEOUTB Bus timeout B 16 12 TEXTEN Extended clock timeout enable 31 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) 16 1 read-only BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C3 0x40005C00 I2C3_EV I2C3 event interrupt 72 I2C3_ER I2C3 error interrupt 73 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 33 I2C2_ER I2C2 error interrupt 34 I2C4 0x40008400 I2C4_EV I2C4 event interrupt, wakeup through EXTI 83 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 4 ACR ACR Access control register 0x0 0x20 read-write 0x00000600 LATENCY Latency 0 3 PRFTEN Prefetch enable 8 1 ICEN Instruction cache enable 9 1 DCEN Data cache enable 10 1 ICRST Instruction cache reset 11 1 DCRST Data cache reset 12 1 RUN_PD Flash Power-down mode during Low-power run mode 13 1 SLEEP_PD Flash Power-down mode during Low-power sleep mode 14 1 PDKEYR PDKEYR Power down key register 0x4 0x20 write-only 0x00000000 PDKEYR RUN_PD in FLASH_ACR key 0 32 KEYR KEYR Flash key register 0x8 0x20 write-only 0x00000000 KEYR KEYR 0 32 OPTKEYR OPTKEYR Option byte key register 0xC 0x20 write-only 0x00000000 OPTKEYR Option byte key 0 32 SR SR Status register 0x10 0x20 0x00000000 EOP End of operation 0 1 read-write OPERR Operation error 1 1 read-write PROGERR Programming error 3 1 read-write WRPERR Write protected error 4 1 read-write PGAERR Programming alignment error 5 1 read-write SIZERR Size error 6 1 read-write PGSERR Programming sequence error 7 1 read-write MISERR Fast programming data miss error 8 1 read-write FASTERR Fast programming error 9 1 read-write RDERR PCROP read error 14 1 read-write OPTVERR Option validity error 15 1 read-write BSY Busy 16 1 read-only CR CR Flash control register 0x14 0x20 read-write 0xC0000000 PG Programming 0 1 PER Page erase 1 1 MER1 Bank 1 Mass erase 2 1 PNB Page number 3 8 BKER Bank erase 11 1 MER2 Bank 2 Mass erase 15 1 START Start 16 1 OPTSTRT Options modification start 17 1 FSTPG Fast programming 18 1 EOPIE End of operation interrupt enable 24 1 ERRIE Error interrupt enable 25 1 RDERRIE PCROP read error interrupt enable 26 1 OBL_LAUNCH Force the option byte loading 27 1 OPTLOCK Options Lock 30 1 LOCK FLASH_CR Lock 31 1 ECCR ECCR Flash ECC register 0x18 0x20 0x00000000 ADDR_ECC ECC fail address 0 19 read-only BK_ECC ECC fail bank 19 1 read-only SYSF_ECC System Flash ECC fail 20 1 read-only ECCIE ECC correction interrupt enable 24 1 read-write ECCC ECC correction 30 1 read-write ECCD ECC detection 31 1 read-write OPTR OPTR Flash option register 0x20 0x20 read-write 0xF0000000 RDP Read protection level 0 8 BOR_LEV BOR reset Level 8 3 nRST_STOP nRST_STOP 12 1 nRST_STDBY nRST_STDBY 13 1 IDWG_SW Independent watchdog selection 16 1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 WWDG_SW Window watchdog selection 19 1 BFB2 Dual-bank boot 20 1 DUALBANK Dual-Bank on 512 KB or 256 KB Flash memory devices 21 1 nBOOT1 Boot configuration 23 1 SRAM2_PE SRAM2 parity check enable 24 1 SRAM2_RST SRAM2 Erase when system reset 25 1 PCROP1SR PCROP1SR Flash Bank 1 PCROP Start address register 0x24 0x20 read-write 0xFFFF0000 PCROP1_STRT Bank 1 PCROP area start offset 0 16 PCROP1ER PCROP1ER Flash Bank 1 PCROP End address register 0x28 0x20 read-write 0x0FFF0000 PCROP1_END Bank 1 PCROP area end offset 0 16 PCROP_RDP PCROP area preserved when RDP level decreased 31 1 WRP1AR WRP1AR Flash Bank 1 WRP area A address register 0x2C 0x20 read-write 0xFF00FF00 WRP1A_STRT Bank 1 WRP first area tart offset 0 8 WRP1A_END Bank 1 WRP first area A end offset 16 8 WRP1BR WRP1BR Flash Bank 1 WRP area B address register 0x30 0x20 read-write 0xFF00FF00 WRP1B_STRT Bank 1 WRP second area B end offset 16 8 WRP1B_END Bank 1 WRP second area B start offset 0 8 PCROP2SR PCROP2SR Flash Bank 2 PCROP Start address register 0x44 0x20 read-write 0xFFFF0000 PCROP2_STRT Bank 2 PCROP area start offset 0 16 PCROP2ER PCROP2ER Flash Bank 2 PCROP End address register 0x48 0x20 read-write 0xFFFF0000 PCROP2_END Bank 2 PCROP area end offset 0 16 WRP2AR WRP2AR Flash Bank 2 WRP area A address register 0x4C 0x20 read-write 0xFF00FF00 WRP2A_STRT Bank 2 WRP first area A start offset 0 8 WRP2A_END Bank 2 WRP first area A end offset 16 8 WRP2BR WRP2BR Flash Bank 2 WRP area B address register 0x50 0x20 read-write 0xFF00FF00 WRP2B_STRT Bank 2 WRP second area B start offset 0 8 WRP2B_END Bank 2 WRP second area B end offset 16 8 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global interrupt 5 CR CR Clock control register 0x0 0x20 0x00000063 PLLSAI1RDY SAI1 PLL clock ready flag 27 1 read-only PLLSAI1ON SAI1 PLL enable 26 1 read-write PLLRDY Main PLL clock ready flag 25 1 read-only PLLON Main PLL enable 24 1 read-write CSSON Clock security system enable 19 1 write-only HSEBYP HSE crystal oscillator bypass 18 1 read-write HSERDY HSE clock ready flag 17 1 read-only HSEON HSE clock enable 16 1 read-write HSIASFS HSI automatic start from Stop 11 1 read-write HSIRDY HSI clock ready flag 10 1 read-only HSIKERON HSI always enable for peripheral kernels 9 1 read-write HSION HSI clock enable 8 1 read-write MSIRANGE MSI clock ranges 4 4 read-write MSIRGSEL MSI clock range selection 3 1 write-only MSIPLLEN MSI clock PLL enable 2 1 read-write MSIRDY MSI clock ready flag 1 1 read-only MSION MSI clock enable 0 1 read-write ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x10000000 HSITRIM HSI clock trimming 24 5 read-write HSICAL HSI clock calibration 16 8 read-only MSITRIM MSI clock trimming 8 8 read-write MSICAL MSI clock calibration 0 8 read-only CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-only MCOSEL Microcontroller clock output 24 3 read-write STOPWUCK Wakeup from Stop and CSS backup clock selection 15 1 read-write PPRE2 APB high-speed prescaler (APB2) 11 3 read-write PPRE1 PB low-speed prescaler (APB1) 8 3 read-write HPRE AHB prescaler 4 4 read-write SWS System clock switch status 2 2 read-only SW System clock switch 0 2 read-write PLLCFGR PLLCFGR PLL configuration register 0xC 0x20 read-write 0x00001000 PLLR Main PLL division factor for PLLCLK (system clock) 25 2 PLLREN Main PLL PLLCLK output enable 24 1 PLLQ Main PLL division factor for PLLUSB1CLK(48 MHz clock) 21 2 PLLQEN Main PLL PLLUSB1CLK output enable 20 1 PLLP Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) 17 1 PLLPEN Main PLL PLLSAI3CLK output enable 16 1 PLLN Main PLL multiplication factor for VCO 8 7 PLLM Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock 4 3 PLLSRC Main PLL, PLLSAI1 and PLLSAI2 entry clock source 0 2 PLLPDIV Main PLL division factor for PLLSAI2CLK 27 5 PLLSAI1CFGR PLLSAI1CFGR PLLSAI1 configuration register 0x10 0x20 read-write 0x00001000 PLLSAI1R PLLSAI1 division factor for PLLADC1CLK (ADC clock) 25 2 PLLSAI1REN PLLSAI1 PLLADC1CLK output enable 24 1 PLLSAI1Q SAI1PLL division factor for PLLUSB2CLK (48 MHz clock) 21 2 PLLSAI1QEN SAI1PLL PLLUSB2CLK output enable 20 1 PLLSAI1P SAI1PLL division factor for PLLSAI1CLK (SAI1 or SAI2 clock) 17 1 PLLSAI1PEN SAI1PLL PLLSAI1CLK output enable 16 1 PLLSAI1N SAI1PLL multiplication factor for VCO 8 7 PLLSAI1PDIV PLLSAI1 division factor for PLLSAI1CLK 27 5 CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 LSECSSIE LSE clock security system interrupt enable 9 1 PLLSAI1RDYIE PLLSAI1 ready interrupt enable 6 1 PLLRDYIE PLL ready interrupt enable 5 1 HSERDYIE HSE ready interrupt enable 4 1 HSIRDYIE HSI ready interrupt enable 3 1 MSIRDYIE MSI ready interrupt enable 2 1 LSERDYIE LSE ready interrupt enable 1 1 LSIRDYIE LSI ready interrupt enable 0 1 HSI48RDYIE HSI48 ready interrupt enable 10 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSECSSF LSE Clock security system interrupt flag 9 1 CSSF Clock security system interrupt flag 8 1 PLLSAI1RDYF PLLSAI1 ready interrupt flag 6 1 PLLRDYF PLL ready interrupt flag 5 1 HSERDYF HSE ready interrupt flag 4 1 HSIRDYF HSI ready interrupt flag 3 1 MSIRDYF MSI ready interrupt flag 2 1 LSERDYF LSE ready interrupt flag 1 1 LSIRDYF LSI ready interrupt flag 0 1 HSI48RDYF HSI48 ready interrupt flag 10 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSECSSC LSE Clock security system interrupt clear 9 1 CSSC Clock security system interrupt clear 8 1 PLLSAI1RDYC PLLSAI1 ready interrupt clear 6 1 PLLRDYC PLL ready interrupt clear 5 1 HSERDYC HSE ready interrupt clear 4 1 HSIRDYC HSI ready interrupt clear 3 1 MSIRDYC MSI ready interrupt clear 2 1 LSERDYC LSE ready interrupt clear 1 1 LSIRDYC LSI ready interrupt clear 0 1 HSI48RDYC HSI48 oscillator ready interrupt clear 10 1 AHB1RSTR AHB1RSTR AHB1 peripheral reset register 0x28 0x20 read-write 0x00000000 TSCRST Touch Sensing Controller reset 16 1 CRCRST CRC reset 11 1 FLASHRST Flash memory interface reset 8 1 DMA2RST DMA2 reset 1 1 DMA1RST DMA1 reset 0 1 AHB2RSTR AHB2RSTR AHB2 peripheral reset register 0x2C 0x20 read-write 0x00000000 RNGRST Random number generator reset 18 1 AESRST AES hardware accelerator reset 16 1 ADCRST ADC reset 13 1 GPIOHRST IO port H reset 7 1 GPIOERST IO port E reset 4 1 GPIODRST IO port D reset 3 1 GPIOCRST IO port C reset 2 1 GPIOBRST IO port B reset 1 1 GPIOARST IO port A reset 0 1 AHB3RSTR AHB3RSTR AHB3 peripheral reset register 0x30 0x20 read-write 0x00000000 QSPIRST Quad SPI memory interface reset 8 1 APB1RSTR1 APB1RSTR1 APB1 peripheral reset register 1 0x38 0x20 read-write 0x00000000 LPTIM1RST Low Power Timer 1 reset 31 1 OPAMPRST OPAMP interface reset 30 1 DAC1RST DAC1 interface reset 29 1 PWRRST Power interface reset 28 1 CAN1RST CAN1 reset 25 1 I2C3RST I2C3 reset 23 1 I2C1RST I2C1 reset 21 1 USART1RST USART1 reset 18 1 USART2RST USART2 reset 17 1 SPI3RST SPI3 reset 15 1 SPI2RST SPI2 reset 14 1 LCDRST LCD interface reset 9 1 TIM7RST TIM7 timer reset 5 1 TIM6RST TIM6 timer reset 4 1 TIM2RST TIM2 timer reset 0 1 USART4RST USART4 reset. 19 1 I2C2RST I2C2 reset 22 1 CRSRST CRS reset 24 1 USBFSRST USB FS reset 26 1 APB1RSTR2 APB1RSTR2 APB1 peripheral reset register 2 0x3C 0x20 read-write 0x00000000 LPTIM2RST Low-power timer 2 reset 5 1 SWPMI1RST Single wire protocol reset 2 1 LPUART1RST Low-power UART 1 reset 0 1 I2C4RST I2C4 reset 1 1 APB2RSTR APB2RSTR APB2 peripheral reset register 0x40 0x20 read-write 0x00000000 SAI1RST Serial audio interface 1 (SAI1) reset 21 1 TIM16RST TIM16 timer reset 17 1 TIM15RST TIM15 timer reset 16 1 USART1RST USART1 reset 14 1 SPI1RST SPI1 reset 12 1 TIM1RST TIM1 timer reset 11 1 SDMMCRST SDMMC reset 10 1 SYSCFGRST System configuration (SYSCFG) reset 0 1 DFSDMRST DFSDM filter reset 24 1 AHB1ENR AHB1ENR AHB1 peripheral clock enable register 0x48 0x20 read-write 0x00000100 TSCEN Touch Sensing Controller clock enable 16 1 CRCEN CRC clock enable 12 1 FLASHEN Flash memory interface clock enable 8 1 DMA2EN DMA2 clock enable 1 1 DMA1EN DMA1 clock enable 0 1 AHB2ENR AHB2ENR AHB2 peripheral clock enable register 0x4C 0x20 read-write 0x00000000 RNGEN Random Number Generator clock enable 18 1 AESEN AES accelerator clock enable 16 1 ADCEN ADC clock enable 13 1 GPIOHEN IO port H clock enable 7 1 GPIOEEN IO port E clock enable 4 1 GPIODEN IO port D clock enable 3 1 GPIOCEN IO port C clock enable 2 1 GPIOBEN IO port B clock enable 1 1 GPIOAEN IO port A clock enable 0 1 AHB3ENR AHB3ENR AHB3 peripheral clock enable register 0x50 0x20 read-write 0x00000000 QSPIEN QSPIEN 8 1 APB1ENR1 APB1ENR1 APB1ENR1 0x58 0x20 read-write 0x00000000 LPTIM1EN Low power timer 1 clock enable 31 1 OPAMPEN OPAMP interface clock enable 30 1 DAC1EN DAC1 interface clock enable 29 1 PWREN Power interface clock enable 28 1 CAN1EN CAN1 clock enable 25 1 I2C3EN I2C3 clock enable 23 1 I2C1EN I2C1 clock enable 21 1 USART1EN USART1 clock enable 18 1 USART2EN USART2 clock enable 17 1 SPI3EN SPI3 clock enable 15 1 SPI1EN SPI1 clock enable 14 1 WWDGEN Window watchdog clock enable 11 1 LCDEN LCD clock enable 9 1 TIM7EN TIM7 timer clock enable 5 1 TIM6EN TIM6 timer clock enable 4 1 TIM2EN TIM2 timer clock enable 0 1 RTCAPBEN RTC APB clock enable 10 1 CRSEN CRS clock enable 24 1 USBF USB FS clock enable 26 1 TIM3EN TIM3 timer clock enable 1 1 UART4EN UART4 clock enable 19 1 I2C2EN I2C2 clock enable 22 1 APB1ENR2 APB1ENR2 APB1 peripheral clock enable register 2 0x5C 0x20 read-write 0x00000000 LPTIM2EN LPTIM2EN 5 1 SWPMI1EN Single wire protocol clock enable 2 1 LPUART1EN Low power UART 1 clock enable 0 1 DFSDMEN DFSDMEN enable 24 1 I2C4EN I2C4 clock enable 1 1 APB2ENR APB2ENR APB2ENR 0x60 0x20 read-write 0x00000000 SAI1EN SAI1 clock enable 21 1 TIM16EN TIM16 timer clock enable 17 1 TIM15EN TIM15 timer clock enable 16 1 USART1EN USART1clock enable 14 1 SPI1EN SPI1 clock enable 12 1 TIM1EN TIM1 timer clock enable 11 1 SDMMCEN SDMMC clock enable 10 1 FIREWALLEN Firewall clock enable 7 1 SYSCFGEN SYSCFG clock enable 0 1 AHB1SMENR AHB1SMENR AHB1 peripheral clocks enable in Sleep and Stop modes register 0x68 0x20 read-write 0x00011303 TSCSMEN Touch Sensing Controller clocks enable during Sleep and Stop modes 16 1 CRCSMEN CRCSMEN 12 1 SRAM1SMEN SRAM1 interface clocks enable during Sleep and Stop modes 9 1 FLASHSMEN Flash memory interface clocks enable during Sleep and Stop modes 8 1 DMA2SMEN DMA2 clocks enable during Sleep and Stop modes 1 1 DMA1SMEN DMA1 clocks enable during Sleep and Stop modes 0 1 AHB2SMENR AHB2SMENR AHB2 peripheral clocks enable in Sleep and Stop modes register 0x6C 0x20 read-write 0x000532FF RNGSMEN Random Number Generator clocks enable during Sleep and Stop modes 18 1 AESSMEN AES accelerator clocks enable during Sleep and Stop modes 16 1 ADCFSSMEN ADC clocks enable during Sleep and Stop modes 13 1 SRAM2SMEN SRAM2 interface clocks enable during Sleep and Stop modes 9 1 GPIOHSMEN IO port H clocks enable during Sleep and Stop modes 7 1 GPIOESMEN IO port E clocks enable during Sleep and Stop modes 4 1 GPIODSMEN IO port D clocks enable during Sleep and Stop modes 3 1 GPIOCSMEN IO port C clocks enable during Sleep and Stop modes 2 1 GPIOBSMEN IO port B clocks enable during Sleep and Stop modes 1 1 GPIOASMEN IO port A clocks enable during Sleep and Stop modes 0 1 AHB3SMENR AHB3SMENR AHB3 peripheral clocks enable in Sleep and Stop modes register 0x70 0x20 read-write 0x000000101 QSPISMEN QSPISMEN 8 1 APB1SMENR1 APB1SMENR1 APB1SMENR1 0x78 0x20 read-write 0xF2FECA3F LPTIM1SMEN Low power timer 1 clocks enable during Sleep and Stop modes 31 1 OPAMPSMEN OPAMP interface clocks enable during Sleep and Stop modes 30 1 DAC1SMEN DAC1 interface clocks enable during Sleep and Stop modes 29 1 PWRSMEN Power interface clocks enable during Sleep and Stop modes 28 1 CAN1SMEN CAN1 clocks enable during Sleep and Stop modes 25 1 I2C3SMEN I2C3 clocks enable during Sleep and Stop modes 23 1 I2C1SMEN I2C1 clocks enable during Sleep and Stop modes 21 1 USART2SMEN USART2 clocks enable during Sleep and Stop modes 18 1 USART1SMEN USART1 clocks enable during Sleep and Stop modes 17 1 SP3SMEN SPI3 clocks enable during Sleep and Stop modes 15 1 SPI2SMEN SPI2 clocks enable during Sleep and Stop modes 14 1 WWDGSMEN Window watchdog clocks enable during Sleep and Stop modes 11 1 LCDSMEN LCD clocks enable during Sleep and Stop modes 9 1 TIM7SMEN TIM7 timer clocks enable during Sleep and Stop modes 5 1 TIM6SMEN TIM6 timer clocks enable during Sleep and Stop modes 4 1 TIM2SMEN TIM2 timer clocks enable during Sleep and Stop modes 0 1 RTCAPBSMEN RTC APB clock enable during Sleep and Stop modes 10 1 USBFSSMEN USB FS clock enable during Sleep and Stop modes 26 1 I2C2SMEN I2C2 clocks enable during Sleep and Stop modes 22 1 CRSSMEN CRS clock enable during Sleep and Stop modes 24 1 APB1SMENR2 APB1SMENR2 APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x7C 0x20 read-write 0x000000025 LPTIM2SMEN LPTIM2SMEN 5 1 SWPMI1SMEN Single wire protocol clocks enable during Sleep and Stop modes 2 1 LPUART1SMEN Low power UART 1 clocks enable during Sleep and Stop modes 0 1 APB2SMENR APB2SMENR APB2SMENR 0x80 0x20 read-write 0x01677C01 SAI1SMEN SAI1 clocks enable during Sleep and Stop modes 21 1 TIM16SMEN TIM16 timer clocks enable during Sleep and Stop modes 17 1 TIM15SMEN TIM15 timer clocks enable during Sleep and Stop modes 16 1 USART1SMEN USART1clocks enable during Sleep and Stop modes 14 1 SPI1SMEN SPI1 clocks enable during Sleep and Stop modes 12 1 TIM1SMEN TIM1 timer clocks enable during Sleep and Stop modes 11 1 SDMMCSMEN SDMMC clocks enable during Sleep and Stop modes 10 1 SYSCFGSMEN SYSCFG clocks enable during Sleep and Stop modes 0 1 CCIPR CCIPR CCIPR 0x88 0x20 read-write 0x00000000 SWPMI1SEL SWPMI1 clock source selection 30 1 ADCSEL ADCs clock source selection 28 2 CLK48SEL 48 MHz clock source selection 26 2 SAI1SEL SAI1 clock source selection 22 2 LPTIM2SEL Low power timer 2 clock source selection 20 2 LPTIM1SEL Low power timer 1 clock source selection 18 2 I2C3SEL I2C3 clock source selection 16 2 I2C1SEL I2C1 clock source selection 12 2 LPUART1SEL LPUART1 clock source selection 10 2 USART2SEL USART2 clock source selection 2 2 USART1SEL USART1 clock source selection 0 2 USART4SEL USART4 clock source selection 6 2 USART3SEL USART3 clock source selection 4 2 I2C2SEL I2C2 clock source selection 14 2 BDCR BDCR BDCR 0x90 0x20 0x00000000 LSCOSEL Low speed clock output selection 25 1 read-write LSCOEN Low speed clock output enable 24 1 read-write BDRST Backup domain software reset 16 1 read-write RTCEN RTC clock enable 15 1 read-write RTCSEL RTC clock source selection 8 2 read-write LSECSSD LSECSSD 6 1 read-only LSECSSON LSECSSON 5 1 read-write LSEDRV SE oscillator drive capability 3 2 read-write LSEBYP LSE oscillator bypass 2 1 read-write LSERDY LSE oscillator ready 1 1 read-only LSEON LSE oscillator enable 0 1 read-write CSR CSR CSR 0x94 0x20 0x0C000600 LPWRSTF Low-power reset flag 31 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only IWDGRSTF Independent window watchdog reset flag 29 1 read-only SFTRSTF Software reset flag 28 1 read-only BORRSTF BOR flag 27 1 read-only PINRSTF Pin reset flag 26 1 read-only OBLRSTF Option byte loader reset flag 25 1 read-only FIREWALLRSTF Firewall reset flag 24 1 read-only RMVF Remove reset flag 23 1 read-write MSISRANGE SI range after Standby mode 8 4 read-write LSIRDY LSI oscillator ready 1 1 read-only LSION LSI oscillator enable 0 1 read-write CRRCR CRRCR Clock recovery RC register 0x98 0x20 0x0C000600 HSI48ON HSI48 clock enable 0 1 read-write HSI48RDY HSI48 clock ready flag 1 1 read-only HSI48CAL HSI48 clock calibration 7 9 read-only PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00000200 LPR Low-power run 14 1 VOS Voltage scaling range selection 9 2 DBP Disable backup domain write protection 8 1 LPMS Low-power mode selection 0 3 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000000 USV VDDUSB USB supply valid 10 1 IOSV VDDIO2 Independent I/Os supply valid 9 1 PVME4 Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V 7 1 PVME3 Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 6 1 PVME2 Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V 5 1 PVME1 Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 4 1 PLS Power voltage detector level selection 1 3 PVDE Power voltage detector enable 0 1 CR3 CR3 Power control register 3 0x8 0x20 read-write 0X00008000 EWF Enable internal wakeup line 15 1 APC Apply pull-up and pull-down configuration 10 1 RRS SRAM2 retention in Standby mode 8 1 EWUP5 Enable Wakeup pin WKUP5 4 1 EWUP4 Enable Wakeup pin WKUP4 3 1 EWUP3 Enable Wakeup pin WKUP3 2 1 EWUP2 Enable Wakeup pin WKUP2 1 1 EWUP1 Enable Wakeup pin WKUP1 0 1 CR4 CR4 Power control register 4 0xC 0x20 read-write 0x00000000 VBRS VBAT battery charging resistor selection 9 1 VBE VBAT battery charging enable 8 1 WP5 Wakeup pin WKUP5 polarity 4 1 WP4 Wakeup pin WKUP4 polarity 3 1 WP3 Wakeup pin WKUP3 polarity 2 1 WP2 Wakeup pin WKUP2 polarity 1 1 WP1 Wakeup pin WKUP1 polarity 0 1 SR1 SR1 Power status register 1 0x10 0x20 read-only 0x00000000 WUFI Wakeup flag internal 15 1 CSBF Standby flag 8 1 CWUF5 Wakeup flag 5 4 1 CWUF4 Wakeup flag 4 3 1 CWUF3 Wakeup flag 3 2 1 CWUF2 Wakeup flag 2 1 1 CWUF1 Wakeup flag 1 0 1 SR2 SR2 Power status register 2 0x14 0x20 read-only 0x00000000 PVMO4 Peripheral voltage monitoring output: VDDA vs. 2.2 V 15 1 PVMO3 Peripheral voltage monitoring output: VDDA vs. 1.62 V 14 1 PVMO2 Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V 13 1 PVMO1 Peripheral voltage monitoring output: VDDUSB vs. 1.2 V 12 1 PVDO Power voltage detector output 11 1 VOSF Voltage scaling flag 10 1 REGLPF Low-power regulator flag 9 1 REGLPS Low-power regulator started 8 1 SCR SCR Power status clear register 0x18 0x20 write-only 0x00000000 SBF Clear standby flag 8 1 WUF5 Clear wakeup flag 5 4 1 WUF4 Clear wakeup flag 4 3 1 WUF3 Clear wakeup flag 3 2 1 WUF2 Clear wakeup flag 2 1 1 WUF1 Clear wakeup flag 1 0 1 PUCRA PUCRA Power Port A pull-up control register 0x20 0x20 read-write 0x00000000 PU15 Port A pull-up bit y (y=0..15) 15 1 PU14 Port A pull-up bit y (y=0..15) 14 1 PU13 Port A pull-up bit y (y=0..15) 13 1 PU12 Port A pull-up bit y (y=0..15) 12 1 PU11 Port A pull-up bit y (y=0..15) 11 1 PU10 Port A pull-up bit y (y=0..15) 10 1 PU9 Port A pull-up bit y (y=0..15) 9 1 PU8 Port A pull-up bit y (y=0..15) 8 1 PU7 Port A pull-up bit y (y=0..15) 7 1 PU6 Port A pull-up bit y (y=0..15) 6 1 PU5 Port A pull-up bit y (y=0..15) 5 1 PU4 Port A pull-up bit y (y=0..15) 4 1 PU3 Port A pull-up bit y (y=0..15) 3 1 PU2 Port A pull-up bit y (y=0..15) 2 1 PU1 Port A pull-up bit y (y=0..15) 1 1 PU0 Port A pull-up bit y (y=0..15) 0 1 PDCRA PDCRA Power Port A pull-down control register 0x24 0x20 read-write 0x00000000 PD15 Port A pull-down bit y (y=0..15) 15 1 PD14 Port A pull-down bit y (y=0..15) 14 1 PD13 Port A pull-down bit y (y=0..15) 13 1 PD12 Port A pull-down bit y (y=0..15) 12 1 PD11 Port A pull-down bit y (y=0..15) 11 1 PD10 Port A pull-down bit y (y=0..15) 10 1 PD9 Port A pull-down bit y (y=0..15) 9 1 PD8 Port A pull-down bit y (y=0..15) 8 1 PD7 Port A pull-down bit y (y=0..15) 7 1 PD6 Port A pull-down bit y (y=0..15) 6 1 PD5 Port A pull-down bit y (y=0..15) 5 1 PD4 Port A pull-down bit y (y=0..15) 4 1 PD3 Port A pull-down bit y (y=0..15) 3 1 PD2 Port A pull-down bit y (y=0..15) 2 1 PD1 Port A pull-down bit y (y=0..15) 1 1 PD0 Port A pull-down bit y (y=0..15) 0 1 PUCRB PUCRB Power Port B pull-up control register 0x28 0x20 read-write 0x00000000 PU15 Port B pull-up bit y (y=0..15) 15 1 PU14 Port B pull-up bit y (y=0..15) 14 1 PU13 Port B pull-up bit y (y=0..15) 13 1 PU12 Port B pull-up bit y (y=0..15) 12 1 PU11 Port B pull-up bit y (y=0..15) 11 1 PU10 Port B pull-up bit y (y=0..15) 10 1 PU9 Port B pull-up bit y (y=0..15) 9 1 PU8 Port B pull-up bit y (y=0..15) 8 1 PU7 Port B pull-up bit y (y=0..15) 7 1 PU6 Port B pull-up bit y (y=0..15) 6 1 PU5 Port B pull-up bit y (y=0..15) 5 1 PU4 Port B pull-up bit y (y=0..15) 4 1 PU3 Port B pull-up bit y (y=0..15) 3 1 PU2 Port B pull-up bit y (y=0..15) 2 1 PU1 Port B pull-up bit y (y=0..15) 1 1 PU0 Port B pull-up bit y (y=0..15) 0 1 PDCRB PDCRB Power Port B pull-down control register 0x2C 0x20 read-write 0x00000000 PD15 Port B pull-down bit y (y=0..15) 15 1 PD14 Port B pull-down bit y (y=0..15) 14 1 PD13 Port B pull-down bit y (y=0..15) 13 1 PD12 Port B pull-down bit y (y=0..15) 12 1 PD11 Port B pull-down bit y (y=0..15) 11 1 PD10 Port B pull-down bit y (y=0..15) 10 1 PD9 Port B pull-down bit y (y=0..15) 9 1 PD8 Port B pull-down bit y (y=0..15) 8 1 PD7 Port B pull-down bit y (y=0..15) 7 1 PD6 Port B pull-down bit y (y=0..15) 6 1 PD5 Port B pull-down bit y (y=0..15) 5 1 PD4 Port B pull-down bit y (y=0..15) 4 1 PD3 Port B pull-down bit y (y=0..15) 3 1 PD2 Port B pull-down bit y (y=0..15) 2 1 PD1 Port B pull-down bit y (y=0..15) 1 1 PD0 Port B pull-down bit y (y=0..15) 0 1 PUCRC PUCRC Power Port C pull-up control register 0x30 0x20 read-write 0x00000000 PU15 Port C pull-up bit y (y=0..15) 15 1 PU14 Port C pull-up bit y (y=0..15) 14 1 PU13 Port C pull-up bit y (y=0..15) 13 1 PU12 Port C pull-up bit y (y=0..15) 12 1 PU11 Port C pull-up bit y (y=0..15) 11 1 PU10 Port C pull-up bit y (y=0..15) 10 1 PU9 Port C pull-up bit y (y=0..15) 9 1 PU8 Port C pull-up bit y (y=0..15) 8 1 PU7 Port C pull-up bit y (y=0..15) 7 1 PU6 Port C pull-up bit y (y=0..15) 6 1 PU5 Port C pull-up bit y (y=0..15) 5 1 PU4 Port C pull-up bit y (y=0..15) 4 1 PU3 Port C pull-up bit y (y=0..15) 3 1 PU2 Port C pull-up bit y (y=0..15) 2 1 PU1 Port C pull-up bit y (y=0..15) 1 1 PU0 Port C pull-up bit y (y=0..15) 0 1 PDCRC PDCRC Power Port C pull-down control register 0x34 0x20 read-write 0x00000000 PD15 Port C pull-down bit y (y=0..15) 15 1 PD14 Port C pull-down bit y (y=0..15) 14 1 PD13 Port C pull-down bit y (y=0..15) 13 1 PD12 Port C pull-down bit y (y=0..15) 12 1 PD11 Port C pull-down bit y (y=0..15) 11 1 PD10 Port C pull-down bit y (y=0..15) 10 1 PD9 Port C pull-down bit y (y=0..15) 9 1 PD8 Port C pull-down bit y (y=0..15) 8 1 PD7 Port C pull-down bit y (y=0..15) 7 1 PD6 Port C pull-down bit y (y=0..15) 6 1 PD5 Port C pull-down bit y (y=0..15) 5 1 PD4 Port C pull-down bit y (y=0..15) 4 1 PD3 Port C pull-down bit y (y=0..15) 3 1 PD2 Port C pull-down bit y (y=0..15) 2 1 PD1 Port C pull-down bit y (y=0..15) 1 1 PD0 Port C pull-down bit y (y=0..15) 0 1 PUCRD PUCRD Power Port D pull-up control register 0x38 0x20 read-write 0x00000000 PU15 Port D pull-up bit y (y=0..15) 15 1 PU14 Port D pull-up bit y (y=0..15) 14 1 PU13 Port D pull-up bit y (y=0..15) 13 1 PU12 Port D pull-up bit y (y=0..15) 12 1 PU11 Port D pull-up bit y (y=0..15) 11 1 PU10 Port D pull-up bit y (y=0..15) 10 1 PU9 Port D pull-up bit y (y=0..15) 9 1 PU8 Port D pull-up bit y (y=0..15) 8 1 PU7 Port D pull-up bit y (y=0..15) 7 1 PU6 Port D pull-up bit y (y=0..15) 6 1 PU5 Port D pull-up bit y (y=0..15) 5 1 PU4 Port D pull-up bit y (y=0..15) 4 1 PU3 Port D pull-up bit y (y=0..15) 3 1 PU2 Port D pull-up bit y (y=0..15) 2 1 PU1 Port D pull-up bit y (y=0..15) 1 1 PU0 Port D pull-up bit y (y=0..15) 0 1 PDCRD PDCRD Power Port D pull-down control register 0x3C 0x20 read-write 0x00000000 PD15 Port D pull-down bit y (y=0..15) 15 1 PD14 Port D pull-down bit y (y=0..15) 14 1 PD13 Port D pull-down bit y (y=0..15) 13 1 PD12 Port D pull-down bit y (y=0..15) 12 1 PD11 Port D pull-down bit y (y=0..15) 11 1 PD10 Port D pull-down bit y (y=0..15) 10 1 PD9 Port D pull-down bit y (y=0..15) 9 1 PD8 Port D pull-down bit y (y=0..15) 8 1 PD7 Port D pull-down bit y (y=0..15) 7 1 PD6 Port D pull-down bit y (y=0..15) 6 1 PD5 Port D pull-down bit y (y=0..15) 5 1 PD4 Port D pull-down bit y (y=0..15) 4 1 PD3 Port D pull-down bit y (y=0..15) 3 1 PD2 Port D pull-down bit y (y=0..15) 2 1 PD1 Port D pull-down bit y (y=0..15) 1 1 PD0 Port D pull-down bit y (y=0..15) 0 1 PUCRE PUCRE Power Port E pull-up control register 0x40 0x20 read-write 0x00000000 PU15 Port E pull-up bit y (y=0..15) 15 1 PU14 Port E pull-up bit y (y=0..15) 14 1 PU13 Port E pull-up bit y (y=0..15) 13 1 PU12 Port E pull-up bit y (y=0..15) 12 1 PU11 Port E pull-up bit y (y=0..15) 11 1 PU10 Port E pull-up bit y (y=0..15) 10 1 PU9 Port E pull-up bit y (y=0..15) 9 1 PU8 Port E pull-up bit y (y=0..15) 8 1 PU7 Port E pull-up bit y (y=0..15) 7 1 PU6 Port E pull-up bit y (y=0..15) 6 1 PU5 Port E pull-up bit y (y=0..15) 5 1 PU4 Port E pull-up bit y (y=0..15) 4 1 PU3 Port E pull-up bit y (y=0..15) 3 1 PU2 Port E pull-up bit y (y=0..15) 2 1 PU1 Port E pull-up bit y (y=0..15) 1 1 PU0 Port E pull-up bit y (y=0..15) 0 1 PDCRE PDCRE Power Port E pull-down control register 0x44 0x20 read-write 0x00000000 PD15 Port E pull-down bit y (y=0..15) 15 1 PD14 Port E pull-down bit y (y=0..15) 14 1 PD13 Port E pull-down bit y (y=0..15) 13 1 PD12 Port E pull-down bit y (y=0..15) 12 1 PD11 Port E pull-down bit y (y=0..15) 11 1 PD10 Port E pull-down bit y (y=0..15) 10 1 PD9 Port E pull-down bit y (y=0..15) 9 1 PD8 Port E pull-down bit y (y=0..15) 8 1 PD7 Port E pull-down bit y (y=0..15) 7 1 PD6 Port E pull-down bit y (y=0..15) 6 1 PD5 Port E pull-down bit y (y=0..15) 5 1 PD4 Port E pull-down bit y (y=0..15) 4 1 PD3 Port E pull-down bit y (y=0..15) 3 1 PD2 Port E pull-down bit y (y=0..15) 2 1 PD1 Port E pull-down bit y (y=0..15) 1 1 PD0 Port E pull-down bit y (y=0..15) 0 1 PUCRF PUCRF Power Port F pull-up control register 0x48 0x20 read-write 0x00000000 PU15 Port F pull-up bit y (y=0..15) 15 1 PU14 Port F pull-up bit y (y=0..15) 14 1 PU13 Port F pull-up bit y (y=0..15) 13 1 PU12 Port F pull-up bit y (y=0..15) 12 1 PU11 Port F pull-up bit y (y=0..15) 11 1 PU10 Port F pull-up bit y (y=0..15) 10 1 PU9 Port F pull-up bit y (y=0..15) 9 1 PU8 Port F pull-up bit y (y=0..15) 8 1 PU7 Port F pull-up bit y (y=0..15) 7 1 PU6 Port F pull-up bit y (y=0..15) 6 1 PU5 Port F pull-up bit y (y=0..15) 5 1 PU4 Port F pull-up bit y (y=0..15) 4 1 PU3 Port F pull-up bit y (y=0..15) 3 1 PU2 Port F pull-up bit y (y=0..15) 2 1 PU1 Port F pull-up bit y (y=0..15) 1 1 PU0 Port F pull-up bit y (y=0..15) 0 1 PDCRF PDCRF Power Port F pull-down control register 0x4C 0x20 read-write 0x00000000 PD15 Port F pull-down bit y (y=0..15) 15 1 PD14 Port F pull-down bit y (y=0..15) 14 1 PD13 Port F pull-down bit y (y=0..15) 13 1 PD12 Port F pull-down bit y (y=0..15) 12 1 PD11 Port F pull-down bit y (y=0..15) 11 1 PD10 Port F pull-down bit y (y=0..15) 10 1 PD9 Port F pull-down bit y (y=0..15) 9 1 PD8 Port F pull-down bit y (y=0..15) 8 1 PD7 Port F pull-down bit y (y=0..15) 7 1 PD6 Port F pull-down bit y (y=0..15) 6 1 PD5 Port F pull-down bit y (y=0..15) 5 1 PD4 Port F pull-down bit y (y=0..15) 4 1 PD3 Port F pull-down bit y (y=0..15) 3 1 PD2 Port F pull-down bit y (y=0..15) 2 1 PD1 Port F pull-down bit y (y=0..15) 1 1 PD0 Port F pull-down bit y (y=0..15) 0 1 PUCRG PUCRG Power Port G pull-up control register 0x50 0x20 read-write 0x00000000 PU15 Port G pull-up bit y (y=0..15) 15 1 PU14 Port G pull-up bit y (y=0..15) 14 1 PU13 Port G pull-up bit y (y=0..15) 13 1 PU12 Port G pull-up bit y (y=0..15) 12 1 PU11 Port G pull-up bit y (y=0..15) 11 1 PU10 Port G pull-up bit y (y=0..15) 10 1 PU9 Port G pull-up bit y (y=0..15) 9 1 PU8 Port G pull-up bit y (y=0..15) 8 1 PU7 Port G pull-up bit y (y=0..15) 7 1 PU6 Port G pull-up bit y (y=0..15) 6 1 PU5 Port G pull-up bit y (y=0..15) 5 1 PU4 Port G pull-up bit y (y=0..15) 4 1 PU3 Port G pull-up bit y (y=0..15) 3 1 PU2 Port G pull-up bit y (y=0..15) 2 1 PU1 Port G pull-up bit y (y=0..15) 1 1 PU0 Port G pull-up bit y (y=0..15) 0 1 PDCRG PDCRG Power Port G pull-down control register 0x54 0x20 read-write 0x00000000 PD15 Port G pull-down bit y (y=0..15) 15 1 PD14 Port G pull-down bit y (y=0..15) 14 1 PD13 Port G pull-down bit y (y=0..15) 13 1 PD12 Port G pull-down bit y (y=0..15) 12 1 PD11 Port G pull-down bit y (y=0..15) 11 1 PD10 Port G pull-down bit y (y=0..15) 10 1 PD9 Port G pull-down bit y (y=0..15) 9 1 PD8 Port G pull-down bit y (y=0..15) 8 1 PD7 Port G pull-down bit y (y=0..15) 7 1 PD6 Port G pull-down bit y (y=0..15) 6 1 PD5 Port G pull-down bit y (y=0..15) 5 1 PD4 Port G pull-down bit y (y=0..15) 4 1 PD3 Port G pull-down bit y (y=0..15) 3 1 PD2 Port G pull-down bit y (y=0..15) 2 1 PD1 Port G pull-down bit y (y=0..15) 1 1 PD0 Port G pull-down bit y (y=0..15) 0 1 PUCRH PUCRH Power Port H pull-up control register 0x58 0x20 read-write 0x00000000 PU1 Port H pull-up bit y (y=0..1) 1 1 PU0 Port H pull-up bit y (y=0..1) 0 1 PDCRH PDCRH Power Port H pull-down control register 0x5C 0x20 read-write 0x00000000 PD1 Port H pull-down bit y (y=0..1) 1 1 PD0 Port H pull-down bit y (y=0..1) 0 1 SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers MEMRMP MEMRMP memory remap register 0x0 0x20 read-write 0x00000000 FB_MODE Flash Bank mode selection 8 1 QFS QUADSPI memory mapping swap 3 1 MEM_MODE Memory mapping selection 0 3 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x7C000001 FPU_IE Floating Point Unit interrupts enable bits 26 6 I2C3_FMP I2C3 Fast-mode Plus driving capability activation 22 1 I2C2_FMP I2C2 Fast-mode Plus driving capability activation 21 1 I2C1_FMP I2C1 Fast-mode Plus driving capability activation 20 1 I2C_PB9_FMP Fast-mode Plus (Fm+) driving capability activation on PB9 19 1 I2C_PB8_FMP Fast-mode Plus (Fm+) driving capability activation on PB8 18 1 I2C_PB7_FMP Fast-mode Plus (Fm+) driving capability activation on PB7 17 1 I2C_PB6_FMP Fast-mode Plus (Fm+) driving capability activation on PB6 16 1 BOOSTEN I/O analog switch voltage booster enable 8 1 FWDIS Firewall disable 0 1 EXTICR1 EXTICR1 external interrupt configuration register 1 0x8 0x20 read-write 0x00000000 EXTI3 EXTI 3 configuration bits 12 3 EXTI2 EXTI 2 configuration bits 8 3 EXTI1 EXTI 1 configuration bits 4 3 EXTI0 EXTI 0 configuration bits 0 3 EXTICR2 EXTICR2 external interrupt configuration register 2 0xC 0x20 read-write 0x00000000 EXTI7 EXTI 7 configuration bits 12 3 EXTI6 EXTI 6 configuration bits 8 3 EXTI5 EXTI 5 configuration bits 4 3 EXTI4 EXTI 4 configuration bits 0 3 EXTICR3 EXTICR3 external interrupt configuration register 3 0x10 0x20 read-write 0x00000000 EXTI11 EXTI 11 configuration bits 12 3 EXTI10 EXTI 10 configuration bits 8 3 EXTI9 EXTI 9 configuration bits 4 3 EXTI8 EXTI 8 configuration bits 0 3 EXTICR4 EXTICR4 external interrupt configuration register 4 0x14 0x20 read-write 0x00000000 EXTI15 EXTI15 configuration bits 12 3 EXTI14 EXTI14 configuration bits 8 3 EXTI13 EXTI13 configuration bits 4 3 EXTI12 EXTI12 configuration bits 0 3 SCSR SCSR SCSR 0x18 0x20 0x00000000 SRAM2BSY SRAM2 busy by erase operation 1 1 read-only SRAM2ER SRAM2 Erase 0 1 read-write CFGR2 CFGR2 CFGR2 0x1C 0x20 0x00000000 SPF SRAM2 parity error flag 8 1 read-write ECCL ECC Lock 3 1 write-only PVDL PVD lock enable bit 2 1 write-only SPL SRAM2 parity lock bit 1 1 write-only CLL OCKUP (Hardfault) output enable bit 0 1 write-only SWPR SWPR SWPR 0x20 0x20 write-only 0x00000000 P31WP SRAM2 page 31 write protection 31 1 P30WP P30WP 30 1 P29WP P29WP 29 1 P28WP P28WP 28 1 P27WP P27WP 27 1 P26WP P26WP 26 1 P25WP P25WP 25 1 P24WP P24WP 24 1 P23WP P23WP 23 1 P22WP P22WP 22 1 P21WP P21WP 21 1 P20WP P20WP 20 1 P19WP P19WP 19 1 P18WP P18WP 18 1 P17WP P17WP 17 1 P16WP P16WP 16 1 P15WP P15WP 15 1 P14WP P14WP 14 1 P13WP P13WP 13 1 P12WP P12WP 12 1 P11WP P11WP 11 1 P10WP P10WP 10 1 P9WP P9WP 9 1 P8WP P8WP 8 1 P7WP P7WP 7 1 P6WP P6WP 6 1 P5WP P5WP 5 1 P4WP P4WP 4 1 P3WP P3WP 3 1 P2WP P2WP 2 1 P1WP P1WP 1 1 P0WP P0WP 0 1 SKR SKR SKR 0x24 0x20 write-only 0x00000000 KEY SRAM2 write protection key for software erase 0 8 RNG Random number generator RNG 0x50060800 0x0 0x400 registers RNG RNG global interrupt 80 CR CR control register 0x0 0x20 read-write 0x00000000 IE Interrupt enable 3 1 RNGEN Random number generator enable 2 1 SR SR status register 0x4 0x20 0x00000000 SEIS Seed error interrupt status 6 1 read-write CEIS Clock error interrupt status 5 1 read-write SECS Seed error current status 2 1 read-only CECS Clock error current status 1 1 read-only DRDY Data ready 0 1 read-only DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 AES Advanced encryption standard hardware accelerator AES 0x50060000 0x0 0x400 registers AES AES global interrupt 79 CR CR control register 0x0 0x20 read-write 0x00000000 DMAOUTEN Enable DMA management of data output phase 12 1 DMAINEN Enable DMA management of data input phase 11 1 ERRIE Error interrupt enable 10 1 CCFIE CCF flag interrupt enable 9 1 ERRC Error clear 8 1 CCFC Computation Complete Flag Clear 7 1 CHMOD AES chaining mode 5 2 MODE AES operating mode 3 2 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 EN AES enable 0 1 SR SR status register 0x4 0x20 read-only 0x00000000 WRERR Write error flag 2 1 RDERR Read error flag 1 1 CCF Computation complete flag 0 1 DINR DINR data input register 0x8 0x20 read-write 0x00000000 AES_DINR Data Input Register 0 32 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 AES_DOUTR Data output register 0 32 KEYR0 KEYR0 key register 0 0x10 0x20 read-write 0x00000000 AES_KEYR0 Data Output Register (LSB key [31:0]) 0 32 KEYR1 KEYR1 key register 1 0x14 0x20 read-write 0x00000000 AES_KEYR1 AES key register (key [63:32]) 0 32 KEYR2 KEYR2 key register 2 0x18 0x20 read-write 0x00000000 AES_KEYR2 AES key register (key [95:64]) 0 32 KEYR3 KEYR3 key register 3 0x1C 0x20 read-write 0x00000000 AES_KEYR3 AES key register (MSB key [127:96]) 0 32 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 AES_IVR0 initialization vector register (LSB IVR [31:0]) 0 32 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 AES_IVR1 Initialization Vector Register (IVR [63:32]) 0 32 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 AES_IVR2 Initialization Vector Register (IVR [95:64]) 0 32 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 AES_IVR3 Initialization Vector Register (MSB IVR [127:96]) 0 32 ADC Analog-to-Digital Converter ADC 0x50040000 0x0 0xB9 registers ADC1 ADC1 and ADC2 global interrupt 18 ISR ISR interrupt and status register 0x0 0x20 read-write 0x00000000 JQOVF JQOVF 10 1 AWD3 AWD3 9 1 AWD2 AWD2 8 1 AWD1 AWD1 7 1 JEOS JEOS 6 1 JEOC JEOC 5 1 OVR OVR 4 1 EOS EOS 3 1 EOC EOC 2 1 EOSMP EOSMP 1 1 ADRDY ADRDY 0 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 JQOVFIE JQOVFIE 10 1 AWD3IE AWD3IE 9 1 AWD2IE AWD2IE 8 1 AWD1IE AWD1IE 7 1 JEOSIE JEOSIE 6 1 JEOCIE JEOCIE 5 1 OVRIE OVRIE 4 1 EOSIE EOSIE 3 1 EOCIE EOCIE 2 1 EOSMPIE EOSMPIE 1 1 ADRDYIE ADRDYIE 0 1 CR CR control register 0x8 0x20 read-write 0x00000000 ADCAL ADCAL 31 1 ADCALDIF ADCALDIF 30 1 DEEPPWD DEEPPWD 29 1 ADVREGEN ADVREGEN 28 1 JADSTP JADSTP 5 1 ADSTP ADSTP 4 1 JADSTART JADSTART 3 1 ADSTART ADSTART 2 1 ADDIS ADDIS 1 1 ADEN ADEN 0 1 CFGR CFGR configuration register 0xC 0x20 read-write 0x00000000 AWDCH1CH AWDCH1CH 26 5 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 JQM JQM 21 1 JDISCEN JDISCEN 20 1 DISCNUM DISCNUM 17 3 DISCEN DISCEN 16 1 AUTOFF AUTOFF 15 1 AUTDLY AUTDLY 14 1 CONT CONT 13 1 OVRMOD OVRMOD 12 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 6 4 ALIGN ALIGN 5 1 RES RES 3 2 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 CFGR2 CFGR2 configuration register 0x10 0x20 read-write 0x00000000 ROVSM EXTEN 10 1 TOVS EXTSEL 9 1 OVSS ALIGN 5 4 OVSR RES 2 3 JOVSE DMACFG 1 1 ROVSE DMAEN 0 1 SMPR1 SMPR1 sample time register 1 0x14 0x20 read-write 0x00000000 SMP9 SMP9 27 3 SMP8 SMP8 24 3 SMP7 SMP7 21 3 SMP6 SMP6 18 3 SMP5 SMP5 15 3 SMP4 SMP4 12 3 SMP3 SMP3 9 3 SMP2 SMP2 6 3 SMP1 SMP1 3 3 SMPR2 SMPR2 sample time register 2 0x18 0x20 read-write 0x00000000 SMP18 SMP18 24 3 SMP17 SMP17 21 3 SMP16 SMP16 18 3 SMP15 SMP15 15 3 SMP14 SMP14 12 3 SMP13 SMP13 9 3 SMP12 SMP12 6 3 SMP11 SMP11 3 3 SMP10 SMP10 0 3 TR1 TR1 watchdog threshold register 1 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 LT1 LT1 0 12 TR2 TR2 watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 HT2 16 8 LT2 LT2 0 8 TR3 TR3 watchdog threshold register 3 0x28 0x20 read-write 0x0FFF0000 HT3 HT3 16 8 LT3 LT3 0 8 SQR1 SQR1 regular sequence register 1 0x30 0x20 read-write 0x00000000 SQ4 SQ4 24 5 SQ3 SQ3 18 5 SQ2 SQ2 12 5 SQ1 SQ1 6 5 L3 L3 0 4 SQR2 SQR2 regular sequence register 2 0x34 0x20 read-write 0x00000000 SQ9 SQ9 24 5 SQ8 SQ8 18 5 SQ7 SQ7 12 5 SQ6 SQ6 6 5 SQ5 SQ5 0 5 SQR3 SQR3 regular sequence register 3 0x38 0x20 read-write 0x00000000 SQ14 SQ14 24 5 SQ13 SQ13 18 5 SQ12 SQ12 12 5 SQ11 SQ11 6 5 SQ10 SQ10 0 5 SQR4 SQR4 regular sequence register 4 0x3C 0x20 read-write 0x00000000 SQ16 SQ16 6 5 SQ15 SQ15 0 5 DR DR regular Data Register 0x40 0x20 read-only 0x00000000 regularDATA regularDATA 0 16 JSQR JSQR injected sequence register 0x4C 0x20 read-write 0x00000000 JSQ4 JSQ4 26 5 JSQ3 JSQ3 20 5 JSQ2 JSQ2 14 5 JSQ1 JSQ1 8 5 JEXTEN JEXTEN 6 2 JEXTSEL JEXTSEL 2 4 JL JL 0 2 OFR1 OFR1 offset register 1 0x60 0x20 read-write 0x00000000 OFFSET1_EN OFFSET1_EN 31 1 OFFSET1_CH OFFSET1_CH 26 5 OFFSET1 OFFSET1 0 12 OFR2 OFR2 offset register 2 0x64 0x20 read-write 0x00000000 OFFSET2_EN OFFSET2_EN 31 1 OFFSET2_CH OFFSET2_CH 26 5 OFFSET2 OFFSET2 0 12 OFR3 OFR3 offset register 3 0x68 0x20 read-write 0x00000000 OFFSET3_EN OFFSET3_EN 31 1 OFFSET3_CH OFFSET3_CH 26 5 OFFSET3 OFFSET3 0 12 OFR4 OFR4 offset register 4 0x6C 0x20 read-write 0x00000000 OFFSET4_EN OFFSET4_EN 31 1 OFFSET4_CH OFFSET4_CH 26 5 OFFSET4 OFFSET4 0 12 JDR1 JDR1 injected data register 1 0x80 0x20 read-only 0x00000000 JDATA1 JDATA1 0 16 JDR2 JDR2 injected data register 2 0x84 0x20 read-only 0x00000000 JDATA2 JDATA2 0 16 JDR3 JDR3 injected data register 3 0x88 0x20 read-only 0x00000000 JDATA3 JDATA3 0 16 JDR4 JDR4 injected data register 4 0x8C 0x20 read-only 0x00000000 JDATA4 JDATA4 0 16 AWD2CR AWD2CR Analog Watchdog 2 Configuration Register 0xA0 0x20 read-write 0x00000000 AWD2CH AWD2CH 1 18 AWD3CR AWD3CR Analog Watchdog 3 Configuration Register 0xA4 0x20 read-write 0x00000000 AWD3CH AWD3CH 1 18 DIFSEL DIFSEL Differential Mode Selection Register 2 0xB0 0x20 0x00000000 DIFSEL_1_15 Differential mode for channels 15 to 1 1 15 read-write DIFSEL_16_18 Differential mode for channels 18 to 16 16 3 read-only CALFACT CALFACT Calibration Factors 0xB4 0x20 read-write 0x00000000 CALFACT_D CALFACT_D 16 7 CALFACT_S CALFACT_S 0 7 GPIOA General-purpose I/Os GPIO 0x48000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xA8000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x64000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOB General-purpose I/Os GPIO 0x48000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000280 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x000000C0 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000100 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOC General-purpose I/Os GPIO 0x48000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0x00000000 MODER15 Port x configuration bits (y = 0..15) 30 2 MODER14 Port x configuration bits (y = 0..15) 28 2 MODER13 Port x configuration bits (y = 0..15) 26 2 MODER12 Port x configuration bits (y = 0..15) 24 2 MODER11 Port x configuration bits (y = 0..15) 22 2 MODER10 Port x configuration bits (y = 0..15) 20 2 MODER9 Port x configuration bits (y = 0..15) 18 2 MODER8 Port x configuration bits (y = 0..15) 16 2 MODER7 Port x configuration bits (y = 0..15) 14 2 MODER6 Port x configuration bits (y = 0..15) 12 2 MODER5 Port x configuration bits (y = 0..15) 10 2 MODER4 Port x configuration bits (y = 0..15) 8 2 MODER3 Port x configuration bits (y = 0..15) 6 2 MODER2 Port x configuration bits (y = 0..15) 4 2 MODER1 Port x configuration bits (y = 0..15) 2 2 MODER0 Port x configuration bits (y = 0..15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y = 0..15) 15 1 OT14 Port x configuration bits (y = 0..15) 14 1 OT13 Port x configuration bits (y = 0..15) 13 1 OT12 Port x configuration bits (y = 0..15) 12 1 OT11 Port x configuration bits (y = 0..15) 11 1 OT10 Port x configuration bits (y = 0..15) 10 1 OT9 Port x configuration bits (y = 0..15) 9 1 OT8 Port x configuration bits (y = 0..15) 8 1 OT7 Port x configuration bits (y = 0..15) 7 1 OT6 Port x configuration bits (y = 0..15) 6 1 OT5 Port x configuration bits (y = 0..15) 5 1 OT4 Port x configuration bits (y = 0..15) 4 1 OT3 Port x configuration bits (y = 0..15) 3 1 OT2 Port x configuration bits (y = 0..15) 2 1 OT1 Port x configuration bits (y = 0..15) 1 1 OT0 Port x configuration bits (y = 0..15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x00000000 OSPEEDR15 Port x configuration bits (y = 0..15) 30 2 OSPEEDR14 Port x configuration bits (y = 0..15) 28 2 OSPEEDR13 Port x configuration bits (y = 0..15) 26 2 OSPEEDR12 Port x configuration bits (y = 0..15) 24 2 OSPEEDR11 Port x configuration bits (y = 0..15) 22 2 OSPEEDR10 Port x configuration bits (y = 0..15) 20 2 OSPEEDR9 Port x configuration bits (y = 0..15) 18 2 OSPEEDR8 Port x configuration bits (y = 0..15) 16 2 OSPEEDR7 Port x configuration bits (y = 0..15) 14 2 OSPEEDR6 Port x configuration bits (y = 0..15) 12 2 OSPEEDR5 Port x configuration bits (y = 0..15) 10 2 OSPEEDR4 Port x configuration bits (y = 0..15) 8 2 OSPEEDR3 Port x configuration bits (y = 0..15) 6 2 OSPEEDR2 Port x configuration bits (y = 0..15) 4 2 OSPEEDR1 Port x configuration bits (y = 0..15) 2 2 OSPEEDR0 Port x configuration bits (y = 0..15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x00000000 PUPDR15 Port x configuration bits (y = 0..15) 30 2 PUPDR14 Port x configuration bits (y = 0..15) 28 2 PUPDR13 Port x configuration bits (y = 0..15) 26 2 PUPDR12 Port x configuration bits (y = 0..15) 24 2 PUPDR11 Port x configuration bits (y = 0..15) 22 2 PUPDR10 Port x configuration bits (y = 0..15) 20 2 PUPDR9 Port x configuration bits (y = 0..15) 18 2 PUPDR8 Port x configuration bits (y = 0..15) 16 2 PUPDR7 Port x configuration bits (y = 0..15) 14 2 PUPDR6 Port x configuration bits (y = 0..15) 12 2 PUPDR5 Port x configuration bits (y = 0..15) 10 2 PUPDR4 Port x configuration bits (y = 0..15) 8 2 PUPDR3 Port x configuration bits (y = 0..15) 6 2 PUPDR2 Port x configuration bits (y = 0..15) 4 2 PUPDR1 Port x configuration bits (y = 0..15) 2 2 PUPDR0 Port x configuration bits (y = 0..15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 IDR15 Port input data (y = 0..15) 15 1 IDR14 Port input data (y = 0..15) 14 1 IDR13 Port input data (y = 0..15) 13 1 IDR12 Port input data (y = 0..15) 12 1 IDR11 Port input data (y = 0..15) 11 1 IDR10 Port input data (y = 0..15) 10 1 IDR9 Port input data (y = 0..15) 9 1 IDR8 Port input data (y = 0..15) 8 1 IDR7 Port input data (y = 0..15) 7 1 IDR6 Port input data (y = 0..15) 6 1 IDR5 Port input data (y = 0..15) 5 1 IDR4 Port input data (y = 0..15) 4 1 IDR3 Port input data (y = 0..15) 3 1 IDR2 Port input data (y = 0..15) 2 1 IDR1 Port input data (y = 0..15) 1 1 IDR0 Port input data (y = 0..15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 ODR15 Port output data (y = 0..15) 15 1 ODR14 Port output data (y = 0..15) 14 1 ODR13 Port output data (y = 0..15) 13 1 ODR12 Port output data (y = 0..15) 12 1 ODR11 Port output data (y = 0..15) 11 1 ODR10 Port output data (y = 0..15) 10 1 ODR9 Port output data (y = 0..15) 9 1 ODR8 Port output data (y = 0..15) 8 1 ODR7 Port output data (y = 0..15) 7 1 ODR6 Port output data (y = 0..15) 6 1 ODR5 Port output data (y = 0..15) 5 1 ODR4 Port output data (y = 0..15) 4 1 ODR3 Port output data (y = 0..15) 3 1 ODR2 Port output data (y = 0..15) 2 1 ODR1 Port output data (y = 0..15) 1 1 ODR0 Port output data (y = 0..15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y = 0..15) 31 1 BR14 Port x reset bit y (y = 0..15) 30 1 BR13 Port x reset bit y (y = 0..15) 29 1 BR12 Port x reset bit y (y = 0..15) 28 1 BR11 Port x reset bit y (y = 0..15) 27 1 BR10 Port x reset bit y (y = 0..15) 26 1 BR9 Port x reset bit y (y = 0..15) 25 1 BR8 Port x reset bit y (y = 0..15) 24 1 BR7 Port x reset bit y (y = 0..15) 23 1 BR6 Port x reset bit y (y = 0..15) 22 1 BR5 Port x reset bit y (y = 0..15) 21 1 BR4 Port x reset bit y (y = 0..15) 20 1 BR3 Port x reset bit y (y = 0..15) 19 1 BR2 Port x reset bit y (y = 0..15) 18 1 BR1 Port x reset bit y (y = 0..15) 17 1 BR0 Port x set bit y (y= 0..15) 16 1 BS15 Port x set bit y (y= 0..15) 15 1 BS14 Port x set bit y (y= 0..15) 14 1 BS13 Port x set bit y (y= 0..15) 13 1 BS12 Port x set bit y (y= 0..15) 12 1 BS11 Port x set bit y (y= 0..15) 11 1 BS10 Port x set bit y (y= 0..15) 10 1 BS9 Port x set bit y (y= 0..15) 9 1 BS8 Port x set bit y (y= 0..15) 8 1 BS7 Port x set bit y (y= 0..15) 7 1 BS6 Port x set bit y (y= 0..15) 6 1 BS5 Port x set bit y (y= 0..15) 5 1 BS4 Port x set bit y (y= 0..15) 4 1 BS3 Port x set bit y (y= 0..15) 3 1 BS2 Port x set bit y (y= 0..15) 2 1 BS1 Port x set bit y (y= 0..15) 1 1 BS0 Port x set bit y (y= 0..15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock bit y (y= 0..15) 16 1 LCK15 Port x lock bit y (y= 0..15) 15 1 LCK14 Port x lock bit y (y= 0..15) 14 1 LCK13 Port x lock bit y (y= 0..15) 13 1 LCK12 Port x lock bit y (y= 0..15) 12 1 LCK11 Port x lock bit y (y= 0..15) 11 1 LCK10 Port x lock bit y (y= 0..15) 10 1 LCK9 Port x lock bit y (y= 0..15) 9 1 LCK8 Port x lock bit y (y= 0..15) 8 1 LCK7 Port x lock bit y (y= 0..15) 7 1 LCK6 Port x lock bit y (y= 0..15) 6 1 LCK5 Port x lock bit y (y= 0..15) 5 1 LCK4 Port x lock bit y (y= 0..15) 4 1 LCK3 Port x lock bit y (y= 0..15) 3 1 LCK2 Port x lock bit y (y= 0..15) 2 1 LCK1 Port x lock bit y (y= 0..15) 1 1 LCK0 Port x lock bit y (y= 0..15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFRL7 Alternate function selection for port x bit y (y = 0..7) 28 4 AFRL6 Alternate function selection for port x bit y (y = 0..7) 24 4 AFRL5 Alternate function selection for port x bit y (y = 0..7) 20 4 AFRL4 Alternate function selection for port x bit y (y = 0..7) 16 4 AFRL3 Alternate function selection for port x bit y (y = 0..7) 12 4 AFRL2 Alternate function selection for port x bit y (y = 0..7) 8 4 AFRL1 Alternate function selection for port x bit y (y = 0..7) 4 4 AFRL0 Alternate function selection for port x bit y (y = 0..7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFRH15 Alternate function selection for port x bit y (y = 8..15) 28 4 AFRH14 Alternate function selection for port x bit y (y = 8..15) 24 4 AFRH13 Alternate function selection for port x bit y (y = 8..15) 20 4 AFRH12 Alternate function selection for port x bit y (y = 8..15) 16 4 AFRH11 Alternate function selection for port x bit y (y = 8..15) 12 4 AFRH10 Alternate function selection for port x bit y (y = 8..15) 8 4 AFRH9 Alternate function selection for port x bit y (y = 8..15) 4 4 AFRH8 Alternate function selection for port x bit y (y = 8..15) 0 4 GPIOD 0x48000C00 GPIOE 0x48001000 GPIOH 0x48001C00 SAI1 Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI1 SAI1 global interrupt 74 BCR1 BCR1 BConfiguration register 1 0x24 0x20 read-write 0x00000040 MCJDIV Master clock divider 20 4 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIBEN Audio block B enable 16 1 OutDri Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 BCR2 BCR2 BConfiguration register 2 0x28 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 BFRCR BFRCR BFRCR 0x2C 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 FSDEF Frame synchronization definition 16 1 FSALL Frame synchronization active level length 8 7 FRL Frame length 0 8 BSLOTR BSLOTR BSlot register 0x30 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 BIM BIM BInterrupt mask register2 0x34 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFG Wrong clock configuration interrupt enable 2 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 BSR BSR BStatus register 0x38 0x20 read-only 0x00000000 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 BCLRFR BCLRFR BClear flag register 0x3C 0x20 write-only 0x00000000 LFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 WCKCFG Clear wrong clock configuration flag 2 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 BDR BDR BData register 0x40 0x20 read-write 0x00000000 DATA Data 0 32 ACR1 ACR1 AConfiguration register 1 0x4 0x20 read-write 0x00000040 MCJDIV Master clock divider 20 4 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIAEN Audio block A enable 16 1 OutDri Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 ACR2 ACR2 AConfiguration register 2 0x8 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUS FIFO flush 3 1 FTH FIFO threshold 0 3 AFRCR AFRCR AFRCR 0xC 0x20 read-write 0x00000007 FSOFF Frame synchronization offset 18 1 FSPOL Frame synchronization polarity 17 1 FSDEF Frame synchronization definition 16 1 FSALL Frame synchronization active level length 8 7 FRL Frame length 0 8 ASLOTR ASLOTR ASlot register 0x10 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 AIM AIM AInterrupt mask register2 0x14 0x20 read-write 0x00000000 LFSDET Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFG Wrong clock configuration interrupt enable 2 1 MUTEDET Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 ASR ASR AStatus register 0x18 0x20 read-write 0x00000000 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 ACLRFR ACLRFR AClear flag register 0x1C 0x20 read-write 0x00000000 LFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CNRDY Clear codec not ready flag 4 1 WCKCFG Clear wrong clock configuration flag 2 1 MUTEDET Mute detection flag 1 1 OVRUDR Clear overrun / underrun 0 1 ADR ADR AData register 0x20 0x20 read-write 0x00000000 DATA Data 0 32 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 28 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H High counter value (TIM2 only) 16 16 CNT_L Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR OR TIM2 option register 0x50 0x20 read-write 0x0000 ETR_RMP Timer2 ETR remap 0 3 TI4_RMP Internal trigger 3 2 TIM3 0x40000400 TIM3 TIM3 global interrupt 29 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM1_BRK_TIM15 Timer 15 global interrupt 24 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_2 Output Compare 1 mode 16 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKF Break filter 16 4 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers TIM1_UP_TIM16 Timer 16 global interrupt 25 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CEN Counter enable 0 1 UDIS Update disable 1 1 URS Update request source 2 1 OPM One-pulse mode 3 1 ARPE Auto-reload preload enable 7 1 CKD Clock division 8 2 UIFREMAP UIF status bit remapping 11 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_2 Output Compare 1 mode 16 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 CNT counter value 0 16 read-write UIFCPY UIF Copy 31 1 read-only PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 DTG Dead-time generator setup 0 8 LOCK Lock configuration 8 2 OSSI Off-state selection for Idle mode 10 1 OSSR Off-state selection for Run mode 11 1 BKE Break enable 12 1 BKP Break polarity 13 1 AOE Automatic output enable 14 1 MOE Main output enable 15 1 BKF Break filter 16 4 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR1 OR1 TIM16 option register 1 0x50 0x20 read-write 0x0000 TI1_RMP Input capture 1 remap 0 2 OR2 OR2 TIM17 option register 1 0x60 0x20 read-write 0x0000 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDFBK1E BRK DFSDM_BREAK1 enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarit 11 1 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_TRG_COM TIM1 trigger and commutation interrupt 26 TIM1_CC TIM1 Capture Compare interrupt 27 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 SR SR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 DCR DCR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 OR1 OR1 DMA address for full transfer 0x50 0x20 read-write 0x0000 ETR_ADC1_RMP External trigger remap on ADC1 analog watchdog 0 2 ETR_ADC3_RMP External trigger remap on ADC3 analog watchdog 2 2 TI1_RMP Input Capture 1 remap 4 1 CCMR3_Output CCMR3_Output capture/compare mode register 2 (output mode) 0x54 0x20 read-write 0x00000000 OC6M_bit3 Output Compare 6 mode bit 3 24 1 OC5M_bit3 Output Compare 5 mode bit 3 16 3 OC6CE Output compare 6 clear enable 15 1 OC6M Output compare 6 mode 12 3 OC6PE Output compare 6 preload enable 11 1 OC6FE Output compare 6 fast enable 10 1 OC5CE Output compare 5 clear enable 7 1 OC5M Output compare 5 mode 4 3 OC5PE Output compare 5 preload enable 3 1 OC5FE Output compare 5 fast enable 2 1 CCR5 CCR5 capture/compare register 4 0x58 0x20 read-write 0x00000000 CCR5 Capture/Compare value 0 16 GC5C1 Group Channel 5 and Channel 1 29 1 GC5C2 Group Channel 5 and Channel 2 30 1 GC5C3 Group Channel 5 and Channel 3 31 1 CCR6 CCR6 capture/compare register 4 0x5C 0x20 read-write 0x00000000 CCR6 Capture/Compare value 0 16 OR2 OR2 DMA address for full transfer 0x60 0x20 read-write 0x00000001 BKINE BRK BKIN input enable 0 1 BKCMP1E BRK COMP1 enable 1 1 BKCMP2E BRK COMP2 enable 2 1 BKDFBK0E BRK DFSDM_BREAK0 enable 8 1 BKINP BRK BKIN input polarity 9 1 BKCMP1P BRK COMP1 input polarity 10 1 BKCMP2P BRK COMP2 input polarity 11 1 ETRSEL ETR source selection 14 3 OR3 OR3 DMA address for full transfer 0x64 0x20 read-write 0x00000001 BK2INE BRK2 BKIN input enable 0 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2DFBK0E BRK2 DFSDM_BREAK0 enable 8 1 BK2INP BRK2 BKIN input polarity 9 1 BK2CMP1P BRK2 COMP1 input polarity 10 1 BK2CMP2P BRK2 COMP2 input polarity 11 1 TIM6 Basic-timers TIM 0x40001000 0x0 0x400 registers TIM6_DACUNDER TIM6 global and DAC1 and 2 underrun error interrupts 54 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 UDE Update DMA request enable 8 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG Update generation 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT Low counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Low Auto-reload value 0 16 TIM7 0x40001400 TIM7 TIM7 global interrupt 55 LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LP TIM1 interrupt 65 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMPOK Compare register update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CMPM Compare match 0 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMPOKCF Compare register update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CMPMCF compare match Clear Flag 0 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMPOKIE Compare register update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CMPMIE Compare match Interrupt Enable 0 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 CMP CMP Compare Register 0x14 0x20 read-write 0x00000000 CMP Compare value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 LPTIM2 0x40009400 LPTIM2 LP TIM2 interrupt 66 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 37 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 M1 Word length 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT4 Driver Enable assertion time 25 1 DEAT3 DEAT3 24 1 DEAT2 DEAT2 23 1 DEAT1 DEAT1 22 1 DEAT0 DEAT0 21 1 DEDT4 Driver Enable de-assertion time 20 1 DEDT3 DEDT3 19 1 DEDT2 DEDT2 18 1 DEDT1 DEDT1 17 1 DEDT0 DEDT0 16 1 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD1 Auto baud rate mode 22 1 ABRMOD0 ABRMOD0 21 1 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 DIV_Mantissa DIV_Mantissa 4 12 DIV_Fraction DIV_Fraction 0 4 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x0000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 USART2 0x40004400 USART2 USART2 global interrupt 38 UART4 0x40004C00 UART4 UART4 global Interrupt 52 USART3 Universal synchronous asynchronous receiver transmitter USART 0x40004800 0x0 0x400 registers USART3 USART3 global interrupt 39 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 M1 Word length 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT4 Driver Enable assertion time 25 1 DEAT3 DEAT3 24 1 DEAT2 DEAT2 23 1 DEAT1 DEAT1 22 1 DEAT0 DEAT0 21 1 DEDT4 Driver Enable de-assertion time 20 1 DEDT3 DEDT3 19 1 DEDT2 DEDT2 18 1 DEDT1 DEDT1 17 1 DEDT0 DEDT0 16 1 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 RTOEN Receiver timeout enable 23 1 ABRMOD1 Auto baud rate mode 22 1 ABRMOD0 ABRMOD0 21 1 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 UCESM USART Clock Enable in Stop mode 23 1 TCBGTIE Transmission complete before guard time interrupt enable 24 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR USARTDIV 0 12 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x0000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 TCBGT Transmission complete before guard time completion 25 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 LPUART1 Universal synchronous asynchronous receiver transmitter USART 0x40008000 0x0 0x400 registers LPUART1 LPUART1 global interrupt 70 CR1 CR1 Control register 1 0x0 0x20 read-write 0x0000 M1 Word length 28 1 DEAT4 Driver Enable assertion time 25 1 DEAT3 DEAT3 24 1 DEAT2 DEAT2 23 1 DEAT1 DEAT1 22 1 DEAT0 DEAT0 21 1 DEDT4 Driver Enable de-assertion time 20 1 DEDT3 DEDT3 19 1 DEDT2 DEDT2 18 1 DEDT1 DEDT1 17 1 DEDT0 DEDT0 16 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD4_7 Address of the USART node 28 4 ADD0_3 Address of the USART node 24 4 MSBFIRST Most significant bit first 19 1 TAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 WUFIE Wakeup from Stop mode interrupt enable 22 1 WUS Wakeup from Stop mode interrupt flag selection 20 2 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR BRR 0 20 RQR RQR Request register 0x18 0x20 write-only 0x0000 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ISR ISR Interrupt & status register 0x1C 0x20 read-only 0x00C0 REACK REACK 22 1 TEACK TEACK 21 1 WUF WUF 20 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NF NF 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 WUCF Wakeup from Stop mode clear flag 20 1 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NCF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 SPI1 Serial peripheral interface/Inter-IC sound SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 35 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 RXDMAEN Rx buffer DMA enable 0 1 TXDMAEN Tx buffer DMA enable 1 1 SSOE SS output enable 2 1 NSSP NSS pulse management 3 1 FRF Frame format 4 1 ERRIE Error interrupt enable 5 1 RXNEIE RX buffer not empty interrupt enable 6 1 TXEIE Tx buffer empty interrupt enable 7 1 DS Data size 8 4 FRXTH FIFO reception threshold 12 1 LDMA_RX Last DMA transfer for reception 13 1 LDMA_TX Last DMA transfer for transmission 14 1 SR SR status register 0x8 0x20 0x0002 RXNE Receive buffer not empty 0 1 read-only TXE Transmit buffer empty 1 1 read-only CRCERR CRC error flag 4 1 read-write MODF Mode fault 5 1 read-only OVR Overrun flag 6 1 read-only BSY Busy flag 7 1 read-only TIFRFE TI frame format error 8 1 read-only FRLVL FIFO reception level 9 2 read-only FTLVL FIFO transmission level 11 2 read-only DR DR data register 0xC 0x20 read-write 0x0000 DR Data register 0 16 CRCPR CRCPR CRC polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RXCRCR RXCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 TXCRCR TXCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 SPI3 0x40003C00 SPI3 SPI3 global Interrupt 51 SPI2 0x40003800 SPI2 SPI2 global interrupt 36 SDMMC Secure digital input/output interface SDIO 0x40012800 0x0 0x400 registers SDMMC1 SDMMC global Interrupt 49 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL PWRCTRL 0 2 CLKCR CLKCR SDI clock control register 0x4 0x20 read-write 0x00000000 HWFC_EN HW Flow Control enable 14 1 NEGEDGE SDIO_CK dephasing selection bit 13 1 WIDBUS Wide bus mode enable bit 11 2 BYPASS Clock divider bypass enable bit 10 1 PWRSAV Power saving configuration bit 9 1 CLKEN Clock enable bit 8 1 CLKDIV Clock divide factor 0 8 ARG ARG argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 CMD CMD command register 0xC 0x20 read-write 0x00000000 CE_ATACMD CE-ATA command 14 1 nIEN not Interrupt Enable 13 1 ENCMDcompl Enable CMD completion 12 1 SDIOSuspend SD I/O suspend command 11 1 CPSMEN Command path state machine (CPSM) Enable bit 10 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal) 9 1 WAITINT CPSM waits for interrupt request 8 1 WAITRESP Wait for response bits 6 2 CMDINDEX Command index 0 6 RESPCMD RESPCMD command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 RESP1 RESP1 response 1..4 register 0x14 0x20 read-only 0x00000000 CARDSTATUS1 see Table 132 0 32 RESP2 RESP2 response 1..4 register 0x18 0x20 read-only 0x00000000 CARDSTATUS2 see Table 132 0 32 RESP3 RESP3 response 1..4 register 0x1C 0x20 read-only 0x00000000 CARDSTATUS3 see Table 132 0 32 RESP4 RESP4 response 1..4 register 0x20 0x20 read-only 0x00000000 CARDSTATUS4 see Table 132 0 32 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data timeout period 0 32 DLEN DLEN data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 SDIOEN SD I/O enable functions 11 1 RWMOD Read wait mode 10 1 RWSTOP Read wait stop 9 1 RWSTART Read wait start 8 1 DBLOCKSIZE Data block size 4 4 DMAEN DMA enable bit 3 1 DTMODE Data transfer mode selection 1: Stream or SDIO multibyte data transfer 2 1 DTDIR Data transfer direction selection 1 1 DTEN DTEN 0 1 DCOUNT DCOUNT data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 STA STA status register 0x34 0x20 read-only 0x00000000 CEATAEND CE-ATA command completion signal received for CMD61 23 1 SDIOIT SDIO interrupt received 22 1 RXDAVL Data available in receive FIFO 21 1 TXDAVL Data available in transmit FIFO 20 1 RXFIFOE Receive FIFO empty 19 1 TXFIFOE Transmit FIFO empty 18 1 RXFIFOF Receive FIFO full 17 1 TXFIFOF Transmit FIFO full 16 1 RXFIFOHF Receive FIFO half full: there are at least 8 words in the FIFO 15 1 TXFIFOHE Transmit FIFO half empty: at least 8 words can be written into the FIFO 14 1 RXACT Data receive in progress 13 1 TXACT Data transmit in progress 12 1 CMDACT Command transfer in progress 11 1 DBCKEND Data block sent/received (CRC check passed) 10 1 STBITERR Start bit not detected on all data signals in wide bus mode 9 1 DATAEND Data end (data counter, SDIDCOUNT, is zero) 8 1 CMDSENT Command sent (no response required) 7 1 CMDREND Command response received (CRC check passed) 6 1 RXOVERR Received FIFO overrun error 5 1 TXUNDERR Transmit FIFO underrun error 4 1 DTIMEOUT Data timeout 3 1 CTIMEOUT Command response timeout 2 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 CCRCFAIL Command response received (CRC check failed) 0 1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 CEATAENDC CEATAEND flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 DBCKENDC DBCKEND flag clear bit 10 1 STBITERRC STBITERR flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 CCRCFAILC CCRCFAIL flag clear bit 0 1 MASK MASK mask register 0x3C 0x20 read-write 0x00000000 CEATAENDIE CE-ATA command completion signal received interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 RXDAVLIE Data available in Rx FIFO interrupt enable 21 1 TXDAVLIE Data available in Tx FIFO interrupt enable 20 1 RXFIFOEIE Rx FIFO empty interrupt enable 19 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 TXFIFOFIE Tx FIFO full interrupt enable 16 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 RXACTIE Data receive acting interrupt enable 13 1 TXACTIE Data transmit acting interrupt enable 12 1 CMDACTIE Command acting interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 STBITERRIE Start bit error interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 CCRCFAILIE Command CRC fail interrupt enable 0 1 FIFOCNT FIFOCNT FIFO counter register 0x48 0x20 read-only 0x00000000 FIFOCOUNT Remaining number of words to be written to or read from the FIFO 0 24 FIFO FIFO data FIFO register 0x80 0x20 read-write 0x00000000 FIFOData Receive and transmit FIFO data 0 32 EXTI External interrupt/event controller EXTI 0x40010400 0x0 0x400 registers PVD_PVM PVD through EXTI line detection 1 EXTI0 EXTI Line 0 interrupt 6 EXTI1 EXTI Line 1 interrupt 7 EXTI2 EXTI Line 2 interrupt 8 EXTI3 EXTI Line 3 interrupt 9 EXTI4 EXTI Line4 interrupt 10 EXTI9_5 EXTI Line5 to Line9 interrupts 23 EXTI15_10 EXTI Lines 10 to 15 interrupts 40 IMR1 IMR1 Interrupt mask register 0x0 0x20 read-write 0xFF820000 MR0 Interrupt Mask on line 0 0 1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 MR19 Interrupt Mask on line 19 19 1 MR20 Interrupt Mask on line 20 20 1 MR21 Interrupt Mask on line 21 21 1 MR22 Interrupt Mask on line 22 22 1 MR23 Interrupt Mask on line 23 23 1 MR24 Interrupt Mask on line 24 24 1 MR25 Interrupt Mask on line 25 25 1 MR26 Interrupt Mask on line 26 26 1 MR27 Interrupt Mask on line 27 27 1 MR28 Interrupt Mask on line 28 28 1 MR29 Interrupt Mask on line 29 29 1 MR30 Interrupt Mask on line 30 30 1 MR31 Interrupt Mask on line 31 31 1 EMR1 EMR1 Event mask register 0x4 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 MR19 Event Mask on line 19 19 1 MR20 Event Mask on line 20 20 1 MR21 Event Mask on line 21 21 1 MR22 Event Mask on line 22 22 1 MR23 Event Mask on line 23 23 1 MR24 Event Mask on line 24 24 1 MR25 Event Mask on line 25 25 1 MR26 Event Mask on line 26 26 1 MR27 Event Mask on line 27 27 1 MR28 Event Mask on line 28 28 1 MR29 Event Mask on line 29 29 1 MR30 Event Mask on line 30 30 1 MR31 Event Mask on line 31 31 1 RTSR1 RTSR1 Rising Trigger selection register 0x8 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR18 Rising trigger event configuration of line 18 18 1 TR19 Rising trigger event configuration of line 19 19 1 TR20 Rising trigger event configuration of line 20 20 1 TR21 Rising trigger event configuration of line 21 21 1 TR22 Rising trigger event configuration of line 22 22 1 FTSR1 FTSR1 Falling Trigger selection register 0xC 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR18 Falling trigger event configuration of line 18 18 1 TR19 Falling trigger event configuration of line 19 19 1 TR20 Falling trigger event configuration of line 20 20 1 TR21 Falling trigger event configuration of line 21 21 1 TR22 Falling trigger event configuration of line 22 22 1 SWIER1 SWIER1 Software interrupt event register 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER18 Software Interrupt on line 18 18 1 SWIER19 Software Interrupt on line 19 19 1 SWIER20 Software Interrupt on line 20 20 1 SWIER21 Software Interrupt on line 21 21 1 SWIER22 Software Interrupt on line 22 22 1 PR1 PR1 Pending register 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 PR1 Pending bit 1 1 1 PR2 Pending bit 2 2 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 PR10 Pending bit 10 10 1 PR11 Pending bit 11 11 1 PR12 Pending bit 12 12 1 PR13 Pending bit 13 13 1 PR14 Pending bit 14 14 1 PR15 Pending bit 15 15 1 PR16 Pending bit 16 16 1 PR18 Pending bit 18 18 1 PR19 Pending bit 19 19 1 PR20 Pending bit 20 20 1 PR21 Pending bit 21 21 1 PR22 Pending bit 22 22 1 IMR2 IMR2 Interrupt mask register 0x20 0x20 read-write 0xFFFFFF87 MR32 Interrupt Mask on external/internal line 32 0 1 MR33 Interrupt Mask on external/internal line 33 1 1 MR34 Interrupt Mask on external/internal line 34 2 1 MR35 Interrupt Mask on external/internal line 35 3 1 MR36 Interrupt Mask on external/internal line 36 4 1 MR37 Interrupt Mask on external/internal line 37 5 1 MR38 Interrupt Mask on external/internal line 38 6 1 MR39 Interrupt Mask on external/internal line 39 7 1 EMR2 EMR2 Event mask register 0x24 0x20 read-write 0x00000000 MR32 Event mask on external/internal line 32 0 1 MR33 Event mask on external/internal line 33 1 1 MR34 Event mask on external/internal line 34 2 1 MR35 Event mask on external/internal line 35 3 1 MR36 Event mask on external/internal line 36 4 1 MR37 Event mask on external/internal line 37 5 1 MR38 Event mask on external/internal line 38 6 1 MR39 Event mask on external/internal line 39 7 1 RTSR2 RTSR2 Rising Trigger selection register 0x28 0x20 read-write 0x00000000 RT35 Rising trigger event configuration bit of line 35 3 1 RT36 Rising trigger event configuration bit of line 36 4 1 RT37 Rising trigger event configuration bit of line 37 5 1 RT38 Rising trigger event configuration bit of line 38 6 1 FTSR2 FTSR2 Falling Trigger selection register 0x2C 0x20 read-write 0x00000000 FT35 Falling trigger event configuration bit of line 35 3 1 FT36 Falling trigger event configuration bit of line 36 4 1 FT37 Falling trigger event configuration bit of line 37 5 1 FT38 Falling trigger event configuration bit of line 38 6 1 SWIER2 SWIER2 Software interrupt event register 0x30 0x20 read-write 0x00000000 SWI35 Software interrupt on line 35 3 1 SWI36 Software interrupt on line 36 4 1 SWI37 Software interrupt on line 37 5 1 SWI38 Software interrupt on line 38 6 1 PR2 PR2 Pending register 0x34 0x20 read-write 0x00000000 PIF35 Pending interrupt flag on line 35 3 1 PIF36 Pending interrupt flag on line 36 4 1 PIF37 Pending interrupt flag on line 37 5 1 PIF38 Pending interrupt flag on line 38 6 1 VREFBUF Voltage reference buffer VREF 0x40010030 0x0 0x1D0 registers FPU Floating point interrupt 81 CSR CSR VREF control and status register 0x0 0x20 0x00000002 ENVR Voltage reference buffer enable 0 1 read-write HIZ High impedance mode 1 1 read-write VRS Voltage reference scale 2 1 read-write VRR Voltage reference buffer ready 3 1 read-only CCR CCR calibration control register 0x4 0x20 read-write 0x00000000 TRIM Trimming code 0 6 CAN1 Controller area network CAN 0x40006400 0x0 0x400 registers CAN1_TX CAN1 TX interrupts 19 CAN1_RX0 CAN1 RX0 interrupts 20 CAN1_RX1 CAN1 RX1 interrupts 21 CAN1_SCE CAN1 SCE interrupt 22 MCR MCR master control register 0x0 0x20 read-write 0x00010002 DBF DBF 16 1 RESET RESET 15 1 TTCM TTCM 7 1 ABOM ABOM 6 1 AWUM AWUM 5 1 NART NART 4 1 RFLM RFLM 3 1 TXFP TXFP 2 1 SLEEP SLEEP 1 1 INRQ INRQ 0 1 MSR MSR master status register 0x4 0x20 0x00000C02 RX RX 11 1 read-only SAMP SAMP 10 1 read-only RXM RXM 9 1 read-only TXM TXM 8 1 read-only SLAKI SLAKI 4 1 read-write WKUI WKUI 3 1 read-write ERRI ERRI 2 1 read-write SLAK SLAK 1 1 read-only INAK INAK 0 1 read-only TSR TSR transmit status register 0x8 0x20 0x1C000000 LOW2 Lowest priority flag for mailbox 2 31 1 read-only LOW1 Lowest priority flag for mailbox 1 30 1 read-only LOW0 Lowest priority flag for mailbox 0 29 1 read-only TME2 Lowest priority flag for mailbox 2 28 1 read-only TME1 Lowest priority flag for mailbox 1 27 1 read-only TME0 Lowest priority flag for mailbox 0 26 1 read-only CODE CODE 24 2 read-only ABRQ2 ABRQ2 23 1 read-write TERR2 TERR2 19 1 read-write ALST2 ALST2 18 1 read-write TXOK2 TXOK2 17 1 read-write RQCP2 RQCP2 16 1 read-write ABRQ1 ABRQ1 15 1 read-write TERR1 TERR1 11 1 read-write ALST1 ALST1 10 1 read-write TXOK1 TXOK1 9 1 read-write RQCP1 RQCP1 8 1 read-write ABRQ0 ABRQ0 7 1 read-write TERR0 TERR0 3 1 read-write ALST0 ALST0 2 1 read-write TXOK0 TXOK0 1 1 read-write RQCP0 RQCP0 0 1 read-write RF0R RF0R receive FIFO 0 register 0xC 0x20 0x00000000 RFOM0 RFOM0 5 1 read-write FOVR0 FOVR0 4 1 read-write FULL0 FULL0 3 1 read-write FMP0 FMP0 0 2 read-only RF1R RF1R receive FIFO 1 register 0x10 0x20 0x00000000 RFOM1 RFOM1 5 1 read-write FOVR1 FOVR1 4 1 read-write FULL1 FULL1 3 1 read-write FMP1 FMP1 0 2 read-only IER IER interrupt enable register 0x14 0x20 read-write 0x00000000 SLKIE SLKIE 17 1 WKUIE WKUIE 16 1 ERRIE ERRIE 15 1 LECIE LECIE 11 1 BOFIE BOFIE 10 1 EPVIE EPVIE 9 1 EWGIE EWGIE 8 1 FOVIE1 FOVIE1 6 1 FFIE1 FFIE1 5 1 FMPIE1 FMPIE1 4 1 FOVIE0 FOVIE0 3 1 FFIE0 FFIE0 2 1 FMPIE0 FMPIE0 1 1 TMEIE TMEIE 0 1 ESR ESR interrupt enable register 0x18 0x20 0x00000000 REC REC 24 8 read-only TEC TEC 16 8 read-only LEC LEC 4 3 read-write BOFF BOFF 2 1 read-only EPVF EPVF 1 1 read-only EWGF EWGF 0 1 read-only BTR BTR bit timing register 0x1C 0x20 read-write 0x00000000 SILM SILM 31 1 LBKM LBKM 30 1 SJW SJW 24 2 TS2 TS2 20 3 TS1 TS1 16 4 BRP BRP 0 10 TI0R TI0R TX mailbox identifier register 0x180 0x20 read-write 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 TXRQ TXRQ 0 1 TDT0R TDT0R mailbox data length control and time stamp register 0x184 0x20 read-write 0x00000000 TIME TIME 16 16 TGT TGT 8 1 DLC DLC 0 4 TDL0R TDL0R mailbox data low register 0x188 0x20 read-write 0x00000000 DATA3 DATA3 24 8 DATA2 DATA2 16 8 DATA1 DATA1 8 8 DATA0 DATA0 0 8 TDH0R TDH0R mailbox data high register 0x18C 0x20 read-write 0x00000000 DATA7 DATA7 24 8 DATA6 DATA6 16 8 DATA5 DATA5 8 8 DATA4 DATA4 0 8 TI1R TI1R mailbox identifier register 0x190 0x20 read-write 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 TXRQ TXRQ 0 1 TDT1R TDT1R mailbox data length control and time stamp register 0x194 0x20 read-write 0x00000000 TIME TIME 16 16 TGT TGT 8 1 DLC DLC 0 4 TDL1R TDL1R mailbox data low register 0x198 0x20 read-write 0x00000000 DATA3 DATA3 24 8 DATA2 DATA2 16 8 DATA1 DATA1 8 8 DATA0 DATA0 0 8 TDH1R TDH1R mailbox data high register 0x19C 0x20 read-write 0x00000000 DATA7 DATA7 24 8 DATA6 DATA6 16 8 DATA5 DATA5 8 8 DATA4 DATA4 0 8 TI2R TI2R mailbox identifier register 0x1A0 0x20 read-write 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 TXRQ TXRQ 0 1 TDT2R TDT2R mailbox data length control and time stamp register 0x1A4 0x20 read-write 0x00000000 TIME TIME 16 16 TGT TGT 8 1 DLC DLC 0 4 TDL2R TDL2R mailbox data low register 0x1A8 0x20 read-write 0x00000000 DATA3 DATA3 24 8 DATA2 DATA2 16 8 DATA1 DATA1 8 8 DATA0 DATA0 0 8 TDH2R TDH2R mailbox data high register 0x1AC 0x20 read-write 0x00000000 DATA7 DATA7 24 8 DATA6 DATA6 16 8 DATA5 DATA5 8 8 DATA4 DATA4 0 8 RI0R RI0R receive FIFO mailbox identifier register 0x1B0 0x20 read-only 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 RDT0R RDT0R mailbox data high register 0x1B4 0x20 read-only 0x00000000 TIME TIME 16 16 FMI FMI 8 8 DLC DLC 0 4 RDL0R RDL0R mailbox data high register 0x1B8 0x20 read-only 0x00000000 DATA3 DATA3 24 8 DATA2 DATA2 16 8 DATA1 DATA1 8 8 DATA0 DATA0 0 8 RDH0R RDH0R receive FIFO mailbox data high register 0x1BC 0x20 read-only 0x00000000 DATA7 DATA7 24 8 DATA6 DATA6 16 8 DATA5 DATA5 8 8 DATA4 DATA4 0 8 RI1R RI1R mailbox data high register 0x1C0 0x20 read-only 0x00000000 STID STID 21 11 EXID EXID 3 18 IDE IDE 2 1 RTR RTR 1 1 RDT1R RDT1R mailbox data high register 0x1C4 0x20 read-only 0x00000000 TIME TIME 16 16 FMI FMI 8 8 DLC DLC 0 4 RDL1R RDL1R mailbox data high register 0x1C8 0x20 read-only 0x00000000 DATA3 DATA3 24 8 DATA2 DATA2 16 8 DATA1 DATA1 8 8 DATA0 DATA0 0 8 RDH1R RDH1R mailbox data high register 0x1CC 0x20 read-only 0x00000000 DATA7 DATA7 24 8 DATA6 DATA6 16 8 DATA5 DATA5 8 8 DATA4 DATA4 0 8 FMR FMR filter master register 0x200 0x20 read-write 0x2A1C0E01 FINIT Filter initialization mode 0 1 FM1R FM1R filter mode register 0x204 0x20 read-write 0x00000000 FBM0 Filter mode 0 1 FBM1 Filter mode 1 1 FBM2 Filter mode 2 1 FBM3 Filter mode 3 1 FBM4 Filter mode 4 1 FBM5 Filter mode 5 1 FBM6 Filter mode 6 1 FBM7 Filter mode 7 1 FBM8 Filter mode 8 1 FBM9 Filter mode 9 1 FBM10 Filter mode 10 1 FBM11 Filter mode 11 1 FBM12 Filter mode 12 1 FBM13 Filter mode 13 1 FS1R FS1R filter scale register 0x20C 0x20 read-write 0x00000000 FSC0 Filter scale configuration 0 1 FSC1 Filter scale configuration 1 1 FSC2 Filter scale configuration 2 1 FSC3 Filter scale configuration 3 1 FSC4 Filter scale configuration 4 1 FSC5 Filter scale configuration 5 1 FSC6 Filter scale configuration 6 1 FSC7 Filter scale configuration 7 1 FSC8 Filter scale configuration 8 1 FSC9 Filter scale configuration 9 1 FSC10 Filter scale configuration 10 1 FSC11 Filter scale configuration 11 1 FSC12 Filter scale configuration 12 1 FSC13 Filter scale configuration 13 1 FFA1R FFA1R filter FIFO assignment register 0x214 0x20 read-write 0x00000000 FFA0 Filter FIFO assignment for filter 0 0 1 FFA1 Filter FIFO assignment for filter 1 1 1 FFA2 Filter FIFO assignment for filter 2 2 1 FFA3 Filter FIFO assignment for filter 3 3 1 FFA4 Filter FIFO assignment for filter 4 4 1 FFA5 Filter FIFO assignment for filter 5 5 1 FFA6 Filter FIFO assignment for filter 6 6 1 FFA7 Filter FIFO assignment for filter 7 7 1 FFA8 Filter FIFO assignment for filter 8 8 1 FFA9 Filter FIFO assignment for filter 9 9 1 FFA10 Filter FIFO assignment for filter 10 10 1 FFA11 Filter FIFO assignment for filter 11 11 1 FFA12 Filter FIFO assignment for filter 12 12 1 FFA13 Filter FIFO assignment for filter 13 13 1 FA1R FA1R filter activation register 0x21C 0x20 read-write 0x00000000 FACT0 Filter active 0 1 FACT1 Filter active 1 1 FACT2 Filter active 2 1 FACT3 Filter active 3 1 FACT4 Filter active 4 1 FACT5 Filter active 5 1 FACT6 Filter active 6 1 FACT7 Filter active 7 1 FACT8 Filter active 8 1 FACT9 Filter active 9 1 FACT10 Filter active 10 1 FACT11 Filter active 11 1 FACT12 Filter active 12 1 FACT13 Filter active 13 1 F0R1 F0R1 Filter bank 0 register 1 0x240 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F0R2 F0R2 Filter bank 0 register 2 0x244 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F1R1 F1R1 Filter bank 1 register 1 0x248 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F1R2 F1R2 Filter bank 1 register 2 0x24C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F2R1 F2R1 Filter bank 2 register 1 0x250 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F2R2 F2R2 Filter bank 2 register 2 0x254 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F3R1 F3R1 Filter bank 3 register 1 0x258 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F3R2 F3R2 Filter bank 3 register 2 0x25C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F4R1 F4R1 Filter bank 4 register 1 0x260 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F4R2 F4R2 Filter bank 4 register 2 0x264 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F5R1 F5R1 Filter bank 5 register 1 0x268 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F5R2 F5R2 Filter bank 5 register 2 0x26C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F6R1 F6R1 Filter bank 6 register 1 0x270 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F6R2 F6R2 Filter bank 6 register 2 0x274 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F7R1 F7R1 Filter bank 7 register 1 0x278 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F7R2 F7R2 Filter bank 7 register 2 0x27C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F8R1 F8R1 Filter bank 8 register 1 0x280 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F8R2 F8R2 Filter bank 8 register 2 0x284 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F9R1 F9R1 Filter bank 9 register 1 0x288 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F9R2 F9R2 Filter bank 9 register 2 0x28C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F10R1 F10R1 Filter bank 10 register 1 0x290 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F10R2 F10R2 Filter bank 10 register 2 0x294 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F11R1 F11R1 Filter bank 11 register 1 0x298 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F11R2 F11R2 Filter bank 11 register 2 0x29C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F12R1 F12R1 Filter bank 4 register 1 0x2A0 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F12R2 F12R2 Filter bank 12 register 2 0x2A4 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F13R1 F13R1 Filter bank 13 register 1 0x2A8 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F13R2 F13R2 Filter bank 13 register 2 0x2AC 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F14R1 F14R1 Filter bank 14 register 1 0x2B0 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F14R2 F14R2 Filter bank 14 register 2 0x2B4 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F15R1 F15R1 Filter bank 15 register 1 0x2B8 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F15R2 F15R2 Filter bank 15 register 2 0x2BC 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F16R1 F16R1 Filter bank 16 register 1 0x2C0 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F16R2 F16R2 Filter bank 16 register 2 0x2C4 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F17R1 F17R1 Filter bank 17 register 1 0x2C8 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F17R2 F17R2 Filter bank 17 register 2 0x2CC 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F18R1 F18R1 Filter bank 18 register 1 0x2D0 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F18R2 F18R2 Filter bank 18 register 2 0x2D4 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F19R1 F19R1 Filter bank 19 register 1 0x2D8 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F19R2 F19R2 Filter bank 19 register 2 0x2DC 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F20R1 F20R1 Filter bank 20 register 1 0x2E0 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F20R2 F20R2 Filter bank 20 register 2 0x2E4 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F21R1 F21R1 Filter bank 21 register 1 0x2E8 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F21R2 F21R2 Filter bank 21 register 2 0x2EC 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F22R1 F22R1 Filter bank 22 register 1 0x2F0 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F22R2 F22R2 Filter bank 22 register 2 0x2F4 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F23R1 F23R1 Filter bank 23 register 1 0x2F8 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F23R2 F23R2 Filter bank 23 register 2 0x2FC 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F24R1 F24R1 Filter bank 24 register 1 0x300 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F24R2 F24R2 Filter bank 24 register 2 0x304 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F25R1 F25R1 Filter bank 25 register 1 0x308 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F25R2 F25R2 Filter bank 25 register 2 0x30C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F26R1 F26R1 Filter bank 26 register 1 0x310 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F26R2 F26R2 Filter bank 26 register 2 0x314 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F27R1 F27R1 Filter bank 27 register 1 0x318 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 F27R2 F27R2 Filter bank 27 register 2 0x31C 0x20 read-write 0x00000000 FB0 Filter bits 0 1 FB1 Filter bits 1 1 FB2 Filter bits 2 1 FB3 Filter bits 3 1 FB4 Filter bits 4 1 FB5 Filter bits 5 1 FB6 Filter bits 6 1 FB7 Filter bits 7 1 FB8 Filter bits 8 1 FB9 Filter bits 9 1 FB10 Filter bits 10 1 FB11 Filter bits 11 1 FB12 Filter bits 12 1 FB13 Filter bits 13 1 FB14 Filter bits 14 1 FB15 Filter bits 15 1 FB16 Filter bits 16 1 FB17 Filter bits 17 1 FB18 Filter bits 18 1 FB19 Filter bits 19 1 FB20 Filter bits 20 1 FB21 Filter bits 21 1 FB22 Filter bits 22 1 FB23 Filter bits 23 1 FB24 Filter bits 24 1 FB25 Filter bits 25 1 FB26 Filter bits 26 1 FB27 Filter bits 27 1 FB28 Filter bits 28 1 FB29 Filter bits 29 1 FB30 Filter bits 30 1 FB31 Filter bits 31 1 RTC Real-time clock RTC 0x40002800 0x0 0x400 registers RTC_TAMP_STAMP Tamper and TimeStamp interrupts 2 RTC_WKUP RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts 3 RTC_ALARM RTC alarms through EXTI line 18 interrupts 41 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 CR CR control register 0x8 0x20 read-write 0x00000000 WCKSEL Wakeup clock selection 0 3 TSEDGE Time-stamp event active edge 3 1 REFCKON Reference clock detection enable (50 or 60 Hz) 4 1 BYPSHAD Bypass the shadow registers 5 1 FMT Hour format 6 1 ALRAE Alarm A enable 8 1 ALRBE Alarm B enable 9 1 WUTE Wakeup timer enable 10 1 TSE Time stamp enable 11 1 ALRAIE Alarm A interrupt enable 12 1 ALRBIE Alarm B interrupt enable 13 1 WUTIE Wakeup timer interrupt enable 14 1 TSIE Time-stamp interrupt enable 15 1 ADD1H Add 1 hour (summer time change) 16 1 SUB1H Subtract 1 hour (winter time change) 17 1 BKP Backup 18 1 COSEL Calibration output selection 19 1 POL Output polarity 20 1 OSEL Output selection 21 2 COE Calibration output enable 23 1 ITSE timestamp on internal event enable 24 1 ISR ISR initialization and status register 0xC 0x20 0x00000007 ALRAWF Alarm A write flag 0 1 read-only ALRBWF Alarm B write flag 1 1 read-only WUTWF Wakeup timer write flag 2 1 read-only SHPF Shift operation pending 3 1 read-write INITS Initialization status flag 4 1 read-only RSF Registers synchronization flag 5 1 read-write INITF Initialization flag 6 1 read-only INIT Initialization mode 7 1 read-write ALRAF Alarm A flag 8 1 read-write ALRBF Alarm B flag 9 1 read-write WUTF Wakeup timer flag 10 1 read-write TSF Time-stamp flag 11 1 read-write TSOVF Time-stamp overflow flag 12 1 read-write TAMP1F Tamper detection flag 13 1 read-write TAMP2F RTC_TAMP2 detection flag 14 1 read-write TAMP3F RTC_TAMP3 detection flag 15 1 read-write RECALPF Recalibration pending Flag 16 1 read-only PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 ALRMAR ALRMAR alarm A register 0x1C 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMBR ALRMBR alarm B register 0x20 0x20 read-write 0x00000000 MSK4 Alarm B date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm B hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm B minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 SSR SSR sub second register 0x28 0x20 read-only 0x00000000 SS Sub second value 0 16 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 TSTR TSTR time stamp time register 0x30 0x20 read-only 0x00000000 SU Second units in BCD format 0 4 ST Second tens in BCD format 4 3 MNU Minute units in BCD format 8 4 MNT Minute tens in BCD format 12 3 HU Hour units in BCD format 16 4 HT Hour tens in BCD format 20 2 PM AM/PM notation 22 1 TSDR TSDR time stamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 16 CALR CALR calibration register 0x3C 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW16 Use a 16-second calibration cycle period 13 1 CALM Calibration minus 0 9 TAMPCR TAMPCR tamper configuration register 0x40 0x20 read-write 0x00000000 TAMP1E Tamper 1 detection enable 0 1 TAMP1TRG Active level for tamper 1 1 1 TAMPIE Tamper interrupt enable 2 1 TAMP2E Tamper 2 detection enable 3 1 TAMP2TRG Active level for tamper 2 4 1 TAMP3E Tamper 3 detection enable 5 1 TAMP3TRG Active level for tamper 3 6 1 TAMPTS Activate timestamp on tamper detection event 7 1 TAMPFREQ Tamper sampling frequency 8 3 TAMPFLT Tamper filter count 11 2 TAMPPRCH Tamper precharge duration 13 2 TAMPPUDIS TAMPER pull-up disable 15 1 TAMP1IE Tamper 1 interrupt enable 16 1 TAMP1NOERASE Tamper 1 no erase 17 1 TAMP1MF Tamper 1 mask flag 18 1 TAMP2IE Tamper 2 interrupt enable 19 1 TAMP2NOERASE Tamper 2 no erase 20 1 TAMP2MF Tamper 2 mask flag 21 1 TAMP3IE Tamper 3 interrupt enable 22 1 TAMP3NOERASE Tamper 3 no erase 23 1 TAMP3MF Tamper 3 mask flag 24 1 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 ALRMBSSR ALRMBSSR alarm B sub second register 0x48 0x20 read-write 0x00000000 MASKSS Mask the most-significant bits starting at this bit 24 4 SS Sub seconds value 0 15 OR OR option register 0x4C 0x20 read-write 0x00000000 RTC_ALARM_TYPE RTC_ALARM on PC13 output type 0 1 RTC_OUT_RMP RTC_OUT remap 1 1 BKP0R BKP0R backup register 0x50 0x20 read-write 0x00000000 BKP BKP 0 32 BKP1R BKP1R backup register 0x54 0x20 read-write 0x00000000 BKP BKP 0 32 BKP2R BKP2R backup register 0x58 0x20 read-write 0x00000000 BKP BKP 0 32 BKP3R BKP3R backup register 0x5C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP4R BKP4R backup register 0x60 0x20 read-write 0x00000000 BKP BKP 0 32 BKP5R BKP5R backup register 0x64 0x20 read-write 0x00000000 BKP BKP 0 32 BKP6R BKP6R backup register 0x68 0x20 read-write 0x00000000 BKP BKP 0 32 BKP7R BKP7R backup register 0x6C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP8R BKP8R backup register 0x70 0x20 read-write 0x00000000 BKP BKP 0 32 BKP9R BKP9R backup register 0x74 0x20 read-write 0x00000000 BKP BKP 0 32 BKP10R BKP10R backup register 0x78 0x20 read-write 0x00000000 BKP BKP 0 32 BKP11R BKP11R backup register 0x7C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP12R BKP12R backup register 0x80 0x20 read-write 0x00000000 BKP BKP 0 32 BKP13R BKP13R backup register 0x84 0x20 read-write 0x00000000 BKP BKP 0 32 BKP14R BKP14R backup register 0x88 0x20 read-write 0x00000000 BKP BKP 0 32 BKP15R BKP15R backup register 0x8C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP16R BKP16R backup register 0x90 0x20 read-write 0x00000000 BKP BKP 0 32 BKP17R BKP17R backup register 0x94 0x20 read-write 0x00000000 BKP BKP 0 32 BKP18R BKP18R backup register 0x98 0x20 read-write 0x00000000 BKP BKP 0 32 BKP19R BKP19R backup register 0x9C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP20R BKP20R backup register 0xA0 0x20 read-write 0x00000000 BKP BKP 0 32 BKP21R BKP21R backup register 0xA4 0x20 read-write 0x00000000 BKP BKP 0 32 BKP22R BKP22R backup register 0xA8 0x20 read-write 0x00000000 BKP BKP 0 32 BKP23R BKP23R backup register 0xAC 0x20 read-write 0x00000000 BKP BKP 0 32 BKP24R BKP24R backup register 0xB0 0x20 read-write 0x00000000 BKP BKP 0 32 BKP25R BKP25R backup register 0xB4 0x20 read-write 0x00000000 BKP BKP 0 32 BKP26R BKP26R backup register 0xB8 0x20 read-write 0x00000000 BKP BKP 0 32 BKP27R BKP27R backup register 0xBC 0x20 read-write 0x00000000 BKP BKP 0 32 BKP28R BKP28R backup register 0xC0 0x20 read-write 0x00000000 BKP BKP 0 32 BKP29R BKP29R backup register 0xC4 0x20 read-write 0x00000000 BKP BKP 0 32 BKP30R BKP30R backup register 0xC8 0x20 read-write 0x00000000 BKP BKP 0 32 BKP31R BKP31R backup register 0xCC 0x20 read-write 0x00000000 BKP BKP 0 32 SWPMI1 Single Wire Protocol Master Interface SWPMI 0x40008800 0x0 0x400 registers SWPMI1 SWPMI1 global interrupt 76 CR CR SWPMI Configuration/Control register 0x0 0x20 read-write 0x00000000 RXDMA Reception DMA enable 0 1 TXDMA Transmission DMA enable 1 1 RXMODE Reception buffering mode 2 1 TXMODE Transmission buffering mode 3 1 LPBK Loopback mode enable 4 1 SWPME Single wire protocol master interface enable 5 1 DEACT Single wire protocol master interface deactivate 10 1 BRR BRR SWPMI Bitrate register 0x4 0x20 read-write 0x00000001 BR Bitrate prescaler 0 6 ISR ISR SWPMI Interrupt and Status register 0xC 0x20 read-only 0x000002C2 RXBFF Receive buffer full flag 0 1 TXBEF Transmit buffer empty flag 1 1 RXBERF Receive CRC error flag 2 1 RXOVRF Receive overrun error flag 3 1 TXUNRF Transmit underrun error flag 4 1 RXNE Receive data register not empty 5 1 TXE Transmit data register empty 6 1 TCF Transfer complete flag 7 1 SRF Slave resume flag 8 1 SUSP SUSPEND flag 9 1 DEACTF DEACTIVATED flag 10 1 ICR ICR SWPMI Interrupt Flag Clear register 0x10 0x20 write-only 0x00000000 CRXBFF Clear receive buffer full flag 0 1 CTXBEF Clear transmit buffer empty flag 1 1 CRXBERF Clear receive CRC error flag 2 1 CRXOVRF Clear receive overrun error flag 3 1 CTXUNRF Clear transmit underrun error flag 4 1 CTCF Clear transfer complete flag 7 1 CSRF Clear slave resume flag 8 1 IER IER SWPMI Interrupt Enable register 0x14 0x20 read-write 0x00000000 RXBFIE Receive buffer full interrupt enable 0 1 TXBEIE Transmit buffer empty interrupt enable 1 1 RXBERIE Receive CRC error interrupt enable 2 1 RXOVRIE Receive overrun error interrupt enable 3 1 TXUNRIE Transmit underrun error interrupt enable 4 1 RIE Receive interrupt enable 5 1 TIE Transmit interrupt enable 6 1 TCIE Transmit complete interrupt enable 7 1 SRIE Slave resume interrupt enable 8 1 RFL RFL SWPMI Receive Frame Length register 0x18 0x20 read-only 0x00000000 RFL Receive frame length 0 5 TDR TDR SWPMI Transmit data register 0x1C 0x20 write-only 0x00000000 TD Transmit data 0 32 RDR RDR SWPMI Receive data register 0x20 0x20 read-only 0x00000000 RD received data 0 32 OPAMP Operational amplifiers OPAMP 0x40007800 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x0 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 VM_SEL Inverting input selection 8 2 VP_SEL Non inverted input selection 10 1 CALON Calibration mode enabled 12 1 CALSEL Calibration selection 13 1 USERTRIM allows to switch from AOP offset trimmed values to AOP offset 14 1 CALOUT Operational amplifier calibration output 15 1 OPA_RANGE Operational amplifier power supply range for stability 31 1 OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x4 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP1_LPOTR OPAMP1_LPOTR OPAMP1 offset trimming register in low-power mode 0x8 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_CSR OPAMP2_CSR OPAMP2 control/status register 0x10 0x20 read-write 0x00000000 OPAEN Operational amplifier Enable 0 1 OPALPM Operational amplifier Low Power Mode 1 1 OPAMODE Operational amplifier PGA mode 2 2 PGA_GAIN Operational amplifier Programmable amplifier gain value 4 2 VM_SEL Inverting input selection 8 2 VP_SEL Non inverted input selection 10 1 CALON Calibration mode enabled 12 1 CALSEL Calibration selection 13 1 USERTRIM allows to switch from AOP offset trimmed values to AOP offset 14 1 CALOUT Operational amplifier calibration output 15 1 OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 0x20 read-write 0x00000000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 TRIMOFFSETP Trim for PMOS differential pairs 8 5 OPAMP2_LPOTR OPAMP2_LPOTR OPAMP2 offset trimming register in low-power mode 0x18 0x20 read-write 0x00000000 TRIMLPOFFSETN Trim for NMOS differential pairs 0 5 TRIMLPOFFSETP Trim for PMOS differential pairs 8 5 NVIC Nested Vectored Interrupt Controller NVIC 0xE000E100 0x0 0x355 registers ISER0 ISER0 Interrupt Set-Enable Register 0x0 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER1 ISER1 Interrupt Set-Enable Register 0x4 0x20 read-write 0x00000000 SETENA SETENA 0 32 ISER2 ISER2 Interrupt Set-Enable Register 0x8 0x20 read-write 0x00000000 SETENA SETENA 0 32 ICER0 ICER0 Interrupt Clear-Enable Register 0x80 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER1 ICER1 Interrupt Clear-Enable Register 0x84 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ICER2 ICER2 Interrupt Clear-Enable Register 0x88 0x20 read-write 0x00000000 CLRENA CLRENA 0 32 ISPR0 ISPR0 Interrupt Set-Pending Register 0x100 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR1 ISPR1 Interrupt Set-Pending Register 0x104 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ISPR2 ISPR2 Interrupt Set-Pending Register 0x108 0x20 read-write 0x00000000 SETPEND SETPEND 0 32 ICPR0 ICPR0 Interrupt Clear-Pending Register 0x180 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR1 ICPR1 Interrupt Clear-Pending Register 0x184 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 ICPR2 ICPR2 Interrupt Clear-Pending Register 0x188 0x20 read-write 0x00000000 CLRPEND CLRPEND 0 32 IABR0 IABR0 Interrupt Active Bit Register 0x200 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR1 IABR1 Interrupt Active Bit Register 0x204 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IABR2 IABR2 Interrupt Active Bit Register 0x208 0x20 read-only 0x00000000 ACTIVE ACTIVE 0 32 IPR0 IPR0 Interrupt Priority Register 0x300 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR1 IPR1 Interrupt Priority Register 0x304 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR2 IPR2 Interrupt Priority Register 0x308 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR3 IPR3 Interrupt Priority Register 0x30C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR4 IPR4 Interrupt Priority Register 0x310 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR5 IPR5 Interrupt Priority Register 0x314 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR6 IPR6 Interrupt Priority Register 0x318 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR7 IPR7 Interrupt Priority Register 0x31C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR8 IPR8 Interrupt Priority Register 0x320 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR9 IPR9 Interrupt Priority Register 0x324 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR10 IPR10 Interrupt Priority Register 0x328 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR11 IPR11 Interrupt Priority Register 0x32C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR12 IPR12 Interrupt Priority Register 0x330 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR13 IPR13 Interrupt Priority Register 0x334 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR14 IPR14 Interrupt Priority Register 0x338 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR15 IPR15 Interrupt Priority Register 0x33C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR16 IPR16 Interrupt Priority Register 0x340 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR17 IPR17 Interrupt Priority Register 0x344 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR18 IPR18 Interrupt Priority Register 0x348 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR19 IPR19 Interrupt Priority Register 0x34C 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 IPR20 IPR20 Interrupt Priority Register 0x350 0x20 read-write 0x00000000 IPR_N0 IPR_N0 0 8 IPR_N1 IPR_N1 8 8 IPR_N2 IPR_N2 16 8 IPR_N3 IPR_N3 24 8 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CRS CRS interrupt 82 CR CR control register 0x0 0x20 read-write 0x00002000 TRIM HSI48 oscillator smooth trimming 8 6 SWSYNC Generate software SYNC event 7 1 AUTOTRIMEN Automatic trimming enable 6 1 CEN Frequency error counter enable 5 1 ESYNCIE Expected SYNC interrupt enable 3 1 ERRIE Synchronization or trimming error interrupt enable 2 1 SYNCWARNIE SYNC warning interrupt enable 1 1 SYNCOKIE SYNC event OK interrupt enable 0 1 CFGR CFGR configuration register 0x4 0x20 read-write 0x2022BB7F SYNCPOL SYNC polarity selection 31 1 SYNCSRC SYNC signal source selection 28 2 SYNCDIV SYNC divider 24 3 FELIM Frequency error limit 16 8 RELOAD Counter reload value 0 16 ISR ISR interrupt and status register 0x8 0x20 read-only 0x00000000 FECAP Frequency error capture 16 16 FEDIR Frequency error direction 15 1 TRIMOVF Trimming overflow or underflow 10 1 SYNCMISS SYNC missed 9 1 SYNCERR SYNC error 8 1 ESYNCF Expected SYNC flag 3 1 ERRF Error flag 2 1 SYNCWARNF SYNC warning flag 1 1 SYNCOKF SYNC event OK flag 0 1 ICR ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 ESYNCC Expected SYNC clear flag 3 1 ERRC Error clear flag 2 1 SYNCWARNC SYNC warning clear flag 1 1 SYNCOKC SYNC event OK clear flag 0 1 USB_SRAM Universal serial bus full-speed device interface USB 0x40006C00 0x0 0x400 registers EP0R EP0R endpoint 0 register 0x0 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP1R EP1R endpoint 1 register 0x4 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP2R EP2R endpoint 2 register 0x8 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP3R EP3R endpoint 3 register 0xC 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP4R EP4R endpoint 4 register 0x10 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP5R EP5R endpoint 5 register 0x14 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP6R EP6R endpoint 6 register 0x18 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP7R EP7R endpoint 7 register 0x1C 0x20 read-write 0x00000000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 CNTR CNTR control register 0x40 0x20 read-write 0x00000003 FRES Force USB Reset 0 1 PDWN Power down 1 1 LPMODE Low-power mode 2 1 FSUSP Force suspend 3 1 RESUME Resume request 4 1 L1RESUME LPM L1 Resume request 5 1 L1REQM LPM L1 state request interrupt mask 7 1 ESOFM Expected start of frame interrupt mask 8 1 SOFM Start of frame interrupt mask 9 1 RESETM USB reset interrupt mask 10 1 SUSPM Suspend mode interrupt mask 11 1 WKUPM Wakeup interrupt mask 12 1 ERRM Error interrupt mask 13 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 CTRM Correct transfer interrupt mask 15 1 ISTR ISTR interrupt status register 0x44 0x20 0x00000000 EP_ID Endpoint Identifier 0 4 read-only DIR Direction of transaction 4 1 read-only L1REQ LPM L1 state request 7 1 read-write ESOF Expected start frame 8 1 read-write SOF start of frame 9 1 read-write RESET reset request 10 1 read-write SUSP Suspend mode request 11 1 read-write WKUP Wakeup 12 1 read-write ERR Error 13 1 read-write PMAOVR Packet memory area over / underrun 14 1 read-write CTR Correct transfer 15 1 read-only FNR FNR frame number register 0x48 0x20 read-only 0x0000 FN Frame number 0 11 LSOF Lost SOF 11 2 LCK Locked 13 1 RXDM Receive data - line status 14 1 RXDP Receive data + line status 15 1 DADDR DADDR device address 0x4C 0x20 read-write 0x0000 ADD Device address 0 7 EF Enable function 7 1 BTABLE BTABLE Buffer table address 0x50 0x20 read-write 0x0000 BTABLE Buffer table 3 13 LPMCSR LPMCSR LPM control and status register 0x54 0x20 0x0000 LPMEN LPM support enable 0 1 read-write LPMACK LPM Token acknowledge enable 1 1 read-write REMWAKE bRemoteWake value 3 1 read-only BESL BESL value 4 4 read-only BCDR BCDR Battery charging detector 0x58 0x20 0x0000 BCDEN Battery charging detector 0 1 read-write DCDEN Data contact detection 1 1 read-write PDEN Primary detection 2 1 read-write SDEN Secondary detection 3 1 read-write DCDET Data contact detection 4 1 read-only PDET Primary detection 5 1 read-only SDET Secondary detection 6 1 read-only PS2DET DM pull-up detection status 7 1 read-only DPPU DP pull-up control 15 1 read-write USB_FS 0x40006800 USB_FS USB event interrupt through EXTI 67 DFSDM Digital filter for sigma delta modulators DFSDM 0x40016000 0x0 0x500 registers DFSDM1_FLT3 DFSDM1_FLT3 global interrupt 42 DFSDM1 DFSDM1_FLT0 global interrupt 61 DFSDM2 DFSDM1_FLT1 global interrupt 62 DFSDM1_FLT2 DFSDM1_FLT2 global interrupt 63 I2C4_ER I2C4 error interrupt 84 CHCFG0R1 CHCFG0R1 channel configuration y register 0x0 0x20 read-write 0x0 DFSDMEN DFSDMEN 31 1 CKOUTSRC CKOUTSRC 30 1 CKOUTDIV CKOUTDIV 16 8 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG0R2 CHCFG0R2 channel configuration y register 0x4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD0R AWSCD0R analog watchdog and short-circuit detector register 0x8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT0R CHWDAT0R channel watchdog filter data register 0xC 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN0R CHDATIN0R channel data input register 0x10 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CHCFG1R1 CHCFG1R1 CHCFG1R1 0x20 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG1R2 CHCFG1R2 CHCFG1R2 0x24 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD1R AWSCD1R AWSCD1R 0x28 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT1R CHWDAT1R CHWDAT1R 0x2C 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN1R CHDATIN1R CHDATIN1R 0x30 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CHCFG2R1 CHCFG2R1 CHCFG2R1 0x40 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG2R2 CHCFG2R2 CHCFG2R2 0x44 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD2R AWSCD2R AWSCD2R 0x48 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT2R CHWDAT2R CHWDAT2R 0x4C 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN2R CHDATIN2R CHDATIN2R 0x50 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CHCFG3R1 CHCFG3R1 CHCFG3R1 0x60 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG3R2 CHCFG3R2 CHCFG3R2 0x64 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD3R AWSCD3R AWSCD3R 0x68 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT3R CHWDAT3R CHWDAT3R 0x6C 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN3R CHDATIN3R CHDATIN3R 0x70 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CHCFG4R1 CHCFG4R1 CHCFG4R1 0x80 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG4R2 CHCFG4R2 CHCFG4R2 0x84 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD4R AWSCD4R AWSCD4R 0x88 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT4R CHWDAT4R CHWDAT4R 0x8C 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN4R CHDATIN4R CHDATIN4R 0x90 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CHCFG5R1 CHCFG5R1 CHCFG5R1 0xA0 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG5R2 CHCFG5R2 CHCFG5R2 0xA4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD5R AWSCD5R AWSCD5R 0xA8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT5R CHWDAT5R CHWDAT5R 0xAC 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN5R CHDATIN5R CHDATIN5R 0xB0 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CHCFG6R1 CHCFG6R1 CHCFG6R1 0xC0 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG6R2 CHCFG6R2 CHCFG6R2 0xC4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD6R AWSCD6R AWSCD6R 0xC8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT6R CHWDAT6R CHWDAT6R 0xCC 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN6R CHDATIN6R CHDATIN6R 0xD0 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 CHCFG7R1 CHCFG7R1 CHCFG7R1 0xE0 0x20 read-write 0x0 DATPACK DATPACK 14 2 DATMPX DATMPX 12 2 CHINSEL CHINSEL 8 1 CHEN CHEN 7 1 CKABEN CKABEN 6 1 SCDEN SCDEN 5 1 SPICKSEL SPICKSEL 2 2 SITP SITP 0 2 CHCFG7R2 CHCFG7R2 CHCFG7R2 0xE4 0x20 read-write 0x0 OFFSET OFFSET 8 24 DTRBS DTRBS 3 5 AWSCD7R AWSCD7R AWSCD7R 0xE8 0x20 read-write 0x0 AWFORD AWFORD 22 2 AWFOSR AWFOSR 16 5 BKSCD BKSCD 12 4 SCDT SCDT 0 8 CHWDAT7R CHWDAT7R CHWDAT7R 0xEC 0x20 read-write 0x0 WDATA WDATA 0 16 CHDATIN7R CHDATIN7R CHDATIN7R 0xF0 0x20 read-write 0x0 INDAT1 INDAT1 16 16 INDAT0 INDAT0 0 16 DFSDM0_CR1 DFSDM0_CR1 control register 1 0x100 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 DFSDM0_CR2 DFSDM0_CR2 control register 2 0x104 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 DFSDM0_ISR DFSDM0_ISR interrupt and status register 0x108 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 DFSDM0_ICR DFSDM0_ICR interrupt flag clear register 0x10C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 DFSDM0_JCHGR DFSDM0_JCHGR injected channel group selection register 0x110 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 DFSDM0_FCR DFSDM0_FCR filter control register 0x114 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM0_JDATAR DFSDM0_JDATAR data register for injected group 0x118 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM0_RDATAR DFSDM0_RDATAR data register for the regular channel 0x11C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 DFSDM0_AWHTR DFSDM0_AWHTR analog watchdog high threshold register 0x120 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM0_AWLTR DFSDM0_AWLTR analog watchdog low threshold register 0x124 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM0_AWSR DFSDM0_AWSR analog watchdog status register 0x128 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM0_AWCFR DFSDM0_AWCFR analog watchdog clear flag register 0x12C 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM0_EXMAX DFSDM0_EXMAX Extremes detector maximum register 0x130 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM0_EXMIN DFSDM0_EXMIN Extremes detector minimum register 0x134 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM0_CNVTIMR DFSDM0_CNVTIMR conversion timer register 0x138 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM1_CR1 DFSDM1_CR1 control register 1 0x200 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 DFSDM1_CR2 DFSDM1_CR2 control register 2 0x204 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 DFSDM1_ISR DFSDM1_ISR interrupt and status register 0x208 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 DFSDM1_ICR DFSDM1_ICR interrupt flag clear register 0x20C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 DFSDM1_JCHGR DFSDM1_JCHGR injected channel group selection register 0x210 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 DFSDM1_FCR DFSDM1_FCR filter control register 0x214 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM1_JDATAR DFSDM1_JDATAR data register for injected group 0x218 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM1_RDATAR DFSDM1_RDATAR data register for the regular channel 0x21C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 DFSDM1_AWHTR DFSDM1_AWHTR analog watchdog high threshold register 0x220 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM1_AWLTR DFSDM1_AWLTR analog watchdog low threshold register 0x224 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM1_AWSR DFSDM1_AWSR analog watchdog status register 0x228 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM1_AWCFR DFSDM1_AWCFR analog watchdog clear flag register 0x22C 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM1_EXMAX DFSDM1_EXMAX Extremes detector maximum register 0x230 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM1_EXMIN DFSDM1_EXMIN Extremes detector minimum register 0x234 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM1_CNVTIMR DFSDM1_CNVTIMR conversion timer register 0x238 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM2_CR1 DFSDM2_CR1 control register 1 0x300 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 DFSDM2_CR2 DFSDM2_CR2 control register 2 0x304 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 DFSDM2_ISR DFSDM2_ISR interrupt and status register 0x308 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 DFSDM2_ICR DFSDM2_ICR interrupt flag clear register 0x30C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 DFSDM2_JCHGR DFSDM2_JCHGR injected channel group selection register 0x310 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 DFSDM2_FCR DFSDM2_FCR filter control register 0x314 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM2_JDATAR DFSDM2_JDATAR data register for injected group 0x318 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM2_RDATAR DFSDM2_RDATAR data register for the regular channel 0x31C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 DFSDM2_AWHTR DFSDM2_AWHTR analog watchdog high threshold register 0x320 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM2_AWLTR DFSDM2_AWLTR analog watchdog low threshold register 0x324 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM2_AWSR DFSDM2_AWSR analog watchdog status register 0x328 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM2_AWCFR DFSDM2_AWCFR analog watchdog clear flag register 0x32C 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM2_EXMAX DFSDM2_EXMAX Extremes detector maximum register 0x330 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM2_EXMIN DFSDM2_EXMIN Extremes detector minimum register 0x334 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM2_CNVTIMR DFSDM2_CNVTIMR conversion timer register 0x338 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 DFSDM3_CR1 DFSDM3_CR1 control register 1 0x400 0x20 read-write 0x00000000 AWFSEL Analog watchdog fast mode select 30 1 FAST Fast conversion mode selection for regular conversions 29 1 RCH Regular channel selection 24 3 RDMAEN DMA channel enabled to read data for the regular conversion 21 1 RSYNC Launch regular conversion synchronously with DFSDM0 19 1 RCONT Continuous mode selection for regular conversions 18 1 RSWSTART Software start of a conversion on the regular channel 17 1 JEXTEN Trigger enable and trigger edge selection for injected conversions 13 2 JEXTSEL Trigger signal selection for launching injected conversions 8 3 JDMAEN DMA channel enabled to read data for the injected channel group 5 1 JSCAN Scanning conversion mode for injected conversions 4 1 JSYNC Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger 3 1 JSWSTART Start a conversion of the injected group of channels 1 1 DFEN DFSDM enable 0 1 DFSDM3_CR2 DFSDM3_CR2 control register 2 0x404 0x20 read-write 0x00000000 AWDCH Analog watchdog channel selection 16 8 EXCH Extremes detector channel selection 8 8 CKABIE Clock absence interrupt enable 6 1 SCDIE Short-circuit detector interrupt enable 5 1 AWDIE Analog watchdog interrupt enable 4 1 ROVRIE Regular data overrun interrupt enable 3 1 JOVRIE Injected data overrun interrupt enable 2 1 REOCIE Regular end of conversion interrupt enable 1 1 JEOCIE Injected end of conversion interrupt enable 0 1 DFSDM3_ISR DFSDM3_ISR interrupt and status register 0x408 0x20 read-only 0x00FF0000 SCDF short-circuit detector flag 24 8 CKABF Clock absence flag 16 8 RCIP Regular conversion in progress status 14 1 JCIP Injected conversion in progress status 13 1 AWDF Analog watchdog 4 1 ROVRF Regular conversion overrun flag 3 1 JOVRF Injected conversion overrun flag 2 1 REOCF End of regular conversion flag 1 1 JEOCF End of injected conversion flag 0 1 DFSDM3_ICR DFSDM3_ICR interrupt flag clear register 0x40C 0x20 read-write 0x00000000 CLRSCDF Clear the short-circuit detector flag 24 8 CLRCKABF Clear the clock absence flag 16 8 CLRROVRF Clear the regular conversion overrun flag 3 1 CLRJOVRF Clear the injected conversion overrun flag 2 1 DFSDM3_JCHGR DFSDM3_JCHGR injected channel group selection register 0x410 0x20 read-write 0x00000001 JCHG Injected channel group selection 0 8 DFSDM3_FCR DFSDM3_FCR filter control register 0x414 0x20 read-write 0x00000000 FORD Sinc filter order 29 3 FOSR Sinc filter oversampling ratio (decimation rate) 16 10 IOSR Integrator oversampling ratio (averaging length) 0 8 DFSDM3_JDATAR DFSDM3_JDATAR data register for injected group 0x418 0x20 read-only 0x00000000 JDATA Injected group conversion data 8 24 JDATACH Injected channel most recently converted 0 3 DFSDM3_RDATAR DFSDM3_RDATAR data register for the regular channel 0x41C 0x20 read-only 0x00000000 RDATA Regular channel conversion data 8 24 RPEND Regular channel pending data 4 1 RDATACH Regular channel most recently converted 0 3 DFSDM3_AWHTR DFSDM3_AWHTR analog watchdog high threshold register 0x420 0x20 read-write 0x00000000 AWHT Analog watchdog high threshold 8 24 BKAWH Break signal assignment to analog watchdog high threshold event 0 4 DFSDM3_AWLTR DFSDM3_AWLTR analog watchdog low threshold register 0x424 0x20 read-write 0x00000000 AWLT Analog watchdog low threshold 8 24 BKAWL Break signal assignment to analog watchdog low threshold event 0 4 DFSDM3_AWSR DFSDM3_AWSR analog watchdog status register 0x428 0x20 read-only 0x00000000 AWHTF Analog watchdog high threshold flag 8 8 AWLTF Analog watchdog low threshold flag 0 8 DFSDM3_AWCFR DFSDM3_AWCFR analog watchdog clear flag register 0x42C 0x20 read-write 0x00000000 CLRAWHTF Clear the analog watchdog high threshold flag 8 8 CLRAWLTF Clear the analog watchdog low threshold flag 0 8 DFSDM3_EXMAX DFSDM3_EXMAX Extremes detector maximum register 0x430 0x20 read-only 0x80000000 EXMAX Extremes detector maximum value 8 24 EXMAXCH Extremes detector maximum data channel 0 3 DFSDM3_EXMIN DFSDM3_EXMIN Extremes detector minimum register 0x434 0x20 read-only 0x7FFFFF00 EXMIN EXMIN 8 24 EXMINCH Extremes detector minimum data channel 0 3 DFSDM3_CNVTIMR DFSDM3_CNVTIMR conversion timer register 0x438 0x20 read-only 0x00000000 CNVCNT 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN 4 28 QUADSPI QuadSPI interface QUADSPI 0xA0001000 0x0 0x400 registers QUADSPI Quad SPI global interrupt 71 CR CR control register 0x0 0x20 read-write 0x00000000 PRESCALER Clock prescaler 24 8 PMM Polling match mode 23 1 APMS Automatic poll mode stop 22 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 TEIE Transfer error interrupt enable 16 1 FTHRES IFO threshold level 8 5 FSEL FLASH memory selection 7 1 DFM Dual-flash mode 6 1 SSHIFT Sample shift 4 1 TCEN Timeout counter enable 3 1 DMAEN DMA enable 2 1 ABORT Abort request 1 1 EN Enable 0 1 DCR DCR device configuration register 0x4 0x20 read-write 0x00000000 FSIZE FLASH memory size 16 5 CSHT Chip select high time 8 3 CKMODE Mode 0 / mode 3 0 1 SR SR status register 0x8 0x20 read-only 0x00000000 FLEVEL FIFO level 8 7 BUSY Busy 5 1 TOF Timeout flag 4 1 SMF Status match flag 3 1 FTF FIFO threshold flag 2 1 TCF Transfer complete flag 1 1 TEF Transfer error flag 0 1 FCR FCR flag clear register 0xC 0x20 read-write 0x00000000 CTOF Clear timeout flag 4 1 CSMF Clear status match flag 3 1 CTCF Clear transfer complete flag 1 1 CTEF Clear transfer error flag 0 1 DLR DLR data length register 0x10 0x20 read-write 0x00000000 DL Data length 0 32 CCR CCR communication configuration register 0x14 0x20 read-write 0x00000000 DDRM Double data rate mode 31 1 DHHC DDR hold half cycle 30 1 SIOO Send instruction only once mode 28 1 FMODE Functional mode 26 2 DMODE Data mode 24 2 DCYC Number of dummy cycles 18 5 ABSIZE Alternate bytes size 16 2 ABMODE Alternate bytes mode 14 2 ADSIZE Address size 12 2 ADMODE Address mode 10 2 IMODE Instruction mode 8 2 INSTRUCTION Instruction 0 8 AR AR address register 0x18 0x20 read-write 0x00000000 ADDRESS Address 0 32 ABR ABR ABR 0x1C 0x20 read-write 0x00000000 ALTERNATE ALTERNATE 0 32 DR DR data register 0x20 0x20 read-write 0x00000000 DATA Data 0 32 PSMKR PSMKR polling status mask register 0x24 0x20 read-write 0x00000000 MASK Status mask 0 32 PSMAR PSMAR polling status match register 0x28 0x20 read-write 0x00000000 MATCH Status match 0 32 PIR PIR polling interval register 0x2C 0x20 read-write 0x00000000 INTERVAL Polling interval 0 16 LPTR LPTR low-power timeout register 0x30 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 DBGMCU MCU debug component DBGMCU 0xE0042000 0x0 0x15 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x00000000 DEV_ID Device identifier 0 12 REV_ID Revision identifie 16 16 CR CR Debug MCU configuration register 0x4 0x20 read-write 0x00000000 DBG_SLEEP Debug Sleep mode 0 1 DBG_STOP Debug Stop mode 1 1 DBG_STANDBY Debug Standby mode 2 1 TRACE_IOEN Trace pin assignment control 5 1 TRACE_MODE Trace pin assignment control 6 2 APB1FZR1 APB1FZR1 Debug MCU APB1 freeze register1 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP TIM2 counter stopped when core is halted 0 1 DBG_TIM6_STOP TIM6 counter stopped when core is halted 4 1 DBG_TIM7_STOP TIM7 counter stopped when core is halted 5 1 DBG_RTC_STOP RTC counter stopped when core is halted 10 1 DBG_WWDG_STOP Window watchdog counter stopped when core is halted 11 1 DBG_IWDG_STOP Independent watchdog counter stopped when core is halted 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout counter stopped when core is halted 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout counter stopped when core is halted 22 1 DBG_I2C3_STOP I2C3 SMBUS timeout counter stopped when core is halted 23 1 DBG_CAN_STOP bxCAN stopped when core is halted 25 1 DBG_LPTIM1_STOP LPTIM1 counter stopped when core is halted 31 1 APB1FZR2 APB1FZR2 Debug MCU APB1 freeze register 2 0xC 0x20 read-write 0x00000000 DBG_LPTIM2_STOP LPTIM2 counter stopped when core is halted 5 1 APB2FZR APB2FZR Debug MCU APB2 freeze register 0x10 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 FPU Floting point unit FPU 0xE000EF34 0x0 0xD registers FPU Floating point unit interrupt 81 FPU Floating point interrupt 81 FPCCR FPCCR Floating-point context control register 0x0 0x20 read-write 0x00000000 LSPACT LSPACT 0 1 USER USER 1 1 THREAD THREAD 3 1 HFRDY HFRDY 4 1 MMRDY MMRDY 5 1 BFRDY BFRDY 6 1 MONRDY MONRDY 8 1 LSPEN LSPEN 30 1 ASPEN ASPEN 31 1 FPCAR FPCAR Floating-point context address register 0x4 0x20 read-write 0x00000000 ADDRESS Location of unpopulated floating-point 3 29 FPSCR FPSCR Floating-point status control register 0x8 0x20 read-write 0x00000000 IOC Invalid operation cumulative exception bit 0 1 DZC Division by zero cumulative exception bit. 1 1 OFC Overflow cumulative exception bit 2 1 UFC Underflow cumulative exception bit 3 1 IXC Inexact cumulative exception bit 4 1 IDC Input denormal cumulative exception bit. 7 1 RMode Rounding Mode control field 22 2 FZ Flush-to-zero mode control bit: 24 1 DN Default NaN mode control bit 25 1 AHP Alternative half-precision control bit 26 1 V Overflow condition code flag 28 1 C Carry condition code flag 29 1 Z Zero condition code flag 30 1 N Negative condition code flag 31 1 MPU Memory protection unit MPU 0xE000ED90 0x0 0x15 registers MPU_TYPER MPU_TYPER MPU type register 0x0 0x20 read-only 0X00000800 SEPARATE Separate flag 0 1 DREGION Number of MPU data regions 8 8 IREGION Number of MPU instruction regions 16 8 MPU_CTRL MPU_CTRL MPU control register 0x4 0x20 read-only 0X00000000 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault 1 1 PRIVDEFENA Enable priviliged software access to default memory map 2 1 MPU_RNR MPU_RNR MPU region number register 0x8 0x20 read-write 0X00000000 REGION MPU region 0 8 MPU_RBAR MPU_RBAR MPU region base address register 0xC 0x20 read-write 0X00000000 REGION MPU region field 0 4 VALID MPU region number valid 4 1 ADDR Region base address field 5 27 MPU_RASR MPU_RASR MPU region attribute and size register 0x10 0x20 read-write 0X00000000 ENABLE Region enable bit. 0 1 SIZE Size of the MPU protection region 1 5 SRD Subregion disable bits 8 8 B memory attribute 16 1 C memory attribute 17 1 S Shareable memory attribute 18 1 TEX memory attribute 19 3 AP Access permission 24 3 XN Instruction access disable bit 28 1 STK SysTick timer STK 0xE000E010 0x0 0x11 registers CTRL CTRL SysTick control and status register 0x0 0x20 read-write 0X00000000 ENABLE Counter enable 0 1 TICKINT SysTick exception request enable 1 1 CLKSOURCE Clock source selection 2 1 COUNTFLAG COUNTFLAG 16 1 LOAD LOAD SysTick reload value register 0x4 0x20 read-write 0X00000000 RELOAD RELOAD value 0 24 VAL VAL SysTick current value register 0x8 0x20 read-write 0X00000000 CURRENT Current counter value 0 24 CALIB CALIB SysTick calibration value register 0xC 0x20 read-write 0X00000000 TENMS Calibration value 0 24 SKEW SKEW flag: Indicates whether the TENMS value is exact 30 1 NOREF NOREF flag. Reads as zero 31 1 SCB System control block SCB 0xE000ED00 0x0 0x41 registers CPUID CPUID CPUID base register 0x0 0x20 read-only 0x410FC241 Revision Revision number 0 4 PartNo Part number of the processor 4 12 Constant Reads as 0xF 16 4 Variant Variant number 20 4 Implementer Implementer code 24 8 ICSR ICSR Interrupt control and state register 0x4 0x20 read-write 0x00000000 VECTACTIVE Active vector 0 9 RETTOBASE Return to base level 11 1 VECTPENDING Pending vector 12 7 ISRPENDING Interrupt pending flag 22 1 PENDSTCLR SysTick exception clear-pending bit 25 1 PENDSTSET SysTick exception set-pending bit 26 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVSET PendSV set-pending bit 28 1 NMIPENDSET NMI set-pending bit. 31 1 VTOR VTOR Vector table offset register 0x8 0x20 read-write 0x00000000 TBLOFF Vector table base offset field 9 21 AIRCR AIRCR Application interrupt and reset control register 0xC 0x20 read-write 0x00000000 VECTRESET VECTRESET 0 1 VECTCLRACTIVE VECTCLRACTIVE 1 1 SYSRESETREQ SYSRESETREQ 2 1 PRIGROUP PRIGROUP 8 3 ENDIANESS ENDIANESS 15 1 VECTKEYSTAT Register key 16 16 SCR SCR System control register 0x10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 SEVEONPEND Send Event on Pending bit 4 1 CCR CCR Configuration and control register 0x14 0x20 read-write 0x00000000 NONBASETHRDENA Configures how the processor enters Thread mode 0 1 USERSETMPEND USERSETMPEND 1 1 UNALIGN__TRP UNALIGN_ TRP 3 1 DIV_0_TRP DIV_0_TRP 4 1 BFHFNMIGN BFHFNMIGN 8 1 STKALIGN STKALIGN 9 1 SHPR1 SHPR1 System handler priority registers 0x18 0x20 read-write 0x00000000 PRI_4 Priority of system handler 4 0 8 PRI_5 Priority of system handler 5 8 8 PRI_6 Priority of system handler 6 16 8 SHPR2 SHPR2 System handler priority registers 0x1C 0x20 read-write 0x00000000 PRI_11 Priority of system handler 11 24 8 SHPR3 SHPR3 System handler priority registers 0x20 0x20 read-write 0x00000000 PRI_14 Priority of system handler 14 16 8 PRI_15 Priority of system handler 15 24 8 SHCRS SHCRS System handler control and state register 0x24 0x20 read-write 0x00000000 MEMFAULTACT Memory management fault exception active bit 0 1 BUSFAULTACT Bus fault exception active bit 1 1 USGFAULTACT Usage fault exception active bit 3 1 SVCALLACT SVC call active bit 7 1 MONITORACT Debug monitor active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTPENDED Usage fault exception pending bit 12 1 MEMFAULTPENDED Memory management fault exception pending bit 13 1 BUSFAULTPENDED Bus fault exception pending bit 14 1 SVCALLPENDED SVC call pending bit 15 1 MEMFAULTENA Memory management fault enable bit 16 1 BUSFAULTENA Bus fault enable bit 17 1 USGFAULTENA Usage fault enable bit 18 1 CFSR_UFSR_BFSR_MMFSR CFSR_UFSR_BFSR_MMFSR Configurable fault status register 0x28 0x20 read-write 0x00000000 IACCVIOL Instruction access violation flag 1 1 MUNSTKERR Memory manager fault on unstacking for a return from exception 3 1 MSTKERR Memory manager fault on stacking for exception entry. 4 1 MLSPERR MLSPERR 5 1 MMARVALID Memory Management Fault Address Register (MMAR) valid flag 7 1 IBUSERR Instruction bus error 8 1 PRECISERR Precise data bus error 9 1 IMPRECISERR Imprecise data bus error 10 1 UNSTKERR Bus fault on unstacking for a return from exception 11 1 STKERR Bus fault on stacking for exception entry 12 1 LSPERR Bus fault on floating-point lazy state preservation 13 1 BFARVALID Bus Fault Address Register (BFAR) valid flag 15 1 UNDEFINSTR Undefined instruction usage fault 16 1 INVSTATE Invalid state usage fault 17 1 INVPC Invalid PC load usage fault 18 1 NOCP No coprocessor usage fault. 19 1 UNALIGNED Unaligned access usage fault 24 1 DIVBYZERO Divide by zero usage fault 25 1 HFSR HFSR Hard fault status register 0x2C 0x20 read-write 0x00000000 VECTTBL Vector table hard fault 1 1 FORCED Forced hard fault 30 1 DEBUG_VT Reserved for Debug use 31 1 MMFAR MMFAR Memory management fault address register 0x34 0x20 read-write 0x00000000 MMFAR Memory management fault address 0 32 BFAR BFAR Bus fault address register 0x38 0x20 read-write 0x00000000 BFAR Bus fault address 0 32 AFSR AFSR Auxiliary fault status register 0x3C 0x20 read-write 0x00000000 IMPDEF Implementation defined 0 32 NVIC_STIR Nested vectored interrupt controller NVIC 0xE000EF00 0x0 0x5 registers STIR STIR Software trigger interrupt register 0x0 0x20 read-write 0x00000000 INTID Software generated interrupt ID 0 9 FPU_CPACR Floating point unit CPACR FPU 0xE000ED88 0x0 0x5 registers CPACR CPACR Coprocessor access control register 0x0 0x20 read-write 0x0000000 CP CP 20 4 SCB_ACTRL System control block ACTLR SCB 0xE000E008 0x0 0x5 registers ACTRL ACTRL Auxiliary control register 0x0 0x20 read-write 0x00000000 DISMCYCINT DISMCYCINT 0 1 DISDEFWBUF DISDEFWBUF 1 1 DISFOLD DISFOLD 2 1 DISFPCA DISFPCA 8 1 DISOOFP DISOOFP 9 1