[package]
name = "extract_rust_hdl_interface"
version = "0.2.0"
edition = "2021"
license = "MIT"
keywords = ["rust-hdl", "verilog", "fpga"]
authors = ["zebreus <lennarteichhorn@googlemail.com>"]
categories = ["development-tools::build-utils"]
repository = "https://github.com/zebreus/bachelor-thesis"
homepage = "https://github.com/zebreus/bachelor-thesis/tree/master/bambu-macro/extract_rust_hdl_interface"
description = "Extracts the information needed for a rust-hdl module from a verilog module"

[dependencies]
itertools = "0.10.5"
sv-parser = "0.13.1"