/dts-v1/;

/ {
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	compatible = "sifive,hifive-unleashed-a00";
	model = "SiFive HiFive Unleashed A00";

	chosen {
		bootargs = [00];
		stdout-path = "/soc/serial@10010000";
	};

	aliases {
		serial0 = "/soc/serial@10010000";
		ethernet0 = "/soc/ethernet@10090000";
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <0x0a 0x0a 0x01>;
	};

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		timebase-frequency = <0x989680>;

		cpu@0 {
			device_type = "cpu";
			reg = <0x00>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imacu";

			interrupt-controller {
				#interrupt-cells = <0x01>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x07>;
			};
		};

		cpu@1 {
			device_type = "cpu";
			reg = <0x01>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafdcsu";
			mmu-type = "riscv,sv48";

			interrupt-controller {
				#interrupt-cells = <0x01>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x06>;
			};
		};

		cpu@2 {
			device_type = "cpu";
			reg = <0x02>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafdcsu";
			mmu-type = "riscv,sv48";

			interrupt-controller {
				#interrupt-cells = <0x01>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x05>;
			};
		};

		cpu@3 {
			device_type = "cpu";
			reg = <0x03>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafdcsu";
			mmu-type = "riscv,sv48";

			interrupt-controller {
				#interrupt-cells = <0x01>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x04>;
			};
		};

		cpu@4 {
			device_type = "cpu";
			reg = <0x04>;
			status = "okay";
			compatible = "riscv";
			riscv,isa = "rv64imafdcsu";
			mmu-type = "riscv,sv48";

			interrupt-controller {
				#interrupt-cells = <0x01>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
				phandle = <0x03>;
			};
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00 0x80000000 0x00 0x20000000>;
	};

	rtcclk {
		#clock-cells = <0x00>;
		compatible = "fixed-clock";
		clock-frequency = <0xf4240>;
		clock-output-names = "rtcclk";
		phandle = <0x02>;
	};

	hfclk {
		#clock-cells = <0x00>;
		compatible = "fixed-clock";
		clock-frequency = <0x1fca055>;
		clock-output-names = "hfclk";
		phandle = <0x01>;
	};

	soc {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		compatible = "simple-bus";
		ranges;

		serial@10010000 {
			interrupts = <0x04>;
			interrupt-parent = <0x09>;
			clocks = <0x08 0x03>;
			reg = <0x00 0x10010000 0x00 0x1000>;
			compatible = "sifive,uart0";
		};

		ethernet@10090000 {
			#size-cells = <0x00>;
			#address-cells = <0x01>;
			local-mac-address = [52 54 00 12 34 56];
			clock-names = "pclk\0hclk";
			clocks = <0x08 0x02 0x08 0x02>;
			interrupts = <0x35>;
			interrupt-parent = <0x09>;
			phy-handle = <0x0b>;
			phy-mode = "gmii";
			reg-names = "control";
			reg = <0x00 0x10090000 0x00 0x2000 0x00 0x100a0000 0x00 0x1000>;
			compatible = "sifive,fu540-c000-gem";

			ethernet-phy@0 {
				reg = <0x00>;
				phandle = <0x0b>;
			};
		};

		gpio@10060000 {
			compatible = "sifive,gpio0";
			interrupt-parent = <0x09>;
			interrupts = <0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16>;
			reg = <0x00 0x10060000 0x00 0x1000>;
			gpio-controller;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			clocks = <0x08 0x03>;
			phandle = <0x0a>;
		};

		interrupt-controller@c000000 {
			phandle = <0x09>;
			riscv,ndev = <0x35>;
			reg = <0x00 0xc000000 0x00 0x4000000>;
			interrupts-extended = <0x07 0x0b 0x06 0x0b 0x06 0x09 0x05 0x0b 0x05 0x09 0x04 0x0b 0x04 0x09 0x03 0x0b 0x03 0x09>;
			interrupt-controller;
			compatible = "riscv,plic0";
			#interrupt-cells = <0x01>;
		};

		clock-controller@10000000 {
			compatible = "sifive,fu540-c000-prci";
			reg = <0x00 0x10000000 0x00 0x1000>;
			clocks = <0x01 0x02>;
			#clock-cells = <0x01>;
			phandle = <0x08>;
		};

		otp@10070000 {
			compatible = "sifive,fu540-c000-otp";
			reg = <0x00 0x10070000 0x00 0x1000>;
			fuse-count = <0x1000>;
		};

		clint@2000000 {
			interrupts-extended = <0x07 0x03 0x07 0x07 0x06 0x03 0x06 0x07 0x05 0x03 0x05 0x07 0x04 0x03 0x04 0x07 0x03 0x03 0x03 0x07>;
			reg = <0x00 0x2000000 0x00 0x10000>;
			compatible = "riscv,clint0";
		};
	};
};