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\n The event inter-arrival rate defines how fast this MoC source gets replenished in the light of\n tagged-signal model, or the discrete-event model, equivalently.\n The faster the rate, the faster the data present in this boundary signal is \"fresh\".\n This notion can differ along different MoCs.\n For example, in the Synchronous MoC, this means that a new data is available in the signal (SYSignal
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\n see eventProductionRateNumerator
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\n A map of port connections.\n
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\n\n\n For example, there could be a \"ANSI-C\" implementation and a \"CUDA\" implementation\n so that the requirements can be expressed\n as an associative array with these two possibilties as follow.\n
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\n A map of memory requirements for different implementations of this instrumented behavior for different instruction categories.\n These are memory requirements.\n When a number of a certain operation is \"x\" larger, it means semantically that a host storage element\n must give \"x\" more space to this behaviour so that it can be stored.\n the memory of a behaviour semantically include both its \"execution size\" (instruction size in languages like C)\n and \"internal state\" (internal variables in languages like C).\n
\n\n\n For example, there could be a \"RISCV\" implementation, a \"niosII\" implementation and a\n \"FPGA logic area implementation\" so that the computational requirements can be expressed\n as an associative array with these three possibilities as follow.\n
\n\n\n maxSizeInBits: {\n \"RISCV\": 1000L,\n \"niosII\": 500L,\n \"FPGA logic area implementation\": 200L\n }\n\n In this case, the FPGA implementation tries to capture the logic area consumed by the synthesized behaviour.\n\n","initializationCode":{},"defaultValue":null,"propertyType":{"category":"MapPropertyType","keyType":{"category":"StringPropertyType","keyType":null,"valueType":null},"valueType":{"category":"IntegerPropertyType","bits":64,"unsigned":false,"keyType":null,"valueType":null}}}},"javaCanonicalName":"forsyde.io.lib.hierarchy.implementation.functional.InstrumentedBehaviour","simpleName":"InstrumentedBehaviour"},"forsyde::io::lib::hierarchy::platform::runtime::SuperLoopRuntime":{"canonicalName":"forsyde::io::lib::hierarchy::platform::runtime::SuperLoopRuntime","htmlDescription":" A super loop runtime captures the entry-point for programmable devices that have no runtime at all, i.e. almost or completely bare-metal.\n These runtimes will generally represent \"superloop\" approaches, where the processes being scheduled are inside\n a big while loop that runs forever, executing the processes unconditionally.\n This does not exclude the fact that a process might stall its processing element while waiting for data or any\n other activation condition.\n","refinedTraits":["forsyde::io::lib::hierarchy::platform::runtime::AbstractRuntime"],"requiredPorts":{},"requiredProperties":{"superLoopEntries":{"name":"superLoopEntries","htmlDescription":null,"initializationCode":{"java":"if (!getViewedVertex().hasProperty(\"superLoopEntries\")) getViewedVertex().putProperty(\"superLoopEntries\", forsyde.io.lib.hierarchy.platform.runtime.SuperLoopRuntime.super.superLoopEntries())"},"defaultValue":null,"propertyType":{"category":"ArrayPropertyType","valueType":{"category":"StringPropertyType","keyType":null,"valueType":null},"keyType":null}}},"javaCanonicalName":"forsyde.io.lib.hierarchy.platform.runtime.SuperLoopRuntime","simpleName":"SuperLoopRuntime"},"forsyde::io::lib::hierarchy::behavior::execution::Stimulatable":{"canonicalName":"forsyde::io::lib::hierarchy::behavior::execution::Stimulatable","htmlDescription":null,"refinedTraits":[],"requiredPorts":{"activators":{"name":"activators","htmlDescription":null,"vertexTrait":"forsyde::io::lib::hierarchy::behavior::execution::Stimulator","edgeTrait":"forsyde::io::lib::hierarchy::behavior::execution::EventEdge","multiple":true,"optional":false,"outgoing":false,"incoming":true}},"requiredProperties":{"hasORSemantics":{"name":"hasORSemantics","htmlDescription":null,"initializationCode":{"java":"if (!getViewedVertex().hasProperty(\"hasORSemantics\")) getViewedVertex().putProperty(\"hasORSemantics\", forsyde.io.lib.hierarchy.behavior.execution.Stimulatable.super.hasORSemantics())"},"defaultValue":null,"propertyType":{"category":"BooleanPropertyType","keyType":null,"valueType":null}}},"javaCanonicalName":"forsyde.io.lib.hierarchy.behavior.execution.Stimulatable","simpleName":"Stimulatable"},"forsyde::io::lib::hierarchy::platform::hardware::Structure":{"canonicalName":"forsyde::io::lib::hierarchy::platform::hardware::Structure","htmlDescription":" A structure is simply a collection of platform elements without\n any specific meaning. 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\n A MoC in this hierarchy is understood as in the paper:\n
\n\n Lee, E.A., Sangiovanni-Vincentelli, A., 1998. A framework for comparing models of computation.\n IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, 1217–1229.\n DOI\n
\n\n This trait does not enforce anything on its own, but serves as a \"categorical\"\n trait which can be used to susbet any MoCs present in a system graph.\n To get more information on a vertex and its MoC-like behaviour, one should\n directly query for specific MoCs, e.g. SYProcess or SDFActor.\n
\n","refinedTraits":[],"requiredPorts":{},"requiredProperties":{},"javaCanonicalName":"forsyde.io.lib.hierarchy.behavior.moc.MoCEntity","simpleName":"MoCEntity"},"forsyde::io::lib::hierarchy::behavior::data::RealLike":{"canonicalName":"forsyde::io::lib::hierarchy::behavior::data::RealLike","htmlDescription":" This trait captures a real-like datum.\n By real-like, it means that it represents a real number, but the actual encoding is left open to\n be present in refinements of this trait.\n In other words, _do not assume_ that this trait implies that the vertex being viewed is a IEEE 754 floating point.\n Rather, look what refinements exist for this trait or create another to properly capture the desired real number\n encoding.\n\n The only property enforced in this trait is the total number of bits, which is universal across any real number\n encoding.\n","refinedTraits":["forsyde::io::lib::hierarchy::behavior::DataTypeLike"],"requiredPorts":{},"requiredProperties":{"numberOfBits":{"name":"numberOfBits","htmlDescription":" The _total_ number of bits encoded in this representation.\n If a particular encoding separates bits in different categories, include all the categories.\n Using 32-bit IEEE 754 as an example, this number is 32, despite the sign bit, the 8 exponent and 23 fraction bits.\n","initializationCode":{},"defaultValue":null,"propertyType":{"category":"IntegerPropertyType","bits":32,"unsigned":false,"keyType":null,"valueType":null}}},"javaCanonicalName":"forsyde.io.lib.hierarchy.behavior.data.RealLike","simpleName":"RealLike"},"forsyde::io::lib::hierarchy::decision::AnalyzedBehavior":{"canonicalName":"forsyde::io::lib::hierarchy::decision::AnalyzedBehavior","htmlDescription":" This trait attaches analysis and optimisation data to a behavior entity.\n It contains information like the behaviour's throughput.\n","refinedTraits":["forsyde::io::lib::hierarchy::behavior::BehaviourEntity"],"requiredPorts":{},"requiredProperties":{"throughputInSecsNumerator":{"name":"throughputInSecsNumerator","htmlDescription":null,"initializationCode":{"java":"if (!getViewedVertex().hasProperty(\"throughputInSecsNumerator\")) getViewedVertex().putProperty(\"throughputInSecsNumerator\", forsyde.io.lib.hierarchy.decision.AnalyzedBehavior.super.throughputInSecsNumerator())"},"defaultValue":null,"propertyType":{"category":"IntegerPropertyType","bits":64,"unsigned":false,"keyType":null,"valueType":null}},"throughputInSecsDenominator":{"name":"throughputInSecsDenominator","htmlDescription":null,"initializationCode":{"java":"if (!getViewedVertex().hasProperty(\"throughputInSecsDenominator\")) getViewedVertex().putProperty(\"throughputInSecsDenominator\", forsyde.io.lib.hierarchy.decision.AnalyzedBehavior.super.throughputInSecsDenominator())"},"defaultValue":null,"propertyType":{"category":"IntegerPropertyType","bits":64,"unsigned":false,"keyType":null,"valueType":null}}},"javaCanonicalName":"forsyde.io.lib.hierarchy.decision.AnalyzedBehavior","simpleName":"AnalyzedBehavior"},"forsyde::io::lib::hierarchy::behavior::moc::MoCSink":{"canonicalName":"forsyde::io::lib::hierarchy::behavior::moc::MoCSink","htmlDescription":" A boundary signal between a MoC process network and anything outside this network.\n\n\n All MoCs can use this sink trait since all MoCs can be compared in the light of a discrete-event model,\n or, the tagged-signal model (see the reference of MoCEntity
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\n see eventConsumptionRateNumerator
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\n If this processing element exhibits higher level of parallelism (see `GenericProcessingModule`), then the provisions\n should always be provided _per parallel \"thread\"_.\n For example, if the processing element is a typical dual-core, the model instructions per cycle property\n should be as the intructions per cycle _per core_, not their summed total.\n","refinedTraits":["forsyde::io::lib::hierarchy::platform::hardware::GenericProcessingModule"],"requiredPorts":{},"requiredProperties":{"modalInstructionCategory":{"name":"modalInstructionCategory","htmlDescription":"
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\n\n\n For example, there could be a \"RISCV\" instruction category and a \"niosII\" instruction category\n as a set as follows.\n
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\n Where the real numbers describe the amount of the requirements (provisions) is provided per clock cycle.\n So, if you want the amount of requirements (provisions) this processing element is giving per second, you\n simply do:\n
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