import "primitives/std.lib";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    const0 = std_const(32, 4);
    const1 = std_const(32, 5);
    add = std_add(32);
    mult = std_mult_pipe(32);
    reg0 = std_reg(32);
    reg1 = std_reg(32);
    @generated fsm = std_reg(2);
  }
  wires {
    done = fsm.out == 2'd2 ? 1'd1;
    add.left = !reg0.done & fsm.out == 2'd0 & go ? const0.out;
    add.right = !reg0.done & fsm.out == 2'd0 & go ? const1.out;
    fsm.clk = clk;
    fsm.in = fsm.out == 2'd2 ? 2'd0;
    fsm.in = fsm.out == 2'd0 & reg0.done & go ? 2'd1;
    fsm.in = fsm.out == 2'd1 & reg1.done & go ? 2'd2;
    fsm.reset = reset;
    fsm.write_en = fsm.out == 2'd0 & reg0.done & go | fsm.out == 2'd1 & reg1.done & go | fsm.out == 2'd2 ? 1'd1;
    mult.clk = clk;
    mult.go = !mult.done & !reg1.done & fsm.out == 2'd1 & go ? 1'd1;
    mult.left = !reg1.done & fsm.out == 2'd1 & go ? const0.out;
    mult.right = !reg1.done & fsm.out == 2'd1 & go ? const1.out;
    reg0.clk = clk;
    reg0.in = !reg0.done & fsm.out == 2'd0 & go ? add.out;
    reg0.write_en = !reg0.done & fsm.out == 2'd0 & go ? 1'd1;
    reg1.clk = clk;
    reg1.in = !reg1.done & fsm.out == 2'd1 & go ? mult.out;
    reg1.write_en = !reg1.done & fsm.out == 2'd1 & go ? mult.done;
  }

  control {}
}