/* verilator lint_off WIDTH */
module std_reg
  #(parameter width = 32)
   (input wire [width-1:0] in,
    input wire write_en,
    input wire clk,
    // output
    output logic [width - 1:0] out,
    output logic done);

  always_ff @(posedge clk) begin
    if (write_en) begin
      out <= in;
      done <= 1'd1;
    end else
      done <= 1'd0;
  end
endmodule

module std_add
  #(parameter width = 32)
  (input  logic [width-1:0] left,
    input  logic [width-1:0] right,
    output logic [width-1:0] out);
  assign out = left + right;
endmodule

module std_mult_pipe
  #(parameter width = 32)
   (input logic [width-1:0] left,
    input logic [width-1:0] right,
    input logic go,
    input logic clk,
    output logic [width-1:0] out,
    output logic done);
   logic [width-1:0] rtmp;
   logic [width-1:0] ltmp;
   logic [width-1:0] out_tmp;
   reg done_buf[1:0];
   always_ff @(posedge clk) begin
     if (go) begin
       rtmp <= right;
       ltmp <= left;
       out_tmp <= rtmp * ltmp;
       out <= out_tmp;

       done <= done_buf[1];
       done_buf[0] <= 1'b1;
       done_buf[1] <= done_buf[0];
     end else begin
       rtmp <= 0;
       ltmp <= 0;
       out_tmp <= 0;
       out <= 0;

       done <= 0;
       done_buf[0] <= 0;
       done_buf[1] <= 0;
     end
   end
 endmodule

module std_mem_d1
  #(parameter width = 32,
    parameter size = 16,
    parameter idx_size = 4)
   (input logic [idx_size-1:0] addr0,
    input logic [width-1:0]   write_data,
    input logic               write_en,
    input logic               clk,
    output logic [width-1:0]  read_data,
    output logic done);

  logic [width-1:0]  mem[size-1:0];

  assign read_data = mem[addr0];
  always_ff @(posedge clk) begin
    if (write_en) begin
      mem[addr0] <= write_data;
      done <= 1'd1;
    end else
      done <= 1'd0;
  end
endmodule

module std_mem_d2
  #(parameter width = 32,
    parameter d0_size = 16,
    parameter d1_size = 16,
    parameter d0_idx_size = 4,
    parameter d1_idx_size = 4)
   (input logic [d0_idx_size-1:0] addr0,
    input logic [d1_idx_size-1:0] addr1,
    input logic [width-1:0]   write_data,
    input logic               write_en,
    input logic               clk,
    output logic [width-1:0]  read_data,
    output logic done);

  logic [width-1:0]  mem[d0_size-1:0][d1_size-1:0];

  assign read_data = mem[addr0][addr1];
  always_ff @(posedge clk) begin
    if (write_en) begin
      mem[addr0][addr1] <= write_data;
      done <= 1'd1;
    end else
      done <= 1'd0;
  end
endmodule

// Component Signature
module mac_pe (
      input logic [31:0] top,
      input logic [31:0] left,
      input logic go,
      input logic clk,
      output logic [31:0] down,
      output logic [31:0] right,
      output logic [31:0] out,
      output logic done
  );
  
  // Structure wire declarations
  logic [31:0] mul_left;
  logic [31:0] mul_right;
  logic mul_go;
  logic mul_clk;
  logic [31:0] mul_out;
  logic mul_done;
  logic [31:0] add_left;
  logic [31:0] add_right;
  logic [31:0] add_out;
  logic [31:0] mul_reg_in;
  logic mul_reg_write_en;
  logic mul_reg_clk;
  logic [31:0] mul_reg_out;
  logic mul_reg_done;
  logic [31:0] acc_in;
  logic acc_write_en;
  logic acc_clk;
  logic [31:0] acc_out;
  logic acc_done;
  logic [31:0] fsm0_in;
  logic fsm0_write_en;
  logic fsm0_clk;
  logic [31:0] fsm0_out;
  logic fsm0_done;
  
  // Subcomponent Instances
  std_mult_pipe #(32) mul (
      .left(mul_left),
      .right(mul_right),
      .go(mul_go),
      .clk(clk),
      .out(mul_out),
      .done(mul_done)
  );
  
  std_add #(32) add (
      .left(add_left),
      .right(add_right),
      .out(add_out)
  );
  
  std_reg #(32) mul_reg (
      .in(mul_reg_in),
      .write_en(mul_reg_write_en),
      .clk(clk),
      .out(mul_reg_out),
      .done(mul_reg_done)
  );
  
  std_reg #(32) acc (
      .in(acc_in),
      .write_en(acc_write_en),
      .clk(clk),
      .out(acc_out),
      .done(acc_done)
  );
  
  std_reg #(32) fsm0 (
      .in(fsm0_in),
      .write_en(fsm0_write_en),
      .clk(clk),
      .out(fsm0_out),
      .done(fsm0_done)
  );
  
  // Memory initialization / finalization 
  import "DPI-C" function string futil_getenv (input string env_var);
  string DATA;
   initial begin
  DATA = futil_getenv("DATA");
      $fdisplay(2, "DATA (path to meminit files): %s", DATA);
      
  end
  
   final begin
      
  end
  
  // Input / output connections
  always_comb begin
    down = top;
    right = left;
    out = acc_out;
    if ((fsm0_out == 32'd2))
      done = 1'd1;
    else 
      done = '0;
    
    if ((fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_left = top;
    else 
      mul_left = '0;
    
    if ((fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_right = left;
    else 
      mul_right = '0;
    
    if ((!mul_done & fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_go = 1'd1;
    else 
      mul_go = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      add_left = acc_out;
    else 
      add_left = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      add_right = mul_reg_out;
    else 
      add_right = '0;
    
    if ((mul_done & fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_reg_in = mul_out;
    else 
      mul_reg_in = '0;
    
    if ((mul_done & fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_reg_write_en = 1'd1;
    else 
      mul_reg_write_en = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      acc_in = add_out;
    else 
      acc_in = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      acc_write_en = 1'd1;
    else 
      acc_write_en = '0;
    
    if ((fsm0_out == 32'd1 & acc_done & go))
      fsm0_in = 32'd2;
    else if ((fsm0_out == 32'd0 & mul_reg_done & go))
      fsm0_in = 32'd1;
    else if ((fsm0_out == 32'd2))
      fsm0_in = 32'd0;
    else 
      fsm0_in = '0;
    
    if ((fsm0_out == 32'd0 & mul_reg_done & go | fsm0_out == 32'd1 & acc_done & go | fsm0_out == 32'd2))
      fsm0_write_en = 1'd1;
    else 
      fsm0_write_en = '0;
    
  end
endmodule // end mac_pe
// Component Signature
module main (
      input logic go,
      input logic clk,
      output logic done
  );
  
  // Structure wire declarations
  logic [31:0] left_00_read_in;
  logic left_00_read_write_en;
  logic left_00_read_clk;
  logic [31:0] left_00_read_out;
  logic left_00_read_done;
  logic [31:0] top_00_read_in;
  logic top_00_read_write_en;
  logic top_00_read_clk;
  logic [31:0] top_00_read_out;
  logic top_00_read_done;
  logic [31:0] pe_00_top;
  logic [31:0] pe_00_left;
  logic pe_00_go;
  logic pe_00_clk;
  logic [31:0] pe_00_down;
  logic [31:0] pe_00_right;
  logic [31:0] pe_00_out;
  logic pe_00_done;
  logic out_mem_addr0;
  logic out_mem_addr1;
  logic [31:0] out_mem_write_data;
  logic out_mem_write_en;
  logic out_mem_clk;
  logic [31:0] out_mem_read_data;
  logic out_mem_done;
  logic [1:0] l0_addr0;
  logic [31:0] l0_write_data;
  logic l0_write_en;
  logic l0_clk;
  logic [31:0] l0_read_data;
  logic l0_done;
  logic [1:0] l0_add_left;
  logic [1:0] l0_add_right;
  logic [1:0] l0_add_out;
  logic [1:0] l0_idx_in;
  logic l0_idx_write_en;
  logic l0_idx_clk;
  logic [1:0] l0_idx_out;
  logic l0_idx_done;
  logic [1:0] t0_addr0;
  logic [31:0] t0_write_data;
  logic t0_write_en;
  logic t0_clk;
  logic [31:0] t0_read_data;
  logic t0_done;
  logic [1:0] t0_add_left;
  logic [1:0] t0_add_right;
  logic [1:0] t0_add_out;
  logic [1:0] t0_idx_in;
  logic t0_idx_write_en;
  logic t0_idx_clk;
  logic [1:0] t0_idx_out;
  logic t0_idx_done;
  logic par_reset0_in;
  logic par_reset0_write_en;
  logic par_reset0_clk;
  logic par_reset0_out;
  logic par_reset0_done;
  logic par_done_reg0_in;
  logic par_done_reg0_write_en;
  logic par_done_reg0_clk;
  logic par_done_reg0_out;
  logic par_done_reg0_done;
  logic par_done_reg1_in;
  logic par_done_reg1_write_en;
  logic par_done_reg1_clk;
  logic par_done_reg1_out;
  logic par_done_reg1_done;
  logic par_reset1_in;
  logic par_reset1_write_en;
  logic par_reset1_clk;
  logic par_reset1_out;
  logic par_reset1_done;
  logic par_done_reg2_in;
  logic par_done_reg2_write_en;
  logic par_done_reg2_clk;
  logic par_done_reg2_out;
  logic par_done_reg2_done;
  logic par_done_reg3_in;
  logic par_done_reg3_write_en;
  logic par_done_reg3_clk;
  logic par_done_reg3_out;
  logic par_done_reg3_done;
  logic par_reset2_in;
  logic par_reset2_write_en;
  logic par_reset2_clk;
  logic par_reset2_out;
  logic par_reset2_done;
  logic par_done_reg4_in;
  logic par_done_reg4_write_en;
  logic par_done_reg4_clk;
  logic par_done_reg4_out;
  logic par_done_reg4_done;
  logic par_done_reg5_in;
  logic par_done_reg5_write_en;
  logic par_done_reg5_clk;
  logic par_done_reg5_out;
  logic par_done_reg5_done;
  logic par_reset3_in;
  logic par_reset3_write_en;
  logic par_reset3_clk;
  logic par_reset3_out;
  logic par_reset3_done;
  logic par_done_reg6_in;
  logic par_done_reg6_write_en;
  logic par_done_reg6_clk;
  logic par_done_reg6_out;
  logic par_done_reg6_done;
  logic par_done_reg7_in;
  logic par_done_reg7_write_en;
  logic par_done_reg7_clk;
  logic par_done_reg7_out;
  logic par_done_reg7_done;
  logic par_done_reg8_in;
  logic par_done_reg8_write_en;
  logic par_done_reg8_clk;
  logic par_done_reg8_out;
  logic par_done_reg8_done;
  logic par_reset4_in;
  logic par_reset4_write_en;
  logic par_reset4_clk;
  logic par_reset4_out;
  logic par_reset4_done;
  logic par_done_reg9_in;
  logic par_done_reg9_write_en;
  logic par_done_reg9_clk;
  logic par_done_reg9_out;
  logic par_done_reg9_done;
  logic par_done_reg10_in;
  logic par_done_reg10_write_en;
  logic par_done_reg10_clk;
  logic par_done_reg10_out;
  logic par_done_reg10_done;
  logic par_reset5_in;
  logic par_reset5_write_en;
  logic par_reset5_clk;
  logic par_reset5_out;
  logic par_reset5_done;
  logic par_done_reg11_in;
  logic par_done_reg11_write_en;
  logic par_done_reg11_clk;
  logic par_done_reg11_out;
  logic par_done_reg11_done;
  logic par_done_reg12_in;
  logic par_done_reg12_write_en;
  logic par_done_reg12_clk;
  logic par_done_reg12_out;
  logic par_done_reg12_done;
  logic par_done_reg13_in;
  logic par_done_reg13_write_en;
  logic par_done_reg13_clk;
  logic par_done_reg13_out;
  logic par_done_reg13_done;
  logic par_reset6_in;
  logic par_reset6_write_en;
  logic par_reset6_clk;
  logic par_reset6_out;
  logic par_reset6_done;
  logic par_done_reg14_in;
  logic par_done_reg14_write_en;
  logic par_done_reg14_clk;
  logic par_done_reg14_out;
  logic par_done_reg14_done;
  logic par_done_reg15_in;
  logic par_done_reg15_write_en;
  logic par_done_reg15_clk;
  logic par_done_reg15_out;
  logic par_done_reg15_done;
  logic par_reset7_in;
  logic par_reset7_write_en;
  logic par_reset7_clk;
  logic par_reset7_out;
  logic par_reset7_done;
  logic par_done_reg16_in;
  logic par_done_reg16_write_en;
  logic par_done_reg16_clk;
  logic par_done_reg16_out;
  logic par_done_reg16_done;
  logic [31:0] fsm0_in;
  logic fsm0_write_en;
  logic fsm0_clk;
  logic [31:0] fsm0_out;
  logic fsm0_done;
  
  // Subcomponent Instances
  std_reg #(32) left_00_read (
      .in(left_00_read_in),
      .write_en(left_00_read_write_en),
      .clk(clk),
      .out(left_00_read_out),
      .done(left_00_read_done)
  );
  
  std_reg #(32) top_00_read (
      .in(top_00_read_in),
      .write_en(top_00_read_write_en),
      .clk(clk),
      .out(top_00_read_out),
      .done(top_00_read_done)
  );
  
  mac_pe #() pe_00 (
      .top(pe_00_top),
      .left(pe_00_left),
      .go(pe_00_go),
      .clk(clk),
      .down(pe_00_down),
      .right(pe_00_right),
      .out(pe_00_out),
      .done(pe_00_done)
  );
  
  std_mem_d2 #(32, 1, 1, 1, 1) out_mem (
      .addr0(out_mem_addr0),
      .addr1(out_mem_addr1),
      .write_data(out_mem_write_data),
      .write_en(out_mem_write_en),
      .clk(clk),
      .read_data(out_mem_read_data),
      .done(out_mem_done)
  );
  
  std_mem_d1 #(32, 3, 2) l0 (
      .addr0(l0_addr0),
      .write_data(l0_write_data),
      .write_en(l0_write_en),
      .clk(clk),
      .read_data(l0_read_data),
      .done(l0_done)
  );
  
  std_add #(2) l0_add (
      .left(l0_add_left),
      .right(l0_add_right),
      .out(l0_add_out)
  );
  
  std_reg #(2) l0_idx (
      .in(l0_idx_in),
      .write_en(l0_idx_write_en),
      .clk(clk),
      .out(l0_idx_out),
      .done(l0_idx_done)
  );
  
  std_mem_d1 #(32, 3, 2) t0 (
      .addr0(t0_addr0),
      .write_data(t0_write_data),
      .write_en(t0_write_en),
      .clk(clk),
      .read_data(t0_read_data),
      .done(t0_done)
  );
  
  std_add #(2) t0_add (
      .left(t0_add_left),
      .right(t0_add_right),
      .out(t0_add_out)
  );
  
  std_reg #(2) t0_idx (
      .in(t0_idx_in),
      .write_en(t0_idx_write_en),
      .clk(clk),
      .out(t0_idx_out),
      .done(t0_idx_done)
  );
  
  std_reg #(1) par_reset0 (
      .in(par_reset0_in),
      .write_en(par_reset0_write_en),
      .clk(clk),
      .out(par_reset0_out),
      .done(par_reset0_done)
  );
  
  std_reg #(1) par_done_reg0 (
      .in(par_done_reg0_in),
      .write_en(par_done_reg0_write_en),
      .clk(clk),
      .out(par_done_reg0_out),
      .done(par_done_reg0_done)
  );
  
  std_reg #(1) par_done_reg1 (
      .in(par_done_reg1_in),
      .write_en(par_done_reg1_write_en),
      .clk(clk),
      .out(par_done_reg1_out),
      .done(par_done_reg1_done)
  );
  
  std_reg #(1) par_reset1 (
      .in(par_reset1_in),
      .write_en(par_reset1_write_en),
      .clk(clk),
      .out(par_reset1_out),
      .done(par_reset1_done)
  );
  
  std_reg #(1) par_done_reg2 (
      .in(par_done_reg2_in),
      .write_en(par_done_reg2_write_en),
      .clk(clk),
      .out(par_done_reg2_out),
      .done(par_done_reg2_done)
  );
  
  std_reg #(1) par_done_reg3 (
      .in(par_done_reg3_in),
      .write_en(par_done_reg3_write_en),
      .clk(clk),
      .out(par_done_reg3_out),
      .done(par_done_reg3_done)
  );
  
  std_reg #(1) par_reset2 (
      .in(par_reset2_in),
      .write_en(par_reset2_write_en),
      .clk(clk),
      .out(par_reset2_out),
      .done(par_reset2_done)
  );
  
  std_reg #(1) par_done_reg4 (
      .in(par_done_reg4_in),
      .write_en(par_done_reg4_write_en),
      .clk(clk),
      .out(par_done_reg4_out),
      .done(par_done_reg4_done)
  );
  
  std_reg #(1) par_done_reg5 (
      .in(par_done_reg5_in),
      .write_en(par_done_reg5_write_en),
      .clk(clk),
      .out(par_done_reg5_out),
      .done(par_done_reg5_done)
  );
  
  std_reg #(1) par_reset3 (
      .in(par_reset3_in),
      .write_en(par_reset3_write_en),
      .clk(clk),
      .out(par_reset3_out),
      .done(par_reset3_done)
  );
  
  std_reg #(1) par_done_reg6 (
      .in(par_done_reg6_in),
      .write_en(par_done_reg6_write_en),
      .clk(clk),
      .out(par_done_reg6_out),
      .done(par_done_reg6_done)
  );
  
  std_reg #(1) par_done_reg7 (
      .in(par_done_reg7_in),
      .write_en(par_done_reg7_write_en),
      .clk(clk),
      .out(par_done_reg7_out),
      .done(par_done_reg7_done)
  );
  
  std_reg #(1) par_done_reg8 (
      .in(par_done_reg8_in),
      .write_en(par_done_reg8_write_en),
      .clk(clk),
      .out(par_done_reg8_out),
      .done(par_done_reg8_done)
  );
  
  std_reg #(1) par_reset4 (
      .in(par_reset4_in),
      .write_en(par_reset4_write_en),
      .clk(clk),
      .out(par_reset4_out),
      .done(par_reset4_done)
  );
  
  std_reg #(1) par_done_reg9 (
      .in(par_done_reg9_in),
      .write_en(par_done_reg9_write_en),
      .clk(clk),
      .out(par_done_reg9_out),
      .done(par_done_reg9_done)
  );
  
  std_reg #(1) par_done_reg10 (
      .in(par_done_reg10_in),
      .write_en(par_done_reg10_write_en),
      .clk(clk),
      .out(par_done_reg10_out),
      .done(par_done_reg10_done)
  );
  
  std_reg #(1) par_reset5 (
      .in(par_reset5_in),
      .write_en(par_reset5_write_en),
      .clk(clk),
      .out(par_reset5_out),
      .done(par_reset5_done)
  );
  
  std_reg #(1) par_done_reg11 (
      .in(par_done_reg11_in),
      .write_en(par_done_reg11_write_en),
      .clk(clk),
      .out(par_done_reg11_out),
      .done(par_done_reg11_done)
  );
  
  std_reg #(1) par_done_reg12 (
      .in(par_done_reg12_in),
      .write_en(par_done_reg12_write_en),
      .clk(clk),
      .out(par_done_reg12_out),
      .done(par_done_reg12_done)
  );
  
  std_reg #(1) par_done_reg13 (
      .in(par_done_reg13_in),
      .write_en(par_done_reg13_write_en),
      .clk(clk),
      .out(par_done_reg13_out),
      .done(par_done_reg13_done)
  );
  
  std_reg #(1) par_reset6 (
      .in(par_reset6_in),
      .write_en(par_reset6_write_en),
      .clk(clk),
      .out(par_reset6_out),
      .done(par_reset6_done)
  );
  
  std_reg #(1) par_done_reg14 (
      .in(par_done_reg14_in),
      .write_en(par_done_reg14_write_en),
      .clk(clk),
      .out(par_done_reg14_out),
      .done(par_done_reg14_done)
  );
  
  std_reg #(1) par_done_reg15 (
      .in(par_done_reg15_in),
      .write_en(par_done_reg15_write_en),
      .clk(clk),
      .out(par_done_reg15_out),
      .done(par_done_reg15_done)
  );
  
  std_reg #(1) par_reset7 (
      .in(par_reset7_in),
      .write_en(par_reset7_write_en),
      .clk(clk),
      .out(par_reset7_out),
      .done(par_reset7_done)
  );
  
  std_reg #(1) par_done_reg16 (
      .in(par_done_reg16_in),
      .write_en(par_done_reg16_write_en),
      .clk(clk),
      .out(par_done_reg16_out),
      .done(par_done_reg16_done)
  );
  
  std_reg #(32) fsm0 (
      .in(fsm0_in),
      .write_en(fsm0_write_en),
      .clk(clk),
      .out(fsm0_out),
      .done(fsm0_done)
  );
  
  // Memory initialization / finalization 
  import "DPI-C" function string futil_getenv (input string env_var);
  string DATA;
   initial begin
  DATA = futil_getenv("DATA");
      $fdisplay(2, "DATA (path to meminit files): %s", DATA);
      $readmemh({ DATA, "/out_mem.dat" }, out_mem.mem);
      $readmemh({ DATA, "/l0.dat" }, l0.mem);
      $readmemh({ DATA, "/t0.dat" }, t0.mem);
  end
  
   final begin
      $writememh({ DATA, "/out_mem.out" }, out_mem.mem);
      $writememh({ DATA, "/l0.out" }, l0.mem);
      $writememh({ DATA, "/t0.out" }, t0.mem);
  end
  
  // Input / output connections
  always_comb begin
    if ((fsm0_out == 32'd9))
      done = 1'd1;
    else 
      done = '0;
    
    if ((!(par_done_reg5_out | left_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg10_out | left_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg15_out | left_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      left_00_read_in = l0_read_data;
    else 
      left_00_read_in = '0;
    
    if ((!(par_done_reg5_out | left_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg10_out | left_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg15_out | left_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      left_00_read_write_en = 1'd1;
    else 
      left_00_read_write_en = '0;
    
    if ((!(par_done_reg4_out | top_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg9_out | top_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg14_out | top_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      top_00_read_in = t0_read_data;
    else 
      top_00_read_in = '0;
    
    if ((!(par_done_reg4_out | top_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg9_out | top_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg14_out | top_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      top_00_read_write_en = 1'd1;
    else 
      top_00_read_write_en = '0;
    
    if ((!(par_done_reg8_out | pe_00_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg13_out | pe_00_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg16_out | pe_00_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      pe_00_top = top_00_read_out;
    else 
      pe_00_top = '0;
    
    if ((!(par_done_reg8_out | pe_00_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg13_out | pe_00_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg16_out | pe_00_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      pe_00_left = left_00_read_out;
    else 
      pe_00_left = '0;
    
    if ((!pe_00_done & (!(par_done_reg8_out | pe_00_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg13_out | pe_00_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg16_out | pe_00_done) & fsm0_out == 32'd7 & !par_reset7_out & go)))
      pe_00_go = 1'd1;
    else 
      pe_00_go = '0;
    
    if ((fsm0_out == 32'd8 & !out_mem_done & go))
      out_mem_addr0 = 1'd0;
    else 
      out_mem_addr0 = '0;
    
    if ((fsm0_out == 32'd8 & !out_mem_done & go))
      out_mem_addr1 = 1'd0;
    else 
      out_mem_addr1 = '0;
    
    if ((fsm0_out == 32'd8 & !out_mem_done & go))
      out_mem_write_data = pe_00_out;
    else 
      out_mem_write_data = '0;
    
    if ((fsm0_out == 32'd8 & !out_mem_done & go))
      out_mem_write_en = 1'd1;
    else 
      out_mem_write_en = '0;
    
    if ((!(par_done_reg5_out | left_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg10_out | left_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg15_out | left_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      l0_addr0 = l0_idx_out;
    else 
      l0_addr0 = '0;
    
    if ((!(par_done_reg3_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg7_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg12_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_add_left = 2'd1;
    else 
      l0_add_left = '0;
    
    if ((!(par_done_reg3_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg7_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg12_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_add_right = l0_idx_out;
    else 
      l0_add_right = '0;
    
    if ((!(par_done_reg3_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg7_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg12_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_idx_in = l0_add_out;
    else if ((!(par_done_reg1_out | l0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go))
      l0_idx_in = 2'd3;
    else 
      l0_idx_in = '0;
    
    if ((!(par_done_reg1_out | l0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go | !(par_done_reg3_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg7_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg12_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_idx_write_en = 1'd1;
    else 
      l0_idx_write_en = '0;
    
    if ((!(par_done_reg4_out | top_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg9_out | top_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg14_out | top_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      t0_addr0 = t0_idx_out;
    else 
      t0_addr0 = '0;
    
    if ((!(par_done_reg2_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg6_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg11_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_add_left = 2'd1;
    else 
      t0_add_left = '0;
    
    if ((!(par_done_reg2_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg6_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg11_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_add_right = t0_idx_out;
    else 
      t0_add_right = '0;
    
    if ((!(par_done_reg2_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg6_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg11_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_idx_in = t0_add_out;
    else if ((!(par_done_reg0_out | t0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go))
      t0_idx_in = 2'd3;
    else 
      t0_idx_in = '0;
    
    if ((!(par_done_reg0_out | t0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go | !(par_done_reg2_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg6_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg11_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_idx_write_en = 1'd1;
    else 
      t0_idx_write_en = '0;
    
    if (par_reset0_out)
      par_reset0_in = 1'd0;
    else if ((par_done_reg0_out & par_done_reg1_out & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_reset0_in = 1'd1;
    else 
      par_reset0_in = '0;
    
    if ((par_done_reg0_out & par_done_reg1_out & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_reset0_write_en = 1'd1;
    else 
      par_reset0_write_en = '0;
    
    if (par_reset0_out)
      par_done_reg0_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_done_reg0_in = 1'd1;
    else 
      par_done_reg0_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_done_reg0_write_en = 1'd1;
    else 
      par_done_reg0_write_en = '0;
    
    if (par_reset0_out)
      par_done_reg1_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_done_reg1_in = 1'd1;
    else 
      par_done_reg1_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_done_reg1_write_en = 1'd1;
    else 
      par_done_reg1_write_en = '0;
    
    if (par_reset1_out)
      par_reset1_in = 1'd0;
    else if ((par_done_reg2_out & par_done_reg3_out & fsm0_out == 32'd1 & !par_reset1_out & go))
      par_reset1_in = 1'd1;
    else 
      par_reset1_in = '0;
    
    if ((par_done_reg2_out & par_done_reg3_out & fsm0_out == 32'd1 & !par_reset1_out & go | par_reset1_out))
      par_reset1_write_en = 1'd1;
    else 
      par_reset1_write_en = '0;
    
    if (par_reset1_out)
      par_done_reg2_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go))
      par_done_reg2_in = 1'd1;
    else 
      par_done_reg2_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go | par_reset1_out))
      par_done_reg2_write_en = 1'd1;
    else 
      par_done_reg2_write_en = '0;
    
    if (par_reset1_out)
      par_done_reg3_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go))
      par_done_reg3_in = 1'd1;
    else 
      par_done_reg3_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go | par_reset1_out))
      par_done_reg3_write_en = 1'd1;
    else 
      par_done_reg3_write_en = '0;
    
    if (par_reset2_out)
      par_reset2_in = 1'd0;
    else if ((par_done_reg4_out & par_done_reg5_out & fsm0_out == 32'd2 & !par_reset2_out & go))
      par_reset2_in = 1'd1;
    else 
      par_reset2_in = '0;
    
    if ((par_done_reg4_out & par_done_reg5_out & fsm0_out == 32'd2 & !par_reset2_out & go | par_reset2_out))
      par_reset2_write_en = 1'd1;
    else 
      par_reset2_write_en = '0;
    
    if (par_reset2_out)
      par_done_reg4_in = 1'd0;
    else if ((top_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go))
      par_done_reg4_in = 1'd1;
    else 
      par_done_reg4_in = '0;
    
    if ((top_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go | par_reset2_out))
      par_done_reg4_write_en = 1'd1;
    else 
      par_done_reg4_write_en = '0;
    
    if (par_reset2_out)
      par_done_reg5_in = 1'd0;
    else if ((left_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go))
      par_done_reg5_in = 1'd1;
    else 
      par_done_reg5_in = '0;
    
    if ((left_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go | par_reset2_out))
      par_done_reg5_write_en = 1'd1;
    else 
      par_done_reg5_write_en = '0;
    
    if (par_reset3_out)
      par_reset3_in = 1'd0;
    else if ((par_done_reg6_out & par_done_reg7_out & par_done_reg8_out & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_reset3_in = 1'd1;
    else 
      par_reset3_in = '0;
    
    if ((par_done_reg6_out & par_done_reg7_out & par_done_reg8_out & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_reset3_write_en = 1'd1;
    else 
      par_reset3_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg6_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg6_in = 1'd1;
    else 
      par_done_reg6_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg6_write_en = 1'd1;
    else 
      par_done_reg6_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg7_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg7_in = 1'd1;
    else 
      par_done_reg7_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg7_write_en = 1'd1;
    else 
      par_done_reg7_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg8_in = 1'd0;
    else if ((pe_00_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg8_in = 1'd1;
    else 
      par_done_reg8_in = '0;
    
    if ((pe_00_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg8_write_en = 1'd1;
    else 
      par_done_reg8_write_en = '0;
    
    if (par_reset4_out)
      par_reset4_in = 1'd0;
    else if ((par_done_reg9_out & par_done_reg10_out & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_reset4_in = 1'd1;
    else 
      par_reset4_in = '0;
    
    if ((par_done_reg9_out & par_done_reg10_out & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_reset4_write_en = 1'd1;
    else 
      par_reset4_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg9_in = 1'd0;
    else if ((top_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg9_in = 1'd1;
    else 
      par_done_reg9_in = '0;
    
    if ((top_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg9_write_en = 1'd1;
    else 
      par_done_reg9_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg10_in = 1'd0;
    else if ((left_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg10_in = 1'd1;
    else 
      par_done_reg10_in = '0;
    
    if ((left_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg10_write_en = 1'd1;
    else 
      par_done_reg10_write_en = '0;
    
    if (par_reset5_out)
      par_reset5_in = 1'd0;
    else if ((par_done_reg11_out & par_done_reg12_out & par_done_reg13_out & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_reset5_in = 1'd1;
    else 
      par_reset5_in = '0;
    
    if ((par_done_reg11_out & par_done_reg12_out & par_done_reg13_out & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_reset5_write_en = 1'd1;
    else 
      par_reset5_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg11_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg11_in = 1'd1;
    else 
      par_done_reg11_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg11_write_en = 1'd1;
    else 
      par_done_reg11_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg12_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg12_in = 1'd1;
    else 
      par_done_reg12_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg12_write_en = 1'd1;
    else 
      par_done_reg12_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg13_in = 1'd0;
    else if ((pe_00_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg13_in = 1'd1;
    else 
      par_done_reg13_in = '0;
    
    if ((pe_00_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg13_write_en = 1'd1;
    else 
      par_done_reg13_write_en = '0;
    
    if (par_reset6_out)
      par_reset6_in = 1'd0;
    else if ((par_done_reg14_out & par_done_reg15_out & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_reset6_in = 1'd1;
    else 
      par_reset6_in = '0;
    
    if ((par_done_reg14_out & par_done_reg15_out & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_reset6_write_en = 1'd1;
    else 
      par_reset6_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg14_in = 1'd0;
    else if ((top_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg14_in = 1'd1;
    else 
      par_done_reg14_in = '0;
    
    if ((top_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg14_write_en = 1'd1;
    else 
      par_done_reg14_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg15_in = 1'd0;
    else if ((left_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg15_in = 1'd1;
    else 
      par_done_reg15_in = '0;
    
    if ((left_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg15_write_en = 1'd1;
    else 
      par_done_reg15_write_en = '0;
    
    if (par_reset7_out)
      par_reset7_in = 1'd0;
    else if ((par_done_reg16_out & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_reset7_in = 1'd1;
    else 
      par_reset7_in = '0;
    
    if ((par_done_reg16_out & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_reset7_write_en = 1'd1;
    else 
      par_reset7_write_en = '0;
    
    if (par_reset7_out)
      par_done_reg16_in = 1'd0;
    else if ((pe_00_done & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_done_reg16_in = 1'd1;
    else 
      par_done_reg16_in = '0;
    
    if ((pe_00_done & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_done_reg16_write_en = 1'd1;
    else 
      par_done_reg16_write_en = '0;
    
    if ((fsm0_out == 32'd4 & par_reset4_out & go))
      fsm0_in = 32'd5;
    else if ((fsm0_out == 32'd3 & par_reset3_out & go))
      fsm0_in = 32'd4;
    else if ((fsm0_out == 32'd2 & par_reset2_out & go))
      fsm0_in = 32'd3;
    else if ((fsm0_out == 32'd1 & par_reset1_out & go))
      fsm0_in = 32'd2;
    else if ((fsm0_out == 32'd0 & par_reset0_out & go))
      fsm0_in = 32'd1;
    else if ((fsm0_out == 32'd9))
      fsm0_in = 32'd0;
    else if ((fsm0_out == 32'd8 & out_mem_done & go))
      fsm0_in = 32'd9;
    else if ((fsm0_out == 32'd7 & par_reset7_out & go))
      fsm0_in = 32'd8;
    else if ((fsm0_out == 32'd6 & par_reset6_out & go))
      fsm0_in = 32'd7;
    else if ((fsm0_out == 32'd5 & par_reset5_out & go))
      fsm0_in = 32'd6;
    else 
      fsm0_in = '0;
    
    if ((fsm0_out == 32'd0 & par_reset0_out & go | fsm0_out == 32'd1 & par_reset1_out & go | fsm0_out == 32'd2 & par_reset2_out & go | fsm0_out == 32'd3 & par_reset3_out & go | fsm0_out == 32'd4 & par_reset4_out & go | fsm0_out == 32'd5 & par_reset5_out & go | fsm0_out == 32'd6 & par_reset6_out & go | fsm0_out == 32'd7 & par_reset7_out & go | fsm0_out == 32'd8 & out_mem_done & go | fsm0_out == 32'd9))
      fsm0_write_en = 1'd1;
    else 
      fsm0_write_en = '0;
    
  end
endmodule // end main