/* verilator lint_off WIDTH */
module std_reg
  #(parameter width = 32)
   (input wire [width-1:0] in,
    input wire write_en,
    input wire clk,
    // output
    output logic [width - 1:0] out,
    output logic done);

  always_ff @(posedge clk) begin
    if (write_en) begin
      out <= in;
      done <= 1'd1;
    end else
      done <= 1'd0;
  end
endmodule

module std_add
  #(parameter width = 32)
  (input  logic [width-1:0] left,
    input  logic [width-1:0] right,
    output logic [width-1:0] out);
  assign out = left + right;
endmodule

module std_mult_pipe
  #(parameter width = 32)
   (input logic [width-1:0] left,
    input logic [width-1:0] right,
    input logic go,
    input logic clk,
    output logic [width-1:0] out,
    output logic done);
   logic [width-1:0] rtmp;
   logic [width-1:0] ltmp;
   logic [width-1:0] out_tmp;
   reg done_buf[1:0];
   always_ff @(posedge clk) begin
     if (go) begin
       rtmp <= right;
       ltmp <= left;
       out_tmp <= rtmp * ltmp;
       out <= out_tmp;

       done <= done_buf[1];
       done_buf[0] <= 1'b1;
       done_buf[1] <= done_buf[0];
     end else begin
       rtmp <= 0;
       ltmp <= 0;
       out_tmp <= 0;
       out <= 0;

       done <= 0;
       done_buf[0] <= 0;
       done_buf[1] <= 0;
     end
   end
 endmodule

module std_mem_d1
  #(parameter width = 32,
    parameter size = 16,
    parameter idx_size = 4)
   (input logic [idx_size-1:0] addr0,
    input logic [width-1:0]   write_data,
    input logic               write_en,
    input logic               clk,
    output logic [width-1:0]  read_data,
    output logic done);

  logic [width-1:0]  mem[size-1:0];

  assign read_data = mem[addr0];
  always_ff @(posedge clk) begin
    if (write_en) begin
      mem[addr0] <= write_data;
      done <= 1'd1;
    end else
      done <= 1'd0;
  end
endmodule

module std_mem_d2
  #(parameter width = 32,
    parameter d0_size = 16,
    parameter d1_size = 16,
    parameter d0_idx_size = 4,
    parameter d1_idx_size = 4)
   (input logic [d0_idx_size-1:0] addr0,
    input logic [d1_idx_size-1:0] addr1,
    input logic [width-1:0]   write_data,
    input logic               write_en,
    input logic               clk,
    output logic [width-1:0]  read_data,
    output logic done);

  logic [width-1:0]  mem[d0_size-1:0][d1_size-1:0];

  assign read_data = mem[addr0][addr1];
  always_ff @(posedge clk) begin
    if (write_en) begin
      mem[addr0][addr1] <= write_data;
      done <= 1'd1;
    end else
      done <= 1'd0;
  end
endmodule

// Component Signature
module mac_pe (
      input logic [31:0] top,
      input logic [31:0] left,
      input logic go,
      input logic clk,
      output logic [31:0] down,
      output logic [31:0] right,
      output logic [31:0] out,
      output logic done
  );
  
  // Structure wire declarations
  logic [31:0] mul_left;
  logic [31:0] mul_right;
  logic mul_go;
  logic mul_clk;
  logic [31:0] mul_out;
  logic mul_done;
  logic [31:0] add_left;
  logic [31:0] add_right;
  logic [31:0] add_out;
  logic [31:0] mul_reg_in;
  logic mul_reg_write_en;
  logic mul_reg_clk;
  logic [31:0] mul_reg_out;
  logic mul_reg_done;
  logic [31:0] acc_in;
  logic acc_write_en;
  logic acc_clk;
  logic [31:0] acc_out;
  logic acc_done;
  logic [31:0] fsm0_in;
  logic fsm0_write_en;
  logic fsm0_clk;
  logic [31:0] fsm0_out;
  logic fsm0_done;
  
  // Subcomponent Instances
  std_mult_pipe #(32) mul (
      .left(mul_left),
      .right(mul_right),
      .go(mul_go),
      .clk(clk),
      .out(mul_out),
      .done(mul_done)
  );
  
  std_add #(32) add (
      .left(add_left),
      .right(add_right),
      .out(add_out)
  );
  
  std_reg #(32) mul_reg (
      .in(mul_reg_in),
      .write_en(mul_reg_write_en),
      .clk(clk),
      .out(mul_reg_out),
      .done(mul_reg_done)
  );
  
  std_reg #(32) acc (
      .in(acc_in),
      .write_en(acc_write_en),
      .clk(clk),
      .out(acc_out),
      .done(acc_done)
  );
  
  std_reg #(32) fsm0 (
      .in(fsm0_in),
      .write_en(fsm0_write_en),
      .clk(clk),
      .out(fsm0_out),
      .done(fsm0_done)
  );
  
  // Memory initialization / finalization 
  import "DPI-C" function string futil_getenv (input string env_var);
  string DATA;
   initial begin
  DATA = futil_getenv("DATA");
      $fdisplay(2, "DATA (path to meminit files): %s", DATA);
      
  end
  
   final begin
      
  end
  
  // Input / output connections
  always_comb begin
    down = top;
    right = left;
    out = acc_out;
    if ((fsm0_out == 32'd2))
      done = 1'd1;
    else 
      done = '0;
    
    if ((fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_left = top;
    else 
      mul_left = '0;
    
    if ((fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_right = left;
    else 
      mul_right = '0;
    
    if ((!mul_done & fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_go = 1'd1;
    else 
      mul_go = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      add_left = acc_out;
    else 
      add_left = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      add_right = mul_reg_out;
    else 
      add_right = '0;
    
    if ((mul_done & fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_reg_in = mul_out;
    else 
      mul_reg_in = '0;
    
    if ((mul_done & fsm0_out == 32'd0 & !mul_reg_done & go))
      mul_reg_write_en = 1'd1;
    else 
      mul_reg_write_en = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      acc_in = add_out;
    else 
      acc_in = '0;
    
    if ((fsm0_out == 32'd1 & !acc_done & go))
      acc_write_en = 1'd1;
    else 
      acc_write_en = '0;
    
    if ((fsm0_out == 32'd1 & acc_done & go))
      fsm0_in = 32'd2;
    else if ((fsm0_out == 32'd0 & mul_reg_done & go))
      fsm0_in = 32'd1;
    else if ((fsm0_out == 32'd2))
      fsm0_in = 32'd0;
    else 
      fsm0_in = '0;
    
    if ((fsm0_out == 32'd0 & mul_reg_done & go | fsm0_out == 32'd1 & acc_done & go | fsm0_out == 32'd2))
      fsm0_write_en = 1'd1;
    else 
      fsm0_write_en = '0;
    
  end
endmodule // end mac_pe
// Component Signature
module main (
      input logic go,
      input logic clk,
      output logic done
  );
  
  // Structure wire declarations
  logic [31:0] left_11_read_in;
  logic left_11_read_write_en;
  logic left_11_read_clk;
  logic [31:0] left_11_read_out;
  logic left_11_read_done;
  logic [31:0] top_11_read_in;
  logic top_11_read_write_en;
  logic top_11_read_clk;
  logic [31:0] top_11_read_out;
  logic top_11_read_done;
  logic [31:0] pe_11_top;
  logic [31:0] pe_11_left;
  logic pe_11_go;
  logic pe_11_clk;
  logic [31:0] pe_11_down;
  logic [31:0] pe_11_right;
  logic [31:0] pe_11_out;
  logic pe_11_done;
  logic [31:0] right_10_write_in;
  logic right_10_write_write_en;
  logic right_10_write_clk;
  logic [31:0] right_10_write_out;
  logic right_10_write_done;
  logic [31:0] left_10_read_in;
  logic left_10_read_write_en;
  logic left_10_read_clk;
  logic [31:0] left_10_read_out;
  logic left_10_read_done;
  logic [31:0] top_10_read_in;
  logic top_10_read_write_en;
  logic top_10_read_clk;
  logic [31:0] top_10_read_out;
  logic top_10_read_done;
  logic [31:0] pe_10_top;
  logic [31:0] pe_10_left;
  logic pe_10_go;
  logic pe_10_clk;
  logic [31:0] pe_10_down;
  logic [31:0] pe_10_right;
  logic [31:0] pe_10_out;
  logic pe_10_done;
  logic [31:0] down_01_write_in;
  logic down_01_write_write_en;
  logic down_01_write_clk;
  logic [31:0] down_01_write_out;
  logic down_01_write_done;
  logic [31:0] left_01_read_in;
  logic left_01_read_write_en;
  logic left_01_read_clk;
  logic [31:0] left_01_read_out;
  logic left_01_read_done;
  logic [31:0] top_01_read_in;
  logic top_01_read_write_en;
  logic top_01_read_clk;
  logic [31:0] top_01_read_out;
  logic top_01_read_done;
  logic [31:0] pe_01_top;
  logic [31:0] pe_01_left;
  logic pe_01_go;
  logic pe_01_clk;
  logic [31:0] pe_01_down;
  logic [31:0] pe_01_right;
  logic [31:0] pe_01_out;
  logic pe_01_done;
  logic [31:0] down_00_write_in;
  logic down_00_write_write_en;
  logic down_00_write_clk;
  logic [31:0] down_00_write_out;
  logic down_00_write_done;
  logic [31:0] right_00_write_in;
  logic right_00_write_write_en;
  logic right_00_write_clk;
  logic [31:0] right_00_write_out;
  logic right_00_write_done;
  logic [31:0] left_00_read_in;
  logic left_00_read_write_en;
  logic left_00_read_clk;
  logic [31:0] left_00_read_out;
  logic left_00_read_done;
  logic [31:0] top_00_read_in;
  logic top_00_read_write_en;
  logic top_00_read_clk;
  logic [31:0] top_00_read_out;
  logic top_00_read_done;
  logic [31:0] pe_00_top;
  logic [31:0] pe_00_left;
  logic pe_00_go;
  logic pe_00_clk;
  logic [31:0] pe_00_down;
  logic [31:0] pe_00_right;
  logic [31:0] pe_00_out;
  logic pe_00_done;
  logic [1:0] out_mem_addr0;
  logic [1:0] out_mem_addr1;
  logic [31:0] out_mem_write_data;
  logic out_mem_write_en;
  logic out_mem_clk;
  logic [31:0] out_mem_read_data;
  logic out_mem_done;
  logic [1:0] l1_addr0;
  logic [31:0] l1_write_data;
  logic l1_write_en;
  logic l1_clk;
  logic [31:0] l1_read_data;
  logic l1_done;
  logic [1:0] l1_add_left;
  logic [1:0] l1_add_right;
  logic [1:0] l1_add_out;
  logic [1:0] l1_idx_in;
  logic l1_idx_write_en;
  logic l1_idx_clk;
  logic [1:0] l1_idx_out;
  logic l1_idx_done;
  logic [1:0] l0_addr0;
  logic [31:0] l0_write_data;
  logic l0_write_en;
  logic l0_clk;
  logic [31:0] l0_read_data;
  logic l0_done;
  logic [1:0] l0_add_left;
  logic [1:0] l0_add_right;
  logic [1:0] l0_add_out;
  logic [1:0] l0_idx_in;
  logic l0_idx_write_en;
  logic l0_idx_clk;
  logic [1:0] l0_idx_out;
  logic l0_idx_done;
  logic [1:0] t1_addr0;
  logic [31:0] t1_write_data;
  logic t1_write_en;
  logic t1_clk;
  logic [31:0] t1_read_data;
  logic t1_done;
  logic [1:0] t1_add_left;
  logic [1:0] t1_add_right;
  logic [1:0] t1_add_out;
  logic [1:0] t1_idx_in;
  logic t1_idx_write_en;
  logic t1_idx_clk;
  logic [1:0] t1_idx_out;
  logic t1_idx_done;
  logic [1:0] t0_addr0;
  logic [31:0] t0_write_data;
  logic t0_write_en;
  logic t0_clk;
  logic [31:0] t0_read_data;
  logic t0_done;
  logic [1:0] t0_add_left;
  logic [1:0] t0_add_right;
  logic [1:0] t0_add_out;
  logic [1:0] t0_idx_in;
  logic t0_idx_write_en;
  logic t0_idx_clk;
  logic [1:0] t0_idx_out;
  logic t0_idx_done;
  logic par_reset0_in;
  logic par_reset0_write_en;
  logic par_reset0_clk;
  logic par_reset0_out;
  logic par_reset0_done;
  logic par_done_reg0_in;
  logic par_done_reg0_write_en;
  logic par_done_reg0_clk;
  logic par_done_reg0_out;
  logic par_done_reg0_done;
  logic par_done_reg1_in;
  logic par_done_reg1_write_en;
  logic par_done_reg1_clk;
  logic par_done_reg1_out;
  logic par_done_reg1_done;
  logic par_done_reg2_in;
  logic par_done_reg2_write_en;
  logic par_done_reg2_clk;
  logic par_done_reg2_out;
  logic par_done_reg2_done;
  logic par_done_reg3_in;
  logic par_done_reg3_write_en;
  logic par_done_reg3_clk;
  logic par_done_reg3_out;
  logic par_done_reg3_done;
  logic par_reset1_in;
  logic par_reset1_write_en;
  logic par_reset1_clk;
  logic par_reset1_out;
  logic par_reset1_done;
  logic par_done_reg4_in;
  logic par_done_reg4_write_en;
  logic par_done_reg4_clk;
  logic par_done_reg4_out;
  logic par_done_reg4_done;
  logic par_done_reg5_in;
  logic par_done_reg5_write_en;
  logic par_done_reg5_clk;
  logic par_done_reg5_out;
  logic par_done_reg5_done;
  logic par_reset2_in;
  logic par_reset2_write_en;
  logic par_reset2_clk;
  logic par_reset2_out;
  logic par_reset2_done;
  logic par_done_reg6_in;
  logic par_done_reg6_write_en;
  logic par_done_reg6_clk;
  logic par_done_reg6_out;
  logic par_done_reg6_done;
  logic par_done_reg7_in;
  logic par_done_reg7_write_en;
  logic par_done_reg7_clk;
  logic par_done_reg7_out;
  logic par_done_reg7_done;
  logic par_reset3_in;
  logic par_reset3_write_en;
  logic par_reset3_clk;
  logic par_reset3_out;
  logic par_reset3_done;
  logic par_done_reg8_in;
  logic par_done_reg8_write_en;
  logic par_done_reg8_clk;
  logic par_done_reg8_out;
  logic par_done_reg8_done;
  logic par_done_reg9_in;
  logic par_done_reg9_write_en;
  logic par_done_reg9_clk;
  logic par_done_reg9_out;
  logic par_done_reg9_done;
  logic par_done_reg10_in;
  logic par_done_reg10_write_en;
  logic par_done_reg10_clk;
  logic par_done_reg10_out;
  logic par_done_reg10_done;
  logic par_done_reg11_in;
  logic par_done_reg11_write_en;
  logic par_done_reg11_clk;
  logic par_done_reg11_out;
  logic par_done_reg11_done;
  logic par_done_reg12_in;
  logic par_done_reg12_write_en;
  logic par_done_reg12_clk;
  logic par_done_reg12_out;
  logic par_done_reg12_done;
  logic par_reset4_in;
  logic par_reset4_write_en;
  logic par_reset4_clk;
  logic par_reset4_out;
  logic par_reset4_done;
  logic par_done_reg13_in;
  logic par_done_reg13_write_en;
  logic par_done_reg13_clk;
  logic par_done_reg13_out;
  logic par_done_reg13_done;
  logic par_done_reg14_in;
  logic par_done_reg14_write_en;
  logic par_done_reg14_clk;
  logic par_done_reg14_out;
  logic par_done_reg14_done;
  logic par_done_reg15_in;
  logic par_done_reg15_write_en;
  logic par_done_reg15_clk;
  logic par_done_reg15_out;
  logic par_done_reg15_done;
  logic par_done_reg16_in;
  logic par_done_reg16_write_en;
  logic par_done_reg16_clk;
  logic par_done_reg16_out;
  logic par_done_reg16_done;
  logic par_done_reg17_in;
  logic par_done_reg17_write_en;
  logic par_done_reg17_clk;
  logic par_done_reg17_out;
  logic par_done_reg17_done;
  logic par_done_reg18_in;
  logic par_done_reg18_write_en;
  logic par_done_reg18_clk;
  logic par_done_reg18_out;
  logic par_done_reg18_done;
  logic par_reset5_in;
  logic par_reset5_write_en;
  logic par_reset5_clk;
  logic par_reset5_out;
  logic par_reset5_done;
  logic par_done_reg19_in;
  logic par_done_reg19_write_en;
  logic par_done_reg19_clk;
  logic par_done_reg19_out;
  logic par_done_reg19_done;
  logic par_done_reg20_in;
  logic par_done_reg20_write_en;
  logic par_done_reg20_clk;
  logic par_done_reg20_out;
  logic par_done_reg20_done;
  logic par_done_reg21_in;
  logic par_done_reg21_write_en;
  logic par_done_reg21_clk;
  logic par_done_reg21_out;
  logic par_done_reg21_done;
  logic par_done_reg22_in;
  logic par_done_reg22_write_en;
  logic par_done_reg22_clk;
  logic par_done_reg22_out;
  logic par_done_reg22_done;
  logic par_done_reg23_in;
  logic par_done_reg23_write_en;
  logic par_done_reg23_clk;
  logic par_done_reg23_out;
  logic par_done_reg23_done;
  logic par_done_reg24_in;
  logic par_done_reg24_write_en;
  logic par_done_reg24_clk;
  logic par_done_reg24_out;
  logic par_done_reg24_done;
  logic par_done_reg25_in;
  logic par_done_reg25_write_en;
  logic par_done_reg25_clk;
  logic par_done_reg25_out;
  logic par_done_reg25_done;
  logic par_reset6_in;
  logic par_reset6_write_en;
  logic par_reset6_clk;
  logic par_reset6_out;
  logic par_reset6_done;
  logic par_done_reg26_in;
  logic par_done_reg26_write_en;
  logic par_done_reg26_clk;
  logic par_done_reg26_out;
  logic par_done_reg26_done;
  logic par_done_reg27_in;
  logic par_done_reg27_write_en;
  logic par_done_reg27_clk;
  logic par_done_reg27_out;
  logic par_done_reg27_done;
  logic par_done_reg28_in;
  logic par_done_reg28_write_en;
  logic par_done_reg28_clk;
  logic par_done_reg28_out;
  logic par_done_reg28_done;
  logic par_done_reg29_in;
  logic par_done_reg29_write_en;
  logic par_done_reg29_clk;
  logic par_done_reg29_out;
  logic par_done_reg29_done;
  logic par_done_reg30_in;
  logic par_done_reg30_write_en;
  logic par_done_reg30_clk;
  logic par_done_reg30_out;
  logic par_done_reg30_done;
  logic par_done_reg31_in;
  logic par_done_reg31_write_en;
  logic par_done_reg31_clk;
  logic par_done_reg31_out;
  logic par_done_reg31_done;
  logic par_done_reg32_in;
  logic par_done_reg32_write_en;
  logic par_done_reg32_clk;
  logic par_done_reg32_out;
  logic par_done_reg32_done;
  logic par_done_reg33_in;
  logic par_done_reg33_write_en;
  logic par_done_reg33_clk;
  logic par_done_reg33_out;
  logic par_done_reg33_done;
  logic par_reset7_in;
  logic par_reset7_write_en;
  logic par_reset7_clk;
  logic par_reset7_out;
  logic par_reset7_done;
  logic par_done_reg34_in;
  logic par_done_reg34_write_en;
  logic par_done_reg34_clk;
  logic par_done_reg34_out;
  logic par_done_reg34_done;
  logic par_done_reg35_in;
  logic par_done_reg35_write_en;
  logic par_done_reg35_clk;
  logic par_done_reg35_out;
  logic par_done_reg35_done;
  logic par_done_reg36_in;
  logic par_done_reg36_write_en;
  logic par_done_reg36_clk;
  logic par_done_reg36_out;
  logic par_done_reg36_done;
  logic par_done_reg37_in;
  logic par_done_reg37_write_en;
  logic par_done_reg37_clk;
  logic par_done_reg37_out;
  logic par_done_reg37_done;
  logic par_done_reg38_in;
  logic par_done_reg38_write_en;
  logic par_done_reg38_clk;
  logic par_done_reg38_out;
  logic par_done_reg38_done;
  logic par_done_reg39_in;
  logic par_done_reg39_write_en;
  logic par_done_reg39_clk;
  logic par_done_reg39_out;
  logic par_done_reg39_done;
  logic par_reset8_in;
  logic par_reset8_write_en;
  logic par_reset8_clk;
  logic par_reset8_out;
  logic par_reset8_done;
  logic par_done_reg40_in;
  logic par_done_reg40_write_en;
  logic par_done_reg40_clk;
  logic par_done_reg40_out;
  logic par_done_reg40_done;
  logic par_done_reg41_in;
  logic par_done_reg41_write_en;
  logic par_done_reg41_clk;
  logic par_done_reg41_out;
  logic par_done_reg41_done;
  logic par_done_reg42_in;
  logic par_done_reg42_write_en;
  logic par_done_reg42_clk;
  logic par_done_reg42_out;
  logic par_done_reg42_done;
  logic par_done_reg43_in;
  logic par_done_reg43_write_en;
  logic par_done_reg43_clk;
  logic par_done_reg43_out;
  logic par_done_reg43_done;
  logic par_done_reg44_in;
  logic par_done_reg44_write_en;
  logic par_done_reg44_clk;
  logic par_done_reg44_out;
  logic par_done_reg44_done;
  logic par_done_reg45_in;
  logic par_done_reg45_write_en;
  logic par_done_reg45_clk;
  logic par_done_reg45_out;
  logic par_done_reg45_done;
  logic par_reset9_in;
  logic par_reset9_write_en;
  logic par_reset9_clk;
  logic par_reset9_out;
  logic par_reset9_done;
  logic par_done_reg46_in;
  logic par_done_reg46_write_en;
  logic par_done_reg46_clk;
  logic par_done_reg46_out;
  logic par_done_reg46_done;
  logic par_done_reg47_in;
  logic par_done_reg47_write_en;
  logic par_done_reg47_clk;
  logic par_done_reg47_out;
  logic par_done_reg47_done;
  logic par_done_reg48_in;
  logic par_done_reg48_write_en;
  logic par_done_reg48_clk;
  logic par_done_reg48_out;
  logic par_done_reg48_done;
  logic par_reset10_in;
  logic par_reset10_write_en;
  logic par_reset10_clk;
  logic par_reset10_out;
  logic par_reset10_done;
  logic par_done_reg49_in;
  logic par_done_reg49_write_en;
  logic par_done_reg49_clk;
  logic par_done_reg49_out;
  logic par_done_reg49_done;
  logic par_done_reg50_in;
  logic par_done_reg50_write_en;
  logic par_done_reg50_clk;
  logic par_done_reg50_out;
  logic par_done_reg50_done;
  logic par_reset11_in;
  logic par_reset11_write_en;
  logic par_reset11_clk;
  logic par_reset11_out;
  logic par_reset11_done;
  logic par_done_reg51_in;
  logic par_done_reg51_write_en;
  logic par_done_reg51_clk;
  logic par_done_reg51_out;
  logic par_done_reg51_done;
  logic [31:0] fsm0_in;
  logic fsm0_write_en;
  logic fsm0_clk;
  logic [31:0] fsm0_out;
  logic fsm0_done;
  
  // Subcomponent Instances
  std_reg #(32) left_11_read (
      .in(left_11_read_in),
      .write_en(left_11_read_write_en),
      .clk(clk),
      .out(left_11_read_out),
      .done(left_11_read_done)
  );
  
  std_reg #(32) top_11_read (
      .in(top_11_read_in),
      .write_en(top_11_read_write_en),
      .clk(clk),
      .out(top_11_read_out),
      .done(top_11_read_done)
  );
  
  mac_pe #() pe_11 (
      .top(pe_11_top),
      .left(pe_11_left),
      .go(pe_11_go),
      .clk(clk),
      .down(pe_11_down),
      .right(pe_11_right),
      .out(pe_11_out),
      .done(pe_11_done)
  );
  
  std_reg #(32) right_10_write (
      .in(right_10_write_in),
      .write_en(right_10_write_write_en),
      .clk(clk),
      .out(right_10_write_out),
      .done(right_10_write_done)
  );
  
  std_reg #(32) left_10_read (
      .in(left_10_read_in),
      .write_en(left_10_read_write_en),
      .clk(clk),
      .out(left_10_read_out),
      .done(left_10_read_done)
  );
  
  std_reg #(32) top_10_read (
      .in(top_10_read_in),
      .write_en(top_10_read_write_en),
      .clk(clk),
      .out(top_10_read_out),
      .done(top_10_read_done)
  );
  
  mac_pe #() pe_10 (
      .top(pe_10_top),
      .left(pe_10_left),
      .go(pe_10_go),
      .clk(clk),
      .down(pe_10_down),
      .right(pe_10_right),
      .out(pe_10_out),
      .done(pe_10_done)
  );
  
  std_reg #(32) down_01_write (
      .in(down_01_write_in),
      .write_en(down_01_write_write_en),
      .clk(clk),
      .out(down_01_write_out),
      .done(down_01_write_done)
  );
  
  std_reg #(32) left_01_read (
      .in(left_01_read_in),
      .write_en(left_01_read_write_en),
      .clk(clk),
      .out(left_01_read_out),
      .done(left_01_read_done)
  );
  
  std_reg #(32) top_01_read (
      .in(top_01_read_in),
      .write_en(top_01_read_write_en),
      .clk(clk),
      .out(top_01_read_out),
      .done(top_01_read_done)
  );
  
  mac_pe #() pe_01 (
      .top(pe_01_top),
      .left(pe_01_left),
      .go(pe_01_go),
      .clk(clk),
      .down(pe_01_down),
      .right(pe_01_right),
      .out(pe_01_out),
      .done(pe_01_done)
  );
  
  std_reg #(32) down_00_write (
      .in(down_00_write_in),
      .write_en(down_00_write_write_en),
      .clk(clk),
      .out(down_00_write_out),
      .done(down_00_write_done)
  );
  
  std_reg #(32) right_00_write (
      .in(right_00_write_in),
      .write_en(right_00_write_write_en),
      .clk(clk),
      .out(right_00_write_out),
      .done(right_00_write_done)
  );
  
  std_reg #(32) left_00_read (
      .in(left_00_read_in),
      .write_en(left_00_read_write_en),
      .clk(clk),
      .out(left_00_read_out),
      .done(left_00_read_done)
  );
  
  std_reg #(32) top_00_read (
      .in(top_00_read_in),
      .write_en(top_00_read_write_en),
      .clk(clk),
      .out(top_00_read_out),
      .done(top_00_read_done)
  );
  
  mac_pe #() pe_00 (
      .top(pe_00_top),
      .left(pe_00_left),
      .go(pe_00_go),
      .clk(clk),
      .down(pe_00_down),
      .right(pe_00_right),
      .out(pe_00_out),
      .done(pe_00_done)
  );
  
  std_mem_d2 #(32, 2, 2, 2, 2) out_mem (
      .addr0(out_mem_addr0),
      .addr1(out_mem_addr1),
      .write_data(out_mem_write_data),
      .write_en(out_mem_write_en),
      .clk(clk),
      .read_data(out_mem_read_data),
      .done(out_mem_done)
  );
  
  std_mem_d1 #(32, 3, 2) l1 (
      .addr0(l1_addr0),
      .write_data(l1_write_data),
      .write_en(l1_write_en),
      .clk(clk),
      .read_data(l1_read_data),
      .done(l1_done)
  );
  
  std_add #(2) l1_add (
      .left(l1_add_left),
      .right(l1_add_right),
      .out(l1_add_out)
  );
  
  std_reg #(2) l1_idx (
      .in(l1_idx_in),
      .write_en(l1_idx_write_en),
      .clk(clk),
      .out(l1_idx_out),
      .done(l1_idx_done)
  );
  
  std_mem_d1 #(32, 3, 2) l0 (
      .addr0(l0_addr0),
      .write_data(l0_write_data),
      .write_en(l0_write_en),
      .clk(clk),
      .read_data(l0_read_data),
      .done(l0_done)
  );
  
  std_add #(2) l0_add (
      .left(l0_add_left),
      .right(l0_add_right),
      .out(l0_add_out)
  );
  
  std_reg #(2) l0_idx (
      .in(l0_idx_in),
      .write_en(l0_idx_write_en),
      .clk(clk),
      .out(l0_idx_out),
      .done(l0_idx_done)
  );
  
  std_mem_d1 #(32, 3, 2) t1 (
      .addr0(t1_addr0),
      .write_data(t1_write_data),
      .write_en(t1_write_en),
      .clk(clk),
      .read_data(t1_read_data),
      .done(t1_done)
  );
  
  std_add #(2) t1_add (
      .left(t1_add_left),
      .right(t1_add_right),
      .out(t1_add_out)
  );
  
  std_reg #(2) t1_idx (
      .in(t1_idx_in),
      .write_en(t1_idx_write_en),
      .clk(clk),
      .out(t1_idx_out),
      .done(t1_idx_done)
  );
  
  std_mem_d1 #(32, 3, 2) t0 (
      .addr0(t0_addr0),
      .write_data(t0_write_data),
      .write_en(t0_write_en),
      .clk(clk),
      .read_data(t0_read_data),
      .done(t0_done)
  );
  
  std_add #(2) t0_add (
      .left(t0_add_left),
      .right(t0_add_right),
      .out(t0_add_out)
  );
  
  std_reg #(2) t0_idx (
      .in(t0_idx_in),
      .write_en(t0_idx_write_en),
      .clk(clk),
      .out(t0_idx_out),
      .done(t0_idx_done)
  );
  
  std_reg #(1) par_reset0 (
      .in(par_reset0_in),
      .write_en(par_reset0_write_en),
      .clk(clk),
      .out(par_reset0_out),
      .done(par_reset0_done)
  );
  
  std_reg #(1) par_done_reg0 (
      .in(par_done_reg0_in),
      .write_en(par_done_reg0_write_en),
      .clk(clk),
      .out(par_done_reg0_out),
      .done(par_done_reg0_done)
  );
  
  std_reg #(1) par_done_reg1 (
      .in(par_done_reg1_in),
      .write_en(par_done_reg1_write_en),
      .clk(clk),
      .out(par_done_reg1_out),
      .done(par_done_reg1_done)
  );
  
  std_reg #(1) par_done_reg2 (
      .in(par_done_reg2_in),
      .write_en(par_done_reg2_write_en),
      .clk(clk),
      .out(par_done_reg2_out),
      .done(par_done_reg2_done)
  );
  
  std_reg #(1) par_done_reg3 (
      .in(par_done_reg3_in),
      .write_en(par_done_reg3_write_en),
      .clk(clk),
      .out(par_done_reg3_out),
      .done(par_done_reg3_done)
  );
  
  std_reg #(1) par_reset1 (
      .in(par_reset1_in),
      .write_en(par_reset1_write_en),
      .clk(clk),
      .out(par_reset1_out),
      .done(par_reset1_done)
  );
  
  std_reg #(1) par_done_reg4 (
      .in(par_done_reg4_in),
      .write_en(par_done_reg4_write_en),
      .clk(clk),
      .out(par_done_reg4_out),
      .done(par_done_reg4_done)
  );
  
  std_reg #(1) par_done_reg5 (
      .in(par_done_reg5_in),
      .write_en(par_done_reg5_write_en),
      .clk(clk),
      .out(par_done_reg5_out),
      .done(par_done_reg5_done)
  );
  
  std_reg #(1) par_reset2 (
      .in(par_reset2_in),
      .write_en(par_reset2_write_en),
      .clk(clk),
      .out(par_reset2_out),
      .done(par_reset2_done)
  );
  
  std_reg #(1) par_done_reg6 (
      .in(par_done_reg6_in),
      .write_en(par_done_reg6_write_en),
      .clk(clk),
      .out(par_done_reg6_out),
      .done(par_done_reg6_done)
  );
  
  std_reg #(1) par_done_reg7 (
      .in(par_done_reg7_in),
      .write_en(par_done_reg7_write_en),
      .clk(clk),
      .out(par_done_reg7_out),
      .done(par_done_reg7_done)
  );
  
  std_reg #(1) par_reset3 (
      .in(par_reset3_in),
      .write_en(par_reset3_write_en),
      .clk(clk),
      .out(par_reset3_out),
      .done(par_reset3_done)
  );
  
  std_reg #(1) par_done_reg8 (
      .in(par_done_reg8_in),
      .write_en(par_done_reg8_write_en),
      .clk(clk),
      .out(par_done_reg8_out),
      .done(par_done_reg8_done)
  );
  
  std_reg #(1) par_done_reg9 (
      .in(par_done_reg9_in),
      .write_en(par_done_reg9_write_en),
      .clk(clk),
      .out(par_done_reg9_out),
      .done(par_done_reg9_done)
  );
  
  std_reg #(1) par_done_reg10 (
      .in(par_done_reg10_in),
      .write_en(par_done_reg10_write_en),
      .clk(clk),
      .out(par_done_reg10_out),
      .done(par_done_reg10_done)
  );
  
  std_reg #(1) par_done_reg11 (
      .in(par_done_reg11_in),
      .write_en(par_done_reg11_write_en),
      .clk(clk),
      .out(par_done_reg11_out),
      .done(par_done_reg11_done)
  );
  
  std_reg #(1) par_done_reg12 (
      .in(par_done_reg12_in),
      .write_en(par_done_reg12_write_en),
      .clk(clk),
      .out(par_done_reg12_out),
      .done(par_done_reg12_done)
  );
  
  std_reg #(1) par_reset4 (
      .in(par_reset4_in),
      .write_en(par_reset4_write_en),
      .clk(clk),
      .out(par_reset4_out),
      .done(par_reset4_done)
  );
  
  std_reg #(1) par_done_reg13 (
      .in(par_done_reg13_in),
      .write_en(par_done_reg13_write_en),
      .clk(clk),
      .out(par_done_reg13_out),
      .done(par_done_reg13_done)
  );
  
  std_reg #(1) par_done_reg14 (
      .in(par_done_reg14_in),
      .write_en(par_done_reg14_write_en),
      .clk(clk),
      .out(par_done_reg14_out),
      .done(par_done_reg14_done)
  );
  
  std_reg #(1) par_done_reg15 (
      .in(par_done_reg15_in),
      .write_en(par_done_reg15_write_en),
      .clk(clk),
      .out(par_done_reg15_out),
      .done(par_done_reg15_done)
  );
  
  std_reg #(1) par_done_reg16 (
      .in(par_done_reg16_in),
      .write_en(par_done_reg16_write_en),
      .clk(clk),
      .out(par_done_reg16_out),
      .done(par_done_reg16_done)
  );
  
  std_reg #(1) par_done_reg17 (
      .in(par_done_reg17_in),
      .write_en(par_done_reg17_write_en),
      .clk(clk),
      .out(par_done_reg17_out),
      .done(par_done_reg17_done)
  );
  
  std_reg #(1) par_done_reg18 (
      .in(par_done_reg18_in),
      .write_en(par_done_reg18_write_en),
      .clk(clk),
      .out(par_done_reg18_out),
      .done(par_done_reg18_done)
  );
  
  std_reg #(1) par_reset5 (
      .in(par_reset5_in),
      .write_en(par_reset5_write_en),
      .clk(clk),
      .out(par_reset5_out),
      .done(par_reset5_done)
  );
  
  std_reg #(1) par_done_reg19 (
      .in(par_done_reg19_in),
      .write_en(par_done_reg19_write_en),
      .clk(clk),
      .out(par_done_reg19_out),
      .done(par_done_reg19_done)
  );
  
  std_reg #(1) par_done_reg20 (
      .in(par_done_reg20_in),
      .write_en(par_done_reg20_write_en),
      .clk(clk),
      .out(par_done_reg20_out),
      .done(par_done_reg20_done)
  );
  
  std_reg #(1) par_done_reg21 (
      .in(par_done_reg21_in),
      .write_en(par_done_reg21_write_en),
      .clk(clk),
      .out(par_done_reg21_out),
      .done(par_done_reg21_done)
  );
  
  std_reg #(1) par_done_reg22 (
      .in(par_done_reg22_in),
      .write_en(par_done_reg22_write_en),
      .clk(clk),
      .out(par_done_reg22_out),
      .done(par_done_reg22_done)
  );
  
  std_reg #(1) par_done_reg23 (
      .in(par_done_reg23_in),
      .write_en(par_done_reg23_write_en),
      .clk(clk),
      .out(par_done_reg23_out),
      .done(par_done_reg23_done)
  );
  
  std_reg #(1) par_done_reg24 (
      .in(par_done_reg24_in),
      .write_en(par_done_reg24_write_en),
      .clk(clk),
      .out(par_done_reg24_out),
      .done(par_done_reg24_done)
  );
  
  std_reg #(1) par_done_reg25 (
      .in(par_done_reg25_in),
      .write_en(par_done_reg25_write_en),
      .clk(clk),
      .out(par_done_reg25_out),
      .done(par_done_reg25_done)
  );
  
  std_reg #(1) par_reset6 (
      .in(par_reset6_in),
      .write_en(par_reset6_write_en),
      .clk(clk),
      .out(par_reset6_out),
      .done(par_reset6_done)
  );
  
  std_reg #(1) par_done_reg26 (
      .in(par_done_reg26_in),
      .write_en(par_done_reg26_write_en),
      .clk(clk),
      .out(par_done_reg26_out),
      .done(par_done_reg26_done)
  );
  
  std_reg #(1) par_done_reg27 (
      .in(par_done_reg27_in),
      .write_en(par_done_reg27_write_en),
      .clk(clk),
      .out(par_done_reg27_out),
      .done(par_done_reg27_done)
  );
  
  std_reg #(1) par_done_reg28 (
      .in(par_done_reg28_in),
      .write_en(par_done_reg28_write_en),
      .clk(clk),
      .out(par_done_reg28_out),
      .done(par_done_reg28_done)
  );
  
  std_reg #(1) par_done_reg29 (
      .in(par_done_reg29_in),
      .write_en(par_done_reg29_write_en),
      .clk(clk),
      .out(par_done_reg29_out),
      .done(par_done_reg29_done)
  );
  
  std_reg #(1) par_done_reg30 (
      .in(par_done_reg30_in),
      .write_en(par_done_reg30_write_en),
      .clk(clk),
      .out(par_done_reg30_out),
      .done(par_done_reg30_done)
  );
  
  std_reg #(1) par_done_reg31 (
      .in(par_done_reg31_in),
      .write_en(par_done_reg31_write_en),
      .clk(clk),
      .out(par_done_reg31_out),
      .done(par_done_reg31_done)
  );
  
  std_reg #(1) par_done_reg32 (
      .in(par_done_reg32_in),
      .write_en(par_done_reg32_write_en),
      .clk(clk),
      .out(par_done_reg32_out),
      .done(par_done_reg32_done)
  );
  
  std_reg #(1) par_done_reg33 (
      .in(par_done_reg33_in),
      .write_en(par_done_reg33_write_en),
      .clk(clk),
      .out(par_done_reg33_out),
      .done(par_done_reg33_done)
  );
  
  std_reg #(1) par_reset7 (
      .in(par_reset7_in),
      .write_en(par_reset7_write_en),
      .clk(clk),
      .out(par_reset7_out),
      .done(par_reset7_done)
  );
  
  std_reg #(1) par_done_reg34 (
      .in(par_done_reg34_in),
      .write_en(par_done_reg34_write_en),
      .clk(clk),
      .out(par_done_reg34_out),
      .done(par_done_reg34_done)
  );
  
  std_reg #(1) par_done_reg35 (
      .in(par_done_reg35_in),
      .write_en(par_done_reg35_write_en),
      .clk(clk),
      .out(par_done_reg35_out),
      .done(par_done_reg35_done)
  );
  
  std_reg #(1) par_done_reg36 (
      .in(par_done_reg36_in),
      .write_en(par_done_reg36_write_en),
      .clk(clk),
      .out(par_done_reg36_out),
      .done(par_done_reg36_done)
  );
  
  std_reg #(1) par_done_reg37 (
      .in(par_done_reg37_in),
      .write_en(par_done_reg37_write_en),
      .clk(clk),
      .out(par_done_reg37_out),
      .done(par_done_reg37_done)
  );
  
  std_reg #(1) par_done_reg38 (
      .in(par_done_reg38_in),
      .write_en(par_done_reg38_write_en),
      .clk(clk),
      .out(par_done_reg38_out),
      .done(par_done_reg38_done)
  );
  
  std_reg #(1) par_done_reg39 (
      .in(par_done_reg39_in),
      .write_en(par_done_reg39_write_en),
      .clk(clk),
      .out(par_done_reg39_out),
      .done(par_done_reg39_done)
  );
  
  std_reg #(1) par_reset8 (
      .in(par_reset8_in),
      .write_en(par_reset8_write_en),
      .clk(clk),
      .out(par_reset8_out),
      .done(par_reset8_done)
  );
  
  std_reg #(1) par_done_reg40 (
      .in(par_done_reg40_in),
      .write_en(par_done_reg40_write_en),
      .clk(clk),
      .out(par_done_reg40_out),
      .done(par_done_reg40_done)
  );
  
  std_reg #(1) par_done_reg41 (
      .in(par_done_reg41_in),
      .write_en(par_done_reg41_write_en),
      .clk(clk),
      .out(par_done_reg41_out),
      .done(par_done_reg41_done)
  );
  
  std_reg #(1) par_done_reg42 (
      .in(par_done_reg42_in),
      .write_en(par_done_reg42_write_en),
      .clk(clk),
      .out(par_done_reg42_out),
      .done(par_done_reg42_done)
  );
  
  std_reg #(1) par_done_reg43 (
      .in(par_done_reg43_in),
      .write_en(par_done_reg43_write_en),
      .clk(clk),
      .out(par_done_reg43_out),
      .done(par_done_reg43_done)
  );
  
  std_reg #(1) par_done_reg44 (
      .in(par_done_reg44_in),
      .write_en(par_done_reg44_write_en),
      .clk(clk),
      .out(par_done_reg44_out),
      .done(par_done_reg44_done)
  );
  
  std_reg #(1) par_done_reg45 (
      .in(par_done_reg45_in),
      .write_en(par_done_reg45_write_en),
      .clk(clk),
      .out(par_done_reg45_out),
      .done(par_done_reg45_done)
  );
  
  std_reg #(1) par_reset9 (
      .in(par_reset9_in),
      .write_en(par_reset9_write_en),
      .clk(clk),
      .out(par_reset9_out),
      .done(par_reset9_done)
  );
  
  std_reg #(1) par_done_reg46 (
      .in(par_done_reg46_in),
      .write_en(par_done_reg46_write_en),
      .clk(clk),
      .out(par_done_reg46_out),
      .done(par_done_reg46_done)
  );
  
  std_reg #(1) par_done_reg47 (
      .in(par_done_reg47_in),
      .write_en(par_done_reg47_write_en),
      .clk(clk),
      .out(par_done_reg47_out),
      .done(par_done_reg47_done)
  );
  
  std_reg #(1) par_done_reg48 (
      .in(par_done_reg48_in),
      .write_en(par_done_reg48_write_en),
      .clk(clk),
      .out(par_done_reg48_out),
      .done(par_done_reg48_done)
  );
  
  std_reg #(1) par_reset10 (
      .in(par_reset10_in),
      .write_en(par_reset10_write_en),
      .clk(clk),
      .out(par_reset10_out),
      .done(par_reset10_done)
  );
  
  std_reg #(1) par_done_reg49 (
      .in(par_done_reg49_in),
      .write_en(par_done_reg49_write_en),
      .clk(clk),
      .out(par_done_reg49_out),
      .done(par_done_reg49_done)
  );
  
  std_reg #(1) par_done_reg50 (
      .in(par_done_reg50_in),
      .write_en(par_done_reg50_write_en),
      .clk(clk),
      .out(par_done_reg50_out),
      .done(par_done_reg50_done)
  );
  
  std_reg #(1) par_reset11 (
      .in(par_reset11_in),
      .write_en(par_reset11_write_en),
      .clk(clk),
      .out(par_reset11_out),
      .done(par_reset11_done)
  );
  
  std_reg #(1) par_done_reg51 (
      .in(par_done_reg51_in),
      .write_en(par_done_reg51_write_en),
      .clk(clk),
      .out(par_done_reg51_out),
      .done(par_done_reg51_done)
  );
  
  std_reg #(32) fsm0 (
      .in(fsm0_in),
      .write_en(fsm0_write_en),
      .clk(clk),
      .out(fsm0_out),
      .done(fsm0_done)
  );
  
  // Memory initialization / finalization 
  import "DPI-C" function string futil_getenv (input string env_var);
  string DATA;
   initial begin
  DATA = futil_getenv("DATA");
      $fdisplay(2, "DATA (path to meminit files): %s", DATA);
      $readmemh({ DATA, "/out_mem.dat" }, out_mem.mem);
      $readmemh({ DATA, "/l1.dat" }, l1.mem);
      $readmemh({ DATA, "/l0.dat" }, l0.mem);
      $readmemh({ DATA, "/t1.dat" }, t1.mem);
      $readmemh({ DATA, "/t0.dat" }, t0.mem);
  end
  
   final begin
      $writememh({ DATA, "/out_mem.out" }, out_mem.mem);
      $writememh({ DATA, "/l1.out" }, l1.mem);
      $writememh({ DATA, "/l0.out" }, l0.mem);
      $writememh({ DATA, "/t1.out" }, t1.mem);
      $writememh({ DATA, "/t0.out" }, t0.mem);
  end
  
  // Input / output connections
  always_comb begin
    if ((fsm0_out == 32'd16))
      done = 1'd1;
    else 
      done = '0;
    
    if ((!(par_done_reg33_out | left_11_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg45_out | left_11_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go | !(par_done_reg50_out | left_11_read_done) & fsm0_out == 32'd10 & !par_reset10_out & go))
      left_11_read_in = right_10_write_out;
    else 
      left_11_read_in = '0;
    
    if ((!(par_done_reg33_out | left_11_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg45_out | left_11_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go | !(par_done_reg50_out | left_11_read_done) & fsm0_out == 32'd10 & !par_reset10_out & go))
      left_11_read_write_en = 1'd1;
    else 
      left_11_read_write_en = '0;
    
    if ((!(par_done_reg29_out | top_11_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg42_out | top_11_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go | !(par_done_reg49_out | top_11_read_done) & fsm0_out == 32'd10 & !par_reset10_out & go))
      top_11_read_in = down_01_write_out;
    else 
      top_11_read_in = '0;
    
    if ((!(par_done_reg29_out | top_11_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg42_out | top_11_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go | !(par_done_reg49_out | top_11_read_done) & fsm0_out == 32'd10 & !par_reset10_out & go))
      top_11_read_write_en = 1'd1;
    else 
      top_11_read_write_en = '0;
    
    if ((!(par_done_reg39_out | pe_11_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg48_out | pe_11_done) & fsm0_out == 32'd9 & !par_reset9_out & go | !(par_done_reg51_out | pe_11_done) & fsm0_out == 32'd11 & !par_reset11_out & go))
      pe_11_top = top_11_read_out;
    else 
      pe_11_top = '0;
    
    if ((!(par_done_reg39_out | pe_11_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg48_out | pe_11_done) & fsm0_out == 32'd9 & !par_reset9_out & go | !(par_done_reg51_out | pe_11_done) & fsm0_out == 32'd11 & !par_reset11_out & go))
      pe_11_left = left_11_read_out;
    else 
      pe_11_left = '0;
    
    if ((!pe_11_done & (!(par_done_reg39_out | pe_11_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg48_out | pe_11_done) & fsm0_out == 32'd9 & !par_reset9_out & go | !(par_done_reg51_out | pe_11_done) & fsm0_out == 32'd11 & !par_reset11_out & go)))
      pe_11_go = 1'd1;
    else 
      pe_11_go = '0;
    
    if ((pe_10_done & (!(par_done_reg25_out | right_10_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg38_out | right_10_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg47_out | right_10_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go)))
      right_10_write_in = pe_10_right;
    else 
      right_10_write_in = '0;
    
    if ((pe_10_done & (!(par_done_reg25_out | right_10_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg38_out | right_10_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg47_out | right_10_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go)))
      right_10_write_write_en = 1'd1;
    else 
      right_10_write_write_en = '0;
    
    if ((!(par_done_reg18_out | left_10_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg32_out | left_10_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg44_out | left_10_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      left_10_read_in = l1_read_data;
    else 
      left_10_read_in = '0;
    
    if ((!(par_done_reg18_out | left_10_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg32_out | left_10_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg44_out | left_10_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      left_10_read_write_en = 1'd1;
    else 
      left_10_read_write_en = '0;
    
    if ((!(par_done_reg15_out | top_10_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg28_out | top_10_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg41_out | top_10_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      top_10_read_in = down_00_write_out;
    else 
      top_10_read_in = '0;
    
    if ((!(par_done_reg15_out | top_10_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg28_out | top_10_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg41_out | top_10_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      top_10_read_write_en = 1'd1;
    else 
      top_10_read_write_en = '0;
    
    if ((!(par_done_reg25_out | right_10_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg38_out | right_10_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg47_out | right_10_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go))
      pe_10_top = top_10_read_out;
    else 
      pe_10_top = '0;
    
    if ((!(par_done_reg25_out | right_10_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg38_out | right_10_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg47_out | right_10_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go))
      pe_10_left = left_10_read_out;
    else 
      pe_10_left = '0;
    
    if ((!pe_10_done & (!(par_done_reg25_out | right_10_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg38_out | right_10_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg47_out | right_10_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go)))
      pe_10_go = 1'd1;
    else 
      pe_10_go = '0;
    
    if ((pe_01_done & (!(par_done_reg24_out | down_01_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg37_out | down_01_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg46_out | down_01_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go)))
      down_01_write_in = pe_01_down;
    else 
      down_01_write_in = '0;
    
    if ((pe_01_done & (!(par_done_reg24_out | down_01_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg37_out | down_01_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg46_out | down_01_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go)))
      down_01_write_write_en = 1'd1;
    else 
      down_01_write_write_en = '0;
    
    if ((!(par_done_reg17_out | left_01_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg31_out | left_01_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg43_out | left_01_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      left_01_read_in = right_00_write_out;
    else 
      left_01_read_in = '0;
    
    if ((!(par_done_reg17_out | left_01_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg31_out | left_01_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg43_out | left_01_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      left_01_read_write_en = 1'd1;
    else 
      left_01_read_write_en = '0;
    
    if ((!(par_done_reg14_out | top_01_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg27_out | top_01_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg40_out | top_01_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      top_01_read_in = t1_read_data;
    else 
      top_01_read_in = '0;
    
    if ((!(par_done_reg14_out | top_01_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg27_out | top_01_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg40_out | top_01_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      top_01_read_write_en = 1'd1;
    else 
      top_01_read_write_en = '0;
    
    if ((!(par_done_reg24_out | down_01_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg37_out | down_01_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg46_out | down_01_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go))
      pe_01_top = top_01_read_out;
    else 
      pe_01_top = '0;
    
    if ((!(par_done_reg24_out | down_01_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg37_out | down_01_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg46_out | down_01_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go))
      pe_01_left = left_01_read_out;
    else 
      pe_01_left = '0;
    
    if ((!pe_01_done & (!(par_done_reg24_out | down_01_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg37_out | down_01_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go | !(par_done_reg46_out | down_01_write_done) & fsm0_out == 32'd9 & !par_reset9_out & go)))
      pe_01_go = 1'd1;
    else 
      pe_01_go = '0;
    
    if ((pe_00_done & (!(par_done_reg12_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg23_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg36_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go)))
      down_00_write_in = pe_00_down;
    else 
      down_00_write_in = '0;
    
    if ((pe_00_done & (!(par_done_reg12_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg23_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg36_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go)))
      down_00_write_write_en = 1'd1;
    else 
      down_00_write_write_en = '0;
    
    if ((pe_00_done & (!(par_done_reg12_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg23_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg36_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go)))
      right_00_write_in = pe_00_right;
    else 
      right_00_write_in = '0;
    
    if ((pe_00_done & (!(par_done_reg12_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg23_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg36_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go)))
      right_00_write_write_en = 1'd1;
    else 
      right_00_write_write_en = '0;
    
    if ((!(par_done_reg7_out | left_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg16_out | left_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg30_out | left_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      left_00_read_in = l0_read_data;
    else 
      left_00_read_in = '0;
    
    if ((!(par_done_reg7_out | left_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg16_out | left_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg30_out | left_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      left_00_read_write_en = 1'd1;
    else 
      left_00_read_write_en = '0;
    
    if ((!(par_done_reg6_out | top_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg13_out | top_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg26_out | top_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      top_00_read_in = t0_read_data;
    else 
      top_00_read_in = '0;
    
    if ((!(par_done_reg6_out | top_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg13_out | top_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg26_out | top_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      top_00_read_write_en = 1'd1;
    else 
      top_00_read_write_en = '0;
    
    if ((!(par_done_reg12_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg23_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg36_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      pe_00_top = top_00_read_out;
    else 
      pe_00_top = '0;
    
    if ((!(par_done_reg12_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg23_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg36_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      pe_00_left = left_00_read_out;
    else 
      pe_00_left = '0;
    
    if ((!pe_00_done & (!(par_done_reg12_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg23_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg36_out | right_00_write_done & down_00_write_done) & fsm0_out == 32'd7 & !par_reset7_out & go)))
      pe_00_go = 1'd1;
    else 
      pe_00_go = '0;
    
    if ((fsm0_out == 32'd12 & !out_mem_done & go | fsm0_out == 32'd13 & !out_mem_done & go))
      out_mem_addr0 = 2'd0;
    else if ((fsm0_out == 32'd14 & !out_mem_done & go | fsm0_out == 32'd15 & !out_mem_done & go))
      out_mem_addr0 = 2'd1;
    else 
      out_mem_addr0 = '0;
    
    if ((fsm0_out == 32'd12 & !out_mem_done & go | fsm0_out == 32'd14 & !out_mem_done & go))
      out_mem_addr1 = 2'd0;
    else if ((fsm0_out == 32'd13 & !out_mem_done & go | fsm0_out == 32'd15 & !out_mem_done & go))
      out_mem_addr1 = 2'd1;
    else 
      out_mem_addr1 = '0;
    
    if ((fsm0_out == 32'd15 & !out_mem_done & go))
      out_mem_write_data = pe_11_out;
    else if ((fsm0_out == 32'd14 & !out_mem_done & go))
      out_mem_write_data = pe_10_out;
    else if ((fsm0_out == 32'd13 & !out_mem_done & go))
      out_mem_write_data = pe_01_out;
    else if ((fsm0_out == 32'd12 & !out_mem_done & go))
      out_mem_write_data = pe_00_out;
    else 
      out_mem_write_data = '0;
    
    if ((fsm0_out == 32'd12 & !out_mem_done & go | fsm0_out == 32'd13 & !out_mem_done & go | fsm0_out == 32'd14 & !out_mem_done & go | fsm0_out == 32'd15 & !out_mem_done & go))
      out_mem_write_en = 1'd1;
    else 
      out_mem_write_en = '0;
    
    if ((!(par_done_reg18_out | left_10_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg32_out | left_10_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg44_out | left_10_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      l1_addr0 = l1_idx_out;
    else 
      l1_addr0 = '0;
    
    if ((!(par_done_reg11_out | l1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg22_out | l1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg35_out | l1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      l1_add_left = 2'd1;
    else 
      l1_add_left = '0;
    
    if ((!(par_done_reg11_out | l1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg22_out | l1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg35_out | l1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      l1_add_right = l1_idx_out;
    else 
      l1_add_right = '0;
    
    if ((!(par_done_reg11_out | l1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg22_out | l1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg35_out | l1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      l1_idx_in = l1_add_out;
    else if ((!(par_done_reg3_out | l1_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go))
      l1_idx_in = 2'd3;
    else 
      l1_idx_in = '0;
    
    if ((!(par_done_reg3_out | l1_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go | !(par_done_reg11_out | l1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg22_out | l1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg35_out | l1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      l1_idx_write_en = 1'd1;
    else 
      l1_idx_write_en = '0;
    
    if ((!(par_done_reg7_out | left_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg16_out | left_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg30_out | left_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      l0_addr0 = l0_idx_out;
    else 
      l0_addr0 = '0;
    
    if ((!(par_done_reg5_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg9_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg20_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_add_left = 2'd1;
    else 
      l0_add_left = '0;
    
    if ((!(par_done_reg5_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg9_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg20_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_add_right = l0_idx_out;
    else 
      l0_add_right = '0;
    
    if ((!(par_done_reg5_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg9_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg20_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_idx_in = l0_add_out;
    else if ((!(par_done_reg2_out | l0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go))
      l0_idx_in = 2'd3;
    else 
      l0_idx_in = '0;
    
    if ((!(par_done_reg2_out | l0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go | !(par_done_reg5_out | l0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg9_out | l0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg20_out | l0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      l0_idx_write_en = 1'd1;
    else 
      l0_idx_write_en = '0;
    
    if ((!(par_done_reg14_out | top_01_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg27_out | top_01_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go | !(par_done_reg40_out | top_01_read_done) & fsm0_out == 32'd8 & !par_reset8_out & go))
      t1_addr0 = t1_idx_out;
    else 
      t1_addr0 = '0;
    
    if ((!(par_done_reg10_out | t1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg21_out | t1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg34_out | t1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      t1_add_left = 2'd1;
    else 
      t1_add_left = '0;
    
    if ((!(par_done_reg10_out | t1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg21_out | t1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg34_out | t1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      t1_add_right = t1_idx_out;
    else 
      t1_add_right = '0;
    
    if ((!(par_done_reg10_out | t1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg21_out | t1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg34_out | t1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      t1_idx_in = t1_add_out;
    else if ((!(par_done_reg1_out | t1_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go))
      t1_idx_in = 2'd3;
    else 
      t1_idx_in = '0;
    
    if ((!(par_done_reg1_out | t1_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go | !(par_done_reg10_out | t1_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg21_out | t1_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go | !(par_done_reg34_out | t1_idx_done) & fsm0_out == 32'd7 & !par_reset7_out & go))
      t1_idx_write_en = 1'd1;
    else 
      t1_idx_write_en = '0;
    
    if ((!(par_done_reg6_out | top_00_read_done) & fsm0_out == 32'd2 & !par_reset2_out & go | !(par_done_reg13_out | top_00_read_done) & fsm0_out == 32'd4 & !par_reset4_out & go | !(par_done_reg26_out | top_00_read_done) & fsm0_out == 32'd6 & !par_reset6_out & go))
      t0_addr0 = t0_idx_out;
    else 
      t0_addr0 = '0;
    
    if ((!(par_done_reg4_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg8_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg19_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_add_left = 2'd1;
    else 
      t0_add_left = '0;
    
    if ((!(par_done_reg4_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg8_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg19_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_add_right = t0_idx_out;
    else 
      t0_add_right = '0;
    
    if ((!(par_done_reg4_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg8_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg19_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_idx_in = t0_add_out;
    else if ((!(par_done_reg0_out | t0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go))
      t0_idx_in = 2'd3;
    else 
      t0_idx_in = '0;
    
    if ((!(par_done_reg0_out | t0_idx_done) & fsm0_out == 32'd0 & !par_reset0_out & go | !(par_done_reg4_out | t0_idx_done) & fsm0_out == 32'd1 & !par_reset1_out & go | !(par_done_reg8_out | t0_idx_done) & fsm0_out == 32'd3 & !par_reset3_out & go | !(par_done_reg19_out | t0_idx_done) & fsm0_out == 32'd5 & !par_reset5_out & go))
      t0_idx_write_en = 1'd1;
    else 
      t0_idx_write_en = '0;
    
    if (par_reset0_out)
      par_reset0_in = 1'd0;
    else if ((par_done_reg0_out & par_done_reg1_out & par_done_reg2_out & par_done_reg3_out & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_reset0_in = 1'd1;
    else 
      par_reset0_in = '0;
    
    if ((par_done_reg0_out & par_done_reg1_out & par_done_reg2_out & par_done_reg3_out & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_reset0_write_en = 1'd1;
    else 
      par_reset0_write_en = '0;
    
    if (par_reset0_out)
      par_done_reg0_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_done_reg0_in = 1'd1;
    else 
      par_done_reg0_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_done_reg0_write_en = 1'd1;
    else 
      par_done_reg0_write_en = '0;
    
    if (par_reset0_out)
      par_done_reg1_in = 1'd0;
    else if ((t1_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_done_reg1_in = 1'd1;
    else 
      par_done_reg1_in = '0;
    
    if ((t1_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_done_reg1_write_en = 1'd1;
    else 
      par_done_reg1_write_en = '0;
    
    if (par_reset0_out)
      par_done_reg2_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_done_reg2_in = 1'd1;
    else 
      par_done_reg2_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_done_reg2_write_en = 1'd1;
    else 
      par_done_reg2_write_en = '0;
    
    if (par_reset0_out)
      par_done_reg3_in = 1'd0;
    else if ((l1_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go))
      par_done_reg3_in = 1'd1;
    else 
      par_done_reg3_in = '0;
    
    if ((l1_idx_done & fsm0_out == 32'd0 & !par_reset0_out & go | par_reset0_out))
      par_done_reg3_write_en = 1'd1;
    else 
      par_done_reg3_write_en = '0;
    
    if (par_reset1_out)
      par_reset1_in = 1'd0;
    else if ((par_done_reg4_out & par_done_reg5_out & fsm0_out == 32'd1 & !par_reset1_out & go))
      par_reset1_in = 1'd1;
    else 
      par_reset1_in = '0;
    
    if ((par_done_reg4_out & par_done_reg5_out & fsm0_out == 32'd1 & !par_reset1_out & go | par_reset1_out))
      par_reset1_write_en = 1'd1;
    else 
      par_reset1_write_en = '0;
    
    if (par_reset1_out)
      par_done_reg4_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go))
      par_done_reg4_in = 1'd1;
    else 
      par_done_reg4_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go | par_reset1_out))
      par_done_reg4_write_en = 1'd1;
    else 
      par_done_reg4_write_en = '0;
    
    if (par_reset1_out)
      par_done_reg5_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go))
      par_done_reg5_in = 1'd1;
    else 
      par_done_reg5_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd1 & !par_reset1_out & go | par_reset1_out))
      par_done_reg5_write_en = 1'd1;
    else 
      par_done_reg5_write_en = '0;
    
    if (par_reset2_out)
      par_reset2_in = 1'd0;
    else if ((par_done_reg6_out & par_done_reg7_out & fsm0_out == 32'd2 & !par_reset2_out & go))
      par_reset2_in = 1'd1;
    else 
      par_reset2_in = '0;
    
    if ((par_done_reg6_out & par_done_reg7_out & fsm0_out == 32'd2 & !par_reset2_out & go | par_reset2_out))
      par_reset2_write_en = 1'd1;
    else 
      par_reset2_write_en = '0;
    
    if (par_reset2_out)
      par_done_reg6_in = 1'd0;
    else if ((top_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go))
      par_done_reg6_in = 1'd1;
    else 
      par_done_reg6_in = '0;
    
    if ((top_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go | par_reset2_out))
      par_done_reg6_write_en = 1'd1;
    else 
      par_done_reg6_write_en = '0;
    
    if (par_reset2_out)
      par_done_reg7_in = 1'd0;
    else if ((left_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go))
      par_done_reg7_in = 1'd1;
    else 
      par_done_reg7_in = '0;
    
    if ((left_00_read_done & fsm0_out == 32'd2 & !par_reset2_out & go | par_reset2_out))
      par_done_reg7_write_en = 1'd1;
    else 
      par_done_reg7_write_en = '0;
    
    if (par_reset3_out)
      par_reset3_in = 1'd0;
    else if ((par_done_reg8_out & par_done_reg9_out & par_done_reg10_out & par_done_reg11_out & par_done_reg12_out & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_reset3_in = 1'd1;
    else 
      par_reset3_in = '0;
    
    if ((par_done_reg8_out & par_done_reg9_out & par_done_reg10_out & par_done_reg11_out & par_done_reg12_out & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_reset3_write_en = 1'd1;
    else 
      par_reset3_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg8_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg8_in = 1'd1;
    else 
      par_done_reg8_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg8_write_en = 1'd1;
    else 
      par_done_reg8_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg9_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg9_in = 1'd1;
    else 
      par_done_reg9_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg9_write_en = 1'd1;
    else 
      par_done_reg9_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg10_in = 1'd0;
    else if ((t1_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg10_in = 1'd1;
    else 
      par_done_reg10_in = '0;
    
    if ((t1_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg10_write_en = 1'd1;
    else 
      par_done_reg10_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg11_in = 1'd0;
    else if ((l1_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg11_in = 1'd1;
    else 
      par_done_reg11_in = '0;
    
    if ((l1_idx_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg11_write_en = 1'd1;
    else 
      par_done_reg11_write_en = '0;
    
    if (par_reset3_out)
      par_done_reg12_in = 1'd0;
    else if ((right_00_write_done & down_00_write_done & fsm0_out == 32'd3 & !par_reset3_out & go))
      par_done_reg12_in = 1'd1;
    else 
      par_done_reg12_in = '0;
    
    if ((right_00_write_done & down_00_write_done & fsm0_out == 32'd3 & !par_reset3_out & go | par_reset3_out))
      par_done_reg12_write_en = 1'd1;
    else 
      par_done_reg12_write_en = '0;
    
    if (par_reset4_out)
      par_reset4_in = 1'd0;
    else if ((par_done_reg13_out & par_done_reg14_out & par_done_reg15_out & par_done_reg16_out & par_done_reg17_out & par_done_reg18_out & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_reset4_in = 1'd1;
    else 
      par_reset4_in = '0;
    
    if ((par_done_reg13_out & par_done_reg14_out & par_done_reg15_out & par_done_reg16_out & par_done_reg17_out & par_done_reg18_out & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_reset4_write_en = 1'd1;
    else 
      par_reset4_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg13_in = 1'd0;
    else if ((top_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg13_in = 1'd1;
    else 
      par_done_reg13_in = '0;
    
    if ((top_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg13_write_en = 1'd1;
    else 
      par_done_reg13_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg14_in = 1'd0;
    else if ((top_01_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg14_in = 1'd1;
    else 
      par_done_reg14_in = '0;
    
    if ((top_01_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg14_write_en = 1'd1;
    else 
      par_done_reg14_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg15_in = 1'd0;
    else if ((top_10_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg15_in = 1'd1;
    else 
      par_done_reg15_in = '0;
    
    if ((top_10_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg15_write_en = 1'd1;
    else 
      par_done_reg15_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg16_in = 1'd0;
    else if ((left_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg16_in = 1'd1;
    else 
      par_done_reg16_in = '0;
    
    if ((left_00_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg16_write_en = 1'd1;
    else 
      par_done_reg16_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg17_in = 1'd0;
    else if ((left_01_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg17_in = 1'd1;
    else 
      par_done_reg17_in = '0;
    
    if ((left_01_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg17_write_en = 1'd1;
    else 
      par_done_reg17_write_en = '0;
    
    if (par_reset4_out)
      par_done_reg18_in = 1'd0;
    else if ((left_10_read_done & fsm0_out == 32'd4 & !par_reset4_out & go))
      par_done_reg18_in = 1'd1;
    else 
      par_done_reg18_in = '0;
    
    if ((left_10_read_done & fsm0_out == 32'd4 & !par_reset4_out & go | par_reset4_out))
      par_done_reg18_write_en = 1'd1;
    else 
      par_done_reg18_write_en = '0;
    
    if (par_reset5_out)
      par_reset5_in = 1'd0;
    else if ((par_done_reg19_out & par_done_reg20_out & par_done_reg21_out & par_done_reg22_out & par_done_reg23_out & par_done_reg24_out & par_done_reg25_out & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_reset5_in = 1'd1;
    else 
      par_reset5_in = '0;
    
    if ((par_done_reg19_out & par_done_reg20_out & par_done_reg21_out & par_done_reg22_out & par_done_reg23_out & par_done_reg24_out & par_done_reg25_out & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_reset5_write_en = 1'd1;
    else 
      par_reset5_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg19_in = 1'd0;
    else if ((t0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg19_in = 1'd1;
    else 
      par_done_reg19_in = '0;
    
    if ((t0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg19_write_en = 1'd1;
    else 
      par_done_reg19_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg20_in = 1'd0;
    else if ((l0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg20_in = 1'd1;
    else 
      par_done_reg20_in = '0;
    
    if ((l0_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg20_write_en = 1'd1;
    else 
      par_done_reg20_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg21_in = 1'd0;
    else if ((t1_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg21_in = 1'd1;
    else 
      par_done_reg21_in = '0;
    
    if ((t1_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg21_write_en = 1'd1;
    else 
      par_done_reg21_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg22_in = 1'd0;
    else if ((l1_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg22_in = 1'd1;
    else 
      par_done_reg22_in = '0;
    
    if ((l1_idx_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg22_write_en = 1'd1;
    else 
      par_done_reg22_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg23_in = 1'd0;
    else if ((right_00_write_done & down_00_write_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg23_in = 1'd1;
    else 
      par_done_reg23_in = '0;
    
    if ((right_00_write_done & down_00_write_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg23_write_en = 1'd1;
    else 
      par_done_reg23_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg24_in = 1'd0;
    else if ((down_01_write_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg24_in = 1'd1;
    else 
      par_done_reg24_in = '0;
    
    if ((down_01_write_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg24_write_en = 1'd1;
    else 
      par_done_reg24_write_en = '0;
    
    if (par_reset5_out)
      par_done_reg25_in = 1'd0;
    else if ((right_10_write_done & fsm0_out == 32'd5 & !par_reset5_out & go))
      par_done_reg25_in = 1'd1;
    else 
      par_done_reg25_in = '0;
    
    if ((right_10_write_done & fsm0_out == 32'd5 & !par_reset5_out & go | par_reset5_out))
      par_done_reg25_write_en = 1'd1;
    else 
      par_done_reg25_write_en = '0;
    
    if (par_reset6_out)
      par_reset6_in = 1'd0;
    else if ((par_done_reg26_out & par_done_reg27_out & par_done_reg28_out & par_done_reg29_out & par_done_reg30_out & par_done_reg31_out & par_done_reg32_out & par_done_reg33_out & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_reset6_in = 1'd1;
    else 
      par_reset6_in = '0;
    
    if ((par_done_reg26_out & par_done_reg27_out & par_done_reg28_out & par_done_reg29_out & par_done_reg30_out & par_done_reg31_out & par_done_reg32_out & par_done_reg33_out & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_reset6_write_en = 1'd1;
    else 
      par_reset6_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg26_in = 1'd0;
    else if ((top_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg26_in = 1'd1;
    else 
      par_done_reg26_in = '0;
    
    if ((top_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg26_write_en = 1'd1;
    else 
      par_done_reg26_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg27_in = 1'd0;
    else if ((top_01_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg27_in = 1'd1;
    else 
      par_done_reg27_in = '0;
    
    if ((top_01_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg27_write_en = 1'd1;
    else 
      par_done_reg27_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg28_in = 1'd0;
    else if ((top_10_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg28_in = 1'd1;
    else 
      par_done_reg28_in = '0;
    
    if ((top_10_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg28_write_en = 1'd1;
    else 
      par_done_reg28_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg29_in = 1'd0;
    else if ((top_11_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg29_in = 1'd1;
    else 
      par_done_reg29_in = '0;
    
    if ((top_11_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg29_write_en = 1'd1;
    else 
      par_done_reg29_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg30_in = 1'd0;
    else if ((left_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg30_in = 1'd1;
    else 
      par_done_reg30_in = '0;
    
    if ((left_00_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg30_write_en = 1'd1;
    else 
      par_done_reg30_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg31_in = 1'd0;
    else if ((left_01_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg31_in = 1'd1;
    else 
      par_done_reg31_in = '0;
    
    if ((left_01_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg31_write_en = 1'd1;
    else 
      par_done_reg31_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg32_in = 1'd0;
    else if ((left_10_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg32_in = 1'd1;
    else 
      par_done_reg32_in = '0;
    
    if ((left_10_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg32_write_en = 1'd1;
    else 
      par_done_reg32_write_en = '0;
    
    if (par_reset6_out)
      par_done_reg33_in = 1'd0;
    else if ((left_11_read_done & fsm0_out == 32'd6 & !par_reset6_out & go))
      par_done_reg33_in = 1'd1;
    else 
      par_done_reg33_in = '0;
    
    if ((left_11_read_done & fsm0_out == 32'd6 & !par_reset6_out & go | par_reset6_out))
      par_done_reg33_write_en = 1'd1;
    else 
      par_done_reg33_write_en = '0;
    
    if (par_reset7_out)
      par_reset7_in = 1'd0;
    else if ((par_done_reg34_out & par_done_reg35_out & par_done_reg36_out & par_done_reg37_out & par_done_reg38_out & par_done_reg39_out & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_reset7_in = 1'd1;
    else 
      par_reset7_in = '0;
    
    if ((par_done_reg34_out & par_done_reg35_out & par_done_reg36_out & par_done_reg37_out & par_done_reg38_out & par_done_reg39_out & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_reset7_write_en = 1'd1;
    else 
      par_reset7_write_en = '0;
    
    if (par_reset7_out)
      par_done_reg34_in = 1'd0;
    else if ((t1_idx_done & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_done_reg34_in = 1'd1;
    else 
      par_done_reg34_in = '0;
    
    if ((t1_idx_done & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_done_reg34_write_en = 1'd1;
    else 
      par_done_reg34_write_en = '0;
    
    if (par_reset7_out)
      par_done_reg35_in = 1'd0;
    else if ((l1_idx_done & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_done_reg35_in = 1'd1;
    else 
      par_done_reg35_in = '0;
    
    if ((l1_idx_done & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_done_reg35_write_en = 1'd1;
    else 
      par_done_reg35_write_en = '0;
    
    if (par_reset7_out)
      par_done_reg36_in = 1'd0;
    else if ((right_00_write_done & down_00_write_done & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_done_reg36_in = 1'd1;
    else 
      par_done_reg36_in = '0;
    
    if ((right_00_write_done & down_00_write_done & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_done_reg36_write_en = 1'd1;
    else 
      par_done_reg36_write_en = '0;
    
    if (par_reset7_out)
      par_done_reg37_in = 1'd0;
    else if ((down_01_write_done & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_done_reg37_in = 1'd1;
    else 
      par_done_reg37_in = '0;
    
    if ((down_01_write_done & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_done_reg37_write_en = 1'd1;
    else 
      par_done_reg37_write_en = '0;
    
    if (par_reset7_out)
      par_done_reg38_in = 1'd0;
    else if ((right_10_write_done & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_done_reg38_in = 1'd1;
    else 
      par_done_reg38_in = '0;
    
    if ((right_10_write_done & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_done_reg38_write_en = 1'd1;
    else 
      par_done_reg38_write_en = '0;
    
    if (par_reset7_out)
      par_done_reg39_in = 1'd0;
    else if ((pe_11_done & fsm0_out == 32'd7 & !par_reset7_out & go))
      par_done_reg39_in = 1'd1;
    else 
      par_done_reg39_in = '0;
    
    if ((pe_11_done & fsm0_out == 32'd7 & !par_reset7_out & go | par_reset7_out))
      par_done_reg39_write_en = 1'd1;
    else 
      par_done_reg39_write_en = '0;
    
    if (par_reset8_out)
      par_reset8_in = 1'd0;
    else if ((par_done_reg40_out & par_done_reg41_out & par_done_reg42_out & par_done_reg43_out & par_done_reg44_out & par_done_reg45_out & fsm0_out == 32'd8 & !par_reset8_out & go))
      par_reset8_in = 1'd1;
    else 
      par_reset8_in = '0;
    
    if ((par_done_reg40_out & par_done_reg41_out & par_done_reg42_out & par_done_reg43_out & par_done_reg44_out & par_done_reg45_out & fsm0_out == 32'd8 & !par_reset8_out & go | par_reset8_out))
      par_reset8_write_en = 1'd1;
    else 
      par_reset8_write_en = '0;
    
    if (par_reset8_out)
      par_done_reg40_in = 1'd0;
    else if ((top_01_read_done & fsm0_out == 32'd8 & !par_reset8_out & go))
      par_done_reg40_in = 1'd1;
    else 
      par_done_reg40_in = '0;
    
    if ((top_01_read_done & fsm0_out == 32'd8 & !par_reset8_out & go | par_reset8_out))
      par_done_reg40_write_en = 1'd1;
    else 
      par_done_reg40_write_en = '0;
    
    if (par_reset8_out)
      par_done_reg41_in = 1'd0;
    else if ((top_10_read_done & fsm0_out == 32'd8 & !par_reset8_out & go))
      par_done_reg41_in = 1'd1;
    else 
      par_done_reg41_in = '0;
    
    if ((top_10_read_done & fsm0_out == 32'd8 & !par_reset8_out & go | par_reset8_out))
      par_done_reg41_write_en = 1'd1;
    else 
      par_done_reg41_write_en = '0;
    
    if (par_reset8_out)
      par_done_reg42_in = 1'd0;
    else if ((top_11_read_done & fsm0_out == 32'd8 & !par_reset8_out & go))
      par_done_reg42_in = 1'd1;
    else 
      par_done_reg42_in = '0;
    
    if ((top_11_read_done & fsm0_out == 32'd8 & !par_reset8_out & go | par_reset8_out))
      par_done_reg42_write_en = 1'd1;
    else 
      par_done_reg42_write_en = '0;
    
    if (par_reset8_out)
      par_done_reg43_in = 1'd0;
    else if ((left_01_read_done & fsm0_out == 32'd8 & !par_reset8_out & go))
      par_done_reg43_in = 1'd1;
    else 
      par_done_reg43_in = '0;
    
    if ((left_01_read_done & fsm0_out == 32'd8 & !par_reset8_out & go | par_reset8_out))
      par_done_reg43_write_en = 1'd1;
    else 
      par_done_reg43_write_en = '0;
    
    if (par_reset8_out)
      par_done_reg44_in = 1'd0;
    else if ((left_10_read_done & fsm0_out == 32'd8 & !par_reset8_out & go))
      par_done_reg44_in = 1'd1;
    else 
      par_done_reg44_in = '0;
    
    if ((left_10_read_done & fsm0_out == 32'd8 & !par_reset8_out & go | par_reset8_out))
      par_done_reg44_write_en = 1'd1;
    else 
      par_done_reg44_write_en = '0;
    
    if (par_reset8_out)
      par_done_reg45_in = 1'd0;
    else if ((left_11_read_done & fsm0_out == 32'd8 & !par_reset8_out & go))
      par_done_reg45_in = 1'd1;
    else 
      par_done_reg45_in = '0;
    
    if ((left_11_read_done & fsm0_out == 32'd8 & !par_reset8_out & go | par_reset8_out))
      par_done_reg45_write_en = 1'd1;
    else 
      par_done_reg45_write_en = '0;
    
    if (par_reset9_out)
      par_reset9_in = 1'd0;
    else if ((par_done_reg46_out & par_done_reg47_out & par_done_reg48_out & fsm0_out == 32'd9 & !par_reset9_out & go))
      par_reset9_in = 1'd1;
    else 
      par_reset9_in = '0;
    
    if ((par_done_reg46_out & par_done_reg47_out & par_done_reg48_out & fsm0_out == 32'd9 & !par_reset9_out & go | par_reset9_out))
      par_reset9_write_en = 1'd1;
    else 
      par_reset9_write_en = '0;
    
    if (par_reset9_out)
      par_done_reg46_in = 1'd0;
    else if ((down_01_write_done & fsm0_out == 32'd9 & !par_reset9_out & go))
      par_done_reg46_in = 1'd1;
    else 
      par_done_reg46_in = '0;
    
    if ((down_01_write_done & fsm0_out == 32'd9 & !par_reset9_out & go | par_reset9_out))
      par_done_reg46_write_en = 1'd1;
    else 
      par_done_reg46_write_en = '0;
    
    if (par_reset9_out)
      par_done_reg47_in = 1'd0;
    else if ((right_10_write_done & fsm0_out == 32'd9 & !par_reset9_out & go))
      par_done_reg47_in = 1'd1;
    else 
      par_done_reg47_in = '0;
    
    if ((right_10_write_done & fsm0_out == 32'd9 & !par_reset9_out & go | par_reset9_out))
      par_done_reg47_write_en = 1'd1;
    else 
      par_done_reg47_write_en = '0;
    
    if (par_reset9_out)
      par_done_reg48_in = 1'd0;
    else if ((pe_11_done & fsm0_out == 32'd9 & !par_reset9_out & go))
      par_done_reg48_in = 1'd1;
    else 
      par_done_reg48_in = '0;
    
    if ((pe_11_done & fsm0_out == 32'd9 & !par_reset9_out & go | par_reset9_out))
      par_done_reg48_write_en = 1'd1;
    else 
      par_done_reg48_write_en = '0;
    
    if (par_reset10_out)
      par_reset10_in = 1'd0;
    else if ((par_done_reg49_out & par_done_reg50_out & fsm0_out == 32'd10 & !par_reset10_out & go))
      par_reset10_in = 1'd1;
    else 
      par_reset10_in = '0;
    
    if ((par_done_reg49_out & par_done_reg50_out & fsm0_out == 32'd10 & !par_reset10_out & go | par_reset10_out))
      par_reset10_write_en = 1'd1;
    else 
      par_reset10_write_en = '0;
    
    if (par_reset10_out)
      par_done_reg49_in = 1'd0;
    else if ((top_11_read_done & fsm0_out == 32'd10 & !par_reset10_out & go))
      par_done_reg49_in = 1'd1;
    else 
      par_done_reg49_in = '0;
    
    if ((top_11_read_done & fsm0_out == 32'd10 & !par_reset10_out & go | par_reset10_out))
      par_done_reg49_write_en = 1'd1;
    else 
      par_done_reg49_write_en = '0;
    
    if (par_reset10_out)
      par_done_reg50_in = 1'd0;
    else if ((left_11_read_done & fsm0_out == 32'd10 & !par_reset10_out & go))
      par_done_reg50_in = 1'd1;
    else 
      par_done_reg50_in = '0;
    
    if ((left_11_read_done & fsm0_out == 32'd10 & !par_reset10_out & go | par_reset10_out))
      par_done_reg50_write_en = 1'd1;
    else 
      par_done_reg50_write_en = '0;
    
    if (par_reset11_out)
      par_reset11_in = 1'd0;
    else if ((par_done_reg51_out & fsm0_out == 32'd11 & !par_reset11_out & go))
      par_reset11_in = 1'd1;
    else 
      par_reset11_in = '0;
    
    if ((par_done_reg51_out & fsm0_out == 32'd11 & !par_reset11_out & go | par_reset11_out))
      par_reset11_write_en = 1'd1;
    else 
      par_reset11_write_en = '0;
    
    if (par_reset11_out)
      par_done_reg51_in = 1'd0;
    else if ((pe_11_done & fsm0_out == 32'd11 & !par_reset11_out & go))
      par_done_reg51_in = 1'd1;
    else 
      par_done_reg51_in = '0;
    
    if ((pe_11_done & fsm0_out == 32'd11 & !par_reset11_out & go | par_reset11_out))
      par_done_reg51_write_en = 1'd1;
    else 
      par_done_reg51_write_en = '0;
    
    if ((fsm0_out == 32'd3 & par_reset3_out & go))
      fsm0_in = 32'd4;
    else if ((fsm0_out == 32'd2 & par_reset2_out & go))
      fsm0_in = 32'd3;
    else if ((fsm0_out == 32'd1 & par_reset1_out & go))
      fsm0_in = 32'd2;
    else if ((fsm0_out == 32'd0 & par_reset0_out & go))
      fsm0_in = 32'd1;
    else if ((fsm0_out == 32'd16))
      fsm0_in = 32'd0;
    else if ((fsm0_out == 32'd15 & out_mem_done & go))
      fsm0_in = 32'd16;
    else if ((fsm0_out == 32'd14 & out_mem_done & go))
      fsm0_in = 32'd15;
    else if ((fsm0_out == 32'd13 & out_mem_done & go))
      fsm0_in = 32'd14;
    else if ((fsm0_out == 32'd12 & out_mem_done & go))
      fsm0_in = 32'd13;
    else if ((fsm0_out == 32'd11 & par_reset11_out & go))
      fsm0_in = 32'd12;
    else if ((fsm0_out == 32'd10 & par_reset10_out & go))
      fsm0_in = 32'd11;
    else if ((fsm0_out == 32'd9 & par_reset9_out & go))
      fsm0_in = 32'd10;
    else if ((fsm0_out == 32'd8 & par_reset8_out & go))
      fsm0_in = 32'd9;
    else if ((fsm0_out == 32'd7 & par_reset7_out & go))
      fsm0_in = 32'd8;
    else if ((fsm0_out == 32'd6 & par_reset6_out & go))
      fsm0_in = 32'd7;
    else if ((fsm0_out == 32'd5 & par_reset5_out & go))
      fsm0_in = 32'd6;
    else if ((fsm0_out == 32'd4 & par_reset4_out & go))
      fsm0_in = 32'd5;
    else 
      fsm0_in = '0;
    
    if ((fsm0_out == 32'd0 & par_reset0_out & go | fsm0_out == 32'd1 & par_reset1_out & go | fsm0_out == 32'd2 & par_reset2_out & go | fsm0_out == 32'd3 & par_reset3_out & go | fsm0_out == 32'd4 & par_reset4_out & go | fsm0_out == 32'd5 & par_reset5_out & go | fsm0_out == 32'd6 & par_reset6_out & go | fsm0_out == 32'd7 & par_reset7_out & go | fsm0_out == 32'd8 & par_reset8_out & go | fsm0_out == 32'd9 & par_reset9_out & go | fsm0_out == 32'd10 & par_reset10_out & go | fsm0_out == 32'd11 & par_reset11_out & go | fsm0_out == 32'd12 & out_mem_done & go | fsm0_out == 32'd13 & out_mem_done & go | fsm0_out == 32'd14 & out_mem_done & go | fsm0_out == 32'd15 & out_mem_done & go | fsm0_out == 32'd16))
      fsm0_write_en = 1'd1;
    else 
      fsm0_write_en = '0;
    
  end
endmodule // end main