// -d dead-cell-removal -b verilog
import "primitives/core.futil";
component main() -> () {
  cells {
    m0 = std_mem_d1(32, 4, 4);
    @external(1) m1 = std_mem_d1(32, 4, 4);
  }
  wires {
    done = m1.done;
  }
  control {}
}