import "primitives/core.futil"; component main() -> () { cells { @external(1) i = std_mem_d1(32, 1, 1); lt = std_lt(32); add = std_add(32); } wires { group cond<"static"=0> { i.addr0 = 1'd0; lt.left = i.read_data; lt.right = 32'd8; cond[done] = 1'b1; } group incr<"static"=1> { i.write_data = add.out; i.addr0 = 1'd0; i.write_en = 1'b1; add.right = i.read_data; add.left = 32'd1; incr[done] = i.done; } } control { while lt.out with cond { incr; } } }