import "primitives/std.lib";
component main() -> () {
  cells {
    add0 = std_add(32);
    const0 = std_const(32,0);
    const1 = std_const(32,7);
    const2 = std_const(32,1);
    i0 = std_reg(32);
    le0 = std_le(32);
  }
  wires {
    group cond0<"static"=0> {
      cond0[done] = 1'd1;
      le0.left = i0.out;
      le0.right = const1.out;
    }
    group let0<"static"=1> {
      i0.in = const0.out;
      i0.write_en = 1'd1;
      let0[done] = i0.done;
    }
    group upd0<"static"=1> {
      i0.write_en = 1'd1;
      add0.left = i0.out;
      add0.right = const2.out;
      i0.in = 1'd1 ? add0.out;
      upd0[done] = i0.done ? 1'd1;
    }
  }
  control {
    seq {
      let0;
      @bound(8) while le0.out with cond0 {
        upd0;
      }
    }
  }
}