import "primitives/std.lib";
component main() -> () {
  cells {
    @external(1) a0_00_0 = std_mem_d2(16,2,2,2,2);
    a0_0_read0_0 = std_reg(16);
    add0 = std_fp_add(16,8,8);
    add1 = std_add(2);
    add2 = std_add(2);
    @external(1) b0_00_0 = std_mem_d2(16,2,2,2,2);
    b0_0_read0_0 = std_reg(16);
    const0 = std_const(2,0);
    const1 = std_const(2,1);
    const2 = std_const(2,0);
    const3 = std_const(2,1);
    const4 = std_const(2,1);
    const5 = std_const(2,1);
    i0 = std_reg(2);
    j0 = std_reg(2);
    le0 = std_le(2);
    le1 = std_le(2);
    @external(1) result0_00_0 = std_mem_d2(16,2,2,2,2);
  }
  wires {
    group cond0<"static"=0> {
      cond0[done] = 1'd1;
      le0.left = i0.out;
      le0.right = const1.out;
    }
    group cond1<"static"=0> {
      cond1[done] = 1'd1;
      le1.left = j0.out;
      le1.right = const3.out;
    }
    group let0<"static"=1> {
      i0.in = const0.out;
      i0.write_en = 1'd1;
      let0[done] = i0.done;
    }
    group let1<"static"=1> {
      j0.in = const2.out;
      j0.write_en = 1'd1;
      let1[done] = j0.done;
    }
    group upd0<"static"=1> {
      a0_0_read0_0.write_en = 1'd1;
      a0_00_0.addr1 = j0.out;
      a0_00_0.addr0 = i0.out;
      a0_0_read0_0.in = 1'd1 ? a0_00_0.read_data;
      upd0[done] = a0_0_read0_0.done ? 1'd1;
    }
    group upd1<"static"=1> {
      b0_0_read0_0.write_en = 1'd1;
      b0_00_0.addr1 = j0.out;
      b0_00_0.addr0 = i0.out;
      b0_0_read0_0.in = 1'd1 ? b0_00_0.read_data;
      upd1[done] = b0_0_read0_0.done ? 1'd1;
    }
    group upd2<"static"=1> {
      result0_00_0.addr1 = j0.out;
      result0_00_0.addr0 = i0.out;
      result0_00_0.write_en = 1'd1;
      add0.left = a0_0_read0_0.out;
      add0.right = b0_0_read0_0.out;
      result0_00_0.write_data = 1'd1 ? add0.out;
      upd2[done] = result0_00_0.done ? 1'd1;
    }
    group upd3<"static"=1> {
      j0.write_en = 1'd1;
      add1.left = j0.out;
      add1.right = const4.out;
      j0.in = 1'd1 ? add1.out;
      upd3[done] = j0.done ? 1'd1;
    }
    group upd4<"static"=1> {
      i0.write_en = 1'd1;
      add2.left = i0.out;
      add2.right = const5.out;
      i0.in = 1'd1 ? add2.out;
      upd4[done] = i0.done ? 1'd1;
    }
  }
  control {
    seq {
      let0;
      @bound(2) while le0.out with cond0 {
        seq {
          let1;
          @bound(2) while le1.out with cond1 {
            seq {
              par {
                upd0;
                upd1;
              }
              upd2;
              upd3;
            }
          }
          upd4;
        }
      }
    }
  }
}