import "primitives/std.lib"; import "primitives/math.futil"; component main() -> () { cells { @external(1) x = std_mem_d3(32, 1, 2, 2, 1, 2, 2); @external(1) x1 = std_mem_d2(32, 1, 4, 1, 3); batch_flatten_1x4_ = batch_flatten_1x4(); } wires { } control { seq { invoke batch_flatten_1x4_(x0_0_0_read_data=x.read_data, x10_0_done=x1.done, x10_0_read_data=x1.read_data)(x0_0_0_addr0=x.addr0, x0_0_0_addr1=x.addr1, x0_0_0_addr2=x.addr2, x10_0_write_data=x1.write_data, x10_0_write_en=x1.write_en, x10_0_addr0=x1.addr0, x10_0_addr1=x1.addr1); } } } component batch_flatten_1x4(x0_0_0_read_data: 32, x0_0_0_done: 1, x10_0_read_data: 32, x10_0_done: 1) -> (x0_0_0_write_data: 32, x0_0_0_write_en: 1, x0_0_0_addr0: 1, x0_0_0_addr1: 2, x0_0_0_addr2: 2, x10_0_write_data: 32, x10_0_write_en: 1, x10_0_addr0: 1, x10_0_addr1: 3) { cells { __i0 = std_reg(1); __j0 = std_reg(2); __k0 = std_reg(2); __l_0 = std_reg(3); add0 = std_add(3); add1 = std_add(2); add2 = std_add(2); add3 = std_add(1); const0 = std_const(3,0); const1 = std_const(1,0); const10 = std_const(1,1); const2 = std_const(1,0); const3 = std_const(2,0); const4 = std_const(2,1); const5 = std_const(2,0); const6 = std_const(2,1); const7 = std_const(3,1); const8 = std_const(2,1); const9 = std_const(2,1); le0 = std_le(1); le1 = std_le(2); le2 = std_le(2); x_read0_0 = std_reg(32); } wires { group cond0<"static"=0> { cond0[done] = 1'd1; le0.left = __i0.out; le0.right = const2.out; } group cond1<"static"=0> { cond1[done] = 1'd1; le1.left = __j0.out; le1.right = const4.out; } group cond2<"static"=0> { cond2[done] = 1'd1; le2.left = __k0.out; le2.right = const6.out; } group let0<"static"=1> { __l_0.in = const0.out; __l_0.write_en = 1'd1; let0[done] = __l_0.done; } group let1<"static"=1> { __i0.in = const1.out; __i0.write_en = 1'd1; let1[done] = __i0.done; } group let2<"static"=1> { __j0.in = const3.out; __j0.write_en = 1'd1; let2[done] = __j0.done; } group let3<"static"=1> { __k0.in = const5.out; __k0.write_en = 1'd1; let3[done] = __k0.done; } group upd0<"static"=1> { x_read0_0.write_en = 1'd1; x0_0_0_addr2 = __k0.out; x0_0_0_addr1 = __j0.out; x0_0_0_addr0 = __i0.out; x_read0_0.in = 1'd1 ? x0_0_0_read_data; upd0[done] = x_read0_0.done ? 1'd1; } group upd1<"static"=1> { x10_0_addr1 = __l_0.out; x10_0_addr0 = __i0.out; x10_0_write_en = 1'd1; x10_0_write_data = 1'd1 ? x_read0_0.out; upd1[done] = x10_0_done ? 1'd1; } group upd2<"static"=1> { __l_0.write_en = 1'd1; add0.left = __l_0.out; add0.right = const7.out; __l_0.in = 1'd1 ? add0.out; upd2[done] = __l_0.done ? 1'd1; } group upd3<"static"=1> { __k0.write_en = 1'd1; add1.left = __k0.out; add1.right = const8.out; __k0.in = 1'd1 ? add1.out; upd3[done] = __k0.done ? 1'd1; } group upd4<"static"=1> { __j0.write_en = 1'd1; add2.left = __j0.out; add2.right = const9.out; __j0.in = 1'd1 ? add2.out; upd4[done] = __j0.done ? 1'd1; } group upd5<"static"=1> { __i0.write_en = 1'd1; add3.left = __i0.out; add3.right = const10.out; __i0.in = 1'd1 ? add3.out; upd5[done] = __i0.done ? 1'd1; } } control { seq { let0; let1; @bound(1) while le0.out with cond0 { seq { let2; @bound(2) while le1.out with cond1 { seq { let3; @bound(2) while le2.out with cond2 { seq { upd0; upd1; upd2; upd3; } } upd4; } } upd5; } } } } }