import "primitives/std.lib";
import "primitives/math.futil";
component main() -> () {
  cells {
    @external(1) x = std_mem_d2(32, 1, 4096, 1, 13);
    @external(1) y = std_mem_d2(32, 10, 4096, 4, 13);
    @external(1) x1 = std_mem_d2(32, 1, 10, 1, 4);
    dense_1x10_ = dense_1x10();
  }
  wires {

  }
  control {
    seq {
      invoke dense_1x10_(x0_0_read_data=x.read_data, y0_0_read_data=y.read_data, x10_0_done=x1.done, x10_0_read_data=x1.read_data)(x0_0_addr0=x.addr0, x0_0_addr1=x.addr1, y0_0_addr0=y.addr0, y0_0_addr1=y.addr1, x10_0_write_data=x1.write_data, x10_0_write_en=x1.write_en, x10_0_addr0=x1.addr0, x10_0_addr1=x1.addr1);
    }
  }
}
component dense_1x10(x0_0_read_data: 32, x0_0_done: 1, y0_0_read_data: 32, y0_0_done: 1, x10_0_read_data: 32, x10_0_done: 1) -> (x0_0_write_data: 32, x0_0_write_en: 1, x0_0_addr0: 1, x0_0_addr1: 13, y0_0_write_data: 32, y0_0_write_en: 1, y0_0_addr0: 4, y0_0_addr1: 13, x10_0_write_data: 32, x10_0_write_en: 1, x10_0_addr0: 1, x10_0_addr1: 4) {
  cells {
    __i0 = std_reg(4);
    __i1 = std_reg(1);
    __j0 = std_reg(13);
    __j1 = std_reg(4);
    __k0 = std_reg(13);
    __product_0 = std_reg(32);
    __transpose_y0_0 = std_mem_d2(32,4096,10,13,4);
    __transpose_y_read0_0 = std_reg(32);
    add0 = std_add(13);
    add1 = std_add(4);
    add2 = std_sadd(32);
    add3 = std_add(13);
    add4 = std_add(4);
    add5 = std_add(1);
    bin_read0_0 = std_reg(32);
    const0 = std_const(4,0);
    const1 = std_const(4,9);
    const10 = std_const(13,0);
    const11 = std_const(13,4095);
    const12 = std_const(13,1);
    const13 = std_const(4,1);
    const14 = std_const(1,1);
    const2 = std_const(13,0);
    const3 = std_const(13,4095);
    const4 = std_const(13,1);
    const5 = std_const(4,1);
    const6 = std_const(1,0);
    const7 = std_const(1,0);
    const8 = std_const(4,0);
    const9 = std_const(4,9);
    le0 = std_le(4);
    le1 = std_le(13);
    le2 = std_le(1);
    le3 = std_le(4);
    le4 = std_le(13);
    mult_pipe0 = std_smult_pipe(32);
    red_read00 = std_reg(32);
    x_read0_0 = std_reg(32);
    y_read0_0 = std_reg(32);
  }
  wires {
    group cond0<"static"=0> {
      cond0[done] = 1'd1;
      le0.left = __i0.out;
      le0.right = const1.out;
    }
    group cond1<"static"=0> {
      cond1[done] = 1'd1;
      le1.left = __j0.out;
      le1.right = const3.out;
    }
    group cond2<"static"=0> {
      cond2[done] = 1'd1;
      le2.left = __i1.out;
      le2.right = const7.out;
    }
    group cond3<"static"=0> {
      cond3[done] = 1'd1;
      le3.left = __j1.out;
      le3.right = const9.out;
    }
    group cond4<"static"=0> {
      cond4[done] = 1'd1;
      le4.left = __k0.out;
      le4.right = const11.out;
    }
    group let0<"static"=1> {
      __i0.in = const0.out;
      __i0.write_en = 1'd1;
      let0[done] = __i0.done;
    }
    group let1<"static"=1> {
      __j0.in = const2.out;
      __j0.write_en = 1'd1;
      let1[done] = __j0.done;
    }
    group let2<"static"=1> {
      __i1.in = const6.out;
      __i1.write_en = 1'd1;
      let2[done] = __i1.done;
    }
    group let3<"static"=1> {
      __j1.in = const8.out;
      __j1.write_en = 1'd1;
      let3[done] = __j1.done;
    }
    group let4<"static"=1> {
      __k0.in = const10.out;
      __k0.write_en = 1'd1;
      let4[done] = __k0.done;
    }
    group let5<"static"=4> {
      bin_read0_0.in = mult_pipe0.out;
      bin_read0_0.write_en = mult_pipe0.done;
      let5[done] = bin_read0_0.done;
      mult_pipe0.left = x_read0_0.out;
      mult_pipe0.right = __transpose_y_read0_0.out;
      mult_pipe0.go = !mult_pipe0.done ? 1'd1;
    }
    group let6<"static"=1> {
      __product_0.in = bin_read0_0.out;
      __product_0.write_en = 1'd1;
      let6[done] = __product_0.done;
    }
    group let7<"static"=1> {
      red_read00.in = x10_0_read_data;
      red_read00.write_en = 1'd1;
      let7[done] = red_read00.done;
      x10_0_addr1 = __j1.out;
      x10_0_addr0 = __i1.out;
    }
    group upd0<"static"=1> {
      y_read0_0.write_en = 1'd1;
      y0_0_addr1 = __j0.out;
      y0_0_addr0 = __i0.out;
      y_read0_0.in = 1'd1 ? y0_0_read_data;
      upd0[done] = y_read0_0.done ? 1'd1;
    }
    group upd1<"static"=1> {
      __transpose_y0_0.addr1 = __i0.out;
      __transpose_y0_0.addr0 = __j0.out;
      __transpose_y0_0.write_en = 1'd1;
      __transpose_y0_0.write_data = 1'd1 ? y_read0_0.out;
      upd1[done] = __transpose_y0_0.done ? 1'd1;
    }
    group upd2<"static"=1> {
      __j0.write_en = 1'd1;
      add0.left = __j0.out;
      add0.right = const4.out;
      __j0.in = 1'd1 ? add0.out;
      upd2[done] = __j0.done ? 1'd1;
    }
    group upd3<"static"=1> {
      __i0.write_en = 1'd1;
      add1.left = __i0.out;
      add1.right = const5.out;
      __i0.in = 1'd1 ? add1.out;
      upd3[done] = __i0.done ? 1'd1;
    }
    group upd4<"static"=1> {
      x_read0_0.write_en = 1'd1;
      x0_0_addr1 = __k0.out;
      x0_0_addr0 = __i1.out;
      x_read0_0.in = 1'd1 ? x0_0_read_data;
      upd4[done] = x_read0_0.done ? 1'd1;
    }
    group upd5<"static"=1> {
      __transpose_y_read0_0.write_en = 1'd1;
      __transpose_y0_0.addr1 = __j1.out;
      __transpose_y0_0.addr0 = __k0.out;
      __transpose_y_read0_0.in = 1'd1 ? __transpose_y0_0.read_data;
      upd5[done] = __transpose_y_read0_0.done ? 1'd1;
    }
    group upd6<"static"=1> {
      x10_0_addr1 = __j1.out;
      x10_0_addr0 = __i1.out;
      x10_0_write_en = 1'd1;
      add2.left = red_read00.out;
      add2.right = __product_0.out;
      x10_0_write_data = 1'd1 ? add2.out;
      upd6[done] = x10_0_done ? 1'd1;
    }
    group upd7<"static"=1> {
      __k0.write_en = 1'd1;
      add3.left = __k0.out;
      add3.right = const12.out;
      __k0.in = 1'd1 ? add3.out;
      upd7[done] = __k0.done ? 1'd1;
    }
    group upd8<"static"=1> {
      __j1.write_en = 1'd1;
      add4.left = __j1.out;
      add4.right = const13.out;
      __j1.in = 1'd1 ? add4.out;
      upd8[done] = __j1.done ? 1'd1;
    }
    group upd9<"static"=1> {
      __i1.write_en = 1'd1;
      add5.left = __i1.out;
      add5.right = const14.out;
      __i1.in = 1'd1 ? add5.out;
      upd9[done] = __i1.done ? 1'd1;
    }
  }
  control {
    seq {
      let0;
      @bound(10) while le0.out with cond0 {
        seq {
          let1;
          @bound(4096) while le1.out with cond1 {
            seq {
              upd0;
              upd1;
              upd2;
            }
          }
          upd3;
        }
      }
      let2;
      @bound(1) while le2.out with cond2 {
        seq {
          let3;
          @bound(10) while le3.out with cond3 {
            seq {
              let4;
              @bound(4096) while le4.out with cond4 {
                seq {
                  par {
                    upd4;
                    upd5;
                  }
                  let5;
                  let6;
                  let7;
                  upd6;
                  upd7;
                }
              }
              upd8;
            }
          }
          upd9;
        }
      }
    }
  }
}