import "primitives/std.lib";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    t = std_reg(1);
    f = std_reg(1);
    lt = std_lt(1);
    @generated comb_reg = std_reg(1);
    @generated fsm = std_reg(2);
    @generated cond_stored = std_reg(1);
    @generated incr = std_add(2);
  }
  wires {
    group true<"static"=1> {
      t.in = 1'd1;
      t.write_en = 1'd1;
      true[done] = t.done;
    }
    group false<"static"=1> {
      f.in = 1'd1;
      f.write_en = 1'd1;
      false[done] = f.done;
    }
    group cond<"static"=1> {
      lt.left = 1'd1;
      lt.right = 1'd0;
      cond[done] = comb_reg.done ? 1'd1;
      comb_reg.in = lt.out;
      comb_reg.write_en = 1'd1;
    }
    group static_if<"static"=3> {
      incr.left = fsm.out;
      incr.right = 2'd1;
      fsm.in = fsm.out != 2'd3 ? incr.out;
      fsm.write_en = fsm.out != 2'd3 ? 1'd1;
      cond[go] = fsm.out < 2'd1 ? 1'd1;
      cond_stored.write_en = fsm.out == 2'd1 ? 1'd1;
      true[go] = fsm.out > 2'd1 & fsm.out < 2'd3 & cond_stored.out ? 1'd1;
      false[go] = fsm.out > 2'd1 & fsm.out < 2'd3 & !cond_stored.out ? 1'd1;
      static_if[done] = fsm.out == 2'd3 ? 1'd1;
      cond_stored.in = fsm.out == 2'd1 ? comb_reg.out;
    }
    fsm.in = fsm.out == 2'd3 ? 2'd0;
    fsm.write_en = fsm.out == 2'd3 ? 1'd1;
  }

  control {
    static_if;
  }
}