import "primitives/std.lib";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    t = std_reg(1);
    f = std_reg(1);
    lt = std_lt(1);
    @generated cond_computed = std_reg(1);
    @generated cond_stored = std_reg(1);
    @generated done_reg = std_reg(1);
  }
  wires {
    group true {
      t.in = 1'd1;
      t.write_en = 1'd1;
      true[done] = t.done;
    }
    group false {
      f.in = 1'd1;
      f.write_en = 1'd1;
      false[done] = f.done;
    }
    group cond {
      lt.left = 1'd1;
      lt.right = 1'd0;
      cond[done] = 1'd1;
    }
    group if {
      cond_stored.in = cond[go] & cond[done] ? lt.out;
      cond_stored.write_en = cond[go] & cond[done] ? lt.out;
      cond[go] = !cond_computed.out ? 1'd1;
      cond_computed.in = cond[go] & cond[done] ? 1'd1;
      cond_computed.write_en = cond[go] & cond[done] ? 1'd1;
      true[go] = !true[done] & cond_computed.out & cond_stored.out ? 1'd1;
      false[go] = !false[done] & cond_computed.out & !cond_stored.out ? 1'd1;
      done_reg.in = cond_computed.out & cond_stored.out & true[done] | cond_computed.out & !cond_stored.out & false[done] ? 1'd1;
      done_reg.write_en = cond_computed.out & cond_stored.out & true[done] | cond_computed.out & !cond_stored.out & false[done] ? 1'd1;
      if[done] = done_reg.out ? 1'd1;
    }
    done_reg.in = done_reg.out ? 1'd0;
    done_reg.write_en = done_reg.out ? 1'd1;
    cond_computed.in = done_reg.out ? 1'd0;
    cond_computed.write_en = done_reg.out ? 1'd1;
    cond_stored.in = done_reg.out ? 1'd0;
    cond_stored.write_en = done_reg.out ? 1'd1;
  }

  control {
    if;
  }
}