import "primitives/std.lib";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    add = std_add(32);
    add_r = std_reg(32);
    lt = std_lt(32);
    lt_r = std_reg(1);
    @generated fsm = std_reg(2);
    @generated cond_stored = std_reg(1);
    @generated incr = std_add(2);
  }
  wires {
    group do_add<"static"=1> {
      add.right = 32'd4;
      add.left = 32'd4;
      add_r.in = add.out;
      add_r.write_en = 1'd1;
      do_add[done] = add_r.done;
    }
    group cond<"static"=1> {
      lt.right = 32'd5;
      lt.left = 32'd1;
      lt_r.in = lt.out;
      lt_r.write_en = 1'd1;
      cond[done] = lt_r.out;
    }
    group static_while {
      incr.left = fsm.out;
      incr.right = 2'd1;
      fsm.in = fsm.out < 2'd2 | fsm.out >= 2'd2 & fsm.out < 2'd3 & cond_stored.out ? incr.out;
      fsm.write_en = fsm.out < 2'd2 | fsm.out >= 2'd2 & fsm.out < 2'd3 & cond_stored.out ? 1'd1;
      cond[go] = fsm.out < 2'd1 ? 1'd1;
      cond_stored.write_en = fsm.out == 2'd1 ? 1'd1;
      do_add[go] = cond_stored.out & fsm.out >= 2'd2 & fsm.out < 2'd3 ? 1'd1;
      fsm.in = fsm.out == 2'd3 ? 2'd0;
      fsm.write_en = fsm.out == 2'd3 ? 1'd1;
      static_while[done] = fsm.out == 2'd2 & !cond_stored.out ? 1'd1;
      cond_stored.in = fsm.out == 2'd1 ? lt_r.out;
    }
    fsm.in = fsm.out == 2'd2 & !cond_stored.out ? 2'd0;
    fsm.write_en = fsm.out == 2'd2 & !cond_stored.out ? 1'd1;
  }

  control {
    static_while;
  }
}