// -p remove-comb-groups -p static-timing

import "primitives/std.lib";

component main() -> () {
  cells {
    add = std_add(32);
    add_r = std_reg(32); // to make body not combinational

    lt = std_lt(32);
    lt_r = std_reg(1); // to make body not combinational
  }

  wires {
    group do_add<"static"=1> {
      add.right = 32'd4;
      add.left = 32'd4;
      add_r.in = add.out;
      add_r.write_en = 1'b1;
      do_add[done] = add_r.done;
    }

    group cond<"static"=1> {
      lt.right = 32'd5;
      lt.left = 32'd1;
      lt_r.in = lt.out;
      lt_r.write_en = 1'b1;
      cond[done] = lt_r.out;
    }

  }

  control {
    while lt_r.out with cond {
      do_add;
    }
  }
}