import "primitives/std.lib";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    add = std_add(32);
    lt = std_lt(32);
    @generated cond_computed = std_reg(1);
    @generated cond_stored = std_reg(1);
    @generated done_reg = std_reg(1);
  }
  wires {
    group do_add {
      add.right = 32'd4;
      add.left = 32'd4;
      do_add[done] = 1'd1;
    }
    group cond {
      lt.right = 32'd5;
      lt.left = 32'd1;
      cond[done] = 1'd1;
    }
    group while {
      cond_stored.in = cond[go] & cond[done] ? lt.out;
      cond[go] = !cond_computed.out ? 1'd1;
      cond_computed.in = cond[go] & cond[done] ? 1'd1;
      cond_computed.write_en = cond[go] & cond[done] ? 1'd1;
      cond_stored.write_en = cond[go] & cond[done] ? 1'd1;
      do_add[go] = cond_stored.out & cond_computed.out & !do_add[done] ? 1'd1;
      cond_computed.in = cond_stored.out & cond_computed.out & do_add[done] ? 1'd0;
      cond_computed.write_en = cond_stored.out & cond_computed.out & do_add[done] ? 1'd1;
      done_reg.in = cond_computed.out & !cond_stored.out ? 1'd1;
      done_reg.write_en = cond_computed.out & !cond_stored.out ? 1'd1;
      while[done] = done_reg.out ? 1'd1;
      cond_computed.in = cond_computed.out & !cond_stored.out ? 1'd0;
      cond_computed.write_en = cond_computed.out & !cond_stored.out ? 1'd1;
    }
    done_reg.in = done_reg.out ? 1'd0;
    done_reg.write_en = done_reg.out ? 1'd1;
  }

  control {
    while;
  }
}