component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
  }
  wires {
    group A {
      A[done] = 1'd1;
    }
    A[go] = go;
    done = A[done] ? 1'd1;
  }

  control {
    A;
  }
}