import "primitives/std.lib";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    r1 = std_reg(32);
    r2 = std_reg(32);
    fsm = std_reg(1);
  }
  wires {
    r1.in = fsm.out == 1'd0 & go ? 32'd1;
    r1.write_en = fsm.out == 1'd0 & go ? 1'd1;
    r2.in = fsm.out == 1'd1 & go ? r1.out;
    r2.write_en = fsm.out == 1'd1 & go ? 1'd1;
    fsm.in = r1.done & go ? 1'd1;
    done = r2.done ? 1'd1;
  }

  control {}
}