import "primitives/std.lib";
component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    r = std_reg(32);
    add = std_add(32);
    @generated fsm = std_reg(2);
  }
  wires {
    done = fsm.out == 2'd2 ? 1'd1;
    add.left = !r.done & go & (fsm.out == 2'd1 | fsm.out == 2'd0) ? 32'd1;
    add.right = !r.done & go & (fsm.out == 2'd1 | fsm.out == 2'd0) ? r.out;
    fsm.clk = clk;
    fsm.in = fsm.out == 2'd2 ? 2'd0;
    fsm.in = fsm.out == 2'd0 & r.done & go ? 2'd1;
    fsm.in = fsm.out == 2'd1 & r.done & go ? 2'd2;
    fsm.reset = reset;
    fsm.write_en = fsm.out == 2'd2 | r.done & go & fsm.out == 2'd1 | fsm.out == 2'd0 & r.done & go ? 1'd1;
    r.clk = clk;
    r.in = !r.done & go & (fsm.out == 2'd1 | fsm.out == 2'd0) ? add.out;
    r.write_en = !r.done & go & (fsm.out == 2'd1 | fsm.out == 2'd0) ? 1'd1;
  }

  control {}
}