import "primitives/core.futil";
component main(in: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
  cells {
    e0 = std_eq(32);
    e1 = std_eq(32);
    e2 = std_eq(32);
    e3 = std_eq(32);
    r = std_reg(32);
    @generated comb_reg = std_reg(1);
    @generated comb_reg0 = std_reg(1);
    @generated comb_reg1 = std_reg(1);
    @generated comb_reg2 = std_reg(1);
  }
  wires {
    group find_index<"static"=1> {
      e0.left = in;
      e0.right = 32'd1;
      e1.left = in;
      e1.right = 32'd1;
      e2.left = in;
      e2.right = 32'd2;
      e3.left = in;
      e3.right = 32'd3;
      find_index[done] = comb_reg.done & comb_reg0.done & comb_reg1.done & comb_reg2.done ? 1'd1;
      comb_reg.in = e0.out;
      comb_reg.write_en = 1'd1;
      comb_reg0.in = e1.out;
      comb_reg0.write_en = 1'd1;
      comb_reg1.in = e2.out;
      comb_reg1.write_en = 1'd1;
      comb_reg2.in = e3.out;
      comb_reg2.write_en = 1'd1;
    }
    group write {
      r.write_en = 1'd1;
      r.in = 32'd1;
      write[done] = r.done;
    }
  }

  control {
    par {
      if comb_reg.out with find_index {
        write;
      }
      if comb_reg0.out with find_index {
        write;
      }
      if comb_reg1.out with find_index {
        write;
      }
      if comb_reg2.out with find_index {
        write;
      }
    }
  }
}