import "primitives/std.lib";
component main(go: 1, clk: 1) -> (done: 1) {
  cells {
    mem = std_mem_d2(32, 8, 8, 4, 4);
    rsh0 = std_rsh(4);
    rsh1 = std_rsh(4);
  }
  wires {
    group upd1<"static"=1> {
      rsh0.left = 4'd1;
      rsh0.right = 4'd0;
      rsh1.left = 4'd1;
      rsh1.right = 4'd0;
      mem.addr1 = rsh0.out;
      mem.addr0 = rsh1.out;
      upd1[done] = mem.done;
    }
  }

  control {
    upd1;
  }
}