{
  "modules": {
    "Top": {
      "ports": {
        "a": {
          "direction": "input",
          "bits": [ 2, 3, 4, 5, 6, 7, 8, 9 ]
        },
        "b": {
          "direction": "input",
          "bits": [ 10, 11, 12, 13, 14, 15, 16, 17 ]
        },
        "o": {
          "direction": "output",
          "bits": [ 18, 19, 20, 21, 22, 23, 24, 25 ]
        }
      },
      "cells": {
        "and_gate": {
          "type": "$and",
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 2, 3, 4, 5, 6, 7, 8, 9 ],
            "B": [ 10, 11, 12, 13, 14, 15, 16, 17 ],
            "Y": [ 18, 19, 20, 21, 22, 23, 24, 25 ]
          }
        }
      }
    }
  }
}