module Stack2 (
    input clk,
    output [16:0] rd,
    input we,
    input [2:0] delta,
    input [16:0] wd
);
    localparam WIDTH = 16;
    localparam DEPTH = 18;
    localparam BITS = (WIDTH * DEPTH);
    reg [(1)-1:0] do_move;
    always @(*) do_move = delta[0];
    reg [(1)-1:0] move_dir;
    always @(*) move_dir = delta[1];
    reg [(16)-1:0] head;
    reg [(288)-1:0] tail;
    reg [(16)-1:0] headN;
    always @(*) begin
        headN = (we ? wd : tail[(16)-1:0]);
    end
    reg [(288)-1:0] tailN;
    always @(*) begin
        tailN = (move_dir ? {21930, tail[(BITS)-1:16]} : {tail[((BITS - 16))-1:0], head});
    end
    always @(posedge clk) begin
        if ((we | do_move)) begin
            head <= headN;
        end
        if (do_move) begin
            tail <= tailN;
        end
    end
    always @(*) begin
        rd = head;
    end
endmodule

module J1a (
    input clk,
    input reset,
    output [13:0] code_addr,
    input [16:0] insn,
    output LED1
);
    localparam WIDTH = 16;
    reg [(4)-1:0] dsp;
    reg [(4)-1:0] dspN;
    reg [(16)-1:0] st0;
    reg [(16)-1:0] st0N;
    reg [(1)-1:0] dstkW;
    reg [(13)-1:0] pc;
    reg [(13)-1:0] pcN;
    reg [(13)-1:0] pc_plus_1;
    always @(*) pc_plus_1 = (pc + 1);
    reg [(1)-1:0] reboot;
    always @(*) begin
        code_addr = pcN;
    end
    reg [(16)-1:0] st1;
    reg [(2)-1:0] dspI;
    Stack2 dstack(.clk (clk),
        .rd (st1),
        .we (dstkW),
        .wd (st0),
        .delta (dspI));
    reg [(17)-1:0] minus;
    always @(*) minus = (({1, !(st0)} + st1) + 1);
    always @(*) begin
        if ((insn[15] == 0)) begin
            st0N = insn;
            dstkW = 1;
            dspI = 2;
        end
        else begin
            case (insn[(15)-1:0])
                0: begin
                    st0N = minus[(16)-1:0];
                    dstkW = 0;
                    dspI = 0;
                end
                1: begin
                    st0N = st0;
                    dstkW = 0;
                    dspI = 3;
                end
                2: begin
                    st0N = (st0 & st1);
                    dstkW = 1;
                    dspI = 3;
                end
                3: begin
                    st0N = (st0 | st1);
                    dstkW = 1;
                    dspI = 3;
                end
                4: begin
                    st0N = (st0 + st1);
                    dstkW = 1;
                    dspI = 3;
                end
                default: begin
                    st0N = {(16){1}};
                    dstkW = 0;
                    dspI = 3;
                end
            endcase
        end
    end
    always @(posedge clk) begin
        case (insn)
            32773: begin
                LED1 <= st0[0];
            end
        endcase
    end
    always @(*) begin
        if (reboot) begin
            pcN = 0;
        end
        else begin
            case (insn)
                32769: begin
                    pcN = st0;
                end
                default: begin
                    pcN = pc_plus_1;
                end
            endcase
        end
    end
    always @(posedge clk) begin
        if (reset) begin
            reboot <= 1;
            pc <= 0;
            st0 <= 0;
        end
        else begin
            reboot <= 0;
            pc <= pcN;
            st0 <= st0N;
        end
    end
endmodule

module Main (
    input clk,
    output LED1,
    output LED2,
    output LED3,
    output LED4
);
    reg [(1)-1:0] init_active_Z = 0;
    reg [(1)-1:0] reset;
    always @(*) begin
        reset = !(init_active_Z);
    end
    always @(negedge clk) begin
        init_active_Z <= 1;
    end
    reg [(8)-1:0] code [(4)-1:0];
    always @(*) begin
        code[0] = 1;
        code[1] = 32773;
        code[2] = 0;
        code[3] = 32769;
    end
    reg [(16)-1:0] insn;
    reg [(13)-1:0] code_addr;
    J1a j1(.clk (clk),
        .reset (reset),
        .code_addr (code_addr),
        .insn (insn),
        .LED1 (LED1));
    always @(*) begin
        LED2 = 0;
        LED3 = 0;
        LED4 = 0;
    end
    always @(negedge clk) begin
        insn <= code[code_addr];
    end
endmodule