# Generated by Yosys 0.7+ 25 (git sha1 c17d98f, clang 8.0.0 -fPIC -Os) .model Main .inputs clk PIO3_03 .outputs LED1 LED2 .names $false .names $true 1 .names $undef .gate SB_IO D_IN_0=input_0 D_IN_1=input_180 INPUT_CLK=clk PACKAGE_PIN=PIO3_03 .attr src "test.v:11" .param IO_STANDARD "SB_LVDS_INPUT" .param PIN_TYPE 000000 .names input_0 LED1 1 1 .names input_180 LED2 1 1 .end