entity Second {
    in clk: bit,
    out signal: bit,
}

impl Second {
    def mut index: uint{..12000000};

    on clk.posedge {
        if index == 12000000 - 1 {
            signal <= 1;
        } else {
            index <= index + 1;
            signal <= 0;
        }
    }
}

entity Main {
    in clk: bit,
    out LED1: bit,
    out LED2: bit,
    out LED3: bit,
    out LED4: bit,
    out LED5: bit,
}

impl Main {
    def mut rot: bit[4];
    def mut divider: uint{..1200000};

    def ready;
    def sec = Second {
        clk: clk,
        signal: ready
    };

    on clk.posedge {
        if !ready {
            divider <= 0;
        } else {
            if divider == 1200000 - 1 {
                divider <= 0;
                sequence {
                    rot <= 0b0001;
                    yield;
                    rot <= 0b0011;
                    yield;
                    rot <= 0b0110;
                    yield;
                    rot <= 0b1100;
                    yield;
                    rot <= 0b1000;
                    yield;
                    rot <= 0b0000;
                }
            } else {
                divider <= divider + 1;
            }
        }
    }

    // Defines LED states.
    LED1 = ready && rot[0];
    LED2 = ready && rot[1];
    LED3 = ready && rot[2];
    LED4 = ready && rot[3];
    LED5 = !ready;
}