#![doc = "Peripheral access API for HPM5361 microcontrollers (generated using svd2rust v0.31.5 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.31.5/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
use core::marker::PhantomData;
use core::ops::Deref;
#[doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS: u8 = 7;
#[allow(unused_imports)]
use generic::*;
#[doc = "Common register and bit access and modify traits"]
pub mod generic;
#[cfg(feature = "rt")]
extern "C" {}
#[doc(hidden)]
#[repr(C)]
pub union Vector {
    pub _handler: unsafe extern "C" fn(),
    pub _reserved: usize,
}
#[cfg(feature = "rt")]
#[doc(hidden)]
#[no_mangle]
pub static __EXTERNAL_INTERRUPTS: [Vector; 0] = [];
#[doc = "FGPIO"]
pub struct FGPIO {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for FGPIO {}
impl FGPIO {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const fgpio::RegisterBlock = 0x000c_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const fgpio::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for FGPIO {
    type Target = fgpio::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for FGPIO {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("FGPIO").finish()
    }
}
#[doc = "FGPIO"]
pub mod fgpio {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        di: (),
        _reserved1: [u8; 0x0100],
        do_: [DO; 15],
        _reserved2: [u8; 0x10],
        oe: [OE; 15],
        _reserved3: [u8; 0x10],
        if_: (),
        _reserved4: [u8; 0x0100],
        ie: [IE; 15],
        _reserved5: [u8; 0x10],
        pl: [PL; 15],
        _reserved6: [u8; 0x10],
        tp: [TP; 15],
        _reserved7: [u8; 0x10],
        as_: [AS; 15],
        _reserved8: [u8; 0x10],
        pd: [PD; 15],
    }
    impl RegisterBlock {
        #[doc = "0x00..0x3c - no description available"]
        #[inline(always)]
        pub const fn di(&self, n: usize) -> &DI {
            #[allow(clippy::no_effect)]
            [(); 15][n];
            unsafe { &*(self as *const Self).cast::<u8>().add(0).add(16 * n).cast() }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x3c - no description available"]
        #[inline(always)]
        pub fn di_iter(&self) -> impl Iterator<Item = &DI> {
            (0..15).map(move |n| unsafe {
                &*(self as *const Self).cast::<u8>().add(0).add(16 * n).cast()
            })
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn digpioa(&self) -> &DI {
            self.di(0)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn digpiob(&self) -> &DI {
            self.di(1)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn dirsv3(&self) -> &DI {
            self.di(2)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn dirsv4(&self) -> &DI {
            self.di(3)
        }
        #[doc = "0x40 - no description available"]
        #[inline(always)]
        pub const fn dirsv5(&self) -> &DI {
            self.di(4)
        }
        #[doc = "0x50 - no description available"]
        #[inline(always)]
        pub const fn dirsv6(&self) -> &DI {
            self.di(5)
        }
        #[doc = "0x60 - no description available"]
        #[inline(always)]
        pub const fn dirsv7(&self) -> &DI {
            self.di(6)
        }
        #[doc = "0x70 - no description available"]
        #[inline(always)]
        pub const fn dirsv8(&self) -> &DI {
            self.di(7)
        }
        #[doc = "0x80 - no description available"]
        #[inline(always)]
        pub const fn dirsv9(&self) -> &DI {
            self.di(8)
        }
        #[doc = "0x90 - no description available"]
        #[inline(always)]
        pub const fn dirsv10(&self) -> &DI {
            self.di(9)
        }
        #[doc = "0xa0 - no description available"]
        #[inline(always)]
        pub const fn dirsv11(&self) -> &DI {
            self.di(10)
        }
        #[doc = "0xb0 - no description available"]
        #[inline(always)]
        pub const fn dirsv12(&self) -> &DI {
            self.di(11)
        }
        #[doc = "0xc0 - no description available"]
        #[inline(always)]
        pub const fn dirsv13(&self) -> &DI {
            self.di(12)
        }
        #[doc = "0xd0 - no description available"]
        #[inline(always)]
        pub const fn digpiox(&self) -> &DI {
            self.di(13)
        }
        #[doc = "0xe0 - no description available"]
        #[inline(always)]
        pub const fn digpioy(&self) -> &DI {
            self.di(14)
        }
        #[doc = "0x100..0x1f0 - no description available"]
        #[inline(always)]
        pub const fn do_(&self, n: usize) -> &DO {
            &self.do_[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x100..0x1f0 - no description available"]
        #[inline(always)]
        pub fn do__iter(&self) -> impl Iterator<Item = &DO> {
            self.do_.iter()
        }
        #[doc = "0x100..0x110 - no description available"]
        #[inline(always)]
        pub const fn dogpioa(&self) -> &DO {
            self.do_(0)
        }
        #[doc = "0x110..0x120 - no description available"]
        #[inline(always)]
        pub const fn dogpiob(&self) -> &DO {
            self.do_(1)
        }
        #[doc = "0x120..0x130 - no description available"]
        #[inline(always)]
        pub const fn dorsv3(&self) -> &DO {
            self.do_(2)
        }
        #[doc = "0x130..0x140 - no description available"]
        #[inline(always)]
        pub const fn dorsv4(&self) -> &DO {
            self.do_(3)
        }
        #[doc = "0x140..0x150 - no description available"]
        #[inline(always)]
        pub const fn dorsv5(&self) -> &DO {
            self.do_(4)
        }
        #[doc = "0x150..0x160 - no description available"]
        #[inline(always)]
        pub const fn dorsv6(&self) -> &DO {
            self.do_(5)
        }
        #[doc = "0x160..0x170 - no description available"]
        #[inline(always)]
        pub const fn dorsv7(&self) -> &DO {
            self.do_(6)
        }
        #[doc = "0x170..0x180 - no description available"]
        #[inline(always)]
        pub const fn dorsv8(&self) -> &DO {
            self.do_(7)
        }
        #[doc = "0x180..0x190 - no description available"]
        #[inline(always)]
        pub const fn dorsv9(&self) -> &DO {
            self.do_(8)
        }
        #[doc = "0x190..0x1a0 - no description available"]
        #[inline(always)]
        pub const fn dorsv10(&self) -> &DO {
            self.do_(9)
        }
        #[doc = "0x1a0..0x1b0 - no description available"]
        #[inline(always)]
        pub const fn dorsv11(&self) -> &DO {
            self.do_(10)
        }
        #[doc = "0x1b0..0x1c0 - no description available"]
        #[inline(always)]
        pub const fn dorsv12(&self) -> &DO {
            self.do_(11)
        }
        #[doc = "0x1c0..0x1d0 - no description available"]
        #[inline(always)]
        pub const fn dorsv13(&self) -> &DO {
            self.do_(12)
        }
        #[doc = "0x1d0..0x1e0 - no description available"]
        #[inline(always)]
        pub const fn dogpiox(&self) -> &DO {
            self.do_(13)
        }
        #[doc = "0x1e0..0x1f0 - no description available"]
        #[inline(always)]
        pub const fn dogpioy(&self) -> &DO {
            self.do_(14)
        }
        #[doc = "0x200..0x2f0 - no description available"]
        #[inline(always)]
        pub const fn oe(&self, n: usize) -> &OE {
            &self.oe[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x200..0x2f0 - no description available"]
        #[inline(always)]
        pub fn oe_iter(&self) -> impl Iterator<Item = &OE> {
            self.oe.iter()
        }
        #[doc = "0x200..0x210 - no description available"]
        #[inline(always)]
        pub const fn oegpioa(&self) -> &OE {
            self.oe(0)
        }
        #[doc = "0x210..0x220 - no description available"]
        #[inline(always)]
        pub const fn oegpiob(&self) -> &OE {
            self.oe(1)
        }
        #[doc = "0x220..0x230 - no description available"]
        #[inline(always)]
        pub const fn oersv3(&self) -> &OE {
            self.oe(2)
        }
        #[doc = "0x230..0x240 - no description available"]
        #[inline(always)]
        pub const fn oersv4(&self) -> &OE {
            self.oe(3)
        }
        #[doc = "0x240..0x250 - no description available"]
        #[inline(always)]
        pub const fn oersv5(&self) -> &OE {
            self.oe(4)
        }
        #[doc = "0x250..0x260 - no description available"]
        #[inline(always)]
        pub const fn oersv6(&self) -> &OE {
            self.oe(5)
        }
        #[doc = "0x260..0x270 - no description available"]
        #[inline(always)]
        pub const fn oersv7(&self) -> &OE {
            self.oe(6)
        }
        #[doc = "0x270..0x280 - no description available"]
        #[inline(always)]
        pub const fn oersv8(&self) -> &OE {
            self.oe(7)
        }
        #[doc = "0x280..0x290 - no description available"]
        #[inline(always)]
        pub const fn oersv9(&self) -> &OE {
            self.oe(8)
        }
        #[doc = "0x290..0x2a0 - no description available"]
        #[inline(always)]
        pub const fn oersv10(&self) -> &OE {
            self.oe(9)
        }
        #[doc = "0x2a0..0x2b0 - no description available"]
        #[inline(always)]
        pub const fn oersv11(&self) -> &OE {
            self.oe(10)
        }
        #[doc = "0x2b0..0x2c0 - no description available"]
        #[inline(always)]
        pub const fn oersv12(&self) -> &OE {
            self.oe(11)
        }
        #[doc = "0x2c0..0x2d0 - no description available"]
        #[inline(always)]
        pub const fn oersv13(&self) -> &OE {
            self.oe(12)
        }
        #[doc = "0x2d0..0x2e0 - no description available"]
        #[inline(always)]
        pub const fn oegpiox(&self) -> &OE {
            self.oe(13)
        }
        #[doc = "0x2e0..0x2f0 - no description available"]
        #[inline(always)]
        pub const fn oegpioy(&self) -> &OE {
            self.oe(14)
        }
        #[doc = "0x300..0x33c - no description available"]
        #[inline(always)]
        pub const fn if_(&self, n: usize) -> &IF {
            #[allow(clippy::no_effect)]
            [(); 15][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(768)
                    .add(16 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x300..0x33c - no description available"]
        #[inline(always)]
        pub fn if__iter(&self) -> impl Iterator<Item = &IF> {
            (0..15).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(768)
                    .add(16 * n)
                    .cast()
            })
        }
        #[doc = "0x300 - no description available"]
        #[inline(always)]
        pub const fn ifgpioa(&self) -> &IF {
            self.if_(0)
        }
        #[doc = "0x310 - no description available"]
        #[inline(always)]
        pub const fn ifgpiob(&self) -> &IF {
            self.if_(1)
        }
        #[doc = "0x320 - no description available"]
        #[inline(always)]
        pub const fn ifrsv3(&self) -> &IF {
            self.if_(2)
        }
        #[doc = "0x330 - no description available"]
        #[inline(always)]
        pub const fn ifrsv4(&self) -> &IF {
            self.if_(3)
        }
        #[doc = "0x340 - no description available"]
        #[inline(always)]
        pub const fn ifrsv5(&self) -> &IF {
            self.if_(4)
        }
        #[doc = "0x350 - no description available"]
        #[inline(always)]
        pub const fn ifrsv6(&self) -> &IF {
            self.if_(5)
        }
        #[doc = "0x360 - no description available"]
        #[inline(always)]
        pub const fn ifrsv7(&self) -> &IF {
            self.if_(6)
        }
        #[doc = "0x370 - no description available"]
        #[inline(always)]
        pub const fn ifrsv8(&self) -> &IF {
            self.if_(7)
        }
        #[doc = "0x380 - no description available"]
        #[inline(always)]
        pub const fn ifrsv9(&self) -> &IF {
            self.if_(8)
        }
        #[doc = "0x390 - no description available"]
        #[inline(always)]
        pub const fn ifrsv10(&self) -> &IF {
            self.if_(9)
        }
        #[doc = "0x3a0 - no description available"]
        #[inline(always)]
        pub const fn ifrsv11(&self) -> &IF {
            self.if_(10)
        }
        #[doc = "0x3b0 - no description available"]
        #[inline(always)]
        pub const fn ifrsv12(&self) -> &IF {
            self.if_(11)
        }
        #[doc = "0x3c0 - no description available"]
        #[inline(always)]
        pub const fn ifrsv13(&self) -> &IF {
            self.if_(12)
        }
        #[doc = "0x3d0 - no description available"]
        #[inline(always)]
        pub const fn ifgpiox(&self) -> &IF {
            self.if_(13)
        }
        #[doc = "0x3e0 - no description available"]
        #[inline(always)]
        pub const fn ifgpioy(&self) -> &IF {
            self.if_(14)
        }
        #[doc = "0x400..0x4f0 - no description available"]
        #[inline(always)]
        pub const fn ie(&self, n: usize) -> &IE {
            &self.ie[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x400..0x4f0 - no description available"]
        #[inline(always)]
        pub fn ie_iter(&self) -> impl Iterator<Item = &IE> {
            self.ie.iter()
        }
        #[doc = "0x400..0x410 - no description available"]
        #[inline(always)]
        pub const fn iegpioa(&self) -> &IE {
            self.ie(0)
        }
        #[doc = "0x410..0x420 - no description available"]
        #[inline(always)]
        pub const fn iegpiob(&self) -> &IE {
            self.ie(1)
        }
        #[doc = "0x420..0x430 - no description available"]
        #[inline(always)]
        pub const fn iersv3(&self) -> &IE {
            self.ie(2)
        }
        #[doc = "0x430..0x440 - no description available"]
        #[inline(always)]
        pub const fn iersv4(&self) -> &IE {
            self.ie(3)
        }
        #[doc = "0x440..0x450 - no description available"]
        #[inline(always)]
        pub const fn iersv5(&self) -> &IE {
            self.ie(4)
        }
        #[doc = "0x450..0x460 - no description available"]
        #[inline(always)]
        pub const fn iersv6(&self) -> &IE {
            self.ie(5)
        }
        #[doc = "0x460..0x470 - no description available"]
        #[inline(always)]
        pub const fn iersv7(&self) -> &IE {
            self.ie(6)
        }
        #[doc = "0x470..0x480 - no description available"]
        #[inline(always)]
        pub const fn iersv8(&self) -> &IE {
            self.ie(7)
        }
        #[doc = "0x480..0x490 - no description available"]
        #[inline(always)]
        pub const fn iersv9(&self) -> &IE {
            self.ie(8)
        }
        #[doc = "0x490..0x4a0 - no description available"]
        #[inline(always)]
        pub const fn iersv10(&self) -> &IE {
            self.ie(9)
        }
        #[doc = "0x4a0..0x4b0 - no description available"]
        #[inline(always)]
        pub const fn iersv11(&self) -> &IE {
            self.ie(10)
        }
        #[doc = "0x4b0..0x4c0 - no description available"]
        #[inline(always)]
        pub const fn iersv12(&self) -> &IE {
            self.ie(11)
        }
        #[doc = "0x4c0..0x4d0 - no description available"]
        #[inline(always)]
        pub const fn iersv13(&self) -> &IE {
            self.ie(12)
        }
        #[doc = "0x4d0..0x4e0 - no description available"]
        #[inline(always)]
        pub const fn iegpiox(&self) -> &IE {
            self.ie(13)
        }
        #[doc = "0x4e0..0x4f0 - no description available"]
        #[inline(always)]
        pub const fn iegpioy(&self) -> &IE {
            self.ie(14)
        }
        #[doc = "0x500..0x5f0 - no description available"]
        #[inline(always)]
        pub const fn pl(&self, n: usize) -> &PL {
            &self.pl[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x500..0x5f0 - no description available"]
        #[inline(always)]
        pub fn pl_iter(&self) -> impl Iterator<Item = &PL> {
            self.pl.iter()
        }
        #[doc = "0x500..0x510 - no description available"]
        #[inline(always)]
        pub const fn plgpioa(&self) -> &PL {
            self.pl(0)
        }
        #[doc = "0x510..0x520 - no description available"]
        #[inline(always)]
        pub const fn plgpiob(&self) -> &PL {
            self.pl(1)
        }
        #[doc = "0x520..0x530 - no description available"]
        #[inline(always)]
        pub const fn plrsv3(&self) -> &PL {
            self.pl(2)
        }
        #[doc = "0x530..0x540 - no description available"]
        #[inline(always)]
        pub const fn plrsv4(&self) -> &PL {
            self.pl(3)
        }
        #[doc = "0x540..0x550 - no description available"]
        #[inline(always)]
        pub const fn plrsv5(&self) -> &PL {
            self.pl(4)
        }
        #[doc = "0x550..0x560 - no description available"]
        #[inline(always)]
        pub const fn plrsv6(&self) -> &PL {
            self.pl(5)
        }
        #[doc = "0x560..0x570 - no description available"]
        #[inline(always)]
        pub const fn plrsv7(&self) -> &PL {
            self.pl(6)
        }
        #[doc = "0x570..0x580 - no description available"]
        #[inline(always)]
        pub const fn plrsv8(&self) -> &PL {
            self.pl(7)
        }
        #[doc = "0x580..0x590 - no description available"]
        #[inline(always)]
        pub const fn plrsv9(&self) -> &PL {
            self.pl(8)
        }
        #[doc = "0x590..0x5a0 - no description available"]
        #[inline(always)]
        pub const fn plrsv10(&self) -> &PL {
            self.pl(9)
        }
        #[doc = "0x5a0..0x5b0 - no description available"]
        #[inline(always)]
        pub const fn plrsv11(&self) -> &PL {
            self.pl(10)
        }
        #[doc = "0x5b0..0x5c0 - no description available"]
        #[inline(always)]
        pub const fn plrsv12(&self) -> &PL {
            self.pl(11)
        }
        #[doc = "0x5c0..0x5d0 - no description available"]
        #[inline(always)]
        pub const fn plrsv13(&self) -> &PL {
            self.pl(12)
        }
        #[doc = "0x5d0..0x5e0 - no description available"]
        #[inline(always)]
        pub const fn plgpiox(&self) -> &PL {
            self.pl(13)
        }
        #[doc = "0x5e0..0x5f0 - no description available"]
        #[inline(always)]
        pub const fn plgpioy(&self) -> &PL {
            self.pl(14)
        }
        #[doc = "0x600..0x6f0 - no description available"]
        #[inline(always)]
        pub const fn tp(&self, n: usize) -> &TP {
            &self.tp[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x600..0x6f0 - no description available"]
        #[inline(always)]
        pub fn tp_iter(&self) -> impl Iterator<Item = &TP> {
            self.tp.iter()
        }
        #[doc = "0x600..0x610 - no description available"]
        #[inline(always)]
        pub const fn tpgpioa(&self) -> &TP {
            self.tp(0)
        }
        #[doc = "0x610..0x620 - no description available"]
        #[inline(always)]
        pub const fn tpgpiob(&self) -> &TP {
            self.tp(1)
        }
        #[doc = "0x620..0x630 - no description available"]
        #[inline(always)]
        pub const fn tprsv3(&self) -> &TP {
            self.tp(2)
        }
        #[doc = "0x630..0x640 - no description available"]
        #[inline(always)]
        pub const fn tprsv4(&self) -> &TP {
            self.tp(3)
        }
        #[doc = "0x640..0x650 - no description available"]
        #[inline(always)]
        pub const fn tprsv5(&self) -> &TP {
            self.tp(4)
        }
        #[doc = "0x650..0x660 - no description available"]
        #[inline(always)]
        pub const fn tprsv6(&self) -> &TP {
            self.tp(5)
        }
        #[doc = "0x660..0x670 - no description available"]
        #[inline(always)]
        pub const fn tprsv7(&self) -> &TP {
            self.tp(6)
        }
        #[doc = "0x670..0x680 - no description available"]
        #[inline(always)]
        pub const fn tprsv8(&self) -> &TP {
            self.tp(7)
        }
        #[doc = "0x680..0x690 - no description available"]
        #[inline(always)]
        pub const fn tprsv9(&self) -> &TP {
            self.tp(8)
        }
        #[doc = "0x690..0x6a0 - no description available"]
        #[inline(always)]
        pub const fn tprsv10(&self) -> &TP {
            self.tp(9)
        }
        #[doc = "0x6a0..0x6b0 - no description available"]
        #[inline(always)]
        pub const fn tprsv11(&self) -> &TP {
            self.tp(10)
        }
        #[doc = "0x6b0..0x6c0 - no description available"]
        #[inline(always)]
        pub const fn tprsv12(&self) -> &TP {
            self.tp(11)
        }
        #[doc = "0x6c0..0x6d0 - no description available"]
        #[inline(always)]
        pub const fn tprsv13(&self) -> &TP {
            self.tp(12)
        }
        #[doc = "0x6d0..0x6e0 - no description available"]
        #[inline(always)]
        pub const fn tpgpiox(&self) -> &TP {
            self.tp(13)
        }
        #[doc = "0x6e0..0x6f0 - no description available"]
        #[inline(always)]
        pub const fn tpgpioy(&self) -> &TP {
            self.tp(14)
        }
        #[doc = "0x700..0x7f0 - no description available"]
        #[inline(always)]
        pub const fn as_(&self, n: usize) -> &AS {
            &self.as_[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x700..0x7f0 - no description available"]
        #[inline(always)]
        pub fn as__iter(&self) -> impl Iterator<Item = &AS> {
            self.as_.iter()
        }
        #[doc = "0x700..0x710 - no description available"]
        #[inline(always)]
        pub const fn asgpioa(&self) -> &AS {
            self.as_(0)
        }
        #[doc = "0x710..0x720 - no description available"]
        #[inline(always)]
        pub const fn asgpiob(&self) -> &AS {
            self.as_(1)
        }
        #[doc = "0x720..0x730 - no description available"]
        #[inline(always)]
        pub const fn asrsv3(&self) -> &AS {
            self.as_(2)
        }
        #[doc = "0x730..0x740 - no description available"]
        #[inline(always)]
        pub const fn asrsv4(&self) -> &AS {
            self.as_(3)
        }
        #[doc = "0x740..0x750 - no description available"]
        #[inline(always)]
        pub const fn asrsv5(&self) -> &AS {
            self.as_(4)
        }
        #[doc = "0x750..0x760 - no description available"]
        #[inline(always)]
        pub const fn asrsv6(&self) -> &AS {
            self.as_(5)
        }
        #[doc = "0x760..0x770 - no description available"]
        #[inline(always)]
        pub const fn asrsv7(&self) -> &AS {
            self.as_(6)
        }
        #[doc = "0x770..0x780 - no description available"]
        #[inline(always)]
        pub const fn asrsv8(&self) -> &AS {
            self.as_(7)
        }
        #[doc = "0x780..0x790 - no description available"]
        #[inline(always)]
        pub const fn asrsv9(&self) -> &AS {
            self.as_(8)
        }
        #[doc = "0x790..0x7a0 - no description available"]
        #[inline(always)]
        pub const fn asrsv10(&self) -> &AS {
            self.as_(9)
        }
        #[doc = "0x7a0..0x7b0 - no description available"]
        #[inline(always)]
        pub const fn asrsv11(&self) -> &AS {
            self.as_(10)
        }
        #[doc = "0x7b0..0x7c0 - no description available"]
        #[inline(always)]
        pub const fn asrsv12(&self) -> &AS {
            self.as_(11)
        }
        #[doc = "0x7c0..0x7d0 - no description available"]
        #[inline(always)]
        pub const fn asrsv13(&self) -> &AS {
            self.as_(12)
        }
        #[doc = "0x7d0..0x7e0 - no description available"]
        #[inline(always)]
        pub const fn asgpiox(&self) -> &AS {
            self.as_(13)
        }
        #[doc = "0x7e0..0x7f0 - no description available"]
        #[inline(always)]
        pub const fn asgpioy(&self) -> &AS {
            self.as_(14)
        }
        #[doc = "0x800..0x8f0 - no description available"]
        #[inline(always)]
        pub const fn pd(&self, n: usize) -> &PD {
            &self.pd[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x800..0x8f0 - no description available"]
        #[inline(always)]
        pub fn pd_iter(&self) -> impl Iterator<Item = &PD> {
            self.pd.iter()
        }
        #[doc = "0x800..0x810 - no description available"]
        #[inline(always)]
        pub const fn pdgpioa(&self) -> &PD {
            self.pd(0)
        }
        #[doc = "0x810..0x820 - no description available"]
        #[inline(always)]
        pub const fn pdgpiob(&self) -> &PD {
            self.pd(1)
        }
        #[doc = "0x820..0x830 - no description available"]
        #[inline(always)]
        pub const fn pdrsv3(&self) -> &PD {
            self.pd(2)
        }
        #[doc = "0x830..0x840 - no description available"]
        #[inline(always)]
        pub const fn pdrsv4(&self) -> &PD {
            self.pd(3)
        }
        #[doc = "0x840..0x850 - no description available"]
        #[inline(always)]
        pub const fn pdrsv5(&self) -> &PD {
            self.pd(4)
        }
        #[doc = "0x850..0x860 - no description available"]
        #[inline(always)]
        pub const fn pdrsv6(&self) -> &PD {
            self.pd(5)
        }
        #[doc = "0x860..0x870 - no description available"]
        #[inline(always)]
        pub const fn pdrsv7(&self) -> &PD {
            self.pd(6)
        }
        #[doc = "0x870..0x880 - no description available"]
        #[inline(always)]
        pub const fn pdrsv8(&self) -> &PD {
            self.pd(7)
        }
        #[doc = "0x880..0x890 - no description available"]
        #[inline(always)]
        pub const fn pdrsv9(&self) -> &PD {
            self.pd(8)
        }
        #[doc = "0x890..0x8a0 - no description available"]
        #[inline(always)]
        pub const fn pdrsv10(&self) -> &PD {
            self.pd(9)
        }
        #[doc = "0x8a0..0x8b0 - no description available"]
        #[inline(always)]
        pub const fn pdrsv11(&self) -> &PD {
            self.pd(10)
        }
        #[doc = "0x8b0..0x8c0 - no description available"]
        #[inline(always)]
        pub const fn pdrsv12(&self) -> &PD {
            self.pd(11)
        }
        #[doc = "0x8c0..0x8d0 - no description available"]
        #[inline(always)]
        pub const fn pdrsv13(&self) -> &PD {
            self.pd(12)
        }
        #[doc = "0x8d0..0x8e0 - no description available"]
        #[inline(always)]
        pub const fn pdgpiox(&self) -> &PD {
            self.pd(13)
        }
        #[doc = "0x8e0..0x8f0 - no description available"]
        #[inline(always)]
        pub const fn pdgpioy(&self) -> &PD {
            self.pd(14)
        }
    }
    #[doc = "no description available"]
    pub use self::di::DI;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod di {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct DI {
            value: VALUE,
        }
        impl DI {
            #[doc = "0x00 - GPIO input value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO input value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO input value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `INPUT` reader - GPIO input bus value, each bit represents a bus bit 0: low level presents on chip pin 1: high level presents on chip pin"]
            pub type INPUT_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO input bus value, each bit represents a bus bit 0: low level presents on chip pin 1: high level presents on chip pin"]
                #[inline(always)]
                pub fn input(&self) -> INPUT_R {
                    INPUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO input value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::do_::DO;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod do_ {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct DO {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl DO {
            #[doc = "0x00 - GPIO output value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - GPIO output set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - GPIO output clear"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - GPIO output toggle"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO output value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO output value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `OUTPUT` reader - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_R = crate::FieldReader<u32>;
            #[doc = "Field `OUTPUT` writer - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                pub fn output(&self) -> OUTPUT_R {
                    OUTPUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                #[must_use]
                pub fn output(&mut self) -> OUTPUT_W<VALUE_SPEC> {
                    OUTPUT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO output value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: GPIO output set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "GPIO output set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `OUTPUT` reader - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_R = crate::FieldReader<u32>;
            #[doc = "Field `OUTPUT` writer - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                pub fn output(&self) -> OUTPUT_R {
                    OUTPUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                #[must_use]
                pub fn output(&mut self) -> OUTPUT_W<SET_SPEC> {
                    OUTPUT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO output set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: GPIO output clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "GPIO output clear"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `OUTPUT` reader - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_R = crate::FieldReader<u32>;
            #[doc = "Field `OUTPUT` writer - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                pub fn output(&self) -> OUTPUT_R {
                    OUTPUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                #[must_use]
                pub fn output(&mut self) -> OUTPUT_W<CLEAR_SPEC> {
                    OUTPUT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO output clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: GPIO output toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "GPIO output toggle"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `OUTPUT` reader - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_R = crate::FieldReader<u32>;
            #[doc = "Field `OUTPUT` writer - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
            pub type OUTPUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                pub fn output(&self) -> OUTPUT_R {
                    OUTPUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO output register value, each bit represents a bus bit 0: chip pin output low level when direction is output 1: chip pin output high level when direction is output"]
                #[inline(always)]
                #[must_use]
                pub fn output(&mut self) -> OUTPUT_W<TOGGLE_SPEC> {
                    OUTPUT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO output toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::oe::OE;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod oe {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct OE {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl OE {
            #[doc = "0x00 - GPIO direction value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - GPIO direction set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - GPIO direction clear"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - GPIO direction toggle"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO direction value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO direction value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `DIRECTION` reader - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_R = crate::FieldReader<u32>;
            #[doc = "Field `DIRECTION` writer - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                pub fn direction(&self) -> DIRECTION_R {
                    DIRECTION_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                #[must_use]
                pub fn direction(&mut self) -> DIRECTION_W<VALUE_SPEC> {
                    DIRECTION_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO direction value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: GPIO direction set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "GPIO direction set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `DIRECTION` reader - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_R = crate::FieldReader<u32>;
            #[doc = "Field `DIRECTION` writer - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                pub fn direction(&self) -> DIRECTION_R {
                    DIRECTION_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                #[must_use]
                pub fn direction(&mut self) -> DIRECTION_W<SET_SPEC> {
                    DIRECTION_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO direction set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: GPIO direction clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "GPIO direction clear"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `DIRECTION` reader - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_R = crate::FieldReader<u32>;
            #[doc = "Field `DIRECTION` writer - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                pub fn direction(&self) -> DIRECTION_R {
                    DIRECTION_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                #[must_use]
                pub fn direction(&mut self) -> DIRECTION_W<CLEAR_SPEC> {
                    DIRECTION_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO direction clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: GPIO direction toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "GPIO direction toggle"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `DIRECTION` reader - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_R = crate::FieldReader<u32>;
            #[doc = "Field `DIRECTION` writer - GPIO direction, each bit represents a bus bit 0: input 1: output"]
            pub type DIRECTION_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                pub fn direction(&self) -> DIRECTION_R {
                    DIRECTION_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO direction, each bit represents a bus bit 0: input 1: output"]
                #[inline(always)]
                #[must_use]
                pub fn direction(&mut self) -> DIRECTION_W<TOGGLE_SPEC> {
                    DIRECTION_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO direction toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::if_::IF;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod if_ {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct IF {
            value: VALUE,
        }
        impl IF {
            #[doc = "0x00 - GPIO interrupt flag value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO interrupt flag value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO interrupt flag value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `IRQ_FLAG` writer - GPIO interrupt flag, write 1 to clear this flag 0: no irq 1: irq pending"]
            pub type IRQ_FLAG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt flag, write 1 to clear this flag 0: no irq 1: irq pending"]
                #[inline(always)]
                #[must_use]
                pub fn irq_flag(&mut self) -> IRQ_FLAG_W<VALUE_SPEC> {
                    IRQ_FLAG_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt flag value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::ie::IE;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod ie {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct IE {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl IE {
            #[doc = "0x00 - GPIO interrupt enable value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - GPIO interrupt enable set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - GPIO interrupt enable clear"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - GPIO interrupt enable toggle"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO interrupt enable value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO interrupt enable value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `IRQ_EN` reader - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_EN` writer - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                pub fn irq_en(&self) -> IRQ_EN_R {
                    IRQ_EN_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                #[must_use]
                pub fn irq_en(&mut self) -> IRQ_EN_W<VALUE_SPEC> {
                    IRQ_EN_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt enable value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: GPIO interrupt enable set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "GPIO interrupt enable set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `IRQ_EN` reader - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_EN` writer - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                pub fn irq_en(&self) -> IRQ_EN_R {
                    IRQ_EN_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                #[must_use]
                pub fn irq_en(&mut self) -> IRQ_EN_W<SET_SPEC> {
                    IRQ_EN_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt enable set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: GPIO interrupt enable clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "GPIO interrupt enable clear"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `IRQ_EN` reader - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_EN` writer - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                pub fn irq_en(&self) -> IRQ_EN_R {
                    IRQ_EN_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                #[must_use]
                pub fn irq_en(&mut self) -> IRQ_EN_W<CLEAR_SPEC> {
                    IRQ_EN_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt enable clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: GPIO interrupt enable toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "GPIO interrupt enable toggle"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `IRQ_EN` reader - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_EN` writer - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
            pub type IRQ_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                pub fn irq_en(&self) -> IRQ_EN_R {
                    IRQ_EN_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt enable, each bit represents a bus bit 0: irq is disabled 1: irq is enable"]
                #[inline(always)]
                #[must_use]
                pub fn irq_en(&mut self) -> IRQ_EN_W<TOGGLE_SPEC> {
                    IRQ_EN_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt enable toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::pl::PL;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod pl {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct PL {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl PL {
            #[doc = "0x00 - GPIO interrupt polarity value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - GPIO interrupt polarity set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - GPIO interrupt polarity clear"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - GPIO interrupt polarity toggle"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO interrupt polarity value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO interrupt polarity value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `IRQ_POL` reader - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_POL` writer - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                pub fn irq_pol(&self) -> IRQ_POL_R {
                    IRQ_POL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_pol(&mut self) -> IRQ_POL_W<VALUE_SPEC> {
                    IRQ_POL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt polarity value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: GPIO interrupt polarity set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "GPIO interrupt polarity set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `IRQ_POL` reader - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_POL` writer - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                pub fn irq_pol(&self) -> IRQ_POL_R {
                    IRQ_POL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_pol(&mut self) -> IRQ_POL_W<SET_SPEC> {
                    IRQ_POL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt polarity set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: GPIO interrupt polarity clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "GPIO interrupt polarity clear"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `IRQ_POL` reader - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_POL` writer - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                pub fn irq_pol(&self) -> IRQ_POL_R {
                    IRQ_POL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_pol(&mut self) -> IRQ_POL_W<CLEAR_SPEC> {
                    IRQ_POL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt polarity clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: GPIO interrupt polarity toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "GPIO interrupt polarity toggle"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `IRQ_POL` reader - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_POL` writer - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
            pub type IRQ_POL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                pub fn irq_pol(&self) -> IRQ_POL_R {
                    IRQ_POL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt polarity, each bit represents a bus bit 0: irq is high level or rising edge 1: irq is low level or falling edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_pol(&mut self) -> IRQ_POL_W<TOGGLE_SPEC> {
                    IRQ_POL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt polarity toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::tp::TP;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod tp {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct TP {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl TP {
            #[doc = "0x00 - GPIO interrupt type value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - GPIO interrupt type set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - GPIO interrupt type clear"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - GPIO interrupt type toggle"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO interrupt type value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO interrupt type value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `IRQ_TYPE` reader - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_TYPE` writer - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                pub fn irq_type(&self) -> IRQ_TYPE_R {
                    IRQ_TYPE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_type(&mut self) -> IRQ_TYPE_W<VALUE_SPEC> {
                    IRQ_TYPE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt type value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: GPIO interrupt type set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "GPIO interrupt type set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `IRQ_TYPE` reader - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_TYPE` writer - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                pub fn irq_type(&self) -> IRQ_TYPE_R {
                    IRQ_TYPE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_type(&mut self) -> IRQ_TYPE_W<SET_SPEC> {
                    IRQ_TYPE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt type set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: GPIO interrupt type clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "GPIO interrupt type clear"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `IRQ_TYPE` reader - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_TYPE` writer - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                pub fn irq_type(&self) -> IRQ_TYPE_R {
                    IRQ_TYPE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_type(&mut self) -> IRQ_TYPE_W<CLEAR_SPEC> {
                    IRQ_TYPE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt type clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: GPIO interrupt type toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "GPIO interrupt type toggle"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `IRQ_TYPE` reader - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_TYPE` writer - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
            pub type IRQ_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                pub fn irq_type(&self) -> IRQ_TYPE_R {
                    IRQ_TYPE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt type, each bit represents a bus bit 0: irq is triggered by level 1: irq is triggered by edge"]
                #[inline(always)]
                #[must_use]
                pub fn irq_type(&mut self) -> IRQ_TYPE_W<TOGGLE_SPEC> {
                    IRQ_TYPE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt type toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::as_::AS;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod as_ {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct AS {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl AS {
            #[doc = "0x00 - GPIO interrupt asynchronous value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - GPIO interrupt asynchronous set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - GPIO interrupt asynchronous clear"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - GPIO interrupt asynchronous toggle"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO interrupt asynchronous value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO interrupt asynchronous value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `IRQ_ASYNC` reader - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_ASYNC` writer - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                pub fn irq_async(&self) -> IRQ_ASYNC_R {
                    IRQ_ASYNC_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                #[must_use]
                pub fn irq_async(&mut self) -> IRQ_ASYNC_W<VALUE_SPEC> {
                    IRQ_ASYNC_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt asynchronous value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: GPIO interrupt asynchronous set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "GPIO interrupt asynchronous set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `IRQ_ASYNC` reader - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_ASYNC` writer - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                pub fn irq_async(&self) -> IRQ_ASYNC_R {
                    IRQ_ASYNC_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                #[must_use]
                pub fn irq_async(&mut self) -> IRQ_ASYNC_W<SET_SPEC> {
                    IRQ_ASYNC_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt asynchronous set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: GPIO interrupt asynchronous clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "GPIO interrupt asynchronous clear"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `IRQ_ASYNC` reader - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_ASYNC` writer - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                pub fn irq_async(&self) -> IRQ_ASYNC_R {
                    IRQ_ASYNC_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                #[must_use]
                pub fn irq_async(&mut self) -> IRQ_ASYNC_W<CLEAR_SPEC> {
                    IRQ_ASYNC_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt asynchronous clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: GPIO interrupt asynchronous toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "GPIO interrupt asynchronous toggle"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `IRQ_ASYNC` reader - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_R = crate::FieldReader<u32>;
            #[doc = "Field `IRQ_ASYNC` writer - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
            pub type IRQ_ASYNC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                pub fn irq_async(&self) -> IRQ_ASYNC_R {
                    IRQ_ASYNC_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - GPIO interrupt asynchronous, each bit represents a bus bit 0: irq is triggered base on system clock 1: irq is triggered combinational Note: combinational interrupt is sensitive to environment noise"]
                #[inline(always)]
                #[must_use]
                pub fn irq_async(&mut self) -> IRQ_ASYNC_W<TOGGLE_SPEC> {
                    IRQ_ASYNC_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO interrupt asynchronous toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::pd::PD;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod pd {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct PD {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl PD {
            #[doc = "0x00 - GPIO dual edge interrupt enable value"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - GPIO dual edge interrupt enable set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - GPIO dual edge interrupt enable clear"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - GPIO dual edge interrupt enable toggle"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: GPIO dual edge interrupt enable value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "GPIO dual edge interrupt enable value"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `IRQ_DUAL` reader - GPIO dual edge interrupt enable 0: single edge interrupt 1: dual edge interrupt enable"]
            pub type IRQ_DUAL_R = crate::BitReader;
            #[doc = "Field `IRQ_DUAL` writer - GPIO dual edge interrupt enable 0: single edge interrupt 1: dual edge interrupt enable"]
            pub type IRQ_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable 0: single edge interrupt 1: dual edge interrupt enable"]
                #[inline(always)]
                pub fn irq_dual(&self) -> IRQ_DUAL_R {
                    IRQ_DUAL_R::new((self.bits & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable 0: single edge interrupt 1: dual edge interrupt enable"]
                #[inline(always)]
                #[must_use]
                pub fn irq_dual(&mut self) -> IRQ_DUAL_W<VALUE_SPEC> {
                    IRQ_DUAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO dual edge interrupt enable value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: GPIO dual edge interrupt enable set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "GPIO dual edge interrupt enable set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `IRQ_DUAL` reader - GPIO dual edge interrupt enable set 0: keep original edge interrupt type 1: dual edge interrupt enable"]
            pub type IRQ_DUAL_R = crate::BitReader;
            #[doc = "Field `IRQ_DUAL` writer - GPIO dual edge interrupt enable set 0: keep original edge interrupt type 1: dual edge interrupt enable"]
            pub type IRQ_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable set 0: keep original edge interrupt type 1: dual edge interrupt enable"]
                #[inline(always)]
                pub fn irq_dual(&self) -> IRQ_DUAL_R {
                    IRQ_DUAL_R::new((self.bits & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable set 0: keep original edge interrupt type 1: dual edge interrupt enable"]
                #[inline(always)]
                #[must_use]
                pub fn irq_dual(&mut self) -> IRQ_DUAL_W<SET_SPEC> {
                    IRQ_DUAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO dual edge interrupt enable set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: GPIO dual edge interrupt enable clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "GPIO dual edge interrupt enable clear"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `IRQ_DUAL` reader - GPIO dual edge interrupt enable clear 0: keep original edge interrupt type 1: single edge interrupt enable"]
            pub type IRQ_DUAL_R = crate::BitReader;
            #[doc = "Field `IRQ_DUAL` writer - GPIO dual edge interrupt enable clear 0: keep original edge interrupt type 1: single edge interrupt enable"]
            pub type IRQ_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable clear 0: keep original edge interrupt type 1: single edge interrupt enable"]
                #[inline(always)]
                pub fn irq_dual(&self) -> IRQ_DUAL_R {
                    IRQ_DUAL_R::new((self.bits & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable clear 0: keep original edge interrupt type 1: single edge interrupt enable"]
                #[inline(always)]
                #[must_use]
                pub fn irq_dual(&mut self) -> IRQ_DUAL_W<CLEAR_SPEC> {
                    IRQ_DUAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO dual edge interrupt enable clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: GPIO dual edge interrupt enable toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "GPIO dual edge interrupt enable toggle"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `IRQ_DUAL` reader - GPIO dual edge interrupt enable toggle 0: keep original edge interrupt type 1: change original edge interrupt type to another one."]
            pub type IRQ_DUAL_R = crate::BitReader;
            #[doc = "Field `IRQ_DUAL` writer - GPIO dual edge interrupt enable toggle 0: keep original edge interrupt type 1: change original edge interrupt type to another one."]
            pub type IRQ_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable toggle 0: keep original edge interrupt type 1: change original edge interrupt type to another one."]
                #[inline(always)]
                pub fn irq_dual(&self) -> IRQ_DUAL_R {
                    IRQ_DUAL_R::new((self.bits & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - GPIO dual edge interrupt enable toggle 0: keep original edge interrupt type 1: change original edge interrupt type to another one."]
                #[inline(always)]
                #[must_use]
                pub fn irq_dual(&mut self) -> IRQ_DUAL_W<TOGGLE_SPEC> {
                    IRQ_DUAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "GPIO dual edge interrupt enable toggle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "GPIO0"]
pub struct GPIO0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIO0 {}
impl GPIO0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const fgpio::RegisterBlock = 0xf00d_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const fgpio::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for GPIO0 {
    type Target = fgpio::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for GPIO0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIO0").finish()
    }
}
#[doc = "GPIO0"]
pub use self::fgpio as gpio0;
#[doc = "PGPIO"]
pub struct PGPIO {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PGPIO {}
impl PGPIO {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const fgpio::RegisterBlock = 0xf411_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const fgpio::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PGPIO {
    type Target = fgpio::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PGPIO {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PGPIO").finish()
    }
}
#[doc = "PGPIO"]
pub use self::fgpio as pgpio;
#[doc = "PLIC"]
pub struct PLIC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PLIC {}
impl PLIC {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const plic::RegisterBlock = 0xe400_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const plic::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PLIC {
    type Target = plic::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PLIC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PLIC").finish()
    }
}
#[doc = "PLIC"]
pub mod plic {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        feature: FEATURE,
        priority: [PRIORITY; 127],
        _reserved2: [u8; 0x0e00],
        pending: [PENDING; 4],
        _reserved3: [u8; 0x70],
        trigger: [TRIGGER; 4],
        _reserved4: [u8; 0x70],
        number: NUMBER,
        info: INFO,
        _reserved6: [u8; 0x0ef8],
        targetint: [TARGETINT; 1],
        _reserved7: [u8; 0x001f_dff0],
        targetconfig: [TARGETCONFIG; 1],
    }
    impl RegisterBlock {
        #[doc = "0x00 - Feature enable register"]
        #[inline(always)]
        pub const fn feature(&self) -> &FEATURE {
            &self.feature
        }
        #[doc = "0x04..0x200 - no description available"]
        #[inline(always)]
        pub const fn priority(&self, n: usize) -> &PRIORITY {
            &self.priority[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x04..0x200 - no description available"]
        #[inline(always)]
        pub fn priority_iter(&self) -> impl Iterator<Item = &PRIORITY> {
            self.priority.iter()
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority1(&self) -> &PRIORITY {
            self.priority(0)
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority2(&self) -> &PRIORITY {
            self.priority(1)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority3(&self) -> &PRIORITY {
            self.priority(2)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority4(&self) -> &PRIORITY {
            self.priority(3)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority5(&self) -> &PRIORITY {
            self.priority(4)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority6(&self) -> &PRIORITY {
            self.priority(5)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority7(&self) -> &PRIORITY {
            self.priority(6)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority8(&self) -> &PRIORITY {
            self.priority(7)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority9(&self) -> &PRIORITY {
            self.priority(8)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority10(&self) -> &PRIORITY {
            self.priority(9)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority11(&self) -> &PRIORITY {
            self.priority(10)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority12(&self) -> &PRIORITY {
            self.priority(11)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority13(&self) -> &PRIORITY {
            self.priority(12)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority14(&self) -> &PRIORITY {
            self.priority(13)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority15(&self) -> &PRIORITY {
            self.priority(14)
        }
        #[doc = "0x40 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority16(&self) -> &PRIORITY {
            self.priority(15)
        }
        #[doc = "0x44 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority17(&self) -> &PRIORITY {
            self.priority(16)
        }
        #[doc = "0x48 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority18(&self) -> &PRIORITY {
            self.priority(17)
        }
        #[doc = "0x4c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority19(&self) -> &PRIORITY {
            self.priority(18)
        }
        #[doc = "0x50 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority20(&self) -> &PRIORITY {
            self.priority(19)
        }
        #[doc = "0x54 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority21(&self) -> &PRIORITY {
            self.priority(20)
        }
        #[doc = "0x58 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority22(&self) -> &PRIORITY {
            self.priority(21)
        }
        #[doc = "0x5c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority23(&self) -> &PRIORITY {
            self.priority(22)
        }
        #[doc = "0x60 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority24(&self) -> &PRIORITY {
            self.priority(23)
        }
        #[doc = "0x64 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority25(&self) -> &PRIORITY {
            self.priority(24)
        }
        #[doc = "0x68 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority26(&self) -> &PRIORITY {
            self.priority(25)
        }
        #[doc = "0x6c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority27(&self) -> &PRIORITY {
            self.priority(26)
        }
        #[doc = "0x70 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority28(&self) -> &PRIORITY {
            self.priority(27)
        }
        #[doc = "0x74 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority29(&self) -> &PRIORITY {
            self.priority(28)
        }
        #[doc = "0x78 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority30(&self) -> &PRIORITY {
            self.priority(29)
        }
        #[doc = "0x7c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority31(&self) -> &PRIORITY {
            self.priority(30)
        }
        #[doc = "0x80 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority32(&self) -> &PRIORITY {
            self.priority(31)
        }
        #[doc = "0x84 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority33(&self) -> &PRIORITY {
            self.priority(32)
        }
        #[doc = "0x88 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority34(&self) -> &PRIORITY {
            self.priority(33)
        }
        #[doc = "0x8c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority35(&self) -> &PRIORITY {
            self.priority(34)
        }
        #[doc = "0x90 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority36(&self) -> &PRIORITY {
            self.priority(35)
        }
        #[doc = "0x94 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority37(&self) -> &PRIORITY {
            self.priority(36)
        }
        #[doc = "0x98 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority38(&self) -> &PRIORITY {
            self.priority(37)
        }
        #[doc = "0x9c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority39(&self) -> &PRIORITY {
            self.priority(38)
        }
        #[doc = "0xa0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority40(&self) -> &PRIORITY {
            self.priority(39)
        }
        #[doc = "0xa4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority41(&self) -> &PRIORITY {
            self.priority(40)
        }
        #[doc = "0xa8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority42(&self) -> &PRIORITY {
            self.priority(41)
        }
        #[doc = "0xac - no description available"]
        #[inline(always)]
        pub const fn prioritypriority43(&self) -> &PRIORITY {
            self.priority(42)
        }
        #[doc = "0xb0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority44(&self) -> &PRIORITY {
            self.priority(43)
        }
        #[doc = "0xb4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority45(&self) -> &PRIORITY {
            self.priority(44)
        }
        #[doc = "0xb8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority46(&self) -> &PRIORITY {
            self.priority(45)
        }
        #[doc = "0xbc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority47(&self) -> &PRIORITY {
            self.priority(46)
        }
        #[doc = "0xc0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority48(&self) -> &PRIORITY {
            self.priority(47)
        }
        #[doc = "0xc4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority49(&self) -> &PRIORITY {
            self.priority(48)
        }
        #[doc = "0xc8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority50(&self) -> &PRIORITY {
            self.priority(49)
        }
        #[doc = "0xcc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority51(&self) -> &PRIORITY {
            self.priority(50)
        }
        #[doc = "0xd0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority52(&self) -> &PRIORITY {
            self.priority(51)
        }
        #[doc = "0xd4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority53(&self) -> &PRIORITY {
            self.priority(52)
        }
        #[doc = "0xd8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority54(&self) -> &PRIORITY {
            self.priority(53)
        }
        #[doc = "0xdc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority55(&self) -> &PRIORITY {
            self.priority(54)
        }
        #[doc = "0xe0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority56(&self) -> &PRIORITY {
            self.priority(55)
        }
        #[doc = "0xe4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority57(&self) -> &PRIORITY {
            self.priority(56)
        }
        #[doc = "0xe8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority58(&self) -> &PRIORITY {
            self.priority(57)
        }
        #[doc = "0xec - no description available"]
        #[inline(always)]
        pub const fn prioritypriority59(&self) -> &PRIORITY {
            self.priority(58)
        }
        #[doc = "0xf0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority60(&self) -> &PRIORITY {
            self.priority(59)
        }
        #[doc = "0xf4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority61(&self) -> &PRIORITY {
            self.priority(60)
        }
        #[doc = "0xf8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority62(&self) -> &PRIORITY {
            self.priority(61)
        }
        #[doc = "0xfc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority63(&self) -> &PRIORITY {
            self.priority(62)
        }
        #[doc = "0x100 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority64(&self) -> &PRIORITY {
            self.priority(63)
        }
        #[doc = "0x104 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority65(&self) -> &PRIORITY {
            self.priority(64)
        }
        #[doc = "0x108 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority66(&self) -> &PRIORITY {
            self.priority(65)
        }
        #[doc = "0x10c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority67(&self) -> &PRIORITY {
            self.priority(66)
        }
        #[doc = "0x110 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority68(&self) -> &PRIORITY {
            self.priority(67)
        }
        #[doc = "0x114 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority69(&self) -> &PRIORITY {
            self.priority(68)
        }
        #[doc = "0x118 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority70(&self) -> &PRIORITY {
            self.priority(69)
        }
        #[doc = "0x11c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority71(&self) -> &PRIORITY {
            self.priority(70)
        }
        #[doc = "0x120 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority72(&self) -> &PRIORITY {
            self.priority(71)
        }
        #[doc = "0x124 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority73(&self) -> &PRIORITY {
            self.priority(72)
        }
        #[doc = "0x128 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority74(&self) -> &PRIORITY {
            self.priority(73)
        }
        #[doc = "0x12c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority75(&self) -> &PRIORITY {
            self.priority(74)
        }
        #[doc = "0x130 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority76(&self) -> &PRIORITY {
            self.priority(75)
        }
        #[doc = "0x134 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority77(&self) -> &PRIORITY {
            self.priority(76)
        }
        #[doc = "0x138 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority78(&self) -> &PRIORITY {
            self.priority(77)
        }
        #[doc = "0x13c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority79(&self) -> &PRIORITY {
            self.priority(78)
        }
        #[doc = "0x140 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority80(&self) -> &PRIORITY {
            self.priority(79)
        }
        #[doc = "0x144 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority81(&self) -> &PRIORITY {
            self.priority(80)
        }
        #[doc = "0x148 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority82(&self) -> &PRIORITY {
            self.priority(81)
        }
        #[doc = "0x14c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority83(&self) -> &PRIORITY {
            self.priority(82)
        }
        #[doc = "0x150 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority84(&self) -> &PRIORITY {
            self.priority(83)
        }
        #[doc = "0x154 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority85(&self) -> &PRIORITY {
            self.priority(84)
        }
        #[doc = "0x158 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority86(&self) -> &PRIORITY {
            self.priority(85)
        }
        #[doc = "0x15c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority87(&self) -> &PRIORITY {
            self.priority(86)
        }
        #[doc = "0x160 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority88(&self) -> &PRIORITY {
            self.priority(87)
        }
        #[doc = "0x164 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority89(&self) -> &PRIORITY {
            self.priority(88)
        }
        #[doc = "0x168 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority90(&self) -> &PRIORITY {
            self.priority(89)
        }
        #[doc = "0x16c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority91(&self) -> &PRIORITY {
            self.priority(90)
        }
        #[doc = "0x170 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority92(&self) -> &PRIORITY {
            self.priority(91)
        }
        #[doc = "0x174 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority93(&self) -> &PRIORITY {
            self.priority(92)
        }
        #[doc = "0x178 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority94(&self) -> &PRIORITY {
            self.priority(93)
        }
        #[doc = "0x17c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority95(&self) -> &PRIORITY {
            self.priority(94)
        }
        #[doc = "0x180 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority96(&self) -> &PRIORITY {
            self.priority(95)
        }
        #[doc = "0x184 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority97(&self) -> &PRIORITY {
            self.priority(96)
        }
        #[doc = "0x188 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority98(&self) -> &PRIORITY {
            self.priority(97)
        }
        #[doc = "0x18c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority99(&self) -> &PRIORITY {
            self.priority(98)
        }
        #[doc = "0x190 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority100(&self) -> &PRIORITY {
            self.priority(99)
        }
        #[doc = "0x194 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority101(&self) -> &PRIORITY {
            self.priority(100)
        }
        #[doc = "0x198 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority102(&self) -> &PRIORITY {
            self.priority(101)
        }
        #[doc = "0x19c - no description available"]
        #[inline(always)]
        pub const fn prioritypriority103(&self) -> &PRIORITY {
            self.priority(102)
        }
        #[doc = "0x1a0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority104(&self) -> &PRIORITY {
            self.priority(103)
        }
        #[doc = "0x1a4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority105(&self) -> &PRIORITY {
            self.priority(104)
        }
        #[doc = "0x1a8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority106(&self) -> &PRIORITY {
            self.priority(105)
        }
        #[doc = "0x1ac - no description available"]
        #[inline(always)]
        pub const fn prioritypriority107(&self) -> &PRIORITY {
            self.priority(106)
        }
        #[doc = "0x1b0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority108(&self) -> &PRIORITY {
            self.priority(107)
        }
        #[doc = "0x1b4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority109(&self) -> &PRIORITY {
            self.priority(108)
        }
        #[doc = "0x1b8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority110(&self) -> &PRIORITY {
            self.priority(109)
        }
        #[doc = "0x1bc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority111(&self) -> &PRIORITY {
            self.priority(110)
        }
        #[doc = "0x1c0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority112(&self) -> &PRIORITY {
            self.priority(111)
        }
        #[doc = "0x1c4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority113(&self) -> &PRIORITY {
            self.priority(112)
        }
        #[doc = "0x1c8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority114(&self) -> &PRIORITY {
            self.priority(113)
        }
        #[doc = "0x1cc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority115(&self) -> &PRIORITY {
            self.priority(114)
        }
        #[doc = "0x1d0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority116(&self) -> &PRIORITY {
            self.priority(115)
        }
        #[doc = "0x1d4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority117(&self) -> &PRIORITY {
            self.priority(116)
        }
        #[doc = "0x1d8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority118(&self) -> &PRIORITY {
            self.priority(117)
        }
        #[doc = "0x1dc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority119(&self) -> &PRIORITY {
            self.priority(118)
        }
        #[doc = "0x1e0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority120(&self) -> &PRIORITY {
            self.priority(119)
        }
        #[doc = "0x1e4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority121(&self) -> &PRIORITY {
            self.priority(120)
        }
        #[doc = "0x1e8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority122(&self) -> &PRIORITY {
            self.priority(121)
        }
        #[doc = "0x1ec - no description available"]
        #[inline(always)]
        pub const fn prioritypriority123(&self) -> &PRIORITY {
            self.priority(122)
        }
        #[doc = "0x1f0 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority124(&self) -> &PRIORITY {
            self.priority(123)
        }
        #[doc = "0x1f4 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority125(&self) -> &PRIORITY {
            self.priority(124)
        }
        #[doc = "0x1f8 - no description available"]
        #[inline(always)]
        pub const fn prioritypriority126(&self) -> &PRIORITY {
            self.priority(125)
        }
        #[doc = "0x1fc - no description available"]
        #[inline(always)]
        pub const fn prioritypriority127(&self) -> &PRIORITY {
            self.priority(126)
        }
        #[doc = "0x1000..0x1010 - no description available"]
        #[inline(always)]
        pub const fn pending(&self, n: usize) -> &PENDING {
            &self.pending[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1000..0x1010 - no description available"]
        #[inline(always)]
        pub fn pending_iter(&self) -> impl Iterator<Item = &PENDING> {
            self.pending.iter()
        }
        #[doc = "0x1000 - no description available"]
        #[inline(always)]
        pub const fn pendingpending0(&self) -> &PENDING {
            self.pending(0)
        }
        #[doc = "0x1004 - no description available"]
        #[inline(always)]
        pub const fn pendingpending1(&self) -> &PENDING {
            self.pending(1)
        }
        #[doc = "0x1008 - no description available"]
        #[inline(always)]
        pub const fn pendingpending2(&self) -> &PENDING {
            self.pending(2)
        }
        #[doc = "0x100c - no description available"]
        #[inline(always)]
        pub const fn pendingpending3(&self) -> &PENDING {
            self.pending(3)
        }
        #[doc = "0x1080..0x1090 - no description available"]
        #[inline(always)]
        pub const fn trigger(&self, n: usize) -> &TRIGGER {
            &self.trigger[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1080..0x1090 - no description available"]
        #[inline(always)]
        pub fn trigger_iter(&self) -> impl Iterator<Item = &TRIGGER> {
            self.trigger.iter()
        }
        #[doc = "0x1080 - no description available"]
        #[inline(always)]
        pub const fn triggertrigger0(&self) -> &TRIGGER {
            self.trigger(0)
        }
        #[doc = "0x1084 - no description available"]
        #[inline(always)]
        pub const fn triggertrigger1(&self) -> &TRIGGER {
            self.trigger(1)
        }
        #[doc = "0x1088 - no description available"]
        #[inline(always)]
        pub const fn triggertrigger2(&self) -> &TRIGGER {
            self.trigger(2)
        }
        #[doc = "0x108c - no description available"]
        #[inline(always)]
        pub const fn triggertrigger3(&self) -> &TRIGGER {
            self.trigger(3)
        }
        #[doc = "0x1100 - Number of supported interrupt sources and targets"]
        #[inline(always)]
        pub const fn number(&self) -> &NUMBER {
            &self.number
        }
        #[doc = "0x1104 - Version and the maximum priority"]
        #[inline(always)]
        pub const fn info(&self) -> &INFO {
            &self.info
        }
        #[doc = "0x2000..0x2010 - no description available"]
        #[inline(always)]
        pub const fn targetint(&self, n: usize) -> &TARGETINT {
            &self.targetint[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x2000..0x2010 - no description available"]
        #[inline(always)]
        pub fn targetint_iter(&self) -> impl Iterator<Item = &TARGETINT> {
            self.targetint.iter()
        }
        #[doc = "0x2000..0x2010 - no description available"]
        #[inline(always)]
        pub const fn targetinttarget0(&self) -> &TARGETINT {
            self.targetint(0)
        }
        #[doc = "0x200000..0x200404 - no description available"]
        #[inline(always)]
        pub const fn targetconfig(&self, n: usize) -> &TARGETCONFIG {
            &self.targetconfig[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x200000..0x200404 - no description available"]
        #[inline(always)]
        pub fn targetconfig_iter(&self) -> impl Iterator<Item = &TARGETCONFIG> {
            self.targetconfig.iter()
        }
        #[doc = "0x200000..0x200404 - no description available"]
        #[inline(always)]
        pub const fn targetconfigtarget0(&self) -> &TARGETCONFIG {
            self.targetconfig(0)
        }
    }
    #[doc = "feature (rw) register accessor: Feature enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`feature::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`feature::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@feature`]
module"]
    pub type FEATURE = crate::Reg<feature::FEATURE_SPEC>;
    #[doc = "Feature enable register"]
    pub mod feature {
        #[doc = "Register `feature` reader"]
        pub type R = crate::R<FEATURE_SPEC>;
        #[doc = "Register `feature` writer"]
        pub type W = crate::W<FEATURE_SPEC>;
        #[doc = "Field `PREEMPT` reader - Preemptive priority interrupt enable 0: Disabled 1: Enabled"]
        pub type PREEMPT_R = crate::BitReader;
        #[doc = "Field `PREEMPT` writer - Preemptive priority interrupt enable 0: Disabled 1: Enabled"]
        pub type PREEMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VECTORED` reader - Vector mode enable 0: Disabled 1: Enabled"]
        pub type VECTORED_R = crate::BitReader;
        #[doc = "Field `VECTORED` writer - Vector mode enable 0: Disabled 1: Enabled"]
        pub type VECTORED_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Preemptive priority interrupt enable 0: Disabled 1: Enabled"]
            #[inline(always)]
            pub fn preempt(&self) -> PREEMPT_R {
                PREEMPT_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Vector mode enable 0: Disabled 1: Enabled"]
            #[inline(always)]
            pub fn vectored(&self) -> VECTORED_R {
                VECTORED_R::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Preemptive priority interrupt enable 0: Disabled 1: Enabled"]
            #[inline(always)]
            #[must_use]
            pub fn preempt(&mut self) -> PREEMPT_W<FEATURE_SPEC> {
                PREEMPT_W::new(self, 0)
            }
            #[doc = "Bit 1 - Vector mode enable 0: Disabled 1: Enabled"]
            #[inline(always)]
            #[must_use]
            pub fn vectored(&mut self) -> VECTORED_W<FEATURE_SPEC> {
                VECTORED_W::new(self, 1)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Feature enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`feature::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`feature::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FEATURE_SPEC;
        impl crate::RegisterSpec for FEATURE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`feature::R`](R) reader structure"]
        impl crate::Readable for FEATURE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`feature::W`](W) writer structure"]
        impl crate::Writable for FEATURE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets feature to value 0"]
        impl crate::Resettable for FEATURE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PRIORITY (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@priority`]
module"]
    pub type PRIORITY = crate::Reg<priority::PRIORITY_SPEC>;
    #[doc = "no description available"]
    pub mod priority {
        #[doc = "Register `PRIORITY[%s]` reader"]
        pub type R = crate::R<PRIORITY_SPEC>;
        #[doc = "Register `PRIORITY[%s]` writer"]
        pub type W = crate::W<PRIORITY_SPEC>;
        #[doc = "Field `PRIORITY` reader - Interrupt source priority. The valid range of this field is 0-7. 0: Never interrupt 1-7: Interrupt source priority. The larger the value, the higher the priority."]
        pub type PRIORITY_R = crate::FieldReader<u32>;
        #[doc = "Field `PRIORITY` writer - Interrupt source priority. The valid range of this field is 0-7. 0: Never interrupt 1-7: Interrupt source priority. The larger the value, the higher the priority."]
        pub type PRIORITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Interrupt source priority. The valid range of this field is 0-7. 0: Never interrupt 1-7: Interrupt source priority. The larger the value, the higher the priority."]
            #[inline(always)]
            pub fn priority(&self) -> PRIORITY_R {
                PRIORITY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Interrupt source priority. The valid range of this field is 0-7. 0: Never interrupt 1-7: Interrupt source priority. The larger the value, the higher the priority."]
            #[inline(always)]
            #[must_use]
            pub fn priority(&mut self) -> PRIORITY_W<PRIORITY_SPEC> {
                PRIORITY_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`priority::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`priority::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PRIORITY_SPEC;
        impl crate::RegisterSpec for PRIORITY_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`priority::R`](R) reader structure"]
        impl crate::Readable for PRIORITY_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`priority::W`](W) writer structure"]
        impl crate::Writable for PRIORITY_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PRIORITY[%s]
to value 0x01"]
        impl crate::Resettable for PRIORITY_SPEC {
            const RESET_VALUE: u32 = 0x01;
        }
    }
    #[doc = "PENDING (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending`]
module"]
    pub type PENDING = crate::Reg<pending::PENDING_SPEC>;
    #[doc = "no description available"]
    pub mod pending {
        #[doc = "Register `PENDING[%s]` reader"]
        pub type R = crate::R<PENDING_SPEC>;
        #[doc = "Register `PENDING[%s]` writer"]
        pub type W = crate::W<PENDING_SPEC>;
        #[doc = "Field `INTERRUPT` reader - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit."]
        pub type INTERRUPT_R = crate::FieldReader<u32>;
        #[doc = "Field `INTERRUPT` writer - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit."]
        pub type INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit."]
            #[inline(always)]
            pub fn interrupt(&self) -> INTERRUPT_R {
                INTERRUPT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit."]
            #[inline(always)]
            #[must_use]
            pub fn interrupt(&mut self) -> INTERRUPT_W<PENDING_SPEC> {
                INTERRUPT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PENDING_SPEC;
        impl crate::RegisterSpec for PENDING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pending::R`](R) reader structure"]
        impl crate::Readable for PENDING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pending::W`](W) writer structure"]
        impl crate::Writable for PENDING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PENDING[%s]
to value 0"]
        impl crate::Resettable for PENDING_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TRIGGER (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigger::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigger`]
module"]
    pub type TRIGGER = crate::Reg<trigger::TRIGGER_SPEC>;
    #[doc = "no description available"]
    pub mod trigger {
        #[doc = "Register `TRIGGER[%s]` reader"]
        pub type R = crate::R<TRIGGER_SPEC>;
        #[doc = "Register `TRIGGER[%s]` writer"]
        pub type W = crate::W<TRIGGER_SPEC>;
        #[doc = "Field `INTERRUPT` reader - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. 0: Level-triggered interrupt 1: Edge-triggered interrupt"]
        pub type INTERRUPT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. 0: Level-triggered interrupt 1: Edge-triggered interrupt"]
            #[inline(always)]
            pub fn interrupt(&self) -> INTERRUPT_R {
                INTERRUPT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trigger::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trigger::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRIGGER_SPEC;
        impl crate::RegisterSpec for TRIGGER_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trigger::R`](R) reader structure"]
        impl crate::Readable for TRIGGER_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trigger::W`](W) writer structure"]
        impl crate::Writable for TRIGGER_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TRIGGER[%s]
to value 0"]
        impl crate::Resettable for TRIGGER_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "NUMBER (rw) register accessor: Number of supported interrupt sources and targets\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`number::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`number::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@number`]
module"]
    pub type NUMBER = crate::Reg<number::NUMBER_SPEC>;
    #[doc = "Number of supported interrupt sources and targets"]
    pub mod number {
        #[doc = "Register `NUMBER` reader"]
        pub type R = crate::R<NUMBER_SPEC>;
        #[doc = "Register `NUMBER` writer"]
        pub type W = crate::W<NUMBER_SPEC>;
        #[doc = "Field `NUM_INTERRUPT` reader - The number of supported interrupt sources"]
        pub type NUM_INTERRUPT_R = crate::FieldReader<u16>;
        #[doc = "Field `NUM_TARGET` reader - The number of supported targets"]
        pub type NUM_TARGET_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - The number of supported interrupt sources"]
            #[inline(always)]
            pub fn num_interrupt(&self) -> NUM_INTERRUPT_R {
                NUM_INTERRUPT_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - The number of supported targets"]
            #[inline(always)]
            pub fn num_target(&self) -> NUM_TARGET_R {
                NUM_TARGET_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Number of supported interrupt sources and targets\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`number::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`number::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct NUMBER_SPEC;
        impl crate::RegisterSpec for NUMBER_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`number::R`](R) reader structure"]
        impl crate::Readable for NUMBER_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`number::W`](W) writer structure"]
        impl crate::Writable for NUMBER_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets NUMBER to value 0"]
        impl crate::Resettable for NUMBER_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INFO (rw) register accessor: Version and the maximum priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`info::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`info::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@info`]
module"]
    pub type INFO = crate::Reg<info::INFO_SPEC>;
    #[doc = "Version and the maximum priority"]
    pub mod info {
        #[doc = "Register `INFO` reader"]
        pub type R = crate::R<INFO_SPEC>;
        #[doc = "Register `INFO` writer"]
        pub type W = crate::W<INFO_SPEC>;
        #[doc = "Field `VERSION` reader - The version of the PLIC design"]
        pub type VERSION_R = crate::FieldReader<u16>;
        #[doc = "Field `MAX_PRIORITY` reader - The maximum priority supported"]
        pub type MAX_PRIORITY_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - The version of the PLIC design"]
            #[inline(always)]
            pub fn version(&self) -> VERSION_R {
                VERSION_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - The maximum priority supported"]
            #[inline(always)]
            pub fn max_priority(&self) -> MAX_PRIORITY_R {
                MAX_PRIORITY_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Version and the maximum priority\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`info::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`info::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INFO_SPEC;
        impl crate::RegisterSpec for INFO_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`info::R`](R) reader structure"]
        impl crate::Readable for INFO_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`info::W`](W) writer structure"]
        impl crate::Writable for INFO_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INFO to value 0"]
        impl crate::Resettable for INFO_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::targetint::TARGETINT;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod targetint {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct TARGETINT {
            inten: [INTEN; 4],
        }
        impl TARGETINT {
            #[doc = "0x00..0x10 - no description available"]
            #[inline(always)]
            pub const fn inten(&self, n: usize) -> &INTEN {
                &self.inten[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x00..0x10 - no description available"]
            #[inline(always)]
            pub fn inten_iter(&self) -> impl Iterator<Item = &INTEN> {
                self.inten.iter()
            }
            #[doc = "0x00 - no description available"]
            #[inline(always)]
            pub const fn inteninten0(&self) -> &INTEN {
                self.inten(0)
            }
            #[doc = "0x04 - no description available"]
            #[inline(always)]
            pub const fn inteninten1(&self) -> &INTEN {
                self.inten(1)
            }
            #[doc = "0x08 - no description available"]
            #[inline(always)]
            pub const fn inteninten2(&self) -> &INTEN {
                self.inten(2)
            }
            #[doc = "0x0c - no description available"]
            #[inline(always)]
            pub const fn inteninten3(&self) -> &INTEN {
                self.inten(3)
            }
        }
        #[doc = "INTEN (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
module"]
        pub type INTEN = crate::Reg<inten::INTEN_SPEC>;
        #[doc = "no description available"]
        pub mod inten {
            #[doc = "Register `INTEN[%s]` reader"]
            pub type R = crate::R<INTEN_SPEC>;
            #[doc = "Register `INTEN[%s]` writer"]
            pub type W = crate::W<INTEN_SPEC>;
            #[doc = "Field `INTERRUPT` reader - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit."]
            pub type INTERRUPT_R = crate::FieldReader<u32>;
            #[doc = "Field `INTERRUPT` writer - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit."]
            pub type INTERRUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit."]
                #[inline(always)]
                pub fn interrupt(&self) -> INTERRUPT_R {
                    INTERRUPT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit."]
                #[inline(always)]
                #[must_use]
                pub fn interrupt(&mut self) -> INTERRUPT_W<INTEN_SPEC> {
                    INTERRUPT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INTEN_SPEC;
            impl crate::RegisterSpec for INTEN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`inten::R`](R) reader structure"]
            impl crate::Readable for INTEN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
            impl crate::Writable for INTEN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INTEN[%s]
to value 0"]
            impl crate::Resettable for INTEN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::targetconfig::TARGETCONFIG;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod targetconfig {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct TARGETCONFIG {
            threshold: THRESHOLD,
            claim: CLAIM,
            _reserved2: [u8; 0x03f8],
            pps: PPS,
        }
        impl TARGETCONFIG {
            #[doc = "0x00 - Target0 priority threshold"]
            #[inline(always)]
            pub const fn threshold(&self) -> &THRESHOLD {
                &self.threshold
            }
            #[doc = "0x04 - Target claim and complete"]
            #[inline(always)]
            pub const fn claim(&self) -> &CLAIM {
                &self.claim
            }
            #[doc = "0x400 - Preempted priority stack"]
            #[inline(always)]
            pub const fn pps(&self) -> &PPS {
                &self.pps
            }
        }
        #[doc = "THRESHOLD (rw) register accessor: Target0 priority threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@threshold`]
module"]
        pub type THRESHOLD = crate::Reg<threshold::THRESHOLD_SPEC>;
        #[doc = "Target0 priority threshold"]
        pub mod threshold {
            #[doc = "Register `THRESHOLD` reader"]
            pub type R = crate::R<THRESHOLD_SPEC>;
            #[doc = "Register `THRESHOLD` writer"]
            pub type W = crate::W<THRESHOLD_SPEC>;
            #[doc = "Field `THRESHOLD` reader - Interrupt priority threshold."]
            pub type THRESHOLD_R = crate::FieldReader<u32>;
            #[doc = "Field `THRESHOLD` writer - Interrupt priority threshold."]
            pub type THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Interrupt priority threshold."]
                #[inline(always)]
                pub fn threshold(&self) -> THRESHOLD_R {
                    THRESHOLD_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Interrupt priority threshold."]
                #[inline(always)]
                #[must_use]
                pub fn threshold(&mut self) -> THRESHOLD_W<THRESHOLD_SPEC> {
                    THRESHOLD_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Target0 priority threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`threshold::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`threshold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct THRESHOLD_SPEC;
            impl crate::RegisterSpec for THRESHOLD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`threshold::R`](R) reader structure"]
            impl crate::Readable for THRESHOLD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`threshold::W`](W) writer structure"]
            impl crate::Writable for THRESHOLD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets THRESHOLD to value 0"]
            impl crate::Resettable for THRESHOLD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLAIM (rw) register accessor: Target claim and complete\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claim`]
module"]
        pub type CLAIM = crate::Reg<claim::CLAIM_SPEC>;
        #[doc = "Target claim and complete"]
        pub mod claim {
            #[doc = "Register `CLAIM` reader"]
            pub type R = crate::R<CLAIM_SPEC>;
            #[doc = "Register `CLAIM` writer"]
            pub type W = crate::W<CLAIM_SPEC>;
            #[doc = "Field `INTERRUPT_ID` reader - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
            pub type INTERRUPT_ID_R = crate::FieldReader<u16>;
            #[doc = "Field `INTERRUPT_ID` writer - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
            pub type INTERRUPT_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
            impl R {
                #[doc = "Bits 0:9 - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
                #[inline(always)]
                pub fn interrupt_id(&self) -> INTERRUPT_ID_R {
                    INTERRUPT_ID_R::new((self.bits & 0x03ff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:9 - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
                #[inline(always)]
                #[must_use]
                pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<CLAIM_SPEC> {
                    INTERRUPT_ID_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Target claim and complete\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claim::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLAIM_SPEC;
            impl crate::RegisterSpec for CLAIM_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`claim::R`](R) reader structure"]
            impl crate::Readable for CLAIM_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`claim::W`](W) writer structure"]
            impl crate::Writable for CLAIM_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLAIM to value 0"]
            impl crate::Resettable for CLAIM_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "PPS (rw) register accessor: Preempted priority stack\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pps::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pps::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pps`]
module"]
        pub type PPS = crate::Reg<pps::PPS_SPEC>;
        #[doc = "Preempted priority stack"]
        pub mod pps {
            #[doc = "Register `PPS` reader"]
            pub type R = crate::R<PPS_SPEC>;
            #[doc = "Register `PPS` writer"]
            pub type W = crate::W<PPS_SPEC>;
            #[doc = "Field `PRIORITY_PREEMPTED` reader - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt."]
            pub type PRIORITY_PREEMPTED_R = crate::FieldReader<u32>;
            #[doc = "Field `PRIORITY_PREEMPTED` writer - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt."]
            pub type PRIORITY_PREEMPTED_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt."]
                #[inline(always)]
                pub fn priority_preempted(&self) -> PRIORITY_PREEMPTED_R {
                    PRIORITY_PREEMPTED_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt."]
                #[inline(always)]
                #[must_use]
                pub fn priority_preempted(&mut self) -> PRIORITY_PREEMPTED_W<PPS_SPEC> {
                    PRIORITY_PREEMPTED_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Preempted priority stack\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pps::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pps::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PPS_SPEC;
            impl crate::RegisterSpec for PPS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pps::R`](R) reader structure"]
            impl crate::Readable for PPS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pps::W`](W) writer structure"]
            impl crate::Writable for PPS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PPS to value 0"]
            impl crate::Resettable for PPS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "MCHTMR"]
pub struct MCHTMR {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MCHTMR {}
impl MCHTMR {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mchtmr::RegisterBlock = 0xe600_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mchtmr::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MCHTMR {
    type Target = mchtmr::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MCHTMR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MCHTMR").finish()
    }
}
#[doc = "MCHTMR"]
pub mod mchtmr {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        mtime: MTIME,
        mtimecmp: MTIMECMP,
    }
    impl RegisterBlock {
        #[doc = "0x00..0x08 - Machine Time"]
        #[inline(always)]
        pub const fn mtime(&self) -> &MTIME {
            &self.mtime
        }
        #[doc = "0x08..0x10 - Machine Time Compare"]
        #[inline(always)]
        pub const fn mtimecmp(&self) -> &MTIMECMP {
            &self.mtimecmp
        }
    }
    #[doc = "MTIME (rw) register accessor: Machine Time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtime::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime`]
module"]
    pub type MTIME = crate::Reg<mtime::MTIME_SPEC>;
    #[doc = "Machine Time"]
    pub mod mtime {
        #[doc = "Register `MTIME` reader"]
        pub type R = crate::R<MTIME_SPEC>;
        #[doc = "Register `MTIME` writer"]
        pub type W = crate::W<MTIME_SPEC>;
        #[doc = "Field `MTIME` reader - Machine time"]
        pub type MTIME_R = crate::FieldReader<u64>;
        #[doc = "Field `MTIME` writer - Machine time"]
        pub type MTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 64, u64>;
        impl R {
            #[doc = "Bits 0:63 - Machine time"]
            #[inline(always)]
            pub fn mtime(&self) -> MTIME_R {
                MTIME_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:63 - Machine time"]
            #[inline(always)]
            #[must_use]
            pub fn mtime(&mut self) -> MTIME_W<MTIME_SPEC> {
                MTIME_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u64) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Machine Time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtime::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtime::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MTIME_SPEC;
        impl crate::RegisterSpec for MTIME_SPEC {
            type Ux = u64;
        }
        #[doc = "`read()` method returns [`mtime::R`](R) reader structure"]
        impl crate::Readable for MTIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`mtime::W`](W) writer structure"]
        impl crate::Writable for MTIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
        }
        #[doc = "`reset()` method sets MTIME to value 0x0002_0210"]
        impl crate::Resettable for MTIME_SPEC {
            const RESET_VALUE: u64 = 0x0002_0210;
        }
    }
    #[doc = "MTIMECMP (rw) register accessor: Machine Time Compare\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp`]
module"]
    pub type MTIMECMP = crate::Reg<mtimecmp::MTIMECMP_SPEC>;
    #[doc = "Machine Time Compare"]
    pub mod mtimecmp {
        #[doc = "Register `MTIMECMP` reader"]
        pub type R = crate::R<MTIMECMP_SPEC>;
        #[doc = "Register `MTIMECMP` writer"]
        pub type W = crate::W<MTIMECMP_SPEC>;
        #[doc = "Field `MTIMECMP` reader - Machine time compare"]
        pub type MTIMECMP_R = crate::FieldReader<u64>;
        #[doc = "Field `MTIMECMP` writer - Machine time compare"]
        pub type MTIMECMP_W<'a, REG> = crate::FieldWriter<'a, REG, 64, u64>;
        impl R {
            #[doc = "Bits 0:63 - Machine time compare"]
            #[inline(always)]
            pub fn mtimecmp(&self) -> MTIMECMP_R {
                MTIMECMP_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:63 - Machine time compare"]
            #[inline(always)]
            #[must_use]
            pub fn mtimecmp(&mut self) -> MTIMECMP_W<MTIMECMP_SPEC> {
                MTIMECMP_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u64) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Machine Time Compare\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtimecmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtimecmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MTIMECMP_SPEC;
        impl crate::RegisterSpec for MTIMECMP_SPEC {
            type Ux = u64;
        }
        #[doc = "`read()` method returns [`mtimecmp::R`](R) reader structure"]
        impl crate::Readable for MTIMECMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`mtimecmp::W`](W) writer structure"]
        impl crate::Writable for MTIMECMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
        }
        #[doc = "`reset()` method sets MTIMECMP to value 0x0002_0210"]
        impl crate::Resettable for MTIMECMP_SPEC {
            const RESET_VALUE: u64 = 0x0002_0210;
        }
    }
}
#[doc = "PLICSW"]
pub struct PLICSW {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PLICSW {}
impl PLICSW {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const plicsw::RegisterBlock = 0xe640_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const plicsw::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PLICSW {
    type Target = plicsw::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PLICSW {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PLICSW").finish()
    }
}
#[doc = "PLICSW"]
pub mod plicsw {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x1000],
        pending: PENDING,
        _reserved1: [u8; 0x0ffc],
        inten: INTEN,
        _reserved2: [u8; 0x001f_e000],
        claim: CLAIM,
    }
    impl RegisterBlock {
        #[doc = "0x1000 - Pending status"]
        #[inline(always)]
        pub const fn pending(&self) -> &PENDING {
            &self.pending
        }
        #[doc = "0x2000 - Interrupt enable"]
        #[inline(always)]
        pub const fn inten(&self) -> &INTEN {
            &self.inten
        }
        #[doc = "0x200004 - Claim and complete."]
        #[inline(always)]
        pub const fn claim(&self) -> &CLAIM {
            &self.claim
        }
    }
    #[doc = "PENDING (rw) register accessor: Pending status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pending`]
module"]
    pub type PENDING = crate::Reg<pending::PENDING_SPEC>;
    #[doc = "Pending status"]
    pub mod pending {
        #[doc = "Register `PENDING` reader"]
        pub type R = crate::R<PENDING_SPEC>;
        #[doc = "Register `PENDING` writer"]
        pub type W = crate::W<PENDING_SPEC>;
        #[doc = "Field `INTERRUPT` reader - writing 1 to trigger software interrupt"]
        pub type INTERRUPT_R = crate::BitReader;
        #[doc = "Field `INTERRUPT` writer - writing 1 to trigger software interrupt"]
        pub type INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 1 - writing 1 to trigger software interrupt"]
            #[inline(always)]
            pub fn interrupt(&self) -> INTERRUPT_R {
                INTERRUPT_R::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 1 - writing 1 to trigger software interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn interrupt(&mut self) -> INTERRUPT_W<PENDING_SPEC> {
                INTERRUPT_W::new(self, 1)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Pending status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pending::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pending::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PENDING_SPEC;
        impl crate::RegisterSpec for PENDING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pending::R`](R) reader structure"]
        impl crate::Readable for PENDING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pending::W`](W) writer structure"]
        impl crate::Writable for PENDING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PENDING to value 0"]
        impl crate::Resettable for PENDING_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INTEN (rw) register accessor: Interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
module"]
    pub type INTEN = crate::Reg<inten::INTEN_SPEC>;
    #[doc = "Interrupt enable"]
    pub mod inten {
        #[doc = "Register `INTEN` reader"]
        pub type R = crate::R<INTEN_SPEC>;
        #[doc = "Register `INTEN` writer"]
        pub type W = crate::W<INTEN_SPEC>;
        #[doc = "Field `INTERRUPT` reader - enable software interrupt"]
        pub type INTERRUPT_R = crate::BitReader;
        #[doc = "Field `INTERRUPT` writer - enable software interrupt"]
        pub type INTERRUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - enable software interrupt"]
            #[inline(always)]
            pub fn interrupt(&self) -> INTERRUPT_R {
                INTERRUPT_R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - enable software interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn interrupt(&mut self) -> INTERRUPT_W<INTEN_SPEC> {
                INTERRUPT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inten::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INTEN_SPEC;
        impl crate::RegisterSpec for INTEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`inten::R`](R) reader structure"]
        impl crate::Readable for INTEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
        impl crate::Writable for INTEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INTEN to value 0"]
        impl crate::Resettable for INTEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CLAIM (rw) register accessor: Claim and complete.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@claim`]
module"]
    pub type CLAIM = crate::Reg<claim::CLAIM_SPEC>;
    #[doc = "Claim and complete."]
    pub mod claim {
        #[doc = "Register `CLAIM` reader"]
        pub type R = crate::R<CLAIM_SPEC>;
        #[doc = "Register `CLAIM` writer"]
        pub type W = crate::W<CLAIM_SPEC>;
        #[doc = "Field `INTERRUPT_ID` reader - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
        pub type INTERRUPT_ID_R = crate::BitReader;
        #[doc = "Field `INTERRUPT_ID` writer - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
        pub type INTERRUPT_ID_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
            #[inline(always)]
            pub fn interrupt_id(&self) -> INTERRUPT_ID_R {
                INTERRUPT_ID_R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed)."]
            #[inline(always)]
            #[must_use]
            pub fn interrupt_id(&mut self) -> INTERRUPT_ID_W<CLAIM_SPEC> {
                INTERRUPT_ID_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Claim and complete.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`claim::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`claim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CLAIM_SPEC;
        impl crate::RegisterSpec for CLAIM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`claim::R`](R) reader structure"]
        impl crate::Readable for CLAIM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`claim::W`](W) writer structure"]
        impl crate::Writable for CLAIM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CLAIM to value 0"]
        impl crate::Resettable for CLAIM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "GPTMR0"]
pub struct GPTMR0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPTMR0 {}
impl GPTMR0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const gptmr0::RegisterBlock = 0xf000_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const gptmr0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for GPTMR0 {
    type Target = gptmr0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for GPTMR0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPTMR0").finish()
    }
}
#[doc = "GPTMR0"]
pub mod gptmr0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        channel: (),
        _reserved1: [u8; 0x0200],
        sr: SR,
        irqen: IRQEN,
        gcr: GCR,
    }
    impl RegisterBlock {
        #[doc = "0x00..0xd0 - no description available"]
        #[inline(always)]
        pub const fn channel(&self, n: usize) -> &CHANNEL {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe { &*(self as *const Self).cast::<u8>().add(0).add(64 * n).cast() }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0xd0 - no description available"]
        #[inline(always)]
        pub fn channel_iter(&self) -> impl Iterator<Item = &CHANNEL> {
            (0..4).map(move |n| unsafe {
                &*(self as *const Self).cast::<u8>().add(0).add(64 * n).cast()
            })
        }
        #[doc = "0x00..0x34 - no description available"]
        #[inline(always)]
        pub const fn channelch0(&self) -> &CHANNEL {
            self.channel(0)
        }
        #[doc = "0x40..0x74 - no description available"]
        #[inline(always)]
        pub const fn channelch1(&self) -> &CHANNEL {
            self.channel(1)
        }
        #[doc = "0x80..0xb4 - no description available"]
        #[inline(always)]
        pub const fn channelch2(&self) -> &CHANNEL {
            self.channel(2)
        }
        #[doc = "0xc0..0xf4 - no description available"]
        #[inline(always)]
        pub const fn channelch3(&self) -> &CHANNEL {
            self.channel(3)
        }
        #[doc = "0x200 - Status register"]
        #[inline(always)]
        pub const fn sr(&self) -> &SR {
            &self.sr
        }
        #[doc = "0x204 - Interrupt request enable register"]
        #[inline(always)]
        pub const fn irqen(&self) -> &IRQEN {
            &self.irqen
        }
        #[doc = "0x208 - Global control register"]
        #[inline(always)]
        pub const fn gcr(&self) -> &GCR {
            &self.gcr
        }
    }
    #[doc = "no description available"]
    pub use self::channel::CHANNEL;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod channel {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct CHANNEL {
            cr: CR,
            cmp: [CMP; 2],
            rld: RLD,
            cntuptval: CNTUPTVAL,
            _reserved4: [u8; 0x0c],
            cappos: CAPPOS,
            capneg: CAPNEG,
            capprd: CAPPRD,
            capdty: CAPDTY,
            cnt: CNT,
        }
        impl CHANNEL {
            #[doc = "0x00 - Control Register"]
            #[inline(always)]
            pub const fn cr(&self) -> &CR {
                &self.cr
            }
            #[doc = "0x04..0x0c - no description available"]
            #[inline(always)]
            pub const fn cmp(&self, n: usize) -> &CMP {
                &self.cmp[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x04..0x0c - no description available"]
            #[inline(always)]
            pub fn cmp_iter(&self) -> impl Iterator<Item = &CMP> {
                self.cmp.iter()
            }
            #[doc = "0x04 - no description available"]
            #[inline(always)]
            pub const fn cmpcmp0(&self) -> &CMP {
                self.cmp(0)
            }
            #[doc = "0x08 - no description available"]
            #[inline(always)]
            pub const fn cmpcmp1(&self) -> &CMP {
                self.cmp(1)
            }
            #[doc = "0x0c - Reload register"]
            #[inline(always)]
            pub const fn rld(&self) -> &RLD {
                &self.rld
            }
            #[doc = "0x10 - Counter update value register"]
            #[inline(always)]
            pub const fn cntuptval(&self) -> &CNTUPTVAL {
                &self.cntuptval
            }
            #[doc = "0x20 - Capture rising edge register"]
            #[inline(always)]
            pub const fn cappos(&self) -> &CAPPOS {
                &self.cappos
            }
            #[doc = "0x24 - Capture falling edge register"]
            #[inline(always)]
            pub const fn capneg(&self) -> &CAPNEG {
                &self.capneg
            }
            #[doc = "0x28 - PWM period measure register"]
            #[inline(always)]
            pub const fn capprd(&self) -> &CAPPRD {
                &self.capprd
            }
            #[doc = "0x2c - PWM duty cycle measure register"]
            #[inline(always)]
            pub const fn capdty(&self) -> &CAPDTY {
                &self.capdty
            }
            #[doc = "0x30 - Counter"]
            #[inline(always)]
            pub const fn cnt(&self) -> &CNT {
                &self.cnt
            }
        }
        #[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
        pub type CR = crate::Reg<cr::CR_SPEC>;
        #[doc = "Control Register"]
        pub mod cr {
            #[doc = "Register `CR` reader"]
            pub type R = crate::R<CR_SPEC>;
            #[doc = "Register `CR` writer"]
            pub type W = crate::W<CR_SPEC>;
            #[doc = "Field `CAPMODE` reader - This bitfield define the input capture mode 100: width measure mode, timer will calculate the input signal period and duty cycle 011: capture at both rising edge and falling edge 010: capture at falling edge 001: capture at rising edge 000: No capture"]
            pub type CAPMODE_R = crate::FieldReader;
            #[doc = "Field `CAPMODE` writer - This bitfield define the input capture mode 100: width measure mode, timer will calculate the input signal period and duty cycle 011: capture at both rising edge and falling edge 010: capture at falling edge 001: capture at rising edge 000: No capture"]
            pub type CAPMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `DBGPAUSE` reader - 1- counter will pause if chip is in debug mode"]
            pub type DBGPAUSE_R = crate::BitReader;
            #[doc = "Field `DBGPAUSE` writer - 1- counter will pause if chip is in debug mode"]
            pub type DBGPAUSE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SWSYNCIEN` reader - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set"]
            pub type SWSYNCIEN_R = crate::BitReader;
            #[doc = "Field `SWSYNCIEN` writer - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set"]
            pub type SWSYNCIEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DMAEN` reader - 1- enable dma"]
            pub type DMAEN_R = crate::BitReader;
            #[doc = "Field `DMAEN` writer - 1- enable dma"]
            pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DMASEL` reader - select one of DMA request: 00- CMP0 flag 01- CMP1 flag 10- Input signal toggle captured 11- RLD flag, counter reload;"]
            pub type DMASEL_R = crate::FieldReader;
            #[doc = "Field `DMASEL` writer - select one of DMA request: 00- CMP0 flag 01- CMP1 flag 10- Input signal toggle captured 11- RLD flag, counter reload;"]
            pub type DMASEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `CMPEN` reader - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings."]
            pub type CMPEN_R = crate::BitReader;
            #[doc = "Field `CMPEN` writer - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings."]
            pub type CMPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CMPINIT` reader - Output compare initial poliarity 1- The channel output initial level is high 0- The channel output initial level is low User should set this bit before set CMPEN to 1."]
            pub type CMPINIT_R = crate::BitReader;
            #[doc = "Field `CMPINIT` writer - Output compare initial poliarity 1- The channel output initial level is high 0- The channel output initial level is low User should set this bit before set CMPEN to 1."]
            pub type CMPINIT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CEN` reader - 1- counter enable"]
            pub type CEN_R = crate::BitReader;
            #[doc = "Field `CEN` writer - 1- counter enable"]
            pub type CEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SYNCIREN` reader - 1- SYNCI is valid on its rising edge"]
            pub type SYNCIREN_R = crate::BitReader;
            #[doc = "Field `SYNCIREN` writer - 1- SYNCI is valid on its rising edge"]
            pub type SYNCIREN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SYNCIFEN` reader - 1- SYNCI is valid on its falling edge"]
            pub type SYNCIFEN_R = crate::BitReader;
            #[doc = "Field `SYNCIFEN` writer - 1- SYNCI is valid on its falling edge"]
            pub type SYNCIFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SYNCFLW` reader - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. This bit is not valid for channel 0."]
            pub type SYNCFLW_R = crate::BitReader;
            #[doc = "Field `SYNCFLW` writer - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. This bit is not valid for channel 0."]
            pub type SYNCFLW_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CNTRST` reader - 1- reset counter"]
            pub type CNTRST_R = crate::BitReader;
            #[doc = "Field `CNTRST` writer - 1- reset counter"]
            pub type CNTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CNTUPT` writer - 1- update counter to new value as CNTUPTVAL This bit will be auto cleared after 1 cycle"]
            pub type CNTUPT_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:2 - This bitfield define the input capture mode 100: width measure mode, timer will calculate the input signal period and duty cycle 011: capture at both rising edge and falling edge 010: capture at falling edge 001: capture at rising edge 000: No capture"]
                #[inline(always)]
                pub fn capmode(&self) -> CAPMODE_R {
                    CAPMODE_R::new((self.bits & 7) as u8)
                }
                #[doc = "Bit 3 - 1- counter will pause if chip is in debug mode"]
                #[inline(always)]
                pub fn dbgpause(&self) -> DBGPAUSE_R {
                    DBGPAUSE_R::new(((self.bits >> 3) & 1) != 0)
                }
                #[doc = "Bit 4 - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set"]
                #[inline(always)]
                pub fn swsyncien(&self) -> SWSYNCIEN_R {
                    SWSYNCIEN_R::new(((self.bits >> 4) & 1) != 0)
                }
                #[doc = "Bit 5 - 1- enable dma"]
                #[inline(always)]
                pub fn dmaen(&self) -> DMAEN_R {
                    DMAEN_R::new(((self.bits >> 5) & 1) != 0)
                }
                #[doc = "Bits 6:7 - select one of DMA request: 00- CMP0 flag 01- CMP1 flag 10- Input signal toggle captured 11- RLD flag, counter reload;"]
                #[inline(always)]
                pub fn dmasel(&self) -> DMASEL_R {
                    DMASEL_R::new(((self.bits >> 6) & 3) as u8)
                }
                #[doc = "Bit 8 - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings."]
                #[inline(always)]
                pub fn cmpen(&self) -> CMPEN_R {
                    CMPEN_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - Output compare initial poliarity 1- The channel output initial level is high 0- The channel output initial level is low User should set this bit before set CMPEN to 1."]
                #[inline(always)]
                pub fn cmpinit(&self) -> CMPINIT_R {
                    CMPINIT_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - 1- counter enable"]
                #[inline(always)]
                pub fn cen(&self) -> CEN_R {
                    CEN_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 11 - 1- SYNCI is valid on its rising edge"]
                #[inline(always)]
                pub fn synciren(&self) -> SYNCIREN_R {
                    SYNCIREN_R::new(((self.bits >> 11) & 1) != 0)
                }
                #[doc = "Bit 12 - 1- SYNCI is valid on its falling edge"]
                #[inline(always)]
                pub fn syncifen(&self) -> SYNCIFEN_R {
                    SYNCIFEN_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bit 13 - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. This bit is not valid for channel 0."]
                #[inline(always)]
                pub fn syncflw(&self) -> SYNCFLW_R {
                    SYNCFLW_R::new(((self.bits >> 13) & 1) != 0)
                }
                #[doc = "Bit 14 - 1- reset counter"]
                #[inline(always)]
                pub fn cntrst(&self) -> CNTRST_R {
                    CNTRST_R::new(((self.bits >> 14) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:2 - This bitfield define the input capture mode 100: width measure mode, timer will calculate the input signal period and duty cycle 011: capture at both rising edge and falling edge 010: capture at falling edge 001: capture at rising edge 000: No capture"]
                #[inline(always)]
                #[must_use]
                pub fn capmode(&mut self) -> CAPMODE_W<CR_SPEC> {
                    CAPMODE_W::new(self, 0)
                }
                #[doc = "Bit 3 - 1- counter will pause if chip is in debug mode"]
                #[inline(always)]
                #[must_use]
                pub fn dbgpause(&mut self) -> DBGPAUSE_W<CR_SPEC> {
                    DBGPAUSE_W::new(self, 3)
                }
                #[doc = "Bit 4 - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set"]
                #[inline(always)]
                #[must_use]
                pub fn swsyncien(&mut self) -> SWSYNCIEN_W<CR_SPEC> {
                    SWSYNCIEN_W::new(self, 4)
                }
                #[doc = "Bit 5 - 1- enable dma"]
                #[inline(always)]
                #[must_use]
                pub fn dmaen(&mut self) -> DMAEN_W<CR_SPEC> {
                    DMAEN_W::new(self, 5)
                }
                #[doc = "Bits 6:7 - select one of DMA request: 00- CMP0 flag 01- CMP1 flag 10- Input signal toggle captured 11- RLD flag, counter reload;"]
                #[inline(always)]
                #[must_use]
                pub fn dmasel(&mut self) -> DMASEL_W<CR_SPEC> {
                    DMASEL_W::new(self, 6)
                }
                #[doc = "Bit 8 - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings."]
                #[inline(always)]
                #[must_use]
                pub fn cmpen(&mut self) -> CMPEN_W<CR_SPEC> {
                    CMPEN_W::new(self, 8)
                }
                #[doc = "Bit 9 - Output compare initial poliarity 1- The channel output initial level is high 0- The channel output initial level is low User should set this bit before set CMPEN to 1."]
                #[inline(always)]
                #[must_use]
                pub fn cmpinit(&mut self) -> CMPINIT_W<CR_SPEC> {
                    CMPINIT_W::new(self, 9)
                }
                #[doc = "Bit 10 - 1- counter enable"]
                #[inline(always)]
                #[must_use]
                pub fn cen(&mut self) -> CEN_W<CR_SPEC> {
                    CEN_W::new(self, 10)
                }
                #[doc = "Bit 11 - 1- SYNCI is valid on its rising edge"]
                #[inline(always)]
                #[must_use]
                pub fn synciren(&mut self) -> SYNCIREN_W<CR_SPEC> {
                    SYNCIREN_W::new(self, 11)
                }
                #[doc = "Bit 12 - 1- SYNCI is valid on its falling edge"]
                #[inline(always)]
                #[must_use]
                pub fn syncifen(&mut self) -> SYNCIFEN_W<CR_SPEC> {
                    SYNCIFEN_W::new(self, 12)
                }
                #[doc = "Bit 13 - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. This bit is not valid for channel 0."]
                #[inline(always)]
                #[must_use]
                pub fn syncflw(&mut self) -> SYNCFLW_W<CR_SPEC> {
                    SYNCFLW_W::new(self, 13)
                }
                #[doc = "Bit 14 - 1- reset counter"]
                #[inline(always)]
                #[must_use]
                pub fn cntrst(&mut self) -> CNTRST_W<CR_SPEC> {
                    CNTRST_W::new(self, 14)
                }
                #[doc = "Bit 31 - 1- update counter to new value as CNTUPTVAL This bit will be auto cleared after 1 cycle"]
                #[inline(always)]
                #[must_use]
                pub fn cntupt(&mut self) -> CNTUPT_W<CR_SPEC> {
                    CNTUPT_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CR_SPEC;
            impl crate::RegisterSpec for CR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cr::R`](R) reader structure"]
            impl crate::Readable for CR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
            impl crate::Writable for CR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CR to value 0"]
            impl crate::Resettable for CR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CMP (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp`]
module"]
        pub type CMP = crate::Reg<cmp::CMP_SPEC>;
        #[doc = "no description available"]
        pub mod cmp {
            #[doc = "Register `CMP[%s]` reader"]
            pub type R = crate::R<CMP_SPEC>;
            #[doc = "Register `CMP[%s]` writer"]
            pub type W = crate::W<CMP_SPEC>;
            #[doc = "Field `CMP` reader - compare value 0"]
            pub type CMP_R = crate::FieldReader<u32>;
            #[doc = "Field `CMP` writer - compare value 0"]
            pub type CMP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - compare value 0"]
                #[inline(always)]
                pub fn cmp(&self) -> CMP_R {
                    CMP_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - compare value 0"]
                #[inline(always)]
                #[must_use]
                pub fn cmp(&mut self) -> CMP_W<CMP_SPEC> {
                    CMP_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CMP_SPEC;
            impl crate::RegisterSpec for CMP_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cmp::R`](R) reader structure"]
            impl crate::Readable for CMP_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cmp::W`](W) writer structure"]
            impl crate::Writable for CMP_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CMP[%s]
to value 0xffff_ffff"]
            impl crate::Resettable for CMP_SPEC {
                const RESET_VALUE: u32 = 0xffff_ffff;
            }
        }
        #[doc = "RLD (rw) register accessor: Reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rld::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rld::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rld`]
module"]
        pub type RLD = crate::Reg<rld::RLD_SPEC>;
        #[doc = "Reload register"]
        pub mod rld {
            #[doc = "Register `RLD` reader"]
            pub type R = crate::R<RLD_SPEC>;
            #[doc = "Register `RLD` writer"]
            pub type W = crate::W<RLD_SPEC>;
            #[doc = "Field `RLD` reader - reload value"]
            pub type RLD_R = crate::FieldReader<u32>;
            #[doc = "Field `RLD` writer - reload value"]
            pub type RLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - reload value"]
                #[inline(always)]
                pub fn rld(&self) -> RLD_R {
                    RLD_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - reload value"]
                #[inline(always)]
                #[must_use]
                pub fn rld(&mut self) -> RLD_W<RLD_SPEC> {
                    RLD_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rld::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rld::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct RLD_SPEC;
            impl crate::RegisterSpec for RLD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`rld::R`](R) reader structure"]
            impl crate::Readable for RLD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`rld::W`](W) writer structure"]
            impl crate::Writable for RLD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets RLD to value 0xffff_ffff"]
            impl crate::Resettable for RLD_SPEC {
                const RESET_VALUE: u32 = 0xffff_ffff;
            }
        }
        #[doc = "CNTUPTVAL (rw) register accessor: Counter update value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntuptval::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntuptval::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntuptval`]
module"]
        pub type CNTUPTVAL = crate::Reg<cntuptval::CNTUPTVAL_SPEC>;
        #[doc = "Counter update value register"]
        pub mod cntuptval {
            #[doc = "Register `CNTUPTVAL` reader"]
            pub type R = crate::R<CNTUPTVAL_SPEC>;
            #[doc = "Register `CNTUPTVAL` writer"]
            pub type W = crate::W<CNTUPTVAL_SPEC>;
            #[doc = "Field `CNTUPTVAL` reader - counter will be set to this value when software write cntupt bit in CR"]
            pub type CNTUPTVAL_R = crate::FieldReader<u32>;
            #[doc = "Field `CNTUPTVAL` writer - counter will be set to this value when software write cntupt bit in CR"]
            pub type CNTUPTVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - counter will be set to this value when software write cntupt bit in CR"]
                #[inline(always)]
                pub fn cntuptval(&self) -> CNTUPTVAL_R {
                    CNTUPTVAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - counter will be set to this value when software write cntupt bit in CR"]
                #[inline(always)]
                #[must_use]
                pub fn cntuptval(&mut self) -> CNTUPTVAL_W<CNTUPTVAL_SPEC> {
                    CNTUPTVAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Counter update value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntuptval::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntuptval::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CNTUPTVAL_SPEC;
            impl crate::RegisterSpec for CNTUPTVAL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cntuptval::R`](R) reader structure"]
            impl crate::Readable for CNTUPTVAL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cntuptval::W`](W) writer structure"]
            impl crate::Writable for CNTUPTVAL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CNTUPTVAL to value 0"]
            impl crate::Resettable for CNTUPTVAL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CAPPOS (rw) register accessor: Capture rising edge register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cappos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cappos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cappos`]
module"]
        pub type CAPPOS = crate::Reg<cappos::CAPPOS_SPEC>;
        #[doc = "Capture rising edge register"]
        pub mod cappos {
            #[doc = "Register `CAPPOS` reader"]
            pub type R = crate::R<CAPPOS_SPEC>;
            #[doc = "Register `CAPPOS` writer"]
            pub type W = crate::W<CAPPOS_SPEC>;
            #[doc = "Field `CAPPOS` reader - This register contains the counter value captured at input signal rising edge"]
            pub type CAPPOS_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - This register contains the counter value captured at input signal rising edge"]
                #[inline(always)]
                pub fn cappos(&self) -> CAPPOS_R {
                    CAPPOS_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Capture rising edge register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cappos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cappos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CAPPOS_SPEC;
            impl crate::RegisterSpec for CAPPOS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cappos::R`](R) reader structure"]
            impl crate::Readable for CAPPOS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cappos::W`](W) writer structure"]
            impl crate::Writable for CAPPOS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CAPPOS to value 0"]
            impl crate::Resettable for CAPPOS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CAPNEG (rw) register accessor: Capture falling edge register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capneg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capneg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capneg`]
module"]
        pub type CAPNEG = crate::Reg<capneg::CAPNEG_SPEC>;
        #[doc = "Capture falling edge register"]
        pub mod capneg {
            #[doc = "Register `CAPNEG` reader"]
            pub type R = crate::R<CAPNEG_SPEC>;
            #[doc = "Register `CAPNEG` writer"]
            pub type W = crate::W<CAPNEG_SPEC>;
            #[doc = "Field `CAPNEG` reader - This register contains the counter value captured at input signal falling edge"]
            pub type CAPNEG_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - This register contains the counter value captured at input signal falling edge"]
                #[inline(always)]
                pub fn capneg(&self) -> CAPNEG_R {
                    CAPNEG_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Capture falling edge register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capneg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capneg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CAPNEG_SPEC;
            impl crate::RegisterSpec for CAPNEG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`capneg::R`](R) reader structure"]
            impl crate::Readable for CAPNEG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`capneg::W`](W) writer structure"]
            impl crate::Writable for CAPNEG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CAPNEG to value 0"]
            impl crate::Resettable for CAPNEG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CAPPRD (rw) register accessor: PWM period measure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capprd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capprd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capprd`]
module"]
        pub type CAPPRD = crate::Reg<capprd::CAPPRD_SPEC>;
        #[doc = "PWM period measure register"]
        pub mod capprd {
            #[doc = "Register `CAPPRD` reader"]
            pub type R = crate::R<CAPPRD_SPEC>;
            #[doc = "Register `CAPPRD` writer"]
            pub type W = crate::W<CAPPRD_SPEC>;
            #[doc = "Field `CAPPRD` reader - This register contains the input signal period when channel is configured to input capture measure mode."]
            pub type CAPPRD_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - This register contains the input signal period when channel is configured to input capture measure mode."]
                #[inline(always)]
                pub fn capprd(&self) -> CAPPRD_R {
                    CAPPRD_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PWM period measure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capprd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capprd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CAPPRD_SPEC;
            impl crate::RegisterSpec for CAPPRD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`capprd::R`](R) reader structure"]
            impl crate::Readable for CAPPRD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`capprd::W`](W) writer structure"]
            impl crate::Writable for CAPPRD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CAPPRD to value 0"]
            impl crate::Resettable for CAPPRD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CAPDTY (rw) register accessor: PWM duty cycle measure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capdty::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capdty::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capdty`]
module"]
        pub type CAPDTY = crate::Reg<capdty::CAPDTY_SPEC>;
        #[doc = "PWM duty cycle measure register"]
        pub mod capdty {
            #[doc = "Register `CAPDTY` reader"]
            pub type R = crate::R<CAPDTY_SPEC>;
            #[doc = "Register `CAPDTY` writer"]
            pub type W = crate::W<CAPDTY_SPEC>;
            #[doc = "Field `MEAS_HIGH` reader - This register contains the input signal duty cycle when channel is configured to input capture measure mode."]
            pub type MEAS_HIGH_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - This register contains the input signal duty cycle when channel is configured to input capture measure mode."]
                #[inline(always)]
                pub fn meas_high(&self) -> MEAS_HIGH_R {
                    MEAS_HIGH_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PWM duty cycle measure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capdty::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capdty::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CAPDTY_SPEC;
            impl crate::RegisterSpec for CAPDTY_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`capdty::R`](R) reader structure"]
            impl crate::Readable for CAPDTY_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`capdty::W`](W) writer structure"]
            impl crate::Writable for CAPDTY_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CAPDTY to value 0"]
            impl crate::Resettable for CAPDTY_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CNT (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
        pub type CNT = crate::Reg<cnt::CNT_SPEC>;
        #[doc = "Counter"]
        pub mod cnt {
            #[doc = "Register `CNT` reader"]
            pub type R = crate::R<CNT_SPEC>;
            #[doc = "Register `CNT` writer"]
            pub type W = crate::W<CNT_SPEC>;
            #[doc = "Field `COUNTER` reader - 32 bit counter value"]
            pub type COUNTER_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - 32 bit counter value"]
                #[inline(always)]
                pub fn counter(&self) -> COUNTER_R {
                    COUNTER_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CNT_SPEC;
            impl crate::RegisterSpec for CNT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
            impl crate::Readable for CNT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
            impl crate::Writable for CNT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CNT to value 0"]
            impl crate::Resettable for CNT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "SR (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
    pub type SR = crate::Reg<sr::SR_SPEC>;
    #[doc = "Status register"]
    pub mod sr {
        #[doc = "Register `SR` reader"]
        pub type R = crate::R<SR_SPEC>;
        #[doc = "Register `SR` writer"]
        pub type W = crate::W<SR_SPEC>;
        #[doc = "Field `CH0RLDF` writer - channel 1 counter reload flag"]
        pub type CH0RLDF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH0CAPF` writer - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
        pub type CH0CAPF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH0CMP0F` writer - channel 1 compare value 1 match flag"]
        pub type CH0CMP0F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH0CMP1F` writer - channel 1 compare value 1 match flag"]
        pub type CH0CMP1F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1RLDF` writer - channel 1 counter reload flag"]
        pub type CH1RLDF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1CAPF` writer - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
        pub type CH1CAPF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1CMP0F` writer - channel 1 compare value 1 match flag"]
        pub type CH1CMP0F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1CMP1F` writer - channel 1 compare value 1 match flag"]
        pub type CH1CMP1F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2RLDF` writer - channel 2 counter reload flag"]
        pub type CH2RLDF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2CAPF` writer - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
        pub type CH2CAPF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2CMP0F` writer - channel 2 compare value 1 match flag"]
        pub type CH2CMP0F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2CMP1F` writer - channel 2 compare value 1 match flag"]
        pub type CH2CMP1F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3RLDF` writer - channel 3 counter reload flag"]
        pub type CH3RLDF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3CAPF` writer - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
        pub type CH3CAPF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3CMP0F` writer - channel 3 compare value 1 match flag"]
        pub type CH3CMP0F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3CMP1F` writer - channel 3 compare value 1 match flag"]
        pub type CH3CMP1F_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - channel 1 counter reload flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch0rldf(&mut self) -> CH0RLDF_W<SR_SPEC> {
                CH0RLDF_W::new(self, 0)
            }
            #[doc = "Bit 1 - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
            #[inline(always)]
            #[must_use]
            pub fn ch0capf(&mut self) -> CH0CAPF_W<SR_SPEC> {
                CH0CAPF_W::new(self, 1)
            }
            #[doc = "Bit 2 - channel 1 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch0cmp0f(&mut self) -> CH0CMP0F_W<SR_SPEC> {
                CH0CMP0F_W::new(self, 2)
            }
            #[doc = "Bit 3 - channel 1 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch0cmp1f(&mut self) -> CH0CMP1F_W<SR_SPEC> {
                CH0CMP1F_W::new(self, 3)
            }
            #[doc = "Bit 4 - channel 1 counter reload flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch1rldf(&mut self) -> CH1RLDF_W<SR_SPEC> {
                CH1RLDF_W::new(self, 4)
            }
            #[doc = "Bit 5 - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
            #[inline(always)]
            #[must_use]
            pub fn ch1capf(&mut self) -> CH1CAPF_W<SR_SPEC> {
                CH1CAPF_W::new(self, 5)
            }
            #[doc = "Bit 6 - channel 1 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch1cmp0f(&mut self) -> CH1CMP0F_W<SR_SPEC> {
                CH1CMP0F_W::new(self, 6)
            }
            #[doc = "Bit 7 - channel 1 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch1cmp1f(&mut self) -> CH1CMP1F_W<SR_SPEC> {
                CH1CMP1F_W::new(self, 7)
            }
            #[doc = "Bit 8 - channel 2 counter reload flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch2rldf(&mut self) -> CH2RLDF_W<SR_SPEC> {
                CH2RLDF_W::new(self, 8)
            }
            #[doc = "Bit 9 - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
            #[inline(always)]
            #[must_use]
            pub fn ch2capf(&mut self) -> CH2CAPF_W<SR_SPEC> {
                CH2CAPF_W::new(self, 9)
            }
            #[doc = "Bit 10 - channel 2 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch2cmp0f(&mut self) -> CH2CMP0F_W<SR_SPEC> {
                CH2CMP0F_W::new(self, 10)
            }
            #[doc = "Bit 11 - channel 2 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch2cmp1f(&mut self) -> CH2CMP1F_W<SR_SPEC> {
                CH2CMP1F_W::new(self, 11)
            }
            #[doc = "Bit 12 - channel 3 counter reload flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch3rldf(&mut self) -> CH3RLDF_W<SR_SPEC> {
                CH3RLDF_W::new(self, 12)
            }
            #[doc = "Bit 13 - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge."]
            #[inline(always)]
            #[must_use]
            pub fn ch3capf(&mut self) -> CH3CAPF_W<SR_SPEC> {
                CH3CAPF_W::new(self, 13)
            }
            #[doc = "Bit 14 - channel 3 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch3cmp0f(&mut self) -> CH3CMP0F_W<SR_SPEC> {
                CH3CMP0F_W::new(self, 14)
            }
            #[doc = "Bit 15 - channel 3 compare value 1 match flag"]
            #[inline(always)]
            #[must_use]
            pub fn ch3cmp1f(&mut self) -> CH3CMP1F_W<SR_SPEC> {
                CH3CMP1F_W::new(self, 15)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SR_SPEC;
        impl crate::RegisterSpec for SR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sr::R`](R) reader structure"]
        impl crate::Readable for SR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
        impl crate::Writable for SR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SR to value 0"]
        impl crate::Resettable for SR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IRQEN (rw) register accessor: Interrupt request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqen`]
module"]
    pub type IRQEN = crate::Reg<irqen::IRQEN_SPEC>;
    #[doc = "Interrupt request enable register"]
    pub mod irqen {
        #[doc = "Register `IRQEN` reader"]
        pub type R = crate::R<IRQEN_SPEC>;
        #[doc = "Register `IRQEN` writer"]
        pub type W = crate::W<IRQEN_SPEC>;
        #[doc = "Field `CH0RLDEN` reader - 1- generate interrupt request when ch0rldf flag is set"]
        pub type CH0RLDEN_R = crate::BitReader;
        #[doc = "Field `CH0RLDEN` writer - 1- generate interrupt request when ch0rldf flag is set"]
        pub type CH0RLDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH0CAPEN` reader - 1- generate interrupt request when ch0capf flag is set"]
        pub type CH0CAPEN_R = crate::BitReader;
        #[doc = "Field `CH0CAPEN` writer - 1- generate interrupt request when ch0capf flag is set"]
        pub type CH0CAPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH0CMP0EN` reader - 1- generate interrupt request when ch0cmp0f flag is set"]
        pub type CH0CMP0EN_R = crate::BitReader;
        #[doc = "Field `CH0CMP0EN` writer - 1- generate interrupt request when ch0cmp0f flag is set"]
        pub type CH0CMP0EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH0CMP1EN` reader - 1- generate interrupt request when ch0cmp1f flag is set"]
        pub type CH0CMP1EN_R = crate::BitReader;
        #[doc = "Field `CH0CMP1EN` writer - 1- generate interrupt request when ch0cmp1f flag is set"]
        pub type CH0CMP1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1RLDEN` reader - 1- generate interrupt request when ch1rldf flag is set"]
        pub type CH1RLDEN_R = crate::BitReader;
        #[doc = "Field `CH1RLDEN` writer - 1- generate interrupt request when ch1rldf flag is set"]
        pub type CH1RLDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1CAPEN` reader - 1- generate interrupt request when ch1capf flag is set"]
        pub type CH1CAPEN_R = crate::BitReader;
        #[doc = "Field `CH1CAPEN` writer - 1- generate interrupt request when ch1capf flag is set"]
        pub type CH1CAPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1CMP0EN` reader - 1- generate interrupt request when ch1cmp0f flag is set"]
        pub type CH1CMP0EN_R = crate::BitReader;
        #[doc = "Field `CH1CMP0EN` writer - 1- generate interrupt request when ch1cmp0f flag is set"]
        pub type CH1CMP0EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH1CMP1EN` reader - 1- generate interrupt request when ch1cmp1f flag is set"]
        pub type CH1CMP1EN_R = crate::BitReader;
        #[doc = "Field `CH1CMP1EN` writer - 1- generate interrupt request when ch1cmp1f flag is set"]
        pub type CH1CMP1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2RLDEN` reader - 1- generate interrupt request when ch2rldf flag is set"]
        pub type CH2RLDEN_R = crate::BitReader;
        #[doc = "Field `CH2RLDEN` writer - 1- generate interrupt request when ch2rldf flag is set"]
        pub type CH2RLDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2CAPEN` reader - 1- generate interrupt request when ch2capf flag is set"]
        pub type CH2CAPEN_R = crate::BitReader;
        #[doc = "Field `CH2CAPEN` writer - 1- generate interrupt request when ch2capf flag is set"]
        pub type CH2CAPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2CMP0EN` reader - 1- generate interrupt request when ch2cmp0f flag is set"]
        pub type CH2CMP0EN_R = crate::BitReader;
        #[doc = "Field `CH2CMP0EN` writer - 1- generate interrupt request when ch2cmp0f flag is set"]
        pub type CH2CMP0EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH2CMP1EN` reader - 1- generate interrupt request when ch2cmp1f flag is set"]
        pub type CH2CMP1EN_R = crate::BitReader;
        #[doc = "Field `CH2CMP1EN` writer - 1- generate interrupt request when ch2cmp1f flag is set"]
        pub type CH2CMP1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3RLDEN` reader - 1- generate interrupt request when ch3rldf flag is set"]
        pub type CH3RLDEN_R = crate::BitReader;
        #[doc = "Field `CH3RLDEN` writer - 1- generate interrupt request when ch3rldf flag is set"]
        pub type CH3RLDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3CAPEN` reader - 1- generate interrupt request when ch3capf flag is set"]
        pub type CH3CAPEN_R = crate::BitReader;
        #[doc = "Field `CH3CAPEN` writer - 1- generate interrupt request when ch3capf flag is set"]
        pub type CH3CAPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3CMP0EN` reader - 1- generate interrupt request when ch3cmp0f flag is set"]
        pub type CH3CMP0EN_R = crate::BitReader;
        #[doc = "Field `CH3CMP0EN` writer - 1- generate interrupt request when ch3cmp0f flag is set"]
        pub type CH3CMP0EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH3CMP1EN` reader - 1- generate interrupt request when ch3cmp1f flag is set"]
        pub type CH3CMP1EN_R = crate::BitReader;
        #[doc = "Field `CH3CMP1EN` writer - 1- generate interrupt request when ch3cmp1f flag is set"]
        pub type CH3CMP1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - 1- generate interrupt request when ch0rldf flag is set"]
            #[inline(always)]
            pub fn ch0rlden(&self) -> CH0RLDEN_R {
                CH0RLDEN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - 1- generate interrupt request when ch0capf flag is set"]
            #[inline(always)]
            pub fn ch0capen(&self) -> CH0CAPEN_R {
                CH0CAPEN_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - 1- generate interrupt request when ch0cmp0f flag is set"]
            #[inline(always)]
            pub fn ch0cmp0en(&self) -> CH0CMP0EN_R {
                CH0CMP0EN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - 1- generate interrupt request when ch0cmp1f flag is set"]
            #[inline(always)]
            pub fn ch0cmp1en(&self) -> CH0CMP1EN_R {
                CH0CMP1EN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - 1- generate interrupt request when ch1rldf flag is set"]
            #[inline(always)]
            pub fn ch1rlden(&self) -> CH1RLDEN_R {
                CH1RLDEN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - 1- generate interrupt request when ch1capf flag is set"]
            #[inline(always)]
            pub fn ch1capen(&self) -> CH1CAPEN_R {
                CH1CAPEN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - 1- generate interrupt request when ch1cmp0f flag is set"]
            #[inline(always)]
            pub fn ch1cmp0en(&self) -> CH1CMP0EN_R {
                CH1CMP0EN_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - 1- generate interrupt request when ch1cmp1f flag is set"]
            #[inline(always)]
            pub fn ch1cmp1en(&self) -> CH1CMP1EN_R {
                CH1CMP1EN_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - 1- generate interrupt request when ch2rldf flag is set"]
            #[inline(always)]
            pub fn ch2rlden(&self) -> CH2RLDEN_R {
                CH2RLDEN_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - 1- generate interrupt request when ch2capf flag is set"]
            #[inline(always)]
            pub fn ch2capen(&self) -> CH2CAPEN_R {
                CH2CAPEN_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - 1- generate interrupt request when ch2cmp0f flag is set"]
            #[inline(always)]
            pub fn ch2cmp0en(&self) -> CH2CMP0EN_R {
                CH2CMP0EN_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - 1- generate interrupt request when ch2cmp1f flag is set"]
            #[inline(always)]
            pub fn ch2cmp1en(&self) -> CH2CMP1EN_R {
                CH2CMP1EN_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - 1- generate interrupt request when ch3rldf flag is set"]
            #[inline(always)]
            pub fn ch3rlden(&self) -> CH3RLDEN_R {
                CH3RLDEN_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - 1- generate interrupt request when ch3capf flag is set"]
            #[inline(always)]
            pub fn ch3capen(&self) -> CH3CAPEN_R {
                CH3CAPEN_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - 1- generate interrupt request when ch3cmp0f flag is set"]
            #[inline(always)]
            pub fn ch3cmp0en(&self) -> CH3CMP0EN_R {
                CH3CMP0EN_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - 1- generate interrupt request when ch3cmp1f flag is set"]
            #[inline(always)]
            pub fn ch3cmp1en(&self) -> CH3CMP1EN_R {
                CH3CMP1EN_R::new(((self.bits >> 15) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - 1- generate interrupt request when ch0rldf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch0rlden(&mut self) -> CH0RLDEN_W<IRQEN_SPEC> {
                CH0RLDEN_W::new(self, 0)
            }
            #[doc = "Bit 1 - 1- generate interrupt request when ch0capf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch0capen(&mut self) -> CH0CAPEN_W<IRQEN_SPEC> {
                CH0CAPEN_W::new(self, 1)
            }
            #[doc = "Bit 2 - 1- generate interrupt request when ch0cmp0f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch0cmp0en(&mut self) -> CH0CMP0EN_W<IRQEN_SPEC> {
                CH0CMP0EN_W::new(self, 2)
            }
            #[doc = "Bit 3 - 1- generate interrupt request when ch0cmp1f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch0cmp1en(&mut self) -> CH0CMP1EN_W<IRQEN_SPEC> {
                CH0CMP1EN_W::new(self, 3)
            }
            #[doc = "Bit 4 - 1- generate interrupt request when ch1rldf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch1rlden(&mut self) -> CH1RLDEN_W<IRQEN_SPEC> {
                CH1RLDEN_W::new(self, 4)
            }
            #[doc = "Bit 5 - 1- generate interrupt request when ch1capf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch1capen(&mut self) -> CH1CAPEN_W<IRQEN_SPEC> {
                CH1CAPEN_W::new(self, 5)
            }
            #[doc = "Bit 6 - 1- generate interrupt request when ch1cmp0f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch1cmp0en(&mut self) -> CH1CMP0EN_W<IRQEN_SPEC> {
                CH1CMP0EN_W::new(self, 6)
            }
            #[doc = "Bit 7 - 1- generate interrupt request when ch1cmp1f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch1cmp1en(&mut self) -> CH1CMP1EN_W<IRQEN_SPEC> {
                CH1CMP1EN_W::new(self, 7)
            }
            #[doc = "Bit 8 - 1- generate interrupt request when ch2rldf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch2rlden(&mut self) -> CH2RLDEN_W<IRQEN_SPEC> {
                CH2RLDEN_W::new(self, 8)
            }
            #[doc = "Bit 9 - 1- generate interrupt request when ch2capf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch2capen(&mut self) -> CH2CAPEN_W<IRQEN_SPEC> {
                CH2CAPEN_W::new(self, 9)
            }
            #[doc = "Bit 10 - 1- generate interrupt request when ch2cmp0f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch2cmp0en(&mut self) -> CH2CMP0EN_W<IRQEN_SPEC> {
                CH2CMP0EN_W::new(self, 10)
            }
            #[doc = "Bit 11 - 1- generate interrupt request when ch2cmp1f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch2cmp1en(&mut self) -> CH2CMP1EN_W<IRQEN_SPEC> {
                CH2CMP1EN_W::new(self, 11)
            }
            #[doc = "Bit 12 - 1- generate interrupt request when ch3rldf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch3rlden(&mut self) -> CH3RLDEN_W<IRQEN_SPEC> {
                CH3RLDEN_W::new(self, 12)
            }
            #[doc = "Bit 13 - 1- generate interrupt request when ch3capf flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch3capen(&mut self) -> CH3CAPEN_W<IRQEN_SPEC> {
                CH3CAPEN_W::new(self, 13)
            }
            #[doc = "Bit 14 - 1- generate interrupt request when ch3cmp0f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch3cmp0en(&mut self) -> CH3CMP0EN_W<IRQEN_SPEC> {
                CH3CMP0EN_W::new(self, 14)
            }
            #[doc = "Bit 15 - 1- generate interrupt request when ch3cmp1f flag is set"]
            #[inline(always)]
            #[must_use]
            pub fn ch3cmp1en(&mut self) -> CH3CMP1EN_W<IRQEN_SPEC> {
                CH3CMP1EN_W::new(self, 15)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IRQEN_SPEC;
        impl crate::RegisterSpec for IRQEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`irqen::R`](R) reader structure"]
        impl crate::Readable for IRQEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`irqen::W`](W) writer structure"]
        impl crate::Writable for IRQEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IRQEN to value 0"]
        impl crate::Resettable for IRQEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GCR (rw) register accessor: Global control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr`]
module"]
    pub type GCR = crate::Reg<gcr::GCR_SPEC>;
    #[doc = "Global control register"]
    pub mod gcr {
        #[doc = "Register `GCR` reader"]
        pub type R = crate::R<GCR_SPEC>;
        #[doc = "Register `GCR` writer"]
        pub type W = crate::W<GCR_SPEC>;
        #[doc = "Field `SWSYNCT` reader - set this bitfield to trigger software coutner sync event"]
        pub type SWSYNCT_R = crate::FieldReader;
        #[doc = "Field `SWSYNCT` writer - set this bitfield to trigger software coutner sync event"]
        pub type SWSYNCT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3 - set this bitfield to trigger software coutner sync event"]
            #[inline(always)]
            pub fn swsynct(&self) -> SWSYNCT_R {
                SWSYNCT_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - set this bitfield to trigger software coutner sync event"]
            #[inline(always)]
            #[must_use]
            pub fn swsynct(&mut self) -> SWSYNCT_W<GCR_SPEC> {
                SWSYNCT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Global control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GCR_SPEC;
        impl crate::RegisterSpec for GCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gcr::R`](R) reader structure"]
        impl crate::Readable for GCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gcr::W`](W) writer structure"]
        impl crate::Writable for GCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GCR to value 0"]
        impl crate::Resettable for GCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "GPTMR1"]
pub struct GPTMR1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPTMR1 {}
impl GPTMR1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const gptmr0::RegisterBlock = 0xf000_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const gptmr0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for GPTMR1 {
    type Target = gptmr0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for GPTMR1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPTMR1").finish()
    }
}
#[doc = "GPTMR1"]
pub use self::gptmr0 as gptmr1;
#[doc = "GPTMR2"]
pub struct GPTMR2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPTMR2 {}
impl GPTMR2 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const gptmr0::RegisterBlock = 0xf000_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const gptmr0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for GPTMR2 {
    type Target = gptmr0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for GPTMR2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPTMR2").finish()
    }
}
#[doc = "GPTMR2"]
pub use self::gptmr0 as gptmr2;
#[doc = "GPTMR3"]
pub struct GPTMR3 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPTMR3 {}
impl GPTMR3 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const gptmr0::RegisterBlock = 0xf000_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const gptmr0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for GPTMR3 {
    type Target = gptmr0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for GPTMR3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPTMR3").finish()
    }
}
#[doc = "GPTMR3"]
pub use self::gptmr0 as gptmr3;
#[doc = "PTMR"]
pub struct PTMR {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PTMR {}
impl PTMR {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const gptmr0::RegisterBlock = 0xf412_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const gptmr0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PTMR {
    type Target = gptmr0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PTMR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PTMR").finish()
    }
}
#[doc = "PTMR"]
pub use self::gptmr0 as ptmr;
#[doc = "LIN0"]
pub struct LIN0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LIN0 {}
impl LIN0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const lin0::RegisterBlock = 0xf002_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const lin0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for LIN0 {
    type Target = lin0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for LIN0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LIN0").finish()
    }
}
#[doc = "LIN0"]
pub mod lin0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved_0_data: [u8; 0x08],
        data_len_id: DATA_LEN_ID,
        control_status: CONTROL_STATUS,
        timing_control: TIMING_CONTROL,
        dma_control: DMA_CONTROL,
    }
    impl RegisterBlock {
        #[doc = "0x00..0x08 - no description available"]
        #[inline(always)]
        pub const fn data_byte(&self, n: usize) -> &DATA_BYTE {
            #[allow(clippy::no_effect)]
            [(); 8][n];
            unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x08 - no description available"]
        #[inline(always)]
        pub fn data_byte_iter(&self) -> impl Iterator<Item = &DATA_BYTE> {
            (0..8).map(move |n| unsafe {
                &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast()
            })
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte0(&self) -> &DATA_BYTE {
            self.data_byte(0)
        }
        #[doc = "0x01 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte1(&self) -> &DATA_BYTE {
            self.data_byte(1)
        }
        #[doc = "0x02 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte2(&self) -> &DATA_BYTE {
            self.data_byte(2)
        }
        #[doc = "0x03 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte3(&self) -> &DATA_BYTE {
            self.data_byte(3)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte4(&self) -> &DATA_BYTE {
            self.data_byte(4)
        }
        #[doc = "0x05 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte5(&self) -> &DATA_BYTE {
            self.data_byte(5)
        }
        #[doc = "0x06 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte6(&self) -> &DATA_BYTE {
            self.data_byte(6)
        }
        #[doc = "0x07 - no description available"]
        #[inline(always)]
        pub const fn data_bytedata_byte7(&self) -> &DATA_BYTE {
            self.data_byte(7)
        }
        #[doc = "0x00..0x08 - no description available"]
        #[inline(always)]
        pub const fn data(&self, n: usize) -> &DATA {
            #[allow(clippy::no_effect)]
            [(); 2][n];
            unsafe { &*(self as *const Self).cast::<u8>().add(0).add(4 * n).cast() }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x08 - no description available"]
        #[inline(always)]
        pub fn data_iter(&self) -> impl Iterator<Item = &DATA> {
            (0..2).map(move |n| unsafe {
                &*(self as *const Self).cast::<u8>().add(0).add(4 * n).cast()
            })
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn datadata0(&self) -> &DATA {
            self.data(0)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn datadata1(&self) -> &DATA {
            self.data(1)
        }
        #[doc = "0x08 - data length and ID register"]
        #[inline(always)]
        pub const fn data_len_id(&self) -> &DATA_LEN_ID {
            &self.data_len_id
        }
        #[doc = "0x0c - control and status register"]
        #[inline(always)]
        pub const fn control_status(&self) -> &CONTROL_STATUS {
            &self.control_status
        }
        #[doc = "0x10 - timing control register"]
        #[inline(always)]
        pub const fn timing_control(&self) -> &TIMING_CONTROL {
            &self.timing_control
        }
        #[doc = "0x14 - dma control register"]
        #[inline(always)]
        pub const fn dma_control(&self) -> &DMA_CONTROL {
            &self.dma_control
        }
    }
    #[doc = "DATA (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
    pub type DATA = crate::Reg<data::DATA_SPEC>;
    #[doc = "no description available"]
    pub mod data {
        #[doc = "Register `DATA[%s]` reader"]
        pub type R = crate::R<DATA_SPEC>;
        #[doc = "Register `DATA[%s]` writer"]
        pub type W = crate::W<DATA_SPEC>;
        #[doc = "Field `DATA` reader - data"]
        pub type DATA_R = crate::FieldReader<u32>;
        #[doc = "Field `DATA` writer - data"]
        pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - data"]
            #[inline(always)]
            pub fn data(&self) -> DATA_R {
                DATA_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - data"]
            #[inline(always)]
            #[must_use]
            pub fn data(&mut self) -> DATA_W<DATA_SPEC> {
                DATA_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DATA_SPEC;
        impl crate::RegisterSpec for DATA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`data::R`](R) reader structure"]
        impl crate::Readable for DATA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
        impl crate::Writable for DATA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DATA[%s]
to value 0"]
        impl crate::Resettable for DATA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DATA_BYTE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_byte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_byte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_byte`]
module"]
    pub type DATA_BYTE = crate::Reg<data_byte::DATA_BYTE_SPEC>;
    #[doc = "no description available"]
    pub mod data_byte {
        #[doc = "Register `DATA_BYTE[%s]` reader"]
        pub type R = crate::R<DATA_BYTE_SPEC>;
        #[doc = "Register `DATA_BYTE[%s]` writer"]
        pub type W = crate::W<DATA_BYTE_SPEC>;
        #[doc = "Field `DATA_BYTE` reader - data byte"]
        pub type DATA_BYTE_R = crate::FieldReader;
        #[doc = "Field `DATA_BYTE` writer - data byte"]
        pub type DATA_BYTE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - data byte"]
            #[inline(always)]
            pub fn data_byte(&self) -> DATA_BYTE_R {
                DATA_BYTE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - data byte"]
            #[inline(always)]
            #[must_use]
            pub fn data_byte(&mut self) -> DATA_BYTE_W<DATA_BYTE_SPEC> {
                DATA_BYTE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_byte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_byte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DATA_BYTE_SPEC;
        impl crate::RegisterSpec for DATA_BYTE_SPEC {
            type Ux = u8;
        }
        #[doc = "`read()` method returns [`data_byte::R`](R) reader structure"]
        impl crate::Readable for DATA_BYTE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`data_byte::W`](W) writer structure"]
        impl crate::Writable for DATA_BYTE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
        }
        #[doc = "`reset()` method sets DATA_BYTE[%s]
to value 0"]
        impl crate::Resettable for DATA_BYTE_SPEC {
            const RESET_VALUE: u8 = 0;
        }
    }
    #[doc = "data_len_id (rw) register accessor: data length and ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_len_id::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_len_id::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_len_id`]
module"]
    pub type DATA_LEN_ID = crate::Reg<data_len_id::DATA_LEN_ID_SPEC>;
    #[doc = "data length and ID register"]
    pub mod data_len_id {
        #[doc = "Register `data_len_id` reader"]
        pub type R = crate::R<DATA_LEN_ID_SPEC>;
        #[doc = "Register `data_len_id` writer"]
        pub type W = crate::W<DATA_LEN_ID_SPEC>;
        #[doc = "Field `DATA_LEN` reader - payload data length control register。The data length will decoded from ID\\[5:4\\]
when all 1 is configured: 00-2 01-2 10-4 11-8"]
        pub type DATA_LEN_R = crate::FieldReader;
        #[doc = "Field `DATA_LEN` writer - payload data length control register。The data length will decoded from ID\\[5:4\\]
when all 1 is configured: 00-2 01-2 10-4 11-8"]
        pub type DATA_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `ENH_CHECK` reader - 1:enhance check mode 0:classical check mode"]
        pub type ENH_CHECK_R = crate::BitReader;
        #[doc = "Field `ENH_CHECK` writer - 1:enhance check mode 0:classical check mode"]
        pub type ENH_CHECK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ID` reader - ID register"]
        pub type ID_R = crate::FieldReader;
        #[doc = "Field `ID` writer - ID register"]
        pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `ID_PARITY` reader - No description avaiable"]
        pub type ID_PARITY_R = crate::FieldReader;
        #[doc = "Field `CHECKSUM` reader - No description avaiable"]
        pub type CHECKSUM_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:3 - payload data length control register。The data length will decoded from ID\\[5:4\\]
when all 1 is configured: 00-2 01-2 10-4 11-8"]
            #[inline(always)]
            pub fn data_len(&self) -> DATA_LEN_R {
                DATA_LEN_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bit 7 - 1:enhance check mode 0:classical check mode"]
            #[inline(always)]
            pub fn enh_check(&self) -> ENH_CHECK_R {
                ENH_CHECK_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:13 - ID register"]
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
            #[doc = "Bits 14:15 - No description avaiable"]
            #[inline(always)]
            pub fn id_parity(&self) -> ID_PARITY_R {
                ID_PARITY_R::new(((self.bits >> 14) & 3) as u8)
            }
            #[doc = "Bits 16:23 - No description avaiable"]
            #[inline(always)]
            pub fn checksum(&self) -> CHECKSUM_R {
                CHECKSUM_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - payload data length control register。The data length will decoded from ID\\[5:4\\]
when all 1 is configured: 00-2 01-2 10-4 11-8"]
            #[inline(always)]
            #[must_use]
            pub fn data_len(&mut self) -> DATA_LEN_W<DATA_LEN_ID_SPEC> {
                DATA_LEN_W::new(self, 0)
            }
            #[doc = "Bit 7 - 1:enhance check mode 0:classical check mode"]
            #[inline(always)]
            #[must_use]
            pub fn enh_check(&mut self) -> ENH_CHECK_W<DATA_LEN_ID_SPEC> {
                ENH_CHECK_W::new(self, 7)
            }
            #[doc = "Bits 8:13 - ID register"]
            #[inline(always)]
            #[must_use]
            pub fn id(&mut self) -> ID_W<DATA_LEN_ID_SPEC> {
                ID_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "data length and ID register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_len_id::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_len_id::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DATA_LEN_ID_SPEC;
        impl crate::RegisterSpec for DATA_LEN_ID_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`data_len_id::R`](R) reader structure"]
        impl crate::Readable for DATA_LEN_ID_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`data_len_id::W`](W) writer structure"]
        impl crate::Writable for DATA_LEN_ID_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets data_len_id to value 0"]
        impl crate::Resettable for DATA_LEN_ID_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "control_status (rw) register accessor: control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control_status`]
module"]
    pub type CONTROL_STATUS = crate::Reg<control_status::CONTROL_STATUS_SPEC>;
    #[doc = "control and status register"]
    pub mod control_status {
        #[doc = "Register `control_status` reader"]
        pub type R = crate::R<CONTROL_STATUS_SPEC>;
        #[doc = "Register `control_status` writer"]
        pub type W = crate::W<CONTROL_STATUS_SPEC>;
        #[doc = "Field `START_REQ` reader - master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete"]
        pub type START_REQ_R = crate::BitReader;
        #[doc = "Field `START_REQ` writer - master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete"]
        pub type START_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAKEUP_REQ` reader - set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete"]
        pub type WAKEUP_REQ_R = crate::BitReader;
        #[doc = "Field `WAKEUP_REQ` writer - set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete"]
        pub type WAKEUP_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESET_ERROR` writer - set 1 will clear the error register, and also the timeout/complete/wakeup register"]
        pub type RESET_ERROR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESET_INT` writer - set 1 will clear the int register"]
        pub type RESET_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DATA_ACK` reader - slave only. Write 1 after handling a data request interrupt"]
        pub type DATA_ACK_R = crate::BitReader;
        #[doc = "Field `DATA_ACK` writer - slave only. Write 1 after handling a data request interrupt"]
        pub type DATA_ACK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRANSMIT` reader - 1: transmit operation 0: receive operation"]
        pub type TRANSMIT_R = crate::BitReader;
        #[doc = "Field `TRANSMIT` writer - 1: transmit operation 0: receive operation"]
        pub type TRANSMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLEEP` reader - The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core."]
        pub type SLEEP_R = crate::BitReader;
        #[doc = "Field `SLEEP` writer - The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core."]
        pub type SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STOP` writer - slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID"]
        pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COMPLETE` reader - set after a transmission has been successful finished and it will reset at the start of a transmission."]
        pub type COMPLETE_R = crate::BitReader;
        #[doc = "Field `WAKEUP` reader - set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1"]
        pub type WAKEUP_R = crate::BitReader;
        #[doc = "Field `ERROR` reader - set when detecte an error, clear by reset_error"]
        pub type ERROR_R = crate::BitReader;
        #[doc = "Field `INT` reader - set when request an interrupt. Reset by reset_int"]
        pub type INT_R = crate::BitReader;
        #[doc = "Field `DATA_REQ` reader - slave only. Sets after receiving the identifier and requests an interrupt to the host controller."]
        pub type DATA_REQ_R = crate::BitReader;
        #[doc = "Field `ABORTED` reader - slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error."]
        pub type ABORTED_R = crate::BitReader;
        #[doc = "Field `BUS_IDLE_TIMEOUT` reader - slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s"]
        pub type BUS_IDLE_TIMEOUT_R = crate::BitReader;
        #[doc = "Field `LIN_ACTIVE` reader - The bit indicates whether the LIN bus is active or not"]
        pub type LIN_ACTIVE_R = crate::BitReader;
        #[doc = "Field `BIT_ERROR` reader - bit error"]
        pub type BIT_ERROR_R = crate::BitReader;
        #[doc = "Field `CHK_ERROR` reader - checksum error"]
        pub type CHK_ERROR_R = crate::BitReader;
        #[doc = "Field `TIME_OUT` reader - timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms"]
        pub type TIME_OUT_R = crate::BitReader;
        #[doc = "Field `PARITY_ERROR` reader - slave only. identifier parity error"]
        pub type PARITY_ERROR_R = crate::BitReader;
        #[doc = "Field `BREAK_ERR` reader - No description avaiable"]
        pub type BREAK_ERR_R = crate::BitReader;
        #[doc = "Field `BREAK_ERR_DIS` reader - No description avaiable"]
        pub type BREAK_ERR_DIS_R = crate::BitReader;
        #[doc = "Field `BREAK_ERR_DIS` writer - No description avaiable"]
        pub type BREAK_ERR_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete"]
            #[inline(always)]
            pub fn start_req(&self) -> START_REQ_R {
                START_REQ_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete"]
            #[inline(always)]
            pub fn wakeup_req(&self) -> WAKEUP_REQ_R {
                WAKEUP_REQ_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 4 - slave only. Write 1 after handling a data request interrupt"]
            #[inline(always)]
            pub fn data_ack(&self) -> DATA_ACK_R {
                DATA_ACK_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - 1: transmit operation 0: receive operation"]
            #[inline(always)]
            pub fn transmit(&self) -> TRANSMIT_R {
                TRANSMIT_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core."]
            #[inline(always)]
            pub fn sleep(&self) -> SLEEP_R {
                SLEEP_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 8 - set after a transmission has been successful finished and it will reset at the start of a transmission."]
            #[inline(always)]
            pub fn complete(&self) -> COMPLETE_R {
                COMPLETE_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1"]
            #[inline(always)]
            pub fn wakeup(&self) -> WAKEUP_R {
                WAKEUP_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - set when detecte an error, clear by reset_error"]
            #[inline(always)]
            pub fn error(&self) -> ERROR_R {
                ERROR_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - set when request an interrupt. Reset by reset_int"]
            #[inline(always)]
            pub fn int(&self) -> INT_R {
                INT_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - slave only. Sets after receiving the identifier and requests an interrupt to the host controller."]
            #[inline(always)]
            pub fn data_req(&self) -> DATA_REQ_R {
                DATA_REQ_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error."]
            #[inline(always)]
            pub fn aborted(&self) -> ABORTED_R {
                ABORTED_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s"]
            #[inline(always)]
            pub fn bus_idle_timeout(&self) -> BUS_IDLE_TIMEOUT_R {
                BUS_IDLE_TIMEOUT_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - The bit indicates whether the LIN bus is active or not"]
            #[inline(always)]
            pub fn lin_active(&self) -> LIN_ACTIVE_R {
                LIN_ACTIVE_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - bit error"]
            #[inline(always)]
            pub fn bit_error(&self) -> BIT_ERROR_R {
                BIT_ERROR_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - checksum error"]
            #[inline(always)]
            pub fn chk_error(&self) -> CHK_ERROR_R {
                CHK_ERROR_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms"]
            #[inline(always)]
            pub fn time_out(&self) -> TIME_OUT_R {
                TIME_OUT_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - slave only. identifier parity error"]
            #[inline(always)]
            pub fn parity_error(&self) -> PARITY_ERROR_R {
                PARITY_ERROR_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            pub fn break_err(&self) -> BREAK_ERR_R {
                BREAK_ERR_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            pub fn break_err_dis(&self) -> BREAK_ERR_DIS_R {
                BREAK_ERR_DIS_R::new(((self.bits >> 21) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the trasmission complete"]
            #[inline(always)]
            #[must_use]
            pub fn start_req(&mut self) -> START_REQ_W<CONTROL_STATUS_SPEC> {
                START_REQ_W::new(self, 0)
            }
            #[doc = "Bit 1 - set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete"]
            #[inline(always)]
            #[must_use]
            pub fn wakeup_req(&mut self) -> WAKEUP_REQ_W<CONTROL_STATUS_SPEC> {
                WAKEUP_REQ_W::new(self, 1)
            }
            #[doc = "Bit 2 - set 1 will clear the error register, and also the timeout/complete/wakeup register"]
            #[inline(always)]
            #[must_use]
            pub fn reset_error(&mut self) -> RESET_ERROR_W<CONTROL_STATUS_SPEC> {
                RESET_ERROR_W::new(self, 2)
            }
            #[doc = "Bit 3 - set 1 will clear the int register"]
            #[inline(always)]
            #[must_use]
            pub fn reset_int(&mut self) -> RESET_INT_W<CONTROL_STATUS_SPEC> {
                RESET_INT_W::new(self, 3)
            }
            #[doc = "Bit 4 - slave only. Write 1 after handling a data request interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn data_ack(&mut self) -> DATA_ACK_W<CONTROL_STATUS_SPEC> {
                DATA_ACK_W::new(self, 4)
            }
            #[doc = "Bit 5 - 1: transmit operation 0: receive operation"]
            #[inline(always)]
            #[must_use]
            pub fn transmit(&mut self) -> TRANSMIT_W<CONTROL_STATUS_SPEC> {
                TRANSMIT_W::new(self, 5)
            }
            #[doc = "Bit 6 - The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core."]
            #[inline(always)]
            #[must_use]
            pub fn sleep(&mut self) -> SLEEP_W<CONTROL_STATUS_SPEC> {
                SLEEP_W::new(self, 6)
            }
            #[doc = "Bit 7 - slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID"]
            #[inline(always)]
            #[must_use]
            pub fn stop(&mut self) -> STOP_W<CONTROL_STATUS_SPEC> {
                STOP_W::new(self, 7)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn break_err_dis(&mut self) -> BREAK_ERR_DIS_W<CONTROL_STATUS_SPEC> {
                BREAK_ERR_DIS_W::new(self, 21)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control and status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CONTROL_STATUS_SPEC;
        impl crate::RegisterSpec for CONTROL_STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`control_status::R`](R) reader structure"]
        impl crate::Readable for CONTROL_STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`control_status::W`](W) writer structure"]
        impl crate::Writable for CONTROL_STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets control_status to value 0"]
        impl crate::Resettable for CONTROL_STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "timing_control (rw) register accessor: timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timing_control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timing_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timing_control`]
module"]
    pub type TIMING_CONTROL = crate::Reg<timing_control::TIMING_CONTROL_SPEC>;
    #[doc = "timing control register"]
    pub mod timing_control {
        #[doc = "Register `timing_control` reader"]
        pub type R = crate::R<TIMING_CONTROL_SPEC>;
        #[doc = "Register `timing_control` writer"]
        pub type W = crate::W<TIMING_CONTROL_SPEC>;
        #[doc = "Field `BT_DIV` reader - bt_div register"]
        pub type BT_DIV_R = crate::FieldReader<u16>;
        #[doc = "Field `BT_DIV` writer - bt_div register"]
        pub type BT_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `BT_MUL` reader - bt_mul register"]
        pub type BT_MUL_R = crate::FieldReader;
        #[doc = "Field `BT_MUL` writer - bt_mul register"]
        pub type BT_MUL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `PRESCL` reader - prescl register"]
        pub type PRESCL_R = crate::FieldReader;
        #[doc = "Field `PRESCL` writer - prescl register"]
        pub type PRESCL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `WUP_REPEAT_TIME` reader - slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms"]
        pub type WUP_REPEAT_TIME_R = crate::FieldReader;
        #[doc = "Field `WUP_REPEAT_TIME` writer - slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms"]
        pub type WUP_REPEAT_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `BUS_INACTIVE_TIME` reader - slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s"]
        pub type BUS_INACTIVE_TIME_R = crate::FieldReader;
        #[doc = "Field `BUS_INACTIVE_TIME` writer - slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s"]
        pub type BUS_INACTIVE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `MASTER_MODE` reader - 1：master mode"]
        pub type MASTER_MODE_R = crate::BitReader;
        #[doc = "Field `MASTER_MODE` writer - 1：master mode"]
        pub type MASTER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LIN_INITIAL` reader - 1:initial lin controller"]
        pub type LIN_INITIAL_R = crate::BitReader;
        #[doc = "Field `LIN_INITIAL` writer - 1:initial lin controller"]
        pub type LIN_INITIAL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LINBUSDISABLE` reader - 1：lin rx is disable"]
        pub type LINBUSDISABLE_R = crate::BitReader;
        #[doc = "Field `LINBUSDISABLE` writer - 1：lin rx is disable"]
        pub type LINBUSDISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BRK_LEN` reader - No description avaiable"]
        pub type BRK_LEN_R = crate::FieldReader;
        #[doc = "Field `BRK_LEN` writer - No description avaiable"]
        pub type BRK_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `WAKE_LEN` reader - No description avaiable"]
        pub type WAKE_LEN_R = crate::FieldReader;
        #[doc = "Field `WAKE_LEN` writer - No description avaiable"]
        pub type WAKE_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:8 - bt_div register"]
            #[inline(always)]
            pub fn bt_div(&self) -> BT_DIV_R {
                BT_DIV_R::new((self.bits & 0x01ff) as u16)
            }
            #[doc = "Bits 9:13 - bt_mul register"]
            #[inline(always)]
            pub fn bt_mul(&self) -> BT_MUL_R {
                BT_MUL_R::new(((self.bits >> 9) & 0x1f) as u8)
            }
            #[doc = "Bits 14:15 - prescl register"]
            #[inline(always)]
            pub fn prescl(&self) -> PRESCL_R {
                PRESCL_R::new(((self.bits >> 14) & 3) as u8)
            }
            #[doc = "Bits 16:17 - slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms"]
            #[inline(always)]
            pub fn wup_repeat_time(&self) -> WUP_REPEAT_TIME_R {
                WUP_REPEAT_TIME_R::new(((self.bits >> 16) & 3) as u8)
            }
            #[doc = "Bits 18:19 - slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s"]
            #[inline(always)]
            pub fn bus_inactive_time(&self) -> BUS_INACTIVE_TIME_R {
                BUS_INACTIVE_TIME_R::new(((self.bits >> 18) & 3) as u8)
            }
            #[doc = "Bit 20 - 1：master mode"]
            #[inline(always)]
            pub fn master_mode(&self) -> MASTER_MODE_R {
                MASTER_MODE_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - 1:initial lin controller"]
            #[inline(always)]
            pub fn lin_initial(&self) -> LIN_INITIAL_R {
                LIN_INITIAL_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - 1：lin rx is disable"]
            #[inline(always)]
            pub fn linbusdisable(&self) -> LINBUSDISABLE_R {
                LINBUSDISABLE_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bits 24:26 - No description avaiable"]
            #[inline(always)]
            pub fn brk_len(&self) -> BRK_LEN_R {
                BRK_LEN_R::new(((self.bits >> 24) & 7) as u8)
            }
            #[doc = "Bits 27:29 - No description avaiable"]
            #[inline(always)]
            pub fn wake_len(&self) -> WAKE_LEN_R {
                WAKE_LEN_R::new(((self.bits >> 27) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:8 - bt_div register"]
            #[inline(always)]
            #[must_use]
            pub fn bt_div(&mut self) -> BT_DIV_W<TIMING_CONTROL_SPEC> {
                BT_DIV_W::new(self, 0)
            }
            #[doc = "Bits 9:13 - bt_mul register"]
            #[inline(always)]
            #[must_use]
            pub fn bt_mul(&mut self) -> BT_MUL_W<TIMING_CONTROL_SPEC> {
                BT_MUL_W::new(self, 9)
            }
            #[doc = "Bits 14:15 - prescl register"]
            #[inline(always)]
            #[must_use]
            pub fn prescl(&mut self) -> PRESCL_W<TIMING_CONTROL_SPEC> {
                PRESCL_W::new(self, 14)
            }
            #[doc = "Bits 16:17 - slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms"]
            #[inline(always)]
            #[must_use]
            pub fn wup_repeat_time(&mut self) -> WUP_REPEAT_TIME_W<TIMING_CONTROL_SPEC> {
                WUP_REPEAT_TIME_W::new(self, 16)
            }
            #[doc = "Bits 18:19 - slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s"]
            #[inline(always)]
            #[must_use]
            pub fn bus_inactive_time(&mut self) -> BUS_INACTIVE_TIME_W<TIMING_CONTROL_SPEC> {
                BUS_INACTIVE_TIME_W::new(self, 18)
            }
            #[doc = "Bit 20 - 1：master mode"]
            #[inline(always)]
            #[must_use]
            pub fn master_mode(&mut self) -> MASTER_MODE_W<TIMING_CONTROL_SPEC> {
                MASTER_MODE_W::new(self, 20)
            }
            #[doc = "Bit 21 - 1:initial lin controller"]
            #[inline(always)]
            #[must_use]
            pub fn lin_initial(&mut self) -> LIN_INITIAL_W<TIMING_CONTROL_SPEC> {
                LIN_INITIAL_W::new(self, 21)
            }
            #[doc = "Bit 22 - 1：lin rx is disable"]
            #[inline(always)]
            #[must_use]
            pub fn linbusdisable(&mut self) -> LINBUSDISABLE_W<TIMING_CONTROL_SPEC> {
                LINBUSDISABLE_W::new(self, 22)
            }
            #[doc = "Bits 24:26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn brk_len(&mut self) -> BRK_LEN_W<TIMING_CONTROL_SPEC> {
                BRK_LEN_W::new(self, 24)
            }
            #[doc = "Bits 27:29 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn wake_len(&mut self) -> WAKE_LEN_W<TIMING_CONTROL_SPEC> {
                WAKE_LEN_W::new(self, 27)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timing control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timing_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timing_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TIMING_CONTROL_SPEC;
        impl crate::RegisterSpec for TIMING_CONTROL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timing_control::R`](R) reader structure"]
        impl crate::Readable for TIMING_CONTROL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`timing_control::W`](W) writer structure"]
        impl crate::Writable for TIMING_CONTROL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets timing_control to value 0x0040_0000"]
        impl crate::Resettable for TIMING_CONTROL_SPEC {
            const RESET_VALUE: u32 = 0x0040_0000;
        }
    }
    #[doc = "dma_control (rw) register accessor: dma control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_control`]
module"]
    pub type DMA_CONTROL = crate::Reg<dma_control::DMA_CONTROL_SPEC>;
    #[doc = "dma control register"]
    pub mod dma_control {
        #[doc = "Register `dma_control` reader"]
        pub type R = crate::R<DMA_CONTROL_SPEC>;
        #[doc = "Register `dma_control` writer"]
        pub type W = crate::W<DMA_CONTROL_SPEC>;
        #[doc = "Field `DMA_REQ_ENABLE` reader - slave mode only. 1: enable dma request for data request ID equal dma_req_id"]
        pub type DMA_REQ_ENABLE_R = crate::BitReader;
        #[doc = "Field `DMA_REQ_ENABLE` writer - slave mode only. 1: enable dma request for data request ID equal dma_req_id"]
        pub type DMA_REQ_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_REQ_ID` reader - dma_req_id register"]
        pub type DMA_REQ_ID_R = crate::FieldReader;
        #[doc = "Field `DMA_REQ_ID` writer - dma_req_id register"]
        pub type DMA_REQ_ID_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `DMA_REQ_ID_TYPE` reader - 1：transmite 0：receive"]
        pub type DMA_REQ_ID_TYPE_R = crate::BitReader;
        #[doc = "Field `DMA_REQ_ID_TYPE` writer - 1：transmite 0：receive"]
        pub type DMA_REQ_ID_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_REQ_LEN` reader - paylaod length for dma request"]
        pub type DMA_REQ_LEN_R = crate::FieldReader;
        #[doc = "Field `DMA_REQ_LEN` writer - paylaod length for dma request"]
        pub type DMA_REQ_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DMA_REQ_ENH_CHK` reader - payload data checksum type for dma operation"]
        pub type DMA_REQ_ENH_CHK_R = crate::BitReader;
        #[doc = "Field `DMA_REQ_ENH_CHK` writer - payload data checksum type for dma operation"]
        pub type DMA_REQ_ENH_CHK_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - slave mode only. 1: enable dma request for data request ID equal dma_req_id"]
            #[inline(always)]
            pub fn dma_req_enable(&self) -> DMA_REQ_ENABLE_R {
                DMA_REQ_ENABLE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:6 - dma_req_id register"]
            #[inline(always)]
            pub fn dma_req_id(&self) -> DMA_REQ_ID_R {
                DMA_REQ_ID_R::new(((self.bits >> 1) & 0x3f) as u8)
            }
            #[doc = "Bit 7 - 1：transmite 0：receive"]
            #[inline(always)]
            pub fn dma_req_id_type(&self) -> DMA_REQ_ID_TYPE_R {
                DMA_REQ_ID_TYPE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:11 - paylaod length for dma request"]
            #[inline(always)]
            pub fn dma_req_len(&self) -> DMA_REQ_LEN_R {
                DMA_REQ_LEN_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            #[doc = "Bit 12 - payload data checksum type for dma operation"]
            #[inline(always)]
            pub fn dma_req_enh_chk(&self) -> DMA_REQ_ENH_CHK_R {
                DMA_REQ_ENH_CHK_R::new(((self.bits >> 12) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - slave mode only. 1: enable dma request for data request ID equal dma_req_id"]
            #[inline(always)]
            #[must_use]
            pub fn dma_req_enable(&mut self) -> DMA_REQ_ENABLE_W<DMA_CONTROL_SPEC> {
                DMA_REQ_ENABLE_W::new(self, 0)
            }
            #[doc = "Bits 1:6 - dma_req_id register"]
            #[inline(always)]
            #[must_use]
            pub fn dma_req_id(&mut self) -> DMA_REQ_ID_W<DMA_CONTROL_SPEC> {
                DMA_REQ_ID_W::new(self, 1)
            }
            #[doc = "Bit 7 - 1：transmite 0：receive"]
            #[inline(always)]
            #[must_use]
            pub fn dma_req_id_type(&mut self) -> DMA_REQ_ID_TYPE_W<DMA_CONTROL_SPEC> {
                DMA_REQ_ID_TYPE_W::new(self, 7)
            }
            #[doc = "Bits 8:11 - paylaod length for dma request"]
            #[inline(always)]
            #[must_use]
            pub fn dma_req_len(&mut self) -> DMA_REQ_LEN_W<DMA_CONTROL_SPEC> {
                DMA_REQ_LEN_W::new(self, 8)
            }
            #[doc = "Bit 12 - payload data checksum type for dma operation"]
            #[inline(always)]
            #[must_use]
            pub fn dma_req_enh_chk(&mut self) -> DMA_REQ_ENH_CHK_W<DMA_CONTROL_SPEC> {
                DMA_REQ_ENH_CHK_W::new(self, 12)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "dma control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DMA_CONTROL_SPEC;
        impl crate::RegisterSpec for DMA_CONTROL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dma_control::R`](R) reader structure"]
        impl crate::Readable for DMA_CONTROL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dma_control::W`](W) writer structure"]
        impl crate::Writable for DMA_CONTROL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets dma_control to value 0"]
        impl crate::Resettable for DMA_CONTROL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "LIN1"]
pub struct LIN1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LIN1 {}
impl LIN1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const lin0::RegisterBlock = 0xf002_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const lin0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for LIN1 {
    type Target = lin0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for LIN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LIN1").finish()
    }
}
#[doc = "LIN1"]
pub use self::lin0 as lin1;
#[doc = "LIN2"]
pub struct LIN2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LIN2 {}
impl LIN2 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const lin0::RegisterBlock = 0xf002_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const lin0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for LIN2 {
    type Target = lin0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for LIN2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LIN2").finish()
    }
}
#[doc = "LIN2"]
pub use self::lin0 as lin2;
#[doc = "LIN3"]
pub struct LIN3 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for LIN3 {}
impl LIN3 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const lin0::RegisterBlock = 0xf002_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const lin0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for LIN3 {
    type Target = lin0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for LIN3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("LIN3").finish()
    }
}
#[doc = "LIN3"]
pub use self::lin0 as lin3;
#[doc = "UART0"]
pub struct UART0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART0 {}
impl UART0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf004_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART0 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART0").finish()
    }
}
#[doc = "UART0"]
pub mod uart0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x04],
        idle_cfg: IDLE_CFG,
        addr_cfg: ADDR_CFG,
        iir2: IIR2,
        cfg: CFG,
        oscr: OSCR,
        fcrr: FCRR,
        moto_cfg: MOTO_CFG,
        _reserved_7_dll: [u8; 0x04],
        _reserved_8_dlm: [u8; 0x04],
        _reserved_9_fcr: [u8; 0x04],
        lcr: LCR,
        mcr: MCR,
        lsr: LSR,
        msr: MSR,
        gpr: GPR,
    }
    impl RegisterBlock {
        #[doc = "0x04 - Idle Configuration Register"]
        #[inline(always)]
        pub const fn idle_cfg(&self) -> &IDLE_CFG {
            &self.idle_cfg
        }
        #[doc = "0x08 - address match config register"]
        #[inline(always)]
        pub const fn addr_cfg(&self) -> &ADDR_CFG {
            &self.addr_cfg
        }
        #[doc = "0x0c - Interrupt Identification Register2"]
        #[inline(always)]
        pub const fn iir2(&self) -> &IIR2 {
            &self.iir2
        }
        #[doc = "0x10 - Configuration Register"]
        #[inline(always)]
        pub const fn cfg(&self) -> &CFG {
            &self.cfg
        }
        #[doc = "0x14 - Over Sample Control Register"]
        #[inline(always)]
        pub const fn oscr(&self) -> &OSCR {
            &self.oscr
        }
        #[doc = "0x18 - FIFO Control Register config"]
        #[inline(always)]
        pub const fn fcrr(&self) -> &FCRR {
            &self.fcrr
        }
        #[doc = "0x1c - moto system control register"]
        #[inline(always)]
        pub const fn moto_cfg(&self) -> &MOTO_CFG {
            &self.moto_cfg
        }
        #[doc = "0x20 - Divisor Latch LSB (when DLAB = 1)"]
        #[inline(always)]
        pub const fn dll(&self) -> &DLL {
            unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
        }
        #[doc = "0x20 - Transmitter Holding Register (when DLAB = 0)"]
        #[inline(always)]
        pub const fn thr(&self) -> &THR {
            unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
        }
        #[doc = "0x20 - Receiver Buffer Register (when DLAB = 0)"]
        #[inline(always)]
        pub const fn rbr(&self) -> &RBR {
            unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
        }
        #[doc = "0x24 - Divisor Latch MSB (when DLAB = 1)"]
        #[inline(always)]
        pub const fn dlm(&self) -> &DLM {
            unsafe { &*(self as *const Self).cast::<u8>().add(36).cast() }
        }
        #[doc = "0x24 - Interrupt Enable Register (when DLAB = 0)"]
        #[inline(always)]
        pub const fn ier(&self) -> &IER {
            unsafe { &*(self as *const Self).cast::<u8>().add(36).cast() }
        }
        #[doc = "0x28 - FIFO Control Register"]
        #[inline(always)]
        pub const fn fcr(&self) -> &FCR {
            unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() }
        }
        #[doc = "0x28 - Interrupt Identification Register"]
        #[inline(always)]
        pub const fn iir(&self) -> &IIR {
            unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() }
        }
        #[doc = "0x2c - Line Control Register"]
        #[inline(always)]
        pub const fn lcr(&self) -> &LCR {
            &self.lcr
        }
        #[doc = "0x30 - Modem Control Register ("]
        #[inline(always)]
        pub const fn mcr(&self) -> &MCR {
            &self.mcr
        }
        #[doc = "0x34 - Line Status Register"]
        #[inline(always)]
        pub const fn lsr(&self) -> &LSR {
            &self.lsr
        }
        #[doc = "0x38 - Modem Status Register"]
        #[inline(always)]
        pub const fn msr(&self) -> &MSR {
            &self.msr
        }
        #[doc = "0x3c - GPR Register"]
        #[inline(always)]
        pub const fn gpr(&self) -> &GPR {
            &self.gpr
        }
    }
    #[doc = "IDLE_CFG (rw) register accessor: Idle Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idle_cfg`]
module"]
    pub type IDLE_CFG = crate::Reg<idle_cfg::IDLE_CFG_SPEC>;
    #[doc = "Idle Configuration Register"]
    pub mod idle_cfg {
        #[doc = "Register `IDLE_CFG` reader"]
        pub type R = crate::R<IDLE_CFG_SPEC>;
        #[doc = "Register `IDLE_CFG` writer"]
        pub type W = crate::W<IDLE_CFG_SPEC>;
        #[doc = "Field `RX_IDLE_THR` reader - Threshold for UART Receive Idle detection (in terms of bits)"]
        pub type RX_IDLE_THR_R = crate::FieldReader;
        #[doc = "Field `RX_IDLE_THR` writer - Threshold for UART Receive Idle detection (in terms of bits)"]
        pub type RX_IDLE_THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `RX_IDLE_EN` reader - UART Idle Detect Enable 0 - Disable 1 - Enable it should be enabled if enable address match feature"]
        pub type RX_IDLE_EN_R = crate::BitReader;
        #[doc = "Field `RX_IDLE_EN` writer - UART Idle Detect Enable 0 - Disable 1 - Enable it should be enabled if enable address match feature"]
        pub type RX_IDLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RX_IDLE_COND` reader - IDLE Detection Condition 0 - Treat as idle if RX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
        pub type RX_IDLE_COND_R = crate::BitReader;
        #[doc = "Field `RX_IDLE_COND` writer - IDLE Detection Condition 0 - Treat as idle if RX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
        pub type RX_IDLE_COND_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXEN` reader - UART receive enable. 0 - hold RX input to high, avoide wrong data input when config pinmux 1 - bypass RX input from PIN software should set it after config pinmux"]
        pub type RXEN_R = crate::BitReader;
        #[doc = "Field `RXEN` writer - UART receive enable. 0 - hold RX input to high, avoide wrong data input when config pinmux 1 - bypass RX input from PIN software should set it after config pinmux"]
        pub type RXEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TX_IDLE_THR` reader - Threshold for UART transmit Idle detection (in terms of bits)"]
        pub type TX_IDLE_THR_R = crate::FieldReader;
        #[doc = "Field `TX_IDLE_THR` writer - Threshold for UART transmit Idle detection (in terms of bits)"]
        pub type TX_IDLE_THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `TX_IDLE_EN` reader - UART TX Idle Detect Enable 0 - Disable 1 - Enable"]
        pub type TX_IDLE_EN_R = crate::BitReader;
        #[doc = "Field `TX_IDLE_EN` writer - UART TX Idle Detect Enable 0 - Disable 1 - Enable"]
        pub type TX_IDLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TX_IDLE_COND` reader - IDLE Detection Condition 0 - Treat as idle if TX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
        pub type TX_IDLE_COND_R = crate::BitReader;
        #[doc = "Field `TX_IDLE_COND` writer - IDLE Detection Condition 0 - Treat as idle if TX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
        pub type TX_IDLE_COND_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:7 - Threshold for UART Receive Idle detection (in terms of bits)"]
            #[inline(always)]
            pub fn rx_idle_thr(&self) -> RX_IDLE_THR_R {
                RX_IDLE_THR_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bit 8 - UART Idle Detect Enable 0 - Disable 1 - Enable it should be enabled if enable address match feature"]
            #[inline(always)]
            pub fn rx_idle_en(&self) -> RX_IDLE_EN_R {
                RX_IDLE_EN_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - IDLE Detection Condition 0 - Treat as idle if RX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
            #[inline(always)]
            pub fn rx_idle_cond(&self) -> RX_IDLE_COND_R {
                RX_IDLE_COND_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 11 - UART receive enable. 0 - hold RX input to high, avoide wrong data input when config pinmux 1 - bypass RX input from PIN software should set it after config pinmux"]
            #[inline(always)]
            pub fn rxen(&self) -> RXEN_R {
                RXEN_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bits 16:23 - Threshold for UART transmit Idle detection (in terms of bits)"]
            #[inline(always)]
            pub fn tx_idle_thr(&self) -> TX_IDLE_THR_R {
                TX_IDLE_THR_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bit 24 - UART TX Idle Detect Enable 0 - Disable 1 - Enable"]
            #[inline(always)]
            pub fn tx_idle_en(&self) -> TX_IDLE_EN_R {
                TX_IDLE_EN_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - IDLE Detection Condition 0 - Treat as idle if TX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
            #[inline(always)]
            pub fn tx_idle_cond(&self) -> TX_IDLE_COND_R {
                TX_IDLE_COND_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Threshold for UART Receive Idle detection (in terms of bits)"]
            #[inline(always)]
            #[must_use]
            pub fn rx_idle_thr(&mut self) -> RX_IDLE_THR_W<IDLE_CFG_SPEC> {
                RX_IDLE_THR_W::new(self, 0)
            }
            #[doc = "Bit 8 - UART Idle Detect Enable 0 - Disable 1 - Enable it should be enabled if enable address match feature"]
            #[inline(always)]
            #[must_use]
            pub fn rx_idle_en(&mut self) -> RX_IDLE_EN_W<IDLE_CFG_SPEC> {
                RX_IDLE_EN_W::new(self, 8)
            }
            #[doc = "Bit 9 - IDLE Detection Condition 0 - Treat as idle if RX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
            #[inline(always)]
            #[must_use]
            pub fn rx_idle_cond(&mut self) -> RX_IDLE_COND_W<IDLE_CFG_SPEC> {
                RX_IDLE_COND_W::new(self, 9)
            }
            #[doc = "Bit 11 - UART receive enable. 0 - hold RX input to high, avoide wrong data input when config pinmux 1 - bypass RX input from PIN software should set it after config pinmux"]
            #[inline(always)]
            #[must_use]
            pub fn rxen(&mut self) -> RXEN_W<IDLE_CFG_SPEC> {
                RXEN_W::new(self, 11)
            }
            #[doc = "Bits 16:23 - Threshold for UART transmit Idle detection (in terms of bits)"]
            #[inline(always)]
            #[must_use]
            pub fn tx_idle_thr(&mut self) -> TX_IDLE_THR_W<IDLE_CFG_SPEC> {
                TX_IDLE_THR_W::new(self, 16)
            }
            #[doc = "Bit 24 - UART TX Idle Detect Enable 0 - Disable 1 - Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tx_idle_en(&mut self) -> TX_IDLE_EN_W<IDLE_CFG_SPEC> {
                TX_IDLE_EN_W::new(self, 24)
            }
            #[doc = "Bit 25 - IDLE Detection Condition 0 - Treat as idle if TX pin is logic one 1 - Treat as idle if UART state machine state is idle"]
            #[inline(always)]
            #[must_use]
            pub fn tx_idle_cond(&mut self) -> TX_IDLE_COND_W<IDLE_CFG_SPEC> {
                TX_IDLE_COND_W::new(self, 25)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Idle Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idle_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idle_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IDLE_CFG_SPEC;
        impl crate::RegisterSpec for IDLE_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`idle_cfg::R`](R) reader structure"]
        impl crate::Readable for IDLE_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`idle_cfg::W`](W) writer structure"]
        impl crate::Writable for IDLE_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IDLE_CFG to value 0"]
        impl crate::Resettable for IDLE_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ADDR_CFG (rw) register accessor: address match config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr_cfg`]
module"]
    pub type ADDR_CFG = crate::Reg<addr_cfg::ADDR_CFG_SPEC>;
    #[doc = "address match config register"]
    pub mod addr_cfg {
        #[doc = "Register `ADDR_CFG` reader"]
        pub type R = crate::R<ADDR_CFG_SPEC>;
        #[doc = "Register `ADDR_CFG` writer"]
        pub type W = crate::W<ADDR_CFG_SPEC>;
        #[doc = "Field `ADDR0` reader - address 0 field."]
        pub type ADDR0_R = crate::FieldReader;
        #[doc = "Field `ADDR0` writer - address 0 field."]
        pub type ADDR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `ADDR1` reader - address 1 fileld. in 9bit mode, this is the full address byte. For other mode(8/7/6/5bit), MSB should be set for address flag. If want address==0 to be matched at 8bit mode, should set addr1=0x80"]
        pub type ADDR1_R = crate::FieldReader;
        #[doc = "Field `ADDR1` writer - address 1 fileld. in 9bit mode, this is the full address byte. For other mode(8/7/6/5bit), MSB should be set for address flag. If want address==0 to be matched at 8bit mode, should set addr1=0x80"]
        pub type ADDR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `A0_EN` reader - enable addr0 compare for the first character"]
        pub type A0_EN_R = crate::BitReader;
        #[doc = "Field `A0_EN` writer - enable addr0 compare for the first character"]
        pub type A0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `A1_EN` reader - enable addr1 compare for the first character. If a1_en OR a0_en, then do not receive data if address not match. If ~a1_en AND ~a0_en, the receive all data like before. NOTE: should set idle_tmout_en if enable address match feature"]
        pub type A1_EN_R = crate::BitReader;
        #[doc = "Field `A1_EN` writer - enable addr1 compare for the first character. If a1_en OR a0_en, then do not receive data if address not match. If ~a1_en AND ~a0_en, the receive all data like before. NOTE: should set idle_tmout_en if enable address match feature"]
        pub type A1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXEN_9BIT` reader - set to use 9bit mode for receiver, only valid if rxen_addr_msb is set"]
        pub type RXEN_9BIT_R = crate::BitReader;
        #[doc = "Field `RXEN_9BIT` writer - set to use 9bit mode for receiver, only valid if rxen_addr_msb is set"]
        pub type RXEN_9BIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXEN_ADDR_MSB` reader - set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). Clr to use first character as address. Only needed if enable address match feature"]
        pub type RXEN_ADDR_MSB_R = crate::BitReader;
        #[doc = "Field `RXEN_ADDR_MSB` writer - set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). Clr to use first character as address. Only needed if enable address match feature"]
        pub type RXEN_ADDR_MSB_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXEN_9BIT` reader - set to use 9bit mode for transmitter, will set the MSB for the first character as address flag, keep 0 for others."]
        pub type TXEN_9BIT_R = crate::BitReader;
        #[doc = "Field `TXEN_9BIT` writer - set to use 9bit mode for transmitter, will set the MSB for the first character as address flag, keep 0 for others."]
        pub type TXEN_9BIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:7 - address 0 field."]
            #[inline(always)]
            pub fn addr0(&self) -> ADDR0_R {
                ADDR0_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - address 1 fileld. in 9bit mode, this is the full address byte. For other mode(8/7/6/5bit), MSB should be set for address flag. If want address==0 to be matched at 8bit mode, should set addr1=0x80"]
            #[inline(always)]
            pub fn addr1(&self) -> ADDR1_R {
                ADDR1_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bit 16 - enable addr0 compare for the first character"]
            #[inline(always)]
            pub fn a0_en(&self) -> A0_EN_R {
                A0_EN_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - enable addr1 compare for the first character. If a1_en OR a0_en, then do not receive data if address not match. If ~a1_en AND ~a0_en, the receive all data like before. NOTE: should set idle_tmout_en if enable address match feature"]
            #[inline(always)]
            pub fn a1_en(&self) -> A1_EN_R {
                A1_EN_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - set to use 9bit mode for receiver, only valid if rxen_addr_msb is set"]
            #[inline(always)]
            pub fn rxen_9bit(&self) -> RXEN_9BIT_R {
                RXEN_9BIT_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). Clr to use first character as address. Only needed if enable address match feature"]
            #[inline(always)]
            pub fn rxen_addr_msb(&self) -> RXEN_ADDR_MSB_R {
                RXEN_ADDR_MSB_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - set to use 9bit mode for transmitter, will set the MSB for the first character as address flag, keep 0 for others."]
            #[inline(always)]
            pub fn txen_9bit(&self) -> TXEN_9BIT_R {
                TXEN_9BIT_R::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - address 0 field."]
            #[inline(always)]
            #[must_use]
            pub fn addr0(&mut self) -> ADDR0_W<ADDR_CFG_SPEC> {
                ADDR0_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - address 1 fileld. in 9bit mode, this is the full address byte. For other mode(8/7/6/5bit), MSB should be set for address flag. If want address==0 to be matched at 8bit mode, should set addr1=0x80"]
            #[inline(always)]
            #[must_use]
            pub fn addr1(&mut self) -> ADDR1_W<ADDR_CFG_SPEC> {
                ADDR1_W::new(self, 8)
            }
            #[doc = "Bit 16 - enable addr0 compare for the first character"]
            #[inline(always)]
            #[must_use]
            pub fn a0_en(&mut self) -> A0_EN_W<ADDR_CFG_SPEC> {
                A0_EN_W::new(self, 16)
            }
            #[doc = "Bit 17 - enable addr1 compare for the first character. If a1_en OR a0_en, then do not receive data if address not match. If ~a1_en AND ~a0_en, the receive all data like before. NOTE: should set idle_tmout_en if enable address match feature"]
            #[inline(always)]
            #[must_use]
            pub fn a1_en(&mut self) -> A1_EN_W<ADDR_CFG_SPEC> {
                A1_EN_W::new(self, 17)
            }
            #[doc = "Bit 18 - set to use 9bit mode for receiver, only valid if rxen_addr_msb is set"]
            #[inline(always)]
            #[must_use]
            pub fn rxen_9bit(&mut self) -> RXEN_9BIT_W<ADDR_CFG_SPEC> {
                RXEN_9BIT_W::new(self, 18)
            }
            #[doc = "Bit 19 - set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). Clr to use first character as address. Only needed if enable address match feature"]
            #[inline(always)]
            #[must_use]
            pub fn rxen_addr_msb(&mut self) -> RXEN_ADDR_MSB_W<ADDR_CFG_SPEC> {
                RXEN_ADDR_MSB_W::new(self, 19)
            }
            #[doc = "Bit 20 - set to use 9bit mode for transmitter, will set the MSB for the first character as address flag, keep 0 for others."]
            #[inline(always)]
            #[must_use]
            pub fn txen_9bit(&mut self) -> TXEN_9BIT_W<ADDR_CFG_SPEC> {
                TXEN_9BIT_W::new(self, 20)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "address match config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADDR_CFG_SPEC;
        impl crate::RegisterSpec for ADDR_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`addr_cfg::R`](R) reader structure"]
        impl crate::Readable for ADDR_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`addr_cfg::W`](W) writer structure"]
        impl crate::Writable for ADDR_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ADDR_CFG to value 0"]
        impl crate::Resettable for ADDR_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IIR2 (rw) register accessor: Interrupt Identification Register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir2`]
module"]
    pub type IIR2 = crate::Reg<iir2::IIR2_SPEC>;
    #[doc = "Interrupt Identification Register2"]
    pub mod iir2 {
        #[doc = "Register `IIR2` reader"]
        pub type R = crate::R<IIR2_SPEC>;
        #[doc = "Register `IIR2` writer"]
        pub type W = crate::W<IIR2_SPEC>;
        #[doc = "Field `INTRID` reader - Interrupt ID, see IIR2 for detail decoding"]
        pub type INTRID_R = crate::FieldReader;
        #[doc = "Field `FIFOED` reader - FIFOs enabled These two bits are 1 when bit 0 of the FIFO Control Register (FIFOE) is set to 1."]
        pub type FIFOED_R = crate::FieldReader;
        #[doc = "Field `DATA_LOST` writer - assert if data lost before address match status, write one clear; It will not assert if no address match occurs"]
        pub type DATA_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ADDR_MATCH_IDLE` writer - address match and idle irq status, assert at rx bus idle if address match event triggered. Write one clear;"]
        pub type ADDR_MATCH_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ADDR_MATCH` writer - address match irq status, assert if either address match(and enabled). Write one clear NOTE: the address byte may not moved by DMA at this point. User can wait next addr_match_idle irq for the whole data include address"]
        pub type ADDR_MATCH_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXIDLE_FLAG` writer - UART TX IDLE Flag, assert after txd low and then tx idle timeout, write one clear 0 - UART TX is busy 1 - UART TX is idle"]
        pub type TXIDLE_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXIDLE_FLAG` writer - UART RX IDLE Flag, assert after rxd low and then rx idle timeout, write one clear 0 - UART RX is busy 1 - UART RX is idle"]
        pub type RXIDLE_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3 - Interrupt ID, see IIR2 for detail decoding"]
            #[inline(always)]
            pub fn intrid(&self) -> INTRID_R {
                INTRID_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 6:7 - FIFOs enabled These two bits are 1 when bit 0 of the FIFO Control Register (FIFOE) is set to 1."]
            #[inline(always)]
            pub fn fifoed(&self) -> FIFOED_R {
                FIFOED_R::new(((self.bits >> 6) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 27 - assert if data lost before address match status, write one clear; It will not assert if no address match occurs"]
            #[inline(always)]
            #[must_use]
            pub fn data_lost(&mut self) -> DATA_LOST_W<IIR2_SPEC> {
                DATA_LOST_W::new(self, 27)
            }
            #[doc = "Bit 28 - address match and idle irq status, assert at rx bus idle if address match event triggered. Write one clear;"]
            #[inline(always)]
            #[must_use]
            pub fn addr_match_idle(&mut self) -> ADDR_MATCH_IDLE_W<IIR2_SPEC> {
                ADDR_MATCH_IDLE_W::new(self, 28)
            }
            #[doc = "Bit 29 - address match irq status, assert if either address match(and enabled). Write one clear NOTE: the address byte may not moved by DMA at this point. User can wait next addr_match_idle irq for the whole data include address"]
            #[inline(always)]
            #[must_use]
            pub fn addr_match(&mut self) -> ADDR_MATCH_W<IIR2_SPEC> {
                ADDR_MATCH_W::new(self, 29)
            }
            #[doc = "Bit 30 - UART TX IDLE Flag, assert after txd low and then tx idle timeout, write one clear 0 - UART TX is busy 1 - UART TX is idle"]
            #[inline(always)]
            #[must_use]
            pub fn txidle_flag(&mut self) -> TXIDLE_FLAG_W<IIR2_SPEC> {
                TXIDLE_FLAG_W::new(self, 30)
            }
            #[doc = "Bit 31 - UART RX IDLE Flag, assert after rxd low and then rx idle timeout, write one clear 0 - UART RX is busy 1 - UART RX is idle"]
            #[inline(always)]
            #[must_use]
            pub fn rxidle_flag(&mut self) -> RXIDLE_FLAG_W<IIR2_SPEC> {
                RXIDLE_FLAG_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Identification Register2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IIR2_SPEC;
        impl crate::RegisterSpec for IIR2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`iir2::R`](R) reader structure"]
        impl crate::Readable for IIR2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`iir2::W`](W) writer structure"]
        impl crate::Writable for IIR2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IIR2 to value 0x01"]
        impl crate::Resettable for IIR2_SPEC {
            const RESET_VALUE: u32 = 0x01;
        }
    }
    #[doc = "Cfg (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
    pub type CFG = crate::Reg<cfg::CFG_SPEC>;
    #[doc = "Configuration Register"]
    pub mod cfg {
        #[doc = "Register `Cfg` reader"]
        pub type R = crate::R<CFG_SPEC>;
        #[doc = "Register `Cfg` writer"]
        pub type W = crate::W<CFG_SPEC>;
        #[doc = "Field `FIFOSIZE` reader - The depth of RXFIFO and TXFIFO 0: 16-byte FIFO 1: 32-byte FIFO 2: 64-byte FIFO 3: 128-byte FIFO"]
        pub type FIFOSIZE_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:1 - The depth of RXFIFO and TXFIFO 0: 16-byte FIFO 1: 32-byte FIFO 2: 64-byte FIFO 3: 128-byte FIFO"]
            #[inline(always)]
            pub fn fifosize(&self) -> FIFOSIZE_R {
                FIFOSIZE_R::new((self.bits & 3) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CFG_SPEC;
        impl crate::RegisterSpec for CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
        impl crate::Readable for CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
        impl crate::Writable for CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Cfg to value 0"]
        impl crate::Resettable for CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "OSCR (rw) register accessor: Over Sample Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oscr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oscr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oscr`]
module"]
    pub type OSCR = crate::Reg<oscr::OSCR_SPEC>;
    #[doc = "Over Sample Control Register"]
    pub mod oscr {
        #[doc = "Register `OSCR` reader"]
        pub type R = crate::R<OSCR_SPEC>;
        #[doc = "Register `OSCR` writer"]
        pub type W = crate::W<OSCR_SPEC>;
        #[doc = "Field `OSC` reader - Over-sample control The value must be an even number; any odd value writes to this field will be converted to an even value. OSC=0: The over-sample ratio is 32 OSC&lt;=8: The over-sample ratio is 8 8 &lt; OSC&lt; 32: The over sample ratio is OSC"]
        pub type OSC_R = crate::FieldReader;
        #[doc = "Field `OSC` writer - Over-sample control The value must be an even number; any odd value writes to this field will be converted to an even value. OSC=0: The over-sample ratio is 32 OSC&lt;=8: The over-sample ratio is 8 8 &lt; OSC&lt; 32: The over sample ratio is OSC"]
        pub type OSC_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:4 - Over-sample control The value must be an even number; any odd value writes to this field will be converted to an even value. OSC=0: The over-sample ratio is 32 OSC&lt;=8: The over-sample ratio is 8 8 &lt; OSC&lt; 32: The over sample ratio is OSC"]
            #[inline(always)]
            pub fn osc(&self) -> OSC_R {
                OSC_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - Over-sample control The value must be an even number; any odd value writes to this field will be converted to an even value. OSC=0: The over-sample ratio is 32 OSC&lt;=8: The over-sample ratio is 8 8 &lt; OSC&lt; 32: The over sample ratio is OSC"]
            #[inline(always)]
            #[must_use]
            pub fn osc(&mut self) -> OSC_W<OSCR_SPEC> {
                OSC_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Over Sample Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oscr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oscr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct OSCR_SPEC;
        impl crate::RegisterSpec for OSCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`oscr::R`](R) reader structure"]
        impl crate::Readable for OSCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`oscr::W`](W) writer structure"]
        impl crate::Writable for OSCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets OSCR to value 0x10"]
        impl crate::Resettable for OSCR_SPEC {
            const RESET_VALUE: u32 = 0x10;
        }
    }
    #[doc = "FCRR (rw) register accessor: FIFO Control Register config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcrr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcrr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcrr`]
module"]
    pub type FCRR = crate::Reg<fcrr::FCRR_SPEC>;
    #[doc = "FIFO Control Register config"]
    pub mod fcrr {
        #[doc = "Register `FCRR` reader"]
        pub type R = crate::R<FCRR_SPEC>;
        #[doc = "Register `FCRR` writer"]
        pub type W = crate::W<FCRR_SPEC>;
        #[doc = "Field `FIFOE` reader - FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles."]
        pub type FIFOE_R = crate::BitReader;
        #[doc = "Field `FIFOE` writer - FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles."]
        pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RFIFORST` writer - Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared."]
        pub type RFIFORST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFIFORST` writer - Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared."]
        pub type TFIFORST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMAE` reader - DMA enable 0: Disable 1: Enable"]
        pub type DMAE_R = crate::BitReader;
        #[doc = "Field `DMAE` writer - DMA enable 0: Disable 1: Enable"]
        pub type DMAE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFIFOT` reader - Transmitter FIFO trigger level"]
        pub type TFIFOT_R = crate::FieldReader;
        #[doc = "Field `TFIFOT` writer - Transmitter FIFO trigger level"]
        pub type TFIFOT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `RFIFOT` reader - Receiver FIFO trigger level"]
        pub type RFIFOT_R = crate::FieldReader;
        #[doc = "Field `RFIFOT` writer - Receiver FIFO trigger level"]
        pub type RFIFOT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `RFIFOT4` reader - rxfifo threshold(0 for 1byte, 0xF for 16bytes). Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled"]
        pub type RFIFOT4_R = crate::FieldReader;
        #[doc = "Field `RFIFOT4` writer - rxfifo threshold(0 for 1byte, 0xF for 16bytes). Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled"]
        pub type RFIFOT4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `TFIFOT4` reader - txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold."]
        pub type TFIFOT4_R = crate::FieldReader;
        #[doc = "Field `TFIFOT4` writer - txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold."]
        pub type TFIFOT4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `FIFOT4EN` reader - set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) clr to use 2bit(TFIFOT and RFIFOT)"]
        pub type FIFOT4EN_R = crate::BitReader;
        #[doc = "Field `FIFOT4EN` writer - set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) clr to use 2bit(TFIFOT and RFIFOT)"]
        pub type FIFOT4EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles."]
            #[inline(always)]
            pub fn fifoe(&self) -> FIFOE_R {
                FIFOE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 3 - DMA enable 0: Disable 1: Enable"]
            #[inline(always)]
            pub fn dmae(&self) -> DMAE_R {
                DMAE_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 4:5 - Transmitter FIFO trigger level"]
            #[inline(always)]
            pub fn tfifot(&self) -> TFIFOT_R {
                TFIFOT_R::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bits 6:7 - Receiver FIFO trigger level"]
            #[inline(always)]
            pub fn rfifot(&self) -> RFIFOT_R {
                RFIFOT_R::new(((self.bits >> 6) & 3) as u8)
            }
            #[doc = "Bits 8:11 - rxfifo threshold(0 for 1byte, 0xF for 16bytes). Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled"]
            #[inline(always)]
            pub fn rfifot4(&self) -> RFIFOT4_R {
                RFIFOT4_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            #[doc = "Bits 16:19 - txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold."]
            #[inline(always)]
            pub fn tfifot4(&self) -> TFIFOT4_R {
                TFIFOT4_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bit 23 - set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) clr to use 2bit(TFIFOT and RFIFOT)"]
            #[inline(always)]
            pub fn fifot4en(&self) -> FIFOT4EN_R {
                FIFOT4EN_R::new(((self.bits >> 23) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles."]
            #[inline(always)]
            #[must_use]
            pub fn fifoe(&mut self) -> FIFOE_W<FCRR_SPEC> {
                FIFOE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared."]
            #[inline(always)]
            #[must_use]
            pub fn rfiforst(&mut self) -> RFIFORST_W<FCRR_SPEC> {
                RFIFORST_W::new(self, 1)
            }
            #[doc = "Bit 2 - Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared."]
            #[inline(always)]
            #[must_use]
            pub fn tfiforst(&mut self) -> TFIFORST_W<FCRR_SPEC> {
                TFIFORST_W::new(self, 2)
            }
            #[doc = "Bit 3 - DMA enable 0: Disable 1: Enable"]
            #[inline(always)]
            #[must_use]
            pub fn dmae(&mut self) -> DMAE_W<FCRR_SPEC> {
                DMAE_W::new(self, 3)
            }
            #[doc = "Bits 4:5 - Transmitter FIFO trigger level"]
            #[inline(always)]
            #[must_use]
            pub fn tfifot(&mut self) -> TFIFOT_W<FCRR_SPEC> {
                TFIFOT_W::new(self, 4)
            }
            #[doc = "Bits 6:7 - Receiver FIFO trigger level"]
            #[inline(always)]
            #[must_use]
            pub fn rfifot(&mut self) -> RFIFOT_W<FCRR_SPEC> {
                RFIFOT_W::new(self, 6)
            }
            #[doc = "Bits 8:11 - rxfifo threshold(0 for 1byte, 0xF for 16bytes). Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled"]
            #[inline(always)]
            #[must_use]
            pub fn rfifot4(&mut self) -> RFIFOT4_W<FCRR_SPEC> {
                RFIFOT4_W::new(self, 8)
            }
            #[doc = "Bits 16:19 - txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold."]
            #[inline(always)]
            #[must_use]
            pub fn tfifot4(&mut self) -> TFIFOT4_W<FCRR_SPEC> {
                TFIFOT4_W::new(self, 16)
            }
            #[doc = "Bit 23 - set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) clr to use 2bit(TFIFOT and RFIFOT)"]
            #[inline(always)]
            #[must_use]
            pub fn fifot4en(&mut self) -> FIFOT4EN_W<FCRR_SPEC> {
                FIFOT4EN_W::new(self, 23)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "FIFO Control Register config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcrr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcrr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FCRR_SPEC;
        impl crate::RegisterSpec for FCRR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`fcrr::R`](R) reader structure"]
        impl crate::Readable for FCRR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`fcrr::W`](W) writer structure"]
        impl crate::Writable for FCRR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FCRR to value 0"]
        impl crate::Resettable for FCRR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "MOTO_CFG (rw) register accessor: moto system control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`moto_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`moto_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@moto_cfg`]
module"]
    pub type MOTO_CFG = crate::Reg<moto_cfg::MOTO_CFG_SPEC>;
    #[doc = "moto system control register"]
    pub mod moto_cfg {
        #[doc = "Register `MOTO_CFG` reader"]
        pub type R = crate::R<MOTO_CFG_SPEC>;
        #[doc = "Register `MOTO_CFG` writer"]
        pub type W = crate::W<MOTO_CFG_SPEC>;
        #[doc = "Field `TXSTOP_INSERT` reader - set to insert STOP bits between each tx byte till tx fifo empty. NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set"]
        pub type TXSTOP_INSERT_R = crate::BitReader;
        #[doc = "Field `TXSTOP_INSERT` writer - set to insert STOP bits between each tx byte till tx fifo empty. NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set"]
        pub type TXSTOP_INSERT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRG_CLR_RFIFO` reader - set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo."]
        pub type TRG_CLR_RFIFO_R = crate::BitReader;
        #[doc = "Field `TRG_CLR_RFIFO` writer - set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo."]
        pub type TRG_CLR_RFIFO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRG_MODE` reader - set to enable trigger mode. software should push needed data into txbuffer frist, uart will not start transmission at this time. User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty NOTE: the hw_trigger should be pulse signal from trig mux."]
        pub type TRG_MODE_R = crate::BitReader;
        #[doc = "Field `TRG_MODE` writer - set to enable trigger mode. software should push needed data into txbuffer frist, uart will not start transmission at this time. User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty NOTE: the hw_trigger should be pulse signal from trig mux."]
        pub type TRG_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HWTRG_EN` reader - set to enable hardware trigger(trigger from moto is shared by other UART)"]
        pub type HWTRG_EN_R = crate::BitReader;
        #[doc = "Field `HWTRG_EN` writer - set to enable hardware trigger(trigger from moto is shared by other UART)"]
        pub type HWTRG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXSTP_BITS` reader - if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits"]
        pub type TXSTP_BITS_R = crate::FieldReader;
        #[doc = "Field `TXSTP_BITS` writer - if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits"]
        pub type TXSTP_BITS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `SWTRG` writer - software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. Hardware auto reset."]
        pub type SWTRG_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 4 - set to insert STOP bits between each tx byte till tx fifo empty. NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set"]
            #[inline(always)]
            pub fn txstop_insert(&self) -> TXSTOP_INSERT_R {
                TXSTOP_INSERT_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo."]
            #[inline(always)]
            pub fn trg_clr_rfifo(&self) -> TRG_CLR_RFIFO_R {
                TRG_CLR_RFIFO_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - set to enable trigger mode. software should push needed data into txbuffer frist, uart will not start transmission at this time. User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty NOTE: the hw_trigger should be pulse signal from trig mux."]
            #[inline(always)]
            pub fn trg_mode(&self) -> TRG_MODE_R {
                TRG_MODE_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - set to enable hardware trigger(trigger from moto is shared by other UART)"]
            #[inline(always)]
            pub fn hwtrg_en(&self) -> HWTRG_EN_R {
                HWTRG_EN_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:15 - if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits"]
            #[inline(always)]
            pub fn txstp_bits(&self) -> TXSTP_BITS_R {
                TXSTP_BITS_R::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bit 4 - set to insert STOP bits between each tx byte till tx fifo empty. NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set"]
            #[inline(always)]
            #[must_use]
            pub fn txstop_insert(&mut self) -> TXSTOP_INSERT_W<MOTO_CFG_SPEC> {
                TXSTOP_INSERT_W::new(self, 4)
            }
            #[doc = "Bit 5 - set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo."]
            #[inline(always)]
            #[must_use]
            pub fn trg_clr_rfifo(&mut self) -> TRG_CLR_RFIFO_W<MOTO_CFG_SPEC> {
                TRG_CLR_RFIFO_W::new(self, 5)
            }
            #[doc = "Bit 6 - set to enable trigger mode. software should push needed data into txbuffer frist, uart will not start transmission at this time. User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty NOTE: the hw_trigger should be pulse signal from trig mux."]
            #[inline(always)]
            #[must_use]
            pub fn trg_mode(&mut self) -> TRG_MODE_W<MOTO_CFG_SPEC> {
                TRG_MODE_W::new(self, 6)
            }
            #[doc = "Bit 7 - set to enable hardware trigger(trigger from moto is shared by other UART)"]
            #[inline(always)]
            #[must_use]
            pub fn hwtrg_en(&mut self) -> HWTRG_EN_W<MOTO_CFG_SPEC> {
                HWTRG_EN_W::new(self, 7)
            }
            #[doc = "Bits 8:15 - if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits"]
            #[inline(always)]
            #[must_use]
            pub fn txstp_bits(&mut self) -> TXSTP_BITS_W<MOTO_CFG_SPEC> {
                TXSTP_BITS_W::new(self, 8)
            }
            #[doc = "Bit 31 - software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. Hardware auto reset."]
            #[inline(always)]
            #[must_use]
            pub fn swtrg(&mut self) -> SWTRG_W<MOTO_CFG_SPEC> {
                SWTRG_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "moto system control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`moto_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`moto_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MOTO_CFG_SPEC;
        impl crate::RegisterSpec for MOTO_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`moto_cfg::R`](R) reader structure"]
        impl crate::Readable for MOTO_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`moto_cfg::W`](W) writer structure"]
        impl crate::Writable for MOTO_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets MOTO_CFG to value 0"]
        impl crate::Resettable for MOTO_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RBR (rw) register accessor: Receiver Buffer Register (when DLAB = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rbr`]
module"]
    pub type RBR = crate::Reg<rbr::RBR_SPEC>;
    #[doc = "Receiver Buffer Register (when DLAB = 0)"]
    pub mod rbr {
        #[doc = "Register `RBR` reader"]
        pub type R = crate::R<RBR_SPEC>;
        #[doc = "Register `RBR` writer"]
        pub type W = crate::W<RBR_SPEC>;
        #[doc = "Field `RBR` reader - Receive data read port"]
        pub type RBR_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Receive data read port"]
            #[inline(always)]
            pub fn rbr(&self) -> RBR_R {
                RBR_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Receiver Buffer Register (when DLAB = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rbr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rbr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RBR_SPEC;
        impl crate::RegisterSpec for RBR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rbr::R`](R) reader structure"]
        impl crate::Readable for RBR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rbr::W`](W) writer structure"]
        impl crate::Writable for RBR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RBR to value 0"]
        impl crate::Resettable for RBR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "THR (rw) register accessor: Transmitter Holding Register (when DLAB = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thr`]
module"]
    pub type THR = crate::Reg<thr::THR_SPEC>;
    #[doc = "Transmitter Holding Register (when DLAB = 0)"]
    pub mod thr {
        #[doc = "Register `THR` reader"]
        pub type R = crate::R<THR_SPEC>;
        #[doc = "Register `THR` writer"]
        pub type W = crate::W<THR_SPEC>;
        #[doc = "Field `THR` writer - Transmit data write port"]
        pub type THR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl W {
            #[doc = "Bits 0:7 - Transmit data write port"]
            #[inline(always)]
            #[must_use]
            pub fn thr(&mut self) -> THR_W<THR_SPEC> {
                THR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Transmitter Holding Register (when DLAB = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct THR_SPEC;
        impl crate::RegisterSpec for THR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`thr::R`](R) reader structure"]
        impl crate::Readable for THR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`thr::W`](W) writer structure"]
        impl crate::Writable for THR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets THR to value 0"]
        impl crate::Resettable for THR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DLL (rw) register accessor: Divisor Latch LSB (when DLAB = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dll`]
module"]
    pub type DLL = crate::Reg<dll::DLL_SPEC>;
    #[doc = "Divisor Latch LSB (when DLAB = 1)"]
    pub mod dll {
        #[doc = "Register `DLL` reader"]
        pub type R = crate::R<DLL_SPEC>;
        #[doc = "Register `DLL` writer"]
        pub type W = crate::W<DLL_SPEC>;
        #[doc = "Field `DLL` reader - Least significant byte of the Divisor Latch"]
        pub type DLL_R = crate::FieldReader;
        #[doc = "Field `DLL` writer - Least significant byte of the Divisor Latch"]
        pub type DLL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Least significant byte of the Divisor Latch"]
            #[inline(always)]
            pub fn dll(&self) -> DLL_R {
                DLL_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Least significant byte of the Divisor Latch"]
            #[inline(always)]
            #[must_use]
            pub fn dll(&mut self) -> DLL_W<DLL_SPEC> {
                DLL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Divisor Latch LSB (when DLAB = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dll::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dll::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DLL_SPEC;
        impl crate::RegisterSpec for DLL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dll::R`](R) reader structure"]
        impl crate::Readable for DLL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dll::W`](W) writer structure"]
        impl crate::Writable for DLL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DLL to value 0x01"]
        impl crate::Resettable for DLL_SPEC {
            const RESET_VALUE: u32 = 0x01;
        }
    }
    #[doc = "IER (rw) register accessor: Interrupt Enable Register (when DLAB = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ier`]
module"]
    pub type IER = crate::Reg<ier::IER_SPEC>;
    #[doc = "Interrupt Enable Register (when DLAB = 0)"]
    pub mod ier {
        #[doc = "Register `IER` reader"]
        pub type R = crate::R<IER_SPEC>;
        #[doc = "Register `IER` writer"]
        pub type W = crate::W<IER_SPEC>;
        #[doc = "Field `ERBI` reader - Enable received data available interrupt and the character timeout interrupt 0: Disable 1: Enable"]
        pub type ERBI_R = crate::BitReader;
        #[doc = "Field `ERBI` writer - Enable received data available interrupt and the character timeout interrupt 0: Disable 1: Enable"]
        pub type ERBI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ETHEI` reader - Enable transmitter holding register interrupt"]
        pub type ETHEI_R = crate::BitReader;
        #[doc = "Field `ETHEI` writer - Enable transmitter holding register interrupt"]
        pub type ETHEI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ELSI` reader - Enable receiver line status interrupt"]
        pub type ELSI_R = crate::BitReader;
        #[doc = "Field `ELSI` writer - Enable receiver line status interrupt"]
        pub type ELSI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EMSI` reader - Enable modem status interrupt The interrupt asserts when the status of one of the following occurs: The status of modem_rin, modem_dcdn, modem_dsrn or modem_ctsn (If the auto-cts mode is disabled) has been changed. If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), modem_ctsn would be used to control the transmitter."]
        pub type EMSI_R = crate::BitReader;
        #[doc = "Field `EMSI` writer - Enable modem status interrupt The interrupt asserts when the status of one of the following occurs: The status of modem_rin, modem_dcdn, modem_dsrn or modem_ctsn (If the auto-cts mode is disabled) has been changed. If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), modem_ctsn would be used to control the transmitter."]
        pub type EMSI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EDATLOST` reader - enable DATA_LOST interrupt"]
        pub type EDATLOST_R = crate::BitReader;
        #[doc = "Field `EDATLOST` writer - enable DATA_LOST interrupt"]
        pub type EDATLOST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EADDRM_IDLE` reader - enable ADDR_MATCH_IDLE interrupt"]
        pub type EADDRM_IDLE_R = crate::BitReader;
        #[doc = "Field `EADDRM_IDLE` writer - enable ADDR_MATCH_IDLE interrupt"]
        pub type EADDRM_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EADDRM` reader - enable ADDR_MATCH interrupt"]
        pub type EADDRM_R = crate::BitReader;
        #[doc = "Field `EADDRM` writer - enable ADDR_MATCH interrupt"]
        pub type EADDRM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ETXIDLE` reader - enable transmit idle interrupt"]
        pub type ETXIDLE_R = crate::BitReader;
        #[doc = "Field `ETXIDLE` writer - enable transmit idle interrupt"]
        pub type ETXIDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERXIDLE` reader - Enable Receive Idle interrupt 0 - Disable Idle interrupt 1 - Enable Idle interrupt"]
        pub type ERXIDLE_R = crate::BitReader;
        #[doc = "Field `ERXIDLE` writer - Enable Receive Idle interrupt 0 - Disable Idle interrupt 1 - Enable Idle interrupt"]
        pub type ERXIDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Enable received data available interrupt and the character timeout interrupt 0: Disable 1: Enable"]
            #[inline(always)]
            pub fn erbi(&self) -> ERBI_R {
                ERBI_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Enable transmitter holding register interrupt"]
            #[inline(always)]
            pub fn ethei(&self) -> ETHEI_R {
                ETHEI_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Enable receiver line status interrupt"]
            #[inline(always)]
            pub fn elsi(&self) -> ELSI_R {
                ELSI_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Enable modem status interrupt The interrupt asserts when the status of one of the following occurs: The status of modem_rin, modem_dcdn, modem_dsrn or modem_ctsn (If the auto-cts mode is disabled) has been changed. If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), modem_ctsn would be used to control the transmitter."]
            #[inline(always)]
            pub fn emsi(&self) -> EMSI_R {
                EMSI_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 27 - enable DATA_LOST interrupt"]
            #[inline(always)]
            pub fn edatlost(&self) -> EDATLOST_R {
                EDATLOST_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - enable ADDR_MATCH_IDLE interrupt"]
            #[inline(always)]
            pub fn eaddrm_idle(&self) -> EADDRM_IDLE_R {
                EADDRM_IDLE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - enable ADDR_MATCH interrupt"]
            #[inline(always)]
            pub fn eaddrm(&self) -> EADDRM_R {
                EADDRM_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - enable transmit idle interrupt"]
            #[inline(always)]
            pub fn etxidle(&self) -> ETXIDLE_R {
                ETXIDLE_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - Enable Receive Idle interrupt 0 - Disable Idle interrupt 1 - Enable Idle interrupt"]
            #[inline(always)]
            pub fn erxidle(&self) -> ERXIDLE_R {
                ERXIDLE_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable received data available interrupt and the character timeout interrupt 0: Disable 1: Enable"]
            #[inline(always)]
            #[must_use]
            pub fn erbi(&mut self) -> ERBI_W<IER_SPEC> {
                ERBI_W::new(self, 0)
            }
            #[doc = "Bit 1 - Enable transmitter holding register interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn ethei(&mut self) -> ETHEI_W<IER_SPEC> {
                ETHEI_W::new(self, 1)
            }
            #[doc = "Bit 2 - Enable receiver line status interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn elsi(&mut self) -> ELSI_W<IER_SPEC> {
                ELSI_W::new(self, 2)
            }
            #[doc = "Bit 3 - Enable modem status interrupt The interrupt asserts when the status of one of the following occurs: The status of modem_rin, modem_dcdn, modem_dsrn or modem_ctsn (If the auto-cts mode is disabled) has been changed. If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), modem_ctsn would be used to control the transmitter."]
            #[inline(always)]
            #[must_use]
            pub fn emsi(&mut self) -> EMSI_W<IER_SPEC> {
                EMSI_W::new(self, 3)
            }
            #[doc = "Bit 27 - enable DATA_LOST interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn edatlost(&mut self) -> EDATLOST_W<IER_SPEC> {
                EDATLOST_W::new(self, 27)
            }
            #[doc = "Bit 28 - enable ADDR_MATCH_IDLE interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn eaddrm_idle(&mut self) -> EADDRM_IDLE_W<IER_SPEC> {
                EADDRM_IDLE_W::new(self, 28)
            }
            #[doc = "Bit 29 - enable ADDR_MATCH interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn eaddrm(&mut self) -> EADDRM_W<IER_SPEC> {
                EADDRM_W::new(self, 29)
            }
            #[doc = "Bit 30 - enable transmit idle interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn etxidle(&mut self) -> ETXIDLE_W<IER_SPEC> {
                ETXIDLE_W::new(self, 30)
            }
            #[doc = "Bit 31 - Enable Receive Idle interrupt 0 - Disable Idle interrupt 1 - Enable Idle interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn erxidle(&mut self) -> ERXIDLE_W<IER_SPEC> {
                ERXIDLE_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Enable Register (when DLAB = 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ier::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IER_SPEC;
        impl crate::RegisterSpec for IER_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ier::R`](R) reader structure"]
        impl crate::Readable for IER_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ier::W`](W) writer structure"]
        impl crate::Writable for IER_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IER to value 0"]
        impl crate::Resettable for IER_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DLM (rw) register accessor: Divisor Latch MSB (when DLAB = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlm::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dlm`]
module"]
    pub type DLM = crate::Reg<dlm::DLM_SPEC>;
    #[doc = "Divisor Latch MSB (when DLAB = 1)"]
    pub mod dlm {
        #[doc = "Register `DLM` reader"]
        pub type R = crate::R<DLM_SPEC>;
        #[doc = "Register `DLM` writer"]
        pub type W = crate::W<DLM_SPEC>;
        #[doc = "Field `DLM` reader - Most significant byte of the Divisor Latch"]
        pub type DLM_R = crate::FieldReader;
        #[doc = "Field `DLM` writer - Most significant byte of the Divisor Latch"]
        pub type DLM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Most significant byte of the Divisor Latch"]
            #[inline(always)]
            pub fn dlm(&self) -> DLM_R {
                DLM_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Most significant byte of the Divisor Latch"]
            #[inline(always)]
            #[must_use]
            pub fn dlm(&mut self) -> DLM_W<DLM_SPEC> {
                DLM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Divisor Latch MSB (when DLAB = 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dlm::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dlm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DLM_SPEC;
        impl crate::RegisterSpec for DLM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dlm::R`](R) reader structure"]
        impl crate::Readable for DLM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dlm::W`](W) writer structure"]
        impl crate::Writable for DLM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DLM to value 0"]
        impl crate::Resettable for DLM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IIR (rw) register accessor: Interrupt Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iir`]
module"]
    pub type IIR = crate::Reg<iir::IIR_SPEC>;
    #[doc = "Interrupt Identification Register"]
    pub mod iir {
        #[doc = "Register `IIR` reader"]
        pub type R = crate::R<IIR_SPEC>;
        #[doc = "Register `IIR` writer"]
        pub type W = crate::W<IIR_SPEC>;
        #[doc = "Field `INTRID` reader - Interrupt ID, see IIR2 for detail decoding"]
        pub type INTRID_R = crate::FieldReader;
        #[doc = "Field `FIFOED` reader - FIFOs enabled These two bits are 1 when bit 0 of the FIFO Control Register (FIFOE) is set to 1."]
        pub type FIFOED_R = crate::FieldReader;
        #[doc = "Field `RXIDLE_FLAG` writer - UART IDLE Flag 0 - UART is busy 1 - UART is idle NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR"]
        pub type RXIDLE_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3 - Interrupt ID, see IIR2 for detail decoding"]
            #[inline(always)]
            pub fn intrid(&self) -> INTRID_R {
                INTRID_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 6:7 - FIFOs enabled These two bits are 1 when bit 0 of the FIFO Control Register (FIFOE) is set to 1."]
            #[inline(always)]
            pub fn fifoed(&self) -> FIFOED_R {
                FIFOED_R::new(((self.bits >> 6) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 31 - UART IDLE Flag 0 - UART is busy 1 - UART is idle NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR"]
            #[inline(always)]
            #[must_use]
            pub fn rxidle_flag(&mut self) -> RXIDLE_FLAG_W<IIR_SPEC> {
                RXIDLE_FLAG_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Identification Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iir::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IIR_SPEC;
        impl crate::RegisterSpec for IIR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`iir::R`](R) reader structure"]
        impl crate::Readable for IIR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`iir::W`](W) writer structure"]
        impl crate::Writable for IIR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IIR to value 0x01"]
        impl crate::Resettable for IIR_SPEC {
            const RESET_VALUE: u32 = 0x01;
        }
    }
    #[doc = "FCR (rw) register accessor: FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcr`]
module"]
    pub type FCR = crate::Reg<fcr::FCR_SPEC>;
    #[doc = "FIFO Control Register"]
    pub mod fcr {
        #[doc = "Register `FCR` reader"]
        pub type R = crate::R<FCR_SPEC>;
        #[doc = "Register `FCR` writer"]
        pub type W = crate::W<FCR_SPEC>;
        #[doc = "Field `FIFOE` writer - FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles."]
        pub type FIFOE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RFIFORST` writer - Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared."]
        pub type RFIFORST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFIFORST` writer - Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared."]
        pub type TFIFORST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMAE` writer - DMA enable 0: Disable 1: Enable"]
        pub type DMAE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFIFOT` writer - Transmitter FIFO trigger level"]
        pub type TFIFOT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `RFIFOT` writer - Receiver FIFO trigger level"]
        pub type RFIFOT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl W {
            #[doc = "Bit 0 - FIFO enable Write 1 to enable both the transmitter and receiver FIFOs. The FIFOs are reset when the value of this bit toggles."]
            #[inline(always)]
            #[must_use]
            pub fn fifoe(&mut self) -> FIFOE_W<FCR_SPEC> {
                FIFOE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Receiver FIFO reset Write 1 to clear all bytes in the RXFIFO and resets its counter. The Receiver Shift Register is not cleared. This bit will automatically be cleared."]
            #[inline(always)]
            #[must_use]
            pub fn rfiforst(&mut self) -> RFIFORST_W<FCR_SPEC> {
                RFIFORST_W::new(self, 1)
            }
            #[doc = "Bit 2 - Transmitter FIFO reset Write 1 to clear all bytes in the TXFIFO and resets its counter. The Transmitter Shift Register is not cleared. This bit will automatically be cleared."]
            #[inline(always)]
            #[must_use]
            pub fn tfiforst(&mut self) -> TFIFORST_W<FCR_SPEC> {
                TFIFORST_W::new(self, 2)
            }
            #[doc = "Bit 3 - DMA enable 0: Disable 1: Enable"]
            #[inline(always)]
            #[must_use]
            pub fn dmae(&mut self) -> DMAE_W<FCR_SPEC> {
                DMAE_W::new(self, 3)
            }
            #[doc = "Bits 4:5 - Transmitter FIFO trigger level"]
            #[inline(always)]
            #[must_use]
            pub fn tfifot(&mut self) -> TFIFOT_W<FCR_SPEC> {
                TFIFOT_W::new(self, 4)
            }
            #[doc = "Bits 6:7 - Receiver FIFO trigger level"]
            #[inline(always)]
            #[must_use]
            pub fn rfifot(&mut self) -> RFIFOT_W<FCR_SPEC> {
                RFIFOT_W::new(self, 6)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FCR_SPEC;
        impl crate::RegisterSpec for FCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`fcr::R`](R) reader structure"]
        impl crate::Readable for FCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`fcr::W`](W) writer structure"]
        impl crate::Writable for FCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FCR to value 0"]
        impl crate::Resettable for FCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "LCR (rw) register accessor: Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcr`]
module"]
    pub type LCR = crate::Reg<lcr::LCR_SPEC>;
    #[doc = "Line Control Register"]
    pub mod lcr {
        #[doc = "Register `LCR` reader"]
        pub type R = crate::R<LCR_SPEC>;
        #[doc = "Register `LCR` writer"]
        pub type W = crate::W<LCR_SPEC>;
        #[doc = "Field `WLS` reader - Word length setting 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits"]
        pub type WLS_R = crate::FieldReader;
        #[doc = "Field `WLS` writer - Word length setting 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits"]
        pub type WLS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `STB` reader - Number of STOP bits 0: 1 bits 1: The number of STOP bit is based on the WLS setting When WLS = 0, STOP bit is 1.5 bits When WLS = 1, 2, 3, STOP bit is 2 bits"]
        pub type STB_R = crate::BitReader;
        #[doc = "Field `STB` writer - Number of STOP bits 0: 1 bits 1: The number of STOP bit is based on the WLS setting When WLS = 0, STOP bit is 1.5 bits When WLS = 1, 2, 3, STOP bit is 2 bits"]
        pub type STB_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PEN` reader - Parity enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data."]
        pub type PEN_R = crate::BitReader;
        #[doc = "Field `PEN` writer - Parity enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data."]
        pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPS` reader - Even parity select 1: Even parity (an even number of logic-1 is in the data and parity bits) 0: Old parity."]
        pub type EPS_R = crate::BitReader;
        #[doc = "Field `EPS` writer - Even parity select 1: Even parity (an even number of logic-1 is in the data and parity bits) 0: Old parity."]
        pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SPS` reader - Stick parity 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 0: Disable the sticky bit parity."]
        pub type SPS_R = crate::BitReader;
        #[doc = "Field `SPS` writer - Stick parity 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 0: Disable the sticky bit parity."]
        pub type SPS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BC` reader - Break control"]
        pub type BC_R = crate::BitReader;
        #[doc = "Field `BC` writer - Break control"]
        pub type BC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DLAB` reader - Divisor latch access bit"]
        pub type DLAB_R = crate::BitReader;
        #[doc = "Field `DLAB` writer - Divisor latch access bit"]
        pub type DLAB_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1 - Word length setting 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits"]
            #[inline(always)]
            pub fn wls(&self) -> WLS_R {
                WLS_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 2 - Number of STOP bits 0: 1 bits 1: The number of STOP bit is based on the WLS setting When WLS = 0, STOP bit is 1.5 bits When WLS = 1, 2, 3, STOP bit is 2 bits"]
            #[inline(always)]
            pub fn stb(&self) -> STB_R {
                STB_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Parity enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data."]
            #[inline(always)]
            pub fn pen(&self) -> PEN_R {
                PEN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Even parity select 1: Even parity (an even number of logic-1 is in the data and parity bits) 0: Old parity."]
            #[inline(always)]
            pub fn eps(&self) -> EPS_R {
                EPS_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Stick parity 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 0: Disable the sticky bit parity."]
            #[inline(always)]
            pub fn sps(&self) -> SPS_R {
                SPS_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Break control"]
            #[inline(always)]
            pub fn bc(&self) -> BC_R {
                BC_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Divisor latch access bit"]
            #[inline(always)]
            pub fn dlab(&self) -> DLAB_R {
                DLAB_R::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - Word length setting 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits"]
            #[inline(always)]
            #[must_use]
            pub fn wls(&mut self) -> WLS_W<LCR_SPEC> {
                WLS_W::new(self, 0)
            }
            #[doc = "Bit 2 - Number of STOP bits 0: 1 bits 1: The number of STOP bit is based on the WLS setting When WLS = 0, STOP bit is 1.5 bits When WLS = 1, 2, 3, STOP bit is 2 bits"]
            #[inline(always)]
            #[must_use]
            pub fn stb(&mut self) -> STB_W<LCR_SPEC> {
                STB_W::new(self, 2)
            }
            #[doc = "Bit 3 - Parity enable When this bit is set, a parity bit is generated in transmitted data before the first STOP bit and the parity bit would be checked for the received data."]
            #[inline(always)]
            #[must_use]
            pub fn pen(&mut self) -> PEN_W<LCR_SPEC> {
                PEN_W::new(self, 3)
            }
            #[doc = "Bit 4 - Even parity select 1: Even parity (an even number of logic-1 is in the data and parity bits) 0: Old parity."]
            #[inline(always)]
            #[must_use]
            pub fn eps(&mut self) -> EPS_W<LCR_SPEC> {
                EPS_W::new(self, 4)
            }
            #[doc = "Bit 5 - Stick parity 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 0: Disable the sticky bit parity."]
            #[inline(always)]
            #[must_use]
            pub fn sps(&mut self) -> SPS_W<LCR_SPEC> {
                SPS_W::new(self, 5)
            }
            #[doc = "Bit 6 - Break control"]
            #[inline(always)]
            #[must_use]
            pub fn bc(&mut self) -> BC_W<LCR_SPEC> {
                BC_W::new(self, 6)
            }
            #[doc = "Bit 7 - Divisor latch access bit"]
            #[inline(always)]
            #[must_use]
            pub fn dlab(&mut self) -> DLAB_W<LCR_SPEC> {
                DLAB_W::new(self, 7)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LCR_SPEC;
        impl crate::RegisterSpec for LCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`lcr::R`](R) reader structure"]
        impl crate::Readable for LCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`lcr::W`](W) writer structure"]
        impl crate::Writable for LCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LCR to value 0"]
        impl crate::Resettable for LCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "MCR (rw) register accessor: Modem Control Register (\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
module"]
    pub type MCR = crate::Reg<mcr::MCR_SPEC>;
    #[doc = "Modem Control Register ("]
    pub mod mcr {
        #[doc = "Register `MCR` reader"]
        pub type R = crate::R<MCR_SPEC>;
        #[doc = "Register `MCR` writer"]
        pub type W = crate::W<MCR_SPEC>;
        #[doc = "Field `RTS` reader - Request to send This bit controls the modem_rtsn output. 0: The modem_rtsn output signal will be driven HIGH 1: The modem_rtsn output signal will be driven LOW"]
        pub type RTS_R = crate::BitReader;
        #[doc = "Field `RTS` writer - Request to send This bit controls the modem_rtsn output. 0: The modem_rtsn output signal will be driven HIGH 1: The modem_rtsn output signal will be driven LOW"]
        pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LOOP` reader - Enable loopback mode 0: Disable 1: Enable"]
        pub type LOOP_R = crate::BitReader;
        #[doc = "Field `LOOP` writer - Enable loopback mode 0: Disable 1: Enable"]
        pub type LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AFE` reader - Auto flow control enable 0: Disable 1: The auto-CTS and auto-RTS setting is based on the RTS bit setting: When RTS = 0, auto-CTS only When RTS = 1, auto-CTS and auto-RTS"]
        pub type AFE_R = crate::BitReader;
        #[doc = "Field `AFE` writer - Auto flow control enable 0: Disable 1: The auto-CTS and auto-RTS setting is based on the RTS bit setting: When RTS = 0, auto-CTS only When RTS = 1, auto-CTS and auto-RTS"]
        pub type AFE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 1 - Request to send This bit controls the modem_rtsn output. 0: The modem_rtsn output signal will be driven HIGH 1: The modem_rtsn output signal will be driven LOW"]
            #[inline(always)]
            pub fn rts(&self) -> RTS_R {
                RTS_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 4 - Enable loopback mode 0: Disable 1: Enable"]
            #[inline(always)]
            pub fn loop_(&self) -> LOOP_R {
                LOOP_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Auto flow control enable 0: Disable 1: The auto-CTS and auto-RTS setting is based on the RTS bit setting: When RTS = 0, auto-CTS only When RTS = 1, auto-CTS and auto-RTS"]
            #[inline(always)]
            pub fn afe(&self) -> AFE_R {
                AFE_R::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 1 - Request to send This bit controls the modem_rtsn output. 0: The modem_rtsn output signal will be driven HIGH 1: The modem_rtsn output signal will be driven LOW"]
            #[inline(always)]
            #[must_use]
            pub fn rts(&mut self) -> RTS_W<MCR_SPEC> {
                RTS_W::new(self, 1)
            }
            #[doc = "Bit 4 - Enable loopback mode 0: Disable 1: Enable"]
            #[inline(always)]
            #[must_use]
            pub fn loop_(&mut self) -> LOOP_W<MCR_SPEC> {
                LOOP_W::new(self, 4)
            }
            #[doc = "Bit 5 - Auto flow control enable 0: Disable 1: The auto-CTS and auto-RTS setting is based on the RTS bit setting: When RTS = 0, auto-CTS only When RTS = 1, auto-CTS and auto-RTS"]
            #[inline(always)]
            #[must_use]
            pub fn afe(&mut self) -> AFE_W<MCR_SPEC> {
                AFE_W::new(self, 5)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Modem Control Register (\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MCR_SPEC;
        impl crate::RegisterSpec for MCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`mcr::R`](R) reader structure"]
        impl crate::Readable for MCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"]
        impl crate::Writable for MCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets MCR to value 0"]
        impl crate::Resettable for MCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "LSR (rw) register accessor: Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lsr`]
module"]
    pub type LSR = crate::Reg<lsr::LSR_SPEC>;
    #[doc = "Line Status Register"]
    pub mod lsr {
        #[doc = "Register `LSR` reader"]
        pub type R = crate::R<LSR_SPEC>;
        #[doc = "Register `LSR` writer"]
        pub type W = crate::W<LSR_SPEC>;
        #[doc = "Field `DR` reader - Data ready. This bit is set when there are incoming received data in the Receiver Buffer Register (RBR). It is cleared when all of the received data are read."]
        pub type DR_R = crate::BitReader;
        #[doc = "Field `OE` reader - Overrun error This bit indicates that data in the Receiver Buffer Register (RBR) is overrun."]
        pub type OE_R = crate::BitReader;
        #[doc = "Field `PE` reader - Parity error This bit is set when the received parity does not match with the parity selected in the LCR\\[5:4\\]. It is cleared when this register is read. In the FIFO mode, this bit indicates the parity error for the received data at the top of the RXFIFO."]
        pub type PE_R = crate::BitReader;
        #[doc = "Field `FE` reader - Framing error This bit is set when the received STOP bit is not HIGH. It is cleared when this register is read. In the FIFO mode, this bit indicates the framing error for the received data at the top of the RXFIFO."]
        pub type FE_R = crate::BitReader;
        #[doc = "Field `LBREAK` reader - Line break This bit is set when the uart_sin input signal was held LOWfor longer than the time for a full-word transmission. A full-word transmission is the transmission of the START, data, parity, and STOP bits. It is cleared when this register is read. In the FIFO mode, this bit indicates the line break for the received data at the top of the RXFIFO."]
        pub type LBREAK_R = crate::BitReader;
        #[doc = "Field `THRE` reader - Transmitter Holding Register empty This bit is 1 when the THR (TXFIFO in the FIFO mode) is empty. Otherwise, it is zero. If the THRE interrupt is enabled, an interrupt is triggered when THRE becomes 1."]
        pub type THRE_R = crate::BitReader;
        #[doc = "Field `TEMT` reader - Transmitter empty This bit is 1 when the THR (TXFIFO in the FIFO mode) and the Transmitter Shift Register (TSR) are both empty. Otherwise, it is zero."]
        pub type TEMT_R = crate::BitReader;
        #[doc = "Field `ERRF` reader - Error in RXFIFO In the FIFO mode, this bit is set when there is at least one parity error, framing error, or line break associated with data in the RXFIFO. It is cleared when this register is read and there is no more error for the rest of data in the RXFIFO."]
        pub type ERRF_R = crate::BitReader;
        #[doc = "Field `TFIFO_NUM` reader - data bytes in txfifo not sent"]
        pub type TFIFO_NUM_R = crate::FieldReader;
        #[doc = "Field `RFIFO_NUM` reader - data bytes in rxfifo not read"]
        pub type RFIFO_NUM_R = crate::FieldReader;
        #[doc = "Field `TXIDLE` reader - txidle after timeout, clear after tx idle condition not match"]
        pub type TXIDLE_R = crate::BitReader;
        #[doc = "Field `RXIDLE` reader - rxidle after timeout, clear after rx idle condition not match"]
        pub type RXIDLE_R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Data ready. This bit is set when there are incoming received data in the Receiver Buffer Register (RBR). It is cleared when all of the received data are read."]
            #[inline(always)]
            pub fn dr(&self) -> DR_R {
                DR_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Overrun error This bit indicates that data in the Receiver Buffer Register (RBR) is overrun."]
            #[inline(always)]
            pub fn oe(&self) -> OE_R {
                OE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Parity error This bit is set when the received parity does not match with the parity selected in the LCR\\[5:4\\]. It is cleared when this register is read. In the FIFO mode, this bit indicates the parity error for the received data at the top of the RXFIFO."]
            #[inline(always)]
            pub fn pe(&self) -> PE_R {
                PE_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Framing error This bit is set when the received STOP bit is not HIGH. It is cleared when this register is read. In the FIFO mode, this bit indicates the framing error for the received data at the top of the RXFIFO."]
            #[inline(always)]
            pub fn fe(&self) -> FE_R {
                FE_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Line break This bit is set when the uart_sin input signal was held LOWfor longer than the time for a full-word transmission. A full-word transmission is the transmission of the START, data, parity, and STOP bits. It is cleared when this register is read. In the FIFO mode, this bit indicates the line break for the received data at the top of the RXFIFO."]
            #[inline(always)]
            pub fn lbreak(&self) -> LBREAK_R {
                LBREAK_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Transmitter Holding Register empty This bit is 1 when the THR (TXFIFO in the FIFO mode) is empty. Otherwise, it is zero. If the THRE interrupt is enabled, an interrupt is triggered when THRE becomes 1."]
            #[inline(always)]
            pub fn thre(&self) -> THRE_R {
                THRE_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Transmitter empty This bit is 1 when the THR (TXFIFO in the FIFO mode) and the Transmitter Shift Register (TSR) are both empty. Otherwise, it is zero."]
            #[inline(always)]
            pub fn temt(&self) -> TEMT_R {
                TEMT_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Error in RXFIFO In the FIFO mode, this bit is set when there is at least one parity error, framing error, or line break associated with data in the RXFIFO. It is cleared when this register is read and there is no more error for the rest of data in the RXFIFO."]
            #[inline(always)]
            pub fn errf(&self) -> ERRF_R {
                ERRF_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:12 - data bytes in txfifo not sent"]
            #[inline(always)]
            pub fn tfifo_num(&self) -> TFIFO_NUM_R {
                TFIFO_NUM_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:20 - data bytes in rxfifo not read"]
            #[inline(always)]
            pub fn rfifo_num(&self) -> RFIFO_NUM_R {
                RFIFO_NUM_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bit 30 - txidle after timeout, clear after tx idle condition not match"]
            #[inline(always)]
            pub fn txidle(&self) -> TXIDLE_R {
                TXIDLE_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - rxidle after timeout, clear after rx idle condition not match"]
            #[inline(always)]
            pub fn rxidle(&self) -> RXIDLE_R {
                RXIDLE_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Line Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LSR_SPEC;
        impl crate::RegisterSpec for LSR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`lsr::R`](R) reader structure"]
        impl crate::Readable for LSR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`lsr::W`](W) writer structure"]
        impl crate::Writable for LSR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LSR to value 0"]
        impl crate::Resettable for LSR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "MSR (rw) register accessor: Modem Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`]
module"]
    pub type MSR = crate::Reg<msr::MSR_SPEC>;
    #[doc = "Modem Status Register"]
    pub mod msr {
        #[doc = "Register `MSR` reader"]
        pub type R = crate::R<MSR_SPEC>;
        #[doc = "Register `MSR` writer"]
        pub type W = crate::W<MSR_SPEC>;
        #[doc = "Field `DCTS` reader - Delta clear to send This bit is set when the state of the modem_ctsn input signal has been changed since the last time this register is read."]
        pub type DCTS_R = crate::BitReader;
        #[doc = "Field `CTS` reader - Clear to send 0: The modem_ctsn input signal is HIGH. 1: The modem_ctsn input signal is LOW."]
        pub type CTS_R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Delta clear to send This bit is set when the state of the modem_ctsn input signal has been changed since the last time this register is read."]
            #[inline(always)]
            pub fn dcts(&self) -> DCTS_R {
                DCTS_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4 - Clear to send 0: The modem_ctsn input signal is HIGH. 1: The modem_ctsn input signal is LOW."]
            #[inline(always)]
            pub fn cts(&self) -> CTS_R {
                CTS_R::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Modem Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MSR_SPEC;
        impl crate::RegisterSpec for MSR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`msr::R`](R) reader structure"]
        impl crate::Readable for MSR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`msr::W`](W) writer structure"]
        impl crate::Writable for MSR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets MSR to value 0"]
        impl crate::Resettable for MSR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GPR (rw) register accessor: GPR Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpr`]
module"]
    pub type GPR = crate::Reg<gpr::GPR_SPEC>;
    #[doc = "GPR Register"]
    pub mod gpr {
        #[doc = "Register `GPR` reader"]
        pub type R = crate::R<GPR_SPEC>;
        #[doc = "Register `GPR` writer"]
        pub type W = crate::W<GPR_SPEC>;
        #[doc = "Field `DATA` reader - An one-byte storage register"]
        pub type DATA_R = crate::FieldReader;
        #[doc = "Field `DATA` writer - An one-byte storage register"]
        pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - An one-byte storage register"]
            #[inline(always)]
            pub fn data(&self) -> DATA_R {
                DATA_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - An one-byte storage register"]
            #[inline(always)]
            #[must_use]
            pub fn data(&mut self) -> DATA_W<GPR_SPEC> {
                DATA_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "GPR Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GPR_SPEC;
        impl crate::RegisterSpec for GPR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gpr::R`](R) reader structure"]
        impl crate::Readable for GPR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gpr::W`](W) writer structure"]
        impl crate::Writable for GPR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GPR to value 0"]
        impl crate::Resettable for GPR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "UART1"]
pub struct UART1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART1 {}
impl UART1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf004_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART1 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART1").finish()
    }
}
#[doc = "UART1"]
pub use self::uart0 as uart1;
#[doc = "UART2"]
pub struct UART2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART2 {}
impl UART2 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf004_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART2 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART2").finish()
    }
}
#[doc = "UART2"]
pub use self::uart0 as uart2;
#[doc = "UART3"]
pub struct UART3 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART3 {}
impl UART3 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf004_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART3 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART3").finish()
    }
}
#[doc = "UART3"]
pub use self::uart0 as uart3;
#[doc = "UART4"]
pub struct UART4 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART4 {}
impl UART4 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf005_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART4 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART4 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART4").finish()
    }
}
#[doc = "UART4"]
pub use self::uart0 as uart4;
#[doc = "UART5"]
pub struct UART5 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART5 {}
impl UART5 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf005_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART5 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART5 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART5").finish()
    }
}
#[doc = "UART5"]
pub use self::uart0 as uart5;
#[doc = "UART6"]
pub struct UART6 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART6 {}
impl UART6 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf005_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART6 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART6 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART6").finish()
    }
}
#[doc = "UART6"]
pub use self::uart0 as uart6;
#[doc = "UART7"]
pub struct UART7 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for UART7 {}
impl UART7 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf005_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for UART7 {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for UART7 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("UART7").finish()
    }
}
#[doc = "UART7"]
pub use self::uart0 as uart7;
#[doc = "PUART"]
pub struct PUART {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PUART {}
impl PUART {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const uart0::RegisterBlock = 0xf412_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const uart0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PUART {
    type Target = uart0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PUART {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PUART").finish()
    }
}
#[doc = "PUART"]
pub use self::uart0 as puart;
#[doc = "I2C0"]
pub struct I2C0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C0 {}
impl I2C0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const i2c0::RegisterBlock = 0xf006_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const i2c0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for I2C0 {
    type Target = i2c0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for I2C0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C0").finish()
    }
}
#[doc = "I2C0"]
pub mod i2c0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x10],
        cfg: CFG,
        int_en: INT_EN,
        status: STATUS,
        addr: ADDR,
        data: DATA,
        ctrl: CTRL,
        cmd: CMD,
        setup: SETUP,
        tpm: TPM,
    }
    impl RegisterBlock {
        #[doc = "0x10 - Configuration Register"]
        #[inline(always)]
        pub const fn cfg(&self) -> &CFG {
            &self.cfg
        }
        #[doc = "0x14 - Interrupt Enable Register"]
        #[inline(always)]
        pub const fn int_en(&self) -> &INT_EN {
            &self.int_en
        }
        #[doc = "0x18 - Status Register"]
        #[inline(always)]
        pub const fn status(&self) -> &STATUS {
            &self.status
        }
        #[doc = "0x1c - Address Register"]
        #[inline(always)]
        pub const fn addr(&self) -> &ADDR {
            &self.addr
        }
        #[doc = "0x20 - Data Register"]
        #[inline(always)]
        pub const fn data(&self) -> &DATA {
            &self.data
        }
        #[doc = "0x24 - Control Register"]
        #[inline(always)]
        pub const fn ctrl(&self) -> &CTRL {
            &self.ctrl
        }
        #[doc = "0x28 - Command Register"]
        #[inline(always)]
        pub const fn cmd(&self) -> &CMD {
            &self.cmd
        }
        #[doc = "0x2c - Setup Register"]
        #[inline(always)]
        pub const fn setup(&self) -> &SETUP {
            &self.setup
        }
        #[doc = "0x30 - I2C Timing Paramater Multiplier"]
        #[inline(always)]
        pub const fn tpm(&self) -> &TPM {
            &self.tpm
        }
    }
    #[doc = "Cfg (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
    pub type CFG = crate::Reg<cfg::CFG_SPEC>;
    #[doc = "Configuration Register"]
    pub mod cfg {
        #[doc = "Register `Cfg` reader"]
        pub type R = crate::R<CFG_SPEC>;
        #[doc = "Register `Cfg` writer"]
        pub type W = crate::W<CFG_SPEC>;
        #[doc = "Field `FIFOSIZE` reader - FIFO Size: 0: 2 bytes 1: 4 bytes 2: 8 bytes 3: 16 bytes"]
        pub type FIFOSIZE_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:1 - FIFO Size: 0: 2 bytes 1: 4 bytes 2: 8 bytes 3: 16 bytes"]
            #[inline(always)]
            pub fn fifosize(&self) -> FIFOSIZE_R {
                FIFOSIZE_R::new((self.bits & 3) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CFG_SPEC;
        impl crate::RegisterSpec for CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
        impl crate::Readable for CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
        impl crate::Writable for CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Cfg to value 0x01"]
        impl crate::Resettable for CFG_SPEC {
            const RESET_VALUE: u32 = 0x01;
        }
    }
    #[doc = "IntEn (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_en`]
module"]
    pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
    #[doc = "Interrupt Enable Register"]
    pub mod int_en {
        #[doc = "Register `IntEn` reader"]
        pub type R = crate::R<INT_EN_SPEC>;
        #[doc = "Register `IntEn` writer"]
        pub type W = crate::W<INT_EN_SPEC>;
        #[doc = "Field `FIFOEMPTY` reader - Set to enabled the FIFO Empty Interrupt Interrupts when the FIFO is empty."]
        pub type FIFOEMPTY_R = crate::BitReader;
        #[doc = "Field `FIFOEMPTY` writer - Set to enabled the FIFO Empty Interrupt Interrupts when the FIFO is empty."]
        pub type FIFOEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FIFOFULL` reader - Set to enable the FIFO Full Interrupt. Interrupts when the FIFO is full."]
        pub type FIFOFULL_R = crate::BitReader;
        #[doc = "Field `FIFOFULL` writer - Set to enable the FIFO Full Interrupt. Interrupts when the FIFO is full."]
        pub type FIFOFULL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FIFOHALF` reader - Set to enable the FIFO Half Interrupt. Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. Transmitter: Interrupts when the FIFO is half-empty, i.e. there is &lt;= 1/2 entries in the FIFO. This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered."]
        pub type FIFOHALF_R = crate::BitReader;
        #[doc = "Field `FIFOHALF` writer - Set to enable the FIFO Half Interrupt. Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. Transmitter: Interrupts when the FIFO is half-empty, i.e. there is &lt;= 1/2 entries in the FIFO. This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered."]
        pub type FIFOHALF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ADDRHIT` reader - Set to enable the Address Hit Interrupt. Master: interrupts when the addressed slave returned an ACK. Slave: interrupts when the controller is addressed."]
        pub type ADDRHIT_R = crate::BitReader;
        #[doc = "Field `ADDRHIT` writer - Set to enable the Address Hit Interrupt. Master: interrupts when the addressed slave returned an ACK. Slave: interrupts when the controller is addressed."]
        pub type ADDRHIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ARBLOSE` reader - Set to enable the Arbitration Lose Interrupt. Master: interrupts when the controller loses the bus arbitration Slave: not available in this mode."]
        pub type ARBLOSE_R = crate::BitReader;
        #[doc = "Field `ARBLOSE` writer - Set to enable the Arbitration Lose Interrupt. Master: interrupts when the controller loses the bus arbitration Slave: not available in this mode."]
        pub type ARBLOSE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STOP` reader - Set to enable the STOP Condition Interrupt Interrupts when a STOP condition is detected."]
        pub type STOP_R = crate::BitReader;
        #[doc = "Field `STOP` writer - Set to enable the STOP Condition Interrupt Interrupts when a STOP condition is detected."]
        pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `START` reader - Set to enable the START Condition Interrupt. Interrupts when a START condition/repeated START condition is detected."]
        pub type START_R = crate::BitReader;
        #[doc = "Field `START` writer - Set to enable the START Condition Interrupt. Interrupts when a START condition/repeated START condition is detected."]
        pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BYTETRANS` reader - Set to enable the Byte Transmit Interrupt. Interrupts when a byte of data is transmitted."]
        pub type BYTETRANS_R = crate::BitReader;
        #[doc = "Field `BYTETRANS` writer - Set to enable the Byte Transmit Interrupt. Interrupts when a byte of data is transmitted."]
        pub type BYTETRANS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BYTERECV` reader - Set to enable the Byte Receive Interrupt. Interrupts when a byte of data is received Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually."]
        pub type BYTERECV_R = crate::BitReader;
        #[doc = "Field `BYTERECV` writer - Set to enable the Byte Receive Interrupt. Interrupts when a byte of data is received Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually."]
        pub type BYTERECV_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CMPL` reader - Set to enable the Completion Interrupt. Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. Slave: interrupts when a transaction addressing the controller is completed."]
        pub type CMPL_R = crate::BitReader;
        #[doc = "Field `CMPL` writer - Set to enable the Completion Interrupt. Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. Slave: interrupts when a transaction addressing the controller is completed."]
        pub type CMPL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Set to enabled the FIFO Empty Interrupt Interrupts when the FIFO is empty."]
            #[inline(always)]
            pub fn fifoempty(&self) -> FIFOEMPTY_R {
                FIFOEMPTY_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Set to enable the FIFO Full Interrupt. Interrupts when the FIFO is full."]
            #[inline(always)]
            pub fn fifofull(&self) -> FIFOFULL_R {
                FIFOFULL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Set to enable the FIFO Half Interrupt. Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. Transmitter: Interrupts when the FIFO is half-empty, i.e. there is &lt;= 1/2 entries in the FIFO. This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered."]
            #[inline(always)]
            pub fn fifohalf(&self) -> FIFOHALF_R {
                FIFOHALF_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Set to enable the Address Hit Interrupt. Master: interrupts when the addressed slave returned an ACK. Slave: interrupts when the controller is addressed."]
            #[inline(always)]
            pub fn addrhit(&self) -> ADDRHIT_R {
                ADDRHIT_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Set to enable the Arbitration Lose Interrupt. Master: interrupts when the controller loses the bus arbitration Slave: not available in this mode."]
            #[inline(always)]
            pub fn arblose(&self) -> ARBLOSE_R {
                ARBLOSE_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Set to enable the STOP Condition Interrupt Interrupts when a STOP condition is detected."]
            #[inline(always)]
            pub fn stop(&self) -> STOP_R {
                STOP_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Set to enable the START Condition Interrupt. Interrupts when a START condition/repeated START condition is detected."]
            #[inline(always)]
            pub fn start(&self) -> START_R {
                START_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Set to enable the Byte Transmit Interrupt. Interrupts when a byte of data is transmitted."]
            #[inline(always)]
            pub fn bytetrans(&self) -> BYTETRANS_R {
                BYTETRANS_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - Set to enable the Byte Receive Interrupt. Interrupts when a byte of data is received Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually."]
            #[inline(always)]
            pub fn byterecv(&self) -> BYTERECV_R {
                BYTERECV_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Set to enable the Completion Interrupt. Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. Slave: interrupts when a transaction addressing the controller is completed."]
            #[inline(always)]
            pub fn cmpl(&self) -> CMPL_R {
                CMPL_R::new(((self.bits >> 9) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Set to enabled the FIFO Empty Interrupt Interrupts when the FIFO is empty."]
            #[inline(always)]
            #[must_use]
            pub fn fifoempty(&mut self) -> FIFOEMPTY_W<INT_EN_SPEC> {
                FIFOEMPTY_W::new(self, 0)
            }
            #[doc = "Bit 1 - Set to enable the FIFO Full Interrupt. Interrupts when the FIFO is full."]
            #[inline(always)]
            #[must_use]
            pub fn fifofull(&mut self) -> FIFOFULL_W<INT_EN_SPEC> {
                FIFOFULL_W::new(self, 1)
            }
            #[doc = "Bit 2 - Set to enable the FIFO Half Interrupt. Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. Transmitter: Interrupts when the FIFO is half-empty, i.e. there is &lt;= 1/2 entries in the FIFO. This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered."]
            #[inline(always)]
            #[must_use]
            pub fn fifohalf(&mut self) -> FIFOHALF_W<INT_EN_SPEC> {
                FIFOHALF_W::new(self, 2)
            }
            #[doc = "Bit 3 - Set to enable the Address Hit Interrupt. Master: interrupts when the addressed slave returned an ACK. Slave: interrupts when the controller is addressed."]
            #[inline(always)]
            #[must_use]
            pub fn addrhit(&mut self) -> ADDRHIT_W<INT_EN_SPEC> {
                ADDRHIT_W::new(self, 3)
            }
            #[doc = "Bit 4 - Set to enable the Arbitration Lose Interrupt. Master: interrupts when the controller loses the bus arbitration Slave: not available in this mode."]
            #[inline(always)]
            #[must_use]
            pub fn arblose(&mut self) -> ARBLOSE_W<INT_EN_SPEC> {
                ARBLOSE_W::new(self, 4)
            }
            #[doc = "Bit 5 - Set to enable the STOP Condition Interrupt Interrupts when a STOP condition is detected."]
            #[inline(always)]
            #[must_use]
            pub fn stop(&mut self) -> STOP_W<INT_EN_SPEC> {
                STOP_W::new(self, 5)
            }
            #[doc = "Bit 6 - Set to enable the START Condition Interrupt. Interrupts when a START condition/repeated START condition is detected."]
            #[inline(always)]
            #[must_use]
            pub fn start(&mut self) -> START_W<INT_EN_SPEC> {
                START_W::new(self, 6)
            }
            #[doc = "Bit 7 - Set to enable the Byte Transmit Interrupt. Interrupts when a byte of data is transmitted."]
            #[inline(always)]
            #[must_use]
            pub fn bytetrans(&mut self) -> BYTETRANS_W<INT_EN_SPEC> {
                BYTETRANS_W::new(self, 7)
            }
            #[doc = "Bit 8 - Set to enable the Byte Receive Interrupt. Interrupts when a byte of data is received Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually."]
            #[inline(always)]
            #[must_use]
            pub fn byterecv(&mut self) -> BYTERECV_W<INT_EN_SPEC> {
                BYTERECV_W::new(self, 8)
            }
            #[doc = "Bit 9 - Set to enable the Completion Interrupt. Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. Slave: interrupts when a transaction addressing the controller is completed."]
            #[inline(always)]
            #[must_use]
            pub fn cmpl(&mut self) -> CMPL_W<INT_EN_SPEC> {
                CMPL_W::new(self, 9)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_EN_SPEC;
        impl crate::RegisterSpec for INT_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_en::R`](R) reader structure"]
        impl crate::Readable for INT_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_en::W`](W) writer structure"]
        impl crate::Writable for INT_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IntEn to value 0"]
        impl crate::Resettable for INT_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Status (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
    pub type STATUS = crate::Reg<status::STATUS_SPEC>;
    #[doc = "Status Register"]
    pub mod status {
        #[doc = "Register `Status` reader"]
        pub type R = crate::R<STATUS_SPEC>;
        #[doc = "Register `Status` writer"]
        pub type W = crate::W<STATUS_SPEC>;
        #[doc = "Field `FIFOEMPTY` reader - Indicates that the FIFO is empty."]
        pub type FIFOEMPTY_R = crate::BitReader;
        #[doc = "Field `FIFOFULL` reader - Indicates that the FIFO is full."]
        pub type FIFOFULL_R = crate::BitReader;
        #[doc = "Field `FIFOHALF` reader - Transmitter: Indicates that the FIFO is half-empty."]
        pub type FIFOHALF_R = crate::BitReader;
        #[doc = "Field `ADDRHIT` writer - Master: indicates that a slave has responded to the transaction. Slave: indicates that a transaction is targeting the controller (including the General Call)."]
        pub type ADDRHIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ARBLOSE` writer - Indicates that the controller has lost the bus arbitration."]
        pub type ARBLOSE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STOP` writer - Indicates that a STOP Condition has been transmitted/received."]
        pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `START` writer - Indicates that a START Condition or a repeated START condition has been transmitted/received."]
        pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BYTETRANS` writer - Indicates that a byte of data has been transmitted."]
        pub type BYTETRANS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BYTERECV` writer - Indicates that a byte of data has been received."]
        pub type BYTERECV_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CMPL` writer - Transaction Completion Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked."]
        pub type CMPL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACK` reader - Indicates the type of the last received/transmitted acknowledgement bit: 1: ACK 0: NACK"]
        pub type ACK_R = crate::BitReader;
        #[doc = "Field `BUSBUSY` reader - Indicates that the bus is busy The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus 1: Busy 0: Not busy"]
        pub type BUSBUSY_R = crate::BitReader;
        #[doc = "Field `GENCALL` reader - Indicates that the address of the current transaction is a general call address: 1: General call 0: Not general call"]
        pub type GENCALL_R = crate::BitReader;
        #[doc = "Field `LINESCL` reader - Indicates the current status of the SCL line on the bus 1: high 0: low"]
        pub type LINESCL_R = crate::BitReader;
        #[doc = "Field `LINESDA` reader - Indicates the current status of the SDA line on the bus 1: high 0: low"]
        pub type LINESDA_R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - Indicates that the FIFO is empty."]
            #[inline(always)]
            pub fn fifoempty(&self) -> FIFOEMPTY_R {
                FIFOEMPTY_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Indicates that the FIFO is full."]
            #[inline(always)]
            pub fn fifofull(&self) -> FIFOFULL_R {
                FIFOFULL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Transmitter: Indicates that the FIFO is half-empty."]
            #[inline(always)]
            pub fn fifohalf(&self) -> FIFOHALF_R {
                FIFOHALF_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 10 - Indicates the type of the last received/transmitted acknowledgement bit: 1: ACK 0: NACK"]
            #[inline(always)]
            pub fn ack(&self) -> ACK_R {
                ACK_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - Indicates that the bus is busy The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus 1: Busy 0: Not busy"]
            #[inline(always)]
            pub fn busbusy(&self) -> BUSBUSY_R {
                BUSBUSY_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Indicates that the address of the current transaction is a general call address: 1: General call 0: Not general call"]
            #[inline(always)]
            pub fn gencall(&self) -> GENCALL_R {
                GENCALL_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Indicates the current status of the SCL line on the bus 1: high 0: low"]
            #[inline(always)]
            pub fn linescl(&self) -> LINESCL_R {
                LINESCL_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - Indicates the current status of the SDA line on the bus 1: high 0: low"]
            #[inline(always)]
            pub fn linesda(&self) -> LINESDA_R {
                LINESDA_R::new(((self.bits >> 14) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 3 - Master: indicates that a slave has responded to the transaction. Slave: indicates that a transaction is targeting the controller (including the General Call)."]
            #[inline(always)]
            #[must_use]
            pub fn addrhit(&mut self) -> ADDRHIT_W<STATUS_SPEC> {
                ADDRHIT_W::new(self, 3)
            }
            #[doc = "Bit 4 - Indicates that the controller has lost the bus arbitration."]
            #[inline(always)]
            #[must_use]
            pub fn arblose(&mut self) -> ARBLOSE_W<STATUS_SPEC> {
                ARBLOSE_W::new(self, 4)
            }
            #[doc = "Bit 5 - Indicates that a STOP Condition has been transmitted/received."]
            #[inline(always)]
            #[must_use]
            pub fn stop(&mut self) -> STOP_W<STATUS_SPEC> {
                STOP_W::new(self, 5)
            }
            #[doc = "Bit 6 - Indicates that a START Condition or a repeated START condition has been transmitted/received."]
            #[inline(always)]
            #[must_use]
            pub fn start(&mut self) -> START_W<STATUS_SPEC> {
                START_W::new(self, 6)
            }
            #[doc = "Bit 7 - Indicates that a byte of data has been transmitted."]
            #[inline(always)]
            #[must_use]
            pub fn bytetrans(&mut self) -> BYTETRANS_W<STATUS_SPEC> {
                BYTETRANS_W::new(self, 7)
            }
            #[doc = "Bit 8 - Indicates that a byte of data has been received."]
            #[inline(always)]
            #[must_use]
            pub fn byterecv(&mut self) -> BYTERECV_W<STATUS_SPEC> {
                BYTERECV_W::new(self, 8)
            }
            #[doc = "Bit 9 - Transaction Completion Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked."]
            #[inline(always)]
            #[must_use]
            pub fn cmpl(&mut self) -> CMPL_W<STATUS_SPEC> {
                CMPL_W::new(self, 9)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STATUS_SPEC;
        impl crate::RegisterSpec for STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`status::R`](R) reader structure"]
        impl crate::Readable for STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
        impl crate::Writable for STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Status to value 0x01"]
        impl crate::Resettable for STATUS_SPEC {
            const RESET_VALUE: u32 = 0x01;
        }
    }
    #[doc = "Addr (rw) register accessor: Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
module"]
    pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
    #[doc = "Address Register"]
    pub mod addr {
        #[doc = "Register `Addr` reader"]
        pub type R = crate::R<ADDR_SPEC>;
        #[doc = "Register `Addr` writer"]
        pub type W = crate::W<ADDR_SPEC>;
        #[doc = "Field `ADDR` reader - The slave address. For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid"]
        pub type ADDR_R = crate::FieldReader<u16>;
        #[doc = "Field `ADDR` writer - The slave address. For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid"]
        pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
        impl R {
            #[doc = "Bits 0:9 - The slave address. For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid"]
            #[inline(always)]
            pub fn addr(&self) -> ADDR_R {
                ADDR_R::new((self.bits & 0x03ff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:9 - The slave address. For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid"]
            #[inline(always)]
            #[must_use]
            pub fn addr(&mut self) -> ADDR_W<ADDR_SPEC> {
                ADDR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADDR_SPEC;
        impl crate::RegisterSpec for ADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`addr::R`](R) reader structure"]
        impl crate::Readable for ADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"]
        impl crate::Writable for ADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Addr to value 0"]
        impl crate::Resettable for ADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Data (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
    pub type DATA = crate::Reg<data::DATA_SPEC>;
    #[doc = "Data Register"]
    pub mod data {
        #[doc = "Register `Data` reader"]
        pub type R = crate::R<DATA_SPEC>;
        #[doc = "Register `Data` writer"]
        pub type W = crate::W<DATA_SPEC>;
        #[doc = "Field `DATA` reader - Write this register to put one byte of data to the FIFO. Read this register to get one byte of data from the FIFO."]
        pub type DATA_R = crate::FieldReader;
        #[doc = "Field `DATA` writer - Write this register to put one byte of data to the FIFO. Read this register to get one byte of data from the FIFO."]
        pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Write this register to put one byte of data to the FIFO. Read this register to get one byte of data from the FIFO."]
            #[inline(always)]
            pub fn data(&self) -> DATA_R {
                DATA_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Write this register to put one byte of data to the FIFO. Read this register to get one byte of data from the FIFO."]
            #[inline(always)]
            #[must_use]
            pub fn data(&mut self) -> DATA_W<DATA_SPEC> {
                DATA_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DATA_SPEC;
        impl crate::RegisterSpec for DATA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`data::R`](R) reader structure"]
        impl crate::Readable for DATA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
        impl crate::Writable for DATA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Data to value 0"]
        impl crate::Resettable for DATA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Ctrl (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
    pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
    #[doc = "Control Register"]
    pub mod ctrl {
        #[doc = "Register `Ctrl` reader"]
        pub type R = crate::R<CTRL_SPEC>;
        #[doc = "Register `Ctrl` writer"]
        pub type W = crate::W<CTRL_SPEC>;
        #[doc = "Field `DATACNT` reader - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
        pub type DATACNT_R = crate::FieldReader;
        #[doc = "Field `DATACNT` writer - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
        pub type DATACNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `DIR` reader - Transaction direction Master: Set this bit to determine the direction for the next transaction. 0: Transmitter 1: Receiver Slave: The direction of the last received transaction. 0: Receiver 1: Transmitter"]
        pub type DIR_R = crate::BitReader;
        #[doc = "Field `DIR` writer - Transaction direction Master: Set this bit to determine the direction for the next transaction. 0: Transmitter 1: Receiver Slave: The direction of the last received transaction. 0: Receiver 1: Transmitter"]
        pub type DIR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHASE_STOP` reader - Enable this bit to send a STOP condition at the end of a transaction. Master mode only."]
        pub type PHASE_STOP_R = crate::BitReader;
        #[doc = "Field `PHASE_STOP` writer - Enable this bit to send a STOP condition at the end of a transaction. Master mode only."]
        pub type PHASE_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHASE_DATA` reader - Enable this bit to send the data after Address phase. Master mode only."]
        pub type PHASE_DATA_R = crate::BitReader;
        #[doc = "Field `PHASE_DATA` writer - Enable this bit to send the data after Address phase. Master mode only."]
        pub type PHASE_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHASE_ADDR` reader - Enable this bit to send the address after START condition. Master mode only."]
        pub type PHASE_ADDR_R = crate::BitReader;
        #[doc = "Field `PHASE_ADDR` writer - Enable this bit to send the address after START condition. Master mode only."]
        pub type PHASE_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHASE_START` reader - Enable this bit to send a START condition at the beginning of transaction. Master mode only."]
        pub type PHASE_START_R = crate::BitReader;
        #[doc = "Field `PHASE_START` writer - Enable this bit to send a START condition at the beginning of transaction. Master mode only."]
        pub type PHASE_START_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESET_ON` reader - set to send reset signals(just toggle clock bus defined by reset_len). this register is clered when reset is end, can't be cleared by software"]
        pub type RESET_ON_R = crate::BitReader;
        #[doc = "Field `RESET_ON` writer - set to send reset signals(just toggle clock bus defined by reset_len). this register is clered when reset is end, can't be cleared by software"]
        pub type RESET_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESET_HOLD_SCKIN` reader - set to hold input clock to high when reset is active"]
        pub type RESET_HOLD_SCKIN_R = crate::BitReader;
        #[doc = "Field `RESET_HOLD_SCKIN` writer - set to hold input clock to high when reset is active"]
        pub type RESET_HOLD_SCKIN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESET_LEN` reader - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle."]
        pub type RESET_LEN_R = crate::FieldReader;
        #[doc = "Field `RESET_LEN` writer - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle."]
        pub type RESET_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DATACNT_HIGH` reader - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
        pub type DATACNT_HIGH_R = crate::FieldReader;
        #[doc = "Field `DATACNT_HIGH` writer - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
        pub type DATACNT_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
            #[inline(always)]
            pub fn datacnt(&self) -> DATACNT_R {
                DATACNT_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bit 8 - Transaction direction Master: Set this bit to determine the direction for the next transaction. 0: Transmitter 1: Receiver Slave: The direction of the last received transaction. 0: Receiver 1: Transmitter"]
            #[inline(always)]
            pub fn dir(&self) -> DIR_R {
                DIR_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Enable this bit to send a STOP condition at the end of a transaction. Master mode only."]
            #[inline(always)]
            pub fn phase_stop(&self) -> PHASE_STOP_R {
                PHASE_STOP_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - Enable this bit to send the data after Address phase. Master mode only."]
            #[inline(always)]
            pub fn phase_data(&self) -> PHASE_DATA_R {
                PHASE_DATA_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - Enable this bit to send the address after START condition. Master mode only."]
            #[inline(always)]
            pub fn phase_addr(&self) -> PHASE_ADDR_R {
                PHASE_ADDR_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Enable this bit to send a START condition at the beginning of transaction. Master mode only."]
            #[inline(always)]
            pub fn phase_start(&self) -> PHASE_START_R {
                PHASE_START_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - set to send reset signals(just toggle clock bus defined by reset_len). this register is clered when reset is end, can't be cleared by software"]
            #[inline(always)]
            pub fn reset_on(&self) -> RESET_ON_R {
                RESET_ON_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - set to hold input clock to high when reset is active"]
            #[inline(always)]
            pub fn reset_hold_sckin(&self) -> RESET_HOLD_SCKIN_R {
                RESET_HOLD_SCKIN_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bits 20:23 - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle."]
            #[inline(always)]
            pub fn reset_len(&self) -> RESET_LEN_R {
                RESET_LEN_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            #[doc = "Bits 24:31 - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
            #[inline(always)]
            pub fn datacnt_high(&self) -> DATACNT_HIGH_R {
                DATACNT_HIGH_R::new(((self.bits >> 24) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
            #[inline(always)]
            #[must_use]
            pub fn datacnt(&mut self) -> DATACNT_W<CTRL_SPEC> {
                DATACNT_W::new(self, 0)
            }
            #[doc = "Bit 8 - Transaction direction Master: Set this bit to determine the direction for the next transaction. 0: Transmitter 1: Receiver Slave: The direction of the last received transaction. 0: Receiver 1: Transmitter"]
            #[inline(always)]
            #[must_use]
            pub fn dir(&mut self) -> DIR_W<CTRL_SPEC> {
                DIR_W::new(self, 8)
            }
            #[doc = "Bit 9 - Enable this bit to send a STOP condition at the end of a transaction. Master mode only."]
            #[inline(always)]
            #[must_use]
            pub fn phase_stop(&mut self) -> PHASE_STOP_W<CTRL_SPEC> {
                PHASE_STOP_W::new(self, 9)
            }
            #[doc = "Bit 10 - Enable this bit to send the data after Address phase. Master mode only."]
            #[inline(always)]
            #[must_use]
            pub fn phase_data(&mut self) -> PHASE_DATA_W<CTRL_SPEC> {
                PHASE_DATA_W::new(self, 10)
            }
            #[doc = "Bit 11 - Enable this bit to send the address after START condition. Master mode only."]
            #[inline(always)]
            #[must_use]
            pub fn phase_addr(&mut self) -> PHASE_ADDR_W<CTRL_SPEC> {
                PHASE_ADDR_W::new(self, 11)
            }
            #[doc = "Bit 12 - Enable this bit to send a START condition at the beginning of transaction. Master mode only."]
            #[inline(always)]
            #[must_use]
            pub fn phase_start(&mut self) -> PHASE_START_W<CTRL_SPEC> {
                PHASE_START_W::new(self, 12)
            }
            #[doc = "Bit 13 - set to send reset signals(just toggle clock bus defined by reset_len). this register is clered when reset is end, can't be cleared by software"]
            #[inline(always)]
            #[must_use]
            pub fn reset_on(&mut self) -> RESET_ON_W<CTRL_SPEC> {
                RESET_ON_W::new(self, 13)
            }
            #[doc = "Bit 14 - set to hold input clock to high when reset is active"]
            #[inline(always)]
            #[must_use]
            pub fn reset_hold_sckin(&mut self) -> RESET_HOLD_SCKIN_W<CTRL_SPEC> {
                RESET_HOLD_SCKIN_W::new(self, 14)
            }
            #[doc = "Bits 20:23 - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle."]
            #[inline(always)]
            #[must_use]
            pub fn reset_len(&mut self) -> RESET_LEN_W<CTRL_SPEC> {
                RESET_LEN_W::new(self, 20)
            }
            #[doc = "Bits 24:31 - Data counts in bytes. Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. Slave: the meaning of DataCnt depends on the DMA mode: If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received."]
            #[inline(always)]
            #[must_use]
            pub fn datacnt_high(&mut self) -> DATACNT_HIGH_W<CTRL_SPEC> {
                DATACNT_HIGH_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CTRL_SPEC;
        impl crate::RegisterSpec for CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
        impl crate::Readable for CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
        impl crate::Writable for CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Ctrl to value 0x0090_5e00"]
        impl crate::Resettable for CTRL_SPEC {
            const RESET_VALUE: u32 = 0x0090_5e00;
        }
    }
    #[doc = "Cmd (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"]
    pub type CMD = crate::Reg<cmd::CMD_SPEC>;
    #[doc = "Command Register"]
    pub mod cmd {
        #[doc = "Register `Cmd` reader"]
        pub type R = crate::R<CMD_SPEC>;
        #[doc = "Register `Cmd` writer"]
        pub type W = crate::W<CMD_SPEC>;
        #[doc = "Field `CMD` reader - Write this register with the following values to perform the corresponding actions: 0x0: no action 0x1: issue a data transaction (Master only) 0x2: respond with an ACK to the received byte 0x3: respond with a NACK to the received byte 0x4: clear the FIFO 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled."]
        pub type CMD_R = crate::FieldReader;
        #[doc = "Field `CMD` writer - Write this register with the following values to perform the corresponding actions: 0x0: no action 0x1: issue a data transaction (Master only) 0x2: respond with an ACK to the received byte 0x3: respond with a NACK to the received byte 0x4: clear the FIFO 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled."]
        pub type CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2 - Write this register with the following values to perform the corresponding actions: 0x0: no action 0x1: issue a data transaction (Master only) 0x2: respond with an ACK to the received byte 0x3: respond with a NACK to the received byte 0x4: clear the FIFO 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled."]
            #[inline(always)]
            pub fn cmd(&self) -> CMD_R {
                CMD_R::new((self.bits & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - Write this register with the following values to perform the corresponding actions: 0x0: no action 0x1: issue a data transaction (Master only) 0x2: respond with an ACK to the received byte 0x3: respond with a NACK to the received byte 0x4: clear the FIFO 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled."]
            #[inline(always)]
            #[must_use]
            pub fn cmd(&mut self) -> CMD_W<CMD_SPEC> {
                CMD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMD_SPEC;
        impl crate::RegisterSpec for CMD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
        impl crate::Readable for CMD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
        impl crate::Writable for CMD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Cmd to value 0"]
        impl crate::Resettable for CMD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Setup (rw) register accessor: Setup Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`setup::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@setup`]
module"]
    pub type SETUP = crate::Reg<setup::SETUP_SPEC>;
    #[doc = "Setup Register"]
    pub mod setup {
        #[doc = "Register `Setup` reader"]
        pub type R = crate::R<SETUP_SPEC>;
        #[doc = "Register `Setup` writer"]
        pub type W = crate::W<SETUP_SPEC>;
        #[doc = "Field `IICEN` reader - Enable the I2C controller. 1: Enable 0: Disable"]
        pub type IICEN_R = crate::BitReader;
        #[doc = "Field `IICEN` writer - Enable the I2C controller. 1: Enable 0: Disable"]
        pub type IICEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ADDRESSING` reader - I2C addressing mode: 1: 10-bit addressing mode 0: 7-bit addressing mode"]
        pub type ADDRESSING_R = crate::BitReader;
        #[doc = "Field `ADDRESSING` writer - I2C addressing mode: 1: 10-bit addressing mode 0: 7-bit addressing mode"]
        pub type ADDRESSING_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MASTER` reader - Configure this device as a master or a slave. 1: Master mode 0: Slave mode"]
        pub type MASTER_R = crate::BitReader;
        #[doc = "Field `MASTER` writer - Configure this device as a master or a slave. 1: Master mode 0: Slave mode"]
        pub type MASTER_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMAEN` reader - Enable the direct memory access mode data transfer. 1: Enable 0: Disable"]
        pub type DMAEN_R = crate::BitReader;
        #[doc = "Field `DMAEN` writer - Enable the direct memory access mode data transfer. 1: Enable 0: Disable"]
        pub type DMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `T_SCLHI` reader - The HIGH period of generated SCL clock is defined by T_SCLHi. SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) The T_SCLHi value must be greater than T_SP and T_HDDAT values. This field is only valid when the controller is in the master mode."]
        pub type T_SCLHI_R = crate::FieldReader<u16>;
        #[doc = "Field `T_SCLHI` writer - The HIGH period of generated SCL clock is defined by T_SCLHi. SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) The T_SCLHi value must be greater than T_SP and T_HDDAT values. This field is only valid when the controller is in the master mode."]
        pub type T_SCLHI_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `T_SCLRADIO` reader - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) 1: ratio = 2 0: ratio = 1 This field is only valid when the controller is in the master mode."]
        pub type T_SCLRADIO_R = crate::BitReader;
        #[doc = "Field `T_SCLRADIO` writer - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) 1: ratio = 2 0: ratio = 1 This field is only valid when the controller is in the master mode."]
        pub type T_SCLRADIO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `T_HDDAT` reader - T_HDDAT defines the data hold time after SCL goes LOW Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1)"]
        pub type T_HDDAT_R = crate::FieldReader;
        #[doc = "Field `T_HDDAT` writer - T_HDDAT defines the data hold time after SCL goes LOW Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1)"]
        pub type T_HDDAT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `T_SP` reader - T_SP defines the pulse width of spikes that must be suppressed by the input filter. Pulse width = T_SP * tpclk* (TPM+1)"]
        pub type T_SP_R = crate::FieldReader;
        #[doc = "Field `T_SP` writer - T_SP defines the pulse width of spikes that must be suppressed by the input filter. Pulse width = T_SP * tpclk* (TPM+1)"]
        pub type T_SP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `T_SUDAT` reader - T_SUDAT defines the data setup time before releasing the SCL. Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) tpclk = PCLK period TPM = The multiplier value in Timing Parameter Multiplier Register"]
        pub type T_SUDAT_R = crate::FieldReader;
        #[doc = "Field `T_SUDAT` writer - T_SUDAT defines the data setup time before releasing the SCL. Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) tpclk = PCLK period TPM = The multiplier value in Timing Parameter Multiplier Register"]
        pub type T_SUDAT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bit 0 - Enable the I2C controller. 1: Enable 0: Disable"]
            #[inline(always)]
            pub fn iicen(&self) -> IICEN_R {
                IICEN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - I2C addressing mode: 1: 10-bit addressing mode 0: 7-bit addressing mode"]
            #[inline(always)]
            pub fn addressing(&self) -> ADDRESSING_R {
                ADDRESSING_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Configure this device as a master or a slave. 1: Master mode 0: Slave mode"]
            #[inline(always)]
            pub fn master(&self) -> MASTER_R {
                MASTER_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Enable the direct memory access mode data transfer. 1: Enable 0: Disable"]
            #[inline(always)]
            pub fn dmaen(&self) -> DMAEN_R {
                DMAEN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 4:12 - The HIGH period of generated SCL clock is defined by T_SCLHi. SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) The T_SCLHi value must be greater than T_SP and T_HDDAT values. This field is only valid when the controller is in the master mode."]
            #[inline(always)]
            pub fn t_sclhi(&self) -> T_SCLHI_R {
                T_SCLHI_R::new(((self.bits >> 4) & 0x01ff) as u16)
            }
            #[doc = "Bit 13 - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) 1: ratio = 2 0: ratio = 1 This field is only valid when the controller is in the master mode."]
            #[inline(always)]
            pub fn t_sclradio(&self) -> T_SCLRADIO_R {
                T_SCLRADIO_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bits 16:20 - T_HDDAT defines the data hold time after SCL goes LOW Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1)"]
            #[inline(always)]
            pub fn t_hddat(&self) -> T_HDDAT_R {
                T_HDDAT_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bits 21:23 - T_SP defines the pulse width of spikes that must be suppressed by the input filter. Pulse width = T_SP * tpclk* (TPM+1)"]
            #[inline(always)]
            pub fn t_sp(&self) -> T_SP_R {
                T_SP_R::new(((self.bits >> 21) & 7) as u8)
            }
            #[doc = "Bits 24:28 - T_SUDAT defines the data setup time before releasing the SCL. Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) tpclk = PCLK period TPM = The multiplier value in Timing Parameter Multiplier Register"]
            #[inline(always)]
            pub fn t_sudat(&self) -> T_SUDAT_R {
                T_SUDAT_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable the I2C controller. 1: Enable 0: Disable"]
            #[inline(always)]
            #[must_use]
            pub fn iicen(&mut self) -> IICEN_W<SETUP_SPEC> {
                IICEN_W::new(self, 0)
            }
            #[doc = "Bit 1 - I2C addressing mode: 1: 10-bit addressing mode 0: 7-bit addressing mode"]
            #[inline(always)]
            #[must_use]
            pub fn addressing(&mut self) -> ADDRESSING_W<SETUP_SPEC> {
                ADDRESSING_W::new(self, 1)
            }
            #[doc = "Bit 2 - Configure this device as a master or a slave. 1: Master mode 0: Slave mode"]
            #[inline(always)]
            #[must_use]
            pub fn master(&mut self) -> MASTER_W<SETUP_SPEC> {
                MASTER_W::new(self, 2)
            }
            #[doc = "Bit 3 - Enable the direct memory access mode data transfer. 1: Enable 0: Disable"]
            #[inline(always)]
            #[must_use]
            pub fn dmaen(&mut self) -> DMAEN_W<SETUP_SPEC> {
                DMAEN_W::new(self, 3)
            }
            #[doc = "Bits 4:12 - The HIGH period of generated SCL clock is defined by T_SCLHi. SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) The T_SCLHi value must be greater than T_SP and T_HDDAT values. This field is only valid when the controller is in the master mode."]
            #[inline(always)]
            #[must_use]
            pub fn t_sclhi(&mut self) -> T_SCLHI_W<SETUP_SPEC> {
                T_SCLHI_W::new(self, 4)
            }
            #[doc = "Bit 13 - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) 1: ratio = 2 0: ratio = 1 This field is only valid when the controller is in the master mode."]
            #[inline(always)]
            #[must_use]
            pub fn t_sclradio(&mut self) -> T_SCLRADIO_W<SETUP_SPEC> {
                T_SCLRADIO_W::new(self, 13)
            }
            #[doc = "Bits 16:20 - T_HDDAT defines the data hold time after SCL goes LOW Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1)"]
            #[inline(always)]
            #[must_use]
            pub fn t_hddat(&mut self) -> T_HDDAT_W<SETUP_SPEC> {
                T_HDDAT_W::new(self, 16)
            }
            #[doc = "Bits 21:23 - T_SP defines the pulse width of spikes that must be suppressed by the input filter. Pulse width = T_SP * tpclk* (TPM+1)"]
            #[inline(always)]
            #[must_use]
            pub fn t_sp(&mut self) -> T_SP_W<SETUP_SPEC> {
                T_SP_W::new(self, 21)
            }
            #[doc = "Bits 24:28 - T_SUDAT defines the data setup time before releasing the SCL. Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) tpclk = PCLK period TPM = The multiplier value in Timing Parameter Multiplier Register"]
            #[inline(always)]
            #[must_use]
            pub fn t_sudat(&mut self) -> T_SUDAT_W<SETUP_SPEC> {
                T_SUDAT_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Setup Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`setup::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`setup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SETUP_SPEC;
        impl crate::RegisterSpec for SETUP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`setup::R`](R) reader structure"]
        impl crate::Readable for SETUP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`setup::W`](W) writer structure"]
        impl crate::Writable for SETUP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Setup to value 0x0525_2100"]
        impl crate::Resettable for SETUP_SPEC {
            const RESET_VALUE: u32 = 0x0525_2100;
        }
    }
    #[doc = "TPM (rw) register accessor: I2C Timing Paramater Multiplier\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpm::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpm`]
module"]
    pub type TPM = crate::Reg<tpm::TPM_SPEC>;
    #[doc = "I2C Timing Paramater Multiplier"]
    pub mod tpm {
        #[doc = "Register `TPM` reader"]
        pub type R = crate::R<TPM_SPEC>;
        #[doc = "Register `TPM` writer"]
        pub type W = crate::W<TPM_SPEC>;
        #[doc = "Field `TPM` reader - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1)."]
        pub type TPM_R = crate::FieldReader;
        #[doc = "Field `TPM` writer - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1)."]
        pub type TPM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:4 - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1)."]
            #[inline(always)]
            pub fn tpm(&self) -> TPM_R {
                TPM_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1)."]
            #[inline(always)]
            #[must_use]
            pub fn tpm(&mut self) -> TPM_W<TPM_SPEC> {
                TPM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "I2C Timing Paramater Multiplier\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpm::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TPM_SPEC;
        impl crate::RegisterSpec for TPM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tpm::R`](R) reader structure"]
        impl crate::Readable for TPM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tpm::W`](W) writer structure"]
        impl crate::Writable for TPM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TPM to value 0"]
        impl crate::Resettable for TPM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "I2C1"]
pub struct I2C1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C1 {}
impl I2C1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const i2c0::RegisterBlock = 0xf006_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const i2c0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for I2C1 {
    type Target = i2c0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for I2C1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C1").finish()
    }
}
#[doc = "I2C1"]
pub use self::i2c0 as i2c1;
#[doc = "I2C2"]
pub struct I2C2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C2 {}
impl I2C2 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const i2c0::RegisterBlock = 0xf006_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const i2c0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for I2C2 {
    type Target = i2c0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for I2C2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C2").finish()
    }
}
#[doc = "I2C2"]
pub use self::i2c0 as i2c2;
#[doc = "I2C3"]
pub struct I2C3 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for I2C3 {}
impl I2C3 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const i2c0::RegisterBlock = 0xf006_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const i2c0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for I2C3 {
    type Target = i2c0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for I2C3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("I2C3").finish()
    }
}
#[doc = "I2C3"]
pub use self::i2c0 as i2c3;
#[doc = "SPI0"]
pub struct SPI0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI0 {}
impl SPI0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const spi0::RegisterBlock = 0xf007_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const spi0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SPI0 {
    type Target = spi0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SPI0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI0").finish()
    }
}
#[doc = "SPI0"]
pub mod spi0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x04],
        wr_trans_cnt: WR_TRANS_CNT,
        rd_trans_cnt: RD_TRANS_CNT,
        _reserved2: [u8; 0x04],
        trans_fmt: TRANS_FMT,
        direct_io: DIRECT_IO,
        _reserved4: [u8; 0x08],
        trans_ctrl: TRANS_CTRL,
        cmd: CMD,
        addr: ADDR,
        data: DATA,
        ctrl: CTRL,
        status: STATUS,
        intr_en: INTR_EN,
        intr_st: INTR_ST,
        timing: TIMING,
        _reserved13: [u8; 0x1c],
        slv_st: SLV_ST,
        slv_data_cnt: SLV_DATA_CNT,
        slv_data_wcnt: SLV_DATA_WCNT,
        slv_data_rcnt: SLV_DATA_RCNT,
        _reserved17: [u8; 0x0c],
        config: CONFIG,
    }
    impl RegisterBlock {
        #[doc = "0x04 - Transfer count for write data"]
        #[inline(always)]
        pub const fn wr_trans_cnt(&self) -> &WR_TRANS_CNT {
            &self.wr_trans_cnt
        }
        #[doc = "0x08 - Transfer count for read data"]
        #[inline(always)]
        pub const fn rd_trans_cnt(&self) -> &RD_TRANS_CNT {
            &self.rd_trans_cnt
        }
        #[doc = "0x10 - Transfer Format Register"]
        #[inline(always)]
        pub const fn trans_fmt(&self) -> &TRANS_FMT {
            &self.trans_fmt
        }
        #[doc = "0x14 - Direct IO Control Register"]
        #[inline(always)]
        pub const fn direct_io(&self) -> &DIRECT_IO {
            &self.direct_io
        }
        #[doc = "0x20 - Transfer Control Register"]
        #[inline(always)]
        pub const fn trans_ctrl(&self) -> &TRANS_CTRL {
            &self.trans_ctrl
        }
        #[doc = "0x24 - Command Register"]
        #[inline(always)]
        pub const fn cmd(&self) -> &CMD {
            &self.cmd
        }
        #[doc = "0x28 - Address Register"]
        #[inline(always)]
        pub const fn addr(&self) -> &ADDR {
            &self.addr
        }
        #[doc = "0x2c - Data Register"]
        #[inline(always)]
        pub const fn data(&self) -> &DATA {
            &self.data
        }
        #[doc = "0x30 - Control Register"]
        #[inline(always)]
        pub const fn ctrl(&self) -> &CTRL {
            &self.ctrl
        }
        #[doc = "0x34 - Status Register"]
        #[inline(always)]
        pub const fn status(&self) -> &STATUS {
            &self.status
        }
        #[doc = "0x38 - Interrupt Enable Register"]
        #[inline(always)]
        pub const fn intr_en(&self) -> &INTR_EN {
            &self.intr_en
        }
        #[doc = "0x3c - Interrupt Status Register"]
        #[inline(always)]
        pub const fn intr_st(&self) -> &INTR_ST {
            &self.intr_st
        }
        #[doc = "0x40 - Interface Timing Register"]
        #[inline(always)]
        pub const fn timing(&self) -> &TIMING {
            &self.timing
        }
        #[doc = "0x60 - Slave Status Register"]
        #[inline(always)]
        pub const fn slv_st(&self) -> &SLV_ST {
            &self.slv_st
        }
        #[doc = "0x64 - Slave Data Count Register"]
        #[inline(always)]
        pub const fn slv_data_cnt(&self) -> &SLV_DATA_CNT {
            &self.slv_data_cnt
        }
        #[doc = "0x68 - WCnt"]
        #[inline(always)]
        pub const fn slv_data_wcnt(&self) -> &SLV_DATA_WCNT {
            &self.slv_data_wcnt
        }
        #[doc = "0x6c - RCnt"]
        #[inline(always)]
        pub const fn slv_data_rcnt(&self) -> &SLV_DATA_RCNT {
            &self.slv_data_rcnt
        }
        #[doc = "0x7c - Configuration Register"]
        #[inline(always)]
        pub const fn config(&self) -> &CONFIG {
            &self.config
        }
    }
    #[doc = "wr_trans_cnt (rw) register accessor: Transfer count for write data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_trans_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_trans_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wr_trans_cnt`]
module"]
    pub type WR_TRANS_CNT = crate::Reg<wr_trans_cnt::WR_TRANS_CNT_SPEC>;
    #[doc = "Transfer count for write data"]
    pub mod wr_trans_cnt {
        #[doc = "Register `wr_trans_cnt` reader"]
        pub type R = crate::R<WR_TRANS_CNT_SPEC>;
        #[doc = "Register `wr_trans_cnt` writer"]
        pub type W = crate::W<WR_TRANS_CNT_SPEC>;
        #[doc = "Field `WRTRANCNT` reader - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
        pub type WRTRANCNT_R = crate::FieldReader<u32>;
        #[doc = "Field `WRTRANCNT` writer - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
        pub type WRTRANCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
            #[inline(always)]
            pub fn wrtrancnt(&self) -> WRTRANCNT_R {
                WRTRANCNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
            #[inline(always)]
            #[must_use]
            pub fn wrtrancnt(&mut self) -> WRTRANCNT_W<WR_TRANS_CNT_SPEC> {
                WRTRANCNT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Transfer count for write data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wr_trans_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wr_trans_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WR_TRANS_CNT_SPEC;
        impl crate::RegisterSpec for WR_TRANS_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wr_trans_cnt::R`](R) reader structure"]
        impl crate::Readable for WR_TRANS_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wr_trans_cnt::W`](W) writer structure"]
        impl crate::Writable for WR_TRANS_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets wr_trans_cnt to value 0"]
        impl crate::Resettable for WR_TRANS_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "rd_trans_cnt (rw) register accessor: Transfer count for read data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_trans_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_trans_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rd_trans_cnt`]
module"]
    pub type RD_TRANS_CNT = crate::Reg<rd_trans_cnt::RD_TRANS_CNT_SPEC>;
    #[doc = "Transfer count for read data"]
    pub mod rd_trans_cnt {
        #[doc = "Register `rd_trans_cnt` reader"]
        pub type R = crate::R<RD_TRANS_CNT_SPEC>;
        #[doc = "Register `rd_trans_cnt` writer"]
        pub type W = crate::W<RD_TRANS_CNT_SPEC>;
        #[doc = "Field `RDTRANCNT` reader - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
        pub type RDTRANCNT_R = crate::FieldReader<u32>;
        #[doc = "Field `RDTRANCNT` writer - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
        pub type RDTRANCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
            #[inline(always)]
            pub fn rdtrancnt(&self) -> RDTRANCNT_R {
                RDTRANCNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
            #[inline(always)]
            #[must_use]
            pub fn rdtrancnt(&mut self) -> RDTRANCNT_W<RD_TRANS_CNT_SPEC> {
                RDTRANCNT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Transfer count for read data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rd_trans_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rd_trans_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RD_TRANS_CNT_SPEC;
        impl crate::RegisterSpec for RD_TRANS_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rd_trans_cnt::R`](R) reader structure"]
        impl crate::Readable for RD_TRANS_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rd_trans_cnt::W`](W) writer structure"]
        impl crate::Writable for RD_TRANS_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets rd_trans_cnt to value 0"]
        impl crate::Resettable for RD_TRANS_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TransFmt (rw) register accessor: Transfer Format Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trans_fmt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trans_fmt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trans_fmt`]
module"]
    pub type TRANS_FMT = crate::Reg<trans_fmt::TRANS_FMT_SPEC>;
    #[doc = "Transfer Format Register"]
    pub mod trans_fmt {
        #[doc = "Register `TransFmt` reader"]
        pub type R = crate::R<TRANS_FMT_SPEC>;
        #[doc = "Register `TransFmt` writer"]
        pub type W = crate::W<TRANS_FMT_SPEC>;
        #[doc = "Field `CPHA` reader - SPI Clock Phase 0x0: Sampling data at odd SCLK edges 0x1: Sampling data at even SCLK edges"]
        pub type CPHA_R = crate::BitReader;
        #[doc = "Field `CPHA` writer - SPI Clock Phase 0x0: Sampling data at odd SCLK edges 0x1: Sampling data at even SCLK edges"]
        pub type CPHA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CPOL` reader - SPI Clock Polarity 0x0: SCLK is LOW in the idle states 0x1: SCLK is HIGH in the idle states"]
        pub type CPOL_R = crate::BitReader;
        #[doc = "Field `CPOL` writer - SPI Clock Polarity 0x0: SCLK is LOW in the idle states 0x1: SCLK is HIGH in the idle states"]
        pub type CPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLVMODE` reader - SPI Master/Slave mode selection 0x0: Master mode 0x1: Slave mode"]
        pub type SLVMODE_R = crate::BitReader;
        #[doc = "Field `SLVMODE` writer - SPI Master/Slave mode selection 0x0: Master mode 0x1: Slave mode"]
        pub type SLVMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LSB` reader - Transfer data with the least significant bit first 0x0: Most significant bit first 0x1: Least significant bit first"]
        pub type LSB_R = crate::BitReader;
        #[doc = "Field `LSB` writer - Transfer data with the least significant bit first 0x0: Most significant bit first 0x1: Least significant bit first"]
        pub type LSB_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MOSIBIDIR` reader - Bi-directional MOSI in regular (single) mode 0x0: MOSI is uni-directional signal in regular mode. 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two"]
        pub type MOSIBIDIR_R = crate::BitReader;
        #[doc = "Field `MOSIBIDIR` writer - Bi-directional MOSI in regular (single) mode 0x0: MOSI is uni-directional signal in regular mode. 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two"]
        pub type MOSIBIDIR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DATAMERGE` reader - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed."]
        pub type DATAMERGE_R = crate::BitReader;
        #[doc = "Field `DATAMERGE` writer - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed."]
        pub type DATAMERGE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DATALEN` reader - The length of each data unit in bits The actual bit number of a data unit is (DataLen + 1)"]
        pub type DATALEN_R = crate::FieldReader;
        #[doc = "Field `DATALEN` writer - The length of each data unit in bits The actual bit number of a data unit is (DataLen + 1)"]
        pub type DATALEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `ADDRLEN` reader - Address length in bytes 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes"]
        pub type ADDRLEN_R = crate::FieldReader;
        #[doc = "Field `ADDRLEN` writer - Address length in bytes 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes"]
        pub type ADDRLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bit 0 - SPI Clock Phase 0x0: Sampling data at odd SCLK edges 0x1: Sampling data at even SCLK edges"]
            #[inline(always)]
            pub fn cpha(&self) -> CPHA_R {
                CPHA_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - SPI Clock Polarity 0x0: SCLK is LOW in the idle states 0x1: SCLK is HIGH in the idle states"]
            #[inline(always)]
            pub fn cpol(&self) -> CPOL_R {
                CPOL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - SPI Master/Slave mode selection 0x0: Master mode 0x1: Slave mode"]
            #[inline(always)]
            pub fn slvmode(&self) -> SLVMODE_R {
                SLVMODE_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Transfer data with the least significant bit first 0x0: Most significant bit first 0x1: Least significant bit first"]
            #[inline(always)]
            pub fn lsb(&self) -> LSB_R {
                LSB_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Bi-directional MOSI in regular (single) mode 0x0: MOSI is uni-directional signal in regular mode. 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two"]
            #[inline(always)]
            pub fn mosibidir(&self) -> MOSIBIDIR_R {
                MOSIBIDIR_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 7 - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed."]
            #[inline(always)]
            pub fn datamerge(&self) -> DATAMERGE_R {
                DATAMERGE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:12 - The length of each data unit in bits The actual bit number of a data unit is (DataLen + 1)"]
            #[inline(always)]
            pub fn datalen(&self) -> DATALEN_R {
                DATALEN_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:17 - Address length in bytes 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes"]
            #[inline(always)]
            pub fn addrlen(&self) -> ADDRLEN_R {
                ADDRLEN_R::new(((self.bits >> 16) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - SPI Clock Phase 0x0: Sampling data at odd SCLK edges 0x1: Sampling data at even SCLK edges"]
            #[inline(always)]
            #[must_use]
            pub fn cpha(&mut self) -> CPHA_W<TRANS_FMT_SPEC> {
                CPHA_W::new(self, 0)
            }
            #[doc = "Bit 1 - SPI Clock Polarity 0x0: SCLK is LOW in the idle states 0x1: SCLK is HIGH in the idle states"]
            #[inline(always)]
            #[must_use]
            pub fn cpol(&mut self) -> CPOL_W<TRANS_FMT_SPEC> {
                CPOL_W::new(self, 1)
            }
            #[doc = "Bit 2 - SPI Master/Slave mode selection 0x0: Master mode 0x1: Slave mode"]
            #[inline(always)]
            #[must_use]
            pub fn slvmode(&mut self) -> SLVMODE_W<TRANS_FMT_SPEC> {
                SLVMODE_W::new(self, 2)
            }
            #[doc = "Bit 3 - Transfer data with the least significant bit first 0x0: Most significant bit first 0x1: Least significant bit first"]
            #[inline(always)]
            #[must_use]
            pub fn lsb(&mut self) -> LSB_W<TRANS_FMT_SPEC> {
                LSB_W::new(self, 3)
            }
            #[doc = "Bit 4 - Bi-directional MOSI in regular (single) mode 0x0: MOSI is uni-directional signal in regular mode. 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two"]
            #[inline(always)]
            #[must_use]
            pub fn mosibidir(&mut self) -> MOSIBIDIR_W<TRANS_FMT_SPEC> {
                MOSIBIDIR_W::new(self, 4)
            }
            #[doc = "Bit 7 - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed."]
            #[inline(always)]
            #[must_use]
            pub fn datamerge(&mut self) -> DATAMERGE_W<TRANS_FMT_SPEC> {
                DATAMERGE_W::new(self, 7)
            }
            #[doc = "Bits 8:12 - The length of each data unit in bits The actual bit number of a data unit is (DataLen + 1)"]
            #[inline(always)]
            #[must_use]
            pub fn datalen(&mut self) -> DATALEN_W<TRANS_FMT_SPEC> {
                DATALEN_W::new(self, 8)
            }
            #[doc = "Bits 16:17 - Address length in bytes 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes"]
            #[inline(always)]
            #[must_use]
            pub fn addrlen(&mut self) -> ADDRLEN_W<TRANS_FMT_SPEC> {
                ADDRLEN_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Transfer Format Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trans_fmt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trans_fmt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRANS_FMT_SPEC;
        impl crate::RegisterSpec for TRANS_FMT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trans_fmt::R`](R) reader structure"]
        impl crate::Readable for TRANS_FMT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trans_fmt::W`](W) writer structure"]
        impl crate::Writable for TRANS_FMT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TransFmt to value 0x0002_0780"]
        impl crate::Resettable for TRANS_FMT_SPEC {
            const RESET_VALUE: u32 = 0x0002_0780;
        }
    }
    #[doc = "DirectIO (rw) register accessor: Direct IO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`direct_io::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`direct_io::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@direct_io`]
module"]
    pub type DIRECT_IO = crate::Reg<direct_io::DIRECT_IO_SPEC>;
    #[doc = "Direct IO Control Register"]
    pub mod direct_io {
        #[doc = "Register `DirectIO` reader"]
        pub type R = crate::R<DIRECT_IO_SPEC>;
        #[doc = "Register `DirectIO` writer"]
        pub type W = crate::W<DIRECT_IO_SPEC>;
        #[doc = "Field `CS_I` reader - Status of the SPI CS (chip select) signal"]
        pub type CS_I_R = crate::BitReader;
        #[doc = "Field `SCLK_I` reader - Status of the SPI SCLK signal"]
        pub type SCLK_I_R = crate::BitReader;
        #[doc = "Field `MOSI_I` reader - Status of the SPI MOSI signal"]
        pub type MOSI_I_R = crate::BitReader;
        #[doc = "Field `MISO_I` reader - Status of the SPI MISO signal"]
        pub type MISO_I_R = crate::BitReader;
        #[doc = "Field `WP_I` reader - Status of the SPI Flash write protect signal"]
        pub type WP_I_R = crate::BitReader;
        #[doc = "Field `HOLD_I` reader - Status of the SPI Flash hold signal"]
        pub type HOLD_I_R = crate::BitReader;
        #[doc = "Field `CS_O` reader - Output value for the SPI CS (chip select) signal"]
        pub type CS_O_R = crate::BitReader;
        #[doc = "Field `CS_O` writer - Output value for the SPI CS (chip select) signal"]
        pub type CS_O_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SCLK_O` reader - Output value for the SPI SCLK signal"]
        pub type SCLK_O_R = crate::BitReader;
        #[doc = "Field `SCLK_O` writer - Output value for the SPI SCLK signal"]
        pub type SCLK_O_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MOSI_O` reader - Output value for the SPI MOSI signal"]
        pub type MOSI_O_R = crate::BitReader;
        #[doc = "Field `MOSI_O` writer - Output value for the SPI MOSI signal"]
        pub type MOSI_O_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MISO_O` reader - Output value for the SPI MISO signal"]
        pub type MISO_O_R = crate::BitReader;
        #[doc = "Field `MISO_O` writer - Output value for the SPI MISO signal"]
        pub type MISO_O_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WP_O` reader - Output value for the SPI Flash write protect signal"]
        pub type WP_O_R = crate::BitReader;
        #[doc = "Field `WP_O` writer - Output value for the SPI Flash write protect signal"]
        pub type WP_O_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOLD_O` reader - Output value for the SPI Flash hold signal"]
        pub type HOLD_O_R = crate::BitReader;
        #[doc = "Field `HOLD_O` writer - Output value for the SPI Flash hold signal"]
        pub type HOLD_O_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CS_OE` reader - Output enable for SPI CS (chip select) signal"]
        pub type CS_OE_R = crate::BitReader;
        #[doc = "Field `CS_OE` writer - Output enable for SPI CS (chip select) signal"]
        pub type CS_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SCLK_OE` reader - Output enable for the SPI SCLK signal"]
        pub type SCLK_OE_R = crate::BitReader;
        #[doc = "Field `SCLK_OE` writer - Output enable for the SPI SCLK signal"]
        pub type SCLK_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MOSI_OE` reader - Output enable for the SPI MOSI signal"]
        pub type MOSI_OE_R = crate::BitReader;
        #[doc = "Field `MOSI_OE` writer - Output enable for the SPI MOSI signal"]
        pub type MOSI_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MISO_OE` reader - Output enable fo the SPI MISO signal"]
        pub type MISO_OE_R = crate::BitReader;
        #[doc = "Field `MISO_OE` writer - Output enable fo the SPI MISO signal"]
        pub type MISO_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WP_OE` reader - Output enable for the SPI Flash write protect signal"]
        pub type WP_OE_R = crate::BitReader;
        #[doc = "Field `WP_OE` writer - Output enable for the SPI Flash write protect signal"]
        pub type WP_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOLD_OE` reader - Output enable for the SPI Flash hold signal"]
        pub type HOLD_OE_R = crate::BitReader;
        #[doc = "Field `HOLD_OE` writer - Output enable for the SPI Flash hold signal"]
        pub type HOLD_OE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRECTIOEN` reader - Enable Direct IO 0x0: Disable 0x1: Enable"]
        pub type DIRECTIOEN_R = crate::BitReader;
        #[doc = "Field `DIRECTIOEN` writer - Enable Direct IO 0x0: Disable 0x1: Enable"]
        pub type DIRECTIOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Status of the SPI CS (chip select) signal"]
            #[inline(always)]
            pub fn cs_i(&self) -> CS_I_R {
                CS_I_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Status of the SPI SCLK signal"]
            #[inline(always)]
            pub fn sclk_i(&self) -> SCLK_I_R {
                SCLK_I_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Status of the SPI MOSI signal"]
            #[inline(always)]
            pub fn mosi_i(&self) -> MOSI_I_R {
                MOSI_I_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Status of the SPI MISO signal"]
            #[inline(always)]
            pub fn miso_i(&self) -> MISO_I_R {
                MISO_I_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Status of the SPI Flash write protect signal"]
            #[inline(always)]
            pub fn wp_i(&self) -> WP_I_R {
                WP_I_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Status of the SPI Flash hold signal"]
            #[inline(always)]
            pub fn hold_i(&self) -> HOLD_I_R {
                HOLD_I_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 8 - Output value for the SPI CS (chip select) signal"]
            #[inline(always)]
            pub fn cs_o(&self) -> CS_O_R {
                CS_O_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Output value for the SPI SCLK signal"]
            #[inline(always)]
            pub fn sclk_o(&self) -> SCLK_O_R {
                SCLK_O_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - Output value for the SPI MOSI signal"]
            #[inline(always)]
            pub fn mosi_o(&self) -> MOSI_O_R {
                MOSI_O_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - Output value for the SPI MISO signal"]
            #[inline(always)]
            pub fn miso_o(&self) -> MISO_O_R {
                MISO_O_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Output value for the SPI Flash write protect signal"]
            #[inline(always)]
            pub fn wp_o(&self) -> WP_O_R {
                WP_O_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Output value for the SPI Flash hold signal"]
            #[inline(always)]
            pub fn hold_o(&self) -> HOLD_O_R {
                HOLD_O_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 16 - Output enable for SPI CS (chip select) signal"]
            #[inline(always)]
            pub fn cs_oe(&self) -> CS_OE_R {
                CS_OE_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - Output enable for the SPI SCLK signal"]
            #[inline(always)]
            pub fn sclk_oe(&self) -> SCLK_OE_R {
                SCLK_OE_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - Output enable for the SPI MOSI signal"]
            #[inline(always)]
            pub fn mosi_oe(&self) -> MOSI_OE_R {
                MOSI_OE_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - Output enable fo the SPI MISO signal"]
            #[inline(always)]
            pub fn miso_oe(&self) -> MISO_OE_R {
                MISO_OE_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - Output enable for the SPI Flash write protect signal"]
            #[inline(always)]
            pub fn wp_oe(&self) -> WP_OE_R {
                WP_OE_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Output enable for the SPI Flash hold signal"]
            #[inline(always)]
            pub fn hold_oe(&self) -> HOLD_OE_R {
                HOLD_OE_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 24 - Enable Direct IO 0x0: Disable 0x1: Enable"]
            #[inline(always)]
            pub fn directioen(&self) -> DIRECTIOEN_R {
                DIRECTIOEN_R::new(((self.bits >> 24) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 8 - Output value for the SPI CS (chip select) signal"]
            #[inline(always)]
            #[must_use]
            pub fn cs_o(&mut self) -> CS_O_W<DIRECT_IO_SPEC> {
                CS_O_W::new(self, 8)
            }
            #[doc = "Bit 9 - Output value for the SPI SCLK signal"]
            #[inline(always)]
            #[must_use]
            pub fn sclk_o(&mut self) -> SCLK_O_W<DIRECT_IO_SPEC> {
                SCLK_O_W::new(self, 9)
            }
            #[doc = "Bit 10 - Output value for the SPI MOSI signal"]
            #[inline(always)]
            #[must_use]
            pub fn mosi_o(&mut self) -> MOSI_O_W<DIRECT_IO_SPEC> {
                MOSI_O_W::new(self, 10)
            }
            #[doc = "Bit 11 - Output value for the SPI MISO signal"]
            #[inline(always)]
            #[must_use]
            pub fn miso_o(&mut self) -> MISO_O_W<DIRECT_IO_SPEC> {
                MISO_O_W::new(self, 11)
            }
            #[doc = "Bit 12 - Output value for the SPI Flash write protect signal"]
            #[inline(always)]
            #[must_use]
            pub fn wp_o(&mut self) -> WP_O_W<DIRECT_IO_SPEC> {
                WP_O_W::new(self, 12)
            }
            #[doc = "Bit 13 - Output value for the SPI Flash hold signal"]
            #[inline(always)]
            #[must_use]
            pub fn hold_o(&mut self) -> HOLD_O_W<DIRECT_IO_SPEC> {
                HOLD_O_W::new(self, 13)
            }
            #[doc = "Bit 16 - Output enable for SPI CS (chip select) signal"]
            #[inline(always)]
            #[must_use]
            pub fn cs_oe(&mut self) -> CS_OE_W<DIRECT_IO_SPEC> {
                CS_OE_W::new(self, 16)
            }
            #[doc = "Bit 17 - Output enable for the SPI SCLK signal"]
            #[inline(always)]
            #[must_use]
            pub fn sclk_oe(&mut self) -> SCLK_OE_W<DIRECT_IO_SPEC> {
                SCLK_OE_W::new(self, 17)
            }
            #[doc = "Bit 18 - Output enable for the SPI MOSI signal"]
            #[inline(always)]
            #[must_use]
            pub fn mosi_oe(&mut self) -> MOSI_OE_W<DIRECT_IO_SPEC> {
                MOSI_OE_W::new(self, 18)
            }
            #[doc = "Bit 19 - Output enable fo the SPI MISO signal"]
            #[inline(always)]
            #[must_use]
            pub fn miso_oe(&mut self) -> MISO_OE_W<DIRECT_IO_SPEC> {
                MISO_OE_W::new(self, 19)
            }
            #[doc = "Bit 20 - Output enable for the SPI Flash write protect signal"]
            #[inline(always)]
            #[must_use]
            pub fn wp_oe(&mut self) -> WP_OE_W<DIRECT_IO_SPEC> {
                WP_OE_W::new(self, 20)
            }
            #[doc = "Bit 21 - Output enable for the SPI Flash hold signal"]
            #[inline(always)]
            #[must_use]
            pub fn hold_oe(&mut self) -> HOLD_OE_W<DIRECT_IO_SPEC> {
                HOLD_OE_W::new(self, 21)
            }
            #[doc = "Bit 24 - Enable Direct IO 0x0: Disable 0x1: Enable"]
            #[inline(always)]
            #[must_use]
            pub fn directioen(&mut self) -> DIRECTIOEN_W<DIRECT_IO_SPEC> {
                DIRECTIOEN_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Direct IO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`direct_io::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`direct_io::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DIRECT_IO_SPEC;
        impl crate::RegisterSpec for DIRECT_IO_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`direct_io::R`](R) reader structure"]
        impl crate::Readable for DIRECT_IO_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`direct_io::W`](W) writer structure"]
        impl crate::Writable for DIRECT_IO_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DirectIO to value 0x3100"]
        impl crate::Resettable for DIRECT_IO_SPEC {
            const RESET_VALUE: u32 = 0x3100;
        }
    }
    #[doc = "TransCtrl (rw) register accessor: Transfer Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trans_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trans_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trans_ctrl`]
module"]
    pub type TRANS_CTRL = crate::Reg<trans_ctrl::TRANS_CTRL_SPEC>;
    #[doc = "Transfer Control Register"]
    pub mod trans_ctrl {
        #[doc = "Register `TransCtrl` reader"]
        pub type R = crate::R<TRANS_CTRL_SPEC>;
        #[doc = "Register `TransCtrl` writer"]
        pub type W = crate::W<TRANS_CTRL_SPEC>;
        #[doc = "Field `RDTRANCNT` reader - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
        pub type RDTRANCNT_R = crate::FieldReader<u16>;
        #[doc = "Field `RDTRANCNT` writer - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
        pub type RDTRANCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `DUMMYCNT` reader - Dummy data count. The actual dummy count is (DummyCnt +1). The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) The Data pins are put into the high impedance during the dummy data phase. DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases."]
        pub type DUMMYCNT_R = crate::FieldReader;
        #[doc = "Field `DUMMYCNT` writer - Dummy data count. The actual dummy count is (DummyCnt +1). The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) The Data pins are put into the high impedance during the dummy data phase. DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases."]
        pub type DUMMYCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TOKENVALUE` reader - Token value (Master mode only) The value of the one-byte special token following the address phase for SPI read transfers. 0x0: token value = 0x00 0x1: token value = 0x69"]
        pub type TOKENVALUE_R = crate::BitReader;
        #[doc = "Field `TOKENVALUE` writer - Token value (Master mode only) The value of the one-byte special token following the address phase for SPI read transfers. 0x0: token value = 0x00 0x1: token value = 0x69"]
        pub type TOKENVALUE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WRTRANCNT` reader - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
        pub type WRTRANCNT_R = crate::FieldReader<u16>;
        #[doc = "Field `WRTRANCNT` writer - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
        pub type WRTRANCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `TOKENEN` reader - Token transfer enable (Master mode only) Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. 0x0: Disable the one-byte special token 0x1: Enable the one-byte special token"]
        pub type TOKENEN_R = crate::BitReader;
        #[doc = "Field `TOKENEN` writer - Token transfer enable (Master mode only) Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. 0x0: Disable the one-byte special token 0x1: Enable the one-byte special token"]
        pub type TOKENEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DUALQUAD` reader - SPI data phase format 0x0: Regular (Single) mode 0x1: Dual I/O mode 0x2: Quad I/O mode 0x3: Reserved"]
        pub type DUALQUAD_R = crate::FieldReader;
        #[doc = "Field `DUALQUAD` writer - SPI data phase format 0x0: Regular (Single) mode 0x1: Dual I/O mode 0x2: Quad I/O mode 0x3: Reserved"]
        pub type DUALQUAD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TRANSMODE` reader - Transfer mode The transfer sequence could be 0x0: Write and read at the same time 0x1: Write only 0x2: Read only 0x3: Write, Read 0x4: Read, Write 0x5: Write, Dummy, Read 0x6: Read, Dummy, Write 0x7: None Data (must enable CmdEn or AddrEn in master mode) 0x8: Dummy, Write 0x9: Dummy, Read 0xa~0xf: Reserved"]
        pub type TRANSMODE_R = crate::FieldReader;
        #[doc = "Field `TRANSMODE` writer - Transfer mode The transfer sequence could be 0x0: Write and read at the same time 0x1: Write only 0x2: Read only 0x3: Write, Read 0x4: Read, Write 0x5: Write, Dummy, Read 0x6: Read, Dummy, Write 0x7: None Data (must enable CmdEn or AddrEn in master mode) 0x8: Dummy, Write 0x9: Dummy, Read 0xa~0xf: Reserved"]
        pub type TRANSMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `ADDRFMT` reader - SPI address phase format (Master mode only) 0x0: Address phase is the regular (single) mode 0x1: The format of the address phase is the same as the data phase (DualQuad)."]
        pub type ADDRFMT_R = crate::BitReader;
        #[doc = "Field `ADDRFMT` writer - SPI address phase format (Master mode only) 0x0: Address phase is the regular (single) mode 0x1: The format of the address phase is the same as the data phase (DualQuad)."]
        pub type ADDRFMT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ADDREN` reader - SPI address phase enable (Master mode only) 0x0: Disable the address phase 0x1: Enable the address phase"]
        pub type ADDREN_R = crate::BitReader;
        #[doc = "Field `ADDREN` writer - SPI address phase enable (Master mode only) 0x0: Disable the address phase 0x1: Enable the address phase"]
        pub type ADDREN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CMDEN` reader - SPI command phase enable (Master mode only) 0x0: Disable the command phase 0x1: Enable the command phase"]
        pub type CMDEN_R = crate::BitReader;
        #[doc = "Field `CMDEN` writer - SPI command phase enable (Master mode only) 0x0: Disable the command phase 0x1: Enable the command phase"]
        pub type CMDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLVDATAONLY` reader - Data-only mode (slave mode only) 0x0: Disable the data-only mode 0x1: Enable the data-only mode Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0."]
        pub type SLVDATAONLY_R = crate::BitReader;
        #[doc = "Field `SLVDATAONLY` writer - Data-only mode (slave mode only) 0x0: Disable the data-only mode 0x1: Enable the data-only mode Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0."]
        pub type SLVDATAONLY_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:8 - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
            #[inline(always)]
            pub fn rdtrancnt(&self) -> RDTRANCNT_R {
                RDTRANCNT_R::new((self.bits & 0x01ff) as u16)
            }
            #[doc = "Bits 9:10 - Dummy data count. The actual dummy count is (DummyCnt +1). The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) The Data pins are put into the high impedance during the dummy data phase. DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases."]
            #[inline(always)]
            pub fn dummycnt(&self) -> DUMMYCNT_R {
                DUMMYCNT_R::new(((self.bits >> 9) & 3) as u8)
            }
            #[doc = "Bit 11 - Token value (Master mode only) The value of the one-byte special token following the address phase for SPI read transfers. 0x0: token value = 0x00 0x1: token value = 0x69"]
            #[inline(always)]
            pub fn tokenvalue(&self) -> TOKENVALUE_R {
                TOKENVALUE_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bits 12:20 - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
            #[inline(always)]
            pub fn wrtrancnt(&self) -> WRTRANCNT_R {
                WRTRANCNT_R::new(((self.bits >> 12) & 0x01ff) as u16)
            }
            #[doc = "Bit 21 - Token transfer enable (Master mode only) Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. 0x0: Disable the one-byte special token 0x1: Enable the one-byte special token"]
            #[inline(always)]
            pub fn tokenen(&self) -> TOKENEN_R {
                TOKENEN_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bits 22:23 - SPI data phase format 0x0: Regular (Single) mode 0x1: Dual I/O mode 0x2: Quad I/O mode 0x3: Reserved"]
            #[inline(always)]
            pub fn dualquad(&self) -> DUALQUAD_R {
                DUALQUAD_R::new(((self.bits >> 22) & 3) as u8)
            }
            #[doc = "Bits 24:27 - Transfer mode The transfer sequence could be 0x0: Write and read at the same time 0x1: Write only 0x2: Read only 0x3: Write, Read 0x4: Read, Write 0x5: Write, Dummy, Read 0x6: Read, Dummy, Write 0x7: None Data (must enable CmdEn or AddrEn in master mode) 0x8: Dummy, Write 0x9: Dummy, Read 0xa~0xf: Reserved"]
            #[inline(always)]
            pub fn transmode(&self) -> TRANSMODE_R {
                TRANSMODE_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            #[doc = "Bit 28 - SPI address phase format (Master mode only) 0x0: Address phase is the regular (single) mode 0x1: The format of the address phase is the same as the data phase (DualQuad)."]
            #[inline(always)]
            pub fn addrfmt(&self) -> ADDRFMT_R {
                ADDRFMT_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - SPI address phase enable (Master mode only) 0x0: Disable the address phase 0x1: Enable the address phase"]
            #[inline(always)]
            pub fn addren(&self) -> ADDREN_R {
                ADDREN_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - SPI command phase enable (Master mode only) 0x0: Disable the command phase 0x1: Enable the command phase"]
            #[inline(always)]
            pub fn cmden(&self) -> CMDEN_R {
                CMDEN_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - Data-only mode (slave mode only) 0x0: Disable the data-only mode 0x1: Enable the data-only mode Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0."]
            #[inline(always)]
            pub fn slvdataonly(&self) -> SLVDATAONLY_R {
                SLVDATAONLY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:8 - Transfer count for read data RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must equal RdTranCnt."]
            #[inline(always)]
            #[must_use]
            pub fn rdtrancnt(&mut self) -> RDTRANCNT_W<TRANS_CTRL_SPEC> {
                RDTRANCNT_W::new(self, 0)
            }
            #[doc = "Bits 9:10 - Dummy data count. The actual dummy count is (DummyCnt +1). The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) The Data pins are put into the high impedance during the dummy data phase. DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases."]
            #[inline(always)]
            #[must_use]
            pub fn dummycnt(&mut self) -> DUMMYCNT_W<TRANS_CTRL_SPEC> {
                DUMMYCNT_W::new(self, 9)
            }
            #[doc = "Bit 11 - Token value (Master mode only) The value of the one-byte special token following the address phase for SPI read transfers. 0x0: token value = 0x00 0x1: token value = 0x69"]
            #[inline(always)]
            #[must_use]
            pub fn tokenvalue(&mut self) -> TOKENVALUE_W<TRANS_CTRL_SPEC> {
                TOKENVALUE_W::new(self, 11)
            }
            #[doc = "Bits 12:20 - Transfer count for write data WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. For TransMode 0, WrTranCnt must be equal to RdTranCnt."]
            #[inline(always)]
            #[must_use]
            pub fn wrtrancnt(&mut self) -> WRTRANCNT_W<TRANS_CTRL_SPEC> {
                WRTRANCNT_W::new(self, 12)
            }
            #[doc = "Bit 21 - Token transfer enable (Master mode only) Append an one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. 0x0: Disable the one-byte special token 0x1: Enable the one-byte special token"]
            #[inline(always)]
            #[must_use]
            pub fn tokenen(&mut self) -> TOKENEN_W<TRANS_CTRL_SPEC> {
                TOKENEN_W::new(self, 21)
            }
            #[doc = "Bits 22:23 - SPI data phase format 0x0: Regular (Single) mode 0x1: Dual I/O mode 0x2: Quad I/O mode 0x3: Reserved"]
            #[inline(always)]
            #[must_use]
            pub fn dualquad(&mut self) -> DUALQUAD_W<TRANS_CTRL_SPEC> {
                DUALQUAD_W::new(self, 22)
            }
            #[doc = "Bits 24:27 - Transfer mode The transfer sequence could be 0x0: Write and read at the same time 0x1: Write only 0x2: Read only 0x3: Write, Read 0x4: Read, Write 0x5: Write, Dummy, Read 0x6: Read, Dummy, Write 0x7: None Data (must enable CmdEn or AddrEn in master mode) 0x8: Dummy, Write 0x9: Dummy, Read 0xa~0xf: Reserved"]
            #[inline(always)]
            #[must_use]
            pub fn transmode(&mut self) -> TRANSMODE_W<TRANS_CTRL_SPEC> {
                TRANSMODE_W::new(self, 24)
            }
            #[doc = "Bit 28 - SPI address phase format (Master mode only) 0x0: Address phase is the regular (single) mode 0x1: The format of the address phase is the same as the data phase (DualQuad)."]
            #[inline(always)]
            #[must_use]
            pub fn addrfmt(&mut self) -> ADDRFMT_W<TRANS_CTRL_SPEC> {
                ADDRFMT_W::new(self, 28)
            }
            #[doc = "Bit 29 - SPI address phase enable (Master mode only) 0x0: Disable the address phase 0x1: Enable the address phase"]
            #[inline(always)]
            #[must_use]
            pub fn addren(&mut self) -> ADDREN_W<TRANS_CTRL_SPEC> {
                ADDREN_W::new(self, 29)
            }
            #[doc = "Bit 30 - SPI command phase enable (Master mode only) 0x0: Disable the command phase 0x1: Enable the command phase"]
            #[inline(always)]
            #[must_use]
            pub fn cmden(&mut self) -> CMDEN_W<TRANS_CTRL_SPEC> {
                CMDEN_W::new(self, 30)
            }
            #[doc = "Bit 31 - Data-only mode (slave mode only) 0x0: Disable the data-only mode 0x1: Enable the data-only mode Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0."]
            #[inline(always)]
            #[must_use]
            pub fn slvdataonly(&mut self) -> SLVDATAONLY_W<TRANS_CTRL_SPEC> {
                SLVDATAONLY_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Transfer Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trans_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trans_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRANS_CTRL_SPEC;
        impl crate::RegisterSpec for TRANS_CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trans_ctrl::R`](R) reader structure"]
        impl crate::Readable for TRANS_CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trans_ctrl::W`](W) writer structure"]
        impl crate::Writable for TRANS_CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TransCtrl to value 0"]
        impl crate::Resettable for TRANS_CTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Cmd (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"]
    pub type CMD = crate::Reg<cmd::CMD_SPEC>;
    #[doc = "Command Register"]
    pub mod cmd {
        #[doc = "Register `Cmd` reader"]
        pub type R = crate::R<CMD_SPEC>;
        #[doc = "Register `Cmd` writer"]
        pub type W = crate::W<CMD_SPEC>;
        #[doc = "Field `CMD` reader - SPI Command"]
        pub type CMD_R = crate::FieldReader;
        #[doc = "Field `CMD` writer - SPI Command"]
        pub type CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - SPI Command"]
            #[inline(always)]
            pub fn cmd(&self) -> CMD_R {
                CMD_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - SPI Command"]
            #[inline(always)]
            #[must_use]
            pub fn cmd(&mut self) -> CMD_W<CMD_SPEC> {
                CMD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMD_SPEC;
        impl crate::RegisterSpec for CMD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
        impl crate::Readable for CMD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
        impl crate::Writable for CMD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Cmd to value 0"]
        impl crate::Resettable for CMD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Addr (rw) register accessor: Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
module"]
    pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
    #[doc = "Address Register"]
    pub mod addr {
        #[doc = "Register `Addr` reader"]
        pub type R = crate::R<ADDR_SPEC>;
        #[doc = "Register `Addr` writer"]
        pub type W = crate::W<ADDR_SPEC>;
        #[doc = "Field `ADDR` reader - SPI Address (Master mode only)"]
        pub type ADDR_R = crate::FieldReader<u32>;
        #[doc = "Field `ADDR` writer - SPI Address (Master mode only)"]
        pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - SPI Address (Master mode only)"]
            #[inline(always)]
            pub fn addr(&self) -> ADDR_R {
                ADDR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - SPI Address (Master mode only)"]
            #[inline(always)]
            #[must_use]
            pub fn addr(&mut self) -> ADDR_W<ADDR_SPEC> {
                ADDR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADDR_SPEC;
        impl crate::RegisterSpec for ADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`addr::R`](R) reader structure"]
        impl crate::Readable for ADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"]
        impl crate::Writable for ADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Addr to value 0"]
        impl crate::Resettable for ADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Data (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
    pub type DATA = crate::Reg<data::DATA_SPEC>;
    #[doc = "Data Register"]
    pub mod data {
        #[doc = "Register `Data` reader"]
        pub type R = crate::R<DATA_SPEC>;
        #[doc = "Register `Data` writer"]
        pub type W = crate::W<DATA_SPEC>;
        #[doc = "Field `DATA` reader - Data to transmit or the received data For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset."]
        pub type DATA_R = crate::FieldReader<u32>;
        #[doc = "Field `DATA` writer - Data to transmit or the received data For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset."]
        pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Data to transmit or the received data For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset."]
            #[inline(always)]
            pub fn data(&self) -> DATA_R {
                DATA_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Data to transmit or the received data For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset."]
            #[inline(always)]
            #[must_use]
            pub fn data(&mut self) -> DATA_W<DATA_SPEC> {
                DATA_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DATA_SPEC;
        impl crate::RegisterSpec for DATA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`data::R`](R) reader structure"]
        impl crate::Readable for DATA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
        impl crate::Writable for DATA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Data to value 0"]
        impl crate::Resettable for DATA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Ctrl (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
    pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
    #[doc = "Control Register"]
    pub mod ctrl {
        #[doc = "Register `Ctrl` reader"]
        pub type R = crate::R<CTRL_SPEC>;
        #[doc = "Register `Ctrl` writer"]
        pub type W = crate::W<CTRL_SPEC>;
        #[doc = "Field `SPIRST` reader - SPI reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
        pub type SPIRST_R = crate::BitReader;
        #[doc = "Field `SPIRST` writer - SPI reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
        pub type SPIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXFIFORST` reader - Receive FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
        pub type RXFIFORST_R = crate::BitReader;
        #[doc = "Field `RXFIFORST` writer - Receive FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
        pub type RXFIFORST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFIFORST` reader - Transmit FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
        pub type TXFIFORST_R = crate::BitReader;
        #[doc = "Field `TXFIFORST` writer - Transmit FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
        pub type TXFIFORST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXDMAEN` reader - RX DMA enable"]
        pub type RXDMAEN_R = crate::BitReader;
        #[doc = "Field `RXDMAEN` writer - RX DMA enable"]
        pub type RXDMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXDMAEN` reader - TX DMA enable"]
        pub type TXDMAEN_R = crate::BitReader;
        #[doc = "Field `TXDMAEN` writer - TX DMA enable"]
        pub type TXDMAEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXTHRES` reader - Receive (RX) FIFO Threshold The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold."]
        pub type RXTHRES_R = crate::FieldReader;
        #[doc = "Field `RXTHRES` writer - Receive (RX) FIFO Threshold The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold."]
        pub type RXTHRES_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `TXTHRES` reader - Transmit (TX) FIFO Threshold The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold."]
        pub type TXTHRES_R = crate::FieldReader;
        #[doc = "Field `TXTHRES` writer - Transmit (TX) FIFO Threshold The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold."]
        pub type TXTHRES_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `CS_EN` reader - No description avaiable"]
        pub type CS_EN_R = crate::FieldReader;
        #[doc = "Field `CS_EN` writer - No description avaiable"]
        pub type CS_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bit 0 - SPI reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
            #[inline(always)]
            pub fn spirst(&self) -> SPIRST_R {
                SPIRST_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Receive FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
            #[inline(always)]
            pub fn rxfiforst(&self) -> RXFIFORST_R {
                RXFIFORST_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Transmit FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
            #[inline(always)]
            pub fn txfiforst(&self) -> TXFIFORST_R {
                TXFIFORST_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - RX DMA enable"]
            #[inline(always)]
            pub fn rxdmaen(&self) -> RXDMAEN_R {
                RXDMAEN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - TX DMA enable"]
            #[inline(always)]
            pub fn txdmaen(&self) -> TXDMAEN_R {
                TXDMAEN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bits 8:15 - Receive (RX) FIFO Threshold The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold."]
            #[inline(always)]
            pub fn rxthres(&self) -> RXTHRES_R {
                RXTHRES_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - Transmit (TX) FIFO Threshold The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold."]
            #[inline(always)]
            pub fn txthres(&self) -> TXTHRES_R {
                TXTHRES_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bits 24:27 - No description avaiable"]
            #[inline(always)]
            pub fn cs_en(&self) -> CS_EN_R {
                CS_EN_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - SPI reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
            #[inline(always)]
            #[must_use]
            pub fn spirst(&mut self) -> SPIRST_W<CTRL_SPEC> {
                SPIRST_W::new(self, 0)
            }
            #[doc = "Bit 1 - Receive FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
            #[inline(always)]
            #[must_use]
            pub fn rxfiforst(&mut self) -> RXFIFORST_W<CTRL_SPEC> {
                RXFIFORST_W::new(self, 1)
            }
            #[doc = "Bit 2 - Transmit FIFO reset Write 1 to reset. It is automatically cleared to 0 after the reset operation completes."]
            #[inline(always)]
            #[must_use]
            pub fn txfiforst(&mut self) -> TXFIFORST_W<CTRL_SPEC> {
                TXFIFORST_W::new(self, 2)
            }
            #[doc = "Bit 3 - RX DMA enable"]
            #[inline(always)]
            #[must_use]
            pub fn rxdmaen(&mut self) -> RXDMAEN_W<CTRL_SPEC> {
                RXDMAEN_W::new(self, 3)
            }
            #[doc = "Bit 4 - TX DMA enable"]
            #[inline(always)]
            #[must_use]
            pub fn txdmaen(&mut self) -> TXDMAEN_W<CTRL_SPEC> {
                TXDMAEN_W::new(self, 4)
            }
            #[doc = "Bits 8:15 - Receive (RX) FIFO Threshold The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold."]
            #[inline(always)]
            #[must_use]
            pub fn rxthres(&mut self) -> RXTHRES_W<CTRL_SPEC> {
                RXTHRES_W::new(self, 8)
            }
            #[doc = "Bits 16:23 - Transmit (TX) FIFO Threshold The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold."]
            #[inline(always)]
            #[must_use]
            pub fn txthres(&mut self) -> TXTHRES_W<CTRL_SPEC> {
                TXTHRES_W::new(self, 16)
            }
            #[doc = "Bits 24:27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cs_en(&mut self) -> CS_EN_W<CTRL_SPEC> {
                CS_EN_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CTRL_SPEC;
        impl crate::RegisterSpec for CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
        impl crate::Readable for CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
        impl crate::Writable for CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Ctrl to value 0"]
        impl crate::Resettable for CTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Status (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
    pub type STATUS = crate::Reg<status::STATUS_SPEC>;
    #[doc = "Status Register"]
    pub mod status {
        #[doc = "Register `Status` reader"]
        pub type R = crate::R<STATUS_SPEC>;
        #[doc = "Register `Status` writer"]
        pub type W = crate::W<STATUS_SPEC>;
        #[doc = "Field `SPIACTIVE` reader - SPI register programming is in progress. In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used."]
        pub type SPIACTIVE_R = crate::BitReader;
        #[doc = "Field `RXNUM_5_0` reader - Number of valid entries in the Receive FIFO"]
        pub type RXNUM_5_0_R = crate::FieldReader;
        #[doc = "Field `RXEMPTY` reader - Receive FIFO Empty flag"]
        pub type RXEMPTY_R = crate::BitReader;
        #[doc = "Field `RXFULL` reader - Receive FIFO Full flag"]
        pub type RXFULL_R = crate::BitReader;
        #[doc = "Field `TXNUM_5_0` reader - Number of valid entries in the Transmit FIFO"]
        pub type TXNUM_5_0_R = crate::FieldReader;
        #[doc = "Field `TXEMPTY` reader - Transmit FIFO Empty flag"]
        pub type TXEMPTY_R = crate::BitReader;
        #[doc = "Field `TXFULL` reader - Transmit FIFO Full flag"]
        pub type TXFULL_R = crate::BitReader;
        #[doc = "Field `RXNUM_7_6` reader - Number of valid entries in the Receive FIFO"]
        pub type RXNUM_7_6_R = crate::FieldReader;
        #[doc = "Field `TXNUM_7_6` reader - Number of valid entries in the Transmit FIFO"]
        pub type TXNUM_7_6_R = crate::FieldReader;
        impl R {
            #[doc = "Bit 0 - SPI register programming is in progress. In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used."]
            #[inline(always)]
            pub fn spiactive(&self) -> SPIACTIVE_R {
                SPIACTIVE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 8:13 - Number of valid entries in the Receive FIFO"]
            #[inline(always)]
            pub fn rxnum_5_0(&self) -> RXNUM_5_0_R {
                RXNUM_5_0_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
            #[doc = "Bit 14 - Receive FIFO Empty flag"]
            #[inline(always)]
            pub fn rxempty(&self) -> RXEMPTY_R {
                RXEMPTY_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - Receive FIFO Full flag"]
            #[inline(always)]
            pub fn rxfull(&self) -> RXFULL_R {
                RXFULL_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bits 16:21 - Number of valid entries in the Transmit FIFO"]
            #[inline(always)]
            pub fn txnum_5_0(&self) -> TXNUM_5_0_R {
                TXNUM_5_0_R::new(((self.bits >> 16) & 0x3f) as u8)
            }
            #[doc = "Bit 22 - Transmit FIFO Empty flag"]
            #[inline(always)]
            pub fn txempty(&self) -> TXEMPTY_R {
                TXEMPTY_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - Transmit FIFO Full flag"]
            #[inline(always)]
            pub fn txfull(&self) -> TXFULL_R {
                TXFULL_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bits 24:25 - Number of valid entries in the Receive FIFO"]
            #[inline(always)]
            pub fn rxnum_7_6(&self) -> RXNUM_7_6_R {
                RXNUM_7_6_R::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bits 28:29 - Number of valid entries in the Transmit FIFO"]
            #[inline(always)]
            pub fn txnum_7_6(&self) -> TXNUM_7_6_R {
                TXNUM_7_6_R::new(((self.bits >> 28) & 3) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STATUS_SPEC;
        impl crate::RegisterSpec for STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`status::R`](R) reader structure"]
        impl crate::Readable for STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
        impl crate::Writable for STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Status to value 0"]
        impl crate::Resettable for STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IntrEn (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_en`]
module"]
    pub type INTR_EN = crate::Reg<intr_en::INTR_EN_SPEC>;
    #[doc = "Interrupt Enable Register"]
    pub mod intr_en {
        #[doc = "Register `IntrEn` reader"]
        pub type R = crate::R<INTR_EN_SPEC>;
        #[doc = "Register `IntrEn` writer"]
        pub type W = crate::W<INTR_EN_SPEC>;
        #[doc = "Field `RXFIFOORINTEN` reader - Enable the SPI Receive FIFO Overrun interrupt. Control whether interrupts are triggered when the Receive FIFO overflows. (Slave mode only)"]
        pub type RXFIFOORINTEN_R = crate::BitReader;
        #[doc = "Field `RXFIFOORINTEN` writer - Enable the SPI Receive FIFO Overrun interrupt. Control whether interrupts are triggered when the Receive FIFO overflows. (Slave mode only)"]
        pub type RXFIFOORINTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFIFOURINTEN` reader - Enable the SPI Transmit FIFO Underrun interrupt. Control whether interrupts are triggered when the Transmit FIFO run out of data. (Slave mode only)"]
        pub type TXFIFOURINTEN_R = crate::BitReader;
        #[doc = "Field `TXFIFOURINTEN` writer - Enable the SPI Transmit FIFO Underrun interrupt. Control whether interrupts are triggered when the Transmit FIFO run out of data. (Slave mode only)"]
        pub type TXFIFOURINTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXFIFOINTEN` reader - Enable the SPI Receive FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold."]
        pub type RXFIFOINTEN_R = crate::BitReader;
        #[doc = "Field `RXFIFOINTEN` writer - Enable the SPI Receive FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold."]
        pub type RXFIFOINTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFIFOINTEN` reader - Enable the SPI Transmit FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold."]
        pub type TXFIFOINTEN_R = crate::BitReader;
        #[doc = "Field `TXFIFOINTEN` writer - Enable the SPI Transmit FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold."]
        pub type TXFIFOINTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ENDINTEN` reader - Enable the End of SPI Transfer interrupt. Control whether interrupts are triggered when SPI transfers end. (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.)"]
        pub type ENDINTEN_R = crate::BitReader;
        #[doc = "Field `ENDINTEN` writer - Enable the End of SPI Transfer interrupt. Control whether interrupts are triggered when SPI transfers end. (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.)"]
        pub type ENDINTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLVCMDEN` reader - Enable the Slave Command Interrupt. Control whether interrupts are triggered whenever slave commands are received. (Slave mode only)"]
        pub type SLVCMDEN_R = crate::BitReader;
        #[doc = "Field `SLVCMDEN` writer - Enable the Slave Command Interrupt. Control whether interrupts are triggered whenever slave commands are received. (Slave mode only)"]
        pub type SLVCMDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Enable the SPI Receive FIFO Overrun interrupt. Control whether interrupts are triggered when the Receive FIFO overflows. (Slave mode only)"]
            #[inline(always)]
            pub fn rxfifoorinten(&self) -> RXFIFOORINTEN_R {
                RXFIFOORINTEN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Enable the SPI Transmit FIFO Underrun interrupt. Control whether interrupts are triggered when the Transmit FIFO run out of data. (Slave mode only)"]
            #[inline(always)]
            pub fn txfifourinten(&self) -> TXFIFOURINTEN_R {
                TXFIFOURINTEN_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Enable the SPI Receive FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold."]
            #[inline(always)]
            pub fn rxfifointen(&self) -> RXFIFOINTEN_R {
                RXFIFOINTEN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Enable the SPI Transmit FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold."]
            #[inline(always)]
            pub fn txfifointen(&self) -> TXFIFOINTEN_R {
                TXFIFOINTEN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Enable the End of SPI Transfer interrupt. Control whether interrupts are triggered when SPI transfers end. (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.)"]
            #[inline(always)]
            pub fn endinten(&self) -> ENDINTEN_R {
                ENDINTEN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Enable the Slave Command Interrupt. Control whether interrupts are triggered whenever slave commands are received. (Slave mode only)"]
            #[inline(always)]
            pub fn slvcmden(&self) -> SLVCMDEN_R {
                SLVCMDEN_R::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable the SPI Receive FIFO Overrun interrupt. Control whether interrupts are triggered when the Receive FIFO overflows. (Slave mode only)"]
            #[inline(always)]
            #[must_use]
            pub fn rxfifoorinten(&mut self) -> RXFIFOORINTEN_W<INTR_EN_SPEC> {
                RXFIFOORINTEN_W::new(self, 0)
            }
            #[doc = "Bit 1 - Enable the SPI Transmit FIFO Underrun interrupt. Control whether interrupts are triggered when the Transmit FIFO run out of data. (Slave mode only)"]
            #[inline(always)]
            #[must_use]
            pub fn txfifourinten(&mut self) -> TXFIFOURINTEN_W<INTR_EN_SPEC> {
                TXFIFOURINTEN_W::new(self, 1)
            }
            #[doc = "Bit 2 - Enable the SPI Receive FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold."]
            #[inline(always)]
            #[must_use]
            pub fn rxfifointen(&mut self) -> RXFIFOINTEN_W<INTR_EN_SPEC> {
                RXFIFOINTEN_W::new(self, 2)
            }
            #[doc = "Bit 3 - Enable the SPI Transmit FIFO Threshold interrupt. Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold."]
            #[inline(always)]
            #[must_use]
            pub fn txfifointen(&mut self) -> TXFIFOINTEN_W<INTR_EN_SPEC> {
                TXFIFOINTEN_W::new(self, 3)
            }
            #[doc = "Bit 4 - Enable the End of SPI Transfer interrupt. Control whether interrupts are triggered when SPI transfers end. (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.)"]
            #[inline(always)]
            #[must_use]
            pub fn endinten(&mut self) -> ENDINTEN_W<INTR_EN_SPEC> {
                ENDINTEN_W::new(self, 4)
            }
            #[doc = "Bit 5 - Enable the Slave Command Interrupt. Control whether interrupts are triggered whenever slave commands are received. (Slave mode only)"]
            #[inline(always)]
            #[must_use]
            pub fn slvcmden(&mut self) -> SLVCMDEN_W<INTR_EN_SPEC> {
                SLVCMDEN_W::new(self, 5)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INTR_EN_SPEC;
        impl crate::RegisterSpec for INTR_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`intr_en::R`](R) reader structure"]
        impl crate::Readable for INTR_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`intr_en::W`](W) writer structure"]
        impl crate::Writable for INTR_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IntrEn to value 0"]
        impl crate::Resettable for INTR_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IntrSt (rw) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_st::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr_st`]
module"]
    pub type INTR_ST = crate::Reg<intr_st::INTR_ST_SPEC>;
    #[doc = "Interrupt Status Register"]
    pub mod intr_st {
        #[doc = "Register `IntrSt` reader"]
        pub type R = crate::R<INTR_ST_SPEC>;
        #[doc = "Register `IntrSt` writer"]
        pub type W = crate::W<INTR_ST_SPEC>;
        #[doc = "Field `RXFIFOORINT` writer - RX FIFO Overrun interrupt. This bit is set when RX FIFO Overrun interrupts occur. (Slave mode only)"]
        pub type RXFIFOORINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFIFOURINT` writer - TX FIFO Underrun interrupt. This bit is set when TX FIFO Underrun interrupts occur. (Slave mode only)"]
        pub type TXFIFOURINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXFIFOINT` writer - RX FIFO Threshold interrupt. This bit is set when RX FIFO Threshold interrupts occur."]
        pub type RXFIFOINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXFIFOINT` writer - TX FIFO Threshold interrupt. This bit is set when TX FIFO Threshold interrupts occur."]
        pub type TXFIFOINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ENDINT` writer - End of SPI Transfer interrupt. This bit is set when End of SPI Transfer interrupts occur."]
        pub type ENDINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLVCMDINT` writer - Slave Command Interrupt. This bit is set when Slave Command interrupts occur. (Slave mode only)"]
        pub type SLVCMDINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - RX FIFO Overrun interrupt. This bit is set when RX FIFO Overrun interrupts occur. (Slave mode only)"]
            #[inline(always)]
            #[must_use]
            pub fn rxfifoorint(&mut self) -> RXFIFOORINT_W<INTR_ST_SPEC> {
                RXFIFOORINT_W::new(self, 0)
            }
            #[doc = "Bit 1 - TX FIFO Underrun interrupt. This bit is set when TX FIFO Underrun interrupts occur. (Slave mode only)"]
            #[inline(always)]
            #[must_use]
            pub fn txfifourint(&mut self) -> TXFIFOURINT_W<INTR_ST_SPEC> {
                TXFIFOURINT_W::new(self, 1)
            }
            #[doc = "Bit 2 - RX FIFO Threshold interrupt. This bit is set when RX FIFO Threshold interrupts occur."]
            #[inline(always)]
            #[must_use]
            pub fn rxfifoint(&mut self) -> RXFIFOINT_W<INTR_ST_SPEC> {
                RXFIFOINT_W::new(self, 2)
            }
            #[doc = "Bit 3 - TX FIFO Threshold interrupt. This bit is set when TX FIFO Threshold interrupts occur."]
            #[inline(always)]
            #[must_use]
            pub fn txfifoint(&mut self) -> TXFIFOINT_W<INTR_ST_SPEC> {
                TXFIFOINT_W::new(self, 3)
            }
            #[doc = "Bit 4 - End of SPI Transfer interrupt. This bit is set when End of SPI Transfer interrupts occur."]
            #[inline(always)]
            #[must_use]
            pub fn endint(&mut self) -> ENDINT_W<INTR_ST_SPEC> {
                ENDINT_W::new(self, 4)
            }
            #[doc = "Bit 5 - Slave Command Interrupt. This bit is set when Slave Command interrupts occur. (Slave mode only)"]
            #[inline(always)]
            #[must_use]
            pub fn slvcmdint(&mut self) -> SLVCMDINT_W<INTR_ST_SPEC> {
                SLVCMDINT_W::new(self, 5)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intr_st::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intr_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INTR_ST_SPEC;
        impl crate::RegisterSpec for INTR_ST_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`intr_st::R`](R) reader structure"]
        impl crate::Readable for INTR_ST_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`intr_st::W`](W) writer structure"]
        impl crate::Writable for INTR_ST_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IntrSt to value 0"]
        impl crate::Resettable for INTR_ST_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Timing (rw) register accessor: Interface Timing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timing::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timing::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timing`]
module"]
    pub type TIMING = crate::Reg<timing::TIMING_SPEC>;
    #[doc = "Interface Timing Register"]
    pub mod timing {
        #[doc = "Register `Timing` reader"]
        pub type R = crate::R<TIMING_SPEC>;
        #[doc = "Register `Timing` writer"]
        pub type W = crate::W<TIMING_SPEC>;
        #[doc = "Field `SCLK_DIV` reader - The clock frequency ratio between the clock source and SPI interface SCLK. SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency."]
        pub type SCLK_DIV_R = crate::FieldReader;
        #[doc = "Field `SCLK_DIV` writer - The clock frequency ratio between the clock source and SPI interface SCLK. SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency."]
        pub type SCLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `CSHT` reader - The minimum time that SPI CS should stay HIGH. SCLK_period * (CSHT + 1) / 2"]
        pub type CSHT_R = crate::FieldReader;
        #[doc = "Field `CSHT` writer - The minimum time that SPI CS should stay HIGH. SCLK_period * (CSHT + 1) / 2"]
        pub type CSHT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `CS2SCLK` reader - The minimum time between the edges of SPI CS and the edges of SCLK. SCLK_period * (CS2SCLK + 1) / 2"]
        pub type CS2SCLK_R = crate::FieldReader;
        #[doc = "Field `CS2SCLK` writer - The minimum time between the edges of SPI CS and the edges of SCLK. SCLK_period * (CS2SCLK + 1) / 2"]
        pub type CS2SCLK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bits 0:7 - The clock frequency ratio between the clock source and SPI interface SCLK. SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency."]
            #[inline(always)]
            pub fn sclk_div(&self) -> SCLK_DIV_R {
                SCLK_DIV_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:11 - The minimum time that SPI CS should stay HIGH. SCLK_period * (CSHT + 1) / 2"]
            #[inline(always)]
            pub fn csht(&self) -> CSHT_R {
                CSHT_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            #[doc = "Bits 12:13 - The minimum time between the edges of SPI CS and the edges of SCLK. SCLK_period * (CS2SCLK + 1) / 2"]
            #[inline(always)]
            pub fn cs2sclk(&self) -> CS2SCLK_R {
                CS2SCLK_R::new(((self.bits >> 12) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - The clock frequency ratio between the clock source and SPI interface SCLK. SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency."]
            #[inline(always)]
            #[must_use]
            pub fn sclk_div(&mut self) -> SCLK_DIV_W<TIMING_SPEC> {
                SCLK_DIV_W::new(self, 0)
            }
            #[doc = "Bits 8:11 - The minimum time that SPI CS should stay HIGH. SCLK_period * (CSHT + 1) / 2"]
            #[inline(always)]
            #[must_use]
            pub fn csht(&mut self) -> CSHT_W<TIMING_SPEC> {
                CSHT_W::new(self, 8)
            }
            #[doc = "Bits 12:13 - The minimum time between the edges of SPI CS and the edges of SCLK. SCLK_period * (CS2SCLK + 1) / 2"]
            #[inline(always)]
            #[must_use]
            pub fn cs2sclk(&mut self) -> CS2SCLK_W<TIMING_SPEC> {
                CS2SCLK_W::new(self, 12)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interface Timing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timing::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timing::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TIMING_SPEC;
        impl crate::RegisterSpec for TIMING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timing::R`](R) reader structure"]
        impl crate::Readable for TIMING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`timing::W`](W) writer structure"]
        impl crate::Writable for TIMING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Timing to value 0"]
        impl crate::Resettable for TIMING_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SlvSt (rw) register accessor: Slave Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_st::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slv_st`]
module"]
    pub type SLV_ST = crate::Reg<slv_st::SLV_ST_SPEC>;
    #[doc = "Slave Status Register"]
    pub mod slv_st {
        #[doc = "Register `SlvSt` reader"]
        pub type R = crate::R<SLV_ST_SPEC>;
        #[doc = "Register `SlvSt` writer"]
        pub type W = crate::W<SLV_ST_SPEC>;
        #[doc = "Field `USR_STATUS` reader - User defined status flags"]
        pub type USR_STATUS_R = crate::FieldReader<u16>;
        #[doc = "Field `USR_STATUS` writer - User defined status flags"]
        pub type USR_STATUS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `READY` reader - Set this bit to indicate that the ATCSPI200 is ready for data transaction. When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0."]
        pub type READY_R = crate::BitReader;
        #[doc = "Field `READY` writer - Set this bit to indicate that the ATCSPI200 is ready for data transaction. When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0."]
        pub type READY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OVERRUN` reader - Data overrun occurs in the last transaction"]
        pub type OVERRUN_R = crate::BitReader;
        #[doc = "Field `OVERRUN` writer - Data overrun occurs in the last transaction"]
        pub type OVERRUN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UNDERRUN` writer - Data underrun occurs in the last transaction"]
        pub type UNDERRUN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:15 - User defined status flags"]
            #[inline(always)]
            pub fn usr_status(&self) -> USR_STATUS_R {
                USR_STATUS_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bit 16 - Set this bit to indicate that the ATCSPI200 is ready for data transaction. When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0."]
            #[inline(always)]
            pub fn ready(&self) -> READY_R {
                READY_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - Data overrun occurs in the last transaction"]
            #[inline(always)]
            pub fn overrun(&self) -> OVERRUN_R {
                OVERRUN_R::new(((self.bits >> 17) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - User defined status flags"]
            #[inline(always)]
            #[must_use]
            pub fn usr_status(&mut self) -> USR_STATUS_W<SLV_ST_SPEC> {
                USR_STATUS_W::new(self, 0)
            }
            #[doc = "Bit 16 - Set this bit to indicate that the ATCSPI200 is ready for data transaction. When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0."]
            #[inline(always)]
            #[must_use]
            pub fn ready(&mut self) -> READY_W<SLV_ST_SPEC> {
                READY_W::new(self, 16)
            }
            #[doc = "Bit 17 - Data overrun occurs in the last transaction"]
            #[inline(always)]
            #[must_use]
            pub fn overrun(&mut self) -> OVERRUN_W<SLV_ST_SPEC> {
                OVERRUN_W::new(self, 17)
            }
            #[doc = "Bit 18 - Data underrun occurs in the last transaction"]
            #[inline(always)]
            #[must_use]
            pub fn underrun(&mut self) -> UNDERRUN_W<SLV_ST_SPEC> {
                UNDERRUN_W::new(self, 18)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Slave Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_st::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SLV_ST_SPEC;
        impl crate::RegisterSpec for SLV_ST_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`slv_st::R`](R) reader structure"]
        impl crate::Readable for SLV_ST_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`slv_st::W`](W) writer structure"]
        impl crate::Writable for SLV_ST_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SlvSt to value 0"]
        impl crate::Resettable for SLV_ST_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SlvDataCnt (rw) register accessor: Slave Data Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_data_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_data_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slv_data_cnt`]
module"]
    pub type SLV_DATA_CNT = crate::Reg<slv_data_cnt::SLV_DATA_CNT_SPEC>;
    #[doc = "Slave Data Count Register"]
    pub mod slv_data_cnt {
        #[doc = "Register `SlvDataCnt` reader"]
        pub type R = crate::R<SLV_DATA_CNT_SPEC>;
        #[doc = "Register `SlvDataCnt` writer"]
        pub type W = crate::W<SLV_DATA_CNT_SPEC>;
        #[doc = "Field `RCNT` reader - Slave received data count"]
        pub type RCNT_R = crate::FieldReader<u16>;
        #[doc = "Field `WCNT` reader - Slave transmitted data count"]
        pub type WCNT_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:9 - Slave received data count"]
            #[inline(always)]
            pub fn rcnt(&self) -> RCNT_R {
                RCNT_R::new((self.bits & 0x03ff) as u16)
            }
            #[doc = "Bits 16:25 - Slave transmitted data count"]
            #[inline(always)]
            pub fn wcnt(&self) -> WCNT_R {
                WCNT_R::new(((self.bits >> 16) & 0x03ff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Slave Data Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_data_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_data_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SLV_DATA_CNT_SPEC;
        impl crate::RegisterSpec for SLV_DATA_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`slv_data_cnt::R`](R) reader structure"]
        impl crate::Readable for SLV_DATA_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`slv_data_cnt::W`](W) writer structure"]
        impl crate::Writable for SLV_DATA_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SlvDataCnt to value 0"]
        impl crate::Resettable for SLV_DATA_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SlvDataWCnt (rw) register accessor: WCnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_data_wcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_data_wcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slv_data_wcnt`]
module"]
    pub type SLV_DATA_WCNT = crate::Reg<slv_data_wcnt::SLV_DATA_WCNT_SPEC>;
    #[doc = "WCnt"]
    pub mod slv_data_wcnt {
        #[doc = "Register `SlvDataWCnt` reader"]
        pub type R = crate::R<SLV_DATA_WCNT_SPEC>;
        #[doc = "Register `SlvDataWCnt` writer"]
        pub type W = crate::W<SLV_DATA_WCNT_SPEC>;
        #[doc = "Field `VAL` reader - No description avaiable"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "WCnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_data_wcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_data_wcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SLV_DATA_WCNT_SPEC;
        impl crate::RegisterSpec for SLV_DATA_WCNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`slv_data_wcnt::R`](R) reader structure"]
        impl crate::Readable for SLV_DATA_WCNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`slv_data_wcnt::W`](W) writer structure"]
        impl crate::Writable for SLV_DATA_WCNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SlvDataWCnt to value 0"]
        impl crate::Resettable for SLV_DATA_WCNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SlvDataRCnt (rw) register accessor: RCnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_data_rcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_data_rcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slv_data_rcnt`]
module"]
    pub type SLV_DATA_RCNT = crate::Reg<slv_data_rcnt::SLV_DATA_RCNT_SPEC>;
    #[doc = "RCnt"]
    pub mod slv_data_rcnt {
        #[doc = "Register `SlvDataRCnt` reader"]
        pub type R = crate::R<SLV_DATA_RCNT_SPEC>;
        #[doc = "Register `SlvDataRCnt` writer"]
        pub type W = crate::W<SLV_DATA_RCNT_SPEC>;
        #[doc = "Field `VAL` reader - No description avaiable"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "RCnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slv_data_rcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slv_data_rcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SLV_DATA_RCNT_SPEC;
        impl crate::RegisterSpec for SLV_DATA_RCNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`slv_data_rcnt::R`](R) reader structure"]
        impl crate::Readable for SLV_DATA_RCNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`slv_data_rcnt::W`](W) writer structure"]
        impl crate::Writable for SLV_DATA_RCNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SlvDataRCnt to value 0"]
        impl crate::Resettable for SLV_DATA_RCNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "Config (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`]
module"]
    pub type CONFIG = crate::Reg<config::CONFIG_SPEC>;
    #[doc = "Configuration Register"]
    pub mod config {
        #[doc = "Register `Config` reader"]
        pub type R = crate::R<CONFIG_SPEC>;
        #[doc = "Register `Config` writer"]
        pub type W = crate::W<CONFIG_SPEC>;
        #[doc = "Field `RXFIFOSIZE` reader - Depth of RX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words"]
        pub type RXFIFOSIZE_R = crate::FieldReader;
        #[doc = "Field `TXFIFOSIZE` reader - Depth of TX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words"]
        pub type TXFIFOSIZE_R = crate::FieldReader;
        #[doc = "Field `DUALSPI` reader - Support for Dual I/O SPI"]
        pub type DUALSPI_R = crate::BitReader;
        #[doc = "Field `QUADSPI` reader - Support for Quad I/O SPI"]
        pub type QUADSPI_R = crate::BitReader;
        #[doc = "Field `SLAVE` reader - Support for SPI Slave mode"]
        pub type SLAVE_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:3 - Depth of RX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words"]
            #[inline(always)]
            pub fn rxfifosize(&self) -> RXFIFOSIZE_R {
                RXFIFOSIZE_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:7 - Depth of TX FIFO 0x0: 2 words 0x1: 4 words 0x2: 8 words 0x3: 16 words 0x4: 32 words 0x5: 64 words 0x6: 128 words"]
            #[inline(always)]
            pub fn txfifosize(&self) -> TXFIFOSIZE_R {
                TXFIFOSIZE_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            #[doc = "Bit 8 - Support for Dual I/O SPI"]
            #[inline(always)]
            pub fn dualspi(&self) -> DUALSPI_R {
                DUALSPI_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Support for Quad I/O SPI"]
            #[inline(always)]
            pub fn quadspi(&self) -> QUADSPI_R {
                QUADSPI_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 14 - Support for SPI Slave mode"]
            #[inline(always)]
            pub fn slave(&self) -> SLAVE_R {
                SLAVE_R::new(((self.bits >> 14) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CONFIG_SPEC;
        impl crate::RegisterSpec for CONFIG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`config::R`](R) reader structure"]
        impl crate::Readable for CONFIG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"]
        impl crate::Writable for CONFIG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets Config to value 0x4311"]
        impl crate::Resettable for CONFIG_SPEC {
            const RESET_VALUE: u32 = 0x4311;
        }
    }
}
#[doc = "SPI1"]
pub struct SPI1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI1 {}
impl SPI1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const spi0::RegisterBlock = 0xf007_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const spi0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SPI1 {
    type Target = spi0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SPI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI1").finish()
    }
}
#[doc = "SPI1"]
pub use self::spi0 as spi1;
#[doc = "SPI2"]
pub struct SPI2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI2 {}
impl SPI2 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const spi0::RegisterBlock = 0xf007_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const spi0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SPI2 {
    type Target = spi0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SPI2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI2").finish()
    }
}
#[doc = "SPI2"]
pub use self::spi0 as spi2;
#[doc = "SPI3"]
pub struct SPI3 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SPI3 {}
impl SPI3 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const spi0::RegisterBlock = 0xf007_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const spi0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SPI3 {
    type Target = spi0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SPI3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SPI3").finish()
    }
}
#[doc = "SPI3"]
pub use self::spi0 as spi3;
#[doc = "CRC"]
pub struct CRC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for CRC {}
impl CRC {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const crc::RegisterBlock = 0xf008_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const crc::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for CRC {
    type Target = crc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for CRC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CRC").finish()
    }
}
#[doc = "CRC"]
pub mod crc {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        chn: (),
    }
    impl RegisterBlock {
        #[doc = "0x00..0x100 - no description available"]
        #[inline(always)]
        pub const fn chn(&self, n: usize) -> &CHN {
            #[allow(clippy::no_effect)]
            [(); 8][n];
            unsafe { &*(self as *const Self).cast::<u8>().add(0).add(64 * n).cast() }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x100 - no description available"]
        #[inline(always)]
        pub fn chn_iter(&self) -> impl Iterator<Item = &CHN> {
            (0..8).map(move |n| unsafe {
                &*(self as *const Self).cast::<u8>().add(0).add(64 * n).cast()
            })
        }
    }
    #[doc = "no description available"]
    pub use self::chn::CHN;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod chn {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct CHN {
            pre_set: PRE_SET,
            clr: CLR,
            poly: POLY,
            init_data: INIT_DATA,
            xorout: XOROUT,
            misc_setting: MISC_SETTING,
            data: DATA,
            result: RESULT,
        }
        impl CHN {
            #[doc = "0x00 - &amp;index0 pre set for crc setting"]
            #[inline(always)]
            pub const fn pre_set(&self) -> &PRE_SET {
                &self.pre_set
            }
            #[doc = "0x04 - chn&amp;index0 clear crc result and setting"]
            #[inline(always)]
            pub const fn clr(&self) -> &CLR {
                &self.clr
            }
            #[doc = "0x08 - chn&amp;index0 poly"]
            #[inline(always)]
            pub const fn poly(&self) -> &POLY {
                &self.poly
            }
            #[doc = "0x0c - chn&amp;index0 init_data"]
            #[inline(always)]
            pub const fn init_data(&self) -> &INIT_DATA {
                &self.init_data
            }
            #[doc = "0x10 - chn&amp;index0 xorout"]
            #[inline(always)]
            pub const fn xorout(&self) -> &XOROUT {
                &self.xorout
            }
            #[doc = "0x14 - chn&amp;index0 misc_setting"]
            #[inline(always)]
            pub const fn misc_setting(&self) -> &MISC_SETTING {
                &self.misc_setting
            }
            #[doc = "0x18 - chn&amp;index0 data"]
            #[inline(always)]
            pub const fn data(&self) -> &DATA {
                &self.data
            }
            #[doc = "0x1c - chn&amp;index0 result"]
            #[inline(always)]
            pub const fn result(&self) -> &RESULT {
                &self.result
            }
        }
        #[doc = "pre_set (rw) register accessor: &amp;index0 pre set for crc setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pre_set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pre_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pre_set`]
module"]
        pub type PRE_SET = crate::Reg<pre_set::PRE_SET_SPEC>;
        #[doc = "&amp;index0 pre set for crc setting"]
        pub mod pre_set {
            #[doc = "Register `pre_set` reader"]
            pub type R = crate::R<PRE_SET_SPEC>;
            #[doc = "Register `pre_set` writer"]
            pub type W = crate::W<PRE_SET_SPEC>;
            #[doc = "Field `PRE_SET` reader - 0: no pre set 1: CRC32 2: CRC32-AUTOSAR 3: CRC16-CCITT 4: CRC16-XMODEM 5: CRC16-MODBUS 1: CRC32 2: CRC32-autosar 3: CRC16-ccitt 4: CRC16-xmodem 5: CRC16-modbus 6: crc16_dnp 7: crc16_x25 8: crc16_usb 9: crc16_maxim 10: crc16_ibm 11: crc8_maxim 12: crc8_rohc 13: crc8_itu 14: crc8 15: crc5_usb"]
            pub type PRE_SET_R = crate::FieldReader;
            #[doc = "Field `PRE_SET` writer - 0: no pre set 1: CRC32 2: CRC32-AUTOSAR 3: CRC16-CCITT 4: CRC16-XMODEM 5: CRC16-MODBUS 1: CRC32 2: CRC32-autosar 3: CRC16-ccitt 4: CRC16-xmodem 5: CRC16-modbus 6: crc16_dnp 7: crc16_x25 8: crc16_usb 9: crc16_maxim 10: crc16_ibm 11: crc8_maxim 12: crc8_rohc 13: crc8_itu 14: crc8 15: crc5_usb"]
            pub type PRE_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bits 0:7 - 0: no pre set 1: CRC32 2: CRC32-AUTOSAR 3: CRC16-CCITT 4: CRC16-XMODEM 5: CRC16-MODBUS 1: CRC32 2: CRC32-autosar 3: CRC16-ccitt 4: CRC16-xmodem 5: CRC16-modbus 6: crc16_dnp 7: crc16_x25 8: crc16_usb 9: crc16_maxim 10: crc16_ibm 11: crc8_maxim 12: crc8_rohc 13: crc8_itu 14: crc8 15: crc5_usb"]
                #[inline(always)]
                pub fn pre_set(&self) -> PRE_SET_R {
                    PRE_SET_R::new((self.bits & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - 0: no pre set 1: CRC32 2: CRC32-AUTOSAR 3: CRC16-CCITT 4: CRC16-XMODEM 5: CRC16-MODBUS 1: CRC32 2: CRC32-autosar 3: CRC16-ccitt 4: CRC16-xmodem 5: CRC16-modbus 6: crc16_dnp 7: crc16_x25 8: crc16_usb 9: crc16_maxim 10: crc16_ibm 11: crc8_maxim 12: crc8_rohc 13: crc8_itu 14: crc8 15: crc5_usb"]
                #[inline(always)]
                #[must_use]
                pub fn pre_set(&mut self) -> PRE_SET_W<PRE_SET_SPEC> {
                    PRE_SET_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "&amp;index0 pre set for crc setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pre_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pre_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PRE_SET_SPEC;
            impl crate::RegisterSpec for PRE_SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pre_set::R`](R) reader structure"]
            impl crate::Readable for PRE_SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pre_set::W`](W) writer structure"]
            impl crate::Writable for PRE_SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets pre_set to value 0"]
            impl crate::Resettable for PRE_SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "clr (rw) register accessor: chn&amp;index0 clear crc result and setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr`]
module"]
        pub type CLR = crate::Reg<clr::CLR_SPEC>;
        #[doc = "chn&amp;index0 clear crc result and setting"]
        pub mod clr {
            #[doc = "Register `clr` reader"]
            pub type R = crate::R<CLR_SPEC>;
            #[doc = "Register `clr` writer"]
            pub type W = crate::W<CLR_SPEC>;
            #[doc = "Field `CLR` reader - write 1 to clr crc setting and result for its channel. always read 0."]
            pub type CLR_R = crate::BitReader;
            #[doc = "Field `CLR` writer - write 1 to clr crc setting and result for its channel. always read 0."]
            pub type CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - write 1 to clr crc setting and result for its channel. always read 0."]
                #[inline(always)]
                pub fn clr(&self) -> CLR_R {
                    CLR_R::new((self.bits & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - write 1 to clr crc setting and result for its channel. always read 0."]
                #[inline(always)]
                #[must_use]
                pub fn clr(&mut self) -> CLR_W<CLR_SPEC> {
                    CLR_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "chn&amp;index0 clear crc result and setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLR_SPEC;
            impl crate::RegisterSpec for CLR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clr::R`](R) reader structure"]
            impl crate::Readable for CLR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
            impl crate::Writable for CLR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets clr to value 0"]
            impl crate::Resettable for CLR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "poly (rw) register accessor: chn&amp;index0 poly\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`poly::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`poly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@poly`]
module"]
        pub type POLY = crate::Reg<poly::POLY_SPEC>;
        #[doc = "chn&amp;index0 poly"]
        pub mod poly {
            #[doc = "Register `poly` reader"]
            pub type R = crate::R<POLY_SPEC>;
            #[doc = "Register `poly` writer"]
            pub type W = crate::W<POLY_SPEC>;
            #[doc = "Field `POLY` reader - poly setting"]
            pub type POLY_R = crate::FieldReader<u32>;
            #[doc = "Field `POLY` writer - poly setting"]
            pub type POLY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - poly setting"]
                #[inline(always)]
                pub fn poly(&self) -> POLY_R {
                    POLY_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - poly setting"]
                #[inline(always)]
                #[must_use]
                pub fn poly(&mut self) -> POLY_W<POLY_SPEC> {
                    POLY_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "chn&amp;index0 poly\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`poly::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`poly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct POLY_SPEC;
            impl crate::RegisterSpec for POLY_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`poly::R`](R) reader structure"]
            impl crate::Readable for POLY_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`poly::W`](W) writer structure"]
            impl crate::Writable for POLY_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets poly to value 0"]
            impl crate::Resettable for POLY_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "init_data (rw) register accessor: chn&amp;index0 init_data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`init_data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`init_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@init_data`]
module"]
        pub type INIT_DATA = crate::Reg<init_data::INIT_DATA_SPEC>;
        #[doc = "chn&amp;index0 init_data"]
        pub mod init_data {
            #[doc = "Register `init_data` reader"]
            pub type R = crate::R<INIT_DATA_SPEC>;
            #[doc = "Register `init_data` writer"]
            pub type W = crate::W<INIT_DATA_SPEC>;
            #[doc = "Field `INIT_DATA` reader - initial data of CRC"]
            pub type INIT_DATA_R = crate::FieldReader<u32>;
            #[doc = "Field `INIT_DATA` writer - initial data of CRC"]
            pub type INIT_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - initial data of CRC"]
                #[inline(always)]
                pub fn init_data(&self) -> INIT_DATA_R {
                    INIT_DATA_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - initial data of CRC"]
                #[inline(always)]
                #[must_use]
                pub fn init_data(&mut self) -> INIT_DATA_W<INIT_DATA_SPEC> {
                    INIT_DATA_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "chn&amp;index0 init_data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`init_data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`init_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INIT_DATA_SPEC;
            impl crate::RegisterSpec for INIT_DATA_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`init_data::R`](R) reader structure"]
            impl crate::Readable for INIT_DATA_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`init_data::W`](W) writer structure"]
            impl crate::Writable for INIT_DATA_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets init_data to value 0"]
            impl crate::Resettable for INIT_DATA_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "xorout (rw) register accessor: chn&amp;index0 xorout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xorout::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xorout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xorout`]
module"]
        pub type XOROUT = crate::Reg<xorout::XOROUT_SPEC>;
        #[doc = "chn&amp;index0 xorout"]
        pub mod xorout {
            #[doc = "Register `xorout` reader"]
            pub type R = crate::R<XOROUT_SPEC>;
            #[doc = "Register `xorout` writer"]
            pub type W = crate::W<XOROUT_SPEC>;
            #[doc = "Field `XOROUT` reader - XOR for CRC result"]
            pub type XOROUT_R = crate::FieldReader<u32>;
            #[doc = "Field `XOROUT` writer - XOR for CRC result"]
            pub type XOROUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - XOR for CRC result"]
                #[inline(always)]
                pub fn xorout(&self) -> XOROUT_R {
                    XOROUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - XOR for CRC result"]
                #[inline(always)]
                #[must_use]
                pub fn xorout(&mut self) -> XOROUT_W<XOROUT_SPEC> {
                    XOROUT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "chn&amp;index0 xorout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xorout::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xorout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct XOROUT_SPEC;
            impl crate::RegisterSpec for XOROUT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`xorout::R`](R) reader structure"]
            impl crate::Readable for XOROUT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`xorout::W`](W) writer structure"]
            impl crate::Writable for XOROUT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets xorout to value 0"]
            impl crate::Resettable for XOROUT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "misc_setting (rw) register accessor: chn&amp;index0 misc_setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_setting::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_setting::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_setting`]
module"]
        pub type MISC_SETTING = crate::Reg<misc_setting::MISC_SETTING_SPEC>;
        #[doc = "chn&amp;index0 misc_setting"]
        pub mod misc_setting {
            #[doc = "Register `misc_setting` reader"]
            pub type R = crate::R<MISC_SETTING_SPEC>;
            #[doc = "Register `misc_setting` writer"]
            pub type W = crate::W<MISC_SETTING_SPEC>;
            #[doc = "Field `POLY_WIDTH` reader - crc data length"]
            pub type POLY_WIDTH_R = crate::FieldReader;
            #[doc = "Field `POLY_WIDTH` writer - crc data length"]
            pub type POLY_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
            #[doc = "Field `REV_IN` reader - 0: no wrap input bit order 1: wrap input bit order"]
            pub type REV_IN_R = crate::BitReader;
            #[doc = "Field `REV_IN` writer - 0: no wrap input bit order 1: wrap input bit order"]
            pub type REV_IN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `REV_OUT` reader - 0: no wrap output bit order 1: wrap output bit order"]
            pub type REV_OUT_R = crate::BitReader;
            #[doc = "Field `REV_OUT` writer - 0: no wrap output bit order 1: wrap output bit order"]
            pub type REV_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `BYTE_REV` reader - 0: no wrap input byte order 1: wrap input byte order"]
            pub type BYTE_REV_R = crate::BitReader;
            #[doc = "Field `BYTE_REV` writer - 0: no wrap input byte order 1: wrap input byte order"]
            pub type BYTE_REV_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:5 - crc data length"]
                #[inline(always)]
                pub fn poly_width(&self) -> POLY_WIDTH_R {
                    POLY_WIDTH_R::new((self.bits & 0x3f) as u8)
                }
                #[doc = "Bit 8 - 0: no wrap input bit order 1: wrap input bit order"]
                #[inline(always)]
                pub fn rev_in(&self) -> REV_IN_R {
                    REV_IN_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 16 - 0: no wrap output bit order 1: wrap output bit order"]
                #[inline(always)]
                pub fn rev_out(&self) -> REV_OUT_R {
                    REV_OUT_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 24 - 0: no wrap input byte order 1: wrap input byte order"]
                #[inline(always)]
                pub fn byte_rev(&self) -> BYTE_REV_R {
                    BYTE_REV_R::new(((self.bits >> 24) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:5 - crc data length"]
                #[inline(always)]
                #[must_use]
                pub fn poly_width(&mut self) -> POLY_WIDTH_W<MISC_SETTING_SPEC> {
                    POLY_WIDTH_W::new(self, 0)
                }
                #[doc = "Bit 8 - 0: no wrap input bit order 1: wrap input bit order"]
                #[inline(always)]
                #[must_use]
                pub fn rev_in(&mut self) -> REV_IN_W<MISC_SETTING_SPEC> {
                    REV_IN_W::new(self, 8)
                }
                #[doc = "Bit 16 - 0: no wrap output bit order 1: wrap output bit order"]
                #[inline(always)]
                #[must_use]
                pub fn rev_out(&mut self) -> REV_OUT_W<MISC_SETTING_SPEC> {
                    REV_OUT_W::new(self, 16)
                }
                #[doc = "Bit 24 - 0: no wrap input byte order 1: wrap input byte order"]
                #[inline(always)]
                #[must_use]
                pub fn byte_rev(&mut self) -> BYTE_REV_W<MISC_SETTING_SPEC> {
                    BYTE_REV_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "chn&amp;index0 misc_setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_setting::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_setting::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MISC_SETTING_SPEC;
            impl crate::RegisterSpec for MISC_SETTING_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`misc_setting::R`](R) reader structure"]
            impl crate::Readable for MISC_SETTING_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`misc_setting::W`](W) writer structure"]
            impl crate::Writable for MISC_SETTING_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets misc_setting to value 0"]
            impl crate::Resettable for MISC_SETTING_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "data (rw) register accessor: chn&amp;index0 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
        pub type DATA = crate::Reg<data::DATA_SPEC>;
        #[doc = "chn&amp;index0 data"]
        pub mod data {
            #[doc = "Register `data` reader"]
            pub type R = crate::R<DATA_SPEC>;
            #[doc = "Register `data` writer"]
            pub type W = crate::W<DATA_SPEC>;
            #[doc = "Field `DATA` reader - data for crc"]
            pub type DATA_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA` writer - data for crc"]
            pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - data for crc"]
                #[inline(always)]
                pub fn data(&self) -> DATA_R {
                    DATA_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - data for crc"]
                #[inline(always)]
                #[must_use]
                pub fn data(&mut self) -> DATA_W<DATA_SPEC> {
                    DATA_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "chn&amp;index0 data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct DATA_SPEC;
            impl crate::RegisterSpec for DATA_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`data::R`](R) reader structure"]
            impl crate::Readable for DATA_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
            impl crate::Writable for DATA_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets data to value 0"]
            impl crate::Resettable for DATA_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "result (rw) register accessor: chn&amp;index0 result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`result::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@result`]
module"]
        pub type RESULT = crate::Reg<result::RESULT_SPEC>;
        #[doc = "chn&amp;index0 result"]
        pub mod result {
            #[doc = "Register `result` reader"]
            pub type R = crate::R<RESULT_SPEC>;
            #[doc = "Register `result` writer"]
            pub type W = crate::W<RESULT_SPEC>;
            #[doc = "Field `RESULT` reader - crc result"]
            pub type RESULT_R = crate::FieldReader<u32>;
            #[doc = "Field `RESULT` writer - crc result"]
            pub type RESULT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - crc result"]
                #[inline(always)]
                pub fn result(&self) -> RESULT_R {
                    RESULT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - crc result"]
                #[inline(always)]
                #[must_use]
                pub fn result(&mut self) -> RESULT_W<RESULT_SPEC> {
                    RESULT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "chn&amp;index0 result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`result::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`result::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct RESULT_SPEC;
            impl crate::RegisterSpec for RESULT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`result::R`](R) reader structure"]
            impl crate::Readable for RESULT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`result::W`](W) writer structure"]
            impl crate::Writable for RESULT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets result to value 0"]
            impl crate::Resettable for RESULT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "TSNS"]
pub struct TSNS {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for TSNS {}
impl TSNS {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const tsns::RegisterBlock = 0xf009_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const tsns::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for TSNS {
    type Target = tsns::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for TSNS {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TSNS").finish()
    }
}
#[doc = "TSNS"]
pub mod tsns {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        t: T,
        tmax: TMAX,
        tmin: TMIN,
        age: AGE,
        status: STATUS,
        config: CONFIG,
        validity: VALIDITY,
        flag: FLAG,
        upper_lim_irq: UPPER_LIM_IRQ,
        lower_lim_irq: LOWER_LIM_IRQ,
        upper_lim_rst: UPPER_LIM_RST,
        lower_lim_rst: LOWER_LIM_RST,
        async_: ASYNC,
        _reserved13: [u8; 0x04],
        advan: ADVAN,
    }
    impl RegisterBlock {
        #[doc = "0x00 - Temperature"]
        #[inline(always)]
        pub const fn t(&self) -> &T {
            &self.t
        }
        #[doc = "0x04 - Maximum Temperature"]
        #[inline(always)]
        pub const fn tmax(&self) -> &TMAX {
            &self.tmax
        }
        #[doc = "0x08 - Minimum Temperature"]
        #[inline(always)]
        pub const fn tmin(&self) -> &TMIN {
            &self.tmin
        }
        #[doc = "0x0c - Sample age"]
        #[inline(always)]
        pub const fn age(&self) -> &AGE {
            &self.age
        }
        #[doc = "0x10 - Status"]
        #[inline(always)]
        pub const fn status(&self) -> &STATUS {
            &self.status
        }
        #[doc = "0x14 - Configuration"]
        #[inline(always)]
        pub const fn config(&self) -> &CONFIG {
            &self.config
        }
        #[doc = "0x18 - Sample validity"]
        #[inline(always)]
        pub const fn validity(&self) -> &VALIDITY {
            &self.validity
        }
        #[doc = "0x1c - Temperature flag"]
        #[inline(always)]
        pub const fn flag(&self) -> &FLAG {
            &self.flag
        }
        #[doc = "0x20 - Maximum temperature to interrupt"]
        #[inline(always)]
        pub const fn upper_lim_irq(&self) -> &UPPER_LIM_IRQ {
            &self.upper_lim_irq
        }
        #[doc = "0x24 - Minimum temperature to interrupt"]
        #[inline(always)]
        pub const fn lower_lim_irq(&self) -> &LOWER_LIM_IRQ {
            &self.lower_lim_irq
        }
        #[doc = "0x28 - Maximum temperature to reset"]
        #[inline(always)]
        pub const fn upper_lim_rst(&self) -> &UPPER_LIM_RST {
            &self.upper_lim_rst
        }
        #[doc = "0x2c - Minimum temperature to reset"]
        #[inline(always)]
        pub const fn lower_lim_rst(&self) -> &LOWER_LIM_RST {
            &self.lower_lim_rst
        }
        #[doc = "0x30 - Configuration in asynchronous mode"]
        #[inline(always)]
        pub const fn async_(&self) -> &ASYNC {
            &self.async_
        }
        #[doc = "0x38 - Advance configuration"]
        #[inline(always)]
        pub const fn advan(&self) -> &ADVAN {
            &self.advan
        }
    }
    #[doc = "T (rw) register accessor: Temperature\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@t`]
module"]
    pub type T = crate::Reg<t::T_SPEC>;
    #[doc = "Temperature"]
    pub mod t {
        #[doc = "Register `T` reader"]
        pub type R = crate::R<T_SPEC>;
        #[doc = "Register `T` writer"]
        pub type W = crate::W<T_SPEC>;
        #[doc = "Field `T` reader - Signed number of temperature in 256 x celsius degree"]
        pub type T_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Signed number of temperature in 256 x celsius degree"]
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Temperature\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`t::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`t::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct T_SPEC;
        impl crate::RegisterSpec for T_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`t::R`](R) reader structure"]
        impl crate::Readable for T_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`t::W`](W) writer structure"]
        impl crate::Writable for T_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets T to value 0"]
        impl crate::Resettable for T_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TMAX (rw) register accessor: Maximum Temperature\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmax::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmax::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmax`]
module"]
    pub type TMAX = crate::Reg<tmax::TMAX_SPEC>;
    #[doc = "Maximum Temperature"]
    pub mod tmax {
        #[doc = "Register `TMAX` reader"]
        pub type R = crate::R<TMAX_SPEC>;
        #[doc = "Register `TMAX` writer"]
        pub type W = crate::W<TMAX_SPEC>;
        #[doc = "Field `T` reader - maximum temperature ever found"]
        pub type T_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - maximum temperature ever found"]
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Maximum Temperature\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmax::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmax::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TMAX_SPEC;
        impl crate::RegisterSpec for TMAX_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tmax::R`](R) reader structure"]
        impl crate::Readable for TMAX_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tmax::W`](W) writer structure"]
        impl crate::Writable for TMAX_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TMAX to value 0xff80_0000"]
        impl crate::Resettable for TMAX_SPEC {
            const RESET_VALUE: u32 = 0xff80_0000;
        }
    }
    #[doc = "TMIN (rw) register accessor: Minimum Temperature\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmin::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmin::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmin`]
module"]
    pub type TMIN = crate::Reg<tmin::TMIN_SPEC>;
    #[doc = "Minimum Temperature"]
    pub mod tmin {
        #[doc = "Register `TMIN` reader"]
        pub type R = crate::R<TMIN_SPEC>;
        #[doc = "Register `TMIN` writer"]
        pub type W = crate::W<TMIN_SPEC>;
        #[doc = "Field `T` reader - minimum temperature ever found"]
        pub type T_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - minimum temperature ever found"]
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Minimum Temperature\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmin::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmin::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TMIN_SPEC;
        impl crate::RegisterSpec for TMIN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tmin::R`](R) reader structure"]
        impl crate::Readable for TMIN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tmin::W`](W) writer structure"]
        impl crate::Writable for TMIN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TMIN to value 0x007f_ffff"]
        impl crate::Resettable for TMIN_SPEC {
            const RESET_VALUE: u32 = 0x007f_ffff;
        }
    }
    #[doc = "AGE (rw) register accessor: Sample age\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`age::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`age::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@age`]
module"]
    pub type AGE = crate::Reg<age::AGE_SPEC>;
    #[doc = "Sample age"]
    pub mod age {
        #[doc = "Register `AGE` reader"]
        pub type R = crate::R<AGE_SPEC>;
        #[doc = "Register `AGE` writer"]
        pub type W = crate::W<AGE_SPEC>;
        #[doc = "Field `AGE` reader - age of T register in 24MHz clock cycles"]
        pub type AGE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - age of T register in 24MHz clock cycles"]
            #[inline(always)]
            pub fn age(&self) -> AGE_R {
                AGE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Sample age\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`age::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`age::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AGE_SPEC;
        impl crate::RegisterSpec for AGE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`age::R`](R) reader structure"]
        impl crate::Readable for AGE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`age::W`](W) writer structure"]
        impl crate::Writable for AGE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets AGE to value 0"]
        impl crate::Resettable for AGE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "STATUS (rw) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
    pub type STATUS = crate::Reg<status::STATUS_SPEC>;
    #[doc = "Status"]
    pub mod status {
        #[doc = "Register `STATUS` reader"]
        pub type R = crate::R<STATUS_SPEC>;
        #[doc = "Register `STATUS` writer"]
        pub type W = crate::W<STATUS_SPEC>;
        #[doc = "Field `TRIGGER` writer - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode"]
        pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VALID` reader - indicate value in T is valid or not 0: not valid 1:valid"]
        pub type VALID_R = crate::BitReader;
        impl R {
            #[doc = "Bit 31 - indicate value in T is valid or not 0: not valid 1:valid"]
            #[inline(always)]
            pub fn valid(&self) -> VALID_R {
                VALID_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode"]
            #[inline(always)]
            #[must_use]
            pub fn trigger(&mut self) -> TRIGGER_W<STATUS_SPEC> {
                TRIGGER_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STATUS_SPEC;
        impl crate::RegisterSpec for STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`status::R`](R) reader structure"]
        impl crate::Readable for STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
        impl crate::Writable for STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets STATUS to value 0"]
        impl crate::Resettable for STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CONFIG (rw) register accessor: Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`]
module"]
    pub type CONFIG = crate::Reg<config::CONFIG_SPEC>;
    #[doc = "Configuration"]
    pub mod config {
        #[doc = "Register `CONFIG` reader"]
        pub type R = crate::R<CONFIG_SPEC>;
        #[doc = "Register `CONFIG` writer"]
        pub type W = crate::W<CONFIG_SPEC>;
        #[doc = "Field `ENABLE` reader - Enable temperature 0: disable, temperature sensor is shut down 1: enable. Temperature sensor enabled"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `ENABLE` writer - Enable temperature 0: disable, temperature sensor is shut down 1: enable. Temperature sensor enabled"]
        pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASYNC` reader - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value 0: active mode 1: Async mode"]
        pub type ASYNC_R = crate::BitReader;
        #[doc = "Field `ASYNC` writer - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value 0: active mode 1: Async mode"]
        pub type ASYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONTINUOUS` reader - continuous mode that keep sampling temperature peridically 0: trigger mode 1: continuous mode"]
        pub type CONTINUOUS_R = crate::BitReader;
        #[doc = "Field `CONTINUOUS` writer - continuous mode that keep sampling temperature peridically 0: trigger mode 1: continuous mode"]
        pub type CONTINUOUS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AVERAGE` reader - Average time, default in 3 0: measure and return 1: twice and average 2: 4 times and average . . . 7: 128 times and average"]
        pub type AVERAGE_R = crate::FieldReader;
        #[doc = "Field `AVERAGE` writer - Average time, default in 3 0: measure and return 1: twice and average 2: 4 times and average . . . 7: 128 times and average"]
        pub type AVERAGE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `SPEED` reader - cycles of a progressive step in 24M clock, valide from 24-255, default 96 24: 24 cycle for a step 25: 25 cycle for a step 26: 26 cycle for a step ... 255: 255 cycle for a step"]
        pub type SPEED_R = crate::FieldReader;
        #[doc = "Field `SPEED` writer - cycles of a progressive step in 24M clock, valide from 24-255, default 96 24: 24 cycle for a step 25: 25 cycle for a step 26: 26 cycle for a step ... 255: 255 cycle for a step"]
        pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `COMPARE_MAX_EN` reader - Enable compare for maximum temperature"]
        pub type COMPARE_MAX_EN_R = crate::BitReader;
        #[doc = "Field `COMPARE_MAX_EN` writer - Enable compare for maximum temperature"]
        pub type COMPARE_MAX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COMPARE_MIN_EN` reader - Enable compare for minimum temperature"]
        pub type COMPARE_MIN_EN_R = crate::BitReader;
        #[doc = "Field `COMPARE_MIN_EN` writer - Enable compare for minimum temperature"]
        pub type COMPARE_MIN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RST_EN` reader - Enable reset"]
        pub type RST_EN_R = crate::BitReader;
        #[doc = "Field `RST_EN` writer - Enable reset"]
        pub type RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IRQ_EN` reader - Enable interrupt"]
        pub type IRQ_EN_R = crate::BitReader;
        #[doc = "Field `IRQ_EN` writer - Enable interrupt"]
        pub type IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Enable temperature 0: disable, temperature sensor is shut down 1: enable. Temperature sensor enabled"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value 0: active mode 1: Async mode"]
            #[inline(always)]
            pub fn async_(&self) -> ASYNC_R {
                ASYNC_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 4 - continuous mode that keep sampling temperature peridically 0: trigger mode 1: continuous mode"]
            #[inline(always)]
            pub fn continuous(&self) -> CONTINUOUS_R {
                CONTINUOUS_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bits 8:10 - Average time, default in 3 0: measure and return 1: twice and average 2: 4 times and average . . . 7: 128 times and average"]
            #[inline(always)]
            pub fn average(&self) -> AVERAGE_R {
                AVERAGE_R::new(((self.bits >> 8) & 7) as u8)
            }
            #[doc = "Bits 16:23 - cycles of a progressive step in 24M clock, valide from 24-255, default 96 24: 24 cycle for a step 25: 25 cycle for a step 26: 26 cycle for a step ... 255: 255 cycle for a step"]
            #[inline(always)]
            pub fn speed(&self) -> SPEED_R {
                SPEED_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bit 24 - Enable compare for maximum temperature"]
            #[inline(always)]
            pub fn compare_max_en(&self) -> COMPARE_MAX_EN_R {
                COMPARE_MAX_EN_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Enable compare for minimum temperature"]
            #[inline(always)]
            pub fn compare_min_en(&self) -> COMPARE_MIN_EN_R {
                COMPARE_MIN_EN_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 30 - Enable reset"]
            #[inline(always)]
            pub fn rst_en(&self) -> RST_EN_R {
                RST_EN_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - Enable interrupt"]
            #[inline(always)]
            pub fn irq_en(&self) -> IRQ_EN_R {
                IRQ_EN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable temperature 0: disable, temperature sensor is shut down 1: enable. Temperature sensor enabled"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<CONFIG_SPEC> {
                ENABLE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value 0: active mode 1: Async mode"]
            #[inline(always)]
            #[must_use]
            pub fn async_(&mut self) -> ASYNC_W<CONFIG_SPEC> {
                ASYNC_W::new(self, 1)
            }
            #[doc = "Bit 4 - continuous mode that keep sampling temperature peridically 0: trigger mode 1: continuous mode"]
            #[inline(always)]
            #[must_use]
            pub fn continuous(&mut self) -> CONTINUOUS_W<CONFIG_SPEC> {
                CONTINUOUS_W::new(self, 4)
            }
            #[doc = "Bits 8:10 - Average time, default in 3 0: measure and return 1: twice and average 2: 4 times and average . . . 7: 128 times and average"]
            #[inline(always)]
            #[must_use]
            pub fn average(&mut self) -> AVERAGE_W<CONFIG_SPEC> {
                AVERAGE_W::new(self, 8)
            }
            #[doc = "Bits 16:23 - cycles of a progressive step in 24M clock, valide from 24-255, default 96 24: 24 cycle for a step 25: 25 cycle for a step 26: 26 cycle for a step ... 255: 255 cycle for a step"]
            #[inline(always)]
            #[must_use]
            pub fn speed(&mut self) -> SPEED_W<CONFIG_SPEC> {
                SPEED_W::new(self, 16)
            }
            #[doc = "Bit 24 - Enable compare for maximum temperature"]
            #[inline(always)]
            #[must_use]
            pub fn compare_max_en(&mut self) -> COMPARE_MAX_EN_W<CONFIG_SPEC> {
                COMPARE_MAX_EN_W::new(self, 24)
            }
            #[doc = "Bit 25 - Enable compare for minimum temperature"]
            #[inline(always)]
            #[must_use]
            pub fn compare_min_en(&mut self) -> COMPARE_MIN_EN_W<CONFIG_SPEC> {
                COMPARE_MIN_EN_W::new(self, 25)
            }
            #[doc = "Bit 30 - Enable reset"]
            #[inline(always)]
            #[must_use]
            pub fn rst_en(&mut self) -> RST_EN_W<CONFIG_SPEC> {
                RST_EN_W::new(self, 30)
            }
            #[doc = "Bit 31 - Enable interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn irq_en(&mut self) -> IRQ_EN_W<CONFIG_SPEC> {
                IRQ_EN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CONFIG_SPEC;
        impl crate::RegisterSpec for CONFIG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`config::R`](R) reader structure"]
        impl crate::Readable for CONFIG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"]
        impl crate::Writable for CONFIG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CONFIG to value 0x0060_0300"]
        impl crate::Resettable for CONFIG_SPEC {
            const RESET_VALUE: u32 = 0x0060_0300;
        }
    }
    #[doc = "VALIDITY (rw) register accessor: Sample validity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`validity::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`validity::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@validity`]
module"]
    pub type VALIDITY = crate::Reg<validity::VALIDITY_SPEC>;
    #[doc = "Sample validity"]
    pub mod validity {
        #[doc = "Register `VALIDITY` reader"]
        pub type R = crate::R<VALIDITY_SPEC>;
        #[doc = "Register `VALIDITY` writer"]
        pub type W = crate::W<VALIDITY_SPEC>;
        #[doc = "Field `VALIDITY` reader - time for temperature values to expire in 24M clock cycles"]
        pub type VALIDITY_R = crate::FieldReader<u32>;
        #[doc = "Field `VALIDITY` writer - time for temperature values to expire in 24M clock cycles"]
        pub type VALIDITY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - time for temperature values to expire in 24M clock cycles"]
            #[inline(always)]
            pub fn validity(&self) -> VALIDITY_R {
                VALIDITY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - time for temperature values to expire in 24M clock cycles"]
            #[inline(always)]
            #[must_use]
            pub fn validity(&mut self) -> VALIDITY_W<VALIDITY_SPEC> {
                VALIDITY_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Sample validity\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`validity::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`validity::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct VALIDITY_SPEC;
        impl crate::RegisterSpec for VALIDITY_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`validity::R`](R) reader structure"]
        impl crate::Readable for VALIDITY_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`validity::W`](W) writer structure"]
        impl crate::Writable for VALIDITY_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets VALIDITY to value 0x016e_3600"]
        impl crate::Resettable for VALIDITY_SPEC {
            const RESET_VALUE: u32 = 0x016e_3600;
        }
    }
    #[doc = "FLAG (rw) register accessor: Temperature flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flag::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flag::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flag`]
module"]
    pub type FLAG = crate::Reg<flag::FLAG_SPEC>;
    #[doc = "Temperature flag"]
    pub mod flag {
        #[doc = "Register `FLAG` reader"]
        pub type R = crate::R<FLAG_SPEC>;
        #[doc = "Register `FLAG` writer"]
        pub type W = crate::W<FLAG_SPEC>;
        #[doc = "Field `IRQ` reader - IRQ flag, write 1 to clear"]
        pub type IRQ_R = crate::BitReader;
        #[doc = "Field `IRQ` writer - IRQ flag, write 1 to clear"]
        pub type IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OVER_TEMP` reader - Clear over temperature status, write 1 to clear"]
        pub type OVER_TEMP_R = crate::BitReader;
        #[doc = "Field `OVER_TEMP` writer - Clear over temperature status, write 1 to clear"]
        pub type OVER_TEMP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UNDER_TEMP` reader - Clear under temperature status, write 1 to clear"]
        pub type UNDER_TEMP_R = crate::BitReader;
        #[doc = "Field `UNDER_TEMP` writer - Clear under temperature status, write 1 to clear"]
        pub type UNDER_TEMP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RECORD_MAX_CLR` reader - Clear maximum recorder of temerature, write 1 to clear"]
        pub type RECORD_MAX_CLR_R = crate::BitReader;
        #[doc = "Field `RECORD_MAX_CLR` writer - Clear maximum recorder of temerature, write 1 to clear"]
        pub type RECORD_MAX_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RECORD_MIN_CLR` reader - Clear minimum recorder of temerature, write 1 to clear"]
        pub type RECORD_MIN_CLR_R = crate::BitReader;
        #[doc = "Field `RECORD_MIN_CLR` writer - Clear minimum recorder of temerature, write 1 to clear"]
        pub type RECORD_MIN_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - IRQ flag, write 1 to clear"]
            #[inline(always)]
            pub fn irq(&self) -> IRQ_R {
                IRQ_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 16 - Clear over temperature status, write 1 to clear"]
            #[inline(always)]
            pub fn over_temp(&self) -> OVER_TEMP_R {
                OVER_TEMP_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - Clear under temperature status, write 1 to clear"]
            #[inline(always)]
            pub fn under_temp(&self) -> UNDER_TEMP_R {
                UNDER_TEMP_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 20 - Clear maximum recorder of temerature, write 1 to clear"]
            #[inline(always)]
            pub fn record_max_clr(&self) -> RECORD_MAX_CLR_R {
                RECORD_MAX_CLR_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Clear minimum recorder of temerature, write 1 to clear"]
            #[inline(always)]
            pub fn record_min_clr(&self) -> RECORD_MIN_CLR_R {
                RECORD_MIN_CLR_R::new(((self.bits >> 21) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - IRQ flag, write 1 to clear"]
            #[inline(always)]
            #[must_use]
            pub fn irq(&mut self) -> IRQ_W<FLAG_SPEC> {
                IRQ_W::new(self, 0)
            }
            #[doc = "Bit 16 - Clear over temperature status, write 1 to clear"]
            #[inline(always)]
            #[must_use]
            pub fn over_temp(&mut self) -> OVER_TEMP_W<FLAG_SPEC> {
                OVER_TEMP_W::new(self, 16)
            }
            #[doc = "Bit 17 - Clear under temperature status, write 1 to clear"]
            #[inline(always)]
            #[must_use]
            pub fn under_temp(&mut self) -> UNDER_TEMP_W<FLAG_SPEC> {
                UNDER_TEMP_W::new(self, 17)
            }
            #[doc = "Bit 20 - Clear maximum recorder of temerature, write 1 to clear"]
            #[inline(always)]
            #[must_use]
            pub fn record_max_clr(&mut self) -> RECORD_MAX_CLR_W<FLAG_SPEC> {
                RECORD_MAX_CLR_W::new(self, 20)
            }
            #[doc = "Bit 21 - Clear minimum recorder of temerature, write 1 to clear"]
            #[inline(always)]
            #[must_use]
            pub fn record_min_clr(&mut self) -> RECORD_MIN_CLR_W<FLAG_SPEC> {
                RECORD_MIN_CLR_W::new(self, 21)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Temperature flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flag::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FLAG_SPEC;
        impl crate::RegisterSpec for FLAG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`flag::R`](R) reader structure"]
        impl crate::Readable for FLAG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`flag::W`](W) writer structure"]
        impl crate::Writable for FLAG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FLAG to value 0"]
        impl crate::Resettable for FLAG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "UPPER_LIM_IRQ (rw) register accessor: Maximum temperature to interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upper_lim_irq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upper_lim_irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upper_lim_irq`]
module"]
    pub type UPPER_LIM_IRQ = crate::Reg<upper_lim_irq::UPPER_LIM_IRQ_SPEC>;
    #[doc = "Maximum temperature to interrupt"]
    pub mod upper_lim_irq {
        #[doc = "Register `UPPER_LIM_IRQ` reader"]
        pub type R = crate::R<UPPER_LIM_IRQ_SPEC>;
        #[doc = "Register `UPPER_LIM_IRQ` writer"]
        pub type W = crate::W<UPPER_LIM_IRQ_SPEC>;
        #[doc = "Field `T` reader - Maximum temperature for compare"]
        pub type T_R = crate::FieldReader<u32>;
        #[doc = "Field `T` writer - Maximum temperature for compare"]
        pub type T_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Maximum temperature for compare"]
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Maximum temperature for compare"]
            #[inline(always)]
            #[must_use]
            pub fn t(&mut self) -> T_W<UPPER_LIM_IRQ_SPEC> {
                T_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Maximum temperature to interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upper_lim_irq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upper_lim_irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UPPER_LIM_IRQ_SPEC;
        impl crate::RegisterSpec for UPPER_LIM_IRQ_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`upper_lim_irq::R`](R) reader structure"]
        impl crate::Readable for UPPER_LIM_IRQ_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`upper_lim_irq::W`](W) writer structure"]
        impl crate::Writable for UPPER_LIM_IRQ_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets UPPER_LIM_IRQ to value 0"]
        impl crate::Resettable for UPPER_LIM_IRQ_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "LOWER_LIM_IRQ (rw) register accessor: Minimum temperature to interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lower_lim_irq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lower_lim_irq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lower_lim_irq`]
module"]
    pub type LOWER_LIM_IRQ = crate::Reg<lower_lim_irq::LOWER_LIM_IRQ_SPEC>;
    #[doc = "Minimum temperature to interrupt"]
    pub mod lower_lim_irq {
        #[doc = "Register `LOWER_LIM_IRQ` reader"]
        pub type R = crate::R<LOWER_LIM_IRQ_SPEC>;
        #[doc = "Register `LOWER_LIM_IRQ` writer"]
        pub type W = crate::W<LOWER_LIM_IRQ_SPEC>;
        #[doc = "Field `T` reader - Minimum temperature for compare"]
        pub type T_R = crate::FieldReader<u32>;
        #[doc = "Field `T` writer - Minimum temperature for compare"]
        pub type T_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Minimum temperature for compare"]
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Minimum temperature for compare"]
            #[inline(always)]
            #[must_use]
            pub fn t(&mut self) -> T_W<LOWER_LIM_IRQ_SPEC> {
                T_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Minimum temperature to interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lower_lim_irq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lower_lim_irq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LOWER_LIM_IRQ_SPEC;
        impl crate::RegisterSpec for LOWER_LIM_IRQ_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`lower_lim_irq::R`](R) reader structure"]
        impl crate::Readable for LOWER_LIM_IRQ_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`lower_lim_irq::W`](W) writer structure"]
        impl crate::Writable for LOWER_LIM_IRQ_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LOWER_LIM_IRQ to value 0"]
        impl crate::Resettable for LOWER_LIM_IRQ_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "UPPER_LIM_RST (rw) register accessor: Maximum temperature to reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upper_lim_rst::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upper_lim_rst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upper_lim_rst`]
module"]
    pub type UPPER_LIM_RST = crate::Reg<upper_lim_rst::UPPER_LIM_RST_SPEC>;
    #[doc = "Maximum temperature to reset"]
    pub mod upper_lim_rst {
        #[doc = "Register `UPPER_LIM_RST` reader"]
        pub type R = crate::R<UPPER_LIM_RST_SPEC>;
        #[doc = "Register `UPPER_LIM_RST` writer"]
        pub type W = crate::W<UPPER_LIM_RST_SPEC>;
        #[doc = "Field `T` reader - Maximum temperature for compare"]
        pub type T_R = crate::FieldReader<u32>;
        #[doc = "Field `T` writer - Maximum temperature for compare"]
        pub type T_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Maximum temperature for compare"]
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Maximum temperature for compare"]
            #[inline(always)]
            #[must_use]
            pub fn t(&mut self) -> T_W<UPPER_LIM_RST_SPEC> {
                T_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Maximum temperature to reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upper_lim_rst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upper_lim_rst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UPPER_LIM_RST_SPEC;
        impl crate::RegisterSpec for UPPER_LIM_RST_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`upper_lim_rst::R`](R) reader structure"]
        impl crate::Readable for UPPER_LIM_RST_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`upper_lim_rst::W`](W) writer structure"]
        impl crate::Writable for UPPER_LIM_RST_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets UPPER_LIM_RST to value 0"]
        impl crate::Resettable for UPPER_LIM_RST_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "LOWER_LIM_RST (rw) register accessor: Minimum temperature to reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lower_lim_rst::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lower_lim_rst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lower_lim_rst`]
module"]
    pub type LOWER_LIM_RST = crate::Reg<lower_lim_rst::LOWER_LIM_RST_SPEC>;
    #[doc = "Minimum temperature to reset"]
    pub mod lower_lim_rst {
        #[doc = "Register `LOWER_LIM_RST` reader"]
        pub type R = crate::R<LOWER_LIM_RST_SPEC>;
        #[doc = "Register `LOWER_LIM_RST` writer"]
        pub type W = crate::W<LOWER_LIM_RST_SPEC>;
        #[doc = "Field `T` reader - Minimum temperature for compare"]
        pub type T_R = crate::FieldReader<u32>;
        #[doc = "Field `T` writer - Minimum temperature for compare"]
        pub type T_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Minimum temperature for compare"]
            #[inline(always)]
            pub fn t(&self) -> T_R {
                T_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Minimum temperature for compare"]
            #[inline(always)]
            #[must_use]
            pub fn t(&mut self) -> T_W<LOWER_LIM_RST_SPEC> {
                T_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Minimum temperature to reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lower_lim_rst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lower_lim_rst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LOWER_LIM_RST_SPEC;
        impl crate::RegisterSpec for LOWER_LIM_RST_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`lower_lim_rst::R`](R) reader structure"]
        impl crate::Readable for LOWER_LIM_RST_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`lower_lim_rst::W`](W) writer structure"]
        impl crate::Writable for LOWER_LIM_RST_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LOWER_LIM_RST to value 0"]
        impl crate::Resettable for LOWER_LIM_RST_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ASYNC (rw) register accessor: Configuration in asynchronous mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`async_::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`async_::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@async_`]
module"]
    pub type ASYNC = crate::Reg<async_::ASYNC_SPEC>;
    #[doc = "Configuration in asynchronous mode"]
    pub mod async_ {
        #[doc = "Register `ASYNC` reader"]
        pub type R = crate::R<ASYNC_SPEC>;
        #[doc = "Register `ASYNC` writer"]
        pub type W = crate::W<ASYNC_SPEC>;
        #[doc = "Field `VALUE` reader - Value of async mode to compare"]
        pub type VALUE_R = crate::FieldReader<u16>;
        #[doc = "Field `VALUE` writer - Value of async mode to compare"]
        pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
        #[doc = "Field `POLARITY` reader - Polarity of internal comparator"]
        pub type POLARITY_R = crate::BitReader;
        #[doc = "Field `POLARITY` writer - Polarity of internal comparator"]
        pub type POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASYNC_TYPE` reader - Compare hotter than or colder than in asynchoronous mode 0: hotter than 1: colder than"]
        pub type ASYNC_TYPE_R = crate::BitReader;
        #[doc = "Field `ASYNC_TYPE` writer - Compare hotter than or colder than in asynchoronous mode 0: hotter than 1: colder than"]
        pub type ASYNC_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:10 - Value of async mode to compare"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new((self.bits & 0x07ff) as u16)
            }
            #[doc = "Bit 16 - Polarity of internal comparator"]
            #[inline(always)]
            pub fn polarity(&self) -> POLARITY_R {
                POLARITY_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 24 - Compare hotter than or colder than in asynchoronous mode 0: hotter than 1: colder than"]
            #[inline(always)]
            pub fn async_type(&self) -> ASYNC_TYPE_R {
                ASYNC_TYPE_R::new(((self.bits >> 24) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:10 - Value of async mode to compare"]
            #[inline(always)]
            #[must_use]
            pub fn value(&mut self) -> VALUE_W<ASYNC_SPEC> {
                VALUE_W::new(self, 0)
            }
            #[doc = "Bit 16 - Polarity of internal comparator"]
            #[inline(always)]
            #[must_use]
            pub fn polarity(&mut self) -> POLARITY_W<ASYNC_SPEC> {
                POLARITY_W::new(self, 16)
            }
            #[doc = "Bit 24 - Compare hotter than or colder than in asynchoronous mode 0: hotter than 1: colder than"]
            #[inline(always)]
            #[must_use]
            pub fn async_type(&mut self) -> ASYNC_TYPE_W<ASYNC_SPEC> {
                ASYNC_TYPE_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Configuration in asynchronous mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`async_::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`async_::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ASYNC_SPEC;
        impl crate::RegisterSpec for ASYNC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`async_::R`](R) reader structure"]
        impl crate::Readable for ASYNC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`async_::W`](W) writer structure"]
        impl crate::Writable for ASYNC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ASYNC to value 0"]
        impl crate::Resettable for ASYNC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ADVAN (rw) register accessor: Advance configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`advan::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`advan::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@advan`]
module"]
    pub type ADVAN = crate::Reg<advan::ADVAN_SPEC>;
    #[doc = "Advance configuration"]
    pub mod advan {
        #[doc = "Register `ADVAN` reader"]
        pub type R = crate::R<ADVAN_SPEC>;
        #[doc = "Register `ADVAN` writer"]
        pub type W = crate::W<ADVAN_SPEC>;
        #[doc = "Field `POS_ONLY` reader - use positive compare polarity only"]
        pub type POS_ONLY_R = crate::BitReader;
        #[doc = "Field `POS_ONLY` writer - use positive compare polarity only"]
        pub type POS_ONLY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NEG_ONLY` reader - use negative compare polarity only"]
        pub type NEG_ONLY_R = crate::BitReader;
        #[doc = "Field `NEG_ONLY` writer - use negative compare polarity only"]
        pub type NEG_ONLY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLING` reader - temperature sampling is working"]
        pub type SAMPLING_R = crate::BitReader;
        #[doc = "Field `ACTIVE_IRQ` reader - interrupt status of active mode"]
        pub type ACTIVE_IRQ_R = crate::BitReader;
        #[doc = "Field `ASYNC_IRQ` reader - interrupt status of asynchronous mode"]
        pub type ASYNC_IRQ_R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - use positive compare polarity only"]
            #[inline(always)]
            pub fn pos_only(&self) -> POS_ONLY_R {
                POS_ONLY_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - use negative compare polarity only"]
            #[inline(always)]
            pub fn neg_only(&self) -> NEG_ONLY_R {
                NEG_ONLY_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 16 - temperature sampling is working"]
            #[inline(always)]
            pub fn sampling(&self) -> SAMPLING_R {
                SAMPLING_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 24 - interrupt status of active mode"]
            #[inline(always)]
            pub fn active_irq(&self) -> ACTIVE_IRQ_R {
                ACTIVE_IRQ_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - interrupt status of asynchronous mode"]
            #[inline(always)]
            pub fn async_irq(&self) -> ASYNC_IRQ_R {
                ASYNC_IRQ_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - use positive compare polarity only"]
            #[inline(always)]
            #[must_use]
            pub fn pos_only(&mut self) -> POS_ONLY_W<ADVAN_SPEC> {
                POS_ONLY_W::new(self, 0)
            }
            #[doc = "Bit 1 - use negative compare polarity only"]
            #[inline(always)]
            #[must_use]
            pub fn neg_only(&mut self) -> NEG_ONLY_W<ADVAN_SPEC> {
                NEG_ONLY_W::new(self, 1)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Advance configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`advan::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`advan::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADVAN_SPEC;
        impl crate::RegisterSpec for ADVAN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`advan::R`](R) reader structure"]
        impl crate::Readable for ADVAN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`advan::W`](W) writer structure"]
        impl crate::Writable for ADVAN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ADVAN to value 0"]
        impl crate::Resettable for ADVAN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "MBX0A"]
pub struct MBX0A {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MBX0A {}
impl MBX0A {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mbx0a::RegisterBlock = 0xf00a_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mbx0a::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MBX0A {
    type Target = mbx0a::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MBX0A {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MBX0A").finish()
    }
}
#[doc = "MBX0A"]
pub mod mbx0a {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        cr: CR,
        sr: SR,
        txreg: TXREG,
        rxreg: RXREG,
        txwrd: [TXWRD; 1],
        _reserved5: [u8; 0x0c],
        rxwrd: [RXWRD; 1],
    }
    impl RegisterBlock {
        #[doc = "0x00 - Command Registers"]
        #[inline(always)]
        pub const fn cr(&self) -> &CR {
            &self.cr
        }
        #[doc = "0x04 - Status Registers"]
        #[inline(always)]
        pub const fn sr(&self) -> &SR {
            &self.sr
        }
        #[doc = "0x08 - Transmit word message to other core."]
        #[inline(always)]
        pub const fn txreg(&self) -> &TXREG {
            &self.txreg
        }
        #[doc = "0x0c - Receive word message from other core."]
        #[inline(always)]
        pub const fn rxreg(&self) -> &RXREG {
            &self.rxreg
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn txwrd(&self, n: usize) -> &TXWRD {
            &self.txwrd[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub fn txwrd_iter(&self) -> impl Iterator<Item = &TXWRD> {
            self.txwrd.iter()
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn txwrdtxfifo0(&self) -> &TXWRD {
            self.txwrd(0)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn rxwrd(&self, n: usize) -> &RXWRD {
            &self.rxwrd[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub fn rxwrd_iter(&self) -> impl Iterator<Item = &RXWRD> {
            self.rxwrd.iter()
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn rxwrdrxfifo0(&self) -> &RXWRD {
            self.rxwrd(0)
        }
    }
    #[doc = "CR (rw) register accessor: Command Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
    pub type CR = crate::Reg<cr::CR_SPEC>;
    #[doc = "Command Registers"]
    pub mod cr {
        #[doc = "Register `CR` reader"]
        pub type R = crate::R<CR_SPEC>;
        #[doc = "Register `CR` writer"]
        pub type W = crate::W<CR_SPEC>;
        #[doc = "Field `RWMVIE` reader - RX word message valid interrupt enable. 1, enable the RX word massage valid interrupt. 0, disable the RX word message valid interrupt."]
        pub type RWMVIE_R = crate::BitReader;
        #[doc = "Field `RWMVIE` writer - RX word message valid interrupt enable. 1, enable the RX word massage valid interrupt. 0, disable the RX word message valid interrupt."]
        pub type RWMVIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TWMEIE` reader - TX word message empty interrupt enable. 1, enable the TX word massage empty interrupt. 0, disable the TX word message empty interrupt."]
        pub type TWMEIE_R = crate::BitReader;
        #[doc = "Field `TWMEIE` writer - TX word message empty interrupt enable. 1, enable the TX word massage empty interrupt. 0, disable the TX word message empty interrupt."]
        pub type TWMEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RFMFIE` reader - RX fifo message full interrupt enable. 1, enable the RX fifo message full interrupt. 0, disable the RX fifo message full interrupt."]
        pub type RFMFIE_R = crate::BitReader;
        #[doc = "Field `RFMFIE` writer - RX fifo message full interrupt enable. 1, enable the RX fifo message full interrupt. 0, disable the RX fifo message full interrupt."]
        pub type RFMFIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RFMAIE` reader - RX FIFO message available interrupt enable. 1, enable the RX FIFO massage available interrupt. 0, disable the RX FIFO message available interrupt."]
        pub type RFMAIE_R = crate::BitReader;
        #[doc = "Field `RFMAIE` writer - RX FIFO message available interrupt enable. 1, enable the RX FIFO massage available interrupt. 0, disable the RX FIFO message available interrupt."]
        pub type RFMAIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFMEIE` reader - TX FIFO message empty interrupt enable. 1, enable the TX FIFO massage empty interrupt. 0, disable the TX FIFO message empty interrupt."]
        pub type TFMEIE_R = crate::BitReader;
        #[doc = "Field `TFMEIE` writer - TX FIFO message empty interrupt enable. 1, enable the TX FIFO massage empty interrupt. 0, disable the TX FIFO message empty interrupt."]
        pub type TFMEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFMAIE` reader - TX FIFO message available interrupt enable. 1, enable the TX FIFO massage available interrupt. 0, disable the TX FIFO message available interrupt."]
        pub type TFMAIE_R = crate::BitReader;
        #[doc = "Field `TFMAIE` writer - TX FIFO message available interrupt enable. 1, enable the TX FIFO massage available interrupt. 0, disable the TX FIFO message available interrupt."]
        pub type TFMAIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BEIE` reader - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. 1, enable the bus access error interrupt. 0, disable the bus access error interrupt."]
        pub type BEIE_R = crate::BitReader;
        #[doc = "Field `BEIE` writer - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. 1, enable the bus access error interrupt. 0, disable the bus access error interrupt."]
        pub type BEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BARCTL` reader - Bus Acccess Response Control, when bit 15:14= 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. 11: reserved."]
        pub type BARCTL_R = crate::FieldReader;
        #[doc = "Field `BARCTL` writer - Bus Acccess Response Control, when bit 15:14= 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. 11: reserved."]
        pub type BARCTL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TXRESET` reader - Reset TX Fifo and word."]
        pub type TXRESET_R = crate::BitReader;
        #[doc = "Field `TXRESET` writer - Reset TX Fifo and word."]
        pub type TXRESET_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - RX word message valid interrupt enable. 1, enable the RX word massage valid interrupt. 0, disable the RX word message valid interrupt."]
            #[inline(always)]
            pub fn rwmvie(&self) -> RWMVIE_R {
                RWMVIE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX word message empty interrupt enable. 1, enable the TX word massage empty interrupt. 0, disable the TX word message empty interrupt."]
            #[inline(always)]
            pub fn twmeie(&self) -> TWMEIE_R {
                TWMEIE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 4 - RX fifo message full interrupt enable. 1, enable the RX fifo message full interrupt. 0, disable the RX fifo message full interrupt."]
            #[inline(always)]
            pub fn rfmfie(&self) -> RFMFIE_R {
                RFMFIE_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - RX FIFO message available interrupt enable. 1, enable the RX FIFO massage available interrupt. 0, disable the RX FIFO message available interrupt."]
            #[inline(always)]
            pub fn rfmaie(&self) -> RFMAIE_R {
                RFMAIE_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - TX FIFO message empty interrupt enable. 1, enable the TX FIFO massage empty interrupt. 0, disable the TX FIFO message empty interrupt."]
            #[inline(always)]
            pub fn tfmeie(&self) -> TFMEIE_R {
                TFMEIE_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - TX FIFO message available interrupt enable. 1, enable the TX FIFO massage available interrupt. 0, disable the TX FIFO message available interrupt."]
            #[inline(always)]
            pub fn tfmaie(&self) -> TFMAIE_R {
                TFMAIE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. 1, enable the bus access error interrupt. 0, disable the bus access error interrupt."]
            #[inline(always)]
            pub fn beie(&self) -> BEIE_R {
                BEIE_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bits 14:15 - Bus Acccess Response Control, when bit 15:14= 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. 11: reserved."]
            #[inline(always)]
            pub fn barctl(&self) -> BARCTL_R {
                BARCTL_R::new(((self.bits >> 14) & 3) as u8)
            }
            #[doc = "Bit 31 - Reset TX Fifo and word."]
            #[inline(always)]
            pub fn txreset(&self) -> TXRESET_R {
                TXRESET_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - RX word message valid interrupt enable. 1, enable the RX word massage valid interrupt. 0, disable the RX word message valid interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn rwmvie(&mut self) -> RWMVIE_W<CR_SPEC> {
                RWMVIE_W::new(self, 0)
            }
            #[doc = "Bit 1 - TX word message empty interrupt enable. 1, enable the TX word massage empty interrupt. 0, disable the TX word message empty interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn twmeie(&mut self) -> TWMEIE_W<CR_SPEC> {
                TWMEIE_W::new(self, 1)
            }
            #[doc = "Bit 4 - RX fifo message full interrupt enable. 1, enable the RX fifo message full interrupt. 0, disable the RX fifo message full interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn rfmfie(&mut self) -> RFMFIE_W<CR_SPEC> {
                RFMFIE_W::new(self, 4)
            }
            #[doc = "Bit 5 - RX FIFO message available interrupt enable. 1, enable the RX FIFO massage available interrupt. 0, disable the RX FIFO message available interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn rfmaie(&mut self) -> RFMAIE_W<CR_SPEC> {
                RFMAIE_W::new(self, 5)
            }
            #[doc = "Bit 6 - TX FIFO message empty interrupt enable. 1, enable the TX FIFO massage empty interrupt. 0, disable the TX FIFO message empty interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn tfmeie(&mut self) -> TFMEIE_W<CR_SPEC> {
                TFMEIE_W::new(self, 6)
            }
            #[doc = "Bit 7 - TX FIFO message available interrupt enable. 1, enable the TX FIFO massage available interrupt. 0, disable the TX FIFO message available interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn tfmaie(&mut self) -> TFMAIE_W<CR_SPEC> {
                TFMAIE_W::new(self, 7)
            }
            #[doc = "Bit 8 - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. 1, enable the bus access error interrupt. 0, disable the bus access error interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn beie(&mut self) -> BEIE_W<CR_SPEC> {
                BEIE_W::new(self, 8)
            }
            #[doc = "Bits 14:15 - Bus Acccess Response Control, when bit 15:14= 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. 11: reserved."]
            #[inline(always)]
            #[must_use]
            pub fn barctl(&mut self) -> BARCTL_W<CR_SPEC> {
                BARCTL_W::new(self, 14)
            }
            #[doc = "Bit 31 - Reset TX Fifo and word."]
            #[inline(always)]
            #[must_use]
            pub fn txreset(&mut self) -> TXRESET_W<CR_SPEC> {
                TXRESET_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Command Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CR_SPEC;
        impl crate::RegisterSpec for CR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cr::R`](R) reader structure"]
        impl crate::Readable for CR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
        impl crate::Writable for CR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CR to value 0"]
        impl crate::Resettable for CR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SR (rw) register accessor: Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
    pub type SR = crate::Reg<sr::SR_SPEC>;
    #[doc = "Status Registers"]
    pub mod sr {
        #[doc = "Register `SR` reader"]
        pub type R = crate::R<SR_SPEC>;
        #[doc = "Register `SR` writer"]
        pub type W = crate::W<SR_SPEC>;
        #[doc = "Field `RWMV` reader - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written word message in the RXREG. 0, no valid word message yet in the RXREG."]
        pub type RWMV_R = crate::BitReader;
        #[doc = "Field `TWME` reader - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, means this core had write word message to TXREG. 0, means no valid word message in the TXREG yet."]
        pub type TWME_R = crate::BitReader;
        #[doc = "Field `RFMF` reader - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written 4x32 message in the RXFIFO. 0, no 4x32 RX FIFO message from other core yet."]
        pub type RFMF_R = crate::BitReader;
        #[doc = "Field `RFMA` reader - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, no any data in the 4x32 TXFIFO message buffer. 0, there are some data in the the 4x32 TXFIFO message buffer already."]
        pub type RFMA_R = crate::BitReader;
        #[doc = "Field `TFME` reader - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. 1, no any message data in TXFIFO from other core. 0, there are some data in the 4x32 TX FIFO from other core yet."]
        pub type TFME_R = crate::BitReader;
        #[doc = "Field `TFME` writer - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. 1, no any message data in TXFIFO from other core. 0, there are some data in the 4x32 TX FIFO from other core yet."]
        pub type TFME_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFMA` reader - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. 1, TXFIFO message buffer has slot available 0, no slot available (fifo full)"]
        pub type TFMA_R = crate::BitReader;
        #[doc = "Field `TFMA` writer - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. 1, TXFIFO message buffer has slot available 0, no slot available (fifo full)"]
        pub type TFMA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EW2RO` writer - bus Error for Write to Read Only address; this bit is W1C bit. 1, write to read only address happened in the bus of this block. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
        pub type EW2RO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EAIVA` writer - bus Error for Accessing Invalid Address; this bit is W1C bit. 1, read and write to invalid address in the bus of this block, will set this bit. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
        pub type EAIVA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EWTFF` writer - bus Error for write when tx fifo full, this bit is W1C bit. 1, write to a fulled tx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
        pub type EWTFF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERRFE` writer - bus Error for read when rx fifo empty, this bit is W1C bit. 1, read from a empty rx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
        pub type ERRFE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EWTRF` writer - bus Error for write when tx word message are still valid, this bit is W1C bit. 1, write to word message when the word message are still valid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
        pub type EWTRF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERRRE` writer - bus Error for read when rx word message are still invalid, this bit is W1C bit. 1, read from word message when the word message are still invalid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
        pub type ERRRE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFEC` reader - TX FIFO empty message word count"]
        pub type TFEC_R = crate::FieldReader;
        #[doc = "Field `RFVC` reader - RX FIFO valid message count"]
        pub type RFVC_R = crate::FieldReader;
        impl R {
            #[doc = "Bit 0 - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written word message in the RXREG. 0, no valid word message yet in the RXREG."]
            #[inline(always)]
            pub fn rwmv(&self) -> RWMV_R {
                RWMV_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, means this core had write word message to TXREG. 0, means no valid word message in the TXREG yet."]
            #[inline(always)]
            pub fn twme(&self) -> TWME_R {
                TWME_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 4 - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, the other core had written 4x32 message in the RXFIFO. 0, no 4x32 RX FIFO message from other core yet."]
            #[inline(always)]
            pub fn rfmf(&self) -> RFMF_R {
                RFMF_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. 1, no any data in the 4x32 TXFIFO message buffer. 0, there are some data in the the 4x32 TXFIFO message buffer already."]
            #[inline(always)]
            pub fn rfma(&self) -> RFMA_R {
                RFMA_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. 1, no any message data in TXFIFO from other core. 0, there are some data in the 4x32 TX FIFO from other core yet."]
            #[inline(always)]
            pub fn tfme(&self) -> TFME_R {
                TFME_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. 1, TXFIFO message buffer has slot available 0, no slot available (fifo full)"]
            #[inline(always)]
            pub fn tfma(&self) -> TFMA_R {
                TFMA_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 16:19 - TX FIFO empty message word count"]
            #[inline(always)]
            pub fn tfec(&self) -> TFEC_R {
                TFEC_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bits 20:23 - RX FIFO valid message count"]
            #[inline(always)]
            pub fn rfvc(&self) -> RFVC_R {
                RFVC_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 6 - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. 1, no any message data in TXFIFO from other core. 0, there are some data in the 4x32 TX FIFO from other core yet."]
            #[inline(always)]
            #[must_use]
            pub fn tfme(&mut self) -> TFME_W<SR_SPEC> {
                TFME_W::new(self, 6)
            }
            #[doc = "Bit 7 - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. 1, TXFIFO message buffer has slot available 0, no slot available (fifo full)"]
            #[inline(always)]
            #[must_use]
            pub fn tfma(&mut self) -> TFMA_W<SR_SPEC> {
                TFMA_W::new(self, 7)
            }
            #[doc = "Bit 8 - bus Error for Write to Read Only address; this bit is W1C bit. 1, write to read only address happened in the bus of this block. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
            #[inline(always)]
            #[must_use]
            pub fn ew2ro(&mut self) -> EW2RO_W<SR_SPEC> {
                EW2RO_W::new(self, 8)
            }
            #[doc = "Bit 9 - bus Error for Accessing Invalid Address; this bit is W1C bit. 1, read and write to invalid address in the bus of this block, will set this bit. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
            #[inline(always)]
            #[must_use]
            pub fn eaiva(&mut self) -> EAIVA_W<SR_SPEC> {
                EAIVA_W::new(self, 9)
            }
            #[doc = "Bit 10 - bus Error for write when tx fifo full, this bit is W1C bit. 1, write to a fulled tx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
            #[inline(always)]
            #[must_use]
            pub fn ewtff(&mut self) -> EWTFF_W<SR_SPEC> {
                EWTFF_W::new(self, 10)
            }
            #[doc = "Bit 11 - bus Error for read when rx fifo empty, this bit is W1C bit. 1, read from a empty rx fifo will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
            #[inline(always)]
            #[must_use]
            pub fn errfe(&mut self) -> ERRFE_W<SR_SPEC> {
                ERRFE_W::new(self, 11)
            }
            #[doc = "Bit 12 - bus Error for write when tx word message are still valid, this bit is W1C bit. 1, write to word message when the word message are still valid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
            #[inline(always)]
            #[must_use]
            pub fn ewtrf(&mut self) -> EWTRF_W<SR_SPEC> {
                EWTRF_W::new(self, 12)
            }
            #[doc = "Bit 13 - bus Error for read when rx word message are still invalid, this bit is W1C bit. 1, read from word message when the word message are still invalid will cause this error bit set. 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen."]
            #[inline(always)]
            #[must_use]
            pub fn errre(&mut self) -> ERRRE_W<SR_SPEC> {
                ERRRE_W::new(self, 13)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SR_SPEC;
        impl crate::RegisterSpec for SR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sr::R`](R) reader structure"]
        impl crate::Readable for SR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
        impl crate::Writable for SR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SR to value 0xe2"]
        impl crate::Resettable for SR_SPEC {
            const RESET_VALUE: u32 = 0xe2;
        }
    }
    #[doc = "TXREG (rw) register accessor: Transmit word message to other core.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txreg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txreg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txreg`]
module"]
    pub type TXREG = crate::Reg<txreg::TXREG_SPEC>;
    #[doc = "Transmit word message to other core."]
    pub mod txreg {
        #[doc = "Register `TXREG` reader"]
        pub type R = crate::R<TXREG_SPEC>;
        #[doc = "Register `TXREG` writer"]
        pub type W = crate::W<TXREG_SPEC>;
        #[doc = "Field `TXREG` writer - Transmit word message to other core."]
        pub type TXREG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - Transmit word message to other core."]
            #[inline(always)]
            #[must_use]
            pub fn txreg(&mut self) -> TXREG_W<TXREG_SPEC> {
                TXREG_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Transmit word message to other core.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txreg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txreg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXREG_SPEC;
        impl crate::RegisterSpec for TXREG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txreg::R`](R) reader structure"]
        impl crate::Readable for TXREG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txreg::W`](W) writer structure"]
        impl crate::Writable for TXREG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXREG to value 0"]
        impl crate::Resettable for TXREG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXREG (rw) register accessor: Receive word message from other core.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxreg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxreg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxreg`]
module"]
    pub type RXREG = crate::Reg<rxreg::RXREG_SPEC>;
    #[doc = "Receive word message from other core."]
    pub mod rxreg {
        #[doc = "Register `RXREG` reader"]
        pub type R = crate::R<RXREG_SPEC>;
        #[doc = "Register `RXREG` writer"]
        pub type W = crate::W<RXREG_SPEC>;
        #[doc = "Field `RXREG` reader - Receive word message from other core."]
        pub type RXREG_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Receive word message from other core."]
            #[inline(always)]
            pub fn rxreg(&self) -> RXREG_R {
                RXREG_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Receive word message from other core.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxreg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxreg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXREG_SPEC;
        impl crate::RegisterSpec for RXREG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxreg::R`](R) reader structure"]
        impl crate::Readable for RXREG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxreg::W`](W) writer structure"]
        impl crate::Writable for RXREG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXREG to value 0"]
        impl crate::Resettable for RXREG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXWRD (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txwrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txwrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txwrd`]
module"]
    pub type TXWRD = crate::Reg<txwrd::TXWRD_SPEC>;
    #[doc = "no description available"]
    pub mod txwrd {
        #[doc = "Register `TXWRD[%s]` reader"]
        pub type R = crate::R<TXWRD_SPEC>;
        #[doc = "Register `TXWRD[%s]` writer"]
        pub type W = crate::W<TXWRD_SPEC>;
        #[doc = "Field `TXFIFO` writer - TXFIFO for sending message to other core, FIFO size, 4x32 can write one of the word address to push data to the FIFO; can also use 4x32 burst write from 0x010 to push 4 words to the FIFO."]
        pub type TXFIFO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - TXFIFO for sending message to other core, FIFO size, 4x32 can write one of the word address to push data to the FIFO; can also use 4x32 burst write from 0x010 to push 4 words to the FIFO."]
            #[inline(always)]
            #[must_use]
            pub fn txfifo(&mut self) -> TXFIFO_W<TXWRD_SPEC> {
                TXFIFO_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txwrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txwrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXWRD_SPEC;
        impl crate::RegisterSpec for TXWRD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txwrd::R`](R) reader structure"]
        impl crate::Readable for TXWRD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txwrd::W`](W) writer structure"]
        impl crate::Writable for TXWRD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXWRD[%s]
to value 0"]
        impl crate::Resettable for TXWRD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXWRD (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxwrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxwrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxwrd`]
module"]
    pub type RXWRD = crate::Reg<rxwrd::RXWRD_SPEC>;
    #[doc = "no description available"]
    pub mod rxwrd {
        #[doc = "Register `RXWRD[%s]` reader"]
        pub type R = crate::R<RXWRD_SPEC>;
        #[doc = "Register `RXWRD[%s]` writer"]
        pub type W = crate::W<RXWRD_SPEC>;
        #[doc = "Field `RXFIFO` reader - RXFIFO for receiving message from other core, FIFO size, 4x32 can read one of the word address to pop data to the FIFO; can also use 4x32 burst read from 0x020 to read 4 words from the FIFO."]
        pub type RXFIFO_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - RXFIFO for receiving message from other core, FIFO size, 4x32 can read one of the word address to pop data to the FIFO; can also use 4x32 burst read from 0x020 to read 4 words from the FIFO."]
            #[inline(always)]
            pub fn rxfifo(&self) -> RXFIFO_R {
                RXFIFO_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxwrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxwrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXWRD_SPEC;
        impl crate::RegisterSpec for RXWRD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxwrd::R`](R) reader structure"]
        impl crate::Readable for RXWRD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxwrd::W`](W) writer structure"]
        impl crate::Writable for RXWRD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXWRD[%s]
to value 0"]
        impl crate::Resettable for RXWRD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "MBX0B"]
pub struct MBX0B {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MBX0B {}
impl MBX0B {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mbx0a::RegisterBlock = 0xf00a_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mbx0a::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MBX0B {
    type Target = mbx0a::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MBX0B {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MBX0B").finish()
    }
}
#[doc = "MBX0B"]
pub use self::mbx0a as mbx0b;
#[doc = "WDG0"]
pub struct WDG0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for WDG0 {}
impl WDG0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const wdg0::RegisterBlock = 0xf00b_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const wdg0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for WDG0 {
    type Target = wdg0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for WDG0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WDG0").finish()
    }
}
#[doc = "WDG0"]
pub mod wdg0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        ctrl0: CTRL0,
        ctrl1: CTRL1,
        ot_int_val: OT_INT_VAL,
        ot_rst_val: OT_RST_VAL,
        wdt_refresh_reg: WDT_REFRESH_REG,
        wdt_status: WDT_STATUS,
        cfg_prot: CFG_PROT,
        ref_prot: REF_PROT,
        wdt_en: WDT_EN,
        ref_time: REF_TIME,
    }
    impl RegisterBlock {
        #[doc = "0x00 - wdog ctrl register 0 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits"]
        #[inline(always)]
        pub const fn ctrl0(&self) -> &CTRL0 {
            &self.ctrl0
        }
        #[doc = "0x04 - wdog ctrl register 1 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits"]
        #[inline(always)]
        pub const fn ctrl1(&self) -> &CTRL1 {
            &self.ctrl1
        }
        #[doc = "0x08 - wdog timeout interrupt counter value"]
        #[inline(always)]
        pub const fn ot_int_val(&self) -> &OT_INT_VAL {
            &self.ot_int_val
        }
        #[doc = "0x0c - wdog timeout reset counter value"]
        #[inline(always)]
        pub const fn ot_rst_val(&self) -> &OT_RST_VAL {
            &self.ot_rst_val
        }
        #[doc = "0x10 - wdog refresh register"]
        #[inline(always)]
        pub const fn wdt_refresh_reg(&self) -> &WDT_REFRESH_REG {
            &self.wdt_refresh_reg
        }
        #[doc = "0x14 - wdog status register"]
        #[inline(always)]
        pub const fn wdt_status(&self) -> &WDT_STATUS {
            &self.wdt_status
        }
        #[doc = "0x18 - ctrl register protection register"]
        #[inline(always)]
        pub const fn cfg_prot(&self) -> &CFG_PROT {
            &self.cfg_prot
        }
        #[doc = "0x1c - refresh protection register"]
        #[inline(always)]
        pub const fn ref_prot(&self) -> &REF_PROT {
            &self.ref_prot
        }
        #[doc = "0x20 - Wdog enable"]
        #[inline(always)]
        pub const fn wdt_en(&self) -> &WDT_EN {
            &self.wdt_en
        }
        #[doc = "0x24 - Refresh period value"]
        #[inline(always)]
        pub const fn ref_time(&self) -> &REF_TIME {
            &self.ref_time
        }
    }
    #[doc = "CTRL0 (rw) register accessor: wdog ctrl register 0 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
module"]
    pub type CTRL0 = crate::Reg<ctrl0::CTRL0_SPEC>;
    #[doc = "wdog ctrl register 0 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits"]
    pub mod ctrl0 {
        #[doc = "Register `CTRL0` reader"]
        pub type R = crate::R<CTRL0_SPEC>;
        #[doc = "Register `CTRL0` writer"]
        pub type W = crate::W<CTRL0_SPEC>;
        #[doc = "Field `EN_LP` reader - WDT enable or not in low power mode 2'b00: wdt is halted once in low power mode 2'b01: wdt will work with 1/4 normal clock freq in low power mode 2'b10: wdt will work with 1/2 normal clock freq in low power mode 2'b11: wdt will work with normal clock freq in low power mode"]
        pub type EN_LP_R = crate::FieldReader;
        #[doc = "Field `EN_LP` writer - WDT enable or not in low power mode 2'b00: wdt is halted once in low power mode 2'b01: wdt will work with 1/4 normal clock freq in low power mode 2'b10: wdt will work with 1/2 normal clock freq in low power mode 2'b11: wdt will work with normal clock freq in low power mode"]
        pub type EN_LP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `EN_DBG` reader - WTD enable or not in debug mode"]
        pub type EN_DBG_R = crate::BitReader;
        #[doc = "Field `EN_DBG` writer - WTD enable or not in debug mode"]
        pub type EN_DBG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `REF_UNLOCK_MEC` reader - Unlock refresh mechanism 00: the required unlock password is the same with refresh_psd_register 01: the required unlock password is a ring shift left value of refresh_psd_register 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1"]
        pub type REF_UNLOCK_MEC_R = crate::FieldReader;
        #[doc = "Field `REF_UNLOCK_MEC` writer - Unlock refresh mechanism 00: the required unlock password is the same with refresh_psd_register 01: the required unlock password is a ring shift left value of refresh_psd_register 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1"]
        pub type REF_UNLOCK_MEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `REF_LOCK` reader - WDT refresh has to be unlocked firstly once refresh lock is enable."]
        pub type REF_LOCK_R = crate::BitReader;
        #[doc = "Field `REF_LOCK` writer - WDT refresh has to be unlocked firstly once refresh lock is enable."]
        pub type REF_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WIN_UPPER` reader - The upper threshold of window value The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value If this register value is zero, then no upper level limitation"]
        pub type WIN_UPPER_R = crate::FieldReader;
        #[doc = "Field `WIN_UPPER` writer - The upper threshold of window value The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value If this register value is zero, then no upper level limitation"]
        pub type WIN_UPPER_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `REF_OT_REQ` reader - If refresh event has to be limited into a period after refresh unlocked. Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
        pub type REF_OT_REQ_R = crate::BitReader;
        #[doc = "Field `REF_OT_REQ` writer - If refresh event has to be limited into a period after refresh unlocked. Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
        pub type REF_OT_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OT_SELF_CLEAR` reader - overtime reset can be self released after 32 function cycles"]
        pub type OT_SELF_CLEAR_R = crate::BitReader;
        #[doc = "Field `OT_SELF_CLEAR` writer - overtime reset can be self released after 32 function cycles"]
        pub type OT_SELF_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CFG_LOCK` reader - The register is locked and unlock is needed before re-config registers Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. The register update needs to be finished in the required period defined by UPD_OT_TIME register"]
        pub type CFG_LOCK_R = crate::BitReader;
        #[doc = "Field `CFG_LOCK` writer - The register is locked and unlock is needed before re-config registers Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. The register update needs to be finished in the required period defined by UPD_OT_TIME register"]
        pub type CFG_LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WIN_LOWER` reader - Once window mode is opened, the lower counter value to refresh wdt 00: 4/8 overtime value 01: 5/8 of overtime value 10: 6/8 of overtime value 11: 7/8 of overtime value"]
        pub type WIN_LOWER_R = crate::FieldReader;
        #[doc = "Field `WIN_LOWER` writer - Once window mode is opened, the lower counter value to refresh wdt 00: 4/8 overtime value 01: 5/8 of overtime value 10: 6/8 of overtime value 11: 7/8 of overtime value"]
        pub type WIN_LOWER_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `WIN_EN` reader - window mode enable"]
        pub type WIN_EN_R = crate::BitReader;
        #[doc = "Field `WIN_EN` writer - window mode enable"]
        pub type WIN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIV_VALUE` reader - clock divider, the clock divider works as 2 ^ div_value for wdt counter"]
        pub type DIV_VALUE_R = crate::FieldReader;
        #[doc = "Field `DIV_VALUE` writer - clock divider, the clock divider works as 2 ^ div_value for wdt counter"]
        pub type DIV_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `CLK_SEL` reader - clock select 0：bus clock 1：ext clock"]
        pub type CLK_SEL_R = crate::BitReader;
        #[doc = "Field `CLK_SEL` writer - clock select 0：bus clock 1：ext clock"]
        pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1 - WDT enable or not in low power mode 2'b00: wdt is halted once in low power mode 2'b01: wdt will work with 1/4 normal clock freq in low power mode 2'b10: wdt will work with 1/2 normal clock freq in low power mode 2'b11: wdt will work with normal clock freq in low power mode"]
            #[inline(always)]
            pub fn en_lp(&self) -> EN_LP_R {
                EN_LP_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 2 - WTD enable or not in debug mode"]
            #[inline(always)]
            pub fn en_dbg(&self) -> EN_DBG_R {
                EN_DBG_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bits 3:4 - Unlock refresh mechanism 00: the required unlock password is the same with refresh_psd_register 01: the required unlock password is a ring shift left value of refresh_psd_register 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1"]
            #[inline(always)]
            pub fn ref_unlock_mec(&self) -> REF_UNLOCK_MEC_R {
                REF_UNLOCK_MEC_R::new(((self.bits >> 3) & 3) as u8)
            }
            #[doc = "Bit 5 - WDT refresh has to be unlocked firstly once refresh lock is enable."]
            #[inline(always)]
            pub fn ref_lock(&self) -> REF_LOCK_R {
                REF_LOCK_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bits 12:14 - The upper threshold of window value The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value If this register value is zero, then no upper level limitation"]
            #[inline(always)]
            pub fn win_upper(&self) -> WIN_UPPER_R {
                WIN_UPPER_R::new(((self.bits >> 12) & 7) as u8)
            }
            #[doc = "Bit 15 - If refresh event has to be limited into a period after refresh unlocked. Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
            #[inline(always)]
            pub fn ref_ot_req(&self) -> REF_OT_REQ_R {
                REF_OT_REQ_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 17 - overtime reset can be self released after 32 function cycles"]
            #[inline(always)]
            pub fn ot_self_clear(&self) -> OT_SELF_CLEAR_R {
                OT_SELF_CLEAR_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 21 - The register is locked and unlock is needed before re-config registers Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. The register update needs to be finished in the required period defined by UPD_OT_TIME register"]
            #[inline(always)]
            pub fn cfg_lock(&self) -> CFG_LOCK_R {
                CFG_LOCK_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bits 22:23 - Once window mode is opened, the lower counter value to refresh wdt 00: 4/8 overtime value 01: 5/8 of overtime value 10: 6/8 of overtime value 11: 7/8 of overtime value"]
            #[inline(always)]
            pub fn win_lower(&self) -> WIN_LOWER_R {
                WIN_LOWER_R::new(((self.bits >> 22) & 3) as u8)
            }
            #[doc = "Bit 24 - window mode enable"]
            #[inline(always)]
            pub fn win_en(&self) -> WIN_EN_R {
                WIN_EN_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bits 25:27 - clock divider, the clock divider works as 2 ^ div_value for wdt counter"]
            #[inline(always)]
            pub fn div_value(&self) -> DIV_VALUE_R {
                DIV_VALUE_R::new(((self.bits >> 25) & 7) as u8)
            }
            #[doc = "Bit 29 - clock select 0：bus clock 1：ext clock"]
            #[inline(always)]
            pub fn clk_sel(&self) -> CLK_SEL_R {
                CLK_SEL_R::new(((self.bits >> 29) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - WDT enable or not in low power mode 2'b00: wdt is halted once in low power mode 2'b01: wdt will work with 1/4 normal clock freq in low power mode 2'b10: wdt will work with 1/2 normal clock freq in low power mode 2'b11: wdt will work with normal clock freq in low power mode"]
            #[inline(always)]
            #[must_use]
            pub fn en_lp(&mut self) -> EN_LP_W<CTRL0_SPEC> {
                EN_LP_W::new(self, 0)
            }
            #[doc = "Bit 2 - WTD enable or not in debug mode"]
            #[inline(always)]
            #[must_use]
            pub fn en_dbg(&mut self) -> EN_DBG_W<CTRL0_SPEC> {
                EN_DBG_W::new(self, 2)
            }
            #[doc = "Bits 3:4 - Unlock refresh mechanism 00: the required unlock password is the same with refresh_psd_register 01: the required unlock password is a ring shift left value of refresh_psd_register 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1"]
            #[inline(always)]
            #[must_use]
            pub fn ref_unlock_mec(&mut self) -> REF_UNLOCK_MEC_W<CTRL0_SPEC> {
                REF_UNLOCK_MEC_W::new(self, 3)
            }
            #[doc = "Bit 5 - WDT refresh has to be unlocked firstly once refresh lock is enable."]
            #[inline(always)]
            #[must_use]
            pub fn ref_lock(&mut self) -> REF_LOCK_W<CTRL0_SPEC> {
                REF_LOCK_W::new(self, 5)
            }
            #[doc = "Bits 12:14 - The upper threshold of window value The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value If this register value is zero, then no upper level limitation"]
            #[inline(always)]
            #[must_use]
            pub fn win_upper(&mut self) -> WIN_UPPER_W<CTRL0_SPEC> {
                WIN_UPPER_W::new(self, 12)
            }
            #[doc = "Bit 15 - If refresh event has to be limited into a period after refresh unlocked. Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
            #[inline(always)]
            #[must_use]
            pub fn ref_ot_req(&mut self) -> REF_OT_REQ_W<CTRL0_SPEC> {
                REF_OT_REQ_W::new(self, 15)
            }
            #[doc = "Bit 17 - overtime reset can be self released after 32 function cycles"]
            #[inline(always)]
            #[must_use]
            pub fn ot_self_clear(&mut self) -> OT_SELF_CLEAR_W<CTRL0_SPEC> {
                OT_SELF_CLEAR_W::new(self, 17)
            }
            #[doc = "Bit 21 - The register is locked and unlock is needed before re-config registers Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. The register update needs to be finished in the required period defined by UPD_OT_TIME register"]
            #[inline(always)]
            #[must_use]
            pub fn cfg_lock(&mut self) -> CFG_LOCK_W<CTRL0_SPEC> {
                CFG_LOCK_W::new(self, 21)
            }
            #[doc = "Bits 22:23 - Once window mode is opened, the lower counter value to refresh wdt 00: 4/8 overtime value 01: 5/8 of overtime value 10: 6/8 of overtime value 11: 7/8 of overtime value"]
            #[inline(always)]
            #[must_use]
            pub fn win_lower(&mut self) -> WIN_LOWER_W<CTRL0_SPEC> {
                WIN_LOWER_W::new(self, 22)
            }
            #[doc = "Bit 24 - window mode enable"]
            #[inline(always)]
            #[must_use]
            pub fn win_en(&mut self) -> WIN_EN_W<CTRL0_SPEC> {
                WIN_EN_W::new(self, 24)
            }
            #[doc = "Bits 25:27 - clock divider, the clock divider works as 2 ^ div_value for wdt counter"]
            #[inline(always)]
            #[must_use]
            pub fn div_value(&mut self) -> DIV_VALUE_W<CTRL0_SPEC> {
                DIV_VALUE_W::new(self, 25)
            }
            #[doc = "Bit 29 - clock select 0：bus clock 1：ext clock"]
            #[inline(always)]
            #[must_use]
            pub fn clk_sel(&mut self) -> CLK_SEL_W<CTRL0_SPEC> {
                CLK_SEL_W::new(self, 29)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wdog ctrl register 0 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CTRL0_SPEC;
        impl crate::RegisterSpec for CTRL0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"]
        impl crate::Readable for CTRL0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
        impl crate::Writable for CTRL0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CTRL0 to value 0"]
        impl crate::Resettable for CTRL0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CTRL1 (rw) register accessor: wdog ctrl register 1 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
module"]
    pub type CTRL1 = crate::Reg<ctrl1::CTRL1_SPEC>;
    #[doc = "wdog ctrl register 1 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits"]
    pub mod ctrl1 {
        #[doc = "Register `CTRL1` reader"]
        pub type R = crate::R<CTRL1_SPEC>;
        #[doc = "Register `CTRL1` writer"]
        pub type W = crate::W<CTRL1_SPEC>;
        #[doc = "Field `PARITY_FAIL_INT_EN` reader - Parity error will trigger a interrupt"]
        pub type PARITY_FAIL_INT_EN_R = crate::BitReader;
        #[doc = "Field `PARITY_FAIL_INT_EN` writer - Parity error will trigger a interrupt"]
        pub type PARITY_FAIL_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PARITY_FAIL_RST_EN` reader - Parity error will trigger a reset A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits"]
        pub type PARITY_FAIL_RST_EN_R = crate::BitReader;
        #[doc = "Field `PARITY_FAIL_RST_EN` writer - Parity error will trigger a reset A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits"]
        pub type PARITY_FAIL_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UNL_CTL_FAIL_INT_EN` reader - Unlock register update failure will trigger a interrupt"]
        pub type UNL_CTL_FAIL_INT_EN_R = crate::BitReader;
        #[doc = "Field `UNL_CTL_FAIL_INT_EN` writer - Unlock register update failure will trigger a interrupt"]
        pub type UNL_CTL_FAIL_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UNL_CTL_FAIL_RST_EN` reader - Unlock register update failure will trigger a reset"]
        pub type UNL_CTL_FAIL_RST_EN_R = crate::BitReader;
        #[doc = "Field `UNL_CTL_FAIL_RST_EN` writer - Unlock register update failure will trigger a reset"]
        pub type UNL_CTL_FAIL_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CTL_VIO_INT_EN` reader - Ctrl update violation will trigger a interrupt"]
        pub type CTL_VIO_INT_EN_R = crate::BitReader;
        #[doc = "Field `CTL_VIO_INT_EN` writer - Ctrl update violation will trigger a interrupt"]
        pub type CTL_VIO_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CTL_VIO_RST_EN` reader - Ctrl update violation will trigger a reset The violation event is to try updating the locked register before unlock them"]
        pub type CTL_VIO_RST_EN_R = crate::BitReader;
        #[doc = "Field `CTL_VIO_RST_EN` writer - Ctrl update violation will trigger a reset The violation event is to try updating the locked register before unlock them"]
        pub type CTL_VIO_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OT_INT_EN` reader - WDT can generate an interrupt warning before timeout"]
        pub type OT_INT_EN_R = crate::BitReader;
        #[doc = "Field `OT_INT_EN` writer - WDT can generate an interrupt warning before timeout"]
        pub type OT_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OT_RST_EN` reader - WDT overtime will generate a reset"]
        pub type OT_RST_EN_R = crate::BitReader;
        #[doc = "Field `OT_RST_EN` writer - WDT overtime will generate a reset"]
        pub type OT_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UNL_REF_FAIL_INT_EN` reader - Refresh unlock fail will trigger a interrupt"]
        pub type UNL_REF_FAIL_INT_EN_R = crate::BitReader;
        #[doc = "Field `UNL_REF_FAIL_INT_EN` writer - Refresh unlock fail will trigger a interrupt"]
        pub type UNL_REF_FAIL_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UNL_REF_FAIL_RST_EN` reader - Refresh unlock fail will trigger a reset"]
        pub type UNL_REF_FAIL_RST_EN_R = crate::BitReader;
        #[doc = "Field `UNL_REF_FAIL_RST_EN` writer - Refresh unlock fail will trigger a reset"]
        pub type UNL_REF_FAIL_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `REF_FAIL_INT_EN` reader - Refresh violation will trigger an interrupt"]
        pub type REF_FAIL_INT_EN_R = crate::BitReader;
        #[doc = "Field `REF_FAIL_INT_EN` writer - Refresh violation will trigger an interrupt"]
        pub type REF_FAIL_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `REF_FAIL_RST_EN` reader - Refresh violation will trigger an reset. These event will be taken as a refresh violation: 1) Not refresh in the window once window mode is enabled 2) Not unlock refresh firstly if unlock is required 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. 4) Not write the required word to refresh wdt."]
        pub type REF_FAIL_RST_EN_R = crate::BitReader;
        #[doc = "Field `REF_FAIL_RST_EN` writer - Refresh violation will trigger an reset. These event will be taken as a refresh violation: 1) Not refresh in the window once window mode is enabled 2) Not unlock refresh firstly if unlock is required 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. 4) Not write the required word to refresh wdt."]
        pub type REF_FAIL_RST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 2 - Parity error will trigger a interrupt"]
            #[inline(always)]
            pub fn parity_fail_int_en(&self) -> PARITY_FAIL_INT_EN_R {
                PARITY_FAIL_INT_EN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Parity error will trigger a reset A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits"]
            #[inline(always)]
            pub fn parity_fail_rst_en(&self) -> PARITY_FAIL_RST_EN_R {
                PARITY_FAIL_RST_EN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Unlock register update failure will trigger a interrupt"]
            #[inline(always)]
            pub fn unl_ctl_fail_int_en(&self) -> UNL_CTL_FAIL_INT_EN_R {
                UNL_CTL_FAIL_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Unlock register update failure will trigger a reset"]
            #[inline(always)]
            pub fn unl_ctl_fail_rst_en(&self) -> UNL_CTL_FAIL_RST_EN_R {
                UNL_CTL_FAIL_RST_EN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Ctrl update violation will trigger a interrupt"]
            #[inline(always)]
            pub fn ctl_vio_int_en(&self) -> CTL_VIO_INT_EN_R {
                CTL_VIO_INT_EN_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Ctrl update violation will trigger a reset The violation event is to try updating the locked register before unlock them"]
            #[inline(always)]
            pub fn ctl_vio_rst_en(&self) -> CTL_VIO_RST_EN_R {
                CTL_VIO_RST_EN_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 16 - WDT can generate an interrupt warning before timeout"]
            #[inline(always)]
            pub fn ot_int_en(&self) -> OT_INT_EN_R {
                OT_INT_EN_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - WDT overtime will generate a reset"]
            #[inline(always)]
            pub fn ot_rst_en(&self) -> OT_RST_EN_R {
                OT_RST_EN_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 20 - Refresh unlock fail will trigger a interrupt"]
            #[inline(always)]
            pub fn unl_ref_fail_int_en(&self) -> UNL_REF_FAIL_INT_EN_R {
                UNL_REF_FAIL_INT_EN_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Refresh unlock fail will trigger a reset"]
            #[inline(always)]
            pub fn unl_ref_fail_rst_en(&self) -> UNL_REF_FAIL_RST_EN_R {
                UNL_REF_FAIL_RST_EN_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - Refresh violation will trigger an interrupt"]
            #[inline(always)]
            pub fn ref_fail_int_en(&self) -> REF_FAIL_INT_EN_R {
                REF_FAIL_INT_EN_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - Refresh violation will trigger an reset. These event will be taken as a refresh violation: 1) Not refresh in the window once window mode is enabled 2) Not unlock refresh firstly if unlock is required 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. 4) Not write the required word to refresh wdt."]
            #[inline(always)]
            pub fn ref_fail_rst_en(&self) -> REF_FAIL_RST_EN_R {
                REF_FAIL_RST_EN_R::new(((self.bits >> 23) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 2 - Parity error will trigger a interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn parity_fail_int_en(&mut self) -> PARITY_FAIL_INT_EN_W<CTRL1_SPEC> {
                PARITY_FAIL_INT_EN_W::new(self, 2)
            }
            #[doc = "Bit 3 - Parity error will trigger a reset A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits"]
            #[inline(always)]
            #[must_use]
            pub fn parity_fail_rst_en(&mut self) -> PARITY_FAIL_RST_EN_W<CTRL1_SPEC> {
                PARITY_FAIL_RST_EN_W::new(self, 3)
            }
            #[doc = "Bit 4 - Unlock register update failure will trigger a interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn unl_ctl_fail_int_en(&mut self) -> UNL_CTL_FAIL_INT_EN_W<CTRL1_SPEC> {
                UNL_CTL_FAIL_INT_EN_W::new(self, 4)
            }
            #[doc = "Bit 5 - Unlock register update failure will trigger a reset"]
            #[inline(always)]
            #[must_use]
            pub fn unl_ctl_fail_rst_en(&mut self) -> UNL_CTL_FAIL_RST_EN_W<CTRL1_SPEC> {
                UNL_CTL_FAIL_RST_EN_W::new(self, 5)
            }
            #[doc = "Bit 6 - Ctrl update violation will trigger a interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn ctl_vio_int_en(&mut self) -> CTL_VIO_INT_EN_W<CTRL1_SPEC> {
                CTL_VIO_INT_EN_W::new(self, 6)
            }
            #[doc = "Bit 7 - Ctrl update violation will trigger a reset The violation event is to try updating the locked register before unlock them"]
            #[inline(always)]
            #[must_use]
            pub fn ctl_vio_rst_en(&mut self) -> CTL_VIO_RST_EN_W<CTRL1_SPEC> {
                CTL_VIO_RST_EN_W::new(self, 7)
            }
            #[doc = "Bit 16 - WDT can generate an interrupt warning before timeout"]
            #[inline(always)]
            #[must_use]
            pub fn ot_int_en(&mut self) -> OT_INT_EN_W<CTRL1_SPEC> {
                OT_INT_EN_W::new(self, 16)
            }
            #[doc = "Bit 17 - WDT overtime will generate a reset"]
            #[inline(always)]
            #[must_use]
            pub fn ot_rst_en(&mut self) -> OT_RST_EN_W<CTRL1_SPEC> {
                OT_RST_EN_W::new(self, 17)
            }
            #[doc = "Bit 20 - Refresh unlock fail will trigger a interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn unl_ref_fail_int_en(&mut self) -> UNL_REF_FAIL_INT_EN_W<CTRL1_SPEC> {
                UNL_REF_FAIL_INT_EN_W::new(self, 20)
            }
            #[doc = "Bit 21 - Refresh unlock fail will trigger a reset"]
            #[inline(always)]
            #[must_use]
            pub fn unl_ref_fail_rst_en(&mut self) -> UNL_REF_FAIL_RST_EN_W<CTRL1_SPEC> {
                UNL_REF_FAIL_RST_EN_W::new(self, 21)
            }
            #[doc = "Bit 22 - Refresh violation will trigger an interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn ref_fail_int_en(&mut self) -> REF_FAIL_INT_EN_W<CTRL1_SPEC> {
                REF_FAIL_INT_EN_W::new(self, 22)
            }
            #[doc = "Bit 23 - Refresh violation will trigger an reset. These event will be taken as a refresh violation: 1) Not refresh in the window once window mode is enabled 2) Not unlock refresh firstly if unlock is required 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. 4) Not write the required word to refresh wdt."]
            #[inline(always)]
            #[must_use]
            pub fn ref_fail_rst_en(&mut self) -> REF_FAIL_RST_EN_W<CTRL1_SPEC> {
                REF_FAIL_RST_EN_W::new(self, 23)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wdog ctrl register 1 Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CTRL1_SPEC;
        impl crate::RegisterSpec for CTRL1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"]
        impl crate::Readable for CTRL1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
        impl crate::Writable for CTRL1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CTRL1 to value 0"]
        impl crate::Resettable for CTRL1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "OT_INT_VAL (rw) register accessor: wdog timeout interrupt counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ot_int_val::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ot_int_val::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ot_int_val`]
module"]
    pub type OT_INT_VAL = crate::Reg<ot_int_val::OT_INT_VAL_SPEC>;
    #[doc = "wdog timeout interrupt counter value"]
    pub mod ot_int_val {
        #[doc = "Register `OT_INT_VAL` reader"]
        pub type R = crate::R<OT_INT_VAL_SPEC>;
        #[doc = "Register `OT_INT_VAL` writer"]
        pub type W = crate::W<OT_INT_VAL_SPEC>;
        #[doc = "Field `OT_INT_VAL` reader - WDT timeout interrupt value"]
        pub type OT_INT_VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `OT_INT_VAL` writer - WDT timeout interrupt value"]
        pub type OT_INT_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - WDT timeout interrupt value"]
            #[inline(always)]
            pub fn ot_int_val(&self) -> OT_INT_VAL_R {
                OT_INT_VAL_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - WDT timeout interrupt value"]
            #[inline(always)]
            #[must_use]
            pub fn ot_int_val(&mut self) -> OT_INT_VAL_W<OT_INT_VAL_SPEC> {
                OT_INT_VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wdog timeout interrupt counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ot_int_val::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ot_int_val::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct OT_INT_VAL_SPEC;
        impl crate::RegisterSpec for OT_INT_VAL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ot_int_val::R`](R) reader structure"]
        impl crate::Readable for OT_INT_VAL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ot_int_val::W`](W) writer structure"]
        impl crate::Writable for OT_INT_VAL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets OT_INT_VAL to value 0"]
        impl crate::Resettable for OT_INT_VAL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "OT_RST_VAL (rw) register accessor: wdog timeout reset counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ot_rst_val::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ot_rst_val::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ot_rst_val`]
module"]
    pub type OT_RST_VAL = crate::Reg<ot_rst_val::OT_RST_VAL_SPEC>;
    #[doc = "wdog timeout reset counter value"]
    pub mod ot_rst_val {
        #[doc = "Register `OT_RST_VAL` reader"]
        pub type R = crate::R<OT_RST_VAL_SPEC>;
        #[doc = "Register `OT_RST_VAL` writer"]
        pub type W = crate::W<OT_RST_VAL_SPEC>;
        #[doc = "Field `OT_RST_VAL` reader - WDT timeout reset value"]
        pub type OT_RST_VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `OT_RST_VAL` writer - WDT timeout reset value"]
        pub type OT_RST_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - WDT timeout reset value"]
            #[inline(always)]
            pub fn ot_rst_val(&self) -> OT_RST_VAL_R {
                OT_RST_VAL_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - WDT timeout reset value"]
            #[inline(always)]
            #[must_use]
            pub fn ot_rst_val(&mut self) -> OT_RST_VAL_W<OT_RST_VAL_SPEC> {
                OT_RST_VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wdog timeout reset counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ot_rst_val::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ot_rst_val::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct OT_RST_VAL_SPEC;
        impl crate::RegisterSpec for OT_RST_VAL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ot_rst_val::R`](R) reader structure"]
        impl crate::Readable for OT_RST_VAL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ot_rst_val::W`](W) writer structure"]
        impl crate::Writable for OT_RST_VAL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets OT_RST_VAL to value 0"]
        impl crate::Resettable for OT_RST_VAL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "WDT_REFRESH_REG (rw) register accessor: wdog refresh register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_refresh_reg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_refresh_reg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_refresh_reg`]
module"]
    pub type WDT_REFRESH_REG = crate::Reg<wdt_refresh_reg::WDT_REFRESH_REG_SPEC>;
    #[doc = "wdog refresh register"]
    pub mod wdt_refresh_reg {
        #[doc = "Register `WDT_REFRESH_REG` reader"]
        pub type R = crate::R<WDT_REFRESH_REG_SPEC>;
        #[doc = "Register `WDT_REFRESH_REG` writer"]
        pub type W = crate::W<WDT_REFRESH_REG_SPEC>;
        #[doc = "Field `WDT_REFRESH_REG` writer - Write this register by 32'h5A45_524F to refresh wdog Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose"]
        pub type WDT_REFRESH_REG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - Write this register by 32'h5A45_524F to refresh wdog Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose"]
            #[inline(always)]
            #[must_use]
            pub fn wdt_refresh_reg(&mut self) -> WDT_REFRESH_REG_W<WDT_REFRESH_REG_SPEC> {
                WDT_REFRESH_REG_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wdog refresh register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_refresh_reg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_refresh_reg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WDT_REFRESH_REG_SPEC;
        impl crate::RegisterSpec for WDT_REFRESH_REG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_refresh_reg::R`](R) reader structure"]
        impl crate::Readable for WDT_REFRESH_REG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wdt_refresh_reg::W`](W) writer structure"]
        impl crate::Writable for WDT_REFRESH_REG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets WDT_REFRESH_REG to value 0"]
        impl crate::Resettable for WDT_REFRESH_REG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "WDT_STATUS (rw) register accessor: wdog status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_status`]
module"]
    pub type WDT_STATUS = crate::Reg<wdt_status::WDT_STATUS_SPEC>;
    #[doc = "wdog status register"]
    pub mod wdt_status {
        #[doc = "Register `WDT_STATUS` reader"]
        pub type R = crate::R<WDT_STATUS_SPEC>;
        #[doc = "Register `WDT_STATUS` writer"]
        pub type W = crate::W<WDT_STATUS_SPEC>;
        #[doc = "Field `REF_VIO` reader - Refresh fail Write one to clear the bit"]
        pub type REF_VIO_R = crate::BitReader;
        #[doc = "Field `REF_VIO` writer - Refresh fail Write one to clear the bit"]
        pub type REF_VIO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `REF_UNL_FAIL` reader - Refresh unlock fail Write one to clear the bit"]
        pub type REF_UNL_FAIL_R = crate::BitReader;
        #[doc = "Field `REF_UNL_FAIL` writer - Refresh unlock fail Write one to clear the bit"]
        pub type REF_UNL_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CTL_VIO` reader - Violate register update protection mechanism Write one to clear the bit"]
        pub type CTL_VIO_R = crate::BitReader;
        #[doc = "Field `CTL_VIO` writer - Violate register update protection mechanism Write one to clear the bit"]
        pub type CTL_VIO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CTL_UNL_FAIL` reader - Unlock ctrl reg update protection fail Write one to clear the bit"]
        pub type CTL_UNL_FAIL_R = crate::BitReader;
        #[doc = "Field `CTL_UNL_FAIL` writer - Unlock ctrl reg update protection fail Write one to clear the bit"]
        pub type CTL_UNL_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OT_INT` reader - Timeout happens, a interrupt will happen once enable bit set This bit can be cleared only by refreshing wdt or reset"]
        pub type OT_INT_R = crate::BitReader;
        #[doc = "Field `OT_RST` reader - Timeout happens, a reset will happen once enable bit set This bit can be cleared only by refreshing wdt or reset"]
        pub type OT_RST_R = crate::BitReader;
        #[doc = "Field `PARITY_ERROR` reader - parity error Write one to clear the bit"]
        pub type PARITY_ERROR_R = crate::BitReader;
        #[doc = "Field `PARITY_ERROR` writer - parity error Write one to clear the bit"]
        pub type PARITY_ERROR_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Refresh fail Write one to clear the bit"]
            #[inline(always)]
            pub fn ref_vio(&self) -> REF_VIO_R {
                REF_VIO_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Refresh unlock fail Write one to clear the bit"]
            #[inline(always)]
            pub fn ref_unl_fail(&self) -> REF_UNL_FAIL_R {
                REF_UNL_FAIL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Violate register update protection mechanism Write one to clear the bit"]
            #[inline(always)]
            pub fn ctl_vio(&self) -> CTL_VIO_R {
                CTL_VIO_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Unlock ctrl reg update protection fail Write one to clear the bit"]
            #[inline(always)]
            pub fn ctl_unl_fail(&self) -> CTL_UNL_FAIL_R {
                CTL_UNL_FAIL_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Timeout happens, a interrupt will happen once enable bit set This bit can be cleared only by refreshing wdt or reset"]
            #[inline(always)]
            pub fn ot_int(&self) -> OT_INT_R {
                OT_INT_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Timeout happens, a reset will happen once enable bit set This bit can be cleared only by refreshing wdt or reset"]
            #[inline(always)]
            pub fn ot_rst(&self) -> OT_RST_R {
                OT_RST_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - parity error Write one to clear the bit"]
            #[inline(always)]
            pub fn parity_error(&self) -> PARITY_ERROR_R {
                PARITY_ERROR_R::new(((self.bits >> 6) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Refresh fail Write one to clear the bit"]
            #[inline(always)]
            #[must_use]
            pub fn ref_vio(&mut self) -> REF_VIO_W<WDT_STATUS_SPEC> {
                REF_VIO_W::new(self, 0)
            }
            #[doc = "Bit 1 - Refresh unlock fail Write one to clear the bit"]
            #[inline(always)]
            #[must_use]
            pub fn ref_unl_fail(&mut self) -> REF_UNL_FAIL_W<WDT_STATUS_SPEC> {
                REF_UNL_FAIL_W::new(self, 1)
            }
            #[doc = "Bit 2 - Violate register update protection mechanism Write one to clear the bit"]
            #[inline(always)]
            #[must_use]
            pub fn ctl_vio(&mut self) -> CTL_VIO_W<WDT_STATUS_SPEC> {
                CTL_VIO_W::new(self, 2)
            }
            #[doc = "Bit 3 - Unlock ctrl reg update protection fail Write one to clear the bit"]
            #[inline(always)]
            #[must_use]
            pub fn ctl_unl_fail(&mut self) -> CTL_UNL_FAIL_W<WDT_STATUS_SPEC> {
                CTL_UNL_FAIL_W::new(self, 3)
            }
            #[doc = "Bit 6 - parity error Write one to clear the bit"]
            #[inline(always)]
            #[must_use]
            pub fn parity_error(&mut self) -> PARITY_ERROR_W<WDT_STATUS_SPEC> {
                PARITY_ERROR_W::new(self, 6)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wdog status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WDT_STATUS_SPEC;
        impl crate::RegisterSpec for WDT_STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_status::R`](R) reader structure"]
        impl crate::Readable for WDT_STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wdt_status::W`](W) writer structure"]
        impl crate::Writable for WDT_STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets WDT_STATUS to value 0"]
        impl crate::Resettable for WDT_STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CFG_PROT (rw) register accessor: ctrl register protection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg_prot::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg_prot::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg_prot`]
module"]
    pub type CFG_PROT = crate::Reg<cfg_prot::CFG_PROT_SPEC>;
    #[doc = "ctrl register protection register"]
    pub mod cfg_prot {
        #[doc = "Register `CFG_PROT` reader"]
        pub type R = crate::R<CFG_PROT_SPEC>;
        #[doc = "Register `CFG_PROT` writer"]
        pub type W = crate::W<CFG_PROT_SPEC>;
        #[doc = "Field `UPD_PSD` reader - The password of unlocking register update"]
        pub type UPD_PSD_R = crate::FieldReader<u16>;
        #[doc = "Field `UPD_PSD` writer - The password of unlocking register update"]
        pub type UPD_PSD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `UPD_OT_TIME` reader - The period in which register update has to be in after unlock The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle"]
        pub type UPD_OT_TIME_R = crate::FieldReader;
        #[doc = "Field `UPD_OT_TIME` writer - The period in which register update has to be in after unlock The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle"]
        pub type UPD_OT_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:15 - The password of unlocking register update"]
            #[inline(always)]
            pub fn upd_psd(&self) -> UPD_PSD_R {
                UPD_PSD_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:19 - The period in which register update has to be in after unlock The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle"]
            #[inline(always)]
            pub fn upd_ot_time(&self) -> UPD_OT_TIME_R {
                UPD_OT_TIME_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - The password of unlocking register update"]
            #[inline(always)]
            #[must_use]
            pub fn upd_psd(&mut self) -> UPD_PSD_W<CFG_PROT_SPEC> {
                UPD_PSD_W::new(self, 0)
            }
            #[doc = "Bits 16:19 - The period in which register update has to be in after unlock The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle"]
            #[inline(always)]
            #[must_use]
            pub fn upd_ot_time(&mut self) -> UPD_OT_TIME_W<CFG_PROT_SPEC> {
                UPD_OT_TIME_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "ctrl register protection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg_prot::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CFG_PROT_SPEC;
        impl crate::RegisterSpec for CFG_PROT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg_prot::R`](R) reader structure"]
        impl crate::Readable for CFG_PROT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cfg_prot::W`](W) writer structure"]
        impl crate::Writable for CFG_PROT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CFG_PROT to value 0"]
        impl crate::Resettable for CFG_PROT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "REF_PROT (rw) register accessor: refresh protection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_prot::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_prot::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ref_prot`]
module"]
    pub type REF_PROT = crate::Reg<ref_prot::REF_PROT_SPEC>;
    #[doc = "refresh protection register"]
    pub mod ref_prot {
        #[doc = "Register `REF_PROT` reader"]
        pub type R = crate::R<REF_PROT_SPEC>;
        #[doc = "Register `REF_PROT` writer"]
        pub type W = crate::W<REF_PROT_SPEC>;
        #[doc = "Field `REF_UNL_PSD` reader - The password to unlock refreshing"]
        pub type REF_UNL_PSD_R = crate::FieldReader<u16>;
        #[doc = "Field `REF_UNL_PSD` writer - The password to unlock refreshing"]
        pub type REF_UNL_PSD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - The password to unlock refreshing"]
            #[inline(always)]
            pub fn ref_unl_psd(&self) -> REF_UNL_PSD_R {
                REF_UNL_PSD_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - The password to unlock refreshing"]
            #[inline(always)]
            #[must_use]
            pub fn ref_unl_psd(&mut self) -> REF_UNL_PSD_W<REF_PROT_SPEC> {
                REF_UNL_PSD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "refresh protection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_prot::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct REF_PROT_SPEC;
        impl crate::RegisterSpec for REF_PROT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ref_prot::R`](R) reader structure"]
        impl crate::Readable for REF_PROT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ref_prot::W`](W) writer structure"]
        impl crate::Writable for REF_PROT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets REF_PROT to value 0"]
        impl crate::Resettable for REF_PROT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "WDT_EN (rw) register accessor: Wdog enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdt_en`]
module"]
    pub type WDT_EN = crate::Reg<wdt_en::WDT_EN_SPEC>;
    #[doc = "Wdog enable"]
    pub mod wdt_en {
        #[doc = "Register `WDT_EN` reader"]
        pub type R = crate::R<WDT_EN_SPEC>;
        #[doc = "Register `WDT_EN` writer"]
        pub type W = crate::W<WDT_EN_SPEC>;
        #[doc = "Field `WDOG_EN` reader - Wdog is enabled, the re-written of this register is impacted by enable lock function"]
        pub type WDOG_EN_R = crate::BitReader;
        #[doc = "Field `WDOG_EN` writer - Wdog is enabled, the re-written of this register is impacted by enable lock function"]
        pub type WDOG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Wdog is enabled, the re-written of this register is impacted by enable lock function"]
            #[inline(always)]
            pub fn wdog_en(&self) -> WDOG_EN_R {
                WDOG_EN_R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Wdog is enabled, the re-written of this register is impacted by enable lock function"]
            #[inline(always)]
            #[must_use]
            pub fn wdog_en(&mut self) -> WDOG_EN_W<WDT_EN_SPEC> {
                WDOG_EN_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Wdog enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdt_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdt_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WDT_EN_SPEC;
        impl crate::RegisterSpec for WDT_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdt_en::R`](R) reader structure"]
        impl crate::Readable for WDT_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wdt_en::W`](W) writer structure"]
        impl crate::Writable for WDT_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets WDT_EN to value 0"]
        impl crate::Resettable for WDT_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "REF_TIME (rw) register accessor: Refresh period value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ref_time`]
module"]
    pub type REF_TIME = crate::Reg<ref_time::REF_TIME_SPEC>;
    #[doc = "Refresh period value"]
    pub mod ref_time {
        #[doc = "Register `REF_TIME` reader"]
        pub type R = crate::R<REF_TIME_SPEC>;
        #[doc = "Register `REF_TIME` writer"]
        pub type W = crate::W<REF_TIME_SPEC>;
        #[doc = "Field `REFRESH_PERIOD` reader - The refresh period after refresh unlocked Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
        pub type REFRESH_PERIOD_R = crate::FieldReader<u16>;
        #[doc = "Field `REFRESH_PERIOD` writer - The refresh period after refresh unlocked Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
        pub type REFRESH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - The refresh period after refresh unlocked Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
            #[inline(always)]
            pub fn refresh_period(&self) -> REFRESH_PERIOD_R {
                REFRESH_PERIOD_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - The refresh period after refresh unlocked Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter"]
            #[inline(always)]
            #[must_use]
            pub fn refresh_period(&mut self) -> REFRESH_PERIOD_W<REF_TIME_SPEC> {
                REFRESH_PERIOD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Refresh period value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ref_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ref_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct REF_TIME_SPEC;
        impl crate::RegisterSpec for REF_TIME_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ref_time::R`](R) reader structure"]
        impl crate::Readable for REF_TIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ref_time::W`](W) writer structure"]
        impl crate::Writable for REF_TIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets REF_TIME to value 0"]
        impl crate::Resettable for REF_TIME_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "WDG1"]
pub struct WDG1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for WDG1 {}
impl WDG1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const wdg0::RegisterBlock = 0xf00b_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const wdg0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for WDG1 {
    type Target = wdg0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for WDG1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("WDG1").finish()
    }
}
#[doc = "WDG1"]
pub use self::wdg0 as wdg1;
#[doc = "PWDG"]
pub struct PWDG {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PWDG {}
impl PWDG {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const wdg0::RegisterBlock = 0xf412_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const wdg0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PWDG {
    type Target = wdg0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PWDG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWDG").finish()
    }
}
#[doc = "PWDG"]
pub use self::wdg0 as pwdg;
#[doc = "DMAMUX"]
pub struct DMAMUX {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for DMAMUX {}
impl DMAMUX {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const dmamux::RegisterBlock = 0xf00c_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const dmamux::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for DMAMUX {
    type Target = dmamux::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for DMAMUX {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DMAMUX").finish()
    }
}
#[doc = "DMAMUX"]
pub mod dmamux {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        muxcfg: [MUXCFG; 32],
    }
    impl RegisterBlock {
        #[doc = "0x00..0x80 - no description available"]
        #[inline(always)]
        pub const fn muxcfg(&self, n: usize) -> &MUXCFG {
            &self.muxcfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x80 - no description available"]
        #[inline(always)]
        pub fn muxcfg_iter(&self) -> impl Iterator<Item = &MUXCFG> {
            self.muxcfg.iter()
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux0(&self) -> &MUXCFG {
            self.muxcfg(0)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux1(&self) -> &MUXCFG {
            self.muxcfg(1)
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux2(&self) -> &MUXCFG {
            self.muxcfg(2)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux3(&self) -> &MUXCFG {
            self.muxcfg(3)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux4(&self) -> &MUXCFG {
            self.muxcfg(4)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux5(&self) -> &MUXCFG {
            self.muxcfg(5)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux6(&self) -> &MUXCFG {
            self.muxcfg(6)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux7(&self) -> &MUXCFG {
            self.muxcfg(7)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux8(&self) -> &MUXCFG {
            self.muxcfg(8)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux9(&self) -> &MUXCFG {
            self.muxcfg(9)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux10(&self) -> &MUXCFG {
            self.muxcfg(10)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux11(&self) -> &MUXCFG {
            self.muxcfg(11)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux12(&self) -> &MUXCFG {
            self.muxcfg(12)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux13(&self) -> &MUXCFG {
            self.muxcfg(13)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux14(&self) -> &MUXCFG {
            self.muxcfg(14)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux15(&self) -> &MUXCFG {
            self.muxcfg(15)
        }
        #[doc = "0x40 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux16(&self) -> &MUXCFG {
            self.muxcfg(16)
        }
        #[doc = "0x44 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux17(&self) -> &MUXCFG {
            self.muxcfg(17)
        }
        #[doc = "0x48 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux18(&self) -> &MUXCFG {
            self.muxcfg(18)
        }
        #[doc = "0x4c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux19(&self) -> &MUXCFG {
            self.muxcfg(19)
        }
        #[doc = "0x50 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux20(&self) -> &MUXCFG {
            self.muxcfg(20)
        }
        #[doc = "0x54 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux21(&self) -> &MUXCFG {
            self.muxcfg(21)
        }
        #[doc = "0x58 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux22(&self) -> &MUXCFG {
            self.muxcfg(22)
        }
        #[doc = "0x5c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux23(&self) -> &MUXCFG {
            self.muxcfg(23)
        }
        #[doc = "0x60 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux24(&self) -> &MUXCFG {
            self.muxcfg(24)
        }
        #[doc = "0x64 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux25(&self) -> &MUXCFG {
            self.muxcfg(25)
        }
        #[doc = "0x68 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux26(&self) -> &MUXCFG {
            self.muxcfg(26)
        }
        #[doc = "0x6c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux27(&self) -> &MUXCFG {
            self.muxcfg(27)
        }
        #[doc = "0x70 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux28(&self) -> &MUXCFG {
            self.muxcfg(28)
        }
        #[doc = "0x74 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux29(&self) -> &MUXCFG {
            self.muxcfg(29)
        }
        #[doc = "0x78 - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux30(&self) -> &MUXCFG {
            self.muxcfg(30)
        }
        #[doc = "0x7c - no description available"]
        #[inline(always)]
        pub const fn muxcfghdma_mux31(&self) -> &MUXCFG {
            self.muxcfg(31)
        }
    }
    #[doc = "MUXCFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`muxcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`muxcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@muxcfg`]
module"]
    pub type MUXCFG = crate::Reg<muxcfg::MUXCFG_SPEC>;
    #[doc = "no description available"]
    pub mod muxcfg {
        #[doc = "Register `MUXCFG[%s]` reader"]
        pub type R = crate::R<MUXCFG_SPEC>;
        #[doc = "Register `MUXCFG[%s]` writer"]
        pub type W = crate::W<MUXCFG_SPEC>;
        #[doc = "Field `SOURCE` reader - DMA Channel Source Specifies which DMA source, if any, is routed to a particular DMA channel. See the \"DMA MUX Mapping\""]
        pub type SOURCE_R = crate::FieldReader;
        #[doc = "Field `SOURCE` writer - DMA Channel Source Specifies which DMA source, if any, is routed to a particular DMA channel. See the \"DMA MUX Mapping\""]
        pub type SOURCE_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `ENABLE` reader - DMA Mux Channel Enable Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b - DMA Mux channel is disabled 1b - DMA Mux channel is enabled"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `ENABLE` writer - DMA Mux Channel Enable Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b - DMA Mux channel is disabled 1b - DMA Mux channel is enabled"]
        pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:6 - DMA Channel Source Specifies which DMA source, if any, is routed to a particular DMA channel. See the \"DMA MUX Mapping\""]
            #[inline(always)]
            pub fn source(&self) -> SOURCE_R {
                SOURCE_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bit 31 - DMA Mux Channel Enable Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b - DMA Mux channel is disabled 1b - DMA Mux channel is enabled"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - DMA Channel Source Specifies which DMA source, if any, is routed to a particular DMA channel. See the \"DMA MUX Mapping\""]
            #[inline(always)]
            #[must_use]
            pub fn source(&mut self) -> SOURCE_W<MUXCFG_SPEC> {
                SOURCE_W::new(self, 0)
            }
            #[doc = "Bit 31 - DMA Mux Channel Enable Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 0b - DMA Mux channel is disabled 1b - DMA Mux channel is enabled"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<MUXCFG_SPEC> {
                ENABLE_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`muxcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`muxcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MUXCFG_SPEC;
        impl crate::RegisterSpec for MUXCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`muxcfg::R`](R) reader structure"]
        impl crate::Readable for MUXCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`muxcfg::W`](W) writer structure"]
        impl crate::Writable for MUXCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets MUXCFG[%s]
to value 0"]
        impl crate::Resettable for MUXCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "HDMA"]
pub struct HDMA {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for HDMA {}
impl HDMA {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const hdma::RegisterBlock = 0xf00c_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const hdma::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for HDMA {
    type Target = hdma::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for HDMA {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("HDMA").finish()
    }
}
#[doc = "HDMA"]
pub mod hdma {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x04],
        idmisc: IDMISC,
        _reserved1: [u8; 0x08],
        dmacfg: DMACFG,
        dmactrl: DMACTRL,
        ch_abort: CH_ABORT,
        _reserved4: [u8; 0x08],
        inthalfsts: INTHALFSTS,
        inttcsts: INTTCSTS,
        intabortsts: INTABORTSTS,
        interrsts: INTERRSTS,
        ch_en: CH_EN,
        _reserved9: [u8; 0x08],
        chctrl: (),
    }
    impl RegisterBlock {
        #[doc = "0x04 - ID Misc"]
        #[inline(always)]
        pub const fn idmisc(&self) -> &IDMISC {
            &self.idmisc
        }
        #[doc = "0x10 - DMAC Configuration Register"]
        #[inline(always)]
        pub const fn dmacfg(&self) -> &DMACFG {
            &self.dmacfg
        }
        #[doc = "0x14 - DMAC Control Register"]
        #[inline(always)]
        pub const fn dmactrl(&self) -> &DMACTRL {
            &self.dmactrl
        }
        #[doc = "0x18 - Channel Abort Register"]
        #[inline(always)]
        pub const fn ch_abort(&self) -> &CH_ABORT {
            &self.ch_abort
        }
        #[doc = "0x24 - Harlf Complete Interrupt Status"]
        #[inline(always)]
        pub const fn inthalfsts(&self) -> &INTHALFSTS {
            &self.inthalfsts
        }
        #[doc = "0x28 - Trans Complete Interrupt Status Register"]
        #[inline(always)]
        pub const fn inttcsts(&self) -> &INTTCSTS {
            &self.inttcsts
        }
        #[doc = "0x2c - Abort Interrupt Status Register"]
        #[inline(always)]
        pub const fn intabortsts(&self) -> &INTABORTSTS {
            &self.intabortsts
        }
        #[doc = "0x30 - Error Interrupt Status Register"]
        #[inline(always)]
        pub const fn interrsts(&self) -> &INTERRSTS {
            &self.interrsts
        }
        #[doc = "0x34 - Channel Enable Register"]
        #[inline(always)]
        pub const fn ch_en(&self) -> &CH_EN {
            &self.ch_en
        }
        #[doc = "0x40..0x3c0 - no description available"]
        #[inline(always)]
        pub const fn chctrl(&self, n: usize) -> &CHCTRL {
            #[allow(clippy::no_effect)]
            [(); 32][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(64)
                    .add(32 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x40..0x3c0 - no description available"]
        #[inline(always)]
        pub fn chctrl_iter(&self) -> impl Iterator<Item = &CHCTRL> {
            (0..32).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(64)
                    .add(32 * n)
                    .cast()
            })
        }
        #[doc = "0x40..0x5c - no description available"]
        #[inline(always)]
        pub const fn chctrlch0(&self) -> &CHCTRL {
            self.chctrl(0)
        }
        #[doc = "0x60..0x7c - no description available"]
        #[inline(always)]
        pub const fn chctrlch1(&self) -> &CHCTRL {
            self.chctrl(1)
        }
        #[doc = "0x80..0x9c - no description available"]
        #[inline(always)]
        pub const fn chctrlch2(&self) -> &CHCTRL {
            self.chctrl(2)
        }
        #[doc = "0xa0..0xbc - no description available"]
        #[inline(always)]
        pub const fn chctrlch3(&self) -> &CHCTRL {
            self.chctrl(3)
        }
        #[doc = "0xc0..0xdc - no description available"]
        #[inline(always)]
        pub const fn chctrlch4(&self) -> &CHCTRL {
            self.chctrl(4)
        }
        #[doc = "0xe0..0xfc - no description available"]
        #[inline(always)]
        pub const fn chctrlch5(&self) -> &CHCTRL {
            self.chctrl(5)
        }
        #[doc = "0x100..0x11c - no description available"]
        #[inline(always)]
        pub const fn chctrlch6(&self) -> &CHCTRL {
            self.chctrl(6)
        }
        #[doc = "0x120..0x13c - no description available"]
        #[inline(always)]
        pub const fn chctrlch7(&self) -> &CHCTRL {
            self.chctrl(7)
        }
        #[doc = "0x140..0x15c - no description available"]
        #[inline(always)]
        pub const fn chctrlch8(&self) -> &CHCTRL {
            self.chctrl(8)
        }
        #[doc = "0x160..0x17c - no description available"]
        #[inline(always)]
        pub const fn chctrlch9(&self) -> &CHCTRL {
            self.chctrl(9)
        }
        #[doc = "0x180..0x19c - no description available"]
        #[inline(always)]
        pub const fn chctrlch10(&self) -> &CHCTRL {
            self.chctrl(10)
        }
        #[doc = "0x1a0..0x1bc - no description available"]
        #[inline(always)]
        pub const fn chctrlch11(&self) -> &CHCTRL {
            self.chctrl(11)
        }
        #[doc = "0x1c0..0x1dc - no description available"]
        #[inline(always)]
        pub const fn chctrlch12(&self) -> &CHCTRL {
            self.chctrl(12)
        }
        #[doc = "0x1e0..0x1fc - no description available"]
        #[inline(always)]
        pub const fn chctrlch13(&self) -> &CHCTRL {
            self.chctrl(13)
        }
        #[doc = "0x200..0x21c - no description available"]
        #[inline(always)]
        pub const fn chctrlch14(&self) -> &CHCTRL {
            self.chctrl(14)
        }
        #[doc = "0x220..0x23c - no description available"]
        #[inline(always)]
        pub const fn chctrlch15(&self) -> &CHCTRL {
            self.chctrl(15)
        }
        #[doc = "0x240..0x25c - no description available"]
        #[inline(always)]
        pub const fn chctrlch16(&self) -> &CHCTRL {
            self.chctrl(16)
        }
        #[doc = "0x260..0x27c - no description available"]
        #[inline(always)]
        pub const fn chctrlch17(&self) -> &CHCTRL {
            self.chctrl(17)
        }
        #[doc = "0x280..0x29c - no description available"]
        #[inline(always)]
        pub const fn chctrlch18(&self) -> &CHCTRL {
            self.chctrl(18)
        }
        #[doc = "0x2a0..0x2bc - no description available"]
        #[inline(always)]
        pub const fn chctrlch19(&self) -> &CHCTRL {
            self.chctrl(19)
        }
        #[doc = "0x2c0..0x2dc - no description available"]
        #[inline(always)]
        pub const fn chctrlch20(&self) -> &CHCTRL {
            self.chctrl(20)
        }
        #[doc = "0x2e0..0x2fc - no description available"]
        #[inline(always)]
        pub const fn chctrlch21(&self) -> &CHCTRL {
            self.chctrl(21)
        }
        #[doc = "0x300..0x31c - no description available"]
        #[inline(always)]
        pub const fn chctrlch22(&self) -> &CHCTRL {
            self.chctrl(22)
        }
        #[doc = "0x320..0x33c - no description available"]
        #[inline(always)]
        pub const fn chctrlch23(&self) -> &CHCTRL {
            self.chctrl(23)
        }
        #[doc = "0x340..0x35c - no description available"]
        #[inline(always)]
        pub const fn chctrlch24(&self) -> &CHCTRL {
            self.chctrl(24)
        }
        #[doc = "0x360..0x37c - no description available"]
        #[inline(always)]
        pub const fn chctrlch25(&self) -> &CHCTRL {
            self.chctrl(25)
        }
        #[doc = "0x380..0x39c - no description available"]
        #[inline(always)]
        pub const fn chctrlch26(&self) -> &CHCTRL {
            self.chctrl(26)
        }
        #[doc = "0x3a0..0x3bc - no description available"]
        #[inline(always)]
        pub const fn chctrlch27(&self) -> &CHCTRL {
            self.chctrl(27)
        }
        #[doc = "0x3c0..0x3dc - no description available"]
        #[inline(always)]
        pub const fn chctrlch28(&self) -> &CHCTRL {
            self.chctrl(28)
        }
        #[doc = "0x3e0..0x3fc - no description available"]
        #[inline(always)]
        pub const fn chctrlch29(&self) -> &CHCTRL {
            self.chctrl(29)
        }
        #[doc = "0x400..0x41c - no description available"]
        #[inline(always)]
        pub const fn chctrlch30(&self) -> &CHCTRL {
            self.chctrl(30)
        }
        #[doc = "0x420..0x43c - no description available"]
        #[inline(always)]
        pub const fn chctrlch31(&self) -> &CHCTRL {
            self.chctrl(31)
        }
    }
    #[doc = "IDMisc (rw) register accessor: ID Misc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idmisc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idmisc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idmisc`]
module"]
    pub type IDMISC = crate::Reg<idmisc::IDMISC_SPEC>;
    #[doc = "ID Misc"]
    pub mod idmisc {
        #[doc = "Register `IDMisc` reader"]
        pub type R = crate::R<IDMISC_SPEC>;
        #[doc = "Register `IDMisc` writer"]
        pub type W = crate::W<IDMISC_SPEC>;
        #[doc = "Field `CURCHAN` reader - current channel in used"]
        pub type CURCHAN_R = crate::FieldReader;
        #[doc = "Field `DMASTATE` reader - DMA state machine localparam ST_IDLE = 3'b000; localparam ST_READ = 3'b001; localparam ST_READ_ACK = 3'b010; localparam ST_WRITE = 3'b011; localparam ST_WRITE_ACK = 3'b100; localparam ST_LL = 3'b101; localparam ST_END = 3'b110; localparam ST_END_WAIT = 3'b111;"]
        pub type DMASTATE_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 8:12 - current channel in used"]
            #[inline(always)]
            pub fn curchan(&self) -> CURCHAN_R {
                CURCHAN_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 13:15 - DMA state machine localparam ST_IDLE = 3'b000; localparam ST_READ = 3'b001; localparam ST_READ_ACK = 3'b010; localparam ST_WRITE = 3'b011; localparam ST_WRITE_ACK = 3'b100; localparam ST_LL = 3'b101; localparam ST_END = 3'b110; localparam ST_END_WAIT = 3'b111;"]
            #[inline(always)]
            pub fn dmastate(&self) -> DMASTATE_R {
                DMASTATE_R::new(((self.bits >> 13) & 7) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "ID Misc\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idmisc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idmisc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IDMISC_SPEC;
        impl crate::RegisterSpec for IDMISC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`idmisc::R`](R) reader structure"]
        impl crate::Readable for IDMISC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`idmisc::W`](W) writer structure"]
        impl crate::Writable for IDMISC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IDMisc to value 0"]
        impl crate::Resettable for IDMISC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DMACfg (rw) register accessor: DMAC Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacfg`]
module"]
    pub type DMACFG = crate::Reg<dmacfg::DMACFG_SPEC>;
    #[doc = "DMAC Configuration Register"]
    pub mod dmacfg {
        #[doc = "Register `DMACfg` reader"]
        pub type R = crate::R<DMACFG_SPEC>;
        #[doc = "Register `DMACfg` writer"]
        pub type W = crate::W<DMACFG_SPEC>;
        #[doc = "Field `CHANNELNUM` reader - Channel number 0x1: 1 channel 0x2: 2 channels ... 0x8: 8 channels Others: Invalid"]
        pub type CHANNELNUM_R = crate::FieldReader;
        #[doc = "Field `FIFODEPTH` reader - FIFO depth 0x4: 4 entries 0x8: 8 entries 0x10: 16 entries 0x20: 32 entries Others: Invalid"]
        pub type FIFODEPTH_R = crate::FieldReader;
        #[doc = "Field `REQNUM` reader - Request/acknowledge pair number 0x0: 0 pair 0x1: 1 pair 0x2: 2 pairs ... 0x10: 16 pairs"]
        pub type REQNUM_R = crate::FieldReader;
        #[doc = "Field `BUSNUM` reader - AXI bus interface number 0x0: 1 AXI bus 0x1: 2 AXI busses"]
        pub type BUSNUM_R = crate::BitReader;
        #[doc = "Field `CORENUM` reader - DMA core number 0x0: 1 core 0x1: 2 cores"]
        pub type CORENUM_R = crate::BitReader;
        #[doc = "Field `ADDRWIDTH` reader - AXI bus address width 0x18: 24 bits 0x19: 25 bits ... 0x40: 64 bits Others: Invalid"]
        pub type ADDRWIDTH_R = crate::FieldReader;
        #[doc = "Field `DATAWIDTH` reader - AXI bus data width 0x0: 32 bits 0x1: 64 bits 0x2: 128 bits 0x3: 256 bits"]
        pub type DATAWIDTH_R = crate::FieldReader;
        #[doc = "Field `REQSYNC` reader - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. 0x0: Request synchronization is not configured 0x1: Request synchronization is configured"]
        pub type REQSYNC_R = crate::BitReader;
        #[doc = "Field `CHAINXFR` reader - Chain transfer 0x0: Chain transfer is not configured 0x1: Chain transfer is configured"]
        pub type CHAINXFR_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:3 - Channel number 0x1: 1 channel 0x2: 2 channels ... 0x8: 8 channels Others: Invalid"]
            #[inline(always)]
            pub fn channelnum(&self) -> CHANNELNUM_R {
                CHANNELNUM_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:9 - FIFO depth 0x4: 4 entries 0x8: 8 entries 0x10: 16 entries 0x20: 32 entries Others: Invalid"]
            #[inline(always)]
            pub fn fifodepth(&self) -> FIFODEPTH_R {
                FIFODEPTH_R::new(((self.bits >> 4) & 0x3f) as u8)
            }
            #[doc = "Bits 10:14 - Request/acknowledge pair number 0x0: 0 pair 0x1: 1 pair 0x2: 2 pairs ... 0x10: 16 pairs"]
            #[inline(always)]
            pub fn reqnum(&self) -> REQNUM_R {
                REQNUM_R::new(((self.bits >> 10) & 0x1f) as u8)
            }
            #[doc = "Bit 15 - AXI bus interface number 0x0: 1 AXI bus 0x1: 2 AXI busses"]
            #[inline(always)]
            pub fn busnum(&self) -> BUSNUM_R {
                BUSNUM_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - DMA core number 0x0: 1 core 0x1: 2 cores"]
            #[inline(always)]
            pub fn corenum(&self) -> CORENUM_R {
                CORENUM_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bits 17:23 - AXI bus address width 0x18: 24 bits 0x19: 25 bits ... 0x40: 64 bits Others: Invalid"]
            #[inline(always)]
            pub fn addrwidth(&self) -> ADDRWIDTH_R {
                ADDRWIDTH_R::new(((self.bits >> 17) & 0x7f) as u8)
            }
            #[doc = "Bits 24:25 - AXI bus data width 0x0: 32 bits 0x1: 64 bits 0x2: 128 bits 0x3: 256 bits"]
            #[inline(always)]
            pub fn datawidth(&self) -> DATAWIDTH_R {
                DATAWIDTH_R::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bit 30 - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. 0x0: Request synchronization is not configured 0x1: Request synchronization is configured"]
            #[inline(always)]
            pub fn reqsync(&self) -> REQSYNC_R {
                REQSYNC_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - Chain transfer 0x0: Chain transfer is not configured 0x1: Chain transfer is configured"]
            #[inline(always)]
            pub fn chainxfr(&self) -> CHAINXFR_R {
                CHAINXFR_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DMAC Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DMACFG_SPEC;
        impl crate::RegisterSpec for DMACFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmacfg::R`](R) reader structure"]
        impl crate::Readable for DMACFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dmacfg::W`](W) writer structure"]
        impl crate::Writable for DMACFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DMACfg to value 0"]
        impl crate::Resettable for DMACFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DMACtrl (rw) register accessor: DMAC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmactrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmactrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactrl`]
module"]
    pub type DMACTRL = crate::Reg<dmactrl::DMACTRL_SPEC>;
    #[doc = "DMAC Control Register"]
    pub mod dmactrl {
        #[doc = "Register `DMACtrl` reader"]
        pub type R = crate::R<DMACTRL_SPEC>;
        #[doc = "Register `DMACtrl` writer"]
        pub type W = crate::W<DMACTRL_SPEC>;
        #[doc = "Field `RESET` writer - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. Note: The software reset may cause the in-completion of AXI transaction."]
        pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. Note: The software reset may cause the in-completion of AXI transaction."]
            #[inline(always)]
            #[must_use]
            pub fn reset(&mut self) -> RESET_W<DMACTRL_SPEC> {
                RESET_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DMAC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmactrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmactrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DMACTRL_SPEC;
        impl crate::RegisterSpec for DMACTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmactrl::R`](R) reader structure"]
        impl crate::Readable for DMACTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dmactrl::W`](W) writer structure"]
        impl crate::Writable for DMACTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DMACtrl to value 0"]
        impl crate::Resettable for DMACTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ChAbort (rw) register accessor: Channel Abort Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_abort::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_abort::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_abort`]
module"]
    pub type CH_ABORT = crate::Reg<ch_abort::CH_ABORT_SPEC>;
    #[doc = "Channel Abort Register"]
    pub mod ch_abort {
        #[doc = "Register `ChAbort` reader"]
        pub type R = crate::R<CH_ABORT_SPEC>;
        #[doc = "Register `ChAbort` writer"]
        pub type W = crate::W<CH_ABORT_SPEC>;
        #[doc = "Field `CHABORT` writer - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels)"]
        pub type CHABORT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels)"]
            #[inline(always)]
            #[must_use]
            pub fn chabort(&mut self) -> CHABORT_W<CH_ABORT_SPEC> {
                CHABORT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Channel Abort Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_abort::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_abort::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CH_ABORT_SPEC;
        impl crate::RegisterSpec for CH_ABORT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ch_abort::R`](R) reader structure"]
        impl crate::Readable for CH_ABORT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ch_abort::W`](W) writer structure"]
        impl crate::Writable for CH_ABORT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ChAbort to value 0"]
        impl crate::Resettable for CH_ABORT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INTHALFSTS (rw) register accessor: Harlf Complete Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inthalfsts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inthalfsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inthalfsts`]
module"]
    pub type INTHALFSTS = crate::Reg<inthalfsts::INTHALFSTS_SPEC>;
    #[doc = "Harlf Complete Interrupt Status"]
    pub mod inthalfsts {
        #[doc = "Register `INTHALFSTS` reader"]
        pub type R = crate::R<INTHALFSTS_SPEC>;
        #[doc = "Register `INTHALFSTS` writer"]
        pub type W = crate::W<INTHALFSTS_SPEC>;
        #[doc = "Field `STS` reader - half transfer done irq status"]
        pub type STS_R = crate::FieldReader<u32>;
        #[doc = "Field `STS` writer - half transfer done irq status"]
        pub type STS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - half transfer done irq status"]
            #[inline(always)]
            pub fn sts(&self) -> STS_R {
                STS_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - half transfer done irq status"]
            #[inline(always)]
            #[must_use]
            pub fn sts(&mut self) -> STS_W<INTHALFSTS_SPEC> {
                STS_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Harlf Complete Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inthalfsts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inthalfsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INTHALFSTS_SPEC;
        impl crate::RegisterSpec for INTHALFSTS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`inthalfsts::R`](R) reader structure"]
        impl crate::Readable for INTHALFSTS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`inthalfsts::W`](W) writer structure"]
        impl crate::Writable for INTHALFSTS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INTHALFSTS to value 0"]
        impl crate::Resettable for INTHALFSTS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INTTCSTS (rw) register accessor: Trans Complete Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inttcsts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inttcsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inttcsts`]
module"]
    pub type INTTCSTS = crate::Reg<inttcsts::INTTCSTS_SPEC>;
    #[doc = "Trans Complete Interrupt Status Register"]
    pub mod inttcsts {
        #[doc = "Register `INTTCSTS` reader"]
        pub type R = crate::R<INTTCSTS_SPEC>;
        #[doc = "Register `INTTCSTS` writer"]
        pub type W = crate::W<INTTCSTS_SPEC>;
        #[doc = "Field `STS` writer - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. 0x0: Channel n has no terminal count status 0x1: Channel n has terminal count status"]
        pub type STS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. 0x0: Channel n has no terminal count status 0x1: Channel n has terminal count status"]
            #[inline(always)]
            #[must_use]
            pub fn sts(&mut self) -> STS_W<INTTCSTS_SPEC> {
                STS_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Trans Complete Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inttcsts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inttcsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INTTCSTS_SPEC;
        impl crate::RegisterSpec for INTTCSTS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`inttcsts::R`](R) reader structure"]
        impl crate::Readable for INTTCSTS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`inttcsts::W`](W) writer structure"]
        impl crate::Writable for INTTCSTS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INTTCSTS to value 0"]
        impl crate::Resettable for INTTCSTS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INTABORTSTS (rw) register accessor: Abort Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intabortsts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intabortsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intabortsts`]
module"]
    pub type INTABORTSTS = crate::Reg<intabortsts::INTABORTSTS_SPEC>;
    #[doc = "Abort Interrupt Status Register"]
    pub mod intabortsts {
        #[doc = "Register `INTABORTSTS` reader"]
        pub type R = crate::R<INTABORTSTS_SPEC>;
        #[doc = "Register `INTABORTSTS` writer"]
        pub type W = crate::W<INTABORTSTS_SPEC>;
        #[doc = "Field `STS` writer - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. 0x0: Channel n has no abort status 0x1: Channel n has abort status"]
        pub type STS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. 0x0: Channel n has no abort status 0x1: Channel n has abort status"]
            #[inline(always)]
            #[must_use]
            pub fn sts(&mut self) -> STS_W<INTABORTSTS_SPEC> {
                STS_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Abort Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intabortsts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intabortsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INTABORTSTS_SPEC;
        impl crate::RegisterSpec for INTABORTSTS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`intabortsts::R`](R) reader structure"]
        impl crate::Readable for INTABORTSTS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`intabortsts::W`](W) writer structure"]
        impl crate::Writable for INTABORTSTS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INTABORTSTS to value 0"]
        impl crate::Resettable for INTABORTSTS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INTERRSTS (rw) register accessor: Error Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrsts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrsts`]
module"]
    pub type INTERRSTS = crate::Reg<interrsts::INTERRSTS_SPEC>;
    #[doc = "Error Interrupt Status Register"]
    pub mod interrsts {
        #[doc = "Register `INTERRSTS` reader"]
        pub type R = crate::R<INTERRSTS_SPEC>;
        #[doc = "Register `INTERRSTS` writer"]
        pub type W = crate::W<INTERRSTS_SPEC>;
        #[doc = "Field `STS` writer - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - Bus error - Unaligned address - Unaligned transfer width - Reserved configuration 0x0: Channel n has no error status 0x1: Channel n has error status"]
        pub type STS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - Bus error - Unaligned address - Unaligned transfer width - Reserved configuration 0x0: Channel n has no error status 0x1: Channel n has error status"]
            #[inline(always)]
            #[must_use]
            pub fn sts(&mut self) -> STS_W<INTERRSTS_SPEC> {
                STS_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Error Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrsts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INTERRSTS_SPEC;
        impl crate::RegisterSpec for INTERRSTS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`interrsts::R`](R) reader structure"]
        impl crate::Readable for INTERRSTS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`interrsts::W`](W) writer structure"]
        impl crate::Writable for INTERRSTS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INTERRSTS to value 0"]
        impl crate::Resettable for INTERRSTS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ChEN (rw) register accessor: Channel Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_en`]
module"]
    pub type CH_EN = crate::Reg<ch_en::CH_EN_SPEC>;
    #[doc = "Channel Enable Register"]
    pub mod ch_en {
        #[doc = "Register `ChEN` reader"]
        pub type R = crate::R<CH_EN_SPEC>;
        #[doc = "Register `ChEN` writer"]
        pub type W = crate::W<CH_EN_SPEC>;
        #[doc = "Field `CHEN` reader - Alias of the Enable field of all ChnCtrl registers"]
        pub type CHEN_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Alias of the Enable field of all ChnCtrl registers"]
            #[inline(always)]
            pub fn chen(&self) -> CHEN_R {
                CHEN_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Channel Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ch_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CH_EN_SPEC;
        impl crate::RegisterSpec for CH_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ch_en::R`](R) reader structure"]
        impl crate::Readable for CH_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ch_en::W`](W) writer structure"]
        impl crate::Writable for CH_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ChEN to value 0"]
        impl crate::Resettable for CH_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::chctrl::CHCTRL;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod chctrl {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct CHCTRL {
            ctrl: CTRL,
            tran_size: TRAN_SIZE,
            src_addr: SRC_ADDR,
            chan_req_ctrl: CHAN_REQ_CTRL,
            dst_addr: DST_ADDR,
            _reserved5: [u8; 0x04],
            llpointer: LLPOINTER,
        }
        impl CHCTRL {
            #[doc = "0x00 - Channel &amp;index0 Control Register"]
            #[inline(always)]
            pub const fn ctrl(&self) -> &CTRL {
                &self.ctrl
            }
            #[doc = "0x04 - Channel &amp;index0Transfer Size Register"]
            #[inline(always)]
            pub const fn tran_size(&self) -> &TRAN_SIZE {
                &self.tran_size
            }
            #[doc = "0x08 - Channel &amp;index0 Source Address Low Part Register"]
            #[inline(always)]
            pub const fn src_addr(&self) -> &SRC_ADDR {
                &self.src_addr
            }
            #[doc = "0x0c - Channel &amp;index0 DMA Request Control Register"]
            #[inline(always)]
            pub const fn chan_req_ctrl(&self) -> &CHAN_REQ_CTRL {
                &self.chan_req_ctrl
            }
            #[doc = "0x10 - Channel &amp;index0 Destination Address Low Part Register"]
            #[inline(always)]
            pub const fn dst_addr(&self) -> &DST_ADDR {
                &self.dst_addr
            }
            #[doc = "0x18 - Channel &amp;index0 Linked List Pointer Low Part Register"]
            #[inline(always)]
            pub const fn llpointer(&self) -> &LLPOINTER {
                &self.llpointer
            }
        }
        #[doc = "Ctrl (rw) register accessor: Channel &amp;index0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
        pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
        #[doc = "Channel &amp;index0 Control Register"]
        pub mod ctrl {
            #[doc = "Register `Ctrl` reader"]
            pub type R = crate::R<CTRL_SPEC>;
            #[doc = "Register `Ctrl` writer"]
            pub type W = crate::W<CTRL_SPEC>;
            #[doc = "Field `ENABLE` reader - Channel enable bit 0x0: Disable 0x1: Enable"]
            pub type ENABLE_R = crate::BitReader;
            #[doc = "Field `ENABLE` writer - Channel enable bit 0x0: Disable 0x1: Enable"]
            pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INTTCMASK` reader - Channel terminal count interrupt mask 0x0: Allow the terminal count interrupt to be triggered 0x1: Disable the terminal count interrupt"]
            pub type INTTCMASK_R = crate::BitReader;
            #[doc = "Field `INTTCMASK` writer - Channel terminal count interrupt mask 0x0: Allow the terminal count interrupt to be triggered 0x1: Disable the terminal count interrupt"]
            pub type INTTCMASK_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INTERRMASK` reader - Channel error interrupt mask 0x0: Allow the error interrupt to be triggered 0x1: Disable the error interrupt"]
            pub type INTERRMASK_R = crate::BitReader;
            #[doc = "Field `INTERRMASK` writer - Channel error interrupt mask 0x0: Allow the error interrupt to be triggered 0x1: Disable the error interrupt"]
            pub type INTERRMASK_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INTABTMASK` reader - Channel abort interrupt mask 0x0: Allow the abort interrupt to be triggered 0x1: Disable the abort interrupt"]
            pub type INTABTMASK_R = crate::BitReader;
            #[doc = "Field `INTABTMASK` writer - Channel abort interrupt mask 0x0: Allow the abort interrupt to be triggered 0x1: Disable the abort interrupt"]
            pub type INTABTMASK_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INTHALFCNTMASK` reader - Channel half interrupt mask 0x0: Allow the half interrupt to be triggered 0x1: Disable the half interrupt"]
            pub type INTHALFCNTMASK_R = crate::BitReader;
            #[doc = "Field `INTHALFCNTMASK` writer - Channel half interrupt mask 0x0: Allow the half interrupt to be triggered 0x1: Disable the half interrupt"]
            pub type INTHALFCNTMASK_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DSTADDRCTRL` reader - Destination address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
            pub type DSTADDRCTRL_R = crate::FieldReader;
            #[doc = "Field `DSTADDRCTRL` writer - Destination address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
            pub type DSTADDRCTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `SRCADDRCTRL` reader - Source address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
            pub type SRCADDRCTRL_R = crate::FieldReader;
            #[doc = "Field `SRCADDRCTRL` writer - Source address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
            pub type SRCADDRCTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `DSTMODE` reader - Destination DMA handshake mode 0x0: Normal mode 0x1: Handshake mode the difference bewteen Source/Destination handshake mode is: the dma block will response hardware request after read in Source handshake mode; the dma block will response hardware request after write in Destination handshake mode; NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown."]
            pub type DSTMODE_R = crate::BitReader;
            #[doc = "Field `DSTMODE` writer - Destination DMA handshake mode 0x0: Normal mode 0x1: Handshake mode the difference bewteen Source/Destination handshake mode is: the dma block will response hardware request after read in Source handshake mode; the dma block will response hardware request after write in Destination handshake mode; NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown."]
            pub type DSTMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SRCMODE` reader - Source DMA handshake mode 0x0: Normal mode 0x1: Handshake mode Normal mode is enabled and started by software set Enable bit; Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block"]
            pub type SRCMODE_R = crate::BitReader;
            #[doc = "Field `SRCMODE` writer - Source DMA handshake mode 0x0: Normal mode 0x1: Handshake mode Normal mode is enabled and started by software set Enable bit; Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block"]
            pub type SRCMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DSTWIDTH` reader - Destination transfer width. Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
            pub type DSTWIDTH_R = crate::FieldReader;
            #[doc = "Field `DSTWIDTH` writer - Destination transfer width. Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
            pub type DSTWIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `SRCWIDTH` reader - Source transfer width 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
            pub type SRCWIDTH_R = crate::FieldReader;
            #[doc = "Field `SRCWIDTH` writer - Source transfer width 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
            pub type SRCWIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `SRCBURSTSIZE` reader - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x0: 1 transfer 0x1: 2 transfers 0x2: 4 transfers 0x3: 8 transfers 0x4: 16 transfers 0x5: 32 transfers 0x6: 64 transfers 0x7: 128 transfers 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception"]
            pub type SRCBURSTSIZE_R = crate::FieldReader;
            #[doc = "Field `SRCBURSTSIZE` writer - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x0: 1 transfer 0x1: 2 transfers 0x2: 4 transfers 0x3: 8 transfers 0x4: 16 transfers 0x5: 32 transfers 0x6: 64 transfers 0x7: 128 transfers 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception"]
            pub type SRCBURSTSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `BURSTOPT` reader - set to change burst_size definition"]
            pub type BURSTOPT_R = crate::BitReader;
            #[doc = "Field `BURSTOPT` writer - set to change burst_size definition"]
            pub type BURSTOPT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PRIORITY` reader - Channel priority level 0x0: Lower priority 0x1: Higher priority"]
            pub type PRIORITY_R = crate::BitReader;
            #[doc = "Field `PRIORITY` writer - Channel priority level 0x0: Lower priority 0x1: Higher priority"]
            pub type PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `HANDSHAKEOPT` reader - 0: one request to transfer one burst 1: one request to transfer all the data defined in ch_tts"]
            pub type HANDSHAKEOPT_R = crate::BitReader;
            #[doc = "Field `HANDSHAKEOPT` writer - 0: one request to transfer one burst 1: one request to transfer all the data defined in ch_tts"]
            pub type HANDSHAKEOPT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INFINITELOOP` reader - set to loop current config infinitely"]
            pub type INFINITELOOP_R = crate::BitReader;
            #[doc = "Field `INFINITELOOP` writer - set to loop current config infinitely"]
            pub type INFINITELOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Channel enable bit 0x0: Disable 0x1: Enable"]
                #[inline(always)]
                pub fn enable(&self) -> ENABLE_R {
                    ENABLE_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - Channel terminal count interrupt mask 0x0: Allow the terminal count interrupt to be triggered 0x1: Disable the terminal count interrupt"]
                #[inline(always)]
                pub fn inttcmask(&self) -> INTTCMASK_R {
                    INTTCMASK_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 2 - Channel error interrupt mask 0x0: Allow the error interrupt to be triggered 0x1: Disable the error interrupt"]
                #[inline(always)]
                pub fn interrmask(&self) -> INTERRMASK_R {
                    INTERRMASK_R::new(((self.bits >> 2) & 1) != 0)
                }
                #[doc = "Bit 3 - Channel abort interrupt mask 0x0: Allow the abort interrupt to be triggered 0x1: Disable the abort interrupt"]
                #[inline(always)]
                pub fn intabtmask(&self) -> INTABTMASK_R {
                    INTABTMASK_R::new(((self.bits >> 3) & 1) != 0)
                }
                #[doc = "Bit 4 - Channel half interrupt mask 0x0: Allow the half interrupt to be triggered 0x1: Disable the half interrupt"]
                #[inline(always)]
                pub fn inthalfcntmask(&self) -> INTHALFCNTMASK_R {
                    INTHALFCNTMASK_R::new(((self.bits >> 4) & 1) != 0)
                }
                #[doc = "Bits 12:13 - Destination address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
                #[inline(always)]
                pub fn dstaddrctrl(&self) -> DSTADDRCTRL_R {
                    DSTADDRCTRL_R::new(((self.bits >> 12) & 3) as u8)
                }
                #[doc = "Bits 14:15 - Source address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
                #[inline(always)]
                pub fn srcaddrctrl(&self) -> SRCADDRCTRL_R {
                    SRCADDRCTRL_R::new(((self.bits >> 14) & 3) as u8)
                }
                #[doc = "Bit 16 - Destination DMA handshake mode 0x0: Normal mode 0x1: Handshake mode the difference bewteen Source/Destination handshake mode is: the dma block will response hardware request after read in Source handshake mode; the dma block will response hardware request after write in Destination handshake mode; NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown."]
                #[inline(always)]
                pub fn dstmode(&self) -> DSTMODE_R {
                    DSTMODE_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 17 - Source DMA handshake mode 0x0: Normal mode 0x1: Handshake mode Normal mode is enabled and started by software set Enable bit; Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block"]
                #[inline(always)]
                pub fn srcmode(&self) -> SRCMODE_R {
                    SRCMODE_R::new(((self.bits >> 17) & 1) != 0)
                }
                #[doc = "Bits 18:20 - Destination transfer width. Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
                #[inline(always)]
                pub fn dstwidth(&self) -> DSTWIDTH_R {
                    DSTWIDTH_R::new(((self.bits >> 18) & 7) as u8)
                }
                #[doc = "Bits 21:23 - Source transfer width 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
                #[inline(always)]
                pub fn srcwidth(&self) -> SRCWIDTH_R {
                    SRCWIDTH_R::new(((self.bits >> 21) & 7) as u8)
                }
                #[doc = "Bits 24:27 - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x0: 1 transfer 0x1: 2 transfers 0x2: 4 transfers 0x3: 8 transfers 0x4: 16 transfers 0x5: 32 transfers 0x6: 64 transfers 0x7: 128 transfers 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception"]
                #[inline(always)]
                pub fn srcburstsize(&self) -> SRCBURSTSIZE_R {
                    SRCBURSTSIZE_R::new(((self.bits >> 24) & 0x0f) as u8)
                }
                #[doc = "Bit 28 - set to change burst_size definition"]
                #[inline(always)]
                pub fn burstopt(&self) -> BURSTOPT_R {
                    BURSTOPT_R::new(((self.bits >> 28) & 1) != 0)
                }
                #[doc = "Bit 29 - Channel priority level 0x0: Lower priority 0x1: Higher priority"]
                #[inline(always)]
                pub fn priority(&self) -> PRIORITY_R {
                    PRIORITY_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 30 - 0: one request to transfer one burst 1: one request to transfer all the data defined in ch_tts"]
                #[inline(always)]
                pub fn handshakeopt(&self) -> HANDSHAKEOPT_R {
                    HANDSHAKEOPT_R::new(((self.bits >> 30) & 1) != 0)
                }
                #[doc = "Bit 31 - set to loop current config infinitely"]
                #[inline(always)]
                pub fn infiniteloop(&self) -> INFINITELOOP_R {
                    INFINITELOOP_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Channel enable bit 0x0: Disable 0x1: Enable"]
                #[inline(always)]
                #[must_use]
                pub fn enable(&mut self) -> ENABLE_W<CTRL_SPEC> {
                    ENABLE_W::new(self, 0)
                }
                #[doc = "Bit 1 - Channel terminal count interrupt mask 0x0: Allow the terminal count interrupt to be triggered 0x1: Disable the terminal count interrupt"]
                #[inline(always)]
                #[must_use]
                pub fn inttcmask(&mut self) -> INTTCMASK_W<CTRL_SPEC> {
                    INTTCMASK_W::new(self, 1)
                }
                #[doc = "Bit 2 - Channel error interrupt mask 0x0: Allow the error interrupt to be triggered 0x1: Disable the error interrupt"]
                #[inline(always)]
                #[must_use]
                pub fn interrmask(&mut self) -> INTERRMASK_W<CTRL_SPEC> {
                    INTERRMASK_W::new(self, 2)
                }
                #[doc = "Bit 3 - Channel abort interrupt mask 0x0: Allow the abort interrupt to be triggered 0x1: Disable the abort interrupt"]
                #[inline(always)]
                #[must_use]
                pub fn intabtmask(&mut self) -> INTABTMASK_W<CTRL_SPEC> {
                    INTABTMASK_W::new(self, 3)
                }
                #[doc = "Bit 4 - Channel half interrupt mask 0x0: Allow the half interrupt to be triggered 0x1: Disable the half interrupt"]
                #[inline(always)]
                #[must_use]
                pub fn inthalfcntmask(&mut self) -> INTHALFCNTMASK_W<CTRL_SPEC> {
                    INTHALFCNTMASK_W::new(self, 4)
                }
                #[doc = "Bits 12:13 - Destination address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
                #[inline(always)]
                #[must_use]
                pub fn dstaddrctrl(&mut self) -> DSTADDRCTRL_W<CTRL_SPEC> {
                    DSTADDRCTRL_W::new(self, 12)
                }
                #[doc = "Bits 14:15 - Source address control 0x0: Increment address 0x1: Decrement address 0x2: Fixed address 0x3: Reserved, setting the field with this value triggers the error exception"]
                #[inline(always)]
                #[must_use]
                pub fn srcaddrctrl(&mut self) -> SRCADDRCTRL_W<CTRL_SPEC> {
                    SRCADDRCTRL_W::new(self, 14)
                }
                #[doc = "Bit 16 - Destination DMA handshake mode 0x0: Normal mode 0x1: Handshake mode the difference bewteen Source/Destination handshake mode is: the dma block will response hardware request after read in Source handshake mode; the dma block will response hardware request after write in Destination handshake mode; NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown."]
                #[inline(always)]
                #[must_use]
                pub fn dstmode(&mut self) -> DSTMODE_W<CTRL_SPEC> {
                    DSTMODE_W::new(self, 16)
                }
                #[doc = "Bit 17 - Source DMA handshake mode 0x0: Normal mode 0x1: Handshake mode Normal mode is enabled and started by software set Enable bit; Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block"]
                #[inline(always)]
                #[must_use]
                pub fn srcmode(&mut self) -> SRCMODE_W<CTRL_SPEC> {
                    SRCMODE_W::new(self, 17)
                }
                #[doc = "Bits 18:20 - Destination transfer width. Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
                #[inline(always)]
                #[must_use]
                pub fn dstwidth(&mut self) -> DSTWIDTH_W<CTRL_SPEC> {
                    DSTWIDTH_W::new(self, 18)
                }
                #[doc = "Bits 21:23 - Source transfer width 0x0: Byte transfer 0x1: Half-word transfer 0x2: Word transfer 0x3: Double word transfer 0x4: Quad word transfer 0x5: Eight word transfer 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception"]
                #[inline(always)]
                #[must_use]
                pub fn srcwidth(&mut self) -> SRCWIDTH_W<CTRL_SPEC> {
                    SRCWIDTH_W::new(self, 21)
                }
                #[doc = "Bits 24:27 - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. The burst transfer byte number is (SrcBurstSize * SrcWidth). 0x0: 1 transfer 0x1: 2 transfers 0x2: 4 transfers 0x3: 8 transfers 0x4: 16 transfers 0x5: 32 transfers 0x6: 64 transfers 0x7: 128 transfers 0x8: 256 transfers 0x9:512 transfers 0xa: 1024 transfers 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception"]
                #[inline(always)]
                #[must_use]
                pub fn srcburstsize(&mut self) -> SRCBURSTSIZE_W<CTRL_SPEC> {
                    SRCBURSTSIZE_W::new(self, 24)
                }
                #[doc = "Bit 28 - set to change burst_size definition"]
                #[inline(always)]
                #[must_use]
                pub fn burstopt(&mut self) -> BURSTOPT_W<CTRL_SPEC> {
                    BURSTOPT_W::new(self, 28)
                }
                #[doc = "Bit 29 - Channel priority level 0x0: Lower priority 0x1: Higher priority"]
                #[inline(always)]
                #[must_use]
                pub fn priority(&mut self) -> PRIORITY_W<CTRL_SPEC> {
                    PRIORITY_W::new(self, 29)
                }
                #[doc = "Bit 30 - 0: one request to transfer one burst 1: one request to transfer all the data defined in ch_tts"]
                #[inline(always)]
                #[must_use]
                pub fn handshakeopt(&mut self) -> HANDSHAKEOPT_W<CTRL_SPEC> {
                    HANDSHAKEOPT_W::new(self, 30)
                }
                #[doc = "Bit 31 - set to loop current config infinitely"]
                #[inline(always)]
                #[must_use]
                pub fn infiniteloop(&mut self) -> INFINITELOOP_W<CTRL_SPEC> {
                    INFINITELOOP_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Channel &amp;index0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CTRL_SPEC;
            impl crate::RegisterSpec for CTRL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
            impl crate::Readable for CTRL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
            impl crate::Writable for CTRL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets Ctrl to value 0"]
            impl crate::Resettable for CTRL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TranSize (rw) register accessor: Channel &amp;index0Transfer Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tran_size::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tran_size::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tran_size`]
module"]
        pub type TRAN_SIZE = crate::Reg<tran_size::TRAN_SIZE_SPEC>;
        #[doc = "Channel &amp;index0Transfer Size Register"]
        pub mod tran_size {
            #[doc = "Register `TranSize` reader"]
            pub type R = crate::R<TRAN_SIZE_SPEC>;
            #[doc = "Register `TranSize` writer"]
            pub type W = crate::W<TRAN_SIZE_SPEC>;
            #[doc = "Field `TRANSIZE` reader - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated."]
            pub type TRANSIZE_R = crate::FieldReader<u32>;
            #[doc = "Field `TRANSIZE` writer - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated."]
            pub type TRANSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
            impl R {
                #[doc = "Bits 0:27 - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated."]
                #[inline(always)]
                pub fn transize(&self) -> TRANSIZE_R {
                    TRANSIZE_R::new(self.bits & 0x0fff_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:27 - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated."]
                #[inline(always)]
                #[must_use]
                pub fn transize(&mut self) -> TRANSIZE_W<TRAN_SIZE_SPEC> {
                    TRANSIZE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Channel &amp;index0Transfer Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tran_size::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tran_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TRAN_SIZE_SPEC;
            impl crate::RegisterSpec for TRAN_SIZE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`tran_size::R`](R) reader structure"]
            impl crate::Readable for TRAN_SIZE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`tran_size::W`](W) writer structure"]
            impl crate::Writable for TRAN_SIZE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TranSize to value 0"]
            impl crate::Resettable for TRAN_SIZE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SrcAddr (rw) register accessor: Channel &amp;index0 Source Address Low Part Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`src_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`src_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@src_addr`]
module"]
        pub type SRC_ADDR = crate::Reg<src_addr::SRC_ADDR_SPEC>;
        #[doc = "Channel &amp;index0 Source Address Low Part Register"]
        pub mod src_addr {
            #[doc = "Register `SrcAddr` reader"]
            pub type R = crate::R<SRC_ADDR_SPEC>;
            #[doc = "Register `SrcAddr` writer"]
            pub type W = crate::W<SRC_ADDR_SPEC>;
            #[doc = "Field `SRCADDRL` reader - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. This address must be aligned to the source transfer size; otherwise, an error event will be triggered."]
            pub type SRCADDRL_R = crate::FieldReader<u32>;
            #[doc = "Field `SRCADDRL` writer - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. This address must be aligned to the source transfer size; otherwise, an error event will be triggered."]
            pub type SRCADDRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. This address must be aligned to the source transfer size; otherwise, an error event will be triggered."]
                #[inline(always)]
                pub fn srcaddrl(&self) -> SRCADDRL_R {
                    SRCADDRL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. This address must be aligned to the source transfer size; otherwise, an error event will be triggered."]
                #[inline(always)]
                #[must_use]
                pub fn srcaddrl(&mut self) -> SRCADDRL_W<SRC_ADDR_SPEC> {
                    SRCADDRL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Channel &amp;index0 Source Address Low Part Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`src_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`src_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SRC_ADDR_SPEC;
            impl crate::RegisterSpec for SRC_ADDR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`src_addr::R`](R) reader structure"]
            impl crate::Readable for SRC_ADDR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`src_addr::W`](W) writer structure"]
            impl crate::Writable for SRC_ADDR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SrcAddr to value 0"]
            impl crate::Resettable for SRC_ADDR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "ChanReqCtrl (rw) register accessor: Channel &amp;index0 DMA Request Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chan_req_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chan_req_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chan_req_ctrl`]
module"]
        pub type CHAN_REQ_CTRL = crate::Reg<chan_req_ctrl::CHAN_REQ_CTRL_SPEC>;
        #[doc = "Channel &amp;index0 DMA Request Control Register"]
        pub mod chan_req_ctrl {
            #[doc = "Register `ChanReqCtrl` reader"]
            pub type R = crate::R<CHAN_REQ_CTRL_SPEC>;
            #[doc = "Register `ChanReqCtrl` writer"]
            pub type W = crate::W<CHAN_REQ_CTRL_SPEC>;
            #[doc = "Field `DSTREQSEL` reader - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to."]
            pub type DSTREQSEL_R = crate::FieldReader;
            #[doc = "Field `DSTREQSEL` writer - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to."]
            pub type DSTREQSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `SRCREQSEL` reader - Source DMA request select. Select the request/ack handshake pair that the source device is connected to."]
            pub type SRCREQSEL_R = crate::FieldReader;
            #[doc = "Field `SRCREQSEL` writer - Source DMA request select. Select the request/ack handshake pair that the source device is connected to."]
            pub type SRCREQSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            impl R {
                #[doc = "Bits 16:20 - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to."]
                #[inline(always)]
                pub fn dstreqsel(&self) -> DSTREQSEL_R {
                    DSTREQSEL_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - Source DMA request select. Select the request/ack handshake pair that the source device is connected to."]
                #[inline(always)]
                pub fn srcreqsel(&self) -> SRCREQSEL_R {
                    SRCREQSEL_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 16:20 - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to."]
                #[inline(always)]
                #[must_use]
                pub fn dstreqsel(&mut self) -> DSTREQSEL_W<CHAN_REQ_CTRL_SPEC> {
                    DSTREQSEL_W::new(self, 16)
                }
                #[doc = "Bits 24:28 - Source DMA request select. Select the request/ack handshake pair that the source device is connected to."]
                #[inline(always)]
                #[must_use]
                pub fn srcreqsel(&mut self) -> SRCREQSEL_W<CHAN_REQ_CTRL_SPEC> {
                    SRCREQSEL_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Channel &amp;index0 DMA Request Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chan_req_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chan_req_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CHAN_REQ_CTRL_SPEC;
            impl crate::RegisterSpec for CHAN_REQ_CTRL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`chan_req_ctrl::R`](R) reader structure"]
            impl crate::Readable for CHAN_REQ_CTRL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`chan_req_ctrl::W`](W) writer structure"]
            impl crate::Writable for CHAN_REQ_CTRL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ChanReqCtrl to value 0"]
            impl crate::Resettable for CHAN_REQ_CTRL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "DstAddr (rw) register accessor: Channel &amp;index0 Destination Address Low Part Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dst_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dst_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dst_addr`]
module"]
        pub type DST_ADDR = crate::Reg<dst_addr::DST_ADDR_SPEC>;
        #[doc = "Channel &amp;index0 Destination Address Low Part Register"]
        pub mod dst_addr {
            #[doc = "Register `DstAddr` reader"]
            pub type R = crate::R<DST_ADDR_SPEC>;
            #[doc = "Register `DstAddr` writer"]
            pub type W = crate::W<DST_ADDR_SPEC>;
            #[doc = "Field `DSTADDRL` reader - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. This address must be aligned to the destination transfer size; otherwise the error event will be triggered."]
            pub type DSTADDRL_R = crate::FieldReader<u32>;
            #[doc = "Field `DSTADDRL` writer - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. This address must be aligned to the destination transfer size; otherwise the error event will be triggered."]
            pub type DSTADDRL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. This address must be aligned to the destination transfer size; otherwise the error event will be triggered."]
                #[inline(always)]
                pub fn dstaddrl(&self) -> DSTADDRL_R {
                    DSTADDRL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. This address must be aligned to the destination transfer size; otherwise the error event will be triggered."]
                #[inline(always)]
                #[must_use]
                pub fn dstaddrl(&mut self) -> DSTADDRL_W<DST_ADDR_SPEC> {
                    DSTADDRL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Channel &amp;index0 Destination Address Low Part Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dst_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dst_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct DST_ADDR_SPEC;
            impl crate::RegisterSpec for DST_ADDR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`dst_addr::R`](R) reader structure"]
            impl crate::Readable for DST_ADDR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`dst_addr::W`](W) writer structure"]
            impl crate::Writable for DST_ADDR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets DstAddr to value 0"]
            impl crate::Resettable for DST_ADDR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "LLPointer (rw) register accessor: Channel &amp;index0 Linked List Pointer Low Part Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`llpointer::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`llpointer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@llpointer`]
module"]
        pub type LLPOINTER = crate::Reg<llpointer::LLPOINTER_SPEC>;
        #[doc = "Channel &amp;index0 Linked List Pointer Low Part Register"]
        pub mod llpointer {
            #[doc = "Register `LLPointer` reader"]
            pub type R = crate::R<LLPOINTER_SPEC>;
            #[doc = "Register `LLPointer` writer"]
            pub type W = crate::W<LLPOINTER_SPEC>;
            #[doc = "Field `LLPOINTERL` reader - Low part of the pointer to the next descriptor. The pointer must be double word aligned."]
            pub type LLPOINTERL_R = crate::FieldReader<u32>;
            #[doc = "Field `LLPOINTERL` writer - Low part of the pointer to the next descriptor. The pointer must be double word aligned."]
            pub type LLPOINTERL_W<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
            impl R {
                #[doc = "Bits 3:31 - Low part of the pointer to the next descriptor. The pointer must be double word aligned."]
                #[inline(always)]
                pub fn llpointerl(&self) -> LLPOINTERL_R {
                    LLPOINTERL_R::new((self.bits >> 3) & 0x1fff_ffff)
                }
            }
            impl W {
                #[doc = "Bits 3:31 - Low part of the pointer to the next descriptor. The pointer must be double word aligned."]
                #[inline(always)]
                #[must_use]
                pub fn llpointerl(&mut self) -> LLPOINTERL_W<LLPOINTER_SPEC> {
                    LLPOINTERL_W::new(self, 3)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Channel &amp;index0 Linked List Pointer Low Part Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`llpointer::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`llpointer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LLPOINTER_SPEC;
            impl crate::RegisterSpec for LLPOINTER_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`llpointer::R`](R) reader structure"]
            impl crate::Readable for LLPOINTER_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`llpointer::W`](W) writer structure"]
            impl crate::Writable for LLPOINTER_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets LLPointer to value 0"]
            impl crate::Resettable for LLPOINTER_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "GPIOM"]
pub struct GPIOM {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for GPIOM {}
impl GPIOM {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const gpiom::RegisterBlock = 0xf00d_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const gpiom::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for GPIOM {
    type Target = gpiom::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for GPIOM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("GPIOM").finish()
    }
}
#[doc = "GPIOM"]
pub mod gpiom {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        assign: [ASSIGN; 15],
    }
    impl RegisterBlock {
        #[doc = "0x00..0x780 - no description available"]
        #[inline(always)]
        pub const fn assign(&self, n: usize) -> &ASSIGN {
            &self.assign[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x780 - no description available"]
        #[inline(always)]
        pub fn assign_iter(&self) -> impl Iterator<Item = &ASSIGN> {
            self.assign.iter()
        }
        #[doc = "0x00..0x80 - no description available"]
        #[inline(always)]
        pub const fn assigngpioa(&self) -> &ASSIGN {
            self.assign(0)
        }
        #[doc = "0x80..0x100 - no description available"]
        #[inline(always)]
        pub const fn assigngpiob(&self) -> &ASSIGN {
            self.assign(1)
        }
        #[doc = "0x100..0x180 - no description available"]
        #[inline(always)]
        pub const fn assignrsv3(&self) -> &ASSIGN {
            self.assign(2)
        }
        #[doc = "0x180..0x200 - no description available"]
        #[inline(always)]
        pub const fn assignrsv4(&self) -> &ASSIGN {
            self.assign(3)
        }
        #[doc = "0x200..0x280 - no description available"]
        #[inline(always)]
        pub const fn assignrsv5(&self) -> &ASSIGN {
            self.assign(4)
        }
        #[doc = "0x280..0x300 - no description available"]
        #[inline(always)]
        pub const fn assignrsv6(&self) -> &ASSIGN {
            self.assign(5)
        }
        #[doc = "0x300..0x380 - no description available"]
        #[inline(always)]
        pub const fn assignrsv7(&self) -> &ASSIGN {
            self.assign(6)
        }
        #[doc = "0x380..0x400 - no description available"]
        #[inline(always)]
        pub const fn assignrsv8(&self) -> &ASSIGN {
            self.assign(7)
        }
        #[doc = "0x400..0x480 - no description available"]
        #[inline(always)]
        pub const fn assignrsv9(&self) -> &ASSIGN {
            self.assign(8)
        }
        #[doc = "0x480..0x500 - no description available"]
        #[inline(always)]
        pub const fn assignrsv10(&self) -> &ASSIGN {
            self.assign(9)
        }
        #[doc = "0x500..0x580 - no description available"]
        #[inline(always)]
        pub const fn assignrsv11(&self) -> &ASSIGN {
            self.assign(10)
        }
        #[doc = "0x580..0x600 - no description available"]
        #[inline(always)]
        pub const fn assignrsv12(&self) -> &ASSIGN {
            self.assign(11)
        }
        #[doc = "0x600..0x680 - no description available"]
        #[inline(always)]
        pub const fn assignrsv13(&self) -> &ASSIGN {
            self.assign(12)
        }
        #[doc = "0x680..0x700 - no description available"]
        #[inline(always)]
        pub const fn assigngpiox(&self) -> &ASSIGN {
            self.assign(13)
        }
        #[doc = "0x700..0x780 - no description available"]
        #[inline(always)]
        pub const fn assigngpioy(&self) -> &ASSIGN {
            self.assign(14)
        }
    }
    #[doc = "no description available"]
    pub use self::assign::ASSIGN;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod assign {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct ASSIGN {
            pin: [PIN; 32],
        }
        impl ASSIGN {
            #[doc = "0x00..0x80 - no description available"]
            #[inline(always)]
            pub const fn pin(&self, n: usize) -> &PIN {
                &self.pin[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x00..0x80 - no description available"]
            #[inline(always)]
            pub fn pin_iter(&self) -> impl Iterator<Item = &PIN> {
                self.pin.iter()
            }
            #[doc = "0x00 - no description available"]
            #[inline(always)]
            pub const fn pinpin00(&self) -> &PIN {
                self.pin(0)
            }
            #[doc = "0x04 - no description available"]
            #[inline(always)]
            pub const fn pinpin01(&self) -> &PIN {
                self.pin(1)
            }
            #[doc = "0x08 - no description available"]
            #[inline(always)]
            pub const fn pinpin02(&self) -> &PIN {
                self.pin(2)
            }
            #[doc = "0x0c - no description available"]
            #[inline(always)]
            pub const fn pinpin03(&self) -> &PIN {
                self.pin(3)
            }
            #[doc = "0x10 - no description available"]
            #[inline(always)]
            pub const fn pinpin04(&self) -> &PIN {
                self.pin(4)
            }
            #[doc = "0x14 - no description available"]
            #[inline(always)]
            pub const fn pinpin05(&self) -> &PIN {
                self.pin(5)
            }
            #[doc = "0x18 - no description available"]
            #[inline(always)]
            pub const fn pinpin06(&self) -> &PIN {
                self.pin(6)
            }
            #[doc = "0x1c - no description available"]
            #[inline(always)]
            pub const fn pinpin07(&self) -> &PIN {
                self.pin(7)
            }
            #[doc = "0x20 - no description available"]
            #[inline(always)]
            pub const fn pinpin08(&self) -> &PIN {
                self.pin(8)
            }
            #[doc = "0x24 - no description available"]
            #[inline(always)]
            pub const fn pinpin09(&self) -> &PIN {
                self.pin(9)
            }
            #[doc = "0x28 - no description available"]
            #[inline(always)]
            pub const fn pinpin10(&self) -> &PIN {
                self.pin(10)
            }
            #[doc = "0x2c - no description available"]
            #[inline(always)]
            pub const fn pinpin11(&self) -> &PIN {
                self.pin(11)
            }
            #[doc = "0x30 - no description available"]
            #[inline(always)]
            pub const fn pinpin12(&self) -> &PIN {
                self.pin(12)
            }
            #[doc = "0x34 - no description available"]
            #[inline(always)]
            pub const fn pinpin13(&self) -> &PIN {
                self.pin(13)
            }
            #[doc = "0x38 - no description available"]
            #[inline(always)]
            pub const fn pinpin14(&self) -> &PIN {
                self.pin(14)
            }
            #[doc = "0x3c - no description available"]
            #[inline(always)]
            pub const fn pinpin15(&self) -> &PIN {
                self.pin(15)
            }
            #[doc = "0x40 - no description available"]
            #[inline(always)]
            pub const fn pinpin16(&self) -> &PIN {
                self.pin(16)
            }
            #[doc = "0x44 - no description available"]
            #[inline(always)]
            pub const fn pinpin17(&self) -> &PIN {
                self.pin(17)
            }
            #[doc = "0x48 - no description available"]
            #[inline(always)]
            pub const fn pinpin18(&self) -> &PIN {
                self.pin(18)
            }
            #[doc = "0x4c - no description available"]
            #[inline(always)]
            pub const fn pinpin19(&self) -> &PIN {
                self.pin(19)
            }
            #[doc = "0x50 - no description available"]
            #[inline(always)]
            pub const fn pinpin20(&self) -> &PIN {
                self.pin(20)
            }
            #[doc = "0x54 - no description available"]
            #[inline(always)]
            pub const fn pinpin21(&self) -> &PIN {
                self.pin(21)
            }
            #[doc = "0x58 - no description available"]
            #[inline(always)]
            pub const fn pinpin22(&self) -> &PIN {
                self.pin(22)
            }
            #[doc = "0x5c - no description available"]
            #[inline(always)]
            pub const fn pinpin23(&self) -> &PIN {
                self.pin(23)
            }
            #[doc = "0x60 - no description available"]
            #[inline(always)]
            pub const fn pinpin24(&self) -> &PIN {
                self.pin(24)
            }
            #[doc = "0x64 - no description available"]
            #[inline(always)]
            pub const fn pinpin25(&self) -> &PIN {
                self.pin(25)
            }
            #[doc = "0x68 - no description available"]
            #[inline(always)]
            pub const fn pinpin26(&self) -> &PIN {
                self.pin(26)
            }
            #[doc = "0x6c - no description available"]
            #[inline(always)]
            pub const fn pinpin27(&self) -> &PIN {
                self.pin(27)
            }
            #[doc = "0x70 - no description available"]
            #[inline(always)]
            pub const fn pinpin28(&self) -> &PIN {
                self.pin(28)
            }
            #[doc = "0x74 - no description available"]
            #[inline(always)]
            pub const fn pinpin29(&self) -> &PIN {
                self.pin(29)
            }
            #[doc = "0x78 - no description available"]
            #[inline(always)]
            pub const fn pinpin30(&self) -> &PIN {
                self.pin(30)
            }
            #[doc = "0x7c - no description available"]
            #[inline(always)]
            pub const fn pinpin31(&self) -> &PIN {
                self.pin(31)
            }
        }
        #[doc = "PIN (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin`]
module"]
        pub type PIN = crate::Reg<pin::PIN_SPEC>;
        #[doc = "no description available"]
        pub mod pin {
            #[doc = "Register `PIN[%s]` reader"]
            pub type R = crate::R<PIN_SPEC>;
            #[doc = "Register `PIN[%s]` writer"]
            pub type W = crate::W<PIN_SPEC>;
            #[doc = "Field `SELECT` reader - select which gpio controls chip pin, 0: soc gpio0; 2: cpu0 fastgpio"]
            pub type SELECT_R = crate::FieldReader;
            #[doc = "Field `SELECT` writer - select which gpio controls chip pin, 0: soc gpio0; 2: cpu0 fastgpio"]
            pub type SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `HIDE` reader - pin value visibility to gpios, bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio"]
            pub type HIDE_R = crate::FieldReader;
            #[doc = "Field `HIDE` writer - pin value visibility to gpios, bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio"]
            pub type HIDE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `LOCK` reader - lock fields in this register, lock can only be cleared by soc reset 0: fields can be changed 1: fields locked to current value, not changeable"]
            pub type LOCK_R = crate::BitReader;
            #[doc = "Field `LOCK` writer - lock fields in this register, lock can only be cleared by soc reset 0: fields can be changed 1: fields locked to current value, not changeable"]
            pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:1 - select which gpio controls chip pin, 0: soc gpio0; 2: cpu0 fastgpio"]
                #[inline(always)]
                pub fn select(&self) -> SELECT_R {
                    SELECT_R::new((self.bits & 3) as u8)
                }
                #[doc = "Bits 8:11 - pin value visibility to gpios, bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio"]
                #[inline(always)]
                pub fn hide(&self) -> HIDE_R {
                    HIDE_R::new(((self.bits >> 8) & 0x0f) as u8)
                }
                #[doc = "Bit 31 - lock fields in this register, lock can only be cleared by soc reset 0: fields can be changed 1: fields locked to current value, not changeable"]
                #[inline(always)]
                pub fn lock(&self) -> LOCK_R {
                    LOCK_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:1 - select which gpio controls chip pin, 0: soc gpio0; 2: cpu0 fastgpio"]
                #[inline(always)]
                #[must_use]
                pub fn select(&mut self) -> SELECT_W<PIN_SPEC> {
                    SELECT_W::new(self, 0)
                }
                #[doc = "Bits 8:11 - pin value visibility to gpios, bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio"]
                #[inline(always)]
                #[must_use]
                pub fn hide(&mut self) -> HIDE_W<PIN_SPEC> {
                    HIDE_W::new(self, 8)
                }
                #[doc = "Bit 31 - lock fields in this register, lock can only be cleared by soc reset 0: fields can be changed 1: fields locked to current value, not changeable"]
                #[inline(always)]
                #[must_use]
                pub fn lock(&mut self) -> LOCK_W<PIN_SPEC> {
                    LOCK_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PIN_SPEC;
            impl crate::RegisterSpec for PIN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pin::R`](R) reader structure"]
            impl crate::Readable for PIN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"]
            impl crate::Writable for PIN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PIN[%s]
to value 0"]
            impl crate::Resettable for PIN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "MCAN0"]
pub struct MCAN0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MCAN0 {}
impl MCAN0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mcan0::RegisterBlock = 0xf028_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mcan0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MCAN0 {
    type Target = mcan0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MCAN0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MCAN0").finish()
    }
}
#[doc = "MCAN0"]
pub mod mcan0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x04],
        endn: ENDN,
        _reserved1: [u8; 0x04],
        dbtp: DBTP,
        test: TEST,
        rwd: RWD,
        cccr: CCCR,
        nbtp: NBTP,
        tscc: TSCC,
        tscv: TSCV,
        tocc: TOCC,
        tocv: TOCV,
        _reserved10: [u8; 0x10],
        ecr: ECR,
        psr: PSR,
        tdcr: TDCR,
        _reserved13: [u8; 0x04],
        ir: IR,
        ie: IE,
        ils: ILS,
        ile: ILE,
        _reserved17: [u8; 0x20],
        gfc: GFC,
        sidfc: SIDFC,
        xidfc: XIDFC,
        _reserved20: [u8; 0x04],
        xidam: XIDAM,
        hpms: HPMS,
        ndat1: NDAT1,
        ndat2: NDAT2,
        rxf0c: RXF0C,
        rxf0s: RXF0S,
        rxf0a: RXF0A,
        rxbc: RXBC,
        rxf1c: RXF1C,
        rxf1s: RXF1S,
        rxf1a: RXF1A,
        rxesc: RXESC,
        txbc: TXBC,
        txfqs: TXFQS,
        txesc: TXESC,
        txbrp: TXBRP,
        txbar: TXBAR,
        txbcr: TXBCR,
        txbto: TXBTO,
        txbcf: TXBCF,
        txbtie: TXBTIE,
        txbcie: TXBCIE,
        _reserved42: [u8; 0x08],
        txefc: TXEFC,
        txefs: TXEFS,
        txefa: TXEFA,
        _reserved45: [u8; 0x0104],
        ts_sel: [TS_SEL; 16],
        crel: CREL,
        tscfg: TSCFG,
        tss1: TSS1,
        tss2: TSS2,
        atb: ATB,
        atbh: ATBH,
        _reserved52: [u8; 0x01a8],
        glb_ctl: GLB_CTL,
        glb_status: GLB_STATUS,
    }
    impl RegisterBlock {
        #[doc = "0x04 - endian register"]
        #[inline(always)]
        pub const fn endn(&self) -> &ENDN {
            &self.endn
        }
        #[doc = "0x0c - data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set"]
        #[inline(always)]
        pub const fn dbtp(&self) -> &DBTP {
            &self.dbtp
        }
        #[doc = "0x10 - test register"]
        #[inline(always)]
        pub const fn test(&self) -> &TEST {
            &self.test
        }
        #[doc = "0x14 - ram watchdog"]
        #[inline(always)]
        pub const fn rwd(&self) -> &RWD {
            &self.rwd
        }
        #[doc = "0x18 - CC control register"]
        #[inline(always)]
        pub const fn cccr(&self) -> &CCCR {
            &self.cccr
        }
        #[doc = "0x1c - nominal bit timing and prescaler register"]
        #[inline(always)]
        pub const fn nbtp(&self) -> &NBTP {
            &self.nbtp
        }
        #[doc = "0x20 - timestamp counter configuration"]
        #[inline(always)]
        pub const fn tscc(&self) -> &TSCC {
            &self.tscc
        }
        #[doc = "0x24 - timestamp counter value"]
        #[inline(always)]
        pub const fn tscv(&self) -> &TSCV {
            &self.tscv
        }
        #[doc = "0x28 - timeout counter configuration"]
        #[inline(always)]
        pub const fn tocc(&self) -> &TOCC {
            &self.tocc
        }
        #[doc = "0x2c - timeout counter value"]
        #[inline(always)]
        pub const fn tocv(&self) -> &TOCV {
            &self.tocv
        }
        #[doc = "0x40 - error counter register"]
        #[inline(always)]
        pub const fn ecr(&self) -> &ECR {
            &self.ecr
        }
        #[doc = "0x44 - protocol status register"]
        #[inline(always)]
        pub const fn psr(&self) -> &PSR {
            &self.psr
        }
        #[doc = "0x48 - transmitter delay compensation"]
        #[inline(always)]
        pub const fn tdcr(&self) -> &TDCR {
            &self.tdcr
        }
        #[doc = "0x50 - interrupt register"]
        #[inline(always)]
        pub const fn ir(&self) -> &IR {
            &self.ir
        }
        #[doc = "0x54 - interrupt enable"]
        #[inline(always)]
        pub const fn ie(&self) -> &IE {
            &self.ie
        }
        #[doc = "0x58 - interrupt line select"]
        #[inline(always)]
        pub const fn ils(&self) -> &ILS {
            &self.ils
        }
        #[doc = "0x5c - interrupt line enable"]
        #[inline(always)]
        pub const fn ile(&self) -> &ILE {
            &self.ile
        }
        #[doc = "0x80 - global filter configuration"]
        #[inline(always)]
        pub const fn gfc(&self) -> &GFC {
            &self.gfc
        }
        #[doc = "0x84 - standard ID filter configuration"]
        #[inline(always)]
        pub const fn sidfc(&self) -> &SIDFC {
            &self.sidfc
        }
        #[doc = "0x88 - extended ID filter configuration"]
        #[inline(always)]
        pub const fn xidfc(&self) -> &XIDFC {
            &self.xidfc
        }
        #[doc = "0x90 - extended id and mask"]
        #[inline(always)]
        pub const fn xidam(&self) -> &XIDAM {
            &self.xidam
        }
        #[doc = "0x94 - high priority message status"]
        #[inline(always)]
        pub const fn hpms(&self) -> &HPMS {
            &self.hpms
        }
        #[doc = "0x98 - new data1"]
        #[inline(always)]
        pub const fn ndat1(&self) -> &NDAT1 {
            &self.ndat1
        }
        #[doc = "0x9c - new data2"]
        #[inline(always)]
        pub const fn ndat2(&self) -> &NDAT2 {
            &self.ndat2
        }
        #[doc = "0xa0 - rx fifo 0 configuration"]
        #[inline(always)]
        pub const fn rxf0c(&self) -> &RXF0C {
            &self.rxf0c
        }
        #[doc = "0xa4 - rx fifo 0 status"]
        #[inline(always)]
        pub const fn rxf0s(&self) -> &RXF0S {
            &self.rxf0s
        }
        #[doc = "0xa8 - rx fifo0 acknowledge"]
        #[inline(always)]
        pub const fn rxf0a(&self) -> &RXF0A {
            &self.rxf0a
        }
        #[doc = "0xac - rx buffer configuration"]
        #[inline(always)]
        pub const fn rxbc(&self) -> &RXBC {
            &self.rxbc
        }
        #[doc = "0xb0 - rx fifo1 configuration"]
        #[inline(always)]
        pub const fn rxf1c(&self) -> &RXF1C {
            &self.rxf1c
        }
        #[doc = "0xb4 - rx fifo1 status"]
        #[inline(always)]
        pub const fn rxf1s(&self) -> &RXF1S {
            &self.rxf1s
        }
        #[doc = "0xb8 - rx fifo 1 acknowledge"]
        #[inline(always)]
        pub const fn rxf1a(&self) -> &RXF1A {
            &self.rxf1a
        }
        #[doc = "0xbc - rx buffer/fifo element size configuration"]
        #[inline(always)]
        pub const fn rxesc(&self) -> &RXESC {
            &self.rxesc
        }
        #[doc = "0xc0 - tx buffer configuration"]
        #[inline(always)]
        pub const fn txbc(&self) -> &TXBC {
            &self.txbc
        }
        #[doc = "0xc4 - tx fifo/queue status"]
        #[inline(always)]
        pub const fn txfqs(&self) -> &TXFQS {
            &self.txfqs
        }
        #[doc = "0xc8 - tx buffer element size configuration"]
        #[inline(always)]
        pub const fn txesc(&self) -> &TXESC {
            &self.txesc
        }
        #[doc = "0xcc - tx buffer request pending"]
        #[inline(always)]
        pub const fn txbrp(&self) -> &TXBRP {
            &self.txbrp
        }
        #[doc = "0xd0 - tx buffer add request"]
        #[inline(always)]
        pub const fn txbar(&self) -> &TXBAR {
            &self.txbar
        }
        #[doc = "0xd4 - tx buffer cancellation request"]
        #[inline(always)]
        pub const fn txbcr(&self) -> &TXBCR {
            &self.txbcr
        }
        #[doc = "0xd8 - tx buffer transmission occurred"]
        #[inline(always)]
        pub const fn txbto(&self) -> &TXBTO {
            &self.txbto
        }
        #[doc = "0xdc - tx buffer cancellation finished"]
        #[inline(always)]
        pub const fn txbcf(&self) -> &TXBCF {
            &self.txbcf
        }
        #[doc = "0xe0 - tx buffer transmission interrupt enable"]
        #[inline(always)]
        pub const fn txbtie(&self) -> &TXBTIE {
            &self.txbtie
        }
        #[doc = "0xe4 - tx buffer cancellation finished interrupt enable"]
        #[inline(always)]
        pub const fn txbcie(&self) -> &TXBCIE {
            &self.txbcie
        }
        #[doc = "0xf0 - tx event fifo configuration"]
        #[inline(always)]
        pub const fn txefc(&self) -> &TXEFC {
            &self.txefc
        }
        #[doc = "0xf4 - tx event fifo status"]
        #[inline(always)]
        pub const fn txefs(&self) -> &TXEFS {
            &self.txefs
        }
        #[doc = "0xf8 - tx event fifo acknowledge"]
        #[inline(always)]
        pub const fn txefa(&self) -> &TXEFA {
            &self.txefa
        }
        #[doc = "0x200..0x240 - no description available"]
        #[inline(always)]
        pub const fn ts_sel(&self, n: usize) -> &TS_SEL {
            &self.ts_sel[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x200..0x240 - no description available"]
        #[inline(always)]
        pub fn ts_sel_iter(&self) -> impl Iterator<Item = &TS_SEL> {
            self.ts_sel.iter()
        }
        #[doc = "0x200 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel0(&self) -> &TS_SEL {
            self.ts_sel(0)
        }
        #[doc = "0x204 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel1(&self) -> &TS_SEL {
            self.ts_sel(1)
        }
        #[doc = "0x208 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel2(&self) -> &TS_SEL {
            self.ts_sel(2)
        }
        #[doc = "0x20c - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel3(&self) -> &TS_SEL {
            self.ts_sel(3)
        }
        #[doc = "0x210 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel4(&self) -> &TS_SEL {
            self.ts_sel(4)
        }
        #[doc = "0x214 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel5(&self) -> &TS_SEL {
            self.ts_sel(5)
        }
        #[doc = "0x218 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel6(&self) -> &TS_SEL {
            self.ts_sel(6)
        }
        #[doc = "0x21c - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel7(&self) -> &TS_SEL {
            self.ts_sel(7)
        }
        #[doc = "0x220 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel8(&self) -> &TS_SEL {
            self.ts_sel(8)
        }
        #[doc = "0x224 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel9(&self) -> &TS_SEL {
            self.ts_sel(9)
        }
        #[doc = "0x228 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel10(&self) -> &TS_SEL {
            self.ts_sel(10)
        }
        #[doc = "0x22c - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel11(&self) -> &TS_SEL {
            self.ts_sel(11)
        }
        #[doc = "0x230 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel12(&self) -> &TS_SEL {
            self.ts_sel(12)
        }
        #[doc = "0x234 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel13(&self) -> &TS_SEL {
            self.ts_sel(13)
        }
        #[doc = "0x238 - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel14(&self) -> &TS_SEL {
            self.ts_sel(14)
        }
        #[doc = "0x23c - no description available"]
        #[inline(always)]
        pub const fn ts_selts_sel15(&self) -> &TS_SEL {
            self.ts_sel(15)
        }
        #[doc = "0x240 - core release register"]
        #[inline(always)]
        pub const fn crel(&self) -> &CREL {
            &self.crel
        }
        #[doc = "0x244 - timestamp configuration"]
        #[inline(always)]
        pub const fn tscfg(&self) -> &TSCFG {
            &self.tscfg
        }
        #[doc = "0x248 - timestamp status1"]
        #[inline(always)]
        pub const fn tss1(&self) -> &TSS1 {
            &self.tss1
        }
        #[doc = "0x24c - timestamp status2"]
        #[inline(always)]
        pub const fn tss2(&self) -> &TSS2 {
            &self.tss2
        }
        #[doc = "0x250 - actual timebase"]
        #[inline(always)]
        pub const fn atb(&self) -> &ATB {
            &self.atb
        }
        #[doc = "0x254 - actual timebase high"]
        #[inline(always)]
        pub const fn atbh(&self) -> &ATBH {
            &self.atbh
        }
        #[doc = "0x400 - global control"]
        #[inline(always)]
        pub const fn glb_ctl(&self) -> &GLB_CTL {
            &self.glb_ctl
        }
        #[doc = "0x404 - global status"]
        #[inline(always)]
        pub const fn glb_status(&self) -> &GLB_STATUS {
            &self.glb_status
        }
    }
    #[doc = "ENDN (rw) register accessor: endian register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endn::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endn`]
module"]
    pub type ENDN = crate::Reg<endn::ENDN_SPEC>;
    #[doc = "endian register"]
    pub mod endn {
        #[doc = "Register `ENDN` reader"]
        pub type R = crate::R<ENDN_SPEC>;
        #[doc = "Register `ENDN` writer"]
        pub type W = crate::W<ENDN_SPEC>;
        #[doc = "Field `EVT` reader - Endianness Test Value The endianness test value is 0x87654321."]
        pub type EVT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Endianness Test Value The endianness test value is 0x87654321."]
            #[inline(always)]
            pub fn evt(&self) -> EVT_R {
                EVT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "endian register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endn::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDN_SPEC;
        impl crate::RegisterSpec for ENDN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endn::R`](R) reader structure"]
        impl crate::Readable for ENDN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endn::W`](W) writer structure"]
        impl crate::Writable for ENDN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDN to value 0x8765_4321"]
        impl crate::Resettable for ENDN_SPEC {
            const RESET_VALUE: u32 = 0x8765_4321;
        }
    }
    #[doc = "DBTP (rw) register accessor: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbtp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbtp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbtp`]
module"]
    pub type DBTP = crate::Reg<dbtp::DBTP_SPEC>;
    #[doc = "data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set"]
    pub mod dbtp {
        #[doc = "Register `DBTP` reader"]
        pub type R = crate::R<DBTP_SPEC>;
        #[doc = "Register `DBTP` writer"]
        pub type W = crate::W<DBTP_SPEC>;
        #[doc = "Field `DSJW` reader - Data (Re)Synchronization Jump Width Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type DSJW_R = crate::FieldReader;
        #[doc = "Field `DSJW` writer - Data (Re)Synchronization Jump Width Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type DSJW_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DTSEG2` reader - Data time segment after sample point Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type DTSEG2_R = crate::FieldReader;
        #[doc = "Field `DTSEG2` writer - Data time segment after sample point Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type DTSEG2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DTSEG1` reader - Data time segment before sample point Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type DTSEG1_R = crate::FieldReader;
        #[doc = "Field `DTSEG1` writer - Data time segment before sample point Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type DTSEG1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `DBRP` reader - Data Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type DBRP_R = crate::FieldReader;
        #[doc = "Field `DBRP` writer - Data Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type DBRP_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `TDC` reader - transmitter delay compensation enable 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled"]
        pub type TDC_R = crate::BitReader;
        #[doc = "Field `TDC` writer - transmitter delay compensation enable 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled"]
        pub type TDC_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            pub fn dsjw(&self) -> DSJW_R {
                DSJW_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:7 - Data time segment after sample point Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            pub fn dtseg2(&self) -> DTSEG2_R {
                DTSEG2_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            #[doc = "Bits 8:12 - Data time segment before sample point Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            pub fn dtseg1(&self) -> DTSEG1_R {
                DTSEG1_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:20 - Data Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            pub fn dbrp(&self) -> DBRP_R {
                DBRP_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bit 23 - transmitter delay compensation enable 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled"]
            #[inline(always)]
            pub fn tdc(&self) -> TDC_R {
                TDC_R::new(((self.bits >> 23) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - Data (Re)Synchronization Jump Width Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            #[must_use]
            pub fn dsjw(&mut self) -> DSJW_W<DBTP_SPEC> {
                DSJW_W::new(self, 0)
            }
            #[doc = "Bits 4:7 - Data time segment after sample point Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            #[must_use]
            pub fn dtseg2(&mut self) -> DTSEG2_W<DBTP_SPEC> {
                DTSEG2_W::new(self, 4)
            }
            #[doc = "Bits 8:12 - Data time segment before sample point Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            #[must_use]
            pub fn dtseg1(&mut self) -> DTSEG1_W<DBTP_SPEC> {
                DTSEG1_W::new(self, 8)
            }
            #[doc = "Bits 16:20 - Data Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            #[must_use]
            pub fn dbrp(&mut self) -> DBRP_W<DBTP_SPEC> {
                DBRP_W::new(self, 16)
            }
            #[doc = "Bit 23 - transmitter delay compensation enable 0= Transmitter Delay Compensation disabled 1= Transmitter Delay Compensation enabled"]
            #[inline(always)]
            #[must_use]
            pub fn tdc(&mut self) -> TDC_W<DBTP_SPEC> {
                TDC_W::new(self, 23)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbtp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbtp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DBTP_SPEC;
        impl crate::RegisterSpec for DBTP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dbtp::R`](R) reader structure"]
        impl crate::Readable for DBTP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dbtp::W`](W) writer structure"]
        impl crate::Writable for DBTP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DBTP to value 0x0a33"]
        impl crate::Resettable for DBTP_SPEC {
            const RESET_VALUE: u32 = 0x0a33;
        }
    }
    #[doc = "TEST (rw) register accessor: test register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@test`]
module"]
    pub type TEST = crate::Reg<test::TEST_SPEC>;
    #[doc = "test register"]
    pub mod test {
        #[doc = "Register `TEST` reader"]
        pub type R = crate::R<TEST_SPEC>;
        #[doc = "Register `TEST` writer"]
        pub type W = crate::W<TEST_SPEC>;
        #[doc = "Field `LBCK` reader - Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled"]
        pub type LBCK_R = crate::BitReader;
        #[doc = "Field `LBCK` writer - Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled"]
        pub type LBCK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TX` reader - Control of Transmit Pin 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_can_tx 10 Dominant (‘0’) level at pin m_can_tx 11 Recessive (‘1’) at pin m_can_tx"]
        pub type TX_R = crate::FieldReader;
        #[doc = "Field `TX` writer - Control of Transmit Pin 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_can_tx 10 Dominant (‘0’) level at pin m_can_tx 11 Recessive (‘1’) at pin m_can_tx"]
        pub type TX_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `RX` reader - Receive Pin Monitors the actual value of pin m_can_rx 0= The CAN bus is dominant (m_can_rx = ‘0’) 1= The CAN bus is recessive (m_can_rx = ‘1’)"]
        pub type RX_R = crate::BitReader;
        #[doc = "Field `TXBNP` reader - Tx Buffer Number Prepared Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31."]
        pub type TXBNP_R = crate::FieldReader;
        #[doc = "Field `PVAL` reader - Prepared Valid 0= Value of TXBNP not valid 1= Value of TXBNP valid"]
        pub type PVAL_R = crate::BitReader;
        #[doc = "Field `TXBNS` reader - Tx Buffer Number Started Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31."]
        pub type TXBNS_R = crate::FieldReader;
        #[doc = "Field `SVAL` reader - Started Valid 0= Value of TXBNS not valid 1= Value of TXBNS valid"]
        pub type SVAL_R = crate::BitReader;
        impl R {
            #[doc = "Bit 4 - Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled"]
            #[inline(always)]
            pub fn lbck(&self) -> LBCK_R {
                LBCK_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bits 5:6 - Control of Transmit Pin 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_can_tx 10 Dominant (‘0’) level at pin m_can_tx 11 Recessive (‘1’) at pin m_can_tx"]
            #[inline(always)]
            pub fn tx(&self) -> TX_R {
                TX_R::new(((self.bits >> 5) & 3) as u8)
            }
            #[doc = "Bit 7 - Receive Pin Monitors the actual value of pin m_can_rx 0= The CAN bus is dominant (m_can_rx = ‘0’) 1= The CAN bus is recessive (m_can_rx = ‘1’)"]
            #[inline(always)]
            pub fn rx(&self) -> RX_R {
                RX_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:12 - Tx Buffer Number Prepared Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31."]
            #[inline(always)]
            pub fn txbnp(&self) -> TXBNP_R {
                TXBNP_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bit 13 - Prepared Valid 0= Value of TXBNP not valid 1= Value of TXBNP valid"]
            #[inline(always)]
            pub fn pval(&self) -> PVAL_R {
                PVAL_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bits 16:20 - Tx Buffer Number Started Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31."]
            #[inline(always)]
            pub fn txbns(&self) -> TXBNS_R {
                TXBNS_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bit 21 - Started Valid 0= Value of TXBNS not valid 1= Value of TXBNS valid"]
            #[inline(always)]
            pub fn sval(&self) -> SVAL_R {
                SVAL_R::new(((self.bits >> 21) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 4 - Loop Back Mode 0= Reset value, Loop Back Mode is disabled 1= Loop Back Mode is enabled"]
            #[inline(always)]
            #[must_use]
            pub fn lbck(&mut self) -> LBCK_W<TEST_SPEC> {
                LBCK_W::new(self, 4)
            }
            #[doc = "Bits 5:6 - Control of Transmit Pin 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_can_tx 10 Dominant (‘0’) level at pin m_can_tx 11 Recessive (‘1’) at pin m_can_tx"]
            #[inline(always)]
            #[must_use]
            pub fn tx(&mut self) -> TX_W<TEST_SPEC> {
                TX_W::new(self, 5)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "test register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`test::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`test::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TEST_SPEC;
        impl crate::RegisterSpec for TEST_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`test::R`](R) reader structure"]
        impl crate::Readable for TEST_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`test::W`](W) writer structure"]
        impl crate::Writable for TEST_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TEST to value 0"]
        impl crate::Resettable for TEST_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RWD (rw) register accessor: ram watchdog\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rwd`]
module"]
    pub type RWD = crate::Reg<rwd::RWD_SPEC>;
    #[doc = "ram watchdog"]
    pub mod rwd {
        #[doc = "Register `RWD` reader"]
        pub type R = crate::R<RWD_SPEC>;
        #[doc = "Register `RWD` writer"]
        pub type W = crate::W<RWD_SPEC>;
        #[doc = "Field `WDC` reader - Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled."]
        pub type WDC_R = crate::FieldReader;
        #[doc = "Field `WDC` writer - Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled."]
        pub type WDC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `WDV` reader - Watchdog Value Actual Message RAM Watchdog Counter Value."]
        pub type WDV_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled."]
            #[inline(always)]
            pub fn wdc(&self) -> WDC_R {
                WDC_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - Watchdog Value Actual Message RAM Watchdog Counter Value."]
            #[inline(always)]
            pub fn wdv(&self) -> WDV_R {
                WDV_R::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Watchdog Configuration Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled."]
            #[inline(always)]
            #[must_use]
            pub fn wdc(&mut self) -> WDC_W<RWD_SPEC> {
                WDC_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "ram watchdog\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rwd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rwd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RWD_SPEC;
        impl crate::RegisterSpec for RWD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rwd::R`](R) reader structure"]
        impl crate::Readable for RWD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rwd::W`](W) writer structure"]
        impl crate::Writable for RWD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RWD to value 0"]
        impl crate::Resettable for RWD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CCCR (rw) register accessor: CC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cccr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cccr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cccr`]
module"]
    pub type CCCR = crate::Reg<cccr::CCCR_SPEC>;
    #[doc = "CC control register"]
    pub mod cccr {
        #[doc = "Register `CCCR` reader"]
        pub type R = crate::R<CCCR_SPEC>;
        #[doc = "Register `CCCR` writer"]
        pub type W = crate::W<CCCR_SPEC>;
        #[doc = "Field `INIT` reader - Initialization 0= Normal Operation 1= Initialization is started"]
        pub type INIT_R = crate::BitReader;
        #[doc = "Field `INIT` writer - Initialization 0= Normal Operation 1= Initialization is started"]
        pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CCE` reader - Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’)"]
        pub type CCE_R = crate::BitReader;
        #[doc = "Field `CCE` writer - Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’)"]
        pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASM` reader - Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active"]
        pub type ASM_R = crate::BitReader;
        #[doc = "Field `ASM` writer - Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active"]
        pub type ASM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CSA` reader - Clock Stop Acknowledge 0= No clock stop acknowledged 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk"]
        pub type CSA_R = crate::BitReader;
        #[doc = "Field `CSR` reader - Clock Stop Request 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle."]
        pub type CSR_R = crate::BitReader;
        #[doc = "Field `CSR` writer - Clock Stop Request 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle."]
        pub type CSR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MON` reader - Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled"]
        pub type MON_R = crate::BitReader;
        #[doc = "Field `MON` writer - Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled"]
        pub type MON_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DAR` reader - Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled"]
        pub type DAR_R = crate::BitReader;
        #[doc = "Field `DAR` writer - Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled"]
        pub type DAR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEST` reader - Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled"]
        pub type TEST_R = crate::BitReader;
        #[doc = "Field `TEST` writer - Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled"]
        pub type TEST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FDOE` reader - FD Operation Enable 0= FD operation disabled 1= FD operation enabled"]
        pub type FDOE_R = crate::BitReader;
        #[doc = "Field `FDOE` writer - FD Operation Enable 0= FD operation disabled 1= FD operation enabled"]
        pub type FDOE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BRSE` reader - Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated."]
        pub type BRSE_R = crate::BitReader;
        #[doc = "Field `BRSE` writer - Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated."]
        pub type BRSE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UTSU` reader - Use Timestamping Unit When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. 0= Internal time stamping 1= External time stamping by TSU Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. In this case bit UTSU is fixed to zero by synthesis."]
        pub type UTSU_R = crate::BitReader;
        #[doc = "Field `UTSU` writer - Use Timestamping Unit When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. 0= Internal time stamping 1= External time stamping by TSU Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. In this case bit UTSU is fixed to zero by synthesis."]
        pub type UTSU_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WMM` reader - Wide Message Marker Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. 0= 8-bit Message Marker used 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO"]
        pub type WMM_R = crate::BitReader;
        #[doc = "Field `WMM` writer - Wide Message Marker Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. 0= 8-bit Message Marker used 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO"]
        pub type WMM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PXHD` reader - Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition."]
        pub type PXHD_R = crate::BitReader;
        #[doc = "Field `PXHD` writer - Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition."]
        pub type PXHD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EFBI` reader - Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization"]
        pub type EFBI_R = crate::BitReader;
        #[doc = "Field `EFBI` writer - Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization"]
        pub type EFBI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXP` reader - Transmit Pause If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled"]
        pub type TXP_R = crate::BitReader;
        #[doc = "Field `TXP` writer - Transmit Pause If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled"]
        pub type TXP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NISO` reader - Non ISO Operation If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015."]
        pub type NISO_R = crate::BitReader;
        #[doc = "Field `NISO` writer - Non ISO Operation If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015."]
        pub type NISO_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Initialization 0= Normal Operation 1= Initialization is started"]
            #[inline(always)]
            pub fn init(&self) -> INIT_R {
                INIT_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’)"]
            #[inline(always)]
            pub fn cce(&self) -> CCE_R {
                CCE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active"]
            #[inline(always)]
            pub fn asm(&self) -> ASM_R {
                ASM_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Clock Stop Acknowledge 0= No clock stop acknowledged 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk"]
            #[inline(always)]
            pub fn csa(&self) -> CSA_R {
                CSA_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Clock Stop Request 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle."]
            #[inline(always)]
            pub fn csr(&self) -> CSR_R {
                CSR_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled"]
            #[inline(always)]
            pub fn mon(&self) -> MON_R {
                MON_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled"]
            #[inline(always)]
            pub fn dar(&self) -> DAR_R {
                DAR_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled"]
            #[inline(always)]
            pub fn test(&self) -> TEST_R {
                TEST_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - FD Operation Enable 0= FD operation disabled 1= FD operation enabled"]
            #[inline(always)]
            pub fn fdoe(&self) -> FDOE_R {
                FDOE_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated."]
            #[inline(always)]
            pub fn brse(&self) -> BRSE_R {
                BRSE_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - Use Timestamping Unit When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. 0= Internal time stamping 1= External time stamping by TSU Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. In this case bit UTSU is fixed to zero by synthesis."]
            #[inline(always)]
            pub fn utsu(&self) -> UTSU_R {
                UTSU_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - Wide Message Marker Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. 0= 8-bit Message Marker used 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO"]
            #[inline(always)]
            pub fn wmm(&self) -> WMM_R {
                WMM_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition."]
            #[inline(always)]
            pub fn pxhd(&self) -> PXHD_R {
                PXHD_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization"]
            #[inline(always)]
            pub fn efbi(&self) -> EFBI_R {
                EFBI_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - Transmit Pause If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled"]
            #[inline(always)]
            pub fn txp(&self) -> TXP_R {
                TXP_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - Non ISO Operation If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015."]
            #[inline(always)]
            pub fn niso(&self) -> NISO_R {
                NISO_R::new(((self.bits >> 15) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Initialization 0= Normal Operation 1= Initialization is started"]
            #[inline(always)]
            #[must_use]
            pub fn init(&mut self) -> INIT_W<CCCR_SPEC> {
                INIT_W::new(self, 0)
            }
            #[doc = "Bit 1 - Configuration Change Enable 0= The CPU has no write access to the protected configuration registers 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’)"]
            #[inline(always)]
            #[must_use]
            pub fn cce(&mut self) -> CCE_W<CCCR_SPEC> {
                CCE_W::new(self, 1)
            }
            #[doc = "Bit 2 - Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. 0= Normal CAN operation 1= Restricted Operation Mode active"]
            #[inline(always)]
            #[must_use]
            pub fn asm(&mut self) -> ASM_W<CCCR_SPEC> {
                ASM_W::new(self, 2)
            }
            #[doc = "Bit 4 - Clock Stop Request 0= No clock stop is requested 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle."]
            #[inline(always)]
            #[must_use]
            pub fn csr(&mut self) -> CSR_W<CCCR_SPEC> {
                CSR_W::new(self, 4)
            }
            #[doc = "Bit 5 - Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. 0= Bus Monitoring Mode is disabled 1= Bus Monitoring Mode is enabled"]
            #[inline(always)]
            #[must_use]
            pub fn mon(&mut self) -> MON_W<CCCR_SPEC> {
                MON_W::new(self, 5)
            }
            #[doc = "Bit 6 - Disable Automatic Retransmission 0= Automatic retransmission of messages not transmitted successfully enabled 1= Automatic retransmission disabled"]
            #[inline(always)]
            #[must_use]
            pub fn dar(&mut self) -> DAR_W<CCCR_SPEC> {
                DAR_W::new(self, 6)
            }
            #[doc = "Bit 7 - Test Mode Enable 0= Normal operation, register TEST holds reset values 1= Test Mode, write access to register TEST enabled"]
            #[inline(always)]
            #[must_use]
            pub fn test(&mut self) -> TEST_W<CCCR_SPEC> {
                TEST_W::new(self, 7)
            }
            #[doc = "Bit 8 - FD Operation Enable 0= FD operation disabled 1= FD operation enabled"]
            #[inline(always)]
            #[must_use]
            pub fn fdoe(&mut self) -> FDOE_W<CCCR_SPEC> {
                FDOE_W::new(self, 8)
            }
            #[doc = "Bit 9 - Bit Rate Switch Enable 0= Bit rate switching for transmissions disabled 1= Bit rate switching for transmissions enabled Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated."]
            #[inline(always)]
            #[must_use]
            pub fn brse(&mut self) -> BRSE_W<CCCR_SPEC> {
                BRSE_W::new(self, 9)
            }
            #[doc = "Bit 10 - Use Timestamping Unit When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. 0= Internal time stamping 1= External time stamping by TSU Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. In this case bit UTSU is fixed to zero by synthesis."]
            #[inline(always)]
            #[must_use]
            pub fn utsu(&mut self) -> UTSU_W<CCCR_SPEC> {
                UTSU_W::new(self, 10)
            }
            #[doc = "Bit 11 - Wide Message Marker Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. 0= 8-bit Message Marker used 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO"]
            #[inline(always)]
            #[must_use]
            pub fn wmm(&mut self) -> WMM_W<CCCR_SPEC> {
                WMM_W::new(self, 11)
            }
            #[doc = "Bit 12 - Protocol Exception Handling Disable 0= Protocol exception handling enabled 1= Protocol exception handling disabled Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition."]
            #[inline(always)]
            #[must_use]
            pub fn pxhd(&mut self) -> PXHD_W<CCCR_SPEC> {
                PXHD_W::new(self, 12)
            }
            #[doc = "Bit 13 - Edge Filtering during Bus Integration 0= Edge filtering disabled 1= Two consecutive dominant tq required to detect an edge for hard synchronization"]
            #[inline(always)]
            #[must_use]
            pub fn efbi(&mut self) -> EFBI_W<CCCR_SPEC> {
                EFBI_W::new(self, 13)
            }
            #[doc = "Bit 14 - Transmit Pause If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5). 0= Transmit pause disabled 1= Transmit pause enabled"]
            #[inline(always)]
            #[must_use]
            pub fn txp(&mut self) -> TXP_W<CCCR_SPEC> {
                TXP_W::new(self, 14)
            }
            #[doc = "Bit 15 - Non ISO Operation If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0. 0= CAN FD frame format according to ISO 11898-1:2015 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015."]
            #[inline(always)]
            #[must_use]
            pub fn niso(&mut self) -> NISO_W<CCCR_SPEC> {
                NISO_W::new(self, 15)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "CC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cccr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CCCR_SPEC;
        impl crate::RegisterSpec for CCCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cccr::R`](R) reader structure"]
        impl crate::Readable for CCCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cccr::W`](W) writer structure"]
        impl crate::Writable for CCCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CCCR to value 0x01"]
        impl crate::Resettable for CCCR_SPEC {
            const RESET_VALUE: u32 = 0x01;
        }
    }
    #[doc = "NBTP (rw) register accessor: nominal bit timing and prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nbtp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nbtp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nbtp`]
module"]
    pub type NBTP = crate::Reg<nbtp::NBTP_SPEC>;
    #[doc = "nominal bit timing and prescaler register"]
    pub mod nbtp {
        #[doc = "Register `NBTP` reader"]
        pub type R = crate::R<NBTP_SPEC>;
        #[doc = "Register `NBTP` writer"]
        pub type W = crate::W<NBTP_SPEC>;
        #[doc = "Field `NTSEG2` reader - Nominal Time segment after sample point Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type NTSEG2_R = crate::FieldReader;
        #[doc = "Field `NTSEG2` writer - Nominal Time segment after sample point Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type NTSEG2_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `NTSEG1` reader - Nominal Time segment before sample point Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type NTSEG1_R = crate::FieldReader;
        #[doc = "Field `NTSEG1` writer - Nominal Time segment before sample point Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
        pub type NTSEG1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `NBRP` reader - Nominal Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type NBRP_R = crate::FieldReader<u16>;
        #[doc = "Field `NBRP` writer - Nominal Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type NBRP_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `NSJW` reader - Nominal (Re)Synchronization Jump Width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type NSJW_R = crate::FieldReader;
        #[doc = "Field `NSJW` writer - Nominal (Re)Synchronization Jump Width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type NSJW_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bits 0:6 - Nominal Time segment after sample point Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            pub fn ntseg2(&self) -> NTSEG2_R {
                NTSEG2_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bits 8:15 - Nominal Time segment before sample point Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            pub fn ntseg1(&self) -> NTSEG1_R {
                NTSEG1_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:24 - Nominal Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            pub fn nbrp(&self) -> NBRP_R {
                NBRP_R::new(((self.bits >> 16) & 0x01ff) as u16)
            }
            #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            pub fn nsjw(&self) -> NSJW_R {
                NSJW_R::new(((self.bits >> 25) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - Nominal Time segment after sample point Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            #[must_use]
            pub fn ntseg2(&mut self) -> NTSEG2_W<NBTP_SPEC> {
                NTSEG2_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - Nominal Time segment before sample point Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used."]
            #[inline(always)]
            #[must_use]
            pub fn ntseg1(&mut self) -> NTSEG1_W<NBTP_SPEC> {
                NTSEG1_W::new(self, 8)
            }
            #[doc = "Bits 16:24 - Nominal Bit Rate Prescaler The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            #[must_use]
            pub fn nbrp(&mut self) -> NBRP_W<NBTP_SPEC> {
                NBRP_W::new(self, 16)
            }
            #[doc = "Bits 25:31 - Nominal (Re)Synchronization Jump Width Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            #[must_use]
            pub fn nsjw(&mut self) -> NSJW_W<NBTP_SPEC> {
                NSJW_W::new(self, 25)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "nominal bit timing and prescaler register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nbtp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nbtp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct NBTP_SPEC;
        impl crate::RegisterSpec for NBTP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`nbtp::R`](R) reader structure"]
        impl crate::Readable for NBTP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`nbtp::W`](W) writer structure"]
        impl crate::Writable for NBTP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets NBTP to value 0x0600_0a03"]
        impl crate::Resettable for NBTP_SPEC {
            const RESET_VALUE: u32 = 0x0600_0a03;
        }
    }
    #[doc = "TSCC (rw) register accessor: timestamp counter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tscc`]
module"]
    pub type TSCC = crate::Reg<tscc::TSCC_SPEC>;
    #[doc = "timestamp counter configuration"]
    pub mod tscc {
        #[doc = "Register `TSCC` reader"]
        pub type R = crate::R<TSCC_SPEC>;
        #[doc = "Register `TSCC` writer"]
        pub type W = crate::W<TSCC_SPEC>;
        #[doc = "Field `TSS` reader - timestamp Select 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as “00”"]
        pub type TSS_R = crate::FieldReader;
        #[doc = "Field `TSS` writer - timestamp Select 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as “00”"]
        pub type TSS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TCP` reader - Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times \\[1…16\\]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type TCP_R = crate::FieldReader;
        #[doc = "Field `TCP` writer - Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times \\[1…16\\]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
        pub type TCP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:1 - timestamp Select 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as “00”"]
            #[inline(always)]
            pub fn tss(&self) -> TSS_R {
                TSS_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bits 16:19 - Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times \\[1…16\\]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            pub fn tcp(&self) -> TCP_R {
                TCP_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - timestamp Select 00= Timestamp counter value always 0x0000 01= Timestamp counter value incremented according to TCP 10= External timestamp counter value used 11= Same as “00”"]
            #[inline(always)]
            #[must_use]
            pub fn tss(&mut self) -> TSS_W<TSCC_SPEC> {
                TSS_W::new(self, 0)
            }
            #[doc = "Bits 16:19 - Timestamp Counter Prescaler Configures the timestamp and timeout counters time unit in multiples of CAN bit times \\[1…16\\]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used."]
            #[inline(always)]
            #[must_use]
            pub fn tcp(&mut self) -> TCP_W<TSCC_SPEC> {
                TCP_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp counter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TSCC_SPEC;
        impl crate::RegisterSpec for TSCC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tscc::R`](R) reader structure"]
        impl crate::Readable for TSCC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tscc::W`](W) writer structure"]
        impl crate::Writable for TSCC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TSCC to value 0"]
        impl crate::Resettable for TSCC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TSCV (rw) register accessor: timestamp counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tscv`]
module"]
    pub type TSCV = crate::Reg<tscv::TSCV_SPEC>;
    #[doc = "timestamp counter value"]
    pub mod tscv {
        #[doc = "Register `TSCV` reader"]
        pub type R = crate::R<TSCV_SPEC>;
        #[doc = "Register `TSCV` writer"]
        pub type W = crate::W<TSCV_SPEC>;
        #[doc = "Field `TSC` reader - Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times \\[1…16\\]
depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact."]
        pub type TSC_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times \\[1…16\\]
depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact."]
            #[inline(always)]
            pub fn tsc(&self) -> TSC_R {
                TSC_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TSCV_SPEC;
        impl crate::RegisterSpec for TSCV_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tscv::R`](R) reader structure"]
        impl crate::Readable for TSCV_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tscv::W`](W) writer structure"]
        impl crate::Writable for TSCV_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TSCV to value 0"]
        impl crate::Resettable for TSCV_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TOCC (rw) register accessor: timeout counter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tocc`]
module"]
    pub type TOCC = crate::Reg<tocc::TOCC_SPEC>;
    #[doc = "timeout counter configuration"]
    pub mod tocc {
        #[doc = "Register `TOCC` reader"]
        pub type R = crate::R<TOCC_SPEC>;
        #[doc = "Register `TOCC` writer"]
        pub type W = crate::W<TOCC_SPEC>;
        #[doc = "Field `RP` reader - Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled"]
        pub type RP_R = crate::BitReader;
        #[doc = "Field `RP` writer - Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled"]
        pub type RP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TOS` reader - Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1"]
        pub type TOS_R = crate::FieldReader;
        #[doc = "Field `TOS` writer - Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1"]
        pub type TOS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TOP` reader - Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period."]
        pub type TOP_R = crate::FieldReader<u16>;
        #[doc = "Field `TOP` writer - Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period."]
        pub type TOP_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bit 0 - Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled"]
            #[inline(always)]
            pub fn rp(&self) -> RP_R {
                RP_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:2 - Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1"]
            #[inline(always)]
            pub fn tos(&self) -> TOS_R {
                TOS_R::new(((self.bits >> 1) & 3) as u8)
            }
            #[doc = "Bits 16:31 - Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period."]
            #[inline(always)]
            pub fn top(&self) -> TOP_R {
                TOP_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable Timeout Counter 0= Timeout Counter disabled 1= Timeout Counter enabled"]
            #[inline(always)]
            #[must_use]
            pub fn rp(&mut self) -> RP_W<TOCC_SPEC> {
                RP_W::new(self, 0)
            }
            #[doc = "Bits 1:2 - Timeout Select When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. 00= Continuous operation 01= Timeout controlled by Tx Event FIFO 10= Timeout controlled by Rx FIFO 0 11= Timeout controlled by Rx FIFO 1"]
            #[inline(always)]
            #[must_use]
            pub fn tos(&mut self) -> TOS_W<TOCC_SPEC> {
                TOS_W::new(self, 1)
            }
            #[doc = "Bits 16:31 - Timeout Period Start value of the Timeout Counter (down-counter). Configures the Timeout Period."]
            #[inline(always)]
            #[must_use]
            pub fn top(&mut self) -> TOP_W<TOCC_SPEC> {
                TOP_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timeout counter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TOCC_SPEC;
        impl crate::RegisterSpec for TOCC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tocc::R`](R) reader structure"]
        impl crate::Readable for TOCC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tocc::W`](W) writer structure"]
        impl crate::Writable for TOCC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TOCC to value 0xffff_0000"]
        impl crate::Resettable for TOCC_SPEC {
            const RESET_VALUE: u32 = 0xffff_0000;
        }
    }
    #[doc = "TOCV (rw) register accessor: timeout counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tocv`]
module"]
    pub type TOCV = crate::Reg<tocv::TOCV_SPEC>;
    #[doc = "timeout counter value"]
    pub mod tocv {
        #[doc = "Register `TOCV` reader"]
        pub type R = crate::R<TOCV_SPEC>;
        #[doc = "Register `TOCV` writer"]
        pub type W = crate::W<TOCV_SPEC>;
        #[doc = "Field `TOC` reader - Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times \\[1…16\\]
depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter."]
        pub type TOC_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times \\[1…16\\]
depending on the configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter."]
            #[inline(always)]
            pub fn toc(&self) -> TOC_R {
                TOC_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timeout counter value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tocv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tocv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TOCV_SPEC;
        impl crate::RegisterSpec for TOCV_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tocv::R`](R) reader structure"]
        impl crate::Readable for TOCV_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tocv::W`](W) writer structure"]
        impl crate::Writable for TOCV_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TOCV to value 0xffff"]
        impl crate::Resettable for TOCV_SPEC {
            const RESET_VALUE: u32 = 0xffff;
        }
    }
    #[doc = "ECR (rw) register accessor: error counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ecr`]
module"]
    pub type ECR = crate::Reg<ecr::ECR_SPEC>;
    #[doc = "error counter register"]
    pub mod ecr {
        #[doc = "Register `ECR` reader"]
        pub type R = crate::R<ECR_SPEC>;
        #[doc = "Register `ECR` writer"]
        pub type W = crate::W<ECR_SPEC>;
        #[doc = "Field `TEC` reader - Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255 Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented."]
        pub type TEC_R = crate::FieldReader;
        #[doc = "Field `REC` reader - Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127"]
        pub type REC_R = crate::FieldReader;
        #[doc = "Field `RP` reader - Receive Error Passive 0= The Receive Error Counter is below the error passive level of 128 1= The Receive Error Counter has reached the error passive level of 128"]
        pub type RP_R = crate::BitReader;
        #[doc = "Field `CEL` reader - CAN Error Logging The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact."]
        pub type CEL_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Transmit Error Counter Actual state of the Transmit Error Counter, values between 0 and 255 Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented."]
            #[inline(always)]
            pub fn tec(&self) -> TEC_R {
                TEC_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:14 - Receive Error Counter Actual state of the Receive Error Counter, values between 0 and 127"]
            #[inline(always)]
            pub fn rec(&self) -> REC_R {
                REC_R::new(((self.bits >> 8) & 0x7f) as u8)
            }
            #[doc = "Bit 15 - Receive Error Passive 0= The Receive Error Counter is below the error passive level of 128 1= The Receive Error Counter has reached the error passive level of 128"]
            #[inline(always)]
            pub fn rp(&self) -> RP_R {
                RP_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bits 16:23 - CAN Error Logging The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact."]
            #[inline(always)]
            pub fn cel(&self) -> CEL_R {
                CEL_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "error counter register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ecr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ecr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ECR_SPEC;
        impl crate::RegisterSpec for ECR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ecr::R`](R) reader structure"]
        impl crate::Readable for ECR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ecr::W`](W) writer structure"]
        impl crate::Writable for ECR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ECR to value 0"]
        impl crate::Resettable for ECR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PSR (rw) register accessor: protocol status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psr`]
module"]
    pub type PSR = crate::Reg<psr::PSR_SPEC>;
    #[doc = "protocol status register"]
    pub mod psr {
        #[doc = "Register `PSR` reader"]
        pub type R = crate::R<PSR_SPEC>;
        #[doc = "Register `PSR` writer"]
        pub type W = crate::W<PSR_SPEC>;
        #[doc = "Field `LEC` reader - Last Error Code The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2= Form Error: A fixed format part of a received frame has the wrong format. 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant. 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact."]
        pub type LEC_R = crate::FieldReader;
        #[doc = "Field `ACT` reader - Activity Monitors the module’s CAN communication state. 00= Synchronizing - node is synchronizing on CAN communication 01= Idle - node is neither receiver nor transmitter 10= Receiver - node is operating as receiver 11= Transmitter - node is operating as transmitter Note: ACT is set to “00” by a Protocol Exception Event."]
        pub type ACT_R = crate::FieldReader;
        #[doc = "Field `EP` reader - Error Passive 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1= The M_CAN is in the Error_Passive state"]
        pub type EP_R = crate::BitReader;
        #[doc = "Field `EW` reader - Warning Status 0= Both error counters are below the Error_Warning limit of 96 1= At least one of error counter has reached the Error_Warning limit of 96"]
        pub type EW_R = crate::BitReader;
        #[doc = "Field `BO` reader - Bus_Off Status 0= The M_CAN is not Bus_Off 1= The M_CAN is in Bus_Off state"]
        pub type BO_R = crate::BitReader;
        #[doc = "Field `DLEC` reader - Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact."]
        pub type DLEC_R = crate::FieldReader;
        #[doc = "Field `RESI` reader - ESI flag of last received CAN FD Message This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its ESI flag set 1= Last received CAN FD message had its ESI flag set Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact."]
        pub type RESI_R = crate::BitReader;
        #[doc = "Field `RBRS` reader - BRS flag of last received CAN FD Message This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its BRS flag set 1= Last received CAN FD message had its BRS flag set Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact."]
        pub type RBRS_R = crate::BitReader;
        #[doc = "Field `RFDF` reader - Received a CAN FD Message This bit is set independent of acceptance filtering. 0= Since this bit was reset by the CPU, no CAN FD message has been received 1= Message in CAN FD format with FDF flag set has been received Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact."]
        pub type RFDF_R = crate::BitReader;
        #[doc = "Field `PXE` reader - Protocol Exception Event 0= No protocol exception event occurred since last read access 1= Protocol exception event occurred Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact."]
        pub type PXE_R = crate::BitReader;
        #[doc = "Field `TDCV` reader - Transmitter Delay Compensation Value Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq."]
        pub type TDCV_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:2 - Last Error Code The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 2= Form Error: A fixed format part of a received frame has the wrong format. 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus value was dominant. 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact."]
            #[inline(always)]
            pub fn lec(&self) -> LEC_R {
                LEC_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bits 3:4 - Activity Monitors the module’s CAN communication state. 00= Synchronizing - node is synchronizing on CAN communication 01= Idle - node is neither receiver nor transmitter 10= Receiver - node is operating as receiver 11= Transmitter - node is operating as transmitter Note: ACT is set to “00” by a Protocol Exception Event."]
            #[inline(always)]
            pub fn act(&self) -> ACT_R {
                ACT_R::new(((self.bits >> 3) & 3) as u8)
            }
            #[doc = "Bit 5 - Error Passive 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected 1= The M_CAN is in the Error_Passive state"]
            #[inline(always)]
            pub fn ep(&self) -> EP_R {
                EP_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Warning Status 0= Both error counters are below the Error_Warning limit of 96 1= At least one of error counter has reached the Error_Warning limit of 96"]
            #[inline(always)]
            pub fn ew(&self) -> EW_R {
                EW_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Bus_Off Status 0= The M_CAN is not Bus_Off 1= The M_CAN is in Bus_Off state"]
            #[inline(always)]
            pub fn bo(&self) -> BO_R {
                BO_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:10 - Data Phase Last Error Code Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error. Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact."]
            #[inline(always)]
            pub fn dlec(&self) -> DLEC_R {
                DLEC_R::new(((self.bits >> 8) & 7) as u8)
            }
            #[doc = "Bit 11 - ESI flag of last received CAN FD Message This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its ESI flag set 1= Last received CAN FD message had its ESI flag set Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact."]
            #[inline(always)]
            pub fn resi(&self) -> RESI_R {
                RESI_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - BRS flag of last received CAN FD Message This bit is set together with RFDF, independent of acceptance filtering. 0= Last received CAN FD message did not have its BRS flag set 1= Last received CAN FD message had its BRS flag set Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact."]
            #[inline(always)]
            pub fn rbrs(&self) -> RBRS_R {
                RBRS_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Received a CAN FD Message This bit is set independent of acceptance filtering. 0= Since this bit was reset by the CPU, no CAN FD message has been received 1= Message in CAN FD format with FDF flag set has been received Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact."]
            #[inline(always)]
            pub fn rfdf(&self) -> RFDF_R {
                RFDF_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - Protocol Exception Event 0= No protocol exception event occurred since last read access 1= Protocol exception event occurred Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact."]
            #[inline(always)]
            pub fn pxe(&self) -> PXE_R {
                PXE_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bits 16:22 - Transmitter Delay Compensation Value Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq."]
            #[inline(always)]
            pub fn tdcv(&self) -> TDCV_R {
                TDCV_R::new(((self.bits >> 16) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "protocol status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PSR_SPEC;
        impl crate::RegisterSpec for PSR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`psr::R`](R) reader structure"]
        impl crate::Readable for PSR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`psr::W`](W) writer structure"]
        impl crate::Writable for PSR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PSR to value 0x0707"]
        impl crate::Resettable for PSR_SPEC {
            const RESET_VALUE: u32 = 0x0707;
        }
    }
    #[doc = "TDCR (rw) register accessor: transmitter delay compensation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdcr`]
module"]
    pub type TDCR = crate::Reg<tdcr::TDCR_SPEC>;
    #[doc = "transmitter delay compensation"]
    pub mod tdcr {
        #[doc = "Register `TDCR` reader"]
        pub type R = crate::R<TDCR_SPEC>;
        #[doc = "Register `TDCR` writer"]
        pub type W = crate::W<TDCR_SPEC>;
        #[doc = "Field `TDCF` reader - Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq."]
        pub type TDCF_R = crate::FieldReader;
        #[doc = "Field `TDCF` writer - Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq."]
        pub type TDCF_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `TDCO` reader - Transmitter Delay Compensation SSP Offset Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq."]
        pub type TDCO_R = crate::FieldReader;
        #[doc = "Field `TDCO` writer - Transmitter Delay Compensation SSP Offset Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq."]
        pub type TDCO_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq."]
            #[inline(always)]
            pub fn tdcf(&self) -> TDCF_R {
                TDCF_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bits 8:14 - Transmitter Delay Compensation SSP Offset Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq."]
            #[inline(always)]
            pub fn tdco(&self) -> TDCO_R {
                TDCO_R::new(((self.bits >> 8) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - Transmitter Delay Compensation Filter Window Length Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq."]
            #[inline(always)]
            #[must_use]
            pub fn tdcf(&mut self) -> TDCF_W<TDCR_SPEC> {
                TDCF_W::new(self, 0)
            }
            #[doc = "Bits 8:14 - Transmitter Delay Compensation SSP Offset Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq."]
            #[inline(always)]
            #[must_use]
            pub fn tdco(&mut self) -> TDCO_W<TDCR_SPEC> {
                TDCO_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "transmitter delay compensation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tdcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TDCR_SPEC;
        impl crate::RegisterSpec for TDCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tdcr::R`](R) reader structure"]
        impl crate::Readable for TDCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tdcr::W`](W) writer structure"]
        impl crate::Writable for TDCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TDCR to value 0"]
        impl crate::Resettable for TDCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IR (rw) register accessor: interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`]
module"]
    pub type IR = crate::Reg<ir::IR_SPEC>;
    #[doc = "interrupt register"]
    pub mod ir {
        #[doc = "Register `IR` reader"]
        pub type R = crate::R<IR_SPEC>;
        #[doc = "Register `IR` writer"]
        pub type W = crate::W<IR_SPEC>;
        #[doc = "Field `RF0N` reader - Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0"]
        pub type RF0N_R = crate::BitReader;
        #[doc = "Field `RF0N` writer - Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0"]
        pub type RF0N_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0W` reader - Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark"]
        pub type RF0W_R = crate::BitReader;
        #[doc = "Field `RF0W` writer - Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark"]
        pub type RF0W_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0F` reader - Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full"]
        pub type RF0F_R = crate::BitReader;
        #[doc = "Field `RF0F` writer - Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full"]
        pub type RF0F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero"]
        pub type RF0L_R = crate::BitReader;
        #[doc = "Field `RF0L` writer - Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero"]
        pub type RF0L_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1N` reader - Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1"]
        pub type RF1N_R = crate::BitReader;
        #[doc = "Field `RF1N` writer - Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1"]
        pub type RF1N_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1W` reader - Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark"]
        pub type RF1W_R = crate::BitReader;
        #[doc = "Field `RF1W` writer - Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark"]
        pub type RF1W_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1F` reader - Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full"]
        pub type RF1F_R = crate::BitReader;
        #[doc = "Field `RF1F` writer - Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full"]
        pub type RF1F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero"]
        pub type RF1L_R = crate::BitReader;
        #[doc = "Field `RF1L` writer - Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero"]
        pub type RF1L_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HPM` reader - High Priority Message 0= No high priority message received 1= High priority message received"]
        pub type HPM_R = crate::BitReader;
        #[doc = "Field `HPM` writer - High Priority Message 0= No high priority message received 1= High priority message received"]
        pub type HPM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TC` reader - Transmission Completed 0= No transmission completed 1= Transmission completed"]
        pub type TC_R = crate::BitReader;
        #[doc = "Field `TC` writer - Transmission Completed 0= No transmission completed 1= Transmission completed"]
        pub type TC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TCF` reader - Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished"]
        pub type TCF_R = crate::BitReader;
        #[doc = "Field `TCF` writer - Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished"]
        pub type TCF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFE` reader - Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty"]
        pub type TFE_R = crate::BitReader;
        #[doc = "Field `TFE` writer - Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty"]
        pub type TFE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFN` reader - Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element"]
        pub type TEFN_R = crate::BitReader;
        #[doc = "Field `TEFN` writer - Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element"]
        pub type TEFN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFW` reader - Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark"]
        pub type TEFW_R = crate::BitReader;
        #[doc = "Field `TEFW` writer - Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark"]
        pub type TEFW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFF` reader - Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full"]
        pub type TEFF_R = crate::BitReader;
        #[doc = "Field `TEFF` writer - Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full"]
        pub type TEFF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero"]
        pub type TEFL_R = crate::BitReader;
        #[doc = "Field `TEFL` writer - Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero"]
        pub type TEFL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TSW` reader - Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around"]
        pub type TSW_R = crate::BitReader;
        #[doc = "Field `TSW` writer - Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around"]
        pub type TSW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MRAF` reader - Message RAM Access Failure The flag is set, when the Rx Handler .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. .was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred"]
        pub type MRAF_R = crate::BitReader;
        #[doc = "Field `MRAF` writer - Message RAM Access Failure The flag is set, when the Rx Handler .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. .was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred"]
        pub type MRAF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TOO` reader - Timeout Occurred 0= No timeout 1= Timeout reached"]
        pub type TOO_R = crate::BitReader;
        #[doc = "Field `TOO` writer - Timeout Occurred 0= No timeout 1= Timeout reached"]
        pub type TOO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DRX` reader - Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into an Rx Buffer"]
        pub type DRX_R = crate::BitReader;
        #[doc = "Field `DRX` writer - Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into an Rx Buffer"]
        pub type DRX_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BEC` reader - Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr\\[0\\]
generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC)"]
        pub type BEC_R = crate::BitReader;
        #[doc = "Field `BEC` writer - Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr\\[0\\]
generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC)"]
        pub type BEC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BEU` reader - Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr\\[1\\]
generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic)"]
        pub type BEU_R = crate::BitReader;
        #[doc = "Field `BEU` writer - Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr\\[1\\]
generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic)"]
        pub type BEU_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ELO` reader - Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred"]
        pub type ELO_R = crate::BitReader;
        #[doc = "Field `ELO` writer - Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred"]
        pub type ELO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EP` reader - Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed"]
        pub type EP_R = crate::BitReader;
        #[doc = "Field `EP` writer - Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed"]
        pub type EP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EW` reader - Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed"]
        pub type EW_R = crate::BitReader;
        #[doc = "Field `EW` writer - Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed"]
        pub type EW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BO` reader - Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed"]
        pub type BO_R = crate::BitReader;
        #[doc = "Field `BO` writer - Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed"]
        pub type BO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDI` reader - Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY"]
        pub type WDI_R = crate::BitReader;
        #[doc = "Field `WDI` writer - Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY"]
        pub type WDI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PEA` reader - Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)"]
        pub type PEA_R = crate::BitReader;
        #[doc = "Field `PEA` writer - Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)"]
        pub type PEA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PED` reader - Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7)"]
        pub type PED_R = crate::BitReader;
        #[doc = "Field `PED` writer - Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7)"]
        pub type PED_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ARA` reader - Access to Reserved Address 0= No access to reserved address occurred 1= Access to reserved address occurred"]
        pub type ARA_R = crate::BitReader;
        #[doc = "Field `ARA` writer - Access to Reserved Address 0= No access to reserved address occurred 1= Access to reserved address occurred"]
        pub type ARA_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0"]
            #[inline(always)]
            pub fn rf0n(&self) -> RF0N_R {
                RF0N_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark"]
            #[inline(always)]
            pub fn rf0w(&self) -> RF0W_R {
                RF0W_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full"]
            #[inline(always)]
            pub fn rf0f(&self) -> RF0F_R {
                RF0F_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero"]
            #[inline(always)]
            pub fn rf0l(&self) -> RF0L_R {
                RF0L_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1"]
            #[inline(always)]
            pub fn rf1n(&self) -> RF1N_R {
                RF1N_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark"]
            #[inline(always)]
            pub fn rf1w(&self) -> RF1W_R {
                RF1W_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full"]
            #[inline(always)]
            pub fn rf1f(&self) -> RF1F_R {
                RF1F_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero"]
            #[inline(always)]
            pub fn rf1l(&self) -> RF1L_R {
                RF1L_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - High Priority Message 0= No high priority message received 1= High priority message received"]
            #[inline(always)]
            pub fn hpm(&self) -> HPM_R {
                HPM_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Transmission Completed 0= No transmission completed 1= Transmission completed"]
            #[inline(always)]
            pub fn tc(&self) -> TC_R {
                TC_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished"]
            #[inline(always)]
            pub fn tcf(&self) -> TCF_R {
                TCF_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty"]
            #[inline(always)]
            pub fn tfe(&self) -> TFE_R {
                TFE_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element"]
            #[inline(always)]
            pub fn tefn(&self) -> TEFN_R {
                TEFN_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark"]
            #[inline(always)]
            pub fn tefw(&self) -> TEFW_R {
                TEFW_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full"]
            #[inline(always)]
            pub fn teff(&self) -> TEFF_R {
                TEFF_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero"]
            #[inline(always)]
            pub fn tefl(&self) -> TEFL_R {
                TEFL_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around"]
            #[inline(always)]
            pub fn tsw(&self) -> TSW_R {
                TSW_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - Message RAM Access Failure The flag is set, when the Rx Handler .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. .was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred"]
            #[inline(always)]
            pub fn mraf(&self) -> MRAF_R {
                MRAF_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - Timeout Occurred 0= No timeout 1= Timeout reached"]
            #[inline(always)]
            pub fn too(&self) -> TOO_R {
                TOO_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into an Rx Buffer"]
            #[inline(always)]
            pub fn drx(&self) -> DRX_R {
                DRX_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr\\[0\\]
generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC)"]
            #[inline(always)]
            pub fn bec(&self) -> BEC_R {
                BEC_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr\\[1\\]
generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic)"]
            #[inline(always)]
            pub fn beu(&self) -> BEU_R {
                BEU_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred"]
            #[inline(always)]
            pub fn elo(&self) -> ELO_R {
                ELO_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed"]
            #[inline(always)]
            pub fn ep(&self) -> EP_R {
                EP_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed"]
            #[inline(always)]
            pub fn ew(&self) -> EW_R {
                EW_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed"]
            #[inline(always)]
            pub fn bo(&self) -> BO_R {
                BO_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY"]
            #[inline(always)]
            pub fn wdi(&self) -> WDI_R {
                WDI_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)"]
            #[inline(always)]
            pub fn pea(&self) -> PEA_R {
                PEA_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7)"]
            #[inline(always)]
            pub fn ped(&self) -> PED_R {
                PED_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - Access to Reserved Address 0= No access to reserved address occurred 1= Access to reserved address occurred"]
            #[inline(always)]
            pub fn ara(&self) -> ARA_R {
                ARA_R::new(((self.bits >> 29) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Rx FIFO 0 New Message 0= No new message written to Rx FIFO 0 1= New message written to Rx FIFO 0"]
            #[inline(always)]
            #[must_use]
            pub fn rf0n(&mut self) -> RF0N_W<IR_SPEC> {
                RF0N_W::new(self, 0)
            }
            #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached 0= Rx FIFO 0 fill level below watermark 1= Rx FIFO 0 fill level reached watermark"]
            #[inline(always)]
            #[must_use]
            pub fn rf0w(&mut self) -> RF0W_W<IR_SPEC> {
                RF0W_W::new(self, 1)
            }
            #[doc = "Bit 2 - Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full"]
            #[inline(always)]
            #[must_use]
            pub fn rf0f(&mut self) -> RF0F_W<IR_SPEC> {
                RF0F_W::new(self, 2)
            }
            #[doc = "Bit 3 - Rx FIFO 0 Message Lost 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero"]
            #[inline(always)]
            #[must_use]
            pub fn rf0l(&mut self) -> RF0L_W<IR_SPEC> {
                RF0L_W::new(self, 3)
            }
            #[doc = "Bit 4 - Rx FIFO 1 New Message 0= No new message written to Rx FIFO 1 1= New message written to Rx FIFO 1"]
            #[inline(always)]
            #[must_use]
            pub fn rf1n(&mut self) -> RF1N_W<IR_SPEC> {
                RF1N_W::new(self, 4)
            }
            #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached 0= Rx FIFO 1 fill level below watermark 1= Rx FIFO 1 fill level reached watermark"]
            #[inline(always)]
            #[must_use]
            pub fn rf1w(&mut self) -> RF1W_W<IR_SPEC> {
                RF1W_W::new(self, 5)
            }
            #[doc = "Bit 6 - Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full"]
            #[inline(always)]
            #[must_use]
            pub fn rf1f(&mut self) -> RF1F_W<IR_SPEC> {
                RF1F_W::new(self, 6)
            }
            #[doc = "Bit 7 - Rx FIFO 1 Message Lost 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero"]
            #[inline(always)]
            #[must_use]
            pub fn rf1l(&mut self) -> RF1L_W<IR_SPEC> {
                RF1L_W::new(self, 7)
            }
            #[doc = "Bit 8 - High Priority Message 0= No high priority message received 1= High priority message received"]
            #[inline(always)]
            #[must_use]
            pub fn hpm(&mut self) -> HPM_W<IR_SPEC> {
                HPM_W::new(self, 8)
            }
            #[doc = "Bit 9 - Transmission Completed 0= No transmission completed 1= Transmission completed"]
            #[inline(always)]
            #[must_use]
            pub fn tc(&mut self) -> TC_W<IR_SPEC> {
                TC_W::new(self, 9)
            }
            #[doc = "Bit 10 - Transmission Cancellation Finished 0= No transmission cancellation finished 1= Transmission cancellation finished"]
            #[inline(always)]
            #[must_use]
            pub fn tcf(&mut self) -> TCF_W<IR_SPEC> {
                TCF_W::new(self, 10)
            }
            #[doc = "Bit 11 - Tx FIFO Empty 0= Tx FIFO non-empty 1= Tx FIFO empty"]
            #[inline(always)]
            #[must_use]
            pub fn tfe(&mut self) -> TFE_W<IR_SPEC> {
                TFE_W::new(self, 11)
            }
            #[doc = "Bit 12 - Tx Event FIFO New Entry 0= Tx Event FIFO unchanged 1= Tx Handler wrote Tx Event FIFO element"]
            #[inline(always)]
            #[must_use]
            pub fn tefn(&mut self) -> TEFN_W<IR_SPEC> {
                TEFN_W::new(self, 12)
            }
            #[doc = "Bit 13 - Tx Event FIFO Watermark Reached 0= Tx Event FIFO fill level below watermark 1= Tx Event FIFO fill level reached watermark"]
            #[inline(always)]
            #[must_use]
            pub fn tefw(&mut self) -> TEFW_W<IR_SPEC> {
                TEFW_W::new(self, 13)
            }
            #[doc = "Bit 14 - Tx Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full"]
            #[inline(always)]
            #[must_use]
            pub fn teff(&mut self) -> TEFF_W<IR_SPEC> {
                TEFF_W::new(self, 14)
            }
            #[doc = "Bit 15 - Tx Event FIFO Element Lost 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero"]
            #[inline(always)]
            #[must_use]
            pub fn tefl(&mut self) -> TEFL_W<IR_SPEC> {
                TEFL_W::new(self, 15)
            }
            #[doc = "Bit 16 - Timestamp Wraparound 0= No timestamp counter wrap-around 1= Timestamp counter wrapped around"]
            #[inline(always)]
            #[must_use]
            pub fn tsw(&mut self) -> TSW_W<IR_SPEC> {
                TSW_W::new(self, 16)
            }
            #[doc = "Bit 17 - Message RAM Access Failure The flag is set, when the Rx Handler .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message. .was not able to write a message to the Message RAM. In this case message storage is aborted. In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0= No Message RAM access failure occurred 1= Message RAM access failure occurred"]
            #[inline(always)]
            #[must_use]
            pub fn mraf(&mut self) -> MRAF_W<IR_SPEC> {
                MRAF_W::new(self, 17)
            }
            #[doc = "Bit 18 - Timeout Occurred 0= No timeout 1= Timeout reached"]
            #[inline(always)]
            #[must_use]
            pub fn too(&mut self) -> TOO_W<IR_SPEC> {
                TOO_W::new(self, 18)
            }
            #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0= No Rx Buffer updated 1= At least one received message stored into an Rx Buffer"]
            #[inline(always)]
            #[must_use]
            pub fn drx(&mut self) -> DRX_W<IR_SPEC> {
                DRX_W::new(self, 19)
            }
            #[doc = "Bit 20 - Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr\\[0\\]
generated by an optional external parity / ECC logic attached to the Message RAM. 0= No bit error detected when reading from Message RAM 1= Bit error detected and corrected (e.g. ECC)"]
            #[inline(always)]
            #[must_use]
            pub fn bec(&mut self) -> BEC_W<IR_SPEC> {
                BEC_W::new(self, 20)
            }
            #[doc = "Bit 21 - Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr\\[1\\]
generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. 0= No bit error detected when reading from Message RAM 1= Bit error detected, uncorrected (e.g. parity logic)"]
            #[inline(always)]
            #[must_use]
            pub fn beu(&mut self) -> BEU_W<IR_SPEC> {
                BEU_W::new(self, 21)
            }
            #[doc = "Bit 22 - Error Logging Overflow 0= CAN Error Logging Counter did not overflow 1= Overflow of CAN Error Logging Counter occurred"]
            #[inline(always)]
            #[must_use]
            pub fn elo(&mut self) -> ELO_W<IR_SPEC> {
                ELO_W::new(self, 22)
            }
            #[doc = "Bit 23 - Error Passive 0= Error_Passive status unchanged 1= Error_Passive status changed"]
            #[inline(always)]
            #[must_use]
            pub fn ep(&mut self) -> EP_W<IR_SPEC> {
                EP_W::new(self, 23)
            }
            #[doc = "Bit 24 - Warning Status 0= Error_Warning status unchanged 1= Error_Warning status changed"]
            #[inline(always)]
            #[must_use]
            pub fn ew(&mut self) -> EW_W<IR_SPEC> {
                EW_W::new(self, 24)
            }
            #[doc = "Bit 25 - Bus_Off Status 0= Bus_Off status unchanged 1= Bus_Off status changed"]
            #[inline(always)]
            #[must_use]
            pub fn bo(&mut self) -> BO_W<IR_SPEC> {
                BO_W::new(self, 25)
            }
            #[doc = "Bit 26 - Watchdog Interrupt 0= No Message RAM Watchdog event occurred 1= Message RAM Watchdog event due to missing READY"]
            #[inline(always)]
            #[must_use]
            pub fn wdi(&mut self) -> WDI_W<IR_SPEC> {
                WDI_W::new(self, 26)
            }
            #[doc = "Bit 27 - Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0= No protocol error in arbitration phase 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7)"]
            #[inline(always)]
            #[must_use]
            pub fn pea(&mut self) -> PEA_W<IR_SPEC> {
                PEA_W::new(self, 27)
            }
            #[doc = "Bit 28 - Protocol Error in Data Phase (Data Bit Time is used) 0= No protocol error in data phase 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7)"]
            #[inline(always)]
            #[must_use]
            pub fn ped(&mut self) -> PED_W<IR_SPEC> {
                PED_W::new(self, 28)
            }
            #[doc = "Bit 29 - Access to Reserved Address 0= No access to reserved address occurred 1= Access to reserved address occurred"]
            #[inline(always)]
            #[must_use]
            pub fn ara(&mut self) -> ARA_W<IR_SPEC> {
                ARA_W::new(self, 29)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "interrupt register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ir::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ir::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IR_SPEC;
        impl crate::RegisterSpec for IR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ir::R`](R) reader structure"]
        impl crate::Readable for IR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ir::W`](W) writer structure"]
        impl crate::Writable for IR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IR to value 0"]
        impl crate::Resettable for IR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IE (rw) register accessor: interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ie`]
module"]
    pub type IE = crate::Reg<ie::IE_SPEC>;
    #[doc = "interrupt enable"]
    pub mod ie {
        #[doc = "Register `IE` reader"]
        pub type R = crate::R<IE_SPEC>;
        #[doc = "Register `IE` writer"]
        pub type W = crate::W<IE_SPEC>;
        #[doc = "Field `RF0NE` reader - Rx FIFO 0 New Message Interrupt Enable"]
        pub type RF0NE_R = crate::BitReader;
        #[doc = "Field `RF0NE` writer - Rx FIFO 0 New Message Interrupt Enable"]
        pub type RF0NE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0WE` reader - Rx FIFO 0 Watermark Reached Interrupt Enable"]
        pub type RF0WE_R = crate::BitReader;
        #[doc = "Field `RF0WE` writer - Rx FIFO 0 Watermark Reached Interrupt Enable"]
        pub type RF0WE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0FE` reader - Rx FIFO 0 Full Interrupt Enable"]
        pub type RF0FE_R = crate::BitReader;
        #[doc = "Field `RF0FE` writer - Rx FIFO 0 Full Interrupt Enable"]
        pub type RF0FE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0LE` reader - Rx FIFO 0 Message Lost Interrupt Enable"]
        pub type RF0LE_R = crate::BitReader;
        #[doc = "Field `RF0LE` writer - Rx FIFO 0 Message Lost Interrupt Enable"]
        pub type RF0LE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1NE` reader - Rx FIFO 1 New Message Interrupt Enable"]
        pub type RF1NE_R = crate::BitReader;
        #[doc = "Field `RF1NE` writer - Rx FIFO 1 New Message Interrupt Enable"]
        pub type RF1NE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1WE` reader - Rx FIFO 1 Watermark Reached Interrupt Enable"]
        pub type RF1WE_R = crate::BitReader;
        #[doc = "Field `RF1WE` writer - Rx FIFO 1 Watermark Reached Interrupt Enable"]
        pub type RF1WE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1FE` reader - Rx FIFO 1 Full Interrupt Enable"]
        pub type RF1FE_R = crate::BitReader;
        #[doc = "Field `RF1FE` writer - Rx FIFO 1 Full Interrupt Enable"]
        pub type RF1FE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1LE` reader - Rx FIFO 1 Message Lost Interrupt Enable"]
        pub type RF1LE_R = crate::BitReader;
        #[doc = "Field `RF1LE` writer - Rx FIFO 1 Message Lost Interrupt Enable"]
        pub type RF1LE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HPME` reader - High Priority Message Interrupt Enable"]
        pub type HPME_R = crate::BitReader;
        #[doc = "Field `HPME` writer - High Priority Message Interrupt Enable"]
        pub type HPME_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TCE` reader - Transmission Completed Interrupt Enable"]
        pub type TCE_R = crate::BitReader;
        #[doc = "Field `TCE` writer - Transmission Completed Interrupt Enable"]
        pub type TCE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TCFE` reader - Transmission Cancellation Finished Interrupt Enable"]
        pub type TCFE_R = crate::BitReader;
        #[doc = "Field `TCFE` writer - Transmission Cancellation Finished Interrupt Enable"]
        pub type TCFE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFEE` reader - Tx FIFO Empty Interrupt Enable"]
        pub type TFEE_R = crate::BitReader;
        #[doc = "Field `TFEE` writer - Tx FIFO Empty Interrupt Enable"]
        pub type TFEE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFNE` reader - Tx Event FIFO New Entry Interrupt Enable"]
        pub type TEFNE_R = crate::BitReader;
        #[doc = "Field `TEFNE` writer - Tx Event FIFO New Entry Interrupt Enable"]
        pub type TEFNE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFWE` reader - Tx Event FIFO Watermark Reached Interrupt Enable"]
        pub type TEFWE_R = crate::BitReader;
        #[doc = "Field `TEFWE` writer - Tx Event FIFO Watermark Reached Interrupt Enable"]
        pub type TEFWE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFFE` reader - Tx Event FIFO Full Interrupt Enable"]
        pub type TEFFE_R = crate::BitReader;
        #[doc = "Field `TEFFE` writer - Tx Event FIFO Full Interrupt Enable"]
        pub type TEFFE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFLE` reader - Tx Event FIFO Event Lost Interrupt Enable"]
        pub type TEFLE_R = crate::BitReader;
        #[doc = "Field `TEFLE` writer - Tx Event FIFO Event Lost Interrupt Enable"]
        pub type TEFLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TSWE` reader - Timestamp Wraparound Interrupt Enable"]
        pub type TSWE_R = crate::BitReader;
        #[doc = "Field `TSWE` writer - Timestamp Wraparound Interrupt Enable"]
        pub type TSWE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MRAFE` reader - Message RAM Access Failure Interrupt Enable"]
        pub type MRAFE_R = crate::BitReader;
        #[doc = "Field `MRAFE` writer - Message RAM Access Failure Interrupt Enable"]
        pub type MRAFE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TOOE` reader - Timeout Occurred Interrupt Enable"]
        pub type TOOE_R = crate::BitReader;
        #[doc = "Field `TOOE` writer - Timeout Occurred Interrupt Enable"]
        pub type TOOE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DRXE` reader - Message stored to Dedicated Rx Buffer Interrupt Enable"]
        pub type DRXE_R = crate::BitReader;
        #[doc = "Field `DRXE` writer - Message stored to Dedicated Rx Buffer Interrupt Enable"]
        pub type DRXE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BECE` reader - Bit Error Corrected Interrupt Enable"]
        pub type BECE_R = crate::BitReader;
        #[doc = "Field `BECE` writer - Bit Error Corrected Interrupt Enable"]
        pub type BECE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BEUE` reader - Bit Error Uncorrected Interrupt Enable"]
        pub type BEUE_R = crate::BitReader;
        #[doc = "Field `BEUE` writer - Bit Error Uncorrected Interrupt Enable"]
        pub type BEUE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ELOE` reader - Error Logging Overflow Interrupt Enable"]
        pub type ELOE_R = crate::BitReader;
        #[doc = "Field `ELOE` writer - Error Logging Overflow Interrupt Enable"]
        pub type ELOE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPE` reader - Error Passive Interrupt Enable"]
        pub type EPE_R = crate::BitReader;
        #[doc = "Field `EPE` writer - Error Passive Interrupt Enable"]
        pub type EPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EWE` reader - Warning Status Interrupt Enable"]
        pub type EWE_R = crate::BitReader;
        #[doc = "Field `EWE` writer - Warning Status Interrupt Enable"]
        pub type EWE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BOE` reader - Bus_Off Status Interrupt Enable"]
        pub type BOE_R = crate::BitReader;
        #[doc = "Field `BOE` writer - Bus_Off Status Interrupt Enable"]
        pub type BOE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDIE` reader - Watchdog Interrupt Enable"]
        pub type WDIE_R = crate::BitReader;
        #[doc = "Field `WDIE` writer - Watchdog Interrupt Enable"]
        pub type WDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PEAE` reader - Protocol Error in Arbitration Phase Enable"]
        pub type PEAE_R = crate::BitReader;
        #[doc = "Field `PEAE` writer - Protocol Error in Arbitration Phase Enable"]
        pub type PEAE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PEDE` reader - Protocol Error in Data Phase Enable"]
        pub type PEDE_R = crate::BitReader;
        #[doc = "Field `PEDE` writer - Protocol Error in Data Phase Enable"]
        pub type PEDE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ARAE` reader - Access to Reserved Address Enable"]
        pub type ARAE_R = crate::BitReader;
        #[doc = "Field `ARAE` writer - Access to Reserved Address Enable"]
        pub type ARAE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"]
            #[inline(always)]
            pub fn rf0ne(&self) -> RF0NE_R {
                RF0NE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"]
            #[inline(always)]
            pub fn rf0we(&self) -> RF0WE_R {
                RF0WE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"]
            #[inline(always)]
            pub fn rf0fe(&self) -> RF0FE_R {
                RF0FE_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"]
            #[inline(always)]
            pub fn rf0le(&self) -> RF0LE_R {
                RF0LE_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"]
            #[inline(always)]
            pub fn rf1ne(&self) -> RF1NE_R {
                RF1NE_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"]
            #[inline(always)]
            pub fn rf1we(&self) -> RF1WE_R {
                RF1WE_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Rx FIFO 1 Full Interrupt Enable"]
            #[inline(always)]
            pub fn rf1fe(&self) -> RF1FE_R {
                RF1FE_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"]
            #[inline(always)]
            pub fn rf1le(&self) -> RF1LE_R {
                RF1LE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - High Priority Message Interrupt Enable"]
            #[inline(always)]
            pub fn hpme(&self) -> HPME_R {
                HPME_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Transmission Completed Interrupt Enable"]
            #[inline(always)]
            pub fn tce(&self) -> TCE_R {
                TCE_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"]
            #[inline(always)]
            pub fn tcfe(&self) -> TCFE_R {
                TCFE_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"]
            #[inline(always)]
            pub fn tfee(&self) -> TFEE_R {
                TFEE_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"]
            #[inline(always)]
            pub fn tefne(&self) -> TEFNE_R {
                TEFNE_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"]
            #[inline(always)]
            pub fn tefwe(&self) -> TEFWE_R {
                TEFWE_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"]
            #[inline(always)]
            pub fn teffe(&self) -> TEFFE_R {
                TEFFE_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - Tx Event FIFO Event Lost Interrupt Enable"]
            #[inline(always)]
            pub fn tefle(&self) -> TEFLE_R {
                TEFLE_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"]
            #[inline(always)]
            pub fn tswe(&self) -> TSWE_R {
                TSWE_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"]
            #[inline(always)]
            pub fn mrafe(&self) -> MRAFE_R {
                MRAFE_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"]
            #[inline(always)]
            pub fn tooe(&self) -> TOOE_R {
                TOOE_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"]
            #[inline(always)]
            pub fn drxe(&self) -> DRXE_R {
                DRXE_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"]
            #[inline(always)]
            pub fn bece(&self) -> BECE_R {
                BECE_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"]
            #[inline(always)]
            pub fn beue(&self) -> BEUE_R {
                BEUE_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"]
            #[inline(always)]
            pub fn eloe(&self) -> ELOE_R {
                ELOE_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - Error Passive Interrupt Enable"]
            #[inline(always)]
            pub fn epe(&self) -> EPE_R {
                EPE_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - Warning Status Interrupt Enable"]
            #[inline(always)]
            pub fn ewe(&self) -> EWE_R {
                EWE_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"]
            #[inline(always)]
            pub fn boe(&self) -> BOE_R {
                BOE_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - Watchdog Interrupt Enable"]
            #[inline(always)]
            pub fn wdie(&self) -> WDIE_R {
                WDIE_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"]
            #[inline(always)]
            pub fn peae(&self) -> PEAE_R {
                PEAE_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - Protocol Error in Data Phase Enable"]
            #[inline(always)]
            pub fn pede(&self) -> PEDE_R {
                PEDE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - Access to Reserved Address Enable"]
            #[inline(always)]
            pub fn arae(&self) -> ARAE_R {
                ARAE_R::new(((self.bits >> 29) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf0ne(&mut self) -> RF0NE_W<IE_SPEC> {
                RF0NE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf0we(&mut self) -> RF0WE_W<IE_SPEC> {
                RF0WE_W::new(self, 1)
            }
            #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf0fe(&mut self) -> RF0FE_W<IE_SPEC> {
                RF0FE_W::new(self, 2)
            }
            #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf0le(&mut self) -> RF0LE_W<IE_SPEC> {
                RF0LE_W::new(self, 3)
            }
            #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf1ne(&mut self) -> RF1NE_W<IE_SPEC> {
                RF1NE_W::new(self, 4)
            }
            #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf1we(&mut self) -> RF1WE_W<IE_SPEC> {
                RF1WE_W::new(self, 5)
            }
            #[doc = "Bit 6 - Rx FIFO 1 Full Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf1fe(&mut self) -> RF1FE_W<IE_SPEC> {
                RF1FE_W::new(self, 6)
            }
            #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn rf1le(&mut self) -> RF1LE_W<IE_SPEC> {
                RF1LE_W::new(self, 7)
            }
            #[doc = "Bit 8 - High Priority Message Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn hpme(&mut self) -> HPME_W<IE_SPEC> {
                HPME_W::new(self, 8)
            }
            #[doc = "Bit 9 - Transmission Completed Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tce(&mut self) -> TCE_W<IE_SPEC> {
                TCE_W::new(self, 9)
            }
            #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tcfe(&mut self) -> TCFE_W<IE_SPEC> {
                TCFE_W::new(self, 10)
            }
            #[doc = "Bit 11 - Tx FIFO Empty Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tfee(&mut self) -> TFEE_W<IE_SPEC> {
                TFEE_W::new(self, 11)
            }
            #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tefne(&mut self) -> TEFNE_W<IE_SPEC> {
                TEFNE_W::new(self, 12)
            }
            #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tefwe(&mut self) -> TEFWE_W<IE_SPEC> {
                TEFWE_W::new(self, 13)
            }
            #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn teffe(&mut self) -> TEFFE_W<IE_SPEC> {
                TEFFE_W::new(self, 14)
            }
            #[doc = "Bit 15 - Tx Event FIFO Event Lost Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tefle(&mut self) -> TEFLE_W<IE_SPEC> {
                TEFLE_W::new(self, 15)
            }
            #[doc = "Bit 16 - Timestamp Wraparound Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tswe(&mut self) -> TSWE_W<IE_SPEC> {
                TSWE_W::new(self, 16)
            }
            #[doc = "Bit 17 - Message RAM Access Failure Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn mrafe(&mut self) -> MRAFE_W<IE_SPEC> {
                MRAFE_W::new(self, 17)
            }
            #[doc = "Bit 18 - Timeout Occurred Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn tooe(&mut self) -> TOOE_W<IE_SPEC> {
                TOOE_W::new(self, 18)
            }
            #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn drxe(&mut self) -> DRXE_W<IE_SPEC> {
                DRXE_W::new(self, 19)
            }
            #[doc = "Bit 20 - Bit Error Corrected Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn bece(&mut self) -> BECE_W<IE_SPEC> {
                BECE_W::new(self, 20)
            }
            #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn beue(&mut self) -> BEUE_W<IE_SPEC> {
                BEUE_W::new(self, 21)
            }
            #[doc = "Bit 22 - Error Logging Overflow Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn eloe(&mut self) -> ELOE_W<IE_SPEC> {
                ELOE_W::new(self, 22)
            }
            #[doc = "Bit 23 - Error Passive Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn epe(&mut self) -> EPE_W<IE_SPEC> {
                EPE_W::new(self, 23)
            }
            #[doc = "Bit 24 - Warning Status Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn ewe(&mut self) -> EWE_W<IE_SPEC> {
                EWE_W::new(self, 24)
            }
            #[doc = "Bit 25 - Bus_Off Status Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn boe(&mut self) -> BOE_W<IE_SPEC> {
                BOE_W::new(self, 25)
            }
            #[doc = "Bit 26 - Watchdog Interrupt Enable"]
            #[inline(always)]
            #[must_use]
            pub fn wdie(&mut self) -> WDIE_W<IE_SPEC> {
                WDIE_W::new(self, 26)
            }
            #[doc = "Bit 27 - Protocol Error in Arbitration Phase Enable"]
            #[inline(always)]
            #[must_use]
            pub fn peae(&mut self) -> PEAE_W<IE_SPEC> {
                PEAE_W::new(self, 27)
            }
            #[doc = "Bit 28 - Protocol Error in Data Phase Enable"]
            #[inline(always)]
            #[must_use]
            pub fn pede(&mut self) -> PEDE_W<IE_SPEC> {
                PEDE_W::new(self, 28)
            }
            #[doc = "Bit 29 - Access to Reserved Address Enable"]
            #[inline(always)]
            #[must_use]
            pub fn arae(&mut self) -> ARAE_W<IE_SPEC> {
                ARAE_W::new(self, 29)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ie::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IE_SPEC;
        impl crate::RegisterSpec for IE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ie::R`](R) reader structure"]
        impl crate::Readable for IE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ie::W`](W) writer structure"]
        impl crate::Writable for IE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IE to value 0"]
        impl crate::Resettable for IE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ILS (rw) register accessor: interrupt line select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ils::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ils::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ils`]
module"]
    pub type ILS = crate::Reg<ils::ILS_SPEC>;
    #[doc = "interrupt line select"]
    pub mod ils {
        #[doc = "Register `ILS` reader"]
        pub type R = crate::R<ILS_SPEC>;
        #[doc = "Register `ILS` writer"]
        pub type W = crate::W<ILS_SPEC>;
        #[doc = "Field `RF0NL` reader - Rx FIFO 0 New Message Interrupt Line"]
        pub type RF0NL_R = crate::BitReader;
        #[doc = "Field `RF0NL` writer - Rx FIFO 0 New Message Interrupt Line"]
        pub type RF0NL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0WL` reader - Rx FIFO 0 Watermark Reached Interrupt Line"]
        pub type RF0WL_R = crate::BitReader;
        #[doc = "Field `RF0WL` writer - Rx FIFO 0 Watermark Reached Interrupt Line"]
        pub type RF0WL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0FL` reader - Rx FIFO 0 Full Interrupt Line"]
        pub type RF0FL_R = crate::BitReader;
        #[doc = "Field `RF0FL` writer - Rx FIFO 0 Full Interrupt Line"]
        pub type RF0FL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF0LL` reader - Rx FIFO 0 Message Lost Interrupt Line"]
        pub type RF0LL_R = crate::BitReader;
        #[doc = "Field `RF0LL` writer - Rx FIFO 0 Message Lost Interrupt Line"]
        pub type RF0LL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1NL` reader - Rx FIFO 1 New Message Interrupt Line"]
        pub type RF1NL_R = crate::BitReader;
        #[doc = "Field `RF1NL` writer - Rx FIFO 1 New Message Interrupt Line"]
        pub type RF1NL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1WL` reader - Rx FIFO 1 Watermark Reached Interrupt Line"]
        pub type RF1WL_R = crate::BitReader;
        #[doc = "Field `RF1WL` writer - Rx FIFO 1 Watermark Reached Interrupt Line"]
        pub type RF1WL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1FL` reader - Rx FIFO 1 Full Interrupt Line"]
        pub type RF1FL_R = crate::BitReader;
        #[doc = "Field `RF1FL` writer - Rx FIFO 1 Full Interrupt Line"]
        pub type RF1FL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RF1LL` reader - Rx FIFO 1 Message Lost Interrupt Line"]
        pub type RF1LL_R = crate::BitReader;
        #[doc = "Field `RF1LL` writer - Rx FIFO 1 Message Lost Interrupt Line"]
        pub type RF1LL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HPML` reader - High Priority Message Interrupt Line"]
        pub type HPML_R = crate::BitReader;
        #[doc = "Field `HPML` writer - High Priority Message Interrupt Line"]
        pub type HPML_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TCL` reader - Transmission Completed Interrupt Line"]
        pub type TCL_R = crate::BitReader;
        #[doc = "Field `TCL` writer - Transmission Completed Interrupt Line"]
        pub type TCL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TCFL` reader - Transmission Cancellation Finished Interrupt Line"]
        pub type TCFL_R = crate::BitReader;
        #[doc = "Field `TCFL` writer - Transmission Cancellation Finished Interrupt Line"]
        pub type TCFL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TFEL` reader - Tx FIFO Empty Interrupt Line"]
        pub type TFEL_R = crate::BitReader;
        #[doc = "Field `TFEL` writer - Tx FIFO Empty Interrupt Line"]
        pub type TFEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFNL` reader - Tx Event FIFO New Entry Interrupt Line"]
        pub type TEFNL_R = crate::BitReader;
        #[doc = "Field `TEFNL` writer - Tx Event FIFO New Entry Interrupt Line"]
        pub type TEFNL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFWL` reader - Tx Event FIFO Watermark Reached Interrupt Line"]
        pub type TEFWL_R = crate::BitReader;
        #[doc = "Field `TEFWL` writer - Tx Event FIFO Watermark Reached Interrupt Line"]
        pub type TEFWL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFFL` reader - Tx Event FIFO Full Interrupt Line"]
        pub type TEFFL_R = crate::BitReader;
        #[doc = "Field `TEFFL` writer - Tx Event FIFO Full Interrupt Line"]
        pub type TEFFL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TEFLL` reader - Tx Event FIFO Event Lost Interrupt Line"]
        pub type TEFLL_R = crate::BitReader;
        #[doc = "Field `TEFLL` writer - Tx Event FIFO Event Lost Interrupt Line"]
        pub type TEFLL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TSWL` reader - Timestamp Wraparound Interrupt Line"]
        pub type TSWL_R = crate::BitReader;
        #[doc = "Field `TSWL` writer - Timestamp Wraparound Interrupt Line"]
        pub type TSWL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MRAFL` reader - Message RAM Access Failure Interrupt Line"]
        pub type MRAFL_R = crate::BitReader;
        #[doc = "Field `MRAFL` writer - Message RAM Access Failure Interrupt Line"]
        pub type MRAFL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TOOL` reader - Timeout Occurred Interrupt Line"]
        pub type TOOL_R = crate::BitReader;
        #[doc = "Field `TOOL` writer - Timeout Occurred Interrupt Line"]
        pub type TOOL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DRXL` reader - Message stored to Dedicated Rx Buffer Interrupt Line"]
        pub type DRXL_R = crate::BitReader;
        #[doc = "Field `DRXL` writer - Message stored to Dedicated Rx Buffer Interrupt Line"]
        pub type DRXL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BECL` reader - Bit Error Corrected Interrupt Line"]
        pub type BECL_R = crate::BitReader;
        #[doc = "Field `BECL` writer - Bit Error Corrected Interrupt Line"]
        pub type BECL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BEUL` reader - Bit Error Uncorrected Interrupt Line"]
        pub type BEUL_R = crate::BitReader;
        #[doc = "Field `BEUL` writer - Bit Error Uncorrected Interrupt Line"]
        pub type BEUL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ELOL` reader - Error Logging Overflow Interrupt Line"]
        pub type ELOL_R = crate::BitReader;
        #[doc = "Field `ELOL` writer - Error Logging Overflow Interrupt Line"]
        pub type ELOL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EPL` reader - Error Passive Interrupt Line"]
        pub type EPL_R = crate::BitReader;
        #[doc = "Field `EPL` writer - Error Passive Interrupt Line"]
        pub type EPL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EWL` reader - Warning Status Interrupt Line"]
        pub type EWL_R = crate::BitReader;
        #[doc = "Field `EWL` writer - Warning Status Interrupt Line"]
        pub type EWL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BOL` reader - Bus_Off Status Interrupt Line"]
        pub type BOL_R = crate::BitReader;
        #[doc = "Field `BOL` writer - Bus_Off Status Interrupt Line"]
        pub type BOL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDIL` reader - Watchdog Interrupt Line"]
        pub type WDIL_R = crate::BitReader;
        #[doc = "Field `WDIL` writer - Watchdog Interrupt Line"]
        pub type WDIL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PEAL` reader - Protocol Error in Arbitration Phase Line"]
        pub type PEAL_R = crate::BitReader;
        #[doc = "Field `PEAL` writer - Protocol Error in Arbitration Phase Line"]
        pub type PEAL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PEDL` reader - Protocol Error in Data Phase Line"]
        pub type PEDL_R = crate::BitReader;
        #[doc = "Field `PEDL` writer - Protocol Error in Data Phase Line"]
        pub type PEDL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ARAL` reader - Access to Reserved Address Line"]
        pub type ARAL_R = crate::BitReader;
        #[doc = "Field `ARAL` writer - Access to Reserved Address Line"]
        pub type ARAL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"]
            #[inline(always)]
            pub fn rf0nl(&self) -> RF0NL_R {
                RF0NL_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"]
            #[inline(always)]
            pub fn rf0wl(&self) -> RF0WL_R {
                RF0WL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"]
            #[inline(always)]
            pub fn rf0fl(&self) -> RF0FL_R {
                RF0FL_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"]
            #[inline(always)]
            pub fn rf0ll(&self) -> RF0LL_R {
                RF0LL_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"]
            #[inline(always)]
            pub fn rf1nl(&self) -> RF1NL_R {
                RF1NL_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"]
            #[inline(always)]
            pub fn rf1wl(&self) -> RF1WL_R {
                RF1WL_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Rx FIFO 1 Full Interrupt Line"]
            #[inline(always)]
            pub fn rf1fl(&self) -> RF1FL_R {
                RF1FL_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"]
            #[inline(always)]
            pub fn rf1ll(&self) -> RF1LL_R {
                RF1LL_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - High Priority Message Interrupt Line"]
            #[inline(always)]
            pub fn hpml(&self) -> HPML_R {
                HPML_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Transmission Completed Interrupt Line"]
            #[inline(always)]
            pub fn tcl(&self) -> TCL_R {
                TCL_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"]
            #[inline(always)]
            pub fn tcfl(&self) -> TCFL_R {
                TCFL_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"]
            #[inline(always)]
            pub fn tfel(&self) -> TFEL_R {
                TFEL_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"]
            #[inline(always)]
            pub fn tefnl(&self) -> TEFNL_R {
                TEFNL_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"]
            #[inline(always)]
            pub fn tefwl(&self) -> TEFWL_R {
                TEFWL_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"]
            #[inline(always)]
            pub fn teffl(&self) -> TEFFL_R {
                TEFFL_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - Tx Event FIFO Event Lost Interrupt Line"]
            #[inline(always)]
            pub fn tefll(&self) -> TEFLL_R {
                TEFLL_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"]
            #[inline(always)]
            pub fn tswl(&self) -> TSWL_R {
                TSWL_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"]
            #[inline(always)]
            pub fn mrafl(&self) -> MRAFL_R {
                MRAFL_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - Timeout Occurred Interrupt Line"]
            #[inline(always)]
            pub fn tool(&self) -> TOOL_R {
                TOOL_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"]
            #[inline(always)]
            pub fn drxl(&self) -> DRXL_R {
                DRXL_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"]
            #[inline(always)]
            pub fn becl(&self) -> BECL_R {
                BECL_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"]
            #[inline(always)]
            pub fn beul(&self) -> BEUL_R {
                BEUL_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"]
            #[inline(always)]
            pub fn elol(&self) -> ELOL_R {
                ELOL_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - Error Passive Interrupt Line"]
            #[inline(always)]
            pub fn epl(&self) -> EPL_R {
                EPL_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - Warning Status Interrupt Line"]
            #[inline(always)]
            pub fn ewl(&self) -> EWL_R {
                EWL_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Bus_Off Status Interrupt Line"]
            #[inline(always)]
            pub fn bol(&self) -> BOL_R {
                BOL_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - Watchdog Interrupt Line"]
            #[inline(always)]
            pub fn wdil(&self) -> WDIL_R {
                WDIL_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"]
            #[inline(always)]
            pub fn peal(&self) -> PEAL_R {
                PEAL_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - Protocol Error in Data Phase Line"]
            #[inline(always)]
            pub fn pedl(&self) -> PEDL_R {
                PEDL_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - Access to Reserved Address Line"]
            #[inline(always)]
            pub fn aral(&self) -> ARAL_R {
                ARAL_R::new(((self.bits >> 29) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Rx FIFO 0 New Message Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf0nl(&mut self) -> RF0NL_W<ILS_SPEC> {
                RF0NL_W::new(self, 0)
            }
            #[doc = "Bit 1 - Rx FIFO 0 Watermark Reached Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf0wl(&mut self) -> RF0WL_W<ILS_SPEC> {
                RF0WL_W::new(self, 1)
            }
            #[doc = "Bit 2 - Rx FIFO 0 Full Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf0fl(&mut self) -> RF0FL_W<ILS_SPEC> {
                RF0FL_W::new(self, 2)
            }
            #[doc = "Bit 3 - Rx FIFO 0 Message Lost Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf0ll(&mut self) -> RF0LL_W<ILS_SPEC> {
                RF0LL_W::new(self, 3)
            }
            #[doc = "Bit 4 - Rx FIFO 1 New Message Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf1nl(&mut self) -> RF1NL_W<ILS_SPEC> {
                RF1NL_W::new(self, 4)
            }
            #[doc = "Bit 5 - Rx FIFO 1 Watermark Reached Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf1wl(&mut self) -> RF1WL_W<ILS_SPEC> {
                RF1WL_W::new(self, 5)
            }
            #[doc = "Bit 6 - Rx FIFO 1 Full Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf1fl(&mut self) -> RF1FL_W<ILS_SPEC> {
                RF1FL_W::new(self, 6)
            }
            #[doc = "Bit 7 - Rx FIFO 1 Message Lost Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn rf1ll(&mut self) -> RF1LL_W<ILS_SPEC> {
                RF1LL_W::new(self, 7)
            }
            #[doc = "Bit 8 - High Priority Message Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn hpml(&mut self) -> HPML_W<ILS_SPEC> {
                HPML_W::new(self, 8)
            }
            #[doc = "Bit 9 - Transmission Completed Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tcl(&mut self) -> TCL_W<ILS_SPEC> {
                TCL_W::new(self, 9)
            }
            #[doc = "Bit 10 - Transmission Cancellation Finished Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tcfl(&mut self) -> TCFL_W<ILS_SPEC> {
                TCFL_W::new(self, 10)
            }
            #[doc = "Bit 11 - Tx FIFO Empty Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tfel(&mut self) -> TFEL_W<ILS_SPEC> {
                TFEL_W::new(self, 11)
            }
            #[doc = "Bit 12 - Tx Event FIFO New Entry Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tefnl(&mut self) -> TEFNL_W<ILS_SPEC> {
                TEFNL_W::new(self, 12)
            }
            #[doc = "Bit 13 - Tx Event FIFO Watermark Reached Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tefwl(&mut self) -> TEFWL_W<ILS_SPEC> {
                TEFWL_W::new(self, 13)
            }
            #[doc = "Bit 14 - Tx Event FIFO Full Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn teffl(&mut self) -> TEFFL_W<ILS_SPEC> {
                TEFFL_W::new(self, 14)
            }
            #[doc = "Bit 15 - Tx Event FIFO Event Lost Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tefll(&mut self) -> TEFLL_W<ILS_SPEC> {
                TEFLL_W::new(self, 15)
            }
            #[doc = "Bit 16 - Timestamp Wraparound Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tswl(&mut self) -> TSWL_W<ILS_SPEC> {
                TSWL_W::new(self, 16)
            }
            #[doc = "Bit 17 - Message RAM Access Failure Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn mrafl(&mut self) -> MRAFL_W<ILS_SPEC> {
                MRAFL_W::new(self, 17)
            }
            #[doc = "Bit 18 - Timeout Occurred Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn tool(&mut self) -> TOOL_W<ILS_SPEC> {
                TOOL_W::new(self, 18)
            }
            #[doc = "Bit 19 - Message stored to Dedicated Rx Buffer Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn drxl(&mut self) -> DRXL_W<ILS_SPEC> {
                DRXL_W::new(self, 19)
            }
            #[doc = "Bit 20 - Bit Error Corrected Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn becl(&mut self) -> BECL_W<ILS_SPEC> {
                BECL_W::new(self, 20)
            }
            #[doc = "Bit 21 - Bit Error Uncorrected Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn beul(&mut self) -> BEUL_W<ILS_SPEC> {
                BEUL_W::new(self, 21)
            }
            #[doc = "Bit 22 - Error Logging Overflow Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn elol(&mut self) -> ELOL_W<ILS_SPEC> {
                ELOL_W::new(self, 22)
            }
            #[doc = "Bit 23 - Error Passive Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn epl(&mut self) -> EPL_W<ILS_SPEC> {
                EPL_W::new(self, 23)
            }
            #[doc = "Bit 24 - Warning Status Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn ewl(&mut self) -> EWL_W<ILS_SPEC> {
                EWL_W::new(self, 24)
            }
            #[doc = "Bit 25 - Bus_Off Status Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn bol(&mut self) -> BOL_W<ILS_SPEC> {
                BOL_W::new(self, 25)
            }
            #[doc = "Bit 26 - Watchdog Interrupt Line"]
            #[inline(always)]
            #[must_use]
            pub fn wdil(&mut self) -> WDIL_W<ILS_SPEC> {
                WDIL_W::new(self, 26)
            }
            #[doc = "Bit 27 - Protocol Error in Arbitration Phase Line"]
            #[inline(always)]
            #[must_use]
            pub fn peal(&mut self) -> PEAL_W<ILS_SPEC> {
                PEAL_W::new(self, 27)
            }
            #[doc = "Bit 28 - Protocol Error in Data Phase Line"]
            #[inline(always)]
            #[must_use]
            pub fn pedl(&mut self) -> PEDL_W<ILS_SPEC> {
                PEDL_W::new(self, 28)
            }
            #[doc = "Bit 29 - Access to Reserved Address Line"]
            #[inline(always)]
            #[must_use]
            pub fn aral(&mut self) -> ARAL_W<ILS_SPEC> {
                ARAL_W::new(self, 29)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "interrupt line select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ils::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ils::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ILS_SPEC;
        impl crate::RegisterSpec for ILS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ils::R`](R) reader structure"]
        impl crate::Readable for ILS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ils::W`](W) writer structure"]
        impl crate::Writable for ILS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ILS to value 0"]
        impl crate::Resettable for ILS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ILE (rw) register accessor: interrupt line enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ile::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ile::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ile`]
module"]
    pub type ILE = crate::Reg<ile::ILE_SPEC>;
    #[doc = "interrupt line enable"]
    pub mod ile {
        #[doc = "Register `ILE` reader"]
        pub type R = crate::R<ILE_SPEC>;
        #[doc = "Register `ILE` writer"]
        pub type W = crate::W<ILE_SPEC>;
        #[doc = "Field `EINT0` reader - Enable Interrupt Line 0 0= Interrupt line m_can_int0 disabled 1= Interrupt line m_can_int0 enabled"]
        pub type EINT0_R = crate::BitReader;
        #[doc = "Field `EINT0` writer - Enable Interrupt Line 0 0= Interrupt line m_can_int0 disabled 1= Interrupt line m_can_int0 enabled"]
        pub type EINT0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EINT1` reader - Enable Interrupt Line 1 0= Interrupt line m_can_int1 disabled 1= Interrupt line m_can_int1 enabled"]
        pub type EINT1_R = crate::BitReader;
        #[doc = "Field `EINT1` writer - Enable Interrupt Line 1 0= Interrupt line m_can_int1 disabled 1= Interrupt line m_can_int1 enabled"]
        pub type EINT1_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Enable Interrupt Line 0 0= Interrupt line m_can_int0 disabled 1= Interrupt line m_can_int0 enabled"]
            #[inline(always)]
            pub fn eint0(&self) -> EINT0_R {
                EINT0_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Enable Interrupt Line 1 0= Interrupt line m_can_int1 disabled 1= Interrupt line m_can_int1 enabled"]
            #[inline(always)]
            pub fn eint1(&self) -> EINT1_R {
                EINT1_R::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable Interrupt Line 0 0= Interrupt line m_can_int0 disabled 1= Interrupt line m_can_int0 enabled"]
            #[inline(always)]
            #[must_use]
            pub fn eint0(&mut self) -> EINT0_W<ILE_SPEC> {
                EINT0_W::new(self, 0)
            }
            #[doc = "Bit 1 - Enable Interrupt Line 1 0= Interrupt line m_can_int1 disabled 1= Interrupt line m_can_int1 enabled"]
            #[inline(always)]
            #[must_use]
            pub fn eint1(&mut self) -> EINT1_W<ILE_SPEC> {
                EINT1_W::new(self, 1)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "interrupt line enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ile::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ile::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ILE_SPEC;
        impl crate::RegisterSpec for ILE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ile::R`](R) reader structure"]
        impl crate::Readable for ILE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ile::W`](W) writer structure"]
        impl crate::Writable for ILE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ILE to value 0"]
        impl crate::Resettable for ILE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GFC (rw) register accessor: global filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gfc`]
module"]
    pub type GFC = crate::Reg<gfc::GFC_SPEC>;
    #[doc = "global filter configuration"]
    pub mod gfc {
        #[doc = "Register `GFC` reader"]
        pub type R = crate::R<GFC_SPEC>;
        #[doc = "Register `GFC` writer"]
        pub type W = crate::W<GFC_SPEC>;
        #[doc = "Field `RRFE` reader - Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs"]
        pub type RRFE_R = crate::BitReader;
        #[doc = "Field `RRFE` writer - Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs"]
        pub type RRFE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RRFS` reader - Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs"]
        pub type RRFS_R = crate::BitReader;
        #[doc = "Field `RRFS` writer - Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs"]
        pub type RRFS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ANFE` reader - Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
        pub type ANFE_R = crate::FieldReader;
        #[doc = "Field `ANFE` writer - Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
        pub type ANFE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ANFS` reader - Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
        pub type ANFS_R = crate::FieldReader;
        #[doc = "Field `ANFS` writer - Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
        pub type ANFS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bit 0 - Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs"]
            #[inline(always)]
            pub fn rrfe(&self) -> RRFE_R {
                RRFE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs"]
            #[inline(always)]
            pub fn rrfs(&self) -> RRFS_R {
                RRFS_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 2:3 - Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
            #[inline(always)]
            pub fn anfe(&self) -> ANFE_R {
                ANFE_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bits 4:5 - Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
            #[inline(always)]
            pub fn anfs(&self) -> ANFS_R {
                ANFS_R::new(((self.bits >> 4) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - Reject Remote Frames Extended 0= Filter remote frames with 29-bit extended IDs 1= Reject all remote frames with 29-bit extended IDs"]
            #[inline(always)]
            #[must_use]
            pub fn rrfe(&mut self) -> RRFE_W<GFC_SPEC> {
                RRFE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Reject Remote Frames Standard 0= Filter remote frames with 11-bit standard IDs 1= Reject all remote frames with 11-bit standard IDs"]
            #[inline(always)]
            #[must_use]
            pub fn rrfs(&mut self) -> RRFS_W<GFC_SPEC> {
                RRFS_W::new(self, 1)
            }
            #[doc = "Bits 2:3 - Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
            #[inline(always)]
            #[must_use]
            pub fn anfe(&mut self) -> ANFE_W<GFC_SPEC> {
                ANFE_W::new(self, 2)
            }
            #[doc = "Bits 4:5 - Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. 00= Accept in Rx FIFO 0 01= Accept in Rx FIFO 1 10= Reject 11= Reject"]
            #[inline(always)]
            #[must_use]
            pub fn anfs(&mut self) -> ANFS_W<GFC_SPEC> {
                ANFS_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "global filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GFC_SPEC;
        impl crate::RegisterSpec for GFC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gfc::R`](R) reader structure"]
        impl crate::Readable for GFC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gfc::W`](W) writer structure"]
        impl crate::Writable for GFC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GFC to value 0"]
        impl crate::Resettable for GFC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SIDFC (rw) register accessor: standard ID filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sidfc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sidfc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sidfc`]
module"]
    pub type SIDFC = crate::Reg<sidfc::SIDFC_SPEC>;
    #[doc = "standard ID filter configuration"]
    pub mod sidfc {
        #[doc = "Register `SIDFC` reader"]
        pub type R = crate::R<SIDFC_SPEC>;
        #[doc = "Register `SIDFC` writer"]
        pub type W = crate::W<SIDFC_SPEC>;
        #[doc = "Field `FLSSA` reader - Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address)"]
        pub type FLSSA_R = crate::FieldReader<u16>;
        #[doc = "Field `FLSSA` writer - Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address)"]
        pub type FLSSA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `LSS` reader - List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements >128= Values greater than 128 are interpreted as 128"]
        pub type LSS_R = crate::FieldReader;
        #[doc = "Field `LSS` writer - List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements >128= Values greater than 128 are interpreted as 128"]
        pub type LSS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 2:15 - Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address)"]
            #[inline(always)]
            pub fn flssa(&self) -> FLSSA_R {
                FLSSA_R::new(((self.bits >> 2) & 0x3fff) as u16)
            }
            #[doc = "Bits 16:23 - List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements >128= Values greater than 128 are interpreted as 128"]
            #[inline(always)]
            pub fn lss(&self) -> LSS_R {
                LSS_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 2:15 - Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address)"]
            #[inline(always)]
            #[must_use]
            pub fn flssa(&mut self) -> FLSSA_W<SIDFC_SPEC> {
                FLSSA_W::new(self, 2)
            }
            #[doc = "Bits 16:23 - List Size Standard 0= No standard Message ID filter 1-128= Number of standard Message ID filter elements >128= Values greater than 128 are interpreted as 128"]
            #[inline(always)]
            #[must_use]
            pub fn lss(&mut self) -> LSS_W<SIDFC_SPEC> {
                LSS_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "standard ID filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sidfc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sidfc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SIDFC_SPEC;
        impl crate::RegisterSpec for SIDFC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sidfc::R`](R) reader structure"]
        impl crate::Readable for SIDFC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sidfc::W`](W) writer structure"]
        impl crate::Writable for SIDFC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SIDFC to value 0"]
        impl crate::Resettable for SIDFC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "XIDFC (rw) register accessor: extended ID filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidfc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidfc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xidfc`]
module"]
    pub type XIDFC = crate::Reg<xidfc::XIDFC_SPEC>;
    #[doc = "extended ID filter configuration"]
    pub mod xidfc {
        #[doc = "Register `XIDFC` reader"]
        pub type R = crate::R<XIDFC_SPEC>;
        #[doc = "Register `XIDFC` writer"]
        pub type W = crate::W<XIDFC_SPEC>;
        #[doc = "Field `FLESA` reader - Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address)."]
        pub type FLESA_R = crate::FieldReader<u16>;
        #[doc = "Field `FLESA` writer - Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address)."]
        pub type FLESA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `LSE` reader - List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements >64= Values greater than 64 are interpreted as 64"]
        pub type LSE_R = crate::FieldReader;
        #[doc = "Field `LSE` writer - List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements >64= Values greater than 64 are interpreted as 64"]
        pub type LSE_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bits 2:15 - Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address)."]
            #[inline(always)]
            pub fn flesa(&self) -> FLESA_R {
                FLESA_R::new(((self.bits >> 2) & 0x3fff) as u16)
            }
            #[doc = "Bits 16:22 - List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements >64= Values greater than 64 are interpreted as 64"]
            #[inline(always)]
            pub fn lse(&self) -> LSE_R {
                LSE_R::new(((self.bits >> 16) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 2:15 - Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address)."]
            #[inline(always)]
            #[must_use]
            pub fn flesa(&mut self) -> FLESA_W<XIDFC_SPEC> {
                FLESA_W::new(self, 2)
            }
            #[doc = "Bits 16:22 - List Size Extended 0= No extended Message ID filter 1-64= Number of extended Message ID filter elements >64= Values greater than 64 are interpreted as 64"]
            #[inline(always)]
            #[must_use]
            pub fn lse(&mut self) -> LSE_W<XIDFC_SPEC> {
                LSE_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "extended ID filter configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidfc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidfc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct XIDFC_SPEC;
        impl crate::RegisterSpec for XIDFC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`xidfc::R`](R) reader structure"]
        impl crate::Readable for XIDFC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`xidfc::W`](W) writer structure"]
        impl crate::Writable for XIDFC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets XIDFC to value 0"]
        impl crate::Resettable for XIDFC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "XIDAM (rw) register accessor: extended id and mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidam::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xidam`]
module"]
    pub type XIDAM = crate::Reg<xidam::XIDAM_SPEC>;
    #[doc = "extended id and mask"]
    pub mod xidam {
        #[doc = "Register `XIDAM` reader"]
        pub type R = crate::R<XIDAM_SPEC>;
        #[doc = "Register `XIDAM` writer"]
        pub type W = crate::W<XIDAM_SPEC>;
        #[doc = "Field `EIDM` reader - Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."]
        pub type EIDM_R = crate::FieldReader<u32>;
        #[doc = "Field `EIDM` writer - Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."]
        pub type EIDM_W<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>;
        impl R {
            #[doc = "Bits 0:28 - Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."]
            #[inline(always)]
            pub fn eidm(&self) -> EIDM_R {
                EIDM_R::new(self.bits & 0x1fff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:28 - Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active."]
            #[inline(always)]
            #[must_use]
            pub fn eidm(&mut self) -> EIDM_W<XIDAM_SPEC> {
                EIDM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "extended id and mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xidam::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xidam::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct XIDAM_SPEC;
        impl crate::RegisterSpec for XIDAM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`xidam::R`](R) reader structure"]
        impl crate::Readable for XIDAM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`xidam::W`](W) writer structure"]
        impl crate::Writable for XIDAM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets XIDAM to value 0x1fff_ffff"]
        impl crate::Resettable for XIDAM_SPEC {
            const RESET_VALUE: u32 = 0x1fff_ffff;
        }
    }
    #[doc = "HPMS (rw) register accessor: high priority message status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpms::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpms::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hpms`]
module"]
    pub type HPMS = crate::Reg<hpms::HPMS_SPEC>;
    #[doc = "high priority message status"]
    pub mod hpms {
        #[doc = "Register `HPMS` reader"]
        pub type R = crate::R<HPMS_SPEC>;
        #[doc = "Register `HPMS` writer"]
        pub type W = crate::W<HPMS_SPEC>;
        #[doc = "Field `BIDX` reader - Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI\\[1\\]
= ‘1’."]
        pub type BIDX_R = crate::FieldReader;
        #[doc = "Field `MSI` reader - Message Storage Indicator 00= No FIFO selected 01= FIFO message lost 10= Message stored in FIFO 0 11= Message stored in FIFO 1"]
        pub type MSI_R = crate::FieldReader;
        #[doc = "Field `FIDX` reader - Filter Index Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1."]
        pub type FIDX_R = crate::FieldReader;
        #[doc = "Field `FLST` reader - Filter List Indicates the filter list of the matching filter element. 0= Standard Filter List 1= Extended Filter List"]
        pub type FLST_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:5 - Buffer Index Index of Rx FIFO element to which the message was stored. Only valid when MSI\\[1\\]
= ‘1’."]
            #[inline(always)]
            pub fn bidx(&self) -> BIDX_R {
                BIDX_R::new((self.bits & 0x3f) as u8)
            }
            #[doc = "Bits 6:7 - Message Storage Indicator 00= No FIFO selected 01= FIFO message lost 10= Message stored in FIFO 0 11= Message stored in FIFO 1"]
            #[inline(always)]
            pub fn msi(&self) -> MSI_R {
                MSI_R::new(((self.bits >> 6) & 3) as u8)
            }
            #[doc = "Bits 8:14 - Filter Index Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1."]
            #[inline(always)]
            pub fn fidx(&self) -> FIDX_R {
                FIDX_R::new(((self.bits >> 8) & 0x7f) as u8)
            }
            #[doc = "Bit 15 - Filter List Indicates the filter list of the matching filter element. 0= Standard Filter List 1= Extended Filter List"]
            #[inline(always)]
            pub fn flst(&self) -> FLST_R {
                FLST_R::new(((self.bits >> 15) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "high priority message status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hpms::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hpms::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HPMS_SPEC;
        impl crate::RegisterSpec for HPMS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`hpms::R`](R) reader structure"]
        impl crate::Readable for HPMS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`hpms::W`](W) writer structure"]
        impl crate::Writable for HPMS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets HPMS to value 0"]
        impl crate::Resettable for HPMS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "NDAT1 (rw) register accessor: new data1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ndat1`]
module"]
    pub type NDAT1 = crate::Reg<ndat1::NDAT1_SPEC>;
    #[doc = "new data1"]
    pub mod ndat1 {
        #[doc = "Register `NDAT1` reader"]
        pub type R = crate::R<NDAT1_SPEC>;
        #[doc = "Register `NDAT1` writer"]
        pub type W = crate::W<NDAT1_SPEC>;
        #[doc = "Field `ND1` reader - New Data\\[31:0\\]
The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
        pub type ND1_R = crate::FieldReader<u32>;
        #[doc = "Field `ND1` writer - New Data\\[31:0\\]
The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
        pub type ND1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - New Data\\[31:0\\]
The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
            #[inline(always)]
            pub fn nd1(&self) -> ND1_R {
                ND1_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - New Data\\[31:0\\]
The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
            #[inline(always)]
            #[must_use]
            pub fn nd1(&mut self) -> ND1_W<NDAT1_SPEC> {
                ND1_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "new data1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct NDAT1_SPEC;
        impl crate::RegisterSpec for NDAT1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ndat1::R`](R) reader structure"]
        impl crate::Readable for NDAT1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ndat1::W`](W) writer structure"]
        impl crate::Writable for NDAT1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets NDAT1 to value 0"]
        impl crate::Resettable for NDAT1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "NDAT2 (rw) register accessor: new data2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ndat2`]
module"]
    pub type NDAT2 = crate::Reg<ndat2::NDAT2_SPEC>;
    #[doc = "new data2"]
    pub mod ndat2 {
        #[doc = "Register `NDAT2` reader"]
        pub type R = crate::R<NDAT2_SPEC>;
        #[doc = "Register `NDAT2` writer"]
        pub type W = crate::W<NDAT2_SPEC>;
        #[doc = "Field `ND2` reader - New Data\\[63:32\\]
The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
        pub type ND2_R = crate::FieldReader<u32>;
        #[doc = "Field `ND2` writer - New Data\\[63:32\\]
The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
        pub type ND2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - New Data\\[63:32\\]
The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
            #[inline(always)]
            pub fn nd2(&self) -> ND2_R {
                ND2_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - New Data\\[63:32\\]
The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. 0= Rx Buffer not updated 1= Rx Buffer updated from new message"]
            #[inline(always)]
            #[must_use]
            pub fn nd2(&mut self) -> ND2_W<NDAT2_SPEC> {
                ND2_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "new data2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ndat2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ndat2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct NDAT2_SPEC;
        impl crate::RegisterSpec for NDAT2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ndat2::R`](R) reader structure"]
        impl crate::Readable for NDAT2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ndat2::W`](W) writer structure"]
        impl crate::Writable for NDAT2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets NDAT2 to value 0"]
        impl crate::Resettable for NDAT2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXF0C (rw) register accessor: rx fifo 0 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0c::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf0c`]
module"]
    pub type RXF0C = crate::Reg<rxf0c::RXF0C_SPEC>;
    #[doc = "rx fifo 0 configuration"]
    pub mod rxf0c {
        #[doc = "Register `RXF0C` reader"]
        pub type R = crate::R<RXF0C_SPEC>;
        #[doc = "Register `RXF0C` writer"]
        pub type W = crate::W<RXF0C_SPEC>;
        #[doc = "Field `F0SA` reader - Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address)"]
        pub type F0SA_R = crate::FieldReader<u16>;
        #[doc = "Field `F0SA` writer - Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address)"]
        pub type F0SA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `F0S` reader - Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1"]
        pub type F0S_R = crate::FieldReader;
        #[doc = "Field `F0S` writer - Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1"]
        pub type F0S_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `F0WM` reader - Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64= Watermark interrupt disabled"]
        pub type F0WM_R = crate::FieldReader;
        #[doc = "Field `F0WM` writer - Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64= Watermark interrupt disabled"]
        pub type F0WM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `F0OM` reader - FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode"]
        pub type F0OM_R = crate::BitReader;
        #[doc = "Field `F0OM` writer - FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode"]
        pub type F0OM_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 2:15 - Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address)"]
            #[inline(always)]
            pub fn f0sa(&self) -> F0SA_R {
                F0SA_R::new(((self.bits >> 2) & 0x3fff) as u16)
            }
            #[doc = "Bits 16:22 - Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1"]
            #[inline(always)]
            pub fn f0s(&self) -> F0S_R {
                F0S_R::new(((self.bits >> 16) & 0x7f) as u8)
            }
            #[doc = "Bits 24:30 - Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64= Watermark interrupt disabled"]
            #[inline(always)]
            pub fn f0wm(&self) -> F0WM_R {
                F0WM_R::new(((self.bits >> 24) & 0x7f) as u8)
            }
            #[doc = "Bit 31 - FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode"]
            #[inline(always)]
            pub fn f0om(&self) -> F0OM_R {
                F0OM_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 2:15 - Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address)"]
            #[inline(always)]
            #[must_use]
            pub fn f0sa(&mut self) -> F0SA_W<RXF0C_SPEC> {
                F0SA_W::new(self, 2)
            }
            #[doc = "Bits 16:22 - Rx FIFO 0 Size 0= No Rx FIFO 0 1-64= Number of Rx FIFO 0 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 0 elements are indexed from 0 to F0S-1"]
            #[inline(always)]
            #[must_use]
            pub fn f0s(&mut self) -> F0S_W<RXF0C_SPEC> {
                F0S_W::new(self, 16)
            }
            #[doc = "Bits 24:30 - Rx FIFO 0 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) >64= Watermark interrupt disabled"]
            #[inline(always)]
            #[must_use]
            pub fn f0wm(&mut self) -> F0WM_W<RXF0C_SPEC> {
                F0WM_W::new(self, 24)
            }
            #[doc = "Bit 31 - FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 0 blocking mode 1= FIFO 0 overwrite mode"]
            #[inline(always)]
            #[must_use]
            pub fn f0om(&mut self) -> F0OM_W<RXF0C_SPEC> {
                F0OM_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx fifo 0 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0c::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXF0C_SPEC;
        impl crate::RegisterSpec for RXF0C_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxf0c::R`](R) reader structure"]
        impl crate::Readable for RXF0C_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxf0c::W`](W) writer structure"]
        impl crate::Writable for RXF0C_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXF0C to value 0"]
        impl crate::Resettable for RXF0C_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXF0S (rw) register accessor: rx fifo 0 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0s::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0s::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf0s`]
module"]
    pub type RXF0S = crate::Reg<rxf0s::RXF0S_SPEC>;
    #[doc = "rx fifo 0 status"]
    pub mod rxf0s {
        #[doc = "Register `RXF0S` reader"]
        pub type R = crate::R<RXF0S_SPEC>;
        #[doc = "Register `RXF0S` writer"]
        pub type W = crate::W<RXF0S_SPEC>;
        #[doc = "Field `F0FL` reader - Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64."]
        pub type F0FL_R = crate::FieldReader;
        #[doc = "Field `F0GI` reader - Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63."]
        pub type F0GI_R = crate::FieldReader;
        #[doc = "Field `F0PI` reader - Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63."]
        pub type F0PI_R = crate::FieldReader;
        #[doc = "Field `F0F` reader - Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full"]
        pub type F0F_R = crate::BitReader;
        #[doc = "Field `RF0L` reader - Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag."]
        pub type RF0L_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:6 - Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0, range 0 to 64."]
            #[inline(always)]
            pub fn f0fl(&self) -> F0FL_R {
                F0FL_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bits 8:13 - Rx FIFO 0 Get Index Rx FIFO 0 read index pointer, range 0 to 63."]
            #[inline(always)]
            pub fn f0gi(&self) -> F0GI_R {
                F0GI_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
            #[doc = "Bits 16:21 - Rx FIFO 0 Put Index Rx FIFO 0 write index pointer, range 0 to 63."]
            #[inline(always)]
            pub fn f0pi(&self) -> F0PI_R {
                F0PI_R::new(((self.bits >> 16) & 0x3f) as u8)
            }
            #[doc = "Bit 24 - Rx FIFO 0 Full 0= Rx FIFO 0 not full 1= Rx FIFO 0 full"]
            #[inline(always)]
            pub fn f0f(&self) -> F0F_R {
                F0F_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. 0= No Rx FIFO 0 message lost 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag."]
            #[inline(always)]
            pub fn rf0l(&self) -> RF0L_R {
                RF0L_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx fifo 0 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0s::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0s::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXF0S_SPEC;
        impl crate::RegisterSpec for RXF0S_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxf0s::R`](R) reader structure"]
        impl crate::Readable for RXF0S_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxf0s::W`](W) writer structure"]
        impl crate::Writable for RXF0S_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXF0S to value 0"]
        impl crate::Resettable for RXF0S_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXF0A (rw) register accessor: rx fifo0 acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0a::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf0a`]
module"]
    pub type RXF0A = crate::Reg<rxf0a::RXF0A_SPEC>;
    #[doc = "rx fifo0 acknowledge"]
    pub mod rxf0a {
        #[doc = "Register `RXF0A` reader"]
        pub type R = crate::R<RXF0A_SPEC>;
        #[doc = "Register `RXF0A` writer"]
        pub type W = crate::W<RXF0A_SPEC>;
        #[doc = "Field `F0AI` reader - Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL."]
        pub type F0AI_R = crate::FieldReader;
        #[doc = "Field `F0AI` writer - Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL."]
        pub type F0AI_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL."]
            #[inline(always)]
            pub fn f0ai(&self) -> F0AI_R {
                F0AI_R::new((self.bits & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:5 - Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL."]
            #[inline(always)]
            #[must_use]
            pub fn f0ai(&mut self) -> F0AI_W<RXF0A_SPEC> {
                F0AI_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx fifo0 acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf0a::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf0a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXF0A_SPEC;
        impl crate::RegisterSpec for RXF0A_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxf0a::R`](R) reader structure"]
        impl crate::Readable for RXF0A_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxf0a::W`](W) writer structure"]
        impl crate::Writable for RXF0A_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXF0A to value 0"]
        impl crate::Resettable for RXF0A_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXBC (rw) register accessor: rx buffer configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxbc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxbc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxbc`]
module"]
    pub type RXBC = crate::Reg<rxbc::RXBC_SPEC>;
    #[doc = "rx buffer configuration"]
    pub mod rxbc {
        #[doc = "Register `RXBC` reader"]
        pub type R = crate::R<RXBC_SPEC>;
        #[doc = "Register `RXBC` writer"]
        pub type W = crate::W<RXBC_SPEC>;
        #[doc = "Field `RBSA` reader - Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C."]
        pub type RBSA_R = crate::FieldReader<u16>;
        #[doc = "Field `RBSA` writer - Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C."]
        pub type RBSA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        impl R {
            #[doc = "Bits 2:15 - Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C."]
            #[inline(always)]
            pub fn rbsa(&self) -> RBSA_R {
                RBSA_R::new(((self.bits >> 2) & 0x3fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 2:15 - Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C."]
            #[inline(always)]
            #[must_use]
            pub fn rbsa(&mut self) -> RBSA_W<RXBC_SPEC> {
                RBSA_W::new(self, 2)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx buffer configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxbc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxbc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXBC_SPEC;
        impl crate::RegisterSpec for RXBC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxbc::R`](R) reader structure"]
        impl crate::Readable for RXBC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxbc::W`](W) writer structure"]
        impl crate::Writable for RXBC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXBC to value 0"]
        impl crate::Resettable for RXBC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXF1C (rw) register accessor: rx fifo1 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1c::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1c::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf1c`]
module"]
    pub type RXF1C = crate::Reg<rxf1c::RXF1C_SPEC>;
    #[doc = "rx fifo1 configuration"]
    pub mod rxf1c {
        #[doc = "Register `RXF1C` reader"]
        pub type R = crate::R<RXF1C_SPEC>;
        #[doc = "Register `RXF1C` writer"]
        pub type W = crate::W<RXF1C_SPEC>;
        #[doc = "Field `F1SA` reader - Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address)"]
        pub type F1SA_R = crate::FieldReader<u16>;
        #[doc = "Field `F1SA` writer - Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address)"]
        pub type F1SA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `F1S` reader - Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1"]
        pub type F1S_R = crate::FieldReader;
        #[doc = "Field `F1S` writer - Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1"]
        pub type F1S_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `F1WM` reader - Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64= Watermark interrupt disabled"]
        pub type F1WM_R = crate::FieldReader;
        #[doc = "Field `F1WM` writer - Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64= Watermark interrupt disabled"]
        pub type F1WM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `F1OM` reader - FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode"]
        pub type F1OM_R = crate::BitReader;
        #[doc = "Field `F1OM` writer - FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode"]
        pub type F1OM_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 2:15 - Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address)"]
            #[inline(always)]
            pub fn f1sa(&self) -> F1SA_R {
                F1SA_R::new(((self.bits >> 2) & 0x3fff) as u16)
            }
            #[doc = "Bits 16:22 - Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1"]
            #[inline(always)]
            pub fn f1s(&self) -> F1S_R {
                F1S_R::new(((self.bits >> 16) & 0x7f) as u8)
            }
            #[doc = "Bits 24:30 - Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64= Watermark interrupt disabled"]
            #[inline(always)]
            pub fn f1wm(&self) -> F1WM_R {
                F1WM_R::new(((self.bits >> 24) & 0x7f) as u8)
            }
            #[doc = "Bit 31 - FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode"]
            #[inline(always)]
            pub fn f1om(&self) -> F1OM_R {
                F1OM_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 2:15 - Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address)"]
            #[inline(always)]
            #[must_use]
            pub fn f1sa(&mut self) -> F1SA_W<RXF1C_SPEC> {
                F1SA_W::new(self, 2)
            }
            #[doc = "Bits 16:22 - Rx FIFO 1 Size 0= No Rx FIFO 1 1-64= Number of Rx FIFO 1 elements >64= Values greater than 64 are interpreted as 64 The Rx FIFO 1 elements are indexed from 0 to F1S - 1"]
            #[inline(always)]
            #[must_use]
            pub fn f1s(&mut self) -> F1S_W<RXF1C_SPEC> {
                F1S_W::new(self, 16)
            }
            #[doc = "Bits 24:30 - Rx FIFO 1 Watermark 0= Watermark interrupt disabled 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) >64= Watermark interrupt disabled"]
            #[inline(always)]
            #[must_use]
            pub fn f1wm(&mut self) -> F1WM_W<RXF1C_SPEC> {
                F1WM_W::new(self, 24)
            }
            #[doc = "Bit 31 - FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). 0= FIFO 1 blocking mode 1= FIFO 1 overwrite mode"]
            #[inline(always)]
            #[must_use]
            pub fn f1om(&mut self) -> F1OM_W<RXF1C_SPEC> {
                F1OM_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx fifo1 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1c::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1c::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXF1C_SPEC;
        impl crate::RegisterSpec for RXF1C_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxf1c::R`](R) reader structure"]
        impl crate::Readable for RXF1C_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxf1c::W`](W) writer structure"]
        impl crate::Writable for RXF1C_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXF1C to value 0"]
        impl crate::Resettable for RXF1C_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXF1S (rw) register accessor: rx fifo1 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1s::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1s::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf1s`]
module"]
    pub type RXF1S = crate::Reg<rxf1s::RXF1S_SPEC>;
    #[doc = "rx fifo1 status"]
    pub mod rxf1s {
        #[doc = "Register `RXF1S` reader"]
        pub type R = crate::R<RXF1S_SPEC>;
        #[doc = "Register `RXF1S` writer"]
        pub type W = crate::W<RXF1S_SPEC>;
        #[doc = "Field `F1FL` reader - Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64."]
        pub type F1FL_R = crate::FieldReader;
        #[doc = "Field `F1GI` reader - Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63."]
        pub type F1GI_R = crate::FieldReader;
        #[doc = "Field `F1PI` reader - Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63."]
        pub type F1PI_R = crate::FieldReader;
        #[doc = "Field `F1F` reader - Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full"]
        pub type F1F_R = crate::BitReader;
        #[doc = "Field `RF1L` reader - Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag."]
        pub type RF1L_R = crate::BitReader;
        #[doc = "Field `DMS` reader - Debug Message Status 00= Idle state, wait for reception of debug messages, DMA request is cleared 01= Debug message A received 10= Debug messages A, B received 11= Debug messages A, B, C received, DMA request is set"]
        pub type DMS_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:6 - Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1, range 0 to 64."]
            #[inline(always)]
            pub fn f1fl(&self) -> F1FL_R {
                F1FL_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bits 8:13 - Rx FIFO 1 Get Index Rx FIFO 1 read index pointer, range 0 to 63."]
            #[inline(always)]
            pub fn f1gi(&self) -> F1GI_R {
                F1GI_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
            #[doc = "Bits 16:21 - Rx FIFO 1 Put Index Rx FIFO 1 write index pointer, range 0 to 63."]
            #[inline(always)]
            pub fn f1pi(&self) -> F1PI_R {
                F1PI_R::new(((self.bits >> 16) & 0x3f) as u8)
            }
            #[doc = "Bit 24 - Rx FIFO 1 Full 0= Rx FIFO 1 not full 1= Rx FIFO 1 full"]
            #[inline(always)]
            pub fn f1f(&self) -> F1F_R {
                F1F_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. 0= No Rx FIFO 1 message lost 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag."]
            #[inline(always)]
            pub fn rf1l(&self) -> RF1L_R {
                RF1L_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bits 30:31 - Debug Message Status 00= Idle state, wait for reception of debug messages, DMA request is cleared 01= Debug message A received 10= Debug messages A, B received 11= Debug messages A, B, C received, DMA request is set"]
            #[inline(always)]
            pub fn dms(&self) -> DMS_R {
                DMS_R::new(((self.bits >> 30) & 3) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx fifo1 status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1s::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1s::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXF1S_SPEC;
        impl crate::RegisterSpec for RXF1S_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxf1s::R`](R) reader structure"]
        impl crate::Readable for RXF1S_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxf1s::W`](W) writer structure"]
        impl crate::Writable for RXF1S_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXF1S to value 0"]
        impl crate::Resettable for RXF1S_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXF1A (rw) register accessor: rx fifo 1 acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1a::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxf1a`]
module"]
    pub type RXF1A = crate::Reg<rxf1a::RXF1A_SPEC>;
    #[doc = "rx fifo 1 acknowledge"]
    pub mod rxf1a {
        #[doc = "Register `RXF1A` reader"]
        pub type R = crate::R<RXF1A_SPEC>;
        #[doc = "Register `RXF1A` writer"]
        pub type W = crate::W<RXF1A_SPEC>;
        #[doc = "Field `F1AI` reader - Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL."]
        pub type F1AI_R = crate::FieldReader;
        #[doc = "Field `F1AI` writer - Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL."]
        pub type F1AI_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL."]
            #[inline(always)]
            pub fn f1ai(&self) -> F1AI_R {
                F1AI_R::new((self.bits & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:5 - Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL."]
            #[inline(always)]
            #[must_use]
            pub fn f1ai(&mut self) -> F1AI_W<RXF1A_SPEC> {
                F1AI_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx fifo 1 acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxf1a::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxf1a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXF1A_SPEC;
        impl crate::RegisterSpec for RXF1A_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxf1a::R`](R) reader structure"]
        impl crate::Readable for RXF1A_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxf1a::W`](W) writer structure"]
        impl crate::Writable for RXF1A_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXF1A to value 0"]
        impl crate::Resettable for RXF1A_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RXESC (rw) register accessor: rx buffer/fifo element size configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxesc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxesc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxesc`]
module"]
    pub type RXESC = crate::Reg<rxesc::RXESC_SPEC>;
    #[doc = "rx buffer/fifo element size configuration"]
    pub mod rxesc {
        #[doc = "Register `RXESC` reader"]
        pub type R = crate::R<RXESC_SPEC>;
        #[doc = "Register `RXESC` writer"]
        pub type W = crate::W<RXESC_SPEC>;
        #[doc = "Field `F0DS` reader - Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored."]
        pub type F0DS_R = crate::FieldReader;
        #[doc = "Field `F0DS` writer - Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored."]
        pub type F0DS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `F1DS` reader - Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
        pub type F1DS_R = crate::FieldReader;
        #[doc = "Field `F1DS` writer - Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
        pub type F1DS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `RBDS` reader - Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
        pub type RBDS_R = crate::FieldReader;
        #[doc = "Field `RBDS` writer - Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
        pub type RBDS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored."]
            #[inline(always)]
            pub fn f0ds(&self) -> F0DS_R {
                F0DS_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
            #[inline(always)]
            pub fn f1ds(&self) -> F1DS_R {
                F1DS_R::new(((self.bits >> 4) & 7) as u8)
            }
            #[doc = "Bits 8:10 - Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
            #[inline(always)]
            pub fn rbds(&self) -> RBDS_R {
                RBDS_R::new(((self.bits >> 8) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - Rx FIFO 0 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored."]
            #[inline(always)]
            #[must_use]
            pub fn f0ds(&mut self) -> F0DS_W<RXESC_SPEC> {
                F0DS_W::new(self, 0)
            }
            #[doc = "Bits 4:6 - Rx FIFO 1 Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
            #[inline(always)]
            #[must_use]
            pub fn f1ds(&mut self) -> F1DS_W<RXESC_SPEC> {
                F1DS_W::new(self, 4)
            }
            #[doc = "Bits 8:10 - Rx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field"]
            #[inline(always)]
            #[must_use]
            pub fn rbds(&mut self) -> RBDS_W<RXESC_SPEC> {
                RBDS_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rx buffer/fifo element size configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxesc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxesc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RXESC_SPEC;
        impl crate::RegisterSpec for RXESC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rxesc::R`](R) reader structure"]
        impl crate::Readable for RXESC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rxesc::W`](W) writer structure"]
        impl crate::Writable for RXESC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RXESC to value 0"]
        impl crate::Resettable for RXESC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBC (rw) register accessor: tx buffer configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbc`]
module"]
    pub type TXBC = crate::Reg<txbc::TXBC_SPEC>;
    #[doc = "tx buffer configuration"]
    pub mod txbc {
        #[doc = "Register `TXBC` reader"]
        pub type R = crate::R<TXBC_SPEC>;
        #[doc = "Register `TXBC` writer"]
        pub type W = crate::W<TXBC_SPEC>;
        #[doc = "Field `TBSA` reader - Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers."]
        pub type TBSA_R = crate::FieldReader<u16>;
        #[doc = "Field `TBSA` writer - Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers."]
        pub type TBSA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `NDTB` reader - Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers >32= Values greater than 32 are interpreted as 32"]
        pub type NDTB_R = crate::FieldReader;
        #[doc = "Field `NDTB` writer - Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers >32= Values greater than 32 are interpreted as 32"]
        pub type NDTB_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `TFQS` reader - Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue >32= Values greater than 32 are interpreted as 32"]
        pub type TFQS_R = crate::FieldReader;
        #[doc = "Field `TFQS` writer - Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue >32= Values greater than 32 are interpreted as 32"]
        pub type TFQS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `TFQM` reader - Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation"]
        pub type TFQM_R = crate::BitReader;
        #[doc = "Field `TFQM` writer - Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation"]
        pub type TFQM_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 2:15 - Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers."]
            #[inline(always)]
            pub fn tbsa(&self) -> TBSA_R {
                TBSA_R::new(((self.bits >> 2) & 0x3fff) as u16)
            }
            #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers >32= Values greater than 32 are interpreted as 32"]
            #[inline(always)]
            pub fn ndtb(&self) -> NDTB_R {
                NDTB_R::new(((self.bits >> 16) & 0x3f) as u8)
            }
            #[doc = "Bits 24:29 - Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue >32= Values greater than 32 are interpreted as 32"]
            #[inline(always)]
            pub fn tfqs(&self) -> TFQS_R {
                TFQS_R::new(((self.bits >> 24) & 0x3f) as u8)
            }
            #[doc = "Bit 30 - Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation"]
            #[inline(always)]
            pub fn tfqm(&self) -> TFQM_R {
                TFQM_R::new(((self.bits >> 30) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 2:15 - Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers."]
            #[inline(always)]
            #[must_use]
            pub fn tbsa(&mut self) -> TBSA_W<TXBC_SPEC> {
                TBSA_W::new(self, 2)
            }
            #[doc = "Bits 16:21 - Number of Dedicated Transmit Buffers 0= No Dedicated Tx Buffers 1-32= Number of Dedicated Tx Buffers >32= Values greater than 32 are interpreted as 32"]
            #[inline(always)]
            #[must_use]
            pub fn ndtb(&mut self) -> NDTB_W<TXBC_SPEC> {
                NDTB_W::new(self, 16)
            }
            #[doc = "Bits 24:29 - Transmit FIFO/Queue Size 0= No Tx FIFO/Queue 1-32= Number of Tx Buffers used for Tx FIFO/Queue >32= Values greater than 32 are interpreted as 32"]
            #[inline(always)]
            #[must_use]
            pub fn tfqs(&mut self) -> TFQS_W<TXBC_SPEC> {
                TFQS_W::new(self, 24)
            }
            #[doc = "Bit 30 - Tx FIFO/Queue Mode 0= Tx FIFO operation 1= Tx Queue operation"]
            #[inline(always)]
            #[must_use]
            pub fn tfqm(&mut self) -> TFQM_W<TXBC_SPEC> {
                TFQM_W::new(self, 30)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBC_SPEC;
        impl crate::RegisterSpec for TXBC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbc::R`](R) reader structure"]
        impl crate::Readable for TXBC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbc::W`](W) writer structure"]
        impl crate::Writable for TXBC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBC to value 0"]
        impl crate::Resettable for TXBC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXFQS (rw) register accessor: tx fifo/queue status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfqs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfqs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfqs`]
module"]
    pub type TXFQS = crate::Reg<txfqs::TXFQS_SPEC>;
    #[doc = "tx fifo/queue status"]
    pub mod txfqs {
        #[doc = "Register `TXFQS` reader"]
        pub type R = crate::R<TXFQS_SPEC>;
        #[doc = "Register `TXFQS` writer"]
        pub type W = crate::W<TXFQS_SPEC>;
        #[doc = "Field `TFFL` reader - Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO."]
        pub type TFFL_R = crate::FieldReader;
        #[doc = "Field `TFGI` reader - Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’)."]
        pub type TFGI_R = crate::FieldReader;
        #[doc = "Field `TFQPI` reader - Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31."]
        pub type TFQPI_R = crate::FieldReader;
        #[doc = "Field `TFQF` reader - Tx FIFO/Queue Full 0= Tx FIFO/Queue not full 1= Tx FIFO/Queue full"]
        pub type TFQF_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:5 - Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers. Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO."]
            #[inline(always)]
            pub fn tffl(&self) -> TFFL_R {
                TFFL_R::new((self.bits & 0x3f) as u8)
            }
            #[doc = "Bits 8:12 - Tx FIFO Get Index Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’)."]
            #[inline(always)]
            pub fn tfgi(&self) -> TFGI_R {
                TFGI_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:20 - Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer, range 0 to 31."]
            #[inline(always)]
            pub fn tfqpi(&self) -> TFQPI_R {
                TFQPI_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bit 21 - Tx FIFO/Queue Full 0= Tx FIFO/Queue not full 1= Tx FIFO/Queue full"]
            #[inline(always)]
            pub fn tfqf(&self) -> TFQF_R {
                TFQF_R::new(((self.bits >> 21) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx fifo/queue status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfqs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfqs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXFQS_SPEC;
        impl crate::RegisterSpec for TXFQS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txfqs::R`](R) reader structure"]
        impl crate::Readable for TXFQS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txfqs::W`](W) writer structure"]
        impl crate::Writable for TXFQS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXFQS to value 0"]
        impl crate::Resettable for TXFQS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXESC (rw) register accessor: tx buffer element size configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txesc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txesc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txesc`]
module"]
    pub type TXESC = crate::Reg<txesc::TXESC_SPEC>;
    #[doc = "tx buffer element size configuration"]
    pub mod txesc {
        #[doc = "Register `TXESC` reader"]
        pub type R = crate::R<TXESC_SPEC>;
        #[doc = "Register `TXESC` writer"]
        pub type W = crate::W<TXESC_SPEC>;
        #[doc = "Field `TBDS` reader - Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes)."]
        pub type TBDS_R = crate::FieldReader;
        #[doc = "Field `TBDS` writer - Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes)."]
        pub type TBDS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2 - Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes)."]
            #[inline(always)]
            pub fn tbds(&self) -> TBDS_R {
                TBDS_R::new((self.bits & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - Tx Buffer Data Field Size 000= 8 byte data field 001= 12 byte data field 010= 16 byte data field 011= 20 byte data field 100= 24 byte data field 101= 32 byte data field 110= 48 byte data field 111= 64 byte data field Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes)."]
            #[inline(always)]
            #[must_use]
            pub fn tbds(&mut self) -> TBDS_W<TXESC_SPEC> {
                TBDS_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer element size configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txesc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txesc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXESC_SPEC;
        impl crate::RegisterSpec for TXESC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txesc::R`](R) reader structure"]
        impl crate::Readable for TXESC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txesc::W`](W) writer structure"]
        impl crate::Writable for TXESC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXESC to value 0"]
        impl crate::Resettable for TXESC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBRP (rw) register accessor: tx buffer request pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbrp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbrp`]
module"]
    pub type TXBRP = crate::Reg<txbrp::TXBRP_SPEC>;
    #[doc = "tx buffer request pending"]
    pub mod txbrp {
        #[doc = "Register `TXBRP` reader"]
        pub type R = crate::R<TXBRP_SPEC>;
        #[doc = "Register `TXBRP` writer"]
        pub type W = crate::W<TXBRP_SPEC>;
        #[doc = "Field `TRP` reader - Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF ? after successful transmission together with the corresponding TXBTO bit ? when the transmission has not yet been started at the point of cancellation ? when the transmission has been aborted due to lost arbitration ? when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0= No transmission request pending 1= Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset."]
        pub type TRP_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register TXBCR. TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the highest priority (Tx Buffer with lowest Message ID). A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. After a cancellation has been requested, a finished cancellation is signalled via TXBCF ? after successful transmission together with the corresponding TXBTO bit ? when the transmission has not yet been started at the point of cancellation ? when the transmission has been aborted due to lost arbitration ? when an error occurred during frame transmission In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. 0= No transmission request pending 1= Transmission request pending Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset."]
            #[inline(always)]
            pub fn trp(&self) -> TRP_R {
                TRP_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer request pending\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbrp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbrp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBRP_SPEC;
        impl crate::RegisterSpec for TXBRP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbrp::R`](R) reader structure"]
        impl crate::Readable for TXBRP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbrp::W`](W) writer structure"]
        impl crate::Writable for TXBRP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBRP to value 0"]
        impl crate::Resettable for TXBRP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBAR (rw) register accessor: tx buffer add request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbar`]
module"]
    pub type TXBAR = crate::Reg<txbar::TXBAR_SPEC>;
    #[doc = "tx buffer add request"]
    pub mod txbar {
        #[doc = "Register `TXBAR` reader"]
        pub type R = crate::R<TXBAR_SPEC>;
        #[doc = "Register `TXBAR` writer"]
        pub type W = crate::W<TXBAR_SPEC>;
        #[doc = "Field `AR` reader - Add Request Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored."]
        pub type AR_R = crate::FieldReader<u32>;
        #[doc = "Field `AR` writer - Add Request Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored."]
        pub type AR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Add Request Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored."]
            #[inline(always)]
            pub fn ar(&self) -> AR_R {
                AR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Add Request Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. 0= No transmission request added 1= Transmission requested added Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored."]
            #[inline(always)]
            #[must_use]
            pub fn ar(&mut self) -> AR_W<TXBAR_SPEC> {
                AR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer add request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBAR_SPEC;
        impl crate::RegisterSpec for TXBAR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbar::R`](R) reader structure"]
        impl crate::Readable for TXBAR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbar::W`](W) writer structure"]
        impl crate::Writable for TXBAR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBAR to value 0"]
        impl crate::Resettable for TXBAR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBCR (rw) register accessor: tx buffer cancellation request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcr`]
module"]
    pub type TXBCR = crate::Reg<txbcr::TXBCR_SPEC>;
    #[doc = "tx buffer cancellation request"]
    pub mod txbcr {
        #[doc = "Register `TXBCR` reader"]
        pub type R = crate::R<TXBCR_SPEC>;
        #[doc = "Register `TXBCR` writer"]
        pub type W = crate::W<TXBCR_SPEC>;
        #[doc = "Field `CR` reader - Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending"]
        pub type CR_R = crate::FieldReader<u32>;
        #[doc = "Field `CR` writer - Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending"]
        pub type CR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending"]
            #[inline(always)]
            pub fn cr(&self) -> CR_R {
                CR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Cancellation Request Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. 0= No cancellation pending 1= Cancellation pending"]
            #[inline(always)]
            #[must_use]
            pub fn cr(&mut self) -> CR_W<TXBCR_SPEC> {
                CR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer cancellation request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBCR_SPEC;
        impl crate::RegisterSpec for TXBCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbcr::R`](R) reader structure"]
        impl crate::Readable for TXBCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbcr::W`](W) writer structure"]
        impl crate::Writable for TXBCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBCR to value 0"]
        impl crate::Resettable for TXBCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBTO (rw) register accessor: tx buffer transmission occurred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbto::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbto::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbto`]
module"]
    pub type TXBTO = crate::Reg<txbto::TXBTO_SPEC>;
    #[doc = "tx buffer transmission occurred"]
    pub mod txbto {
        #[doc = "Register `TXBTO` reader"]
        pub type R = crate::R<TXBTO_SPEC>;
        #[doc = "Register `TXBTO` writer"]
        pub type W = crate::W<TXBTO_SPEC>;
        #[doc = "Field `TO` reader - Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0= No transmission occurred 1= Transmission occurred"]
        pub type TO_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0= No transmission occurred 1= Transmission occurred"]
            #[inline(always)]
            pub fn to(&self) -> TO_R {
                TO_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer transmission occurred\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbto::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbto::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBTO_SPEC;
        impl crate::RegisterSpec for TXBTO_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbto::R`](R) reader structure"]
        impl crate::Readable for TXBTO_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbto::W`](W) writer structure"]
        impl crate::Writable for TXBTO_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBTO to value 0"]
        impl crate::Resettable for TXBTO_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBCF (rw) register accessor: tx buffer cancellation finished\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcf`]
module"]
    pub type TXBCF = crate::Reg<txbcf::TXBCF_SPEC>;
    #[doc = "tx buffer cancellation finished"]
    pub mod txbcf {
        #[doc = "Register `TXBCF` reader"]
        pub type R = crate::R<TXBCF_SPEC>;
        #[doc = "Register `TXBCF` writer"]
        pub type W = crate::W<TXBCF_SPEC>;
        #[doc = "Field `CF` reader - Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished"]
        pub type CF_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. 0= No transmit buffer cancellation 1= Transmit buffer cancellation finished"]
            #[inline(always)]
            pub fn cf(&self) -> CF_R {
                CF_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer cancellation finished\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBCF_SPEC;
        impl crate::RegisterSpec for TXBCF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbcf::R`](R) reader structure"]
        impl crate::Readable for TXBCF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbcf::W`](W) writer structure"]
        impl crate::Writable for TXBCF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBCF to value 0"]
        impl crate::Resettable for TXBCF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBTIE (rw) register accessor: tx buffer transmission interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbtie::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbtie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbtie`]
module"]
    pub type TXBTIE = crate::Reg<txbtie::TXBTIE_SPEC>;
    #[doc = "tx buffer transmission interrupt enable"]
    pub mod txbtie {
        #[doc = "Register `TXBTIE` reader"]
        pub type R = crate::R<TXBTIE_SPEC>;
        #[doc = "Register `TXBTIE` writer"]
        pub type W = crate::W<TXBTIE_SPEC>;
        #[doc = "Field `TIE` reader - Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable"]
        pub type TIE_R = crate::FieldReader<u32>;
        #[doc = "Field `TIE` writer - Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable"]
        pub type TIE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable"]
            #[inline(always)]
            pub fn tie(&self) -> TIE_R {
                TIE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit. 0= Transmission interrupt disabled 1= Transmission interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn tie(&mut self) -> TIE_W<TXBTIE_SPEC> {
                TIE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer transmission interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbtie::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbtie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBTIE_SPEC;
        impl crate::RegisterSpec for TXBTIE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbtie::R`](R) reader structure"]
        impl crate::Readable for TXBTIE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbtie::W`](W) writer structure"]
        impl crate::Writable for TXBTIE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBTIE to value 0"]
        impl crate::Resettable for TXBTIE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXBCIE (rw) register accessor: tx buffer cancellation finished interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcie::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcie`]
module"]
    pub type TXBCIE = crate::Reg<txbcie::TXBCIE_SPEC>;
    #[doc = "tx buffer cancellation finished interrupt enable"]
    pub mod txbcie {
        #[doc = "Register `TXBCIE` reader"]
        pub type R = crate::R<TXBCIE_SPEC>;
        #[doc = "Register `TXBCIE` writer"]
        pub type W = crate::W<TXBCIE_SPEC>;
        #[doc = "Field `CFIE` reader - Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled"]
        pub type CFIE_R = crate::FieldReader<u32>;
        #[doc = "Field `CFIE` writer - Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled"]
        pub type CFIE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled"]
            #[inline(always)]
            pub fn cfie(&self) -> CFIE_R {
                CFIE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. 0= Cancellation finished interrupt disabled 1= Cancellation finished interrupt enabled"]
            #[inline(always)]
            #[must_use]
            pub fn cfie(&mut self) -> CFIE_W<TXBCIE_SPEC> {
                CFIE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx buffer cancellation finished interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcie::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbcie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXBCIE_SPEC;
        impl crate::RegisterSpec for TXBCIE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txbcie::R`](R) reader structure"]
        impl crate::Readable for TXBCIE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txbcie::W`](W) writer structure"]
        impl crate::Writable for TXBCIE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXBCIE to value 0"]
        impl crate::Resettable for TXBCIE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXEFC (rw) register accessor: tx event fifo configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txefc`]
module"]
    pub type TXEFC = crate::Reg<txefc::TXEFC_SPEC>;
    #[doc = "tx event fifo configuration"]
    pub mod txefc {
        #[doc = "Register `TXEFC` reader"]
        pub type R = crate::R<TXEFC_SPEC>;
        #[doc = "Register `TXEFC` writer"]
        pub type W = crate::W<TXEFC_SPEC>;
        #[doc = "Field `EFSA` reader - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address)"]
        pub type EFSA_R = crate::FieldReader<u16>;
        #[doc = "Field `EFSA` writer - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address)"]
        pub type EFSA_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `EFS` reader - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements >32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS - 1"]
        pub type EFS_R = crate::FieldReader;
        #[doc = "Field `EFS` writer - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements >32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS - 1"]
        pub type EFS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `EFWM` reader - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32= Watermark interrupt disabled"]
        pub type EFWM_R = crate::FieldReader;
        #[doc = "Field `EFWM` writer - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32= Watermark interrupt disabled"]
        pub type EFWM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 2:15 - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address)"]
            #[inline(always)]
            pub fn efsa(&self) -> EFSA_R {
                EFSA_R::new(((self.bits >> 2) & 0x3fff) as u16)
            }
            #[doc = "Bits 16:21 - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements >32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS - 1"]
            #[inline(always)]
            pub fn efs(&self) -> EFS_R {
                EFS_R::new(((self.bits >> 16) & 0x3f) as u8)
            }
            #[doc = "Bits 24:29 - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32= Watermark interrupt disabled"]
            #[inline(always)]
            pub fn efwm(&self) -> EFWM_R {
                EFWM_R::new(((self.bits >> 24) & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 2:15 - Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address)"]
            #[inline(always)]
            #[must_use]
            pub fn efsa(&mut self) -> EFSA_W<TXEFC_SPEC> {
                EFSA_W::new(self, 2)
            }
            #[doc = "Bits 16:21 - Event FIFO Size 0= Tx Event FIFO disabled 1-32= Number of Tx Event FIFO elements >32= Values greater than 32 are interpreted as 32 The Tx Event FIFO elements are indexed from 0 to EFS - 1"]
            #[inline(always)]
            #[must_use]
            pub fn efs(&mut self) -> EFS_W<TXEFC_SPEC> {
                EFS_W::new(self, 16)
            }
            #[doc = "Bits 24:29 - Event FIFO Watermark 0= Watermark interrupt disabled 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) >32= Watermark interrupt disabled"]
            #[inline(always)]
            #[must_use]
            pub fn efwm(&mut self) -> EFWM_W<TXEFC_SPEC> {
                EFWM_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx event fifo configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXEFC_SPEC;
        impl crate::RegisterSpec for TXEFC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txefc::R`](R) reader structure"]
        impl crate::Readable for TXEFC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txefc::W`](W) writer structure"]
        impl crate::Writable for TXEFC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXEFC to value 0"]
        impl crate::Resettable for TXEFC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXEFS (rw) register accessor: tx event fifo status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txefs`]
module"]
    pub type TXEFS = crate::Reg<txefs::TXEFS_SPEC>;
    #[doc = "tx event fifo status"]
    pub mod txefs {
        #[doc = "Register `TXEFS` reader"]
        pub type R = crate::R<TXEFS_SPEC>;
        #[doc = "Register `TXEFS` writer"]
        pub type W = crate::W<TXEFS_SPEC>;
        #[doc = "Field `EFFL` reader - Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32."]
        pub type EFFL_R = crate::FieldReader;
        #[doc = "Field `EFGI` reader - Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31."]
        pub type EFGI_R = crate::FieldReader;
        #[doc = "Field `EFPI` reader - Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31."]
        pub type EFPI_R = crate::FieldReader;
        #[doc = "Field `EFF` reader - Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full"]
        pub type EFF_R = crate::BitReader;
        #[doc = "Field `TEFL` reader - Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero."]
        pub type TEFL_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:5 - Event FIFO Fill Level Number of elements stored in Tx Event FIFO, range 0 to 32."]
            #[inline(always)]
            pub fn effl(&self) -> EFFL_R {
                EFFL_R::new((self.bits & 0x3f) as u8)
            }
            #[doc = "Bits 8:12 - Event FIFO Get Index Tx Event FIFO read index pointer, range 0 to 31."]
            #[inline(always)]
            pub fn efgi(&self) -> EFGI_R {
                EFGI_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:20 - Event FIFO Put Index Tx Event FIFO write index pointer, range 0 to 31."]
            #[inline(always)]
            pub fn efpi(&self) -> EFPI_R {
                EFPI_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bit 24 - Event FIFO Full 0= Tx Event FIFO not full 1= Tx Event FIFO full"]
            #[inline(always)]
            pub fn eff(&self) -> EFF_R {
                EFF_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0= No Tx Event FIFO element lost 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero."]
            #[inline(always)]
            pub fn tefl(&self) -> TEFL_R {
                TEFL_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx event fifo status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXEFS_SPEC;
        impl crate::RegisterSpec for TXEFS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txefs::R`](R) reader structure"]
        impl crate::Readable for TXEFS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txefs::W`](W) writer structure"]
        impl crate::Writable for TXEFS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXEFS to value 0"]
        impl crate::Resettable for TXEFS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXEFA (rw) register accessor: tx event fifo acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefa::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txefa`]
module"]
    pub type TXEFA = crate::Reg<txefa::TXEFA_SPEC>;
    #[doc = "tx event fifo acknowledge"]
    pub mod txefa {
        #[doc = "Register `TXEFA` reader"]
        pub type R = crate::R<TXEFA_SPEC>;
        #[doc = "Register `TXEFA` writer"]
        pub type W = crate::W<TXEFA_SPEC>;
        #[doc = "Field `EFAI` reader - Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL."]
        pub type EFAI_R = crate::FieldReader;
        #[doc = "Field `EFAI` writer - Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL."]
        pub type EFAI_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:4 - Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL."]
            #[inline(always)]
            pub fn efai(&self) -> EFAI_R {
                EFAI_R::new((self.bits & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL."]
            #[inline(always)]
            #[must_use]
            pub fn efai(&mut self) -> EFAI_W<TXEFA_SPEC> {
                EFAI_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "tx event fifo acknowledge\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txefa::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txefa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXEFA_SPEC;
        impl crate::RegisterSpec for TXEFA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txefa::R`](R) reader structure"]
        impl crate::Readable for TXEFA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txefa::W`](W) writer structure"]
        impl crate::Writable for TXEFA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXEFA to value 0"]
        impl crate::Resettable for TXEFA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TS_SEL (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ts_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ts_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ts_sel`]
module"]
    pub type TS_SEL = crate::Reg<ts_sel::TS_SEL_SPEC>;
    #[doc = "no description available"]
    pub mod ts_sel {
        #[doc = "Register `TS_SEL[%s]` reader"]
        pub type R = crate::R<TS_SEL_SPEC>;
        #[doc = "Register `TS_SEL[%s]` writer"]
        pub type W = crate::W<TS_SEL_SPEC>;
        #[doc = "Field `TS` reader - Timestamp Word TS default can save 16 timestamps with 32bit; if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…."]
        pub type TS_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Timestamp Word TS default can save 16 timestamps with 32bit; if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…."]
            #[inline(always)]
            pub fn ts(&self) -> TS_R {
                TS_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ts_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ts_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TS_SEL_SPEC;
        impl crate::RegisterSpec for TS_SEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ts_sel::R`](R) reader structure"]
        impl crate::Readable for TS_SEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ts_sel::W`](W) writer structure"]
        impl crate::Writable for TS_SEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TS_SEL[%s]
to value 0"]
        impl crate::Resettable for TS_SEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CREL (rw) register accessor: core release register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crel`]
module"]
    pub type CREL = crate::Reg<crel::CREL_SPEC>;
    #[doc = "core release register"]
    pub mod crel {
        #[doc = "Register `CREL` reader"]
        pub type R = crate::R<CREL_SPEC>;
        #[doc = "Register `CREL` writer"]
        pub type W = crate::W<CREL_SPEC>;
        #[doc = "Field `DAY` reader - Timestamp Day Two digits, BCD-coded. This field is set by generic parameter on synthesis."]
        pub type DAY_R = crate::FieldReader;
        #[doc = "Field `MON` reader - Timestamp Month Two digits, BCD-coded. This field is set by generic parameter on synthesis."]
        pub type MON_R = crate::FieldReader;
        #[doc = "Field `YEAR` reader - Timestamp Year One digit, BCD-coded. This field is set by generic parameter on synthesis."]
        pub type YEAR_R = crate::FieldReader;
        #[doc = "Field `SUBSTEP` reader - Sub-step of Core Release One digit, BCD-coded"]
        pub type SUBSTEP_R = crate::FieldReader;
        #[doc = "Field `STEP` reader - Step of Core Release One digit, BCD-coded."]
        pub type STEP_R = crate::FieldReader;
        #[doc = "Field `REL` reader - Core Release One digit, BCD-coded"]
        pub type REL_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - Timestamp Day Two digits, BCD-coded. This field is set by generic parameter on synthesis."]
            #[inline(always)]
            pub fn day(&self) -> DAY_R {
                DAY_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - Timestamp Month Two digits, BCD-coded. This field is set by generic parameter on synthesis."]
            #[inline(always)]
            pub fn mon(&self) -> MON_R {
                MON_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:19 - Timestamp Year One digit, BCD-coded. This field is set by generic parameter on synthesis."]
            #[inline(always)]
            pub fn year(&self) -> YEAR_R {
                YEAR_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bits 20:23 - Sub-step of Core Release One digit, BCD-coded"]
            #[inline(always)]
            pub fn substep(&self) -> SUBSTEP_R {
                SUBSTEP_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            #[doc = "Bits 24:27 - Step of Core Release One digit, BCD-coded."]
            #[inline(always)]
            pub fn step(&self) -> STEP_R {
                STEP_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            #[doc = "Bits 28:31 - Core Release One digit, BCD-coded"]
            #[inline(always)]
            pub fn rel(&self) -> REL_R {
                REL_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "core release register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CREL_SPEC;
        impl crate::RegisterSpec for CREL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`crel::R`](R) reader structure"]
        impl crate::Readable for CREL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`crel::W`](W) writer structure"]
        impl crate::Writable for CREL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CREL to value 0"]
        impl crate::Resettable for CREL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TSCFG (rw) register accessor: timestamp configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tscfg`]
module"]
    pub type TSCFG = crate::Reg<tscfg::TSCFG_SPEC>;
    #[doc = "timestamp configuration"]
    pub mod tscfg {
        #[doc = "Register `TSCFG` reader"]
        pub type R = crate::R<TSCFG_SPEC>;
        #[doc = "Register `TSCFG` writer"]
        pub type W = crate::W<TSCFG_SPEC>;
        #[doc = "Field `TSUE` reader - Timestamp Unit Enable 0: TSU disabled 1: TSU enabled"]
        pub type TSUE_R = crate::BitReader;
        #[doc = "Field `TSUE` writer - Timestamp Unit Enable 0: TSU disabled 1: TSU enabled"]
        pub type TSUE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TBCS` reader - Timebase Counter Select When the internal timebase is excluded by synthesis, TBCS is fixed to ‘1’. 0: Timestamp value captured from internal timebase counter, ATB.TB\\[31:0\\]
is the internal timbase counter 1: Timestamp value captured from input tsu_tbin\\[31:0\\],ATB.TB\\[31:0\\]
is tsu_tbin\\[31:0\\]"]
        pub type TBCS_R = crate::BitReader;
        #[doc = "Field `TBCS` writer - Timebase Counter Select When the internal timebase is excluded by synthesis, TBCS is fixed to ‘1’. 0: Timestamp value captured from internal timebase counter, ATB.TB\\[31:0\\]
is the internal timbase counter 1: Timestamp value captured from input tsu_tbin\\[31:0\\],ATB.TB\\[31:0\\]
is tsu_tbin\\[31:0\\]"]
        pub type TBCS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SCP` reader - Select Capturing Position 0: Capture Timestamp at EOF 1: Capture Timestamp at SOF"]
        pub type SCP_R = crate::BitReader;
        #[doc = "Field `SCP` writer - Select Capturing Position 0: Capture Timestamp at EOF 1: Capture Timestamp at SOF"]
        pub type SCP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN64` reader - set to use 64bit timestamp. when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. TSP can be used to select different one"]
        pub type EN64_R = crate::BitReader;
        #[doc = "Field `EN64` writer - set to use 64bit timestamp. when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. TSP can be used to select different one"]
        pub type EN64_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TBPRE` reader - Timebase Prescaler 0x00 to 0xFF The value by which the oscillator frequency is divided for generating the timebase counter clock. Valid values for the Timebase Prescaler are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Affects only the TSU internal timebase. When the internal timebase is excluded by synthesis, TBPRE\\[7:0\\]
is fixed to 0x00, the Timestamp Prescaler is not used."]
        pub type TBPRE_R = crate::FieldReader;
        #[doc = "Field `TBPRE` writer - Timebase Prescaler 0x00 to 0xFF The value by which the oscillator frequency is divided for generating the timebase counter clock. Valid values for the Timebase Prescaler are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Affects only the TSU internal timebase. When the internal timebase is excluded by synthesis, TBPRE\\[7:0\\]
is fixed to 0x00, the Timestamp Prescaler is not used."]
        pub type TBPRE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bit 0 - Timestamp Unit Enable 0: TSU disabled 1: TSU enabled"]
            #[inline(always)]
            pub fn tsue(&self) -> TSUE_R {
                TSUE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Timebase Counter Select When the internal timebase is excluded by synthesis, TBCS is fixed to ‘1’. 0: Timestamp value captured from internal timebase counter, ATB.TB\\[31:0\\]
is the internal timbase counter 1: Timestamp value captured from input tsu_tbin\\[31:0\\],ATB.TB\\[31:0\\]
is tsu_tbin\\[31:0\\]"]
            #[inline(always)]
            pub fn tbcs(&self) -> TBCS_R {
                TBCS_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Select Capturing Position 0: Capture Timestamp at EOF 1: Capture Timestamp at SOF"]
            #[inline(always)]
            pub fn scp(&self) -> SCP_R {
                SCP_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - set to use 64bit timestamp. when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. TSP can be used to select different one"]
            #[inline(always)]
            pub fn en64(&self) -> EN64_R {
                EN64_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 8:15 - Timebase Prescaler 0x00 to 0xFF The value by which the oscillator frequency is divided for generating the timebase counter clock. Valid values for the Timebase Prescaler are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Affects only the TSU internal timebase. When the internal timebase is excluded by synthesis, TBPRE\\[7:0\\]
is fixed to 0x00, the Timestamp Prescaler is not used."]
            #[inline(always)]
            pub fn tbpre(&self) -> TBPRE_R {
                TBPRE_R::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - Timestamp Unit Enable 0: TSU disabled 1: TSU enabled"]
            #[inline(always)]
            #[must_use]
            pub fn tsue(&mut self) -> TSUE_W<TSCFG_SPEC> {
                TSUE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Timebase Counter Select When the internal timebase is excluded by synthesis, TBCS is fixed to ‘1’. 0: Timestamp value captured from internal timebase counter, ATB.TB\\[31:0\\]
is the internal timbase counter 1: Timestamp value captured from input tsu_tbin\\[31:0\\],ATB.TB\\[31:0\\]
is tsu_tbin\\[31:0\\]"]
            #[inline(always)]
            #[must_use]
            pub fn tbcs(&mut self) -> TBCS_W<TSCFG_SPEC> {
                TBCS_W::new(self, 1)
            }
            #[doc = "Bit 2 - Select Capturing Position 0: Capture Timestamp at EOF 1: Capture Timestamp at SOF"]
            #[inline(always)]
            #[must_use]
            pub fn scp(&mut self) -> SCP_W<TSCFG_SPEC> {
                SCP_W::new(self, 2)
            }
            #[doc = "Bit 3 - set to use 64bit timestamp. when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. TSP can be used to select different one"]
            #[inline(always)]
            #[must_use]
            pub fn en64(&mut self) -> EN64_W<TSCFG_SPEC> {
                EN64_W::new(self, 3)
            }
            #[doc = "Bits 8:15 - Timebase Prescaler 0x00 to 0xFF The value by which the oscillator frequency is divided for generating the timebase counter clock. Valid values for the Timebase Prescaler are 0 to 255. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. Affects only the TSU internal timebase. When the internal timebase is excluded by synthesis, TBPRE\\[7:0\\]
is fixed to 0x00, the Timestamp Prescaler is not used."]
            #[inline(always)]
            #[must_use]
            pub fn tbpre(&mut self) -> TBPRE_W<TSCFG_SPEC> {
                TBPRE_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tscfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tscfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TSCFG_SPEC;
        impl crate::RegisterSpec for TSCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tscfg::R`](R) reader structure"]
        impl crate::Readable for TSCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tscfg::W`](W) writer structure"]
        impl crate::Writable for TSCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TSCFG to value 0"]
        impl crate::Resettable for TSCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TSS1 (rw) register accessor: timestamp status1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tss1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tss1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tss1`]
module"]
    pub type TSS1 = crate::Reg<tss1::TSS1_SPEC>;
    #[doc = "timestamp status1"]
    pub mod tss1 {
        #[doc = "Register `TSS1` reader"]
        pub type R = crate::R<TSS1_SPEC>;
        #[doc = "Register `TSS1` writer"]
        pub type W = crate::W<TSS1_SPEC>;
        #[doc = "Field `TSN` reader - Timestamp New Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related Timestamp register. Reading a Timestamp register resets the related bit."]
        pub type TSN_R = crate::FieldReader<u16>;
        #[doc = "Field `TSL` reader - Timestamp Lost Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. Reading a Timestamp register resets the related bit."]
        pub type TSL_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Timestamp New Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related Timestamp register. Reading a Timestamp register resets the related bit."]
            #[inline(always)]
            pub fn tsn(&self) -> TSN_R {
                TSN_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - Timestamp Lost Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. Reading a Timestamp register resets the related bit."]
            #[inline(always)]
            pub fn tsl(&self) -> TSL_R {
                TSL_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp status1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tss1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tss1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TSS1_SPEC;
        impl crate::RegisterSpec for TSS1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tss1::R`](R) reader structure"]
        impl crate::Readable for TSS1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tss1::W`](W) writer structure"]
        impl crate::Writable for TSS1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TSS1 to value 0"]
        impl crate::Resettable for TSS1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TSS2 (rw) register accessor: timestamp status2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tss2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tss2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tss2`]
module"]
    pub type TSS2 = crate::Reg<tss2::TSS2_SPEC>;
    #[doc = "timestamp status2"]
    pub mod tss2 {
        #[doc = "Register `TSS2` reader"]
        pub type R = crate::R<TSS2_SPEC>;
        #[doc = "Register `TSS2` writer"]
        pub type W = crate::W<TSS2_SPEC>;
        #[doc = "Field `TSP` reader - Timestamp Pointer The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 depending on number_ts_g), it is incremented to 0. Value also signalled on output m_can_tsp\\[3:0\\]."]
        pub type TSP_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:3 - Timestamp Pointer The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 depending on number_ts_g), it is incremented to 0. Value also signalled on output m_can_tsp\\[3:0\\]."]
            #[inline(always)]
            pub fn tsp(&self) -> TSP_R {
                TSP_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp status2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tss2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tss2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TSS2_SPEC;
        impl crate::RegisterSpec for TSS2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`tss2::R`](R) reader structure"]
        impl crate::Readable for TSS2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`tss2::W`](W) writer structure"]
        impl crate::Writable for TSS2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TSS2 to value 0"]
        impl crate::Resettable for TSS2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ATB (rw) register accessor: actual timebase\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atb`]
module"]
    pub type ATB = crate::Reg<atb::ATB_SPEC>;
    #[doc = "actual timebase"]
    pub mod atb {
        #[doc = "Register `ATB` reader"]
        pub type R = crate::R<ATB_SPEC>;
        #[doc = "Register `ATB` writer"]
        pub type W = crate::W<ATB_SPEC>;
        #[doc = "Field `TB` reader - timebase for timestamp generation 31-0"]
        pub type TB_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - timebase for timestamp generation 31-0"]
            #[inline(always)]
            pub fn tb(&self) -> TB_R {
                TB_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "actual timebase\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ATB_SPEC;
        impl crate::RegisterSpec for ATB_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`atb::R`](R) reader structure"]
        impl crate::Readable for ATB_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`atb::W`](W) writer structure"]
        impl crate::Writable for ATB_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ATB to value 0"]
        impl crate::Resettable for ATB_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ATBH (rw) register accessor: actual timebase high\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atbh::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atbh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@atbh`]
module"]
    pub type ATBH = crate::Reg<atbh::ATBH_SPEC>;
    #[doc = "actual timebase high"]
    pub mod atbh {
        #[doc = "Register `ATBH` reader"]
        pub type R = crate::R<ATBH_SPEC>;
        #[doc = "Register `ATBH` writer"]
        pub type W = crate::W<ATBH_SPEC>;
        #[doc = "Field `TBH` reader - timebase for timestamp generation 63-32"]
        pub type TBH_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - timebase for timestamp generation 63-32"]
            #[inline(always)]
            pub fn tbh(&self) -> TBH_R {
                TBH_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "actual timebase high\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`atbh::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`atbh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ATBH_SPEC;
        impl crate::RegisterSpec for ATBH_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`atbh::R`](R) reader structure"]
        impl crate::Readable for ATBH_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`atbh::W`](W) writer structure"]
        impl crate::Writable for ATBH_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ATBH to value 0"]
        impl crate::Resettable for ATBH_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GLB_CTL (rw) register accessor: global control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glb_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glb_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@glb_ctl`]
module"]
    pub type GLB_CTL = crate::Reg<glb_ctl::GLB_CTL_SPEC>;
    #[doc = "global control"]
    pub mod glb_ctl {
        #[doc = "Register `GLB_CTL` reader"]
        pub type R = crate::R<GLB_CTL_SPEC>;
        #[doc = "Register `GLB_CTL` writer"]
        pub type W = crate::W<GLB_CTL_SPEC>;
        #[doc = "Field `TSU_TBIN_SEL` reader - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1"]
        pub type TSU_TBIN_SEL_R = crate::FieldReader;
        #[doc = "Field `TSU_TBIN_SEL` writer - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1"]
        pub type TSU_TBIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `STBY_POL` reader - standby polarity selection"]
        pub type STBY_POL_R = crate::BitReader;
        #[doc = "Field `STBY_POL` writer - standby polarity selection"]
        pub type STBY_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STBY_CLR_EN` reader - m_can standby clear control 0:controlled by software by standby bit\\[bit31\\]
1:auto clear standby by hardware when rx data is 0"]
        pub type STBY_CLR_EN_R = crate::BitReader;
        #[doc = "Field `STBY_CLR_EN` writer - m_can standby clear control 0:controlled by software by standby bit\\[bit31\\]
1:auto clear standby by hardware when rx data is 0"]
        pub type STBY_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `M_CAN_STBY` reader - m_can standby control"]
        pub type M_CAN_STBY_R = crate::BitReader;
        #[doc = "Field `M_CAN_STBY` writer - m_can standby control"]
        pub type M_CAN_STBY_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1 - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1"]
            #[inline(always)]
            pub fn tsu_tbin_sel(&self) -> TSU_TBIN_SEL_R {
                TSU_TBIN_SEL_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 29 - standby polarity selection"]
            #[inline(always)]
            pub fn stby_pol(&self) -> STBY_POL_R {
                STBY_POL_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - m_can standby clear control 0:controlled by software by standby bit\\[bit31\\]
1:auto clear standby by hardware when rx data is 0"]
            #[inline(always)]
            pub fn stby_clr_en(&self) -> STBY_CLR_EN_R {
                STBY_CLR_EN_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - m_can standby control"]
            #[inline(always)]
            pub fn m_can_stby(&self) -> M_CAN_STBY_R {
                M_CAN_STBY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1"]
            #[inline(always)]
            #[must_use]
            pub fn tsu_tbin_sel(&mut self) -> TSU_TBIN_SEL_W<GLB_CTL_SPEC> {
                TSU_TBIN_SEL_W::new(self, 0)
            }
            #[doc = "Bit 29 - standby polarity selection"]
            #[inline(always)]
            #[must_use]
            pub fn stby_pol(&mut self) -> STBY_POL_W<GLB_CTL_SPEC> {
                STBY_POL_W::new(self, 29)
            }
            #[doc = "Bit 30 - m_can standby clear control 0:controlled by software by standby bit\\[bit31\\]
1:auto clear standby by hardware when rx data is 0"]
            #[inline(always)]
            #[must_use]
            pub fn stby_clr_en(&mut self) -> STBY_CLR_EN_W<GLB_CTL_SPEC> {
                STBY_CLR_EN_W::new(self, 30)
            }
            #[doc = "Bit 31 - m_can standby control"]
            #[inline(always)]
            #[must_use]
            pub fn m_can_stby(&mut self) -> M_CAN_STBY_W<GLB_CTL_SPEC> {
                M_CAN_STBY_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "global control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glb_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glb_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GLB_CTL_SPEC;
        impl crate::RegisterSpec for GLB_CTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`glb_ctl::R`](R) reader structure"]
        impl crate::Readable for GLB_CTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`glb_ctl::W`](W) writer structure"]
        impl crate::Writable for GLB_CTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GLB_CTL to value 0"]
        impl crate::Resettable for GLB_CTL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GLB_STATUS (rw) register accessor: global status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glb_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glb_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@glb_status`]
module"]
    pub type GLB_STATUS = crate::Reg<glb_status::GLB_STATUS_SPEC>;
    #[doc = "global status"]
    pub mod glb_status {
        #[doc = "Register `GLB_STATUS` reader"]
        pub type R = crate::R<GLB_STATUS_SPEC>;
        #[doc = "Register `GLB_STATUS` writer"]
        pub type W = crate::W<GLB_STATUS_SPEC>;
        #[doc = "Field `M_CAN_INT0` reader - m_can interrupt status0"]
        pub type M_CAN_INT0_R = crate::BitReader;
        #[doc = "Field `M_CAN_INT1` reader - m_can interrupt status1"]
        pub type M_CAN_INT1_R = crate::BitReader;
        impl R {
            #[doc = "Bit 2 - m_can interrupt status0"]
            #[inline(always)]
            pub fn m_can_int0(&self) -> M_CAN_INT0_R {
                M_CAN_INT0_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - m_can interrupt status1"]
            #[inline(always)]
            pub fn m_can_int1(&self) -> M_CAN_INT1_R {
                M_CAN_INT1_R::new(((self.bits >> 3) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "global status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glb_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glb_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GLB_STATUS_SPEC;
        impl crate::RegisterSpec for GLB_STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`glb_status::R`](R) reader structure"]
        impl crate::Readable for GLB_STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`glb_status::W`](W) writer structure"]
        impl crate::Writable for GLB_STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GLB_STATUS to value 0"]
        impl crate::Resettable for GLB_STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "MCAN1"]
pub struct MCAN1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MCAN1 {}
impl MCAN1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mcan0::RegisterBlock = 0xf028_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mcan0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MCAN1 {
    type Target = mcan0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MCAN1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MCAN1").finish()
    }
}
#[doc = "MCAN1"]
pub use self::mcan0 as mcan1;
#[doc = "MCAN2"]
pub struct MCAN2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MCAN2 {}
impl MCAN2 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mcan0::RegisterBlock = 0xf028_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mcan0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MCAN2 {
    type Target = mcan0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MCAN2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MCAN2").finish()
    }
}
#[doc = "MCAN2"]
pub use self::mcan0 as mcan2;
#[doc = "MCAN3"]
pub struct MCAN3 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MCAN3 {}
impl MCAN3 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mcan0::RegisterBlock = 0xf028_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mcan0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MCAN3 {
    type Target = mcan0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MCAN3 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MCAN3").finish()
    }
}
#[doc = "MCAN3"]
pub use self::mcan0 as mcan3;
#[doc = "PTPC"]
pub struct PTPC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PTPC {}
impl PTPC {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const ptpc::RegisterBlock = 0xf02f_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const ptpc::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PTPC {
    type Target = ptpc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PTPC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PTPC").finish()
    }
}
#[doc = "PTPC"]
pub mod ptpc {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        ptpc: (),
        _reserved1: [u8; 0x2000],
        time_sel: TIME_SEL,
        int_sts: INT_STS,
        int_en: INT_EN,
        _reserved4: [u8; 0x0ff4],
        ptpc_can_ts_sel: PTPC_CAN_TS_SEL,
    }
    impl RegisterBlock {
        #[doc = "0x00..0x70 - no description available"]
        #[inline(always)]
        pub const fn ptpc(&self, n: usize) -> &PTPC {
            #[allow(clippy::no_effect)]
            [(); 2][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(0)
                    .add(4096 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x70 - no description available"]
        #[inline(always)]
        pub fn ptpc_iter(&self) -> impl Iterator<Item = &PTPC> {
            (0..2).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(0)
                    .add(4096 * n)
                    .cast()
            })
        }
        #[doc = "0x2000 - No description avaiable"]
        #[inline(always)]
        pub const fn time_sel(&self) -> &TIME_SEL {
            &self.time_sel
        }
        #[doc = "0x2004 - No description avaiable"]
        #[inline(always)]
        pub const fn int_sts(&self) -> &INT_STS {
            &self.int_sts
        }
        #[doc = "0x2008 - No description avaiable"]
        #[inline(always)]
        pub const fn int_en(&self) -> &INT_EN {
            &self.int_en
        }
        #[doc = "0x3000 - No description avaiable"]
        #[inline(always)]
        pub const fn ptpc_can_ts_sel(&self) -> &PTPC_CAN_TS_SEL {
            &self.ptpc_can_ts_sel
        }
    }
    #[doc = "no description available"]
    pub use self::ptpc::PTPC;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod ptpc {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct PTPC {
            ctrl0: CTRL0,
            ctrl1: CTRL1,
            timeh: TIMEH,
            timel: TIMEL,
            ts_updth: TS_UPDTH,
            ts_updtl: TS_UPDTL,
            addend: ADDEND,
            tarh: TARH,
            tarl: TARL,
            _reserved9: [u8; 0x08],
            pps_ctrl: PPS_CTRL,
            capt_snaph: CAPT_SNAPH,
            capt_snapl: CAPT_SNAPL,
        }
        impl PTPC {
            #[doc = "0x00 - Control Register 0"]
            #[inline(always)]
            pub const fn ctrl0(&self) -> &CTRL0 {
                &self.ctrl0
            }
            #[doc = "0x04 - Control Register 1"]
            #[inline(always)]
            pub const fn ctrl1(&self) -> &CTRL1 {
                &self.ctrl1
            }
            #[doc = "0x08 - timestamp high"]
            #[inline(always)]
            pub const fn timeh(&self) -> &TIMEH {
                &self.timeh
            }
            #[doc = "0x0c - timestamp low"]
            #[inline(always)]
            pub const fn timel(&self) -> &TIMEL {
                &self.timel
            }
            #[doc = "0x10 - timestamp update high"]
            #[inline(always)]
            pub const fn ts_updth(&self) -> &TS_UPDTH {
                &self.ts_updth
            }
            #[doc = "0x14 - timestamp update low"]
            #[inline(always)]
            pub const fn ts_updtl(&self) -> &TS_UPDTL {
                &self.ts_updtl
            }
            #[doc = "0x18 - No description avaiable"]
            #[inline(always)]
            pub const fn addend(&self) -> &ADDEND {
                &self.addend
            }
            #[doc = "0x1c - No description avaiable"]
            #[inline(always)]
            pub const fn tarh(&self) -> &TARH {
                &self.tarh
            }
            #[doc = "0x20 - No description avaiable"]
            #[inline(always)]
            pub const fn tarl(&self) -> &TARL {
                &self.tarl
            }
            #[doc = "0x2c - No description avaiable"]
            #[inline(always)]
            pub const fn pps_ctrl(&self) -> &PPS_CTRL {
                &self.pps_ctrl
            }
            #[doc = "0x30 - No description avaiable"]
            #[inline(always)]
            pub const fn capt_snaph(&self) -> &CAPT_SNAPH {
                &self.capt_snaph
            }
            #[doc = "0x34 - No description avaiable"]
            #[inline(always)]
            pub const fn capt_snapl(&self) -> &CAPT_SNAPL {
                &self.capt_snapl
            }
        }
        #[doc = "Ctrl0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
module"]
        pub type CTRL0 = crate::Reg<ctrl0::CTRL0_SPEC>;
        #[doc = "Control Register 0"]
        pub mod ctrl0 {
            #[doc = "Register `Ctrl0` reader"]
            pub type R = crate::R<CTRL0_SPEC>;
            #[doc = "Register `Ctrl0` writer"]
            pub type W = crate::W<CTRL0_SPEC>;
            #[doc = "Field `TIMER_ENABLE` reader - No description avaiable"]
            pub type TIMER_ENABLE_R = crate::BitReader;
            #[doc = "Field `TIMER_ENABLE` writer - No description avaiable"]
            pub type TIMER_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FINE_COARSE_SEL` reader - 0: coarse update, ns counter add ss_incr\\[7:0\\]
each clk 1: fine update, ns counter add ss_incr\\[7:0\\]
each time addend counter overflow"]
            pub type FINE_COARSE_SEL_R = crate::BitReader;
            #[doc = "Field `FINE_COARSE_SEL` writer - 0: coarse update, ns counter add ss_incr\\[7:0\\]
each clk 1: fine update, ns counter add ss_incr\\[7:0\\]
each time addend counter overflow"]
            pub type FINE_COARSE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INIT_TIMER` writer - initial timer with ts_updt, pulse, clear after set"]
            pub type INIT_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `UPDATE_TIMER` writer - update timer with +/- ts_updt, pulse, clear after set"]
            pub type UPDATE_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `COMP_EN` reader - set to enable compare, will be cleared by HW when compare event triggered"]
            pub type COMP_EN_R = crate::BitReader;
            #[doc = "Field `COMP_EN` writer - set to enable compare, will be cleared by HW when compare event triggered"]
            pub type COMP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CAPT_SNAP_NEG_EN` reader - No description avaiable"]
            pub type CAPT_SNAP_NEG_EN_R = crate::BitReader;
            #[doc = "Field `CAPT_SNAP_NEG_EN` writer - No description avaiable"]
            pub type CAPT_SNAP_NEG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CAPT_SNAP_POS_EN` reader - set will use posege of input capture signal to latch timestamp value"]
            pub type CAPT_SNAP_POS_EN_R = crate::BitReader;
            #[doc = "Field `CAPT_SNAP_POS_EN` writer - set will use posege of input capture signal to latch timestamp value"]
            pub type CAPT_SNAP_POS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CAPT_SNAP_KEEP` reader - set will keep capture snap till software read capt_snapl. If this bit is set, software should read capt_snaph first to avoid wrong result. If this bit is cleared, capture result will be updated at each capture event"]
            pub type CAPT_SNAP_KEEP_R = crate::BitReader;
            #[doc = "Field `CAPT_SNAP_KEEP` writer - set will keep capture snap till software read capt_snapl. If this bit is set, software should read capt_snaph first to avoid wrong result. If this bit is cleared, capture result will be updated at each capture event"]
            pub type CAPT_SNAP_KEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SUBSEC_DIGITAL_ROLLOVER` reader - Format for ns counter rollover, 1-digital, overflow time 1000000000/0x3B9ACA00 0-binary, overflow time 0x7FFFFFFF"]
            pub type SUBSEC_DIGITAL_ROLLOVER_R = crate::BitReader;
            #[doc = "Field `SUBSEC_DIGITAL_ROLLOVER` writer - Format for ns counter rollover, 1-digital, overflow time 1000000000/0x3B9ACA00 0-binary, overflow time 0x7FFFFFFF"]
            pub type SUBSEC_DIGITAL_ROLLOVER_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - No description avaiable"]
                #[inline(always)]
                pub fn timer_enable(&self) -> TIMER_ENABLE_R {
                    TIMER_ENABLE_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - 0: coarse update, ns counter add ss_incr\\[7:0\\]
each clk 1: fine update, ns counter add ss_incr\\[7:0\\]
each time addend counter overflow"]
                #[inline(always)]
                pub fn fine_coarse_sel(&self) -> FINE_COARSE_SEL_R {
                    FINE_COARSE_SEL_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 4 - set to enable compare, will be cleared by HW when compare event triggered"]
                #[inline(always)]
                pub fn comp_en(&self) -> COMP_EN_R {
                    COMP_EN_R::new(((self.bits >> 4) & 1) != 0)
                }
                #[doc = "Bit 6 - No description avaiable"]
                #[inline(always)]
                pub fn capt_snap_neg_en(&self) -> CAPT_SNAP_NEG_EN_R {
                    CAPT_SNAP_NEG_EN_R::new(((self.bits >> 6) & 1) != 0)
                }
                #[doc = "Bit 7 - set will use posege of input capture signal to latch timestamp value"]
                #[inline(always)]
                pub fn capt_snap_pos_en(&self) -> CAPT_SNAP_POS_EN_R {
                    CAPT_SNAP_POS_EN_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bit 8 - set will keep capture snap till software read capt_snapl. If this bit is set, software should read capt_snaph first to avoid wrong result. If this bit is cleared, capture result will be updated at each capture event"]
                #[inline(always)]
                pub fn capt_snap_keep(&self) -> CAPT_SNAP_KEEP_R {
                    CAPT_SNAP_KEEP_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - Format for ns counter rollover, 1-digital, overflow time 1000000000/0x3B9ACA00 0-binary, overflow time 0x7FFFFFFF"]
                #[inline(always)]
                pub fn subsec_digital_rollover(&self) -> SUBSEC_DIGITAL_ROLLOVER_R {
                    SUBSEC_DIGITAL_ROLLOVER_R::new(((self.bits >> 9) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn timer_enable(&mut self) -> TIMER_ENABLE_W<CTRL0_SPEC> {
                    TIMER_ENABLE_W::new(self, 0)
                }
                #[doc = "Bit 1 - 0: coarse update, ns counter add ss_incr\\[7:0\\]
each clk 1: fine update, ns counter add ss_incr\\[7:0\\]
each time addend counter overflow"]
                #[inline(always)]
                #[must_use]
                pub fn fine_coarse_sel(&mut self) -> FINE_COARSE_SEL_W<CTRL0_SPEC> {
                    FINE_COARSE_SEL_W::new(self, 1)
                }
                #[doc = "Bit 2 - initial timer with ts_updt, pulse, clear after set"]
                #[inline(always)]
                #[must_use]
                pub fn init_timer(&mut self) -> INIT_TIMER_W<CTRL0_SPEC> {
                    INIT_TIMER_W::new(self, 2)
                }
                #[doc = "Bit 3 - update timer with +/- ts_updt, pulse, clear after set"]
                #[inline(always)]
                #[must_use]
                pub fn update_timer(&mut self) -> UPDATE_TIMER_W<CTRL0_SPEC> {
                    UPDATE_TIMER_W::new(self, 3)
                }
                #[doc = "Bit 4 - set to enable compare, will be cleared by HW when compare event triggered"]
                #[inline(always)]
                #[must_use]
                pub fn comp_en(&mut self) -> COMP_EN_W<CTRL0_SPEC> {
                    COMP_EN_W::new(self, 4)
                }
                #[doc = "Bit 6 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn capt_snap_neg_en(&mut self) -> CAPT_SNAP_NEG_EN_W<CTRL0_SPEC> {
                    CAPT_SNAP_NEG_EN_W::new(self, 6)
                }
                #[doc = "Bit 7 - set will use posege of input capture signal to latch timestamp value"]
                #[inline(always)]
                #[must_use]
                pub fn capt_snap_pos_en(&mut self) -> CAPT_SNAP_POS_EN_W<CTRL0_SPEC> {
                    CAPT_SNAP_POS_EN_W::new(self, 7)
                }
                #[doc = "Bit 8 - set will keep capture snap till software read capt_snapl. If this bit is set, software should read capt_snaph first to avoid wrong result. If this bit is cleared, capture result will be updated at each capture event"]
                #[inline(always)]
                #[must_use]
                pub fn capt_snap_keep(&mut self) -> CAPT_SNAP_KEEP_W<CTRL0_SPEC> {
                    CAPT_SNAP_KEEP_W::new(self, 8)
                }
                #[doc = "Bit 9 - Format for ns counter rollover, 1-digital, overflow time 1000000000/0x3B9ACA00 0-binary, overflow time 0x7FFFFFFF"]
                #[inline(always)]
                #[must_use]
                pub fn subsec_digital_rollover(&mut self) -> SUBSEC_DIGITAL_ROLLOVER_W<CTRL0_SPEC> {
                    SUBSEC_DIGITAL_ROLLOVER_W::new(self, 9)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CTRL0_SPEC;
            impl crate::RegisterSpec for CTRL0_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"]
            impl crate::Readable for CTRL0_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
            impl crate::Writable for CTRL0_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets Ctrl0 to value 0"]
            impl crate::Resettable for CTRL0_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "ctrl1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
module"]
        pub type CTRL1 = crate::Reg<ctrl1::CTRL1_SPEC>;
        #[doc = "Control Register 1"]
        pub mod ctrl1 {
            #[doc = "Register `ctrl1` reader"]
            pub type R = crate::R<CTRL1_SPEC>;
            #[doc = "Register `ctrl1` writer"]
            pub type W = crate::W<CTRL1_SPEC>;
            #[doc = "Field `SS_INCR` reader - constant value used to add ns counter; such as for 50MHz timer clock, set it to 8'd20"]
            pub type SS_INCR_R = crate::FieldReader;
            #[doc = "Field `SS_INCR` writer - constant value used to add ns counter; such as for 50MHz timer clock, set it to 8'd20"]
            pub type SS_INCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bits 0:7 - constant value used to add ns counter; such as for 50MHz timer clock, set it to 8'd20"]
                #[inline(always)]
                pub fn ss_incr(&self) -> SS_INCR_R {
                    SS_INCR_R::new((self.bits & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - constant value used to add ns counter; such as for 50MHz timer clock, set it to 8'd20"]
                #[inline(always)]
                #[must_use]
                pub fn ss_incr(&mut self) -> SS_INCR_W<CTRL1_SPEC> {
                    SS_INCR_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CTRL1_SPEC;
            impl crate::RegisterSpec for CTRL1_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"]
            impl crate::Readable for CTRL1_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
            impl crate::Writable for CTRL1_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ctrl1 to value 0"]
            impl crate::Resettable for CTRL1_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "timeh (rw) register accessor: timestamp high\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeh::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeh`]
module"]
        pub type TIMEH = crate::Reg<timeh::TIMEH_SPEC>;
        #[doc = "timestamp high"]
        pub mod timeh {
            #[doc = "Register `timeh` reader"]
            pub type R = crate::R<TIMEH_SPEC>;
            #[doc = "Register `timeh` writer"]
            pub type W = crate::W<TIMEH_SPEC>;
            #[doc = "Field `TIMESTAMP_HIGH` reader - No description avaiable"]
            pub type TIMESTAMP_HIGH_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - No description avaiable"]
                #[inline(always)]
                pub fn timestamp_high(&self) -> TIMESTAMP_HIGH_R {
                    TIMESTAMP_HIGH_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "timestamp high\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeh::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TIMEH_SPEC;
            impl crate::RegisterSpec for TIMEH_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`timeh::R`](R) reader structure"]
            impl crate::Readable for TIMEH_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`timeh::W`](W) writer structure"]
            impl crate::Writable for TIMEH_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets timeh to value 0"]
            impl crate::Resettable for TIMEH_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "timel (rw) register accessor: timestamp low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timel`]
module"]
        pub type TIMEL = crate::Reg<timel::TIMEL_SPEC>;
        #[doc = "timestamp low"]
        pub mod timel {
            #[doc = "Register `timel` reader"]
            pub type R = crate::R<TIMEL_SPEC>;
            #[doc = "Register `timel` writer"]
            pub type W = crate::W<TIMEL_SPEC>;
            #[doc = "Field `TIMESTAMP_LOW` reader - No description avaiable"]
            pub type TIMESTAMP_LOW_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - No description avaiable"]
                #[inline(always)]
                pub fn timestamp_low(&self) -> TIMESTAMP_LOW_R {
                    TIMESTAMP_LOW_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "timestamp low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TIMEL_SPEC;
            impl crate::RegisterSpec for TIMEL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`timel::R`](R) reader structure"]
            impl crate::Readable for TIMEL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`timel::W`](W) writer structure"]
            impl crate::Writable for TIMEL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets timel to value 0"]
            impl crate::Resettable for TIMEL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "ts_updth (rw) register accessor: timestamp update high\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ts_updth::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ts_updth::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ts_updth`]
module"]
        pub type TS_UPDTH = crate::Reg<ts_updth::TS_UPDTH_SPEC>;
        #[doc = "timestamp update high"]
        pub mod ts_updth {
            #[doc = "Register `ts_updth` reader"]
            pub type R = crate::R<TS_UPDTH_SPEC>;
            #[doc = "Register `ts_updth` writer"]
            pub type W = crate::W<TS_UPDTH_SPEC>;
            #[doc = "Field `SEC_UPDATE` reader - together with ts_updtl, used to initial or update timestamp"]
            pub type SEC_UPDATE_R = crate::FieldReader<u32>;
            #[doc = "Field `SEC_UPDATE` writer - together with ts_updtl, used to initial or update timestamp"]
            pub type SEC_UPDATE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - together with ts_updtl, used to initial or update timestamp"]
                #[inline(always)]
                pub fn sec_update(&self) -> SEC_UPDATE_R {
                    SEC_UPDATE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - together with ts_updtl, used to initial or update timestamp"]
                #[inline(always)]
                #[must_use]
                pub fn sec_update(&mut self) -> SEC_UPDATE_W<TS_UPDTH_SPEC> {
                    SEC_UPDATE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "timestamp update high\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ts_updth::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ts_updth::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TS_UPDTH_SPEC;
            impl crate::RegisterSpec for TS_UPDTH_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ts_updth::R`](R) reader structure"]
            impl crate::Readable for TS_UPDTH_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ts_updth::W`](W) writer structure"]
            impl crate::Writable for TS_UPDTH_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ts_updth to value 0"]
            impl crate::Resettable for TS_UPDTH_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "ts_updtl (rw) register accessor: timestamp update low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ts_updtl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ts_updtl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ts_updtl`]
module"]
        pub type TS_UPDTL = crate::Reg<ts_updtl::TS_UPDTL_SPEC>;
        #[doc = "timestamp update low"]
        pub mod ts_updtl {
            #[doc = "Register `ts_updtl` reader"]
            pub type R = crate::R<TS_UPDTL_SPEC>;
            #[doc = "Register `ts_updtl` writer"]
            pub type W = crate::W<TS_UPDTL_SPEC>;
            #[doc = "Field `NS_UPDATE` reader - No description avaiable"]
            pub type NS_UPDATE_R = crate::FieldReader<u32>;
            #[doc = "Field `NS_UPDATE` writer - No description avaiable"]
            pub type NS_UPDATE_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
            #[doc = "Field `ADD_SUB` reader - 1 for sub; 0 for add, used only at update"]
            pub type ADD_SUB_R = crate::BitReader;
            #[doc = "Field `ADD_SUB` writer - 1 for sub; 0 for add, used only at update"]
            pub type ADD_SUB_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:30 - No description avaiable"]
                #[inline(always)]
                pub fn ns_update(&self) -> NS_UPDATE_R {
                    NS_UPDATE_R::new(self.bits & 0x7fff_ffff)
                }
                #[doc = "Bit 31 - 1 for sub; 0 for add, used only at update"]
                #[inline(always)]
                pub fn add_sub(&self) -> ADD_SUB_R {
                    ADD_SUB_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:30 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn ns_update(&mut self) -> NS_UPDATE_W<TS_UPDTL_SPEC> {
                    NS_UPDATE_W::new(self, 0)
                }
                #[doc = "Bit 31 - 1 for sub; 0 for add, used only at update"]
                #[inline(always)]
                #[must_use]
                pub fn add_sub(&mut self) -> ADD_SUB_W<TS_UPDTL_SPEC> {
                    ADD_SUB_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "timestamp update low\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ts_updtl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ts_updtl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TS_UPDTL_SPEC;
            impl crate::RegisterSpec for TS_UPDTL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ts_updtl::R`](R) reader structure"]
            impl crate::Readable for TS_UPDTL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ts_updtl::W`](W) writer structure"]
            impl crate::Writable for TS_UPDTL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ts_updtl to value 0"]
            impl crate::Resettable for TS_UPDTL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "addend (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addend::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addend`]
module"]
        pub type ADDEND = crate::Reg<addend::ADDEND_SPEC>;
        #[doc = "No description avaiable"]
        pub mod addend {
            #[doc = "Register `addend` reader"]
            pub type R = crate::R<ADDEND_SPEC>;
            #[doc = "Register `addend` writer"]
            pub type W = crate::W<ADDEND_SPEC>;
            #[doc = "Field `ADDEND` reader - used in fine update mode only"]
            pub type ADDEND_R = crate::FieldReader<u32>;
            #[doc = "Field `ADDEND` writer - used in fine update mode only"]
            pub type ADDEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - used in fine update mode only"]
                #[inline(always)]
                pub fn addend(&self) -> ADDEND_R {
                    ADDEND_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - used in fine update mode only"]
                #[inline(always)]
                #[must_use]
                pub fn addend(&mut self) -> ADDEND_W<ADDEND_SPEC> {
                    ADDEND_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addend::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct ADDEND_SPEC;
            impl crate::RegisterSpec for ADDEND_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`addend::R`](R) reader structure"]
            impl crate::Readable for ADDEND_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`addend::W`](W) writer structure"]
            impl crate::Writable for ADDEND_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets addend to value 0"]
            impl crate::Resettable for ADDEND_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "tarh (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tarh::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tarh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tarh`]
module"]
        pub type TARH = crate::Reg<tarh::TARH_SPEC>;
        #[doc = "No description avaiable"]
        pub mod tarh {
            #[doc = "Register `tarh` reader"]
            pub type R = crate::R<TARH_SPEC>;
            #[doc = "Register `tarh` writer"]
            pub type W = crate::W<TARH_SPEC>;
            #[doc = "Field `TARGET_TIME_HIGH` reader - used for generate compare signal if enabled"]
            pub type TARGET_TIME_HIGH_R = crate::FieldReader<u32>;
            #[doc = "Field `TARGET_TIME_HIGH` writer - used for generate compare signal if enabled"]
            pub type TARGET_TIME_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - used for generate compare signal if enabled"]
                #[inline(always)]
                pub fn target_time_high(&self) -> TARGET_TIME_HIGH_R {
                    TARGET_TIME_HIGH_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - used for generate compare signal if enabled"]
                #[inline(always)]
                #[must_use]
                pub fn target_time_high(&mut self) -> TARGET_TIME_HIGH_W<TARH_SPEC> {
                    TARGET_TIME_HIGH_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tarh::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tarh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TARH_SPEC;
            impl crate::RegisterSpec for TARH_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`tarh::R`](R) reader structure"]
            impl crate::Readable for TARH_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`tarh::W`](W) writer structure"]
            impl crate::Writable for TARH_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets tarh to value 0"]
            impl crate::Resettable for TARH_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "tarl (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tarl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tarl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tarl`]
module"]
        pub type TARL = crate::Reg<tarl::TARL_SPEC>;
        #[doc = "No description avaiable"]
        pub mod tarl {
            #[doc = "Register `tarl` reader"]
            pub type R = crate::R<TARL_SPEC>;
            #[doc = "Register `tarl` writer"]
            pub type W = crate::W<TARL_SPEC>;
            #[doc = "Field `TARGET_TIME_LOW` reader - No description avaiable"]
            pub type TARGET_TIME_LOW_R = crate::FieldReader<u32>;
            #[doc = "Field `TARGET_TIME_LOW` writer - No description avaiable"]
            pub type TARGET_TIME_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - No description avaiable"]
                #[inline(always)]
                pub fn target_time_low(&self) -> TARGET_TIME_LOW_R {
                    TARGET_TIME_LOW_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn target_time_low(&mut self) -> TARGET_TIME_LOW_W<TARL_SPEC> {
                    TARGET_TIME_LOW_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tarl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tarl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TARL_SPEC;
            impl crate::RegisterSpec for TARL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`tarl::R`](R) reader structure"]
            impl crate::Readable for TARL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`tarl::W`](W) writer structure"]
            impl crate::Writable for TARL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets tarl to value 0"]
            impl crate::Resettable for TARL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "pps_ctrl (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pps_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pps_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pps_ctrl`]
module"]
        pub type PPS_CTRL = crate::Reg<pps_ctrl::PPS_CTRL_SPEC>;
        #[doc = "No description avaiable"]
        pub mod pps_ctrl {
            #[doc = "Register `pps_ctrl` reader"]
            pub type R = crate::R<PPS_CTRL_SPEC>;
            #[doc = "Register `pps_ctrl` writer"]
            pub type W = crate::W<PPS_CTRL_SPEC>;
            #[doc = "Field `PPS_CTRL` reader - No description avaiable"]
            pub type PPS_CTRL_R = crate::FieldReader;
            #[doc = "Field `PPS_CTRL` writer - No description avaiable"]
            pub type PPS_CTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            impl R {
                #[doc = "Bits 0:3 - No description avaiable"]
                #[inline(always)]
                pub fn pps_ctrl(&self) -> PPS_CTRL_R {
                    PPS_CTRL_R::new((self.bits & 0x0f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:3 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn pps_ctrl(&mut self) -> PPS_CTRL_W<PPS_CTRL_SPEC> {
                    PPS_CTRL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pps_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pps_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PPS_CTRL_SPEC;
            impl crate::RegisterSpec for PPS_CTRL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pps_ctrl::R`](R) reader structure"]
            impl crate::Readable for PPS_CTRL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pps_ctrl::W`](W) writer structure"]
            impl crate::Writable for PPS_CTRL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets pps_ctrl to value 0"]
            impl crate::Resettable for PPS_CTRL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "capt_snaph (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capt_snaph::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capt_snaph::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capt_snaph`]
module"]
        pub type CAPT_SNAPH = crate::Reg<capt_snaph::CAPT_SNAPH_SPEC>;
        #[doc = "No description avaiable"]
        pub mod capt_snaph {
            #[doc = "Register `capt_snaph` reader"]
            pub type R = crate::R<CAPT_SNAPH_SPEC>;
            #[doc = "Register `capt_snaph` writer"]
            pub type W = crate::W<CAPT_SNAPH_SPEC>;
            #[doc = "Field `CAPT_SNAP_HIGH` reader - take snapshot for input capture signal, at pos or neg or both; the result can be kept or updated at each event according to cfg0.bit8"]
            pub type CAPT_SNAP_HIGH_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - take snapshot for input capture signal, at pos or neg or both; the result can be kept or updated at each event according to cfg0.bit8"]
                #[inline(always)]
                pub fn capt_snap_high(&self) -> CAPT_SNAP_HIGH_R {
                    CAPT_SNAP_HIGH_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capt_snaph::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capt_snaph::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CAPT_SNAPH_SPEC;
            impl crate::RegisterSpec for CAPT_SNAPH_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`capt_snaph::R`](R) reader structure"]
            impl crate::Readable for CAPT_SNAPH_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`capt_snaph::W`](W) writer structure"]
            impl crate::Writable for CAPT_SNAPH_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets capt_snaph to value 0"]
            impl crate::Resettable for CAPT_SNAPH_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "capt_snapl (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capt_snapl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capt_snapl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capt_snapl`]
module"]
        pub type CAPT_SNAPL = crate::Reg<capt_snapl::CAPT_SNAPL_SPEC>;
        #[doc = "No description avaiable"]
        pub mod capt_snapl {
            #[doc = "Register `capt_snapl` reader"]
            pub type R = crate::R<CAPT_SNAPL_SPEC>;
            #[doc = "Register `capt_snapl` writer"]
            pub type W = crate::W<CAPT_SNAPL_SPEC>;
            #[doc = "Field `CAPT_SNAP_LOW` reader - No description avaiable"]
            pub type CAPT_SNAP_LOW_R = crate::FieldReader<u32>;
            #[doc = "Field `CAPT_SNAP_LOW` writer - No description avaiable"]
            pub type CAPT_SNAP_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - No description avaiable"]
                #[inline(always)]
                pub fn capt_snap_low(&self) -> CAPT_SNAP_LOW_R {
                    CAPT_SNAP_LOW_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn capt_snap_low(&mut self) -> CAPT_SNAP_LOW_W<CAPT_SNAPL_SPEC> {
                    CAPT_SNAP_LOW_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capt_snapl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capt_snapl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CAPT_SNAPL_SPEC;
            impl crate::RegisterSpec for CAPT_SNAPL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`capt_snapl::R`](R) reader structure"]
            impl crate::Readable for CAPT_SNAPL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`capt_snapl::W`](W) writer structure"]
            impl crate::Writable for CAPT_SNAPL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets capt_snapl to value 0"]
            impl crate::Resettable for CAPT_SNAPL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "time_sel (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@time_sel`]
module"]
    pub type TIME_SEL = crate::Reg<time_sel::TIME_SEL_SPEC>;
    #[doc = "No description avaiable"]
    pub mod time_sel {
        #[doc = "Register `time_sel` reader"]
        pub type R = crate::R<TIME_SEL_SPEC>;
        #[doc = "Register `time_sel` writer"]
        pub type W = crate::W<TIME_SEL_SPEC>;
        #[doc = "Field `CAN0_TIME_SEL` reader - set to use ptpc1 for canx clr to use ptpc0 for canx"]
        pub type CAN0_TIME_SEL_R = crate::BitReader;
        #[doc = "Field `CAN0_TIME_SEL` writer - set to use ptpc1 for canx clr to use ptpc0 for canx"]
        pub type CAN0_TIME_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAN1_TIME_SEL` reader - No description avaiable"]
        pub type CAN1_TIME_SEL_R = crate::BitReader;
        #[doc = "Field `CAN1_TIME_SEL` writer - No description avaiable"]
        pub type CAN1_TIME_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAN2_TIME_SEL` reader - No description avaiable"]
        pub type CAN2_TIME_SEL_R = crate::BitReader;
        #[doc = "Field `CAN2_TIME_SEL` writer - No description avaiable"]
        pub type CAN2_TIME_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAN3_TIME_SEL` reader - No description avaiable"]
        pub type CAN3_TIME_SEL_R = crate::BitReader;
        #[doc = "Field `CAN3_TIME_SEL` writer - No description avaiable"]
        pub type CAN3_TIME_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - set to use ptpc1 for canx clr to use ptpc0 for canx"]
            #[inline(always)]
            pub fn can0_time_sel(&self) -> CAN0_TIME_SEL_R {
                CAN0_TIME_SEL_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn can1_time_sel(&self) -> CAN1_TIME_SEL_R {
                CAN1_TIME_SEL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            pub fn can2_time_sel(&self) -> CAN2_TIME_SEL_R {
                CAN2_TIME_SEL_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            pub fn can3_time_sel(&self) -> CAN3_TIME_SEL_R {
                CAN3_TIME_SEL_R::new(((self.bits >> 3) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - set to use ptpc1 for canx clr to use ptpc0 for canx"]
            #[inline(always)]
            #[must_use]
            pub fn can0_time_sel(&mut self) -> CAN0_TIME_SEL_W<TIME_SEL_SPEC> {
                CAN0_TIME_SEL_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn can1_time_sel(&mut self) -> CAN1_TIME_SEL_W<TIME_SEL_SPEC> {
                CAN1_TIME_SEL_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn can2_time_sel(&mut self) -> CAN2_TIME_SEL_W<TIME_SEL_SPEC> {
                CAN2_TIME_SEL_W::new(self, 2)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn can3_time_sel(&mut self) -> CAN3_TIME_SEL_W<TIME_SEL_SPEC> {
                CAN3_TIME_SEL_W::new(self, 3)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TIME_SEL_SPEC;
        impl crate::RegisterSpec for TIME_SEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`time_sel::R`](R) reader structure"]
        impl crate::Readable for TIME_SEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`time_sel::W`](W) writer structure"]
        impl crate::Writable for TIME_SEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets time_sel to value 0"]
        impl crate::Resettable for TIME_SEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "int_sts (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_sts`]
module"]
    pub type INT_STS = crate::Reg<int_sts::INT_STS_SPEC>;
    #[doc = "No description avaiable"]
    pub mod int_sts {
        #[doc = "Register `int_sts` reader"]
        pub type R = crate::R<INT_STS_SPEC>;
        #[doc = "Register `int_sts` writer"]
        pub type W = crate::W<INT_STS_SPEC>;
        #[doc = "Field `PPS_INT_STS0` writer - No description avaiable"]
        pub type PPS_INT_STS0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAPTURE_INT_STS0` writer - No description avaiable"]
        pub type CAPTURE_INT_STS0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COMP_INT_STS0` writer - No description avaiable"]
        pub type COMP_INT_STS0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PPS_INT_STS1` writer - No description avaiable"]
        pub type PPS_INT_STS1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAPTURE_INT_STS1` writer - No description avaiable"]
        pub type CAPTURE_INT_STS1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COMP_INT_STS1` writer - No description avaiable"]
        pub type COMP_INT_STS1_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pps_int_sts0(&mut self) -> PPS_INT_STS0_W<INT_STS_SPEC> {
                PPS_INT_STS0_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn capture_int_sts0(&mut self) -> CAPTURE_INT_STS0_W<INT_STS_SPEC> {
                CAPTURE_INT_STS0_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn comp_int_sts0(&mut self) -> COMP_INT_STS0_W<INT_STS_SPEC> {
                COMP_INT_STS0_W::new(self, 2)
            }
            #[doc = "Bit 16 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pps_int_sts1(&mut self) -> PPS_INT_STS1_W<INT_STS_SPEC> {
                PPS_INT_STS1_W::new(self, 16)
            }
            #[doc = "Bit 17 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn capture_int_sts1(&mut self) -> CAPTURE_INT_STS1_W<INT_STS_SPEC> {
                CAPTURE_INT_STS1_W::new(self, 17)
            }
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn comp_int_sts1(&mut self) -> COMP_INT_STS1_W<INT_STS_SPEC> {
                COMP_INT_STS1_W::new(self, 18)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_STS_SPEC;
        impl crate::RegisterSpec for INT_STS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_sts::R`](R) reader structure"]
        impl crate::Readable for INT_STS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_sts::W`](W) writer structure"]
        impl crate::Writable for INT_STS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets int_sts to value 0"]
        impl crate::Resettable for INT_STS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "int_en (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_en`]
module"]
    pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
    #[doc = "No description avaiable"]
    pub mod int_en {
        #[doc = "Register `int_en` reader"]
        pub type R = crate::R<INT_EN_SPEC>;
        #[doc = "Register `int_en` writer"]
        pub type W = crate::W<INT_EN_SPEC>;
        #[doc = "Field `PPS_INT_STS0` reader - No description avaiable"]
        pub type PPS_INT_STS0_R = crate::BitReader;
        #[doc = "Field `PPS_INT_STS0` writer - No description avaiable"]
        pub type PPS_INT_STS0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAPTURE_INT_STS0` reader - No description avaiable"]
        pub type CAPTURE_INT_STS0_R = crate::BitReader;
        #[doc = "Field `CAPTURE_INT_STS0` writer - No description avaiable"]
        pub type CAPTURE_INT_STS0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COMP_INT_STS0` reader - No description avaiable"]
        pub type COMP_INT_STS0_R = crate::BitReader;
        #[doc = "Field `COMP_INT_STS0` writer - No description avaiable"]
        pub type COMP_INT_STS0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PPS_INT_STS1` reader - No description avaiable"]
        pub type PPS_INT_STS1_R = crate::BitReader;
        #[doc = "Field `PPS_INT_STS1` writer - No description avaiable"]
        pub type PPS_INT_STS1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAPTURE_INT_STS1` reader - No description avaiable"]
        pub type CAPTURE_INT_STS1_R = crate::BitReader;
        #[doc = "Field `CAPTURE_INT_STS1` writer - No description avaiable"]
        pub type CAPTURE_INT_STS1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COMP_INT_STS1` reader - No description avaiable"]
        pub type COMP_INT_STS1_R = crate::BitReader;
        #[doc = "Field `COMP_INT_STS1` writer - No description avaiable"]
        pub type COMP_INT_STS1_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            pub fn pps_int_sts0(&self) -> PPS_INT_STS0_R {
                PPS_INT_STS0_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn capture_int_sts0(&self) -> CAPTURE_INT_STS0_R {
                CAPTURE_INT_STS0_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            pub fn comp_int_sts0(&self) -> COMP_INT_STS0_R {
                COMP_INT_STS0_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 16 - No description avaiable"]
            #[inline(always)]
            pub fn pps_int_sts1(&self) -> PPS_INT_STS1_R {
                PPS_INT_STS1_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - No description avaiable"]
            #[inline(always)]
            pub fn capture_int_sts1(&self) -> CAPTURE_INT_STS1_R {
                CAPTURE_INT_STS1_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            pub fn comp_int_sts1(&self) -> COMP_INT_STS1_R {
                COMP_INT_STS1_R::new(((self.bits >> 18) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pps_int_sts0(&mut self) -> PPS_INT_STS0_W<INT_EN_SPEC> {
                PPS_INT_STS0_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn capture_int_sts0(&mut self) -> CAPTURE_INT_STS0_W<INT_EN_SPEC> {
                CAPTURE_INT_STS0_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn comp_int_sts0(&mut self) -> COMP_INT_STS0_W<INT_EN_SPEC> {
                COMP_INT_STS0_W::new(self, 2)
            }
            #[doc = "Bit 16 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pps_int_sts1(&mut self) -> PPS_INT_STS1_W<INT_EN_SPEC> {
                PPS_INT_STS1_W::new(self, 16)
            }
            #[doc = "Bit 17 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn capture_int_sts1(&mut self) -> CAPTURE_INT_STS1_W<INT_EN_SPEC> {
                CAPTURE_INT_STS1_W::new(self, 17)
            }
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn comp_int_sts1(&mut self) -> COMP_INT_STS1_W<INT_EN_SPEC> {
                COMP_INT_STS1_W::new(self, 18)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_EN_SPEC;
        impl crate::RegisterSpec for INT_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_en::R`](R) reader structure"]
        impl crate::Readable for INT_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_en::W`](W) writer structure"]
        impl crate::Writable for INT_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets int_en to value 0"]
        impl crate::Resettable for INT_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ptpc_can_ts_sel (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ptpc_can_ts_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ptpc_can_ts_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ptpc_can_ts_sel`]
module"]
    pub type PTPC_CAN_TS_SEL = crate::Reg<ptpc_can_ts_sel::PTPC_CAN_TS_SEL_SPEC>;
    #[doc = "No description avaiable"]
    pub mod ptpc_can_ts_sel {
        #[doc = "Register `ptpc_can_ts_sel` reader"]
        pub type R = crate::R<PTPC_CAN_TS_SEL_SPEC>;
        #[doc = "Register `ptpc_can_ts_sel` writer"]
        pub type W = crate::W<PTPC_CAN_TS_SEL_SPEC>;
        #[doc = "Field `TSU_TBIN0_SEL` reader - No description avaiable"]
        pub type TSU_TBIN0_SEL_R = crate::FieldReader;
        #[doc = "Field `TSU_TBIN0_SEL` writer - No description avaiable"]
        pub type TSU_TBIN0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `TSU_TBIN1_SEL` reader - No description avaiable"]
        pub type TSU_TBIN1_SEL_R = crate::FieldReader;
        #[doc = "Field `TSU_TBIN1_SEL` writer - No description avaiable"]
        pub type TSU_TBIN1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `TSU_TBIN2_SEL` reader - No description avaiable"]
        pub type TSU_TBIN2_SEL_R = crate::FieldReader;
        #[doc = "Field `TSU_TBIN2_SEL` writer - No description avaiable"]
        pub type TSU_TBIN2_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `TSU_TBIN3_SEL` reader - No description avaiable"]
        pub type TSU_TBIN3_SEL_R = crate::FieldReader;
        #[doc = "Field `TSU_TBIN3_SEL` writer - No description avaiable"]
        pub type TSU_TBIN3_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 8:13 - No description avaiable"]
            #[inline(always)]
            pub fn tsu_tbin0_sel(&self) -> TSU_TBIN0_SEL_R {
                TSU_TBIN0_SEL_R::new(((self.bits >> 8) & 0x3f) as u8)
            }
            #[doc = "Bits 14:19 - No description avaiable"]
            #[inline(always)]
            pub fn tsu_tbin1_sel(&self) -> TSU_TBIN1_SEL_R {
                TSU_TBIN1_SEL_R::new(((self.bits >> 14) & 0x3f) as u8)
            }
            #[doc = "Bits 20:25 - No description avaiable"]
            #[inline(always)]
            pub fn tsu_tbin2_sel(&self) -> TSU_TBIN2_SEL_R {
                TSU_TBIN2_SEL_R::new(((self.bits >> 20) & 0x3f) as u8)
            }
            #[doc = "Bits 26:31 - No description avaiable"]
            #[inline(always)]
            pub fn tsu_tbin3_sel(&self) -> TSU_TBIN3_SEL_R {
                TSU_TBIN3_SEL_R::new(((self.bits >> 26) & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 8:13 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn tsu_tbin0_sel(&mut self) -> TSU_TBIN0_SEL_W<PTPC_CAN_TS_SEL_SPEC> {
                TSU_TBIN0_SEL_W::new(self, 8)
            }
            #[doc = "Bits 14:19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn tsu_tbin1_sel(&mut self) -> TSU_TBIN1_SEL_W<PTPC_CAN_TS_SEL_SPEC> {
                TSU_TBIN1_SEL_W::new(self, 14)
            }
            #[doc = "Bits 20:25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn tsu_tbin2_sel(&mut self) -> TSU_TBIN2_SEL_W<PTPC_CAN_TS_SEL_SPEC> {
                TSU_TBIN2_SEL_W::new(self, 20)
            }
            #[doc = "Bits 26:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn tsu_tbin3_sel(&mut self) -> TSU_TBIN3_SEL_W<PTPC_CAN_TS_SEL_SPEC> {
                TSU_TBIN3_SEL_W::new(self, 26)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ptpc_can_ts_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ptpc_can_ts_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PTPC_CAN_TS_SEL_SPEC;
        impl crate::RegisterSpec for PTPC_CAN_TS_SEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ptpc_can_ts_sel::R`](R) reader structure"]
        impl crate::Readable for PTPC_CAN_TS_SEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ptpc_can_ts_sel::W`](W) writer structure"]
        impl crate::Writable for PTPC_CAN_TS_SEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ptpc_can_ts_sel to value 0"]
        impl crate::Resettable for PTPC_CAN_TS_SEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "QEI0"]
pub struct QEI0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for QEI0 {}
impl QEI0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const qei0::RegisterBlock = 0xf030_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const qei0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for QEI0 {
    type Target = qei0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for QEI0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("QEI0").finish()
    }
}
#[doc = "QEI0"]
pub mod qei0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        cr: CR,
        phcfg: PHCFG,
        wdgcfg: WDGCFG,
        phidx: PHIDX,
        trgoen: TRGOEN,
        readen: READEN,
        zcmp: ZCMP,
        phcmp: PHCMP,
        spdcmp: SPDCMP,
        dmaen: DMAEN,
        sr: SR,
        irqen: IRQEN,
        count: [COUNT; 4],
        _reserved13: [u8; 0x10],
        zcmp2: ZCMP2,
        phcmp2: PHCMP2,
        spdcmp2: SPDCMP2,
        match_cfg: MATCH_CFG,
        filt_cfg: [FILT_CFG; 6],
        _reserved18: [u8; 0x58],
        qei_cfg: QEI_CFG,
        _reserved19: [u8; 0x0c],
        pulse0_num: PULSE0_NUM,
        pulse1_num: PULSE1_NUM,
        cycle0_cnt: CYCLE0_CNT,
        cycle0pulse_cnt: CYCLE0PULSE_CNT,
        cycle1_cnt: CYCLE1_CNT,
        cycle1pulse_cnt: CYCLE1PULSE_CNT,
        cycle0_snap0: CYCLE0_SNAP0,
        cycle0_snap1: CYCLE0_SNAP1,
        cycle1_snap0: CYCLE1_SNAP0,
        cycle1_snap1: CYCLE1_SNAP1,
        _reserved29: [u8; 0x08],
        cycle0_num: CYCLE0_NUM,
        cycle1_num: CYCLE1_NUM,
        pulse0_cnt: PULSE0_CNT,
        pulse0cycle_cnt: PULSE0CYCLE_CNT,
        pulse1_cnt: PULSE1_CNT,
        pulse1cycle_cnt: PULSE1CYCLE_CNT,
        pulse0_snap0: PULSE0_SNAP0,
        pulse0cycle_snap0: PULSE0CYCLE_SNAP0,
        pulse0_snap1: PULSE0_SNAP1,
        pulse0cycle_snap1: PULSE0CYCLE_SNAP1,
        pulse1_snap0: PULSE1_SNAP0,
        pulse1cycle_snap0: PULSE1CYCLE_SNAP0,
        pulse1_snap1: PULSE1_SNAP1,
        pulse1cycle_snap1: PULSE1CYCLE_SNAP1,
        _reserved43: [u8; 0x88],
        adcx_cfg0: ADCX_CFG0,
        adcx_cfg1: ADCX_CFG1,
        adcx_cfg2: ADCX_CFG2,
        _reserved46: [u8; 0x04],
        adcy_cfg0: ADCY_CFG0,
        adcy_cfg1: ADCY_CFG1,
        adcy_cfg2: ADCY_CFG2,
        _reserved49: [u8; 0x04],
        cal_cfg: CAL_CFG,
        _reserved50: [u8; 0x0c],
        phase_param: PHASE_PARAM,
        angle_adj: ANGLE_ADJ,
        pos_threshold: POS_THRESHOLD,
        _reserved53: [u8; 0x04],
        uvw_pos: [UVW_POS; 6],
        uvw_pos_cfg: [UVW_POS_CFG; 6],
        _reserved55: [u8; 0x10],
        phase_cnt: PHASE_CNT,
        phase_update: PHASE_UPDATE,
        position: POSITION,
        position_update: POSITION_UPDATE,
        angle: ANGLE,
        pos_timeout: POS_TIMEOUT,
    }
    impl RegisterBlock {
        #[doc = "0x00 - Control register"]
        #[inline(always)]
        pub const fn cr(&self) -> &CR {
            &self.cr
        }
        #[doc = "0x04 - Phase configure register"]
        #[inline(always)]
        pub const fn phcfg(&self) -> &PHCFG {
            &self.phcfg
        }
        #[doc = "0x08 - Watchdog configure register"]
        #[inline(always)]
        pub const fn wdgcfg(&self) -> &WDGCFG {
            &self.wdgcfg
        }
        #[doc = "0x0c - Phase index register"]
        #[inline(always)]
        pub const fn phidx(&self) -> &PHIDX {
            &self.phidx
        }
        #[doc = "0x10 - Tigger output enable register"]
        #[inline(always)]
        pub const fn trgoen(&self) -> &TRGOEN {
            &self.trgoen
        }
        #[doc = "0x14 - Read event enable register"]
        #[inline(always)]
        pub const fn readen(&self) -> &READEN {
            &self.readen
        }
        #[doc = "0x18 - Z comparator"]
        #[inline(always)]
        pub const fn zcmp(&self) -> &ZCMP {
            &self.zcmp
        }
        #[doc = "0x1c - Phase comparator"]
        #[inline(always)]
        pub const fn phcmp(&self) -> &PHCMP {
            &self.phcmp
        }
        #[doc = "0x20 - Speed comparator"]
        #[inline(always)]
        pub const fn spdcmp(&self) -> &SPDCMP {
            &self.spdcmp
        }
        #[doc = "0x24 - DMA request enable register"]
        #[inline(always)]
        pub const fn dmaen(&self) -> &DMAEN {
            &self.dmaen
        }
        #[doc = "0x28 - Status register"]
        #[inline(always)]
        pub const fn sr(&self) -> &SR {
            &self.sr
        }
        #[doc = "0x2c - Interrupt request register"]
        #[inline(always)]
        pub const fn irqen(&self) -> &IRQEN {
            &self.irqen
        }
        #[doc = "0x30..0x70 - no description available"]
        #[inline(always)]
        pub const fn count(&self, n: usize) -> &COUNT {
            &self.count[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x30..0x70 - no description available"]
        #[inline(always)]
        pub fn count_iter(&self) -> impl Iterator<Item = &COUNT> {
            self.count.iter()
        }
        #[doc = "0x30..0x40 - no description available"]
        #[inline(always)]
        pub const fn countcurrent(&self) -> &COUNT {
            self.count(0)
        }
        #[doc = "0x40..0x50 - no description available"]
        #[inline(always)]
        pub const fn countread(&self) -> &COUNT {
            self.count(1)
        }
        #[doc = "0x50..0x60 - no description available"]
        #[inline(always)]
        pub const fn countsnap0(&self) -> &COUNT {
            self.count(2)
        }
        #[doc = "0x60..0x70 - no description available"]
        #[inline(always)]
        pub const fn countsnap1(&self) -> &COUNT {
            self.count(3)
        }
        #[doc = "0x80 - Z comparator"]
        #[inline(always)]
        pub const fn zcmp2(&self) -> &ZCMP2 {
            &self.zcmp2
        }
        #[doc = "0x84 - Phase comparator"]
        #[inline(always)]
        pub const fn phcmp2(&self) -> &PHCMP2 {
            &self.phcmp2
        }
        #[doc = "0x88 - Speed comparator"]
        #[inline(always)]
        pub const fn spdcmp2(&self) -> &SPDCMP2 {
            &self.spdcmp2
        }
        #[doc = "0x8c - No description avaiable"]
        #[inline(always)]
        pub const fn match_cfg(&self) -> &MATCH_CFG {
            &self.match_cfg
        }
        #[doc = "0x90..0xa8 - no description available"]
        #[inline(always)]
        pub const fn filt_cfg(&self, n: usize) -> &FILT_CFG {
            &self.filt_cfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x90..0xa8 - no description available"]
        #[inline(always)]
        pub fn filt_cfg_iter(&self) -> impl Iterator<Item = &FILT_CFG> {
            self.filt_cfg.iter()
        }
        #[doc = "0x90 - no description available"]
        #[inline(always)]
        pub const fn filt_cfgfilt_cfg_a(&self) -> &FILT_CFG {
            self.filt_cfg(0)
        }
        #[doc = "0x94 - no description available"]
        #[inline(always)]
        pub const fn filt_cfgfilt_cfg_b(&self) -> &FILT_CFG {
            self.filt_cfg(1)
        }
        #[doc = "0x98 - no description available"]
        #[inline(always)]
        pub const fn filt_cfgfilt_cfg_z(&self) -> &FILT_CFG {
            self.filt_cfg(2)
        }
        #[doc = "0x9c - no description available"]
        #[inline(always)]
        pub const fn filt_cfgfilt_cfg_h(&self) -> &FILT_CFG {
            self.filt_cfg(3)
        }
        #[doc = "0xa0 - no description available"]
        #[inline(always)]
        pub const fn filt_cfgfilt_cfg_h2(&self) -> &FILT_CFG {
            self.filt_cfg(4)
        }
        #[doc = "0xa4 - no description available"]
        #[inline(always)]
        pub const fn filt_cfgfilt_cfg_f(&self) -> &FILT_CFG {
            self.filt_cfg(5)
        }
        #[doc = "0x100 - qei config register"]
        #[inline(always)]
        pub const fn qei_cfg(&self) -> &QEI_CFG {
            &self.qei_cfg
        }
        #[doc = "0x110 - pulse0_num"]
        #[inline(always)]
        pub const fn pulse0_num(&self) -> &PULSE0_NUM {
            &self.pulse0_num
        }
        #[doc = "0x114 - pulse1_num"]
        #[inline(always)]
        pub const fn pulse1_num(&self) -> &PULSE1_NUM {
            &self.pulse1_num
        }
        #[doc = "0x118 - cycle0_cnt"]
        #[inline(always)]
        pub const fn cycle0_cnt(&self) -> &CYCLE0_CNT {
            &self.cycle0_cnt
        }
        #[doc = "0x11c - cycle0pulse_cnt"]
        #[inline(always)]
        pub const fn cycle0pulse_cnt(&self) -> &CYCLE0PULSE_CNT {
            &self.cycle0pulse_cnt
        }
        #[doc = "0x120 - cycle1_cnt"]
        #[inline(always)]
        pub const fn cycle1_cnt(&self) -> &CYCLE1_CNT {
            &self.cycle1_cnt
        }
        #[doc = "0x124 - cycle1pulse_cnt"]
        #[inline(always)]
        pub const fn cycle1pulse_cnt(&self) -> &CYCLE1PULSE_CNT {
            &self.cycle1pulse_cnt
        }
        #[doc = "0x128 - cycle0_snap0"]
        #[inline(always)]
        pub const fn cycle0_snap0(&self) -> &CYCLE0_SNAP0 {
            &self.cycle0_snap0
        }
        #[doc = "0x12c - cycle0_snap1"]
        #[inline(always)]
        pub const fn cycle0_snap1(&self) -> &CYCLE0_SNAP1 {
            &self.cycle0_snap1
        }
        #[doc = "0x130 - cycle1_snap0"]
        #[inline(always)]
        pub const fn cycle1_snap0(&self) -> &CYCLE1_SNAP0 {
            &self.cycle1_snap0
        }
        #[doc = "0x134 - cycle1_snap1"]
        #[inline(always)]
        pub const fn cycle1_snap1(&self) -> &CYCLE1_SNAP1 {
            &self.cycle1_snap1
        }
        #[doc = "0x140 - cycle0_num"]
        #[inline(always)]
        pub const fn cycle0_num(&self) -> &CYCLE0_NUM {
            &self.cycle0_num
        }
        #[doc = "0x144 - cycle1_num"]
        #[inline(always)]
        pub const fn cycle1_num(&self) -> &CYCLE1_NUM {
            &self.cycle1_num
        }
        #[doc = "0x148 - pulse0_cnt"]
        #[inline(always)]
        pub const fn pulse0_cnt(&self) -> &PULSE0_CNT {
            &self.pulse0_cnt
        }
        #[doc = "0x14c - pulse0cycle_cnt"]
        #[inline(always)]
        pub const fn pulse0cycle_cnt(&self) -> &PULSE0CYCLE_CNT {
            &self.pulse0cycle_cnt
        }
        #[doc = "0x150 - pulse1_cnt"]
        #[inline(always)]
        pub const fn pulse1_cnt(&self) -> &PULSE1_CNT {
            &self.pulse1_cnt
        }
        #[doc = "0x154 - pulse1cycle_cnt"]
        #[inline(always)]
        pub const fn pulse1cycle_cnt(&self) -> &PULSE1CYCLE_CNT {
            &self.pulse1cycle_cnt
        }
        #[doc = "0x158 - pulse0_snap0"]
        #[inline(always)]
        pub const fn pulse0_snap0(&self) -> &PULSE0_SNAP0 {
            &self.pulse0_snap0
        }
        #[doc = "0x15c - pulse0cycle_snap0"]
        #[inline(always)]
        pub const fn pulse0cycle_snap0(&self) -> &PULSE0CYCLE_SNAP0 {
            &self.pulse0cycle_snap0
        }
        #[doc = "0x160 - pulse0_snap1"]
        #[inline(always)]
        pub const fn pulse0_snap1(&self) -> &PULSE0_SNAP1 {
            &self.pulse0_snap1
        }
        #[doc = "0x164 - pulse0cycle_snap1"]
        #[inline(always)]
        pub const fn pulse0cycle_snap1(&self) -> &PULSE0CYCLE_SNAP1 {
            &self.pulse0cycle_snap1
        }
        #[doc = "0x168 - pulse1_snap0"]
        #[inline(always)]
        pub const fn pulse1_snap0(&self) -> &PULSE1_SNAP0 {
            &self.pulse1_snap0
        }
        #[doc = "0x16c - pulse1cycle_snap0"]
        #[inline(always)]
        pub const fn pulse1cycle_snap0(&self) -> &PULSE1CYCLE_SNAP0 {
            &self.pulse1cycle_snap0
        }
        #[doc = "0x170 - pulse1_snap1"]
        #[inline(always)]
        pub const fn pulse1_snap1(&self) -> &PULSE1_SNAP1 {
            &self.pulse1_snap1
        }
        #[doc = "0x174 - pulse1cycle_snap1"]
        #[inline(always)]
        pub const fn pulse1cycle_snap1(&self) -> &PULSE1CYCLE_SNAP1 {
            &self.pulse1cycle_snap1
        }
        #[doc = "0x200 - adcx_cfg0"]
        #[inline(always)]
        pub const fn adcx_cfg0(&self) -> &ADCX_CFG0 {
            &self.adcx_cfg0
        }
        #[doc = "0x204 - adcx_cfg1"]
        #[inline(always)]
        pub const fn adcx_cfg1(&self) -> &ADCX_CFG1 {
            &self.adcx_cfg1
        }
        #[doc = "0x208 - adcx_cfg2"]
        #[inline(always)]
        pub const fn adcx_cfg2(&self) -> &ADCX_CFG2 {
            &self.adcx_cfg2
        }
        #[doc = "0x210 - adcy_cfg0"]
        #[inline(always)]
        pub const fn adcy_cfg0(&self) -> &ADCY_CFG0 {
            &self.adcy_cfg0
        }
        #[doc = "0x214 - adcy_cfg1"]
        #[inline(always)]
        pub const fn adcy_cfg1(&self) -> &ADCY_CFG1 {
            &self.adcy_cfg1
        }
        #[doc = "0x218 - adcy_cfg2"]
        #[inline(always)]
        pub const fn adcy_cfg2(&self) -> &ADCY_CFG2 {
            &self.adcy_cfg2
        }
        #[doc = "0x220 - cal_cfg"]
        #[inline(always)]
        pub const fn cal_cfg(&self) -> &CAL_CFG {
            &self.cal_cfg
        }
        #[doc = "0x230 - phase_param"]
        #[inline(always)]
        pub const fn phase_param(&self) -> &PHASE_PARAM {
            &self.phase_param
        }
        #[doc = "0x234 - angle_adj"]
        #[inline(always)]
        pub const fn angle_adj(&self) -> &ANGLE_ADJ {
            &self.angle_adj
        }
        #[doc = "0x238 - pos_threshold"]
        #[inline(always)]
        pub const fn pos_threshold(&self) -> &POS_THRESHOLD {
            &self.pos_threshold
        }
        #[doc = "0x240..0x258 - no description available"]
        #[inline(always)]
        pub const fn uvw_pos(&self, n: usize) -> &UVW_POS {
            &self.uvw_pos[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x240..0x258 - no description available"]
        #[inline(always)]
        pub fn uvw_pos_iter(&self) -> impl Iterator<Item = &UVW_POS> {
            self.uvw_pos.iter()
        }
        #[doc = "0x240 - no description available"]
        #[inline(always)]
        pub const fn uvw_posuvw_pos0(&self) -> &UVW_POS {
            self.uvw_pos(0)
        }
        #[doc = "0x244 - no description available"]
        #[inline(always)]
        pub const fn uvw_posuvw_pos1(&self) -> &UVW_POS {
            self.uvw_pos(1)
        }
        #[doc = "0x248 - no description available"]
        #[inline(always)]
        pub const fn uvw_posuvw_pos2(&self) -> &UVW_POS {
            self.uvw_pos(2)
        }
        #[doc = "0x24c - no description available"]
        #[inline(always)]
        pub const fn uvw_posuvw_pos3(&self) -> &UVW_POS {
            self.uvw_pos(3)
        }
        #[doc = "0x250 - no description available"]
        #[inline(always)]
        pub const fn uvw_posuvw_pos4(&self) -> &UVW_POS {
            self.uvw_pos(4)
        }
        #[doc = "0x254 - no description available"]
        #[inline(always)]
        pub const fn uvw_posuvw_pos5(&self) -> &UVW_POS {
            self.uvw_pos(5)
        }
        #[doc = "0x258..0x270 - no description available"]
        #[inline(always)]
        pub const fn uvw_pos_cfg(&self, n: usize) -> &UVW_POS_CFG {
            &self.uvw_pos_cfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x258..0x270 - no description available"]
        #[inline(always)]
        pub fn uvw_pos_cfg_iter(&self) -> impl Iterator<Item = &UVW_POS_CFG> {
            self.uvw_pos_cfg.iter()
        }
        #[doc = "0x258 - no description available"]
        #[inline(always)]
        pub const fn uvw_pos_cfguvw_pos0_cfg(&self) -> &UVW_POS_CFG {
            self.uvw_pos_cfg(0)
        }
        #[doc = "0x25c - no description available"]
        #[inline(always)]
        pub const fn uvw_pos_cfguvw_pos1_cfg(&self) -> &UVW_POS_CFG {
            self.uvw_pos_cfg(1)
        }
        #[doc = "0x260 - no description available"]
        #[inline(always)]
        pub const fn uvw_pos_cfguvw_pos2_cfg(&self) -> &UVW_POS_CFG {
            self.uvw_pos_cfg(2)
        }
        #[doc = "0x264 - no description available"]
        #[inline(always)]
        pub const fn uvw_pos_cfguvw_pos3_cfg(&self) -> &UVW_POS_CFG {
            self.uvw_pos_cfg(3)
        }
        #[doc = "0x268 - no description available"]
        #[inline(always)]
        pub const fn uvw_pos_cfguvw_pos4_cfg(&self) -> &UVW_POS_CFG {
            self.uvw_pos_cfg(4)
        }
        #[doc = "0x26c - no description available"]
        #[inline(always)]
        pub const fn uvw_pos_cfguvw_pos5_cfg(&self) -> &UVW_POS_CFG {
            self.uvw_pos_cfg(5)
        }
        #[doc = "0x280 - phase_cnt"]
        #[inline(always)]
        pub const fn phase_cnt(&self) -> &PHASE_CNT {
            &self.phase_cnt
        }
        #[doc = "0x284 - phase_update"]
        #[inline(always)]
        pub const fn phase_update(&self) -> &PHASE_UPDATE {
            &self.phase_update
        }
        #[doc = "0x288 - position"]
        #[inline(always)]
        pub const fn position(&self) -> &POSITION {
            &self.position
        }
        #[doc = "0x28c - position_update"]
        #[inline(always)]
        pub const fn position_update(&self) -> &POSITION_UPDATE {
            &self.position_update
        }
        #[doc = "0x290 - No description avaiable"]
        #[inline(always)]
        pub const fn angle(&self) -> &ANGLE {
            &self.angle
        }
        #[doc = "0x294 - pos_timeout"]
        #[inline(always)]
        pub const fn pos_timeout(&self) -> &POS_TIMEOUT {
            &self.pos_timeout
        }
    }
    #[doc = "cr (rw) register accessor: Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
    pub type CR = crate::Reg<cr::CR_SPEC>;
    #[doc = "Control register"]
    pub mod cr {
        #[doc = "Register `cr` reader"]
        pub type R = crate::R<CR_SPEC>;
        #[doc = "Register `cr` writer"]
        pub type W = crate::W<CR_SPEC>;
        #[doc = "Field `ENCTYP` reader - 000-abz; 001-pd; 010-ud; 011-UVW(hal) 100-single A; 101-single sin; 110: sin&amp;cos"]
        pub type ENCTYP_R = crate::FieldReader;
        #[doc = "Field `ENCTYP` writer - 000-abz; 001-pd; 010-ud; 011-UVW(hal) 100-single A; 101-single sin; 110: sin&amp;cos"]
        pub type ENCTYP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `RD_SEL` reader - define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1) 0 : same as hpm1000/500/500s; 1: use width for position; use timer for angle"]
        pub type RD_SEL_R = crate::BitReader;
        #[doc = "Field `RD_SEL` writer - define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1) 0 : same as hpm1000/500/500s; 1: use width for position; use timer for angle"]
        pub type RD_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RSTCNT` reader - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx"]
        pub type RSTCNT_R = crate::BitReader;
        #[doc = "Field `RSTCNT` writer - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx"]
        pub type RSTCNT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SNAPEN` reader - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert"]
        pub type SNAPEN_R = crate::BitReader;
        #[doc = "Field `SNAPEN` writer - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert"]
        pub type SNAPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTPOS` reader - No description avaiable"]
        pub type FAULTPOS_R = crate::BitReader;
        #[doc = "Field `FAULTPOS` writer - No description avaiable"]
        pub type FAULTPOS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HRDIR1` reader - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)"]
        pub type HRDIR1_R = crate::BitReader;
        #[doc = "Field `HRDIR1` writer - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)"]
        pub type HRDIR1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HRDIR0` reader - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)"]
        pub type HRDIR0_R = crate::BitReader;
        #[doc = "Field `HRDIR0` writer - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)"]
        pub type HRDIR0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HFDIR1` reader - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)"]
        pub type HFDIR1_R = crate::BitReader;
        #[doc = "Field `HFDIR1` writer - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)"]
        pub type HFDIR1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HFDIR0` reader - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)"]
        pub type HFDIR0_R = crate::BitReader;
        #[doc = "Field `HFDIR0` writer - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)"]
        pub type HFDIR0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PAUSEZ` reader - 1- pause zcnt when PAUSE assert"]
        pub type PAUSEZ_R = crate::BitReader;
        #[doc = "Field `PAUSEZ` writer - 1- pause zcnt when PAUSE assert"]
        pub type PAUSEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PAUSEPH` reader - 1- pause phcnt when PAUSE assert"]
        pub type PAUSEPH_R = crate::BitReader;
        #[doc = "Field `PAUSEPH` writer - 1- pause phcnt when PAUSE assert"]
        pub type PAUSEPH_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PAUSESPD` reader - 1- pause spdcnt when PAUSE assert"]
        pub type PAUSESPD_R = crate::BitReader;
        #[doc = "Field `PAUSESPD` writer - 1- pause spdcnt when PAUSE assert"]
        pub type PAUSESPD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PAUSEPOS` reader - 1- pause position output valid when PAUSE assert"]
        pub type PAUSEPOS_R = crate::BitReader;
        #[doc = "Field `PAUSEPOS` writer - 1- pause position output valid when PAUSE assert"]
        pub type PAUSEPOS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `H2RDIR1` reader - No description avaiable"]
        pub type H2RDIR1_R = crate::BitReader;
        #[doc = "Field `H2RDIR1` writer - No description avaiable"]
        pub type H2RDIR1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `H2RDIR0` reader - No description avaiable"]
        pub type H2RDIR0_R = crate::BitReader;
        #[doc = "Field `H2RDIR0` writer - No description avaiable"]
        pub type H2RDIR0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `H2FDIR1` reader - No description avaiable"]
        pub type H2FDIR1_R = crate::BitReader;
        #[doc = "Field `H2FDIR1` writer - No description avaiable"]
        pub type H2FDIR1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `H2FDIR0` reader - No description avaiable"]
        pub type H2FDIR0_R = crate::BitReader;
        #[doc = "Field `H2FDIR0` writer - No description avaiable"]
        pub type H2FDIR0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `Z_ONLY_EN` reader - 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz)"]
        pub type Z_ONLY_EN_R = crate::BitReader;
        #[doc = "Field `Z_ONLY_EN` writer - 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz)"]
        pub type Z_ONLY_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHCALIZ` reader - 1- phcnt will set to phidx when Z input assert(for abz digital signsl)"]
        pub type PHCALIZ_R = crate::BitReader;
        #[doc = "Field `PHCALIZ` writer - 1- phcnt will set to phidx when Z input assert(for abz digital signsl)"]
        pub type PHCALIZ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZCNTCFG` reader - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 0- zcnt will increment or decrement when Z input assert"]
        pub type ZCNTCFG_R = crate::BitReader;
        #[doc = "Field `ZCNTCFG` writer - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 0- zcnt will increment or decrement when Z input assert"]
        pub type ZCNTCFG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `READ` writer - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0"]
        pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:2 - 000-abz; 001-pd; 010-ud; 011-UVW(hal) 100-single A; 101-single sin; 110: sin&amp;cos"]
            #[inline(always)]
            pub fn enctyp(&self) -> ENCTYP_R {
                ENCTYP_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 3 - define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1) 0 : same as hpm1000/500/500s; 1: use width for position; use timer for angle"]
            #[inline(always)]
            pub fn rd_sel(&self) -> RD_SEL_R {
                RD_SEL_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx"]
            #[inline(always)]
            pub fn rstcnt(&self) -> RSTCNT_R {
                RSTCNT_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert"]
            #[inline(always)]
            pub fn snapen(&self) -> SNAPEN_R {
                SNAPEN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - No description avaiable"]
            #[inline(always)]
            pub fn faultpos(&self) -> FAULTPOS_R {
                FAULTPOS_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 8 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)"]
            #[inline(always)]
            pub fn hrdir1(&self) -> HRDIR1_R {
                HRDIR1_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)"]
            #[inline(always)]
            pub fn hrdir0(&self) -> HRDIR0_R {
                HRDIR0_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)"]
            #[inline(always)]
            pub fn hfdir1(&self) -> HFDIR1_R {
                HFDIR1_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)"]
            #[inline(always)]
            pub fn hfdir0(&self) -> HFDIR0_R {
                HFDIR0_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - 1- pause zcnt when PAUSE assert"]
            #[inline(always)]
            pub fn pausez(&self) -> PAUSEZ_R {
                PAUSEZ_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - 1- pause phcnt when PAUSE assert"]
            #[inline(always)]
            pub fn pauseph(&self) -> PAUSEPH_R {
                PAUSEPH_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - 1- pause spdcnt when PAUSE assert"]
            #[inline(always)]
            pub fn pausespd(&self) -> PAUSESPD_R {
                PAUSESPD_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - 1- pause position output valid when PAUSE assert"]
            #[inline(always)]
            pub fn pausepos(&self) -> PAUSEPOS_R {
                PAUSEPOS_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - No description avaiable"]
            #[inline(always)]
            pub fn h2rdir1(&self) -> H2RDIR1_R {
                H2RDIR1_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - No description avaiable"]
            #[inline(always)]
            pub fn h2rdir0(&self) -> H2RDIR0_R {
                H2RDIR0_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            pub fn h2fdir1(&self) -> H2FDIR1_R {
                H2FDIR1_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            pub fn h2fdir0(&self) -> H2FDIR0_R {
                H2FDIR0_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz)"]
            #[inline(always)]
            pub fn z_only_en(&self) -> Z_ONLY_EN_R {
                Z_ONLY_EN_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - 1- phcnt will set to phidx when Z input assert(for abz digital signsl)"]
            #[inline(always)]
            pub fn phcaliz(&self) -> PHCALIZ_R {
                PHCALIZ_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 0- zcnt will increment or decrement when Z input assert"]
            #[inline(always)]
            pub fn zcntcfg(&self) -> ZCNTCFG_R {
                ZCNTCFG_R::new(((self.bits >> 22) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - 000-abz; 001-pd; 010-ud; 011-UVW(hal) 100-single A; 101-single sin; 110: sin&amp;cos"]
            #[inline(always)]
            #[must_use]
            pub fn enctyp(&mut self) -> ENCTYP_W<CR_SPEC> {
                ENCTYP_W::new(self, 0)
            }
            #[doc = "Bit 3 - define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, width_snap0,width_snap1, timer_snap0, timer_snap1) 0 : same as hpm1000/500/500s; 1: use width for position; use timer for angle"]
            #[inline(always)]
            #[must_use]
            pub fn rd_sel(&mut self) -> RD_SEL_W<CR_SPEC> {
                RD_SEL_W::new(self, 3)
            }
            #[doc = "Bit 4 - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx"]
            #[inline(always)]
            #[must_use]
            pub fn rstcnt(&mut self) -> RSTCNT_W<CR_SPEC> {
                RSTCNT_W::new(self, 4)
            }
            #[doc = "Bit 5 - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert"]
            #[inline(always)]
            #[must_use]
            pub fn snapen(&mut self) -> SNAPEN_W<CR_SPEC> {
                SNAPEN_W::new(self, 5)
            }
            #[doc = "Bit 6 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn faultpos(&mut self) -> FAULTPOS_W<CR_SPEC> {
                FAULTPOS_W::new(self, 6)
            }
            #[doc = "Bit 8 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)"]
            #[inline(always)]
            #[must_use]
            pub fn hrdir1(&mut self) -> HRDIR1_W<CR_SPEC> {
                HRDIR1_W::new(self, 8)
            }
            #[doc = "Bit 9 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)"]
            #[inline(always)]
            #[must_use]
            pub fn hrdir0(&mut self) -> HRDIR0_W<CR_SPEC> {
                HRDIR0_W::new(self, 9)
            }
            #[doc = "Bit 10 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)"]
            #[inline(always)]
            #[must_use]
            pub fn hfdir1(&mut self) -> HFDIR1_W<CR_SPEC> {
                HFDIR1_W::new(self, 10)
            }
            #[doc = "Bit 11 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)"]
            #[inline(always)]
            #[must_use]
            pub fn hfdir0(&mut self) -> HFDIR0_W<CR_SPEC> {
                HFDIR0_W::new(self, 11)
            }
            #[doc = "Bit 12 - 1- pause zcnt when PAUSE assert"]
            #[inline(always)]
            #[must_use]
            pub fn pausez(&mut self) -> PAUSEZ_W<CR_SPEC> {
                PAUSEZ_W::new(self, 12)
            }
            #[doc = "Bit 13 - 1- pause phcnt when PAUSE assert"]
            #[inline(always)]
            #[must_use]
            pub fn pauseph(&mut self) -> PAUSEPH_W<CR_SPEC> {
                PAUSEPH_W::new(self, 13)
            }
            #[doc = "Bit 14 - 1- pause spdcnt when PAUSE assert"]
            #[inline(always)]
            #[must_use]
            pub fn pausespd(&mut self) -> PAUSESPD_W<CR_SPEC> {
                PAUSESPD_W::new(self, 14)
            }
            #[doc = "Bit 15 - 1- pause position output valid when PAUSE assert"]
            #[inline(always)]
            #[must_use]
            pub fn pausepos(&mut self) -> PAUSEPOS_W<CR_SPEC> {
                PAUSEPOS_W::new(self, 15)
            }
            #[doc = "Bit 16 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn h2rdir1(&mut self) -> H2RDIR1_W<CR_SPEC> {
                H2RDIR1_W::new(self, 16)
            }
            #[doc = "Bit 17 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn h2rdir0(&mut self) -> H2RDIR0_W<CR_SPEC> {
                H2RDIR0_W::new(self, 17)
            }
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn h2fdir1(&mut self) -> H2FDIR1_W<CR_SPEC> {
                H2FDIR1_W::new(self, 18)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn h2fdir0(&mut self) -> H2FDIR0_W<CR_SPEC> {
                H2FDIR0_W::new(self, 19)
            }
            #[doc = "Bit 20 - 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz)"]
            #[inline(always)]
            #[must_use]
            pub fn z_only_en(&mut self) -> Z_ONLY_EN_W<CR_SPEC> {
                Z_ONLY_EN_W::new(self, 20)
            }
            #[doc = "Bit 21 - 1- phcnt will set to phidx when Z input assert(for abz digital signsl)"]
            #[inline(always)]
            #[must_use]
            pub fn phcaliz(&mut self) -> PHCALIZ_W<CR_SPEC> {
                PHCALIZ_W::new(self, 21)
            }
            #[doc = "Bit 22 - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 0- zcnt will increment or decrement when Z input assert"]
            #[inline(always)]
            #[must_use]
            pub fn zcntcfg(&mut self) -> ZCNTCFG_W<CR_SPEC> {
                ZCNTCFG_W::new(self, 22)
            }
            #[doc = "Bit 31 - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0"]
            #[inline(always)]
            #[must_use]
            pub fn read(&mut self) -> READ_W<CR_SPEC> {
                READ_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CR_SPEC;
        impl crate::RegisterSpec for CR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cr::R`](R) reader structure"]
        impl crate::Readable for CR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
        impl crate::Writable for CR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cr to value 0"]
        impl crate::Resettable for CR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "phcfg (rw) register accessor: Phase configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phcfg`]
module"]
    pub type PHCFG = crate::Reg<phcfg::PHCFG_SPEC>;
    #[doc = "Phase configure register"]
    pub mod phcfg {
        #[doc = "Register `phcfg` reader"]
        pub type R = crate::R<PHCFG_SPEC>;
        #[doc = "Register `phcfg` writer"]
        pub type W = crate::W<PHCFG_SPEC>;
        #[doc = "Field `PHMAX` reader - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax"]
        pub type PHMAX_R = crate::FieldReader<u32>;
        #[doc = "Field `PHMAX` writer - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax"]
        pub type PHMAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax"]
            #[inline(always)]
            pub fn phmax(&self) -> PHMAX_R {
                PHMAX_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax"]
            #[inline(always)]
            #[must_use]
            pub fn phmax(&mut self) -> PHMAX_W<PHCFG_SPEC> {
                PHMAX_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Phase configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHCFG_SPEC;
        impl crate::RegisterSpec for PHCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phcfg::R`](R) reader structure"]
        impl crate::Readable for PHCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phcfg::W`](W) writer structure"]
        impl crate::Writable for PHCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets phcfg to value 0"]
        impl crate::Resettable for PHCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "wdgcfg (rw) register accessor: Watchdog configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdgcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdgcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdgcfg`]
module"]
    pub type WDGCFG = crate::Reg<wdgcfg::WDGCFG_SPEC>;
    #[doc = "Watchdog configure register"]
    pub mod wdgcfg {
        #[doc = "Register `wdgcfg` reader"]
        pub type R = crate::R<WDGCFG_SPEC>;
        #[doc = "Register `wdgcfg` writer"]
        pub type W = crate::W<WDGCFG_SPEC>;
        #[doc = "Field `WDGTO` reader - watch dog timeout value"]
        pub type WDGTO_R = crate::FieldReader<u32>;
        #[doc = "Field `WDGTO` writer - watch dog timeout value"]
        pub type WDGTO_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>;
        #[doc = "Field `WDOG_CFG` reader - define as stop if phase_cnt change is less than it if 0, then each change of phase_cnt will clear wdog counter; if 2, then phase_cnt change larger than 2 will clear wdog counter"]
        pub type WDOG_CFG_R = crate::FieldReader;
        #[doc = "Field `WDOG_CFG` writer - define as stop if phase_cnt change is less than it if 0, then each change of phase_cnt will clear wdog counter; if 2, then phase_cnt change larger than 2 will clear wdog counter"]
        pub type WDOG_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `WDGEN` reader - 1- enable wdog counter"]
        pub type WDGEN_R = crate::BitReader;
        #[doc = "Field `WDGEN` writer - 1- enable wdog counter"]
        pub type WDGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:27 - watch dog timeout value"]
            #[inline(always)]
            pub fn wdgto(&self) -> WDGTO_R {
                WDGTO_R::new(self.bits & 0x0fff_ffff)
            }
            #[doc = "Bits 28:30 - define as stop if phase_cnt change is less than it if 0, then each change of phase_cnt will clear wdog counter; if 2, then phase_cnt change larger than 2 will clear wdog counter"]
            #[inline(always)]
            pub fn wdog_cfg(&self) -> WDOG_CFG_R {
                WDOG_CFG_R::new(((self.bits >> 28) & 7) as u8)
            }
            #[doc = "Bit 31 - 1- enable wdog counter"]
            #[inline(always)]
            pub fn wdgen(&self) -> WDGEN_R {
                WDGEN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:27 - watch dog timeout value"]
            #[inline(always)]
            #[must_use]
            pub fn wdgto(&mut self) -> WDGTO_W<WDGCFG_SPEC> {
                WDGTO_W::new(self, 0)
            }
            #[doc = "Bits 28:30 - define as stop if phase_cnt change is less than it if 0, then each change of phase_cnt will clear wdog counter; if 2, then phase_cnt change larger than 2 will clear wdog counter"]
            #[inline(always)]
            #[must_use]
            pub fn wdog_cfg(&mut self) -> WDOG_CFG_W<WDGCFG_SPEC> {
                WDOG_CFG_W::new(self, 28)
            }
            #[doc = "Bit 31 - 1- enable wdog counter"]
            #[inline(always)]
            #[must_use]
            pub fn wdgen(&mut self) -> WDGEN_W<WDGCFG_SPEC> {
                WDGEN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Watchdog configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdgcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdgcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WDGCFG_SPEC;
        impl crate::RegisterSpec for WDGCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdgcfg::R`](R) reader structure"]
        impl crate::Readable for WDGCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wdgcfg::W`](W) writer structure"]
        impl crate::Writable for WDGCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets wdgcfg to value 0"]
        impl crate::Resettable for WDGCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "phidx (rw) register accessor: Phase index register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phidx::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phidx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phidx`]
module"]
    pub type PHIDX = crate::Reg<phidx::PHIDX_SPEC>;
    #[doc = "Phase index register"]
    pub mod phidx {
        #[doc = "Register `phidx` reader"]
        pub type R = crate::R<PHIDX_SPEC>;
        #[doc = "Register `phidx` writer"]
        pub type W = crate::W<PHIDX_SPEC>;
        #[doc = "Field `PHIDX` reader - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1"]
        pub type PHIDX_R = crate::FieldReader<u32>;
        #[doc = "Field `PHIDX` writer - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1"]
        pub type PHIDX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1"]
            #[inline(always)]
            pub fn phidx(&self) -> PHIDX_R {
                PHIDX_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1"]
            #[inline(always)]
            #[must_use]
            pub fn phidx(&mut self) -> PHIDX_W<PHIDX_SPEC> {
                PHIDX_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Phase index register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phidx::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phidx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHIDX_SPEC;
        impl crate::RegisterSpec for PHIDX_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phidx::R`](R) reader structure"]
        impl crate::Readable for PHIDX_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phidx::W`](W) writer structure"]
        impl crate::Writable for PHIDX_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets phidx to value 0"]
        impl crate::Resettable for PHIDX_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "trgoen (rw) register accessor: Tigger output enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgoen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgoen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trgoen`]
module"]
    pub type TRGOEN = crate::Reg<trgoen::TRGOEN_SPEC>;
    #[doc = "Tigger output enable register"]
    pub mod trgoen {
        #[doc = "Register `trgoen` reader"]
        pub type R = crate::R<TRGOEN_SPEC>;
        #[doc = "Register `trgoen` writer"]
        pub type W = crate::W<TRGOEN_SPEC>;
        #[doc = "Field `FAULTFEN` reader - No description avaiable"]
        pub type FAULTFEN_R = crate::BitReader;
        #[doc = "Field `FAULTFEN` writer - No description avaiable"]
        pub type FAULTFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOME2FEN` reader - No description avaiable"]
        pub type HOME2FEN_R = crate::BitReader;
        #[doc = "Field `HOME2FEN` writer - No description avaiable"]
        pub type HOME2FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE1FEN` reader - No description avaiable"]
        pub type PULSE1FEN_R = crate::BitReader;
        #[doc = "Field `PULSE1FEN` writer - No description avaiable"]
        pub type PULSE1FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE0FEN` reader - No description avaiable"]
        pub type PULSE0FEN_R = crate::BitReader;
        #[doc = "Field `PULSE0FEN` writer - No description avaiable"]
        pub type PULSE0FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE1FEN` reader - No description avaiable"]
        pub type CYCLE1FEN_R = crate::BitReader;
        #[doc = "Field `CYCLE1FEN` writer - No description avaiable"]
        pub type CYCLE1FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE0FEN` reader - No description avaiable"]
        pub type CYCLE0FEN_R = crate::BitReader;
        #[doc = "Field `CYCLE0FEN` writer - No description avaiable"]
        pub type CYCLE0FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCHGFEN` reader - No description avaiable"]
        pub type DIRCHGFEN_R = crate::BitReader;
        #[doc = "Field `DIRCHGFEN` writer - No description avaiable"]
        pub type DIRCHGFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS2CMPFEN` reader - No description avaiable"]
        pub type POS2CMPFEN_R = crate::BitReader;
        #[doc = "Field `POS2CMPFEN` writer - No description avaiable"]
        pub type POS2CMPFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WIDTHTMFEN` reader - No description avaiable"]
        pub type WIDTHTMFEN_R = crate::BitReader;
        #[doc = "Field `WIDTHTMFEN` writer - No description avaiable"]
        pub type WIDTHTMFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZMISSFEN` reader - No description avaiable"]
        pub type ZMISSFEN_R = crate::BitReader;
        #[doc = "Field `ZMISSFEN` writer - No description avaiable"]
        pub type ZMISSFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZPHFEN` reader - 1- enable trigger output when zphf flag set"]
        pub type ZPHFEN_R = crate::BitReader;
        #[doc = "Field `ZPHFEN` writer - 1- enable trigger output when zphf flag set"]
        pub type ZPHFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POSCMPFEN` reader - 1- enable trigger output when poscmpf flag set"]
        pub type POSCMPFEN_R = crate::BitReader;
        #[doc = "Field `POSCMPFEN` writer - 1- enable trigger output when poscmpf flag set"]
        pub type POSCMPFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOMEFEN` reader - 1- enable trigger output when homef flag set"]
        pub type HOMEFEN_R = crate::BitReader;
        #[doc = "Field `HOMEFEN` writer - 1- enable trigger output when homef flag set"]
        pub type HOMEFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDGFEN` reader - 1- enable trigger output when wdg flag set"]
        pub type WDGFEN_R = crate::BitReader;
        #[doc = "Field `WDGFEN` writer - 1- enable trigger output when wdg flag set"]
        pub type WDGFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            pub fn faultfen(&self) -> FAULTFEN_R {
                FAULTFEN_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            pub fn home2fen(&self) -> HOME2FEN_R {
                HOME2FEN_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1fen(&self) -> PULSE1FEN_R {
                PULSE1FEN_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0fen(&self) -> PULSE0FEN_R {
                PULSE0FEN_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1fen(&self) -> CYCLE1FEN_R {
                CYCLE1FEN_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0fen(&self) -> CYCLE0FEN_R {
                CYCLE0FEN_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            pub fn dirchgfen(&self) -> DIRCHGFEN_R {
                DIRCHGFEN_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn pos2cmpfen(&self) -> POS2CMPFEN_R {
                POS2CMPFEN_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn widthtmfen(&self) -> WIDTHTMFEN_R {
                WIDTHTMFEN_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            pub fn zmissfen(&self) -> ZMISSFEN_R {
                ZMISSFEN_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - 1- enable trigger output when zphf flag set"]
            #[inline(always)]
            pub fn zphfen(&self) -> ZPHFEN_R {
                ZPHFEN_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - 1- enable trigger output when poscmpf flag set"]
            #[inline(always)]
            pub fn poscmpfen(&self) -> POSCMPFEN_R {
                POSCMPFEN_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - 1- enable trigger output when homef flag set"]
            #[inline(always)]
            pub fn homefen(&self) -> HOMEFEN_R {
                HOMEFEN_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - 1- enable trigger output when wdg flag set"]
            #[inline(always)]
            pub fn wdgfen(&self) -> WDGFEN_R {
                WDGFEN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn faultfen(&mut self) -> FAULTFEN_W<TRGOEN_SPEC> {
                FAULTFEN_W::new(self, 18)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn home2fen(&mut self) -> HOME2FEN_W<TRGOEN_SPEC> {
                HOME2FEN_W::new(self, 19)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse1fen(&mut self) -> PULSE1FEN_W<TRGOEN_SPEC> {
                PULSE1FEN_W::new(self, 20)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse0fen(&mut self) -> PULSE0FEN_W<TRGOEN_SPEC> {
                PULSE0FEN_W::new(self, 21)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle1fen(&mut self) -> CYCLE1FEN_W<TRGOEN_SPEC> {
                CYCLE1FEN_W::new(self, 22)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle0fen(&mut self) -> CYCLE0FEN_W<TRGOEN_SPEC> {
                CYCLE0FEN_W::new(self, 23)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dirchgfen(&mut self) -> DIRCHGFEN_W<TRGOEN_SPEC> {
                DIRCHGFEN_W::new(self, 24)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos2cmpfen(&mut self) -> POS2CMPFEN_W<TRGOEN_SPEC> {
                POS2CMPFEN_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn widthtmfen(&mut self) -> WIDTHTMFEN_W<TRGOEN_SPEC> {
                WIDTHTMFEN_W::new(self, 26)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn zmissfen(&mut self) -> ZMISSFEN_W<TRGOEN_SPEC> {
                ZMISSFEN_W::new(self, 27)
            }
            #[doc = "Bit 28 - 1- enable trigger output when zphf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn zphfen(&mut self) -> ZPHFEN_W<TRGOEN_SPEC> {
                ZPHFEN_W::new(self, 28)
            }
            #[doc = "Bit 29 - 1- enable trigger output when poscmpf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn poscmpfen(&mut self) -> POSCMPFEN_W<TRGOEN_SPEC> {
                POSCMPFEN_W::new(self, 29)
            }
            #[doc = "Bit 30 - 1- enable trigger output when homef flag set"]
            #[inline(always)]
            #[must_use]
            pub fn homefen(&mut self) -> HOMEFEN_W<TRGOEN_SPEC> {
                HOMEFEN_W::new(self, 30)
            }
            #[doc = "Bit 31 - 1- enable trigger output when wdg flag set"]
            #[inline(always)]
            #[must_use]
            pub fn wdgfen(&mut self) -> WDGFEN_W<TRGOEN_SPEC> {
                WDGFEN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Tigger output enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgoen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgoen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRGOEN_SPEC;
        impl crate::RegisterSpec for TRGOEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trgoen::R`](R) reader structure"]
        impl crate::Readable for TRGOEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trgoen::W`](W) writer structure"]
        impl crate::Writable for TRGOEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets trgoen to value 0"]
        impl crate::Resettable for TRGOEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "readen (rw) register accessor: Read event enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`readen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`readen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@readen`]
module"]
    pub type READEN = crate::Reg<readen::READEN_SPEC>;
    #[doc = "Read event enable register"]
    pub mod readen {
        #[doc = "Register `readen` reader"]
        pub type R = crate::R<READEN_SPEC>;
        #[doc = "Register `readen` writer"]
        pub type W = crate::W<READEN_SPEC>;
        #[doc = "Field `FAULTFEN` reader - No description avaiable"]
        pub type FAULTFEN_R = crate::BitReader;
        #[doc = "Field `FAULTFEN` writer - No description avaiable"]
        pub type FAULTFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOME2FEN` reader - No description avaiable"]
        pub type HOME2FEN_R = crate::BitReader;
        #[doc = "Field `HOME2FEN` writer - No description avaiable"]
        pub type HOME2FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE1FEN` reader - No description avaiable"]
        pub type PULSE1FEN_R = crate::BitReader;
        #[doc = "Field `PULSE1FEN` writer - No description avaiable"]
        pub type PULSE1FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE0FEN` reader - No description avaiable"]
        pub type PULSE0FEN_R = crate::BitReader;
        #[doc = "Field `PULSE0FEN` writer - No description avaiable"]
        pub type PULSE0FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE1FEN` reader - No description avaiable"]
        pub type CYCLE1FEN_R = crate::BitReader;
        #[doc = "Field `CYCLE1FEN` writer - No description avaiable"]
        pub type CYCLE1FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE0FEN` reader - No description avaiable"]
        pub type CYCLE0FEN_R = crate::BitReader;
        #[doc = "Field `CYCLE0FEN` writer - No description avaiable"]
        pub type CYCLE0FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCHGFEN` reader - No description avaiable"]
        pub type DIRCHGFEN_R = crate::BitReader;
        #[doc = "Field `DIRCHGFEN` writer - No description avaiable"]
        pub type DIRCHGFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS2CMPFEN` reader - No description avaiable"]
        pub type POS2CMPFEN_R = crate::BitReader;
        #[doc = "Field `POS2CMPFEN` writer - No description avaiable"]
        pub type POS2CMPFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WIDTHTMFEN` reader - No description avaiable"]
        pub type WIDTHTMFEN_R = crate::BitReader;
        #[doc = "Field `WIDTHTMFEN` writer - No description avaiable"]
        pub type WIDTHTMFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZMISSFEN` reader - No description avaiable"]
        pub type ZMISSFEN_R = crate::BitReader;
        #[doc = "Field `ZMISSFEN` writer - No description avaiable"]
        pub type ZMISSFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZPHFEN` reader - 1- load counters to their read registers when zphf flag set"]
        pub type ZPHFEN_R = crate::BitReader;
        #[doc = "Field `ZPHFEN` writer - 1- load counters to their read registers when zphf flag set"]
        pub type ZPHFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POSCMPFEN` reader - 1- load counters to their read registers when poscmpf flag set"]
        pub type POSCMPFEN_R = crate::BitReader;
        #[doc = "Field `POSCMPFEN` writer - 1- load counters to their read registers when poscmpf flag set"]
        pub type POSCMPFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOMEFEN` reader - 1- load counters to their read registers when homef flag set"]
        pub type HOMEFEN_R = crate::BitReader;
        #[doc = "Field `HOMEFEN` writer - 1- load counters to their read registers when homef flag set"]
        pub type HOMEFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDGFEN` reader - 1- load counters to their read registers when wdg flag set"]
        pub type WDGFEN_R = crate::BitReader;
        #[doc = "Field `WDGFEN` writer - 1- load counters to their read registers when wdg flag set"]
        pub type WDGFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            pub fn faultfen(&self) -> FAULTFEN_R {
                FAULTFEN_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            pub fn home2fen(&self) -> HOME2FEN_R {
                HOME2FEN_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1fen(&self) -> PULSE1FEN_R {
                PULSE1FEN_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0fen(&self) -> PULSE0FEN_R {
                PULSE0FEN_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1fen(&self) -> CYCLE1FEN_R {
                CYCLE1FEN_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0fen(&self) -> CYCLE0FEN_R {
                CYCLE0FEN_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            pub fn dirchgfen(&self) -> DIRCHGFEN_R {
                DIRCHGFEN_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn pos2cmpfen(&self) -> POS2CMPFEN_R {
                POS2CMPFEN_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn widthtmfen(&self) -> WIDTHTMFEN_R {
                WIDTHTMFEN_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            pub fn zmissfen(&self) -> ZMISSFEN_R {
                ZMISSFEN_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - 1- load counters to their read registers when zphf flag set"]
            #[inline(always)]
            pub fn zphfen(&self) -> ZPHFEN_R {
                ZPHFEN_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - 1- load counters to their read registers when poscmpf flag set"]
            #[inline(always)]
            pub fn poscmpfen(&self) -> POSCMPFEN_R {
                POSCMPFEN_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - 1- load counters to their read registers when homef flag set"]
            #[inline(always)]
            pub fn homefen(&self) -> HOMEFEN_R {
                HOMEFEN_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - 1- load counters to their read registers when wdg flag set"]
            #[inline(always)]
            pub fn wdgfen(&self) -> WDGFEN_R {
                WDGFEN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn faultfen(&mut self) -> FAULTFEN_W<READEN_SPEC> {
                FAULTFEN_W::new(self, 18)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn home2fen(&mut self) -> HOME2FEN_W<READEN_SPEC> {
                HOME2FEN_W::new(self, 19)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse1fen(&mut self) -> PULSE1FEN_W<READEN_SPEC> {
                PULSE1FEN_W::new(self, 20)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse0fen(&mut self) -> PULSE0FEN_W<READEN_SPEC> {
                PULSE0FEN_W::new(self, 21)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle1fen(&mut self) -> CYCLE1FEN_W<READEN_SPEC> {
                CYCLE1FEN_W::new(self, 22)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle0fen(&mut self) -> CYCLE0FEN_W<READEN_SPEC> {
                CYCLE0FEN_W::new(self, 23)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dirchgfen(&mut self) -> DIRCHGFEN_W<READEN_SPEC> {
                DIRCHGFEN_W::new(self, 24)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos2cmpfen(&mut self) -> POS2CMPFEN_W<READEN_SPEC> {
                POS2CMPFEN_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn widthtmfen(&mut self) -> WIDTHTMFEN_W<READEN_SPEC> {
                WIDTHTMFEN_W::new(self, 26)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn zmissfen(&mut self) -> ZMISSFEN_W<READEN_SPEC> {
                ZMISSFEN_W::new(self, 27)
            }
            #[doc = "Bit 28 - 1- load counters to their read registers when zphf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn zphfen(&mut self) -> ZPHFEN_W<READEN_SPEC> {
                ZPHFEN_W::new(self, 28)
            }
            #[doc = "Bit 29 - 1- load counters to their read registers when poscmpf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn poscmpfen(&mut self) -> POSCMPFEN_W<READEN_SPEC> {
                POSCMPFEN_W::new(self, 29)
            }
            #[doc = "Bit 30 - 1- load counters to their read registers when homef flag set"]
            #[inline(always)]
            #[must_use]
            pub fn homefen(&mut self) -> HOMEFEN_W<READEN_SPEC> {
                HOMEFEN_W::new(self, 30)
            }
            #[doc = "Bit 31 - 1- load counters to their read registers when wdg flag set"]
            #[inline(always)]
            #[must_use]
            pub fn wdgfen(&mut self) -> WDGFEN_W<READEN_SPEC> {
                WDGFEN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Read event enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`readen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`readen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct READEN_SPEC;
        impl crate::RegisterSpec for READEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`readen::R`](R) reader structure"]
        impl crate::Readable for READEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`readen::W`](W) writer structure"]
        impl crate::Writable for READEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets readen to value 0"]
        impl crate::Resettable for READEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "zcmp (rw) register accessor: Z comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zcmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zcmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@zcmp`]
module"]
    pub type ZCMP = crate::Reg<zcmp::ZCMP_SPEC>;
    #[doc = "Z comparator"]
    pub mod zcmp {
        #[doc = "Register `zcmp` reader"]
        pub type R = crate::R<ZCMP_SPEC>;
        #[doc = "Register `zcmp` writer"]
        pub type W = crate::W<ZCMP_SPEC>;
        #[doc = "Field `ZCMP` reader - zcnt postion compare value"]
        pub type ZCMP_R = crate::FieldReader<u32>;
        #[doc = "Field `ZCMP` writer - zcnt postion compare value"]
        pub type ZCMP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - zcnt postion compare value"]
            #[inline(always)]
            pub fn zcmp(&self) -> ZCMP_R {
                ZCMP_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - zcnt postion compare value"]
            #[inline(always)]
            #[must_use]
            pub fn zcmp(&mut self) -> ZCMP_W<ZCMP_SPEC> {
                ZCMP_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Z comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zcmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zcmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ZCMP_SPEC;
        impl crate::RegisterSpec for ZCMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`zcmp::R`](R) reader structure"]
        impl crate::Readable for ZCMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`zcmp::W`](W) writer structure"]
        impl crate::Writable for ZCMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets zcmp to value 0"]
        impl crate::Resettable for ZCMP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "phcmp (rw) register accessor: Phase comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phcmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phcmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phcmp`]
module"]
    pub type PHCMP = crate::Reg<phcmp::PHCMP_SPEC>;
    #[doc = "Phase comparator"]
    pub mod phcmp {
        #[doc = "Register `phcmp` reader"]
        pub type R = crate::R<PHCMP_SPEC>;
        #[doc = "Register `phcmp` writer"]
        pub type W = crate::W<PHCMP_SPEC>;
        #[doc = "Field `PHCMP` reader - phcnt position compare value"]
        pub type PHCMP_R = crate::FieldReader<u32>;
        #[doc = "Field `PHCMP` writer - phcnt position compare value"]
        pub type PHCMP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - phcnt position compare value"]
            #[inline(always)]
            pub fn phcmp(&self) -> PHCMP_R {
                PHCMP_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - phcnt position compare value"]
            #[inline(always)]
            #[must_use]
            pub fn phcmp(&mut self) -> PHCMP_W<PHCMP_SPEC> {
                PHCMP_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Phase comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phcmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phcmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHCMP_SPEC;
        impl crate::RegisterSpec for PHCMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phcmp::R`](R) reader structure"]
        impl crate::Readable for PHCMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phcmp::W`](W) writer structure"]
        impl crate::Writable for PHCMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets phcmp to value 0"]
        impl crate::Resettable for PHCMP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "spdcmp (rw) register accessor: Speed comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spdcmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spdcmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spdcmp`]
module"]
    pub type SPDCMP = crate::Reg<spdcmp::SPDCMP_SPEC>;
    #[doc = "Speed comparator"]
    pub mod spdcmp {
        #[doc = "Register `spdcmp` reader"]
        pub type R = crate::R<SPDCMP_SPEC>;
        #[doc = "Register `spdcmp` writer"]
        pub type W = crate::W<SPDCMP_SPEC>;
        #[doc = "Field `SPDCMP` reader - spdcnt position compare value"]
        pub type SPDCMP_R = crate::FieldReader<u32>;
        #[doc = "Field `SPDCMP` writer - spdcnt position compare value"]
        pub type SPDCMP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - spdcnt position compare value"]
            #[inline(always)]
            pub fn spdcmp(&self) -> SPDCMP_R {
                SPDCMP_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - spdcnt position compare value"]
            #[inline(always)]
            #[must_use]
            pub fn spdcmp(&mut self) -> SPDCMP_W<SPDCMP_SPEC> {
                SPDCMP_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Speed comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spdcmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spdcmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SPDCMP_SPEC;
        impl crate::RegisterSpec for SPDCMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spdcmp::R`](R) reader structure"]
        impl crate::Readable for SPDCMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`spdcmp::W`](W) writer structure"]
        impl crate::Writable for SPDCMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets spdcmp to value 0"]
        impl crate::Resettable for SPDCMP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "dmaen (rw) register accessor: DMA request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaen`]
module"]
    pub type DMAEN = crate::Reg<dmaen::DMAEN_SPEC>;
    #[doc = "DMA request enable register"]
    pub mod dmaen {
        #[doc = "Register `dmaen` reader"]
        pub type R = crate::R<DMAEN_SPEC>;
        #[doc = "Register `dmaen` writer"]
        pub type W = crate::W<DMAEN_SPEC>;
        #[doc = "Field `FAULTFEN` reader - No description avaiable"]
        pub type FAULTFEN_R = crate::BitReader;
        #[doc = "Field `FAULTFEN` writer - No description avaiable"]
        pub type FAULTFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOME2FEN` reader - No description avaiable"]
        pub type HOME2FEN_R = crate::BitReader;
        #[doc = "Field `HOME2FEN` writer - No description avaiable"]
        pub type HOME2FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE1FEN` reader - No description avaiable"]
        pub type PULSE1FEN_R = crate::BitReader;
        #[doc = "Field `PULSE1FEN` writer - No description avaiable"]
        pub type PULSE1FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE0FEN` reader - No description avaiable"]
        pub type PULSE0FEN_R = crate::BitReader;
        #[doc = "Field `PULSE0FEN` writer - No description avaiable"]
        pub type PULSE0FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE1FEN` reader - No description avaiable"]
        pub type CYCLE1FEN_R = crate::BitReader;
        #[doc = "Field `CYCLE1FEN` writer - No description avaiable"]
        pub type CYCLE1FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE0FEN` reader - No description avaiable"]
        pub type CYCLE0FEN_R = crate::BitReader;
        #[doc = "Field `CYCLE0FEN` writer - No description avaiable"]
        pub type CYCLE0FEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCHGFEN` reader - No description avaiable"]
        pub type DIRCHGFEN_R = crate::BitReader;
        #[doc = "Field `DIRCHGFEN` writer - No description avaiable"]
        pub type DIRCHGFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS2CMPFEN` reader - No description avaiable"]
        pub type POS2CMPFEN_R = crate::BitReader;
        #[doc = "Field `POS2CMPFEN` writer - No description avaiable"]
        pub type POS2CMPFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WIDTHTMFEN` reader - No description avaiable"]
        pub type WIDTHTMFEN_R = crate::BitReader;
        #[doc = "Field `WIDTHTMFEN` writer - No description avaiable"]
        pub type WIDTHTMFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZMISSFEN` reader - No description avaiable"]
        pub type ZMISSFEN_R = crate::BitReader;
        #[doc = "Field `ZMISSFEN` writer - No description avaiable"]
        pub type ZMISSFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZPHFEN` reader - 1- generate dma request when zphf flag set"]
        pub type ZPHFEN_R = crate::BitReader;
        #[doc = "Field `ZPHFEN` writer - 1- generate dma request when zphf flag set"]
        pub type ZPHFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POSCMPFEN` reader - 1- generate dma request when poscmpf flag set"]
        pub type POSCMPFEN_R = crate::BitReader;
        #[doc = "Field `POSCMPFEN` writer - 1- generate dma request when poscmpf flag set"]
        pub type POSCMPFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOMEFEN` reader - 1- generate dma request when homef flag set"]
        pub type HOMEFEN_R = crate::BitReader;
        #[doc = "Field `HOMEFEN` writer - 1- generate dma request when homef flag set"]
        pub type HOMEFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDGFEN` reader - 1- generate dma request when wdg flag set"]
        pub type WDGFEN_R = crate::BitReader;
        #[doc = "Field `WDGFEN` writer - 1- generate dma request when wdg flag set"]
        pub type WDGFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            pub fn faultfen(&self) -> FAULTFEN_R {
                FAULTFEN_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            pub fn home2fen(&self) -> HOME2FEN_R {
                HOME2FEN_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1fen(&self) -> PULSE1FEN_R {
                PULSE1FEN_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0fen(&self) -> PULSE0FEN_R {
                PULSE0FEN_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1fen(&self) -> CYCLE1FEN_R {
                CYCLE1FEN_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0fen(&self) -> CYCLE0FEN_R {
                CYCLE0FEN_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            pub fn dirchgfen(&self) -> DIRCHGFEN_R {
                DIRCHGFEN_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn pos2cmpfen(&self) -> POS2CMPFEN_R {
                POS2CMPFEN_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn widthtmfen(&self) -> WIDTHTMFEN_R {
                WIDTHTMFEN_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            pub fn zmissfen(&self) -> ZMISSFEN_R {
                ZMISSFEN_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - 1- generate dma request when zphf flag set"]
            #[inline(always)]
            pub fn zphfen(&self) -> ZPHFEN_R {
                ZPHFEN_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - 1- generate dma request when poscmpf flag set"]
            #[inline(always)]
            pub fn poscmpfen(&self) -> POSCMPFEN_R {
                POSCMPFEN_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - 1- generate dma request when homef flag set"]
            #[inline(always)]
            pub fn homefen(&self) -> HOMEFEN_R {
                HOMEFEN_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - 1- generate dma request when wdg flag set"]
            #[inline(always)]
            pub fn wdgfen(&self) -> WDGFEN_R {
                WDGFEN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn faultfen(&mut self) -> FAULTFEN_W<DMAEN_SPEC> {
                FAULTFEN_W::new(self, 18)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn home2fen(&mut self) -> HOME2FEN_W<DMAEN_SPEC> {
                HOME2FEN_W::new(self, 19)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse1fen(&mut self) -> PULSE1FEN_W<DMAEN_SPEC> {
                PULSE1FEN_W::new(self, 20)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse0fen(&mut self) -> PULSE0FEN_W<DMAEN_SPEC> {
                PULSE0FEN_W::new(self, 21)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle1fen(&mut self) -> CYCLE1FEN_W<DMAEN_SPEC> {
                CYCLE1FEN_W::new(self, 22)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle0fen(&mut self) -> CYCLE0FEN_W<DMAEN_SPEC> {
                CYCLE0FEN_W::new(self, 23)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dirchgfen(&mut self) -> DIRCHGFEN_W<DMAEN_SPEC> {
                DIRCHGFEN_W::new(self, 24)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos2cmpfen(&mut self) -> POS2CMPFEN_W<DMAEN_SPEC> {
                POS2CMPFEN_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn widthtmfen(&mut self) -> WIDTHTMFEN_W<DMAEN_SPEC> {
                WIDTHTMFEN_W::new(self, 26)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn zmissfen(&mut self) -> ZMISSFEN_W<DMAEN_SPEC> {
                ZMISSFEN_W::new(self, 27)
            }
            #[doc = "Bit 28 - 1- generate dma request when zphf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn zphfen(&mut self) -> ZPHFEN_W<DMAEN_SPEC> {
                ZPHFEN_W::new(self, 28)
            }
            #[doc = "Bit 29 - 1- generate dma request when poscmpf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn poscmpfen(&mut self) -> POSCMPFEN_W<DMAEN_SPEC> {
                POSCMPFEN_W::new(self, 29)
            }
            #[doc = "Bit 30 - 1- generate dma request when homef flag set"]
            #[inline(always)]
            #[must_use]
            pub fn homefen(&mut self) -> HOMEFEN_W<DMAEN_SPEC> {
                HOMEFEN_W::new(self, 30)
            }
            #[doc = "Bit 31 - 1- generate dma request when wdg flag set"]
            #[inline(always)]
            #[must_use]
            pub fn wdgfen(&mut self) -> WDGFEN_W<DMAEN_SPEC> {
                WDGFEN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DMA request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DMAEN_SPEC;
        impl crate::RegisterSpec for DMAEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmaen::R`](R) reader structure"]
        impl crate::Readable for DMAEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dmaen::W`](W) writer structure"]
        impl crate::Writable for DMAEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets dmaen to value 0"]
        impl crate::Resettable for DMAEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sr (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
    pub type SR = crate::Reg<sr::SR_SPEC>;
    #[doc = "Status register"]
    pub mod sr {
        #[doc = "Register `sr` reader"]
        pub type R = crate::R<SR_SPEC>;
        #[doc = "Register `sr` writer"]
        pub type W = crate::W<SR_SPEC>;
        #[doc = "Field `FAULTF` reader - No description avaiable"]
        pub type FAULTF_R = crate::BitReader;
        #[doc = "Field `FAULTF` writer - No description avaiable"]
        pub type FAULTF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOME2F` reader - No description avaiable"]
        pub type HOME2F_R = crate::BitReader;
        #[doc = "Field `HOME2F` writer - No description avaiable"]
        pub type HOME2F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE1F` reader - No description avaiable"]
        pub type PULSE1F_R = crate::BitReader;
        #[doc = "Field `PULSE1F` writer - No description avaiable"]
        pub type PULSE1F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE0F` reader - No description avaiable"]
        pub type PULSE0F_R = crate::BitReader;
        #[doc = "Field `PULSE0F` writer - No description avaiable"]
        pub type PULSE0F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE1F` reader - No description avaiable"]
        pub type CYCLE1F_R = crate::BitReader;
        #[doc = "Field `CYCLE1F` writer - No description avaiable"]
        pub type CYCLE1F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE0F` reader - No description avaiable"]
        pub type CYCLE0F_R = crate::BitReader;
        #[doc = "Field `CYCLE0F` writer - No description avaiable"]
        pub type CYCLE0F_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCHGF` reader - No description avaiable"]
        pub type DIRCHGF_R = crate::BitReader;
        #[doc = "Field `DIRCHGF` writer - No description avaiable"]
        pub type DIRCHGF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS2CMPF` reader - No description avaiable"]
        pub type POS2CMPF_R = crate::BitReader;
        #[doc = "Field `POS2CMPF` writer - No description avaiable"]
        pub type POS2CMPF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WIDTHTMF` reader - No description avaiable"]
        pub type WIDTHTMF_R = crate::BitReader;
        #[doc = "Field `WIDTHTMF` writer - No description avaiable"]
        pub type WIDTHTMF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZMISSF` reader - No description avaiable"]
        pub type ZMISSF_R = crate::BitReader;
        #[doc = "Field `ZMISSF` writer - No description avaiable"]
        pub type ZMISSF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZPHF` reader - z input flag"]
        pub type ZPHF_R = crate::BitReader;
        #[doc = "Field `ZPHF` writer - z input flag"]
        pub type ZPHF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POSCMPF` reader - postion compare match flag"]
        pub type POSCMPF_R = crate::BitReader;
        #[doc = "Field `POSCMPF` writer - postion compare match flag"]
        pub type POSCMPF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOMEF` reader - home flag"]
        pub type HOMEF_R = crate::BitReader;
        #[doc = "Field `HOMEF` writer - home flag"]
        pub type HOMEF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDGF` reader - watchdog flag"]
        pub type WDGF_R = crate::BitReader;
        #[doc = "Field `WDGF` writer - watchdog flag"]
        pub type WDGF_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            pub fn faultf(&self) -> FAULTF_R {
                FAULTF_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            pub fn home2f(&self) -> HOME2F_R {
                HOME2F_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1f(&self) -> PULSE1F_R {
                PULSE1F_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0f(&self) -> PULSE0F_R {
                PULSE0F_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1f(&self) -> CYCLE1F_R {
                CYCLE1F_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0f(&self) -> CYCLE0F_R {
                CYCLE0F_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            pub fn dirchgf(&self) -> DIRCHGF_R {
                DIRCHGF_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn pos2cmpf(&self) -> POS2CMPF_R {
                POS2CMPF_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn widthtmf(&self) -> WIDTHTMF_R {
                WIDTHTMF_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            pub fn zmissf(&self) -> ZMISSF_R {
                ZMISSF_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - z input flag"]
            #[inline(always)]
            pub fn zphf(&self) -> ZPHF_R {
                ZPHF_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - postion compare match flag"]
            #[inline(always)]
            pub fn poscmpf(&self) -> POSCMPF_R {
                POSCMPF_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - home flag"]
            #[inline(always)]
            pub fn homef(&self) -> HOMEF_R {
                HOMEF_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - watchdog flag"]
            #[inline(always)]
            pub fn wdgf(&self) -> WDGF_R {
                WDGF_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn faultf(&mut self) -> FAULTF_W<SR_SPEC> {
                FAULTF_W::new(self, 18)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn home2f(&mut self) -> HOME2F_W<SR_SPEC> {
                HOME2F_W::new(self, 19)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse1f(&mut self) -> PULSE1F_W<SR_SPEC> {
                PULSE1F_W::new(self, 20)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse0f(&mut self) -> PULSE0F_W<SR_SPEC> {
                PULSE0F_W::new(self, 21)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle1f(&mut self) -> CYCLE1F_W<SR_SPEC> {
                CYCLE1F_W::new(self, 22)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle0f(&mut self) -> CYCLE0F_W<SR_SPEC> {
                CYCLE0F_W::new(self, 23)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dirchgf(&mut self) -> DIRCHGF_W<SR_SPEC> {
                DIRCHGF_W::new(self, 24)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos2cmpf(&mut self) -> POS2CMPF_W<SR_SPEC> {
                POS2CMPF_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn widthtmf(&mut self) -> WIDTHTMF_W<SR_SPEC> {
                WIDTHTMF_W::new(self, 26)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn zmissf(&mut self) -> ZMISSF_W<SR_SPEC> {
                ZMISSF_W::new(self, 27)
            }
            #[doc = "Bit 28 - z input flag"]
            #[inline(always)]
            #[must_use]
            pub fn zphf(&mut self) -> ZPHF_W<SR_SPEC> {
                ZPHF_W::new(self, 28)
            }
            #[doc = "Bit 29 - postion compare match flag"]
            #[inline(always)]
            #[must_use]
            pub fn poscmpf(&mut self) -> POSCMPF_W<SR_SPEC> {
                POSCMPF_W::new(self, 29)
            }
            #[doc = "Bit 30 - home flag"]
            #[inline(always)]
            #[must_use]
            pub fn homef(&mut self) -> HOMEF_W<SR_SPEC> {
                HOMEF_W::new(self, 30)
            }
            #[doc = "Bit 31 - watchdog flag"]
            #[inline(always)]
            #[must_use]
            pub fn wdgf(&mut self) -> WDGF_W<SR_SPEC> {
                WDGF_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SR_SPEC;
        impl crate::RegisterSpec for SR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sr::R`](R) reader structure"]
        impl crate::Readable for SR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
        impl crate::Writable for SR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sr to value 0"]
        impl crate::Resettable for SR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "irqen (rw) register accessor: Interrupt request register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqen`]
module"]
    pub type IRQEN = crate::Reg<irqen::IRQEN_SPEC>;
    #[doc = "Interrupt request register"]
    pub mod irqen {
        #[doc = "Register `irqen` reader"]
        pub type R = crate::R<IRQEN_SPEC>;
        #[doc = "Register `irqen` writer"]
        pub type W = crate::W<IRQEN_SPEC>;
        #[doc = "Field `FAULTE` reader - No description avaiable"]
        pub type FAULTE_R = crate::BitReader;
        #[doc = "Field `FAULTE` writer - No description avaiable"]
        pub type FAULTE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOME2E` reader - No description avaiable"]
        pub type HOME2E_R = crate::BitReader;
        #[doc = "Field `HOME2E` writer - No description avaiable"]
        pub type HOME2E_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE1E` reader - No description avaiable"]
        pub type PULSE1E_R = crate::BitReader;
        #[doc = "Field `PULSE1E` writer - No description avaiable"]
        pub type PULSE1E_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PULSE0E` reader - No description avaiable"]
        pub type PULSE0E_R = crate::BitReader;
        #[doc = "Field `PULSE0E` writer - No description avaiable"]
        pub type PULSE0E_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE1E` reader - No description avaiable"]
        pub type CYCLE1E_R = crate::BitReader;
        #[doc = "Field `CYCLE1E` writer - No description avaiable"]
        pub type CYCLE1E_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CYCLE0E` reader - No description avaiable"]
        pub type CYCLE0E_R = crate::BitReader;
        #[doc = "Field `CYCLE0E` writer - No description avaiable"]
        pub type CYCLE0E_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCHGE` reader - No description avaiable"]
        pub type DIRCHGE_R = crate::BitReader;
        #[doc = "Field `DIRCHGE` writer - No description avaiable"]
        pub type DIRCHGE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS2CMPE` reader - No description avaiable"]
        pub type POS2CMPE_R = crate::BitReader;
        #[doc = "Field `POS2CMPE` writer - No description avaiable"]
        pub type POS2CMPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WIDTHTME` reader - No description avaiable"]
        pub type WIDTHTME_R = crate::BitReader;
        #[doc = "Field `WIDTHTME` writer - No description avaiable"]
        pub type WIDTHTME_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZMISSE` reader - No description avaiable"]
        pub type ZMISSE_R = crate::BitReader;
        #[doc = "Field `ZMISSE` writer - No description avaiable"]
        pub type ZMISSE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZPHIE` reader - 1- generate interrupt when zphf flag set"]
        pub type ZPHIE_R = crate::BitReader;
        #[doc = "Field `ZPHIE` writer - 1- generate interrupt when zphf flag set"]
        pub type ZPHIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POSCMPIE` reader - 1- generate interrupt when poscmpf flag set"]
        pub type POSCMPIE_R = crate::BitReader;
        #[doc = "Field `POSCMPIE` writer - 1- generate interrupt when poscmpf flag set"]
        pub type POSCMPIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOMEIE` reader - 1- generate interrupt when homef flag set"]
        pub type HOMEIE_R = crate::BitReader;
        #[doc = "Field `HOMEIE` writer - 1- generate interrupt when homef flag set"]
        pub type HOMEIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WDGIE` reader - 1- generate interrupt when wdg flag set"]
        pub type WDGIE_R = crate::BitReader;
        #[doc = "Field `WDGIE` writer - 1- generate interrupt when wdg flag set"]
        pub type WDGIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            pub fn faulte(&self) -> FAULTE_R {
                FAULTE_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            pub fn home2e(&self) -> HOME2E_R {
                HOME2E_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1e(&self) -> PULSE1E_R {
                PULSE1E_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0e(&self) -> PULSE0E_R {
                PULSE0E_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1e(&self) -> CYCLE1E_R {
                CYCLE1E_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0e(&self) -> CYCLE0E_R {
                CYCLE0E_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            pub fn dirchge(&self) -> DIRCHGE_R {
                DIRCHGE_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn pos2cmpe(&self) -> POS2CMPE_R {
                POS2CMPE_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn widthtme(&self) -> WIDTHTME_R {
                WIDTHTME_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            pub fn zmisse(&self) -> ZMISSE_R {
                ZMISSE_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - 1- generate interrupt when zphf flag set"]
            #[inline(always)]
            pub fn zphie(&self) -> ZPHIE_R {
                ZPHIE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - 1- generate interrupt when poscmpf flag set"]
            #[inline(always)]
            pub fn poscmpie(&self) -> POSCMPIE_R {
                POSCMPIE_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - 1- generate interrupt when homef flag set"]
            #[inline(always)]
            pub fn homeie(&self) -> HOMEIE_R {
                HOMEIE_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - 1- generate interrupt when wdg flag set"]
            #[inline(always)]
            pub fn wdgie(&self) -> WDGIE_R {
                WDGIE_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn faulte(&mut self) -> FAULTE_W<IRQEN_SPEC> {
                FAULTE_W::new(self, 18)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn home2e(&mut self) -> HOME2E_W<IRQEN_SPEC> {
                HOME2E_W::new(self, 19)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse1e(&mut self) -> PULSE1E_W<IRQEN_SPEC> {
                PULSE1E_W::new(self, 20)
            }
            #[doc = "Bit 21 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse0e(&mut self) -> PULSE0E_W<IRQEN_SPEC> {
                PULSE0E_W::new(self, 21)
            }
            #[doc = "Bit 22 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle1e(&mut self) -> CYCLE1E_W<IRQEN_SPEC> {
                CYCLE1E_W::new(self, 22)
            }
            #[doc = "Bit 23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle0e(&mut self) -> CYCLE0E_W<IRQEN_SPEC> {
                CYCLE0E_W::new(self, 23)
            }
            #[doc = "Bit 24 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dirchge(&mut self) -> DIRCHGE_W<IRQEN_SPEC> {
                DIRCHGE_W::new(self, 24)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos2cmpe(&mut self) -> POS2CMPE_W<IRQEN_SPEC> {
                POS2CMPE_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn widthtme(&mut self) -> WIDTHTME_W<IRQEN_SPEC> {
                WIDTHTME_W::new(self, 26)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn zmisse(&mut self) -> ZMISSE_W<IRQEN_SPEC> {
                ZMISSE_W::new(self, 27)
            }
            #[doc = "Bit 28 - 1- generate interrupt when zphf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn zphie(&mut self) -> ZPHIE_W<IRQEN_SPEC> {
                ZPHIE_W::new(self, 28)
            }
            #[doc = "Bit 29 - 1- generate interrupt when poscmpf flag set"]
            #[inline(always)]
            #[must_use]
            pub fn poscmpie(&mut self) -> POSCMPIE_W<IRQEN_SPEC> {
                POSCMPIE_W::new(self, 29)
            }
            #[doc = "Bit 30 - 1- generate interrupt when homef flag set"]
            #[inline(always)]
            #[must_use]
            pub fn homeie(&mut self) -> HOMEIE_W<IRQEN_SPEC> {
                HOMEIE_W::new(self, 30)
            }
            #[doc = "Bit 31 - 1- generate interrupt when wdg flag set"]
            #[inline(always)]
            #[must_use]
            pub fn wdgie(&mut self) -> WDGIE_W<IRQEN_SPEC> {
                WDGIE_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt request register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IRQEN_SPEC;
        impl crate::RegisterSpec for IRQEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`irqen::R`](R) reader structure"]
        impl crate::Readable for IRQEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`irqen::W`](W) writer structure"]
        impl crate::Writable for IRQEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets irqen to value 0"]
        impl crate::Resettable for IRQEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::count::COUNT;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod count {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct COUNT {
            z: Z,
            ph: PH,
            spd: SPD,
            tmr: TMR,
        }
        impl COUNT {
            #[doc = "0x00 - Z counter"]
            #[inline(always)]
            pub const fn z(&self) -> &Z {
                &self.z
            }
            #[doc = "0x04 - Phase counter"]
            #[inline(always)]
            pub const fn ph(&self) -> &PH {
                &self.ph
            }
            #[doc = "0x08 - Speed counter"]
            #[inline(always)]
            pub const fn spd(&self) -> &SPD {
                &self.spd
            }
            #[doc = "0x0c - Timer counter"]
            #[inline(always)]
            pub const fn tmr(&self) -> &TMR {
                &self.tmr
            }
        }
        #[doc = "z (rw) register accessor: Z counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@z`]
module"]
        pub type Z = crate::Reg<z::Z_SPEC>;
        #[doc = "Z counter"]
        pub mod z {
            #[doc = "Register `z` reader"]
            pub type R = crate::R<Z_SPEC>;
            #[doc = "Register `z` writer"]
            pub type W = crate::W<Z_SPEC>;
            #[doc = "Field `ZCNT` reader - zcnt value"]
            pub type ZCNT_R = crate::FieldReader<u32>;
            #[doc = "Field `ZCNT` writer - zcnt value"]
            pub type ZCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - zcnt value"]
                #[inline(always)]
                pub fn zcnt(&self) -> ZCNT_R {
                    ZCNT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - zcnt value"]
                #[inline(always)]
                #[must_use]
                pub fn zcnt(&mut self) -> ZCNT_W<Z_SPEC> {
                    ZCNT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Z counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`z::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`z::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct Z_SPEC;
            impl crate::RegisterSpec for Z_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`z::R`](R) reader structure"]
            impl crate::Readable for Z_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`z::W`](W) writer structure"]
            impl crate::Writable for Z_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets z to value 0"]
            impl crate::Resettable for Z_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "ph (rw) register accessor: Phase counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ph::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ph::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ph`]
module"]
        pub type PH = crate::Reg<ph::PH_SPEC>;
        #[doc = "Phase counter"]
        pub mod ph {
            #[doc = "Register `ph` reader"]
            pub type R = crate::R<PH_SPEC>;
            #[doc = "Register `ph` writer"]
            pub type W = crate::W<PH_SPEC>;
            #[doc = "Field `PHCNT` reader - phcnt value"]
            pub type PHCNT_R = crate::FieldReader<u32>;
            #[doc = "Field `BSTAT` reader - 1- b input is high 0- b input is low"]
            pub type BSTAT_R = crate::BitReader;
            #[doc = "Field `ASTAT` reader - 1- a input is high 0- a input is low"]
            pub type ASTAT_R = crate::BitReader;
            #[doc = "Field `DIR` reader - 1- reverse rotation 0- forward rotation"]
            pub type DIR_R = crate::BitReader;
            impl R {
                #[doc = "Bits 0:20 - phcnt value"]
                #[inline(always)]
                pub fn phcnt(&self) -> PHCNT_R {
                    PHCNT_R::new(self.bits & 0x001f_ffff)
                }
                #[doc = "Bit 25 - 1- b input is high 0- b input is low"]
                #[inline(always)]
                pub fn bstat(&self) -> BSTAT_R {
                    BSTAT_R::new(((self.bits >> 25) & 1) != 0)
                }
                #[doc = "Bit 26 - 1- a input is high 0- a input is low"]
                #[inline(always)]
                pub fn astat(&self) -> ASTAT_R {
                    ASTAT_R::new(((self.bits >> 26) & 1) != 0)
                }
                #[doc = "Bit 30 - 1- reverse rotation 0- forward rotation"]
                #[inline(always)]
                pub fn dir(&self) -> DIR_R {
                    DIR_R::new(((self.bits >> 30) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Phase counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ph::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ph::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PH_SPEC;
            impl crate::RegisterSpec for PH_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ph::R`](R) reader structure"]
            impl crate::Readable for PH_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ph::W`](W) writer structure"]
            impl crate::Writable for PH_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ph to value 0"]
            impl crate::Resettable for PH_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "spd (rw) register accessor: Speed counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spd`]
module"]
        pub type SPD = crate::Reg<spd::SPD_SPEC>;
        #[doc = "Speed counter"]
        pub mod spd {
            #[doc = "Register `spd` reader"]
            pub type R = crate::R<SPD_SPEC>;
            #[doc = "Register `spd` writer"]
            pub type W = crate::W<SPD_SPEC>;
            #[doc = "Field `SPDCNT` reader - spdcnt value"]
            pub type SPDCNT_R = crate::FieldReader<u32>;
            #[doc = "Field `BSTAT` reader - 1- b input is high 0- b input is low"]
            pub type BSTAT_R = crate::BitReader;
            #[doc = "Field `BSTAT` writer - 1- b input is high 0- b input is low"]
            pub type BSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `ASTAT` reader - 1- a input is high 0- a input is low"]
            pub type ASTAT_R = crate::BitReader;
            #[doc = "Field `DIR` reader - 1- reverse rotation 0- forward rotation"]
            pub type DIR_R = crate::BitReader;
            impl R {
                #[doc = "Bits 0:27 - spdcnt value"]
                #[inline(always)]
                pub fn spdcnt(&self) -> SPDCNT_R {
                    SPDCNT_R::new(self.bits & 0x0fff_ffff)
                }
                #[doc = "Bit 29 - 1- b input is high 0- b input is low"]
                #[inline(always)]
                pub fn bstat(&self) -> BSTAT_R {
                    BSTAT_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 30 - 1- a input is high 0- a input is low"]
                #[inline(always)]
                pub fn astat(&self) -> ASTAT_R {
                    ASTAT_R::new(((self.bits >> 30) & 1) != 0)
                }
                #[doc = "Bit 31 - 1- reverse rotation 0- forward rotation"]
                #[inline(always)]
                pub fn dir(&self) -> DIR_R {
                    DIR_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 29 - 1- b input is high 0- b input is low"]
                #[inline(always)]
                #[must_use]
                pub fn bstat(&mut self) -> BSTAT_W<SPD_SPEC> {
                    BSTAT_W::new(self, 29)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Speed counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SPD_SPEC;
            impl crate::RegisterSpec for SPD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`spd::R`](R) reader structure"]
            impl crate::Readable for SPD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`spd::W`](W) writer structure"]
            impl crate::Writable for SPD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets spd to value 0"]
            impl crate::Resettable for SPD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "tmr (rw) register accessor: Timer counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmr`]
module"]
        pub type TMR = crate::Reg<tmr::TMR_SPEC>;
        #[doc = "Timer counter"]
        pub mod tmr {
            #[doc = "Register `tmr` reader"]
            pub type R = crate::R<TMR_SPEC>;
            #[doc = "Register `tmr` writer"]
            pub type W = crate::W<TMR_SPEC>;
            #[doc = "Field `TMRCNT` reader - 32 bit free run timer"]
            pub type TMRCNT_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - 32 bit free run timer"]
                #[inline(always)]
                pub fn tmrcnt(&self) -> TMRCNT_R {
                    TMRCNT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Timer counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TMR_SPEC;
            impl crate::RegisterSpec for TMR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`tmr::R`](R) reader structure"]
            impl crate::Readable for TMR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`tmr::W`](W) writer structure"]
            impl crate::Writable for TMR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets tmr to value 0"]
            impl crate::Resettable for TMR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "zcmp2 (rw) register accessor: Z comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zcmp2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zcmp2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@zcmp2`]
module"]
    pub type ZCMP2 = crate::Reg<zcmp2::ZCMP2_SPEC>;
    #[doc = "Z comparator"]
    pub mod zcmp2 {
        #[doc = "Register `zcmp2` reader"]
        pub type R = crate::R<ZCMP2_SPEC>;
        #[doc = "Register `zcmp2` writer"]
        pub type W = crate::W<ZCMP2_SPEC>;
        #[doc = "Field `ZCMP2` reader - No description avaiable"]
        pub type ZCMP2_R = crate::FieldReader<u32>;
        #[doc = "Field `ZCMP2` writer - No description avaiable"]
        pub type ZCMP2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn zcmp2(&self) -> ZCMP2_R {
                ZCMP2_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn zcmp2(&mut self) -> ZCMP2_W<ZCMP2_SPEC> {
                ZCMP2_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Z comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`zcmp2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`zcmp2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ZCMP2_SPEC;
        impl crate::RegisterSpec for ZCMP2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`zcmp2::R`](R) reader structure"]
        impl crate::Readable for ZCMP2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`zcmp2::W`](W) writer structure"]
        impl crate::Writable for ZCMP2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets zcmp2 to value 0"]
        impl crate::Resettable for ZCMP2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "phcmp2 (rw) register accessor: Phase comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phcmp2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phcmp2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phcmp2`]
module"]
    pub type PHCMP2 = crate::Reg<phcmp2::PHCMP2_SPEC>;
    #[doc = "Phase comparator"]
    pub mod phcmp2 {
        #[doc = "Register `phcmp2` reader"]
        pub type R = crate::R<PHCMP2_SPEC>;
        #[doc = "Register `phcmp2` writer"]
        pub type W = crate::W<PHCMP2_SPEC>;
        #[doc = "Field `PHCMP2` reader - No description avaiable"]
        pub type PHCMP2_R = crate::FieldReader<u32>;
        #[doc = "Field `PHCMP2` writer - No description avaiable"]
        pub type PHCMP2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn phcmp2(&self) -> PHCMP2_R {
                PHCMP2_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn phcmp2(&mut self) -> PHCMP2_W<PHCMP2_SPEC> {
                PHCMP2_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Phase comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phcmp2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phcmp2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHCMP2_SPEC;
        impl crate::RegisterSpec for PHCMP2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phcmp2::R`](R) reader structure"]
        impl crate::Readable for PHCMP2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phcmp2::W`](W) writer structure"]
        impl crate::Writable for PHCMP2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets phcmp2 to value 0"]
        impl crate::Resettable for PHCMP2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "spdcmp2 (rw) register accessor: Speed comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spdcmp2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spdcmp2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spdcmp2`]
module"]
    pub type SPDCMP2 = crate::Reg<spdcmp2::SPDCMP2_SPEC>;
    #[doc = "Speed comparator"]
    pub mod spdcmp2 {
        #[doc = "Register `spdcmp2` reader"]
        pub type R = crate::R<SPDCMP2_SPEC>;
        #[doc = "Register `spdcmp2` writer"]
        pub type W = crate::W<SPDCMP2_SPEC>;
        #[doc = "Field `SPDCMP2` reader - No description avaiable"]
        pub type SPDCMP2_R = crate::FieldReader<u32>;
        #[doc = "Field `SPDCMP2` writer - No description avaiable"]
        pub type SPDCMP2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn spdcmp2(&self) -> SPDCMP2_R {
                SPDCMP2_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn spdcmp2(&mut self) -> SPDCMP2_W<SPDCMP2_SPEC> {
                SPDCMP2_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Speed comparator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spdcmp2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spdcmp2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SPDCMP2_SPEC;
        impl crate::RegisterSpec for SPDCMP2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`spdcmp2::R`](R) reader structure"]
        impl crate::Readable for SPDCMP2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`spdcmp2::W`](W) writer structure"]
        impl crate::Writable for SPDCMP2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets spdcmp2 to value 0"]
        impl crate::Resettable for SPDCMP2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "match_cfg (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`match_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`match_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_cfg`]
module"]
    pub type MATCH_CFG = crate::Reg<match_cfg::MATCH_CFG_SPEC>;
    #[doc = "No description avaiable"]
    pub mod match_cfg {
        #[doc = "Register `match_cfg` reader"]
        pub type R = crate::R<MATCH_CFG_SPEC>;
        #[doc = "Register `match_cfg` writer"]
        pub type W = crate::W<MATCH_CFG_SPEC>;
        #[doc = "Field `POS_MATCH2_OPT` reader - No description avaiable"]
        pub type POS_MATCH2_OPT_R = crate::BitReader;
        #[doc = "Field `POS_MATCH2_OPT` writer - No description avaiable"]
        pub type POS_MATCH2_OPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS_MATCH2_DIR` reader - No description avaiable"]
        pub type POS_MATCH2_DIR_R = crate::BitReader;
        #[doc = "Field `POS_MATCH2_DIR` writer - No description avaiable"]
        pub type POS_MATCH2_DIR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHASE_MATCH_DIS2` reader - No description avaiable"]
        pub type PHASE_MATCH_DIS2_R = crate::BitReader;
        #[doc = "Field `PHASE_MATCH_DIS2` writer - No description avaiable"]
        pub type PHASE_MATCH_DIS2_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SPDCMP2DIS` reader - No description avaiable"]
        pub type SPDCMP2DIS_R = crate::BitReader;
        #[doc = "Field `SPDCMP2DIS` writer - No description avaiable"]
        pub type SPDCMP2DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCMP2` reader - No description avaiable"]
        pub type DIRCMP2_R = crate::BitReader;
        #[doc = "Field `DIRCMP2` writer - No description avaiable"]
        pub type DIRCMP2_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCMP2DIS` reader - No description avaiable"]
        pub type DIRCMP2DIS_R = crate::BitReader;
        #[doc = "Field `DIRCMP2DIS` writer - No description avaiable"]
        pub type DIRCMP2DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZCMP2DIS` reader - No description avaiable"]
        pub type ZCMP2DIS_R = crate::BitReader;
        #[doc = "Field `ZCMP2DIS` writer - No description avaiable"]
        pub type ZCMP2DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS_MATCH_OPT` reader - No description avaiable"]
        pub type POS_MATCH_OPT_R = crate::BitReader;
        #[doc = "Field `POS_MATCH_OPT` writer - No description avaiable"]
        pub type POS_MATCH_OPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS_MATCH_DIR` reader - No description avaiable"]
        pub type POS_MATCH_DIR_R = crate::BitReader;
        #[doc = "Field `POS_MATCH_DIR` writer - No description avaiable"]
        pub type POS_MATCH_DIR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHASE_MATCH_DIS` reader - No description avaiable"]
        pub type PHASE_MATCH_DIS_R = crate::BitReader;
        #[doc = "Field `PHASE_MATCH_DIS` writer - No description avaiable"]
        pub type PHASE_MATCH_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SPDCMPDIS` reader - No description avaiable"]
        pub type SPDCMPDIS_R = crate::BitReader;
        #[doc = "Field `SPDCMPDIS` writer - No description avaiable"]
        pub type SPDCMPDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCMP` reader - 0- position compare need positive rotation 1- position compare need negative rotation"]
        pub type DIRCMP_R = crate::BitReader;
        #[doc = "Field `DIRCMP` writer - 0- position compare need positive rotation 1- position compare need negative rotation"]
        pub type DIRCMP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DIRCMPDIS` reader - 1- postion compare not include rotation direction"]
        pub type DIRCMPDIS_R = crate::BitReader;
        #[doc = "Field `DIRCMPDIS` writer - 1- postion compare not include rotation direction"]
        pub type DIRCMPDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZCMPDIS` reader - 1- postion compare not include zcnt"]
        pub type ZCMPDIS_R = crate::BitReader;
        #[doc = "Field `ZCMPDIS` writer - 1- postion compare not include zcnt"]
        pub type ZCMPDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 9 - No description avaiable"]
            #[inline(always)]
            pub fn pos_match2_opt(&self) -> POS_MATCH2_OPT_R {
                POS_MATCH2_OPT_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - No description avaiable"]
            #[inline(always)]
            pub fn pos_match2_dir(&self) -> POS_MATCH2_DIR_R {
                POS_MATCH2_DIR_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - No description avaiable"]
            #[inline(always)]
            pub fn phase_match_dis2(&self) -> PHASE_MATCH_DIS2_R {
                PHASE_MATCH_DIS2_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - No description avaiable"]
            #[inline(always)]
            pub fn spdcmp2dis(&self) -> SPDCMP2DIS_R {
                SPDCMP2DIS_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - No description avaiable"]
            #[inline(always)]
            pub fn dircmp2(&self) -> DIRCMP2_R {
                DIRCMP2_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - No description avaiable"]
            #[inline(always)]
            pub fn dircmp2dis(&self) -> DIRCMP2DIS_R {
                DIRCMP2DIS_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - No description avaiable"]
            #[inline(always)]
            pub fn zcmp2dis(&self) -> ZCMP2DIS_R {
                ZCMP2DIS_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn pos_match_opt(&self) -> POS_MATCH_OPT_R {
                POS_MATCH_OPT_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn pos_match_dir(&self) -> POS_MATCH_DIR_R {
                POS_MATCH_DIR_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            pub fn phase_match_dis(&self) -> PHASE_MATCH_DIS_R {
                PHASE_MATCH_DIS_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - No description avaiable"]
            #[inline(always)]
            pub fn spdcmpdis(&self) -> SPDCMPDIS_R {
                SPDCMPDIS_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - 0- position compare need positive rotation 1- position compare need negative rotation"]
            #[inline(always)]
            pub fn dircmp(&self) -> DIRCMP_R {
                DIRCMP_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - 1- postion compare not include rotation direction"]
            #[inline(always)]
            pub fn dircmpdis(&self) -> DIRCMPDIS_R {
                DIRCMPDIS_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - 1- postion compare not include zcnt"]
            #[inline(always)]
            pub fn zcmpdis(&self) -> ZCMPDIS_R {
                ZCMPDIS_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 9 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos_match2_opt(&mut self) -> POS_MATCH2_OPT_W<MATCH_CFG_SPEC> {
                POS_MATCH2_OPT_W::new(self, 9)
            }
            #[doc = "Bit 10 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos_match2_dir(&mut self) -> POS_MATCH2_DIR_W<MATCH_CFG_SPEC> {
                POS_MATCH2_DIR_W::new(self, 10)
            }
            #[doc = "Bit 11 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn phase_match_dis2(&mut self) -> PHASE_MATCH_DIS2_W<MATCH_CFG_SPEC> {
                PHASE_MATCH_DIS2_W::new(self, 11)
            }
            #[doc = "Bit 12 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn spdcmp2dis(&mut self) -> SPDCMP2DIS_W<MATCH_CFG_SPEC> {
                SPDCMP2DIS_W::new(self, 12)
            }
            #[doc = "Bit 13 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dircmp2(&mut self) -> DIRCMP2_W<MATCH_CFG_SPEC> {
                DIRCMP2_W::new(self, 13)
            }
            #[doc = "Bit 14 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dircmp2dis(&mut self) -> DIRCMP2DIS_W<MATCH_CFG_SPEC> {
                DIRCMP2DIS_W::new(self, 14)
            }
            #[doc = "Bit 15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn zcmp2dis(&mut self) -> ZCMP2DIS_W<MATCH_CFG_SPEC> {
                ZCMP2DIS_W::new(self, 15)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos_match_opt(&mut self) -> POS_MATCH_OPT_W<MATCH_CFG_SPEC> {
                POS_MATCH_OPT_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos_match_dir(&mut self) -> POS_MATCH_DIR_W<MATCH_CFG_SPEC> {
                POS_MATCH_DIR_W::new(self, 26)
            }
            #[doc = "Bit 27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn phase_match_dis(&mut self) -> PHASE_MATCH_DIS_W<MATCH_CFG_SPEC> {
                PHASE_MATCH_DIS_W::new(self, 27)
            }
            #[doc = "Bit 28 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn spdcmpdis(&mut self) -> SPDCMPDIS_W<MATCH_CFG_SPEC> {
                SPDCMPDIS_W::new(self, 28)
            }
            #[doc = "Bit 29 - 0- position compare need positive rotation 1- position compare need negative rotation"]
            #[inline(always)]
            #[must_use]
            pub fn dircmp(&mut self) -> DIRCMP_W<MATCH_CFG_SPEC> {
                DIRCMP_W::new(self, 29)
            }
            #[doc = "Bit 30 - 1- postion compare not include rotation direction"]
            #[inline(always)]
            #[must_use]
            pub fn dircmpdis(&mut self) -> DIRCMPDIS_W<MATCH_CFG_SPEC> {
                DIRCMPDIS_W::new(self, 30)
            }
            #[doc = "Bit 31 - 1- postion compare not include zcnt"]
            #[inline(always)]
            #[must_use]
            pub fn zcmpdis(&mut self) -> ZCMPDIS_W<MATCH_CFG_SPEC> {
                ZCMPDIS_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`match_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`match_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MATCH_CFG_SPEC;
        impl crate::RegisterSpec for MATCH_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`match_cfg::R`](R) reader structure"]
        impl crate::Readable for MATCH_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`match_cfg::W`](W) writer structure"]
        impl crate::Writable for MATCH_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets match_cfg to value 0"]
        impl crate::Resettable for MATCH_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "FILT_CFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filt_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filt_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filt_cfg`]
module"]
    pub type FILT_CFG = crate::Reg<filt_cfg::FILT_CFG_SPEC>;
    #[doc = "no description available"]
    pub mod filt_cfg {
        #[doc = "Register `FILT_CFG[%s]` reader"]
        pub type R = crate::R<FILT_CFG_SPEC>;
        #[doc = "Register `FILT_CFG[%s]` writer"]
        pub type W = crate::W<FILT_CFG_SPEC>;
        #[doc = "Field `FILTLEN` reader - This bitfields defines the filter counter length."]
        pub type FILTLEN_R = crate::FieldReader<u16>;
        #[doc = "Field `FILTLEN` writer - This bitfields defines the filter counter length."]
        pub type FILTLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `SYNCEN` reader - set to enable sychronization input signal with TRGM clock"]
        pub type SYNCEN_R = crate::BitReader;
        #[doc = "Field `SYNCEN` writer - set to enable sychronization input signal with TRGM clock"]
        pub type SYNCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MODE` reader - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stable low mode; 111-stable high mode"]
        pub type MODE_R = crate::FieldReader;
        #[doc = "Field `MODE` writer - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stable low mode; 111-stable high mode"]
        pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `OUTINV` reader - 1- Filter will invert the output 0- Filter will not invert the output"]
        pub type OUTINV_R = crate::BitReader;
        #[doc = "Field `OUTINV` writer - 1- Filter will invert the output 0- Filter will not invert the output"]
        pub type OUTINV_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:11 - This bitfields defines the filter counter length."]
            #[inline(always)]
            pub fn filtlen(&self) -> FILTLEN_R {
                FILTLEN_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bit 12 - set to enable sychronization input signal with TRGM clock"]
            #[inline(always)]
            pub fn syncen(&self) -> SYNCEN_R {
                SYNCEN_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bits 13:15 - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stable low mode; 111-stable high mode"]
            #[inline(always)]
            pub fn mode(&self) -> MODE_R {
                MODE_R::new(((self.bits >> 13) & 7) as u8)
            }
            #[doc = "Bit 16 - 1- Filter will invert the output 0- Filter will not invert the output"]
            #[inline(always)]
            pub fn outinv(&self) -> OUTINV_R {
                OUTINV_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - This bitfields defines the filter counter length."]
            #[inline(always)]
            #[must_use]
            pub fn filtlen(&mut self) -> FILTLEN_W<FILT_CFG_SPEC> {
                FILTLEN_W::new(self, 0)
            }
            #[doc = "Bit 12 - set to enable sychronization input signal with TRGM clock"]
            #[inline(always)]
            #[must_use]
            pub fn syncen(&mut self) -> SYNCEN_W<FILT_CFG_SPEC> {
                SYNCEN_W::new(self, 12)
            }
            #[doc = "Bits 13:15 - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stable low mode; 111-stable high mode"]
            #[inline(always)]
            #[must_use]
            pub fn mode(&mut self) -> MODE_W<FILT_CFG_SPEC> {
                MODE_W::new(self, 13)
            }
            #[doc = "Bit 16 - 1- Filter will invert the output 0- Filter will not invert the output"]
            #[inline(always)]
            #[must_use]
            pub fn outinv(&mut self) -> OUTINV_W<FILT_CFG_SPEC> {
                OUTINV_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filt_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filt_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FILT_CFG_SPEC;
        impl crate::RegisterSpec for FILT_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`filt_cfg::R`](R) reader structure"]
        impl crate::Readable for FILT_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`filt_cfg::W`](W) writer structure"]
        impl crate::Writable for FILT_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FILT_CFG[%s]
to value 0"]
        impl crate::Resettable for FILT_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "qei_cfg (rw) register accessor: qei config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qei_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qei_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qei_cfg`]
module"]
    pub type QEI_CFG = crate::Reg<qei_cfg::QEI_CFG_SPEC>;
    #[doc = "qei config register"]
    pub mod qei_cfg {
        #[doc = "Register `qei_cfg` reader"]
        pub type R = crate::R<QEI_CFG_SPEC>;
        #[doc = "Register `qei_cfg` writer"]
        pub type W = crate::W<QEI_CFG_SPEC>;
        #[doc = "Field `SIGA_EN` reader - No description avaiable"]
        pub type SIGA_EN_R = crate::BitReader;
        #[doc = "Field `SIGA_EN` writer - No description avaiable"]
        pub type SIGA_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SIGB_EN` reader - No description avaiable"]
        pub type SIGB_EN_R = crate::BitReader;
        #[doc = "Field `SIGB_EN` writer - No description avaiable"]
        pub type SIGB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SIGZ_EN` reader - No description avaiable"]
        pub type SIGZ_EN_R = crate::BitReader;
        #[doc = "Field `SIGZ_EN` writer - No description avaiable"]
        pub type SIGZ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POSIDGE_EN` reader - No description avaiable"]
        pub type POSIDGE_EN_R = crate::BitReader;
        #[doc = "Field `POSIDGE_EN` writer - No description avaiable"]
        pub type POSIDGE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NEGEDGE_EN` reader - bit4: negedge enable bit3: posedge enable bit2: W in hal enable bit1: signal b(or V in hal) enable bit0: signal a(or U in hal) enable such as: 01001: use posedge A 11010: use both edge of signal B 11111: use both edge of all HAL siganls"]
        pub type NEGEDGE_EN_R = crate::BitReader;
        #[doc = "Field `NEGEDGE_EN` writer - bit4: negedge enable bit3: posedge enable bit2: W in hal enable bit1: signal b(or V in hal) enable bit0: signal a(or U in hal) enable such as: 01001: use posedge A 11010: use both edge of signal B 11111: use both edge of all HAL siganls"]
        pub type NEGEDGE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UVW_POS_OPT0` reader - set to output next area position for QEO use; clr to output exact point position for MMC use"]
        pub type UVW_POS_OPT0_R = crate::BitReader;
        #[doc = "Field `UVW_POS_OPT0` writer - set to output next area position for QEO use; clr to output exact point position for MMC use"]
        pub type UVW_POS_OPT0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SPEED_DIR_CHG_EN` reader - clear counter if detect direction change"]
        pub type SPEED_DIR_CHG_EN_R = crate::BitReader;
        #[doc = "Field `SPEED_DIR_CHG_EN` writer - clear counter if detect direction change"]
        pub type SPEED_DIR_CHG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            pub fn siga_en(&self) -> SIGA_EN_R {
                SIGA_EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn sigb_en(&self) -> SIGB_EN_R {
                SIGB_EN_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            pub fn sigz_en(&self) -> SIGZ_EN_R {
                SIGZ_EN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            pub fn posidge_en(&self) -> POSIDGE_EN_R {
                POSIDGE_EN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - bit4: negedge enable bit3: posedge enable bit2: W in hal enable bit1: signal b(or V in hal) enable bit0: signal a(or U in hal) enable such as: 01001: use posedge A 11010: use both edge of signal B 11111: use both edge of all HAL siganls"]
            #[inline(always)]
            pub fn negedge_en(&self) -> NEGEDGE_EN_R {
                NEGEDGE_EN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - set to output next area position for QEO use; clr to output exact point position for MMC use"]
            #[inline(always)]
            pub fn uvw_pos_opt0(&self) -> UVW_POS_OPT0_R {
                UVW_POS_OPT0_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 12 - clear counter if detect direction change"]
            #[inline(always)]
            pub fn speed_dir_chg_en(&self) -> SPEED_DIR_CHG_EN_R {
                SPEED_DIR_CHG_EN_R::new(((self.bits >> 12) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn siga_en(&mut self) -> SIGA_EN_W<QEI_CFG_SPEC> {
                SIGA_EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn sigb_en(&mut self) -> SIGB_EN_W<QEI_CFG_SPEC> {
                SIGB_EN_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn sigz_en(&mut self) -> SIGZ_EN_W<QEI_CFG_SPEC> {
                SIGZ_EN_W::new(self, 2)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn posidge_en(&mut self) -> POSIDGE_EN_W<QEI_CFG_SPEC> {
                POSIDGE_EN_W::new(self, 3)
            }
            #[doc = "Bit 4 - bit4: negedge enable bit3: posedge enable bit2: W in hal enable bit1: signal b(or V in hal) enable bit0: signal a(or U in hal) enable such as: 01001: use posedge A 11010: use both edge of signal B 11111: use both edge of all HAL siganls"]
            #[inline(always)]
            #[must_use]
            pub fn negedge_en(&mut self) -> NEGEDGE_EN_W<QEI_CFG_SPEC> {
                NEGEDGE_EN_W::new(self, 4)
            }
            #[doc = "Bit 5 - set to output next area position for QEO use; clr to output exact point position for MMC use"]
            #[inline(always)]
            #[must_use]
            pub fn uvw_pos_opt0(&mut self) -> UVW_POS_OPT0_W<QEI_CFG_SPEC> {
                UVW_POS_OPT0_W::new(self, 5)
            }
            #[doc = "Bit 12 - clear counter if detect direction change"]
            #[inline(always)]
            #[must_use]
            pub fn speed_dir_chg_en(&mut self) -> SPEED_DIR_CHG_EN_W<QEI_CFG_SPEC> {
                SPEED_DIR_CHG_EN_W::new(self, 12)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "qei config register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`qei_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`qei_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct QEI_CFG_SPEC;
        impl crate::RegisterSpec for QEI_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`qei_cfg::R`](R) reader structure"]
        impl crate::Readable for QEI_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`qei_cfg::W`](W) writer structure"]
        impl crate::Writable for QEI_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets qei_cfg to value 0"]
        impl crate::Resettable for QEI_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse0_num (rw) register accessor: pulse0_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_num::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse0_num`]
module"]
    pub type PULSE0_NUM = crate::Reg<pulse0_num::PULSE0_NUM_SPEC>;
    #[doc = "pulse0_num"]
    pub mod pulse0_num {
        #[doc = "Register `pulse0_num` reader"]
        pub type R = crate::R<PULSE0_NUM_SPEC>;
        #[doc = "Register `pulse0_num` writer"]
        pub type W = crate::W<PULSE0_NUM_SPEC>;
        #[doc = "Field `PULSE0_NUM` reader - for speed detection, will count the cycle number for configed pulse_num"]
        pub type PULSE0_NUM_R = crate::FieldReader<u32>;
        #[doc = "Field `PULSE0_NUM` writer - for speed detection, will count the cycle number for configed pulse_num"]
        pub type PULSE0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - for speed detection, will count the cycle number for configed pulse_num"]
            #[inline(always)]
            pub fn pulse0_num(&self) -> PULSE0_NUM_R {
                PULSE0_NUM_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - for speed detection, will count the cycle number for configed pulse_num"]
            #[inline(always)]
            #[must_use]
            pub fn pulse0_num(&mut self) -> PULSE0_NUM_W<PULSE0_NUM_SPEC> {
                PULSE0_NUM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse0_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_num::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE0_NUM_SPEC;
        impl crate::RegisterSpec for PULSE0_NUM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse0_num::R`](R) reader structure"]
        impl crate::Readable for PULSE0_NUM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse0_num::W`](W) writer structure"]
        impl crate::Writable for PULSE0_NUM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse0_num to value 0"]
        impl crate::Resettable for PULSE0_NUM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse1_num (rw) register accessor: pulse1_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_num::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse1_num`]
module"]
    pub type PULSE1_NUM = crate::Reg<pulse1_num::PULSE1_NUM_SPEC>;
    #[doc = "pulse1_num"]
    pub mod pulse1_num {
        #[doc = "Register `pulse1_num` reader"]
        pub type R = crate::R<PULSE1_NUM_SPEC>;
        #[doc = "Register `pulse1_num` writer"]
        pub type W = crate::W<PULSE1_NUM_SPEC>;
        #[doc = "Field `PULSE1_NUM` reader - No description avaiable"]
        pub type PULSE1_NUM_R = crate::FieldReader<u32>;
        #[doc = "Field `PULSE1_NUM` writer - No description avaiable"]
        pub type PULSE1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1_num(&self) -> PULSE1_NUM_R {
                PULSE1_NUM_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pulse1_num(&mut self) -> PULSE1_NUM_W<PULSE1_NUM_SPEC> {
                PULSE1_NUM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse1_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_num::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE1_NUM_SPEC;
        impl crate::RegisterSpec for PULSE1_NUM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse1_num::R`](R) reader structure"]
        impl crate::Readable for PULSE1_NUM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse1_num::W`](W) writer structure"]
        impl crate::Writable for PULSE1_NUM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse1_num to value 0"]
        impl crate::Resettable for PULSE1_NUM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle0_cnt (rw) register accessor: cycle0_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle0_cnt`]
module"]
    pub type CYCLE0_CNT = crate::Reg<cycle0_cnt::CYCLE0_CNT_SPEC>;
    #[doc = "cycle0_cnt"]
    pub mod cycle0_cnt {
        #[doc = "Register `cycle0_cnt` reader"]
        pub type R = crate::R<CYCLE0_CNT_SPEC>;
        #[doc = "Register `cycle0_cnt` writer"]
        pub type W = crate::W<CYCLE0_CNT_SPEC>;
        #[doc = "Field `CYCLE0_CNT` reader - No description avaiable"]
        pub type CYCLE0_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0_cnt(&self) -> CYCLE0_CNT_R {
                CYCLE0_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle0_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE0_CNT_SPEC;
        impl crate::RegisterSpec for CYCLE0_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle0_cnt::R`](R) reader structure"]
        impl crate::Readable for CYCLE0_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle0_cnt::W`](W) writer structure"]
        impl crate::Writable for CYCLE0_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle0_cnt to value 0"]
        impl crate::Resettable for CYCLE0_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle0pulse_cnt (rw) register accessor: cycle0pulse_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0pulse_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0pulse_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle0pulse_cnt`]
module"]
    pub type CYCLE0PULSE_CNT = crate::Reg<cycle0pulse_cnt::CYCLE0PULSE_CNT_SPEC>;
    #[doc = "cycle0pulse_cnt"]
    pub mod cycle0pulse_cnt {
        #[doc = "Register `cycle0pulse_cnt` reader"]
        pub type R = crate::R<CYCLE0PULSE_CNT_SPEC>;
        #[doc = "Register `cycle0pulse_cnt` writer"]
        pub type W = crate::W<CYCLE0PULSE_CNT_SPEC>;
        #[doc = "Field `CYCLE0PULSE_CNT` reader - No description avaiable"]
        pub type CYCLE0PULSE_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0pulse_cnt(&self) -> CYCLE0PULSE_CNT_R {
                CYCLE0PULSE_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle0pulse_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0pulse_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0pulse_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE0PULSE_CNT_SPEC;
        impl crate::RegisterSpec for CYCLE0PULSE_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle0pulse_cnt::R`](R) reader structure"]
        impl crate::Readable for CYCLE0PULSE_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle0pulse_cnt::W`](W) writer structure"]
        impl crate::Writable for CYCLE0PULSE_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle0pulse_cnt to value 0"]
        impl crate::Resettable for CYCLE0PULSE_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle1_cnt (rw) register accessor: cycle1_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle1_cnt`]
module"]
    pub type CYCLE1_CNT = crate::Reg<cycle1_cnt::CYCLE1_CNT_SPEC>;
    #[doc = "cycle1_cnt"]
    pub mod cycle1_cnt {
        #[doc = "Register `cycle1_cnt` reader"]
        pub type R = crate::R<CYCLE1_CNT_SPEC>;
        #[doc = "Register `cycle1_cnt` writer"]
        pub type W = crate::W<CYCLE1_CNT_SPEC>;
        #[doc = "Field `CYCLE1_CNT` reader - No description avaiable"]
        pub type CYCLE1_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1_cnt(&self) -> CYCLE1_CNT_R {
                CYCLE1_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle1_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE1_CNT_SPEC;
        impl crate::RegisterSpec for CYCLE1_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle1_cnt::R`](R) reader structure"]
        impl crate::Readable for CYCLE1_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle1_cnt::W`](W) writer structure"]
        impl crate::Writable for CYCLE1_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle1_cnt to value 0"]
        impl crate::Resettable for CYCLE1_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle1pulse_cnt (rw) register accessor: cycle1pulse_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1pulse_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1pulse_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle1pulse_cnt`]
module"]
    pub type CYCLE1PULSE_CNT = crate::Reg<cycle1pulse_cnt::CYCLE1PULSE_CNT_SPEC>;
    #[doc = "cycle1pulse_cnt"]
    pub mod cycle1pulse_cnt {
        #[doc = "Register `cycle1pulse_cnt` reader"]
        pub type R = crate::R<CYCLE1PULSE_CNT_SPEC>;
        #[doc = "Register `cycle1pulse_cnt` writer"]
        pub type W = crate::W<CYCLE1PULSE_CNT_SPEC>;
        #[doc = "Field `CYCLE1PULSE_CNT` reader - No description avaiable"]
        pub type CYCLE1PULSE_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1pulse_cnt(&self) -> CYCLE1PULSE_CNT_R {
                CYCLE1PULSE_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle1pulse_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1pulse_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1pulse_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE1PULSE_CNT_SPEC;
        impl crate::RegisterSpec for CYCLE1PULSE_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle1pulse_cnt::R`](R) reader structure"]
        impl crate::Readable for CYCLE1PULSE_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle1pulse_cnt::W`](W) writer structure"]
        impl crate::Writable for CYCLE1PULSE_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle1pulse_cnt to value 0"]
        impl crate::Resettable for CYCLE1PULSE_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle0_snap0 (rw) register accessor: cycle0_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_snap0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_snap0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle0_snap0`]
module"]
    pub type CYCLE0_SNAP0 = crate::Reg<cycle0_snap0::CYCLE0_SNAP0_SPEC>;
    #[doc = "cycle0_snap0"]
    pub mod cycle0_snap0 {
        #[doc = "Register `cycle0_snap0` reader"]
        pub type R = crate::R<CYCLE0_SNAP0_SPEC>;
        #[doc = "Register `cycle0_snap0` writer"]
        pub type W = crate::W<CYCLE0_SNAP0_SPEC>;
        #[doc = "Field `CYCLE0_SNAP0` reader - No description avaiable"]
        pub type CYCLE0_SNAP0_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0_snap0(&self) -> CYCLE0_SNAP0_R {
                CYCLE0_SNAP0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle0_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_snap0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_snap0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE0_SNAP0_SPEC;
        impl crate::RegisterSpec for CYCLE0_SNAP0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle0_snap0::R`](R) reader structure"]
        impl crate::Readable for CYCLE0_SNAP0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle0_snap0::W`](W) writer structure"]
        impl crate::Writable for CYCLE0_SNAP0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle0_snap0 to value 0"]
        impl crate::Resettable for CYCLE0_SNAP0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle0_snap1 (rw) register accessor: cycle0_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_snap1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_snap1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle0_snap1`]
module"]
    pub type CYCLE0_SNAP1 = crate::Reg<cycle0_snap1::CYCLE0_SNAP1_SPEC>;
    #[doc = "cycle0_snap1"]
    pub mod cycle0_snap1 {
        #[doc = "Register `cycle0_snap1` reader"]
        pub type R = crate::R<CYCLE0_SNAP1_SPEC>;
        #[doc = "Register `cycle0_snap1` writer"]
        pub type W = crate::W<CYCLE0_SNAP1_SPEC>;
        #[doc = "Field `CYCLE0_SNAP1` reader - No description avaiable"]
        pub type CYCLE0_SNAP1_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0_snap1(&self) -> CYCLE0_SNAP1_R {
                CYCLE0_SNAP1_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle0_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_snap1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_snap1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE0_SNAP1_SPEC;
        impl crate::RegisterSpec for CYCLE0_SNAP1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle0_snap1::R`](R) reader structure"]
        impl crate::Readable for CYCLE0_SNAP1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle0_snap1::W`](W) writer structure"]
        impl crate::Writable for CYCLE0_SNAP1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle0_snap1 to value 0"]
        impl crate::Resettable for CYCLE0_SNAP1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle1_snap0 (rw) register accessor: cycle1_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_snap0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_snap0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle1_snap0`]
module"]
    pub type CYCLE1_SNAP0 = crate::Reg<cycle1_snap0::CYCLE1_SNAP0_SPEC>;
    #[doc = "cycle1_snap0"]
    pub mod cycle1_snap0 {
        #[doc = "Register `cycle1_snap0` reader"]
        pub type R = crate::R<CYCLE1_SNAP0_SPEC>;
        #[doc = "Register `cycle1_snap0` writer"]
        pub type W = crate::W<CYCLE1_SNAP0_SPEC>;
        #[doc = "Field `CYCLE1_SNAP0` reader - No description avaiable"]
        pub type CYCLE1_SNAP0_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1_snap0(&self) -> CYCLE1_SNAP0_R {
                CYCLE1_SNAP0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle1_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_snap0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_snap0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE1_SNAP0_SPEC;
        impl crate::RegisterSpec for CYCLE1_SNAP0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle1_snap0::R`](R) reader structure"]
        impl crate::Readable for CYCLE1_SNAP0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle1_snap0::W`](W) writer structure"]
        impl crate::Writable for CYCLE1_SNAP0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle1_snap0 to value 0"]
        impl crate::Resettable for CYCLE1_SNAP0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle1_snap1 (rw) register accessor: cycle1_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_snap1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_snap1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle1_snap1`]
module"]
    pub type CYCLE1_SNAP1 = crate::Reg<cycle1_snap1::CYCLE1_SNAP1_SPEC>;
    #[doc = "cycle1_snap1"]
    pub mod cycle1_snap1 {
        #[doc = "Register `cycle1_snap1` reader"]
        pub type R = crate::R<CYCLE1_SNAP1_SPEC>;
        #[doc = "Register `cycle1_snap1` writer"]
        pub type W = crate::W<CYCLE1_SNAP1_SPEC>;
        #[doc = "Field `CYCLE1_SNAP1` reader - No description avaiable"]
        pub type CYCLE1_SNAP1_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1_snap1(&self) -> CYCLE1_SNAP1_R {
                CYCLE1_SNAP1_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle1_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_snap1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_snap1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE1_SNAP1_SPEC;
        impl crate::RegisterSpec for CYCLE1_SNAP1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle1_snap1::R`](R) reader structure"]
        impl crate::Readable for CYCLE1_SNAP1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle1_snap1::W`](W) writer structure"]
        impl crate::Writable for CYCLE1_SNAP1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle1_snap1 to value 0"]
        impl crate::Resettable for CYCLE1_SNAP1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle0_num (rw) register accessor: cycle0_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_num::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle0_num`]
module"]
    pub type CYCLE0_NUM = crate::Reg<cycle0_num::CYCLE0_NUM_SPEC>;
    #[doc = "cycle0_num"]
    pub mod cycle0_num {
        #[doc = "Register `cycle0_num` reader"]
        pub type R = crate::R<CYCLE0_NUM_SPEC>;
        #[doc = "Register `cycle0_num` writer"]
        pub type W = crate::W<CYCLE0_NUM_SPEC>;
        #[doc = "Field `CYCLE0_NUM` reader - No description avaiable"]
        pub type CYCLE0_NUM_R = crate::FieldReader<u32>;
        #[doc = "Field `CYCLE0_NUM` writer - No description avaiable"]
        pub type CYCLE0_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle0_num(&self) -> CYCLE0_NUM_R {
                CYCLE0_NUM_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle0_num(&mut self) -> CYCLE0_NUM_W<CYCLE0_NUM_SPEC> {
                CYCLE0_NUM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle0_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle0_num::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle0_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE0_NUM_SPEC;
        impl crate::RegisterSpec for CYCLE0_NUM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle0_num::R`](R) reader structure"]
        impl crate::Readable for CYCLE0_NUM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle0_num::W`](W) writer structure"]
        impl crate::Writable for CYCLE0_NUM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle0_num to value 0"]
        impl crate::Resettable for CYCLE0_NUM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cycle1_num (rw) register accessor: cycle1_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_num::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_num::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cycle1_num`]
module"]
    pub type CYCLE1_NUM = crate::Reg<cycle1_num::CYCLE1_NUM_SPEC>;
    #[doc = "cycle1_num"]
    pub mod cycle1_num {
        #[doc = "Register `cycle1_num` reader"]
        pub type R = crate::R<CYCLE1_NUM_SPEC>;
        #[doc = "Register `cycle1_num` writer"]
        pub type W = crate::W<CYCLE1_NUM_SPEC>;
        #[doc = "Field `CYCLE1_NUM` reader - No description avaiable"]
        pub type CYCLE1_NUM_R = crate::FieldReader<u32>;
        #[doc = "Field `CYCLE1_NUM` writer - No description avaiable"]
        pub type CYCLE1_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn cycle1_num(&self) -> CYCLE1_NUM_R {
                CYCLE1_NUM_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cycle1_num(&mut self) -> CYCLE1_NUM_W<CYCLE1_NUM_SPEC> {
                CYCLE1_NUM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cycle1_num\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cycle1_num::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cycle1_num::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CYCLE1_NUM_SPEC;
        impl crate::RegisterSpec for CYCLE1_NUM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cycle1_num::R`](R) reader structure"]
        impl crate::Readable for CYCLE1_NUM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cycle1_num::W`](W) writer structure"]
        impl crate::Writable for CYCLE1_NUM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cycle1_num to value 0"]
        impl crate::Resettable for CYCLE1_NUM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse0_cnt (rw) register accessor: pulse0_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse0_cnt`]
module"]
    pub type PULSE0_CNT = crate::Reg<pulse0_cnt::PULSE0_CNT_SPEC>;
    #[doc = "pulse0_cnt"]
    pub mod pulse0_cnt {
        #[doc = "Register `pulse0_cnt` reader"]
        pub type R = crate::R<PULSE0_CNT_SPEC>;
        #[doc = "Register `pulse0_cnt` writer"]
        pub type W = crate::W<PULSE0_CNT_SPEC>;
        #[doc = "Field `PULSE0_CNT` reader - No description avaiable"]
        pub type PULSE0_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0_cnt(&self) -> PULSE0_CNT_R {
                PULSE0_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse0_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE0_CNT_SPEC;
        impl crate::RegisterSpec for PULSE0_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse0_cnt::R`](R) reader structure"]
        impl crate::Readable for PULSE0_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse0_cnt::W`](W) writer structure"]
        impl crate::Writable for PULSE0_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse0_cnt to value 0"]
        impl crate::Resettable for PULSE0_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse0cycle_cnt (rw) register accessor: pulse0cycle_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0cycle_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0cycle_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse0cycle_cnt`]
module"]
    pub type PULSE0CYCLE_CNT = crate::Reg<pulse0cycle_cnt::PULSE0CYCLE_CNT_SPEC>;
    #[doc = "pulse0cycle_cnt"]
    pub mod pulse0cycle_cnt {
        #[doc = "Register `pulse0cycle_cnt` reader"]
        pub type R = crate::R<PULSE0CYCLE_CNT_SPEC>;
        #[doc = "Register `pulse0cycle_cnt` writer"]
        pub type W = crate::W<PULSE0CYCLE_CNT_SPEC>;
        #[doc = "Field `PULSE0CYCLE_CNT` reader - No description avaiable"]
        pub type PULSE0CYCLE_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0cycle_cnt(&self) -> PULSE0CYCLE_CNT_R {
                PULSE0CYCLE_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse0cycle_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0cycle_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0cycle_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE0CYCLE_CNT_SPEC;
        impl crate::RegisterSpec for PULSE0CYCLE_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse0cycle_cnt::R`](R) reader structure"]
        impl crate::Readable for PULSE0CYCLE_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse0cycle_cnt::W`](W) writer structure"]
        impl crate::Writable for PULSE0CYCLE_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse0cycle_cnt to value 0"]
        impl crate::Resettable for PULSE0CYCLE_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse1_cnt (rw) register accessor: pulse1_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse1_cnt`]
module"]
    pub type PULSE1_CNT = crate::Reg<pulse1_cnt::PULSE1_CNT_SPEC>;
    #[doc = "pulse1_cnt"]
    pub mod pulse1_cnt {
        #[doc = "Register `pulse1_cnt` reader"]
        pub type R = crate::R<PULSE1_CNT_SPEC>;
        #[doc = "Register `pulse1_cnt` writer"]
        pub type W = crate::W<PULSE1_CNT_SPEC>;
        #[doc = "Field `PULSE1_CNT` reader - No description avaiable"]
        pub type PULSE1_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1_cnt(&self) -> PULSE1_CNT_R {
                PULSE1_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse1_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE1_CNT_SPEC;
        impl crate::RegisterSpec for PULSE1_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse1_cnt::R`](R) reader structure"]
        impl crate::Readable for PULSE1_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse1_cnt::W`](W) writer structure"]
        impl crate::Writable for PULSE1_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse1_cnt to value 0"]
        impl crate::Resettable for PULSE1_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse1cycle_cnt (rw) register accessor: pulse1cycle_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1cycle_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1cycle_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse1cycle_cnt`]
module"]
    pub type PULSE1CYCLE_CNT = crate::Reg<pulse1cycle_cnt::PULSE1CYCLE_CNT_SPEC>;
    #[doc = "pulse1cycle_cnt"]
    pub mod pulse1cycle_cnt {
        #[doc = "Register `pulse1cycle_cnt` reader"]
        pub type R = crate::R<PULSE1CYCLE_CNT_SPEC>;
        #[doc = "Register `pulse1cycle_cnt` writer"]
        pub type W = crate::W<PULSE1CYCLE_CNT_SPEC>;
        #[doc = "Field `PULSE1CYCLE_CNT` reader - No description avaiable"]
        pub type PULSE1CYCLE_CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1cycle_cnt(&self) -> PULSE1CYCLE_CNT_R {
                PULSE1CYCLE_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse1cycle_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1cycle_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1cycle_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE1CYCLE_CNT_SPEC;
        impl crate::RegisterSpec for PULSE1CYCLE_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse1cycle_cnt::R`](R) reader structure"]
        impl crate::Readable for PULSE1CYCLE_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse1cycle_cnt::W`](W) writer structure"]
        impl crate::Writable for PULSE1CYCLE_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse1cycle_cnt to value 0"]
        impl crate::Resettable for PULSE1CYCLE_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse0_snap0 (rw) register accessor: pulse0_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_snap0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_snap0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse0_snap0`]
module"]
    pub type PULSE0_SNAP0 = crate::Reg<pulse0_snap0::PULSE0_SNAP0_SPEC>;
    #[doc = "pulse0_snap0"]
    pub mod pulse0_snap0 {
        #[doc = "Register `pulse0_snap0` reader"]
        pub type R = crate::R<PULSE0_SNAP0_SPEC>;
        #[doc = "Register `pulse0_snap0` writer"]
        pub type W = crate::W<PULSE0_SNAP0_SPEC>;
        #[doc = "Field `PULSE0_SNAP0` reader - No description avaiable"]
        pub type PULSE0_SNAP0_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0_snap0(&self) -> PULSE0_SNAP0_R {
                PULSE0_SNAP0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse0_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_snap0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_snap0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE0_SNAP0_SPEC;
        impl crate::RegisterSpec for PULSE0_SNAP0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse0_snap0::R`](R) reader structure"]
        impl crate::Readable for PULSE0_SNAP0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse0_snap0::W`](W) writer structure"]
        impl crate::Writable for PULSE0_SNAP0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse0_snap0 to value 0"]
        impl crate::Resettable for PULSE0_SNAP0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse0cycle_snap0 (rw) register accessor: pulse0cycle_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0cycle_snap0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0cycle_snap0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse0cycle_snap0`]
module"]
    pub type PULSE0CYCLE_SNAP0 = crate::Reg<pulse0cycle_snap0::PULSE0CYCLE_SNAP0_SPEC>;
    #[doc = "pulse0cycle_snap0"]
    pub mod pulse0cycle_snap0 {
        #[doc = "Register `pulse0cycle_snap0` reader"]
        pub type R = crate::R<PULSE0CYCLE_SNAP0_SPEC>;
        #[doc = "Register `pulse0cycle_snap0` writer"]
        pub type W = crate::W<PULSE0CYCLE_SNAP0_SPEC>;
        #[doc = "Field `PULSE0CYCLE_SNAP0` reader - No description avaiable"]
        pub type PULSE0CYCLE_SNAP0_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0cycle_snap0(&self) -> PULSE0CYCLE_SNAP0_R {
                PULSE0CYCLE_SNAP0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse0cycle_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0cycle_snap0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0cycle_snap0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE0CYCLE_SNAP0_SPEC;
        impl crate::RegisterSpec for PULSE0CYCLE_SNAP0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse0cycle_snap0::R`](R) reader structure"]
        impl crate::Readable for PULSE0CYCLE_SNAP0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse0cycle_snap0::W`](W) writer structure"]
        impl crate::Writable for PULSE0CYCLE_SNAP0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse0cycle_snap0 to value 0"]
        impl crate::Resettable for PULSE0CYCLE_SNAP0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse0_snap1 (rw) register accessor: pulse0_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_snap1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_snap1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse0_snap1`]
module"]
    pub type PULSE0_SNAP1 = crate::Reg<pulse0_snap1::PULSE0_SNAP1_SPEC>;
    #[doc = "pulse0_snap1"]
    pub mod pulse0_snap1 {
        #[doc = "Register `pulse0_snap1` reader"]
        pub type R = crate::R<PULSE0_SNAP1_SPEC>;
        #[doc = "Register `pulse0_snap1` writer"]
        pub type W = crate::W<PULSE0_SNAP1_SPEC>;
        #[doc = "Field `PULSE0_SNAP1` reader - No description avaiable"]
        pub type PULSE0_SNAP1_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0_snap1(&self) -> PULSE0_SNAP1_R {
                PULSE0_SNAP1_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse0_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0_snap1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0_snap1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE0_SNAP1_SPEC;
        impl crate::RegisterSpec for PULSE0_SNAP1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse0_snap1::R`](R) reader structure"]
        impl crate::Readable for PULSE0_SNAP1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse0_snap1::W`](W) writer structure"]
        impl crate::Writable for PULSE0_SNAP1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse0_snap1 to value 0"]
        impl crate::Resettable for PULSE0_SNAP1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse0cycle_snap1 (rw) register accessor: pulse0cycle_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0cycle_snap1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0cycle_snap1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse0cycle_snap1`]
module"]
    pub type PULSE0CYCLE_SNAP1 = crate::Reg<pulse0cycle_snap1::PULSE0CYCLE_SNAP1_SPEC>;
    #[doc = "pulse0cycle_snap1"]
    pub mod pulse0cycle_snap1 {
        #[doc = "Register `pulse0cycle_snap1` reader"]
        pub type R = crate::R<PULSE0CYCLE_SNAP1_SPEC>;
        #[doc = "Register `pulse0cycle_snap1` writer"]
        pub type W = crate::W<PULSE0CYCLE_SNAP1_SPEC>;
        #[doc = "Field `PULSE0CYCLE_SNAP1` reader - No description avaiable"]
        pub type PULSE0CYCLE_SNAP1_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse0cycle_snap1(&self) -> PULSE0CYCLE_SNAP1_R {
                PULSE0CYCLE_SNAP1_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse0cycle_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse0cycle_snap1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse0cycle_snap1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE0CYCLE_SNAP1_SPEC;
        impl crate::RegisterSpec for PULSE0CYCLE_SNAP1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse0cycle_snap1::R`](R) reader structure"]
        impl crate::Readable for PULSE0CYCLE_SNAP1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse0cycle_snap1::W`](W) writer structure"]
        impl crate::Writable for PULSE0CYCLE_SNAP1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse0cycle_snap1 to value 0"]
        impl crate::Resettable for PULSE0CYCLE_SNAP1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse1_snap0 (rw) register accessor: pulse1_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_snap0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_snap0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse1_snap0`]
module"]
    pub type PULSE1_SNAP0 = crate::Reg<pulse1_snap0::PULSE1_SNAP0_SPEC>;
    #[doc = "pulse1_snap0"]
    pub mod pulse1_snap0 {
        #[doc = "Register `pulse1_snap0` reader"]
        pub type R = crate::R<PULSE1_SNAP0_SPEC>;
        #[doc = "Register `pulse1_snap0` writer"]
        pub type W = crate::W<PULSE1_SNAP0_SPEC>;
        #[doc = "Field `PULSE1_SNAP0` reader - No description avaiable"]
        pub type PULSE1_SNAP0_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1_snap0(&self) -> PULSE1_SNAP0_R {
                PULSE1_SNAP0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse1_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_snap0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_snap0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE1_SNAP0_SPEC;
        impl crate::RegisterSpec for PULSE1_SNAP0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse1_snap0::R`](R) reader structure"]
        impl crate::Readable for PULSE1_SNAP0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse1_snap0::W`](W) writer structure"]
        impl crate::Writable for PULSE1_SNAP0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse1_snap0 to value 0"]
        impl crate::Resettable for PULSE1_SNAP0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse1cycle_snap0 (rw) register accessor: pulse1cycle_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1cycle_snap0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1cycle_snap0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse1cycle_snap0`]
module"]
    pub type PULSE1CYCLE_SNAP0 = crate::Reg<pulse1cycle_snap0::PULSE1CYCLE_SNAP0_SPEC>;
    #[doc = "pulse1cycle_snap0"]
    pub mod pulse1cycle_snap0 {
        #[doc = "Register `pulse1cycle_snap0` reader"]
        pub type R = crate::R<PULSE1CYCLE_SNAP0_SPEC>;
        #[doc = "Register `pulse1cycle_snap0` writer"]
        pub type W = crate::W<PULSE1CYCLE_SNAP0_SPEC>;
        #[doc = "Field `PULSE1CYCLE_SNAP0` reader - No description avaiable"]
        pub type PULSE1CYCLE_SNAP0_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1cycle_snap0(&self) -> PULSE1CYCLE_SNAP0_R {
                PULSE1CYCLE_SNAP0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse1cycle_snap0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1cycle_snap0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1cycle_snap0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE1CYCLE_SNAP0_SPEC;
        impl crate::RegisterSpec for PULSE1CYCLE_SNAP0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse1cycle_snap0::R`](R) reader structure"]
        impl crate::Readable for PULSE1CYCLE_SNAP0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse1cycle_snap0::W`](W) writer structure"]
        impl crate::Writable for PULSE1CYCLE_SNAP0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse1cycle_snap0 to value 0"]
        impl crate::Resettable for PULSE1CYCLE_SNAP0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse1_snap1 (rw) register accessor: pulse1_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_snap1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_snap1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse1_snap1`]
module"]
    pub type PULSE1_SNAP1 = crate::Reg<pulse1_snap1::PULSE1_SNAP1_SPEC>;
    #[doc = "pulse1_snap1"]
    pub mod pulse1_snap1 {
        #[doc = "Register `pulse1_snap1` reader"]
        pub type R = crate::R<PULSE1_SNAP1_SPEC>;
        #[doc = "Register `pulse1_snap1` writer"]
        pub type W = crate::W<PULSE1_SNAP1_SPEC>;
        #[doc = "Field `PULSE1_SNAP1` reader - No description avaiable"]
        pub type PULSE1_SNAP1_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1_snap1(&self) -> PULSE1_SNAP1_R {
                PULSE1_SNAP1_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse1_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1_snap1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1_snap1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE1_SNAP1_SPEC;
        impl crate::RegisterSpec for PULSE1_SNAP1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse1_snap1::R`](R) reader structure"]
        impl crate::Readable for PULSE1_SNAP1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse1_snap1::W`](W) writer structure"]
        impl crate::Writable for PULSE1_SNAP1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse1_snap1 to value 0"]
        impl crate::Resettable for PULSE1_SNAP1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pulse1cycle_snap1 (rw) register accessor: pulse1cycle_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1cycle_snap1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1cycle_snap1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pulse1cycle_snap1`]
module"]
    pub type PULSE1CYCLE_SNAP1 = crate::Reg<pulse1cycle_snap1::PULSE1CYCLE_SNAP1_SPEC>;
    #[doc = "pulse1cycle_snap1"]
    pub mod pulse1cycle_snap1 {
        #[doc = "Register `pulse1cycle_snap1` reader"]
        pub type R = crate::R<PULSE1CYCLE_SNAP1_SPEC>;
        #[doc = "Register `pulse1cycle_snap1` writer"]
        pub type W = crate::W<PULSE1CYCLE_SNAP1_SPEC>;
        #[doc = "Field `PULSE1CYCLE_SNAP1` reader - No description avaiable"]
        pub type PULSE1CYCLE_SNAP1_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pulse1cycle_snap1(&self) -> PULSE1CYCLE_SNAP1_R {
                PULSE1CYCLE_SNAP1_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pulse1cycle_snap1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pulse1cycle_snap1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pulse1cycle_snap1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PULSE1CYCLE_SNAP1_SPEC;
        impl crate::RegisterSpec for PULSE1CYCLE_SNAP1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pulse1cycle_snap1::R`](R) reader structure"]
        impl crate::Readable for PULSE1CYCLE_SNAP1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pulse1cycle_snap1::W`](W) writer structure"]
        impl crate::Writable for PULSE1CYCLE_SNAP1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pulse1cycle_snap1 to value 0"]
        impl crate::Resettable for PULSE1CYCLE_SNAP1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adcx_cfg0 (rw) register accessor: adcx_cfg0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcx_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcx_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcx_cfg0`]
module"]
    pub type ADCX_CFG0 = crate::Reg<adcx_cfg0::ADCX_CFG0_SPEC>;
    #[doc = "adcx_cfg0"]
    pub mod adcx_cfg0 {
        #[doc = "Register `adcx_cfg0` reader"]
        pub type R = crate::R<ADCX_CFG0_SPEC>;
        #[doc = "Register `adcx_cfg0` writer"]
        pub type W = crate::W<ADCX_CFG0_SPEC>;
        #[doc = "Field `X_CHAN` reader - No description avaiable"]
        pub type X_CHAN_R = crate::FieldReader;
        #[doc = "Field `X_CHAN` writer - No description avaiable"]
        pub type X_CHAN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `X_ADC_ENABLE` reader - No description avaiable"]
        pub type X_ADC_ENABLE_R = crate::BitReader;
        #[doc = "Field `X_ADC_ENABLE` writer - No description avaiable"]
        pub type X_ADC_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `X_ADCSEL` reader - No description avaiable"]
        pub type X_ADCSEL_R = crate::BitReader;
        #[doc = "Field `X_ADCSEL` writer - No description avaiable"]
        pub type X_ADCSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:4 - No description avaiable"]
            #[inline(always)]
            pub fn x_chan(&self) -> X_CHAN_R {
                X_CHAN_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            pub fn x_adc_enable(&self) -> X_ADC_ENABLE_R {
                X_ADC_ENABLE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            pub fn x_adcsel(&self) -> X_ADCSEL_R {
                X_ADCSEL_R::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn x_chan(&mut self) -> X_CHAN_W<ADCX_CFG0_SPEC> {
                X_CHAN_W::new(self, 0)
            }
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn x_adc_enable(&mut self) -> X_ADC_ENABLE_W<ADCX_CFG0_SPEC> {
                X_ADC_ENABLE_W::new(self, 7)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn x_adcsel(&mut self) -> X_ADCSEL_W<ADCX_CFG0_SPEC> {
                X_ADCSEL_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "adcx_cfg0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcx_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcx_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADCX_CFG0_SPEC;
        impl crate::RegisterSpec for ADCX_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adcx_cfg0::R`](R) reader structure"]
        impl crate::Readable for ADCX_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adcx_cfg0::W`](W) writer structure"]
        impl crate::Writable for ADCX_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adcx_cfg0 to value 0"]
        impl crate::Resettable for ADCX_CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adcx_cfg1 (rw) register accessor: adcx_cfg1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcx_cfg1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcx_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcx_cfg1`]
module"]
    pub type ADCX_CFG1 = crate::Reg<adcx_cfg1::ADCX_CFG1_SPEC>;
    #[doc = "adcx_cfg1"]
    pub mod adcx_cfg1 {
        #[doc = "Register `adcx_cfg1` reader"]
        pub type R = crate::R<ADCX_CFG1_SPEC>;
        #[doc = "Register `adcx_cfg1` writer"]
        pub type W = crate::W<ADCX_CFG1_SPEC>;
        #[doc = "Field `X_PARAM0` reader - No description avaiable"]
        pub type X_PARAM0_R = crate::FieldReader<u16>;
        #[doc = "Field `X_PARAM0` writer - No description avaiable"]
        pub type X_PARAM0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `X_PARAM1` reader - No description avaiable"]
        pub type X_PARAM1_R = crate::FieldReader<u16>;
        #[doc = "Field `X_PARAM1` writer - No description avaiable"]
        pub type X_PARAM1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            pub fn x_param0(&self) -> X_PARAM0_R {
                X_PARAM0_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - No description avaiable"]
            #[inline(always)]
            pub fn x_param1(&self) -> X_PARAM1_R {
                X_PARAM1_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn x_param0(&mut self) -> X_PARAM0_W<ADCX_CFG1_SPEC> {
                X_PARAM0_W::new(self, 0)
            }
            #[doc = "Bits 16:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn x_param1(&mut self) -> X_PARAM1_W<ADCX_CFG1_SPEC> {
                X_PARAM1_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "adcx_cfg1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcx_cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcx_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADCX_CFG1_SPEC;
        impl crate::RegisterSpec for ADCX_CFG1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adcx_cfg1::R`](R) reader structure"]
        impl crate::Readable for ADCX_CFG1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adcx_cfg1::W`](W) writer structure"]
        impl crate::Writable for ADCX_CFG1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adcx_cfg1 to value 0"]
        impl crate::Resettable for ADCX_CFG1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adcx_cfg2 (rw) register accessor: adcx_cfg2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcx_cfg2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcx_cfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcx_cfg2`]
module"]
    pub type ADCX_CFG2 = crate::Reg<adcx_cfg2::ADCX_CFG2_SPEC>;
    #[doc = "adcx_cfg2"]
    pub mod adcx_cfg2 {
        #[doc = "Register `adcx_cfg2` reader"]
        pub type R = crate::R<ADCX_CFG2_SPEC>;
        #[doc = "Register `adcx_cfg2` writer"]
        pub type W = crate::W<ADCX_CFG2_SPEC>;
        #[doc = "Field `X_OFFSET` reader - No description avaiable"]
        pub type X_OFFSET_R = crate::FieldReader<u32>;
        #[doc = "Field `X_OFFSET` writer - No description avaiable"]
        pub type X_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn x_offset(&self) -> X_OFFSET_R {
                X_OFFSET_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn x_offset(&mut self) -> X_OFFSET_W<ADCX_CFG2_SPEC> {
                X_OFFSET_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "adcx_cfg2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcx_cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcx_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADCX_CFG2_SPEC;
        impl crate::RegisterSpec for ADCX_CFG2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adcx_cfg2::R`](R) reader structure"]
        impl crate::Readable for ADCX_CFG2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adcx_cfg2::W`](W) writer structure"]
        impl crate::Writable for ADCX_CFG2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adcx_cfg2 to value 0"]
        impl crate::Resettable for ADCX_CFG2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adcy_cfg0 (rw) register accessor: adcy_cfg0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcy_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcy_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcy_cfg0`]
module"]
    pub type ADCY_CFG0 = crate::Reg<adcy_cfg0::ADCY_CFG0_SPEC>;
    #[doc = "adcy_cfg0"]
    pub mod adcy_cfg0 {
        #[doc = "Register `adcy_cfg0` reader"]
        pub type R = crate::R<ADCY_CFG0_SPEC>;
        #[doc = "Register `adcy_cfg0` writer"]
        pub type W = crate::W<ADCY_CFG0_SPEC>;
        #[doc = "Field `Y_CHAN` reader - No description avaiable"]
        pub type Y_CHAN_R = crate::FieldReader;
        #[doc = "Field `Y_CHAN` writer - No description avaiable"]
        pub type Y_CHAN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `Y_ADC_ENABLE` reader - No description avaiable"]
        pub type Y_ADC_ENABLE_R = crate::BitReader;
        #[doc = "Field `Y_ADC_ENABLE` writer - No description avaiable"]
        pub type Y_ADC_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `Y_ADCSEL` reader - No description avaiable"]
        pub type Y_ADCSEL_R = crate::BitReader;
        #[doc = "Field `Y_ADCSEL` writer - No description avaiable"]
        pub type Y_ADCSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:4 - No description avaiable"]
            #[inline(always)]
            pub fn y_chan(&self) -> Y_CHAN_R {
                Y_CHAN_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            pub fn y_adc_enable(&self) -> Y_ADC_ENABLE_R {
                Y_ADC_ENABLE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            pub fn y_adcsel(&self) -> Y_ADCSEL_R {
                Y_ADCSEL_R::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn y_chan(&mut self) -> Y_CHAN_W<ADCY_CFG0_SPEC> {
                Y_CHAN_W::new(self, 0)
            }
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn y_adc_enable(&mut self) -> Y_ADC_ENABLE_W<ADCY_CFG0_SPEC> {
                Y_ADC_ENABLE_W::new(self, 7)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn y_adcsel(&mut self) -> Y_ADCSEL_W<ADCY_CFG0_SPEC> {
                Y_ADCSEL_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "adcy_cfg0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcy_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcy_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADCY_CFG0_SPEC;
        impl crate::RegisterSpec for ADCY_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adcy_cfg0::R`](R) reader structure"]
        impl crate::Readable for ADCY_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adcy_cfg0::W`](W) writer structure"]
        impl crate::Writable for ADCY_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adcy_cfg0 to value 0"]
        impl crate::Resettable for ADCY_CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adcy_cfg1 (rw) register accessor: adcy_cfg1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcy_cfg1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcy_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcy_cfg1`]
module"]
    pub type ADCY_CFG1 = crate::Reg<adcy_cfg1::ADCY_CFG1_SPEC>;
    #[doc = "adcy_cfg1"]
    pub mod adcy_cfg1 {
        #[doc = "Register `adcy_cfg1` reader"]
        pub type R = crate::R<ADCY_CFG1_SPEC>;
        #[doc = "Register `adcy_cfg1` writer"]
        pub type W = crate::W<ADCY_CFG1_SPEC>;
        #[doc = "Field `Y_PARAM0` reader - No description avaiable"]
        pub type Y_PARAM0_R = crate::FieldReader<u16>;
        #[doc = "Field `Y_PARAM0` writer - No description avaiable"]
        pub type Y_PARAM0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `Y_PARAM1` reader - No description avaiable"]
        pub type Y_PARAM1_R = crate::FieldReader<u16>;
        #[doc = "Field `Y_PARAM1` writer - No description avaiable"]
        pub type Y_PARAM1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            pub fn y_param0(&self) -> Y_PARAM0_R {
                Y_PARAM0_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - No description avaiable"]
            #[inline(always)]
            pub fn y_param1(&self) -> Y_PARAM1_R {
                Y_PARAM1_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn y_param0(&mut self) -> Y_PARAM0_W<ADCY_CFG1_SPEC> {
                Y_PARAM0_W::new(self, 0)
            }
            #[doc = "Bits 16:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn y_param1(&mut self) -> Y_PARAM1_W<ADCY_CFG1_SPEC> {
                Y_PARAM1_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "adcy_cfg1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcy_cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcy_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADCY_CFG1_SPEC;
        impl crate::RegisterSpec for ADCY_CFG1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adcy_cfg1::R`](R) reader structure"]
        impl crate::Readable for ADCY_CFG1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adcy_cfg1::W`](W) writer structure"]
        impl crate::Writable for ADCY_CFG1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adcy_cfg1 to value 0"]
        impl crate::Resettable for ADCY_CFG1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adcy_cfg2 (rw) register accessor: adcy_cfg2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcy_cfg2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcy_cfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcy_cfg2`]
module"]
    pub type ADCY_CFG2 = crate::Reg<adcy_cfg2::ADCY_CFG2_SPEC>;
    #[doc = "adcy_cfg2"]
    pub mod adcy_cfg2 {
        #[doc = "Register `adcy_cfg2` reader"]
        pub type R = crate::R<ADCY_CFG2_SPEC>;
        #[doc = "Register `adcy_cfg2` writer"]
        pub type W = crate::W<ADCY_CFG2_SPEC>;
        #[doc = "Field `Y_OFFSET` reader - No description avaiable"]
        pub type Y_OFFSET_R = crate::FieldReader<u32>;
        #[doc = "Field `Y_OFFSET` writer - No description avaiable"]
        pub type Y_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn y_offset(&self) -> Y_OFFSET_R {
                Y_OFFSET_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn y_offset(&mut self) -> Y_OFFSET_W<ADCY_CFG2_SPEC> {
                Y_OFFSET_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "adcy_cfg2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcy_cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcy_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADCY_CFG2_SPEC;
        impl crate::RegisterSpec for ADCY_CFG2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adcy_cfg2::R`](R) reader structure"]
        impl crate::Readable for ADCY_CFG2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adcy_cfg2::W`](W) writer structure"]
        impl crate::Writable for ADCY_CFG2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adcy_cfg2 to value 0"]
        impl crate::Resettable for ADCY_CFG2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cal_cfg (rw) register accessor: cal_cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cal_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cal_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cal_cfg`]
module"]
    pub type CAL_CFG = crate::Reg<cal_cfg::CAL_CFG_SPEC>;
    #[doc = "cal_cfg"]
    pub mod cal_cfg {
        #[doc = "Register `cal_cfg` reader"]
        pub type R = crate::R<CAL_CFG_SPEC>;
        #[doc = "Register `cal_cfg` writer"]
        pub type W = crate::W<CAL_CFG_SPEC>;
        #[doc = "Field `XY_DELAY` reader - valid x/y delay, larger than this delay will be treated as invalid data. Default 1.25us@200MHz; max 80ms;"]
        pub type XY_DELAY_R = crate::FieldReader<u32>;
        #[doc = "Field `XY_DELAY` writer - valid x/y delay, larger than this delay will be treated as invalid data. Default 1.25us@200MHz; max 80ms;"]
        pub type XY_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 0:23 - valid x/y delay, larger than this delay will be treated as invalid data. Default 1.25us@200MHz; max 80ms;"]
            #[inline(always)]
            pub fn xy_delay(&self) -> XY_DELAY_R {
                XY_DELAY_R::new(self.bits & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - valid x/y delay, larger than this delay will be treated as invalid data. Default 1.25us@200MHz; max 80ms;"]
            #[inline(always)]
            #[must_use]
            pub fn xy_delay(&mut self) -> XY_DELAY_W<CAL_CFG_SPEC> {
                XY_DELAY_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "cal_cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cal_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cal_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CAL_CFG_SPEC;
        impl crate::RegisterSpec for CAL_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cal_cfg::R`](R) reader structure"]
        impl crate::Readable for CAL_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cal_cfg::W`](W) writer structure"]
        impl crate::Writable for CAL_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cal_cfg to value 0"]
        impl crate::Resettable for CAL_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "phase_param (rw) register accessor: phase_param\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_param::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_param::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_param`]
module"]
    pub type PHASE_PARAM = crate::Reg<phase_param::PHASE_PARAM_SPEC>;
    #[doc = "phase_param"]
    pub mod phase_param {
        #[doc = "Register `phase_param` reader"]
        pub type R = crate::R<PHASE_PARAM_SPEC>;
        #[doc = "Register `phase_param` writer"]
        pub type W = crate::W<PHASE_PARAM_SPEC>;
        #[doc = "Field `PHASE_PARAM` reader - No description avaiable"]
        pub type PHASE_PARAM_R = crate::FieldReader<u32>;
        #[doc = "Field `PHASE_PARAM` writer - No description avaiable"]
        pub type PHASE_PARAM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn phase_param(&self) -> PHASE_PARAM_R {
                PHASE_PARAM_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn phase_param(&mut self) -> PHASE_PARAM_W<PHASE_PARAM_SPEC> {
                PHASE_PARAM_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "phase_param\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_param::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_param::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHASE_PARAM_SPEC;
        impl crate::RegisterSpec for PHASE_PARAM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phase_param::R`](R) reader structure"]
        impl crate::Readable for PHASE_PARAM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phase_param::W`](W) writer structure"]
        impl crate::Writable for PHASE_PARAM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets phase_param to value 0"]
        impl crate::Resettable for PHASE_PARAM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "angle_adj (rw) register accessor: angle_adj\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`angle_adj::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`angle_adj::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@angle_adj`]
module"]
    pub type ANGLE_ADJ = crate::Reg<angle_adj::ANGLE_ADJ_SPEC>;
    #[doc = "angle_adj"]
    pub mod angle_adj {
        #[doc = "Register `angle_adj` reader"]
        pub type R = crate::R<ANGLE_ADJ_SPEC>;
        #[doc = "Register `angle_adj` writer"]
        pub type W = crate::W<ANGLE_ADJ_SPEC>;
        #[doc = "Field `ANGLE_ADJ` reader - No description avaiable"]
        pub type ANGLE_ADJ_R = crate::FieldReader<u32>;
        #[doc = "Field `ANGLE_ADJ` writer - No description avaiable"]
        pub type ANGLE_ADJ_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn angle_adj(&self) -> ANGLE_ADJ_R {
                ANGLE_ADJ_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn angle_adj(&mut self) -> ANGLE_ADJ_W<ANGLE_ADJ_SPEC> {
                ANGLE_ADJ_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "angle_adj\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`angle_adj::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`angle_adj::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ANGLE_ADJ_SPEC;
        impl crate::RegisterSpec for ANGLE_ADJ_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`angle_adj::R`](R) reader structure"]
        impl crate::Readable for ANGLE_ADJ_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`angle_adj::W`](W) writer structure"]
        impl crate::Writable for ANGLE_ADJ_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets angle_adj to value 0"]
        impl crate::Resettable for ANGLE_ADJ_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pos_threshold (rw) register accessor: pos_threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_threshold::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_threshold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_threshold`]
module"]
    pub type POS_THRESHOLD = crate::Reg<pos_threshold::POS_THRESHOLD_SPEC>;
    #[doc = "pos_threshold"]
    pub mod pos_threshold {
        #[doc = "Register `pos_threshold` reader"]
        pub type R = crate::R<POS_THRESHOLD_SPEC>;
        #[doc = "Register `pos_threshold` writer"]
        pub type W = crate::W<POS_THRESHOLD_SPEC>;
        #[doc = "Field `POS_THRESHOLD` reader - No description avaiable"]
        pub type POS_THRESHOLD_R = crate::FieldReader<u32>;
        #[doc = "Field `POS_THRESHOLD` writer - No description avaiable"]
        pub type POS_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pos_threshold(&self) -> POS_THRESHOLD_R {
                POS_THRESHOLD_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos_threshold(&mut self) -> POS_THRESHOLD_W<POS_THRESHOLD_SPEC> {
                POS_THRESHOLD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pos_threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_threshold::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_threshold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POS_THRESHOLD_SPEC;
        impl crate::RegisterSpec for POS_THRESHOLD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pos_threshold::R`](R) reader structure"]
        impl crate::Readable for POS_THRESHOLD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pos_threshold::W`](W) writer structure"]
        impl crate::Writable for POS_THRESHOLD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pos_threshold to value 0"]
        impl crate::Resettable for POS_THRESHOLD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "UVW_POS (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uvw_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uvw_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uvw_pos`]
module"]
    pub type UVW_POS = crate::Reg<uvw_pos::UVW_POS_SPEC>;
    #[doc = "no description available"]
    pub mod uvw_pos {
        #[doc = "Register `UVW_POS[%s]` reader"]
        pub type R = crate::R<UVW_POS_SPEC>;
        #[doc = "Register `UVW_POS[%s]` writer"]
        pub type W = crate::W<UVW_POS_SPEC>;
        #[doc = "Field `UVW_POS0` reader - No description avaiable"]
        pub type UVW_POS0_R = crate::FieldReader<u32>;
        #[doc = "Field `UVW_POS0` writer - No description avaiable"]
        pub type UVW_POS0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn uvw_pos0(&self) -> UVW_POS0_R {
                UVW_POS0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn uvw_pos0(&mut self) -> UVW_POS0_W<UVW_POS_SPEC> {
                UVW_POS0_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uvw_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uvw_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UVW_POS_SPEC;
        impl crate::RegisterSpec for UVW_POS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`uvw_pos::R`](R) reader structure"]
        impl crate::Readable for UVW_POS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`uvw_pos::W`](W) writer structure"]
        impl crate::Writable for UVW_POS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets UVW_POS[%s]
to value 0"]
        impl crate::Resettable for UVW_POS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "UVW_POS_CFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uvw_pos_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uvw_pos_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uvw_pos_cfg`]
module"]
    pub type UVW_POS_CFG = crate::Reg<uvw_pos_cfg::UVW_POS_CFG_SPEC>;
    #[doc = "no description available"]
    pub mod uvw_pos_cfg {
        #[doc = "Register `UVW_POS_CFG[%s]` reader"]
        pub type R = crate::R<UVW_POS_CFG_SPEC>;
        #[doc = "Register `UVW_POS_CFG[%s]` writer"]
        pub type W = crate::W<UVW_POS_CFG_SPEC>;
        #[doc = "Field `W_POS_SEL` reader - No description avaiable"]
        pub type W_POS_SEL_R = crate::FieldReader;
        #[doc = "Field `W_POS_SEL` writer - No description avaiable"]
        pub type W_POS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `V_POS_SEL` reader - No description avaiable"]
        pub type V_POS_SEL_R = crate::FieldReader;
        #[doc = "Field `V_POS_SEL` writer - No description avaiable"]
        pub type V_POS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `U_POS_SEL` reader - No description avaiable"]
        pub type U_POS_SEL_R = crate::FieldReader;
        #[doc = "Field `U_POS_SEL` writer - No description avaiable"]
        pub type U_POS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `POS_EN` reader - No description avaiable"]
        pub type POS_EN_R = crate::BitReader;
        #[doc = "Field `POS_EN` writer - No description avaiable"]
        pub type POS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1 - No description avaiable"]
            #[inline(always)]
            pub fn w_pos_sel(&self) -> W_POS_SEL_R {
                W_POS_SEL_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bits 2:3 - No description avaiable"]
            #[inline(always)]
            pub fn v_pos_sel(&self) -> V_POS_SEL_R {
                V_POS_SEL_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bits 4:5 - No description avaiable"]
            #[inline(always)]
            pub fn u_pos_sel(&self) -> U_POS_SEL_R {
                U_POS_SEL_R::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bit 6 - No description avaiable"]
            #[inline(always)]
            pub fn pos_en(&self) -> POS_EN_R {
                POS_EN_R::new(((self.bits >> 6) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn w_pos_sel(&mut self) -> W_POS_SEL_W<UVW_POS_CFG_SPEC> {
                W_POS_SEL_W::new(self, 0)
            }
            #[doc = "Bits 2:3 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn v_pos_sel(&mut self) -> V_POS_SEL_W<UVW_POS_CFG_SPEC> {
                V_POS_SEL_W::new(self, 2)
            }
            #[doc = "Bits 4:5 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn u_pos_sel(&mut self) -> U_POS_SEL_W<UVW_POS_CFG_SPEC> {
                U_POS_SEL_W::new(self, 4)
            }
            #[doc = "Bit 6 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pos_en(&mut self) -> POS_EN_W<UVW_POS_CFG_SPEC> {
                POS_EN_W::new(self, 6)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uvw_pos_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uvw_pos_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UVW_POS_CFG_SPEC;
        impl crate::RegisterSpec for UVW_POS_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`uvw_pos_cfg::R`](R) reader structure"]
        impl crate::Readable for UVW_POS_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`uvw_pos_cfg::W`](W) writer structure"]
        impl crate::Writable for UVW_POS_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets UVW_POS_CFG[%s]
to value 0"]
        impl crate::Resettable for UVW_POS_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "phase_cnt (rw) register accessor: phase_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_cnt`]
module"]
    pub type PHASE_CNT = crate::Reg<phase_cnt::PHASE_CNT_SPEC>;
    #[doc = "phase_cnt"]
    pub mod phase_cnt {
        #[doc = "Register `phase_cnt` reader"]
        pub type R = crate::R<PHASE_CNT_SPEC>;
        #[doc = "Register `phase_cnt` writer"]
        pub type W = crate::W<PHASE_CNT_SPEC>;
        #[doc = "Field `PHASE_CNT` reader - No description avaiable"]
        pub type PHASE_CNT_R = crate::FieldReader<u32>;
        #[doc = "Field `PHASE_CNT` writer - No description avaiable"]
        pub type PHASE_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn phase_cnt(&self) -> PHASE_CNT_R {
                PHASE_CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn phase_cnt(&mut self) -> PHASE_CNT_W<PHASE_CNT_SPEC> {
                PHASE_CNT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "phase_cnt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHASE_CNT_SPEC;
        impl crate::RegisterSpec for PHASE_CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phase_cnt::R`](R) reader structure"]
        impl crate::Readable for PHASE_CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phase_cnt::W`](W) writer structure"]
        impl crate::Writable for PHASE_CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets phase_cnt to value 0"]
        impl crate::Resettable for PHASE_CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "phase_update (rw) register accessor: phase_update\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_update::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_update::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_update`]
module"]
    pub type PHASE_UPDATE = crate::Reg<phase_update::PHASE_UPDATE_SPEC>;
    #[doc = "phase_update"]
    pub mod phase_update {
        #[doc = "Register `phase_update` reader"]
        pub type R = crate::R<PHASE_UPDATE_SPEC>;
        #[doc = "Register `phase_update` writer"]
        pub type W = crate::W<PHASE_UPDATE_SPEC>;
        #[doc = "Field `VALUE` writer - value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation"]
        pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
        #[doc = "Field `DEC` writer - set to minus value from phase_cnt(set inc and dec same time willl act inc)"]
        pub type DEC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INC` writer - set to add value to phase_cnt"]
        pub type INC_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bits 0:29 - value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation"]
            #[inline(always)]
            #[must_use]
            pub fn value(&mut self) -> VALUE_W<PHASE_UPDATE_SPEC> {
                VALUE_W::new(self, 0)
            }
            #[doc = "Bit 30 - set to minus value from phase_cnt(set inc and dec same time willl act inc)"]
            #[inline(always)]
            #[must_use]
            pub fn dec(&mut self) -> DEC_W<PHASE_UPDATE_SPEC> {
                DEC_W::new(self, 30)
            }
            #[doc = "Bit 31 - set to add value to phase_cnt"]
            #[inline(always)]
            #[must_use]
            pub fn inc(&mut self) -> INC_W<PHASE_UPDATE_SPEC> {
                INC_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "phase_update\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_update::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_update::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHASE_UPDATE_SPEC;
        impl crate::RegisterSpec for PHASE_UPDATE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phase_update::R`](R) reader structure"]
        impl crate::Readable for PHASE_UPDATE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phase_update::W`](W) writer structure"]
        impl crate::Writable for PHASE_UPDATE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets phase_update to value 0"]
        impl crate::Resettable for PHASE_UPDATE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "position (rw) register accessor: position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`position::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`position::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@position`]
module"]
    pub type POSITION = crate::Reg<position::POSITION_SPEC>;
    #[doc = "position"]
    pub mod position {
        #[doc = "Register `position` reader"]
        pub type R = crate::R<POSITION_SPEC>;
        #[doc = "Register `position` writer"]
        pub type W = crate::W<POSITION_SPEC>;
        #[doc = "Field `POSITION` reader - No description avaiable"]
        pub type POSITION_R = crate::FieldReader<u32>;
        #[doc = "Field `POSITION` writer - No description avaiable"]
        pub type POSITION_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn position(&self) -> POSITION_R {
                POSITION_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn position(&mut self) -> POSITION_W<POSITION_SPEC> {
                POSITION_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`position::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`position::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POSITION_SPEC;
        impl crate::RegisterSpec for POSITION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`position::R`](R) reader structure"]
        impl crate::Readable for POSITION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`position::W`](W) writer structure"]
        impl crate::Writable for POSITION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets position to value 0"]
        impl crate::Resettable for POSITION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "position_update (rw) register accessor: position_update\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`position_update::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`position_update::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@position_update`]
module"]
    pub type POSITION_UPDATE = crate::Reg<position_update::POSITION_UPDATE_SPEC>;
    #[doc = "position_update"]
    pub mod position_update {
        #[doc = "Register `position_update` reader"]
        pub type R = crate::R<POSITION_UPDATE_SPEC>;
        #[doc = "Register `position_update` writer"]
        pub type W = crate::W<POSITION_UPDATE_SPEC>;
        #[doc = "Field `VALUE` writer - value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation"]
        pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
        #[doc = "Field `DEC` writer - set to minus value from position(set inc and dec same time willl act inc)"]
        pub type DEC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INC` writer - set to add value to position"]
        pub type INC_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bits 0:29 - value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation"]
            #[inline(always)]
            #[must_use]
            pub fn value(&mut self) -> VALUE_W<POSITION_UPDATE_SPEC> {
                VALUE_W::new(self, 0)
            }
            #[doc = "Bit 30 - set to minus value from position(set inc and dec same time willl act inc)"]
            #[inline(always)]
            #[must_use]
            pub fn dec(&mut self) -> DEC_W<POSITION_UPDATE_SPEC> {
                DEC_W::new(self, 30)
            }
            #[doc = "Bit 31 - set to add value to position"]
            #[inline(always)]
            #[must_use]
            pub fn inc(&mut self) -> INC_W<POSITION_UPDATE_SPEC> {
                INC_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "position_update\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`position_update::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`position_update::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POSITION_UPDATE_SPEC;
        impl crate::RegisterSpec for POSITION_UPDATE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`position_update::R`](R) reader structure"]
        impl crate::Readable for POSITION_UPDATE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`position_update::W`](W) writer structure"]
        impl crate::Writable for POSITION_UPDATE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets position_update to value 0"]
        impl crate::Resettable for POSITION_UPDATE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "angle (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`angle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`angle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@angle`]
module"]
    pub type ANGLE = crate::Reg<angle::ANGLE_SPEC>;
    #[doc = "No description avaiable"]
    pub mod angle {
        #[doc = "Register `angle` reader"]
        pub type R = crate::R<ANGLE_SPEC>;
        #[doc = "Register `angle` writer"]
        pub type W = crate::W<ANGLE_SPEC>;
        #[doc = "Field `ANGLE` reader - No description avaiable"]
        pub type ANGLE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn angle(&self) -> ANGLE_R {
                ANGLE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`angle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`angle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ANGLE_SPEC;
        impl crate::RegisterSpec for ANGLE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`angle::R`](R) reader structure"]
        impl crate::Readable for ANGLE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`angle::W`](W) writer structure"]
        impl crate::Writable for ANGLE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets angle to value 0"]
        impl crate::Resettable for ANGLE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pos_timeout (rw) register accessor: pos_timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_timeout::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_timeout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_timeout`]
module"]
    pub type POS_TIMEOUT = crate::Reg<pos_timeout::POS_TIMEOUT_SPEC>;
    #[doc = "pos_timeout"]
    pub mod pos_timeout {
        #[doc = "Register `pos_timeout` reader"]
        pub type R = crate::R<POS_TIMEOUT_SPEC>;
        #[doc = "Register `pos_timeout` writer"]
        pub type W = crate::W<POS_TIMEOUT_SPEC>;
        #[doc = "Field `TIMEOUT` reader - postion timeout value"]
        pub type TIMEOUT_R = crate::FieldReader<u32>;
        #[doc = "Field `TIMEOUT` writer - postion timeout value"]
        pub type TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>;
        #[doc = "Field `ENABLE` reader - enable position timeout feature, if timeout, send valid again"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `ENABLE` writer - enable position timeout feature, if timeout, send valid again"]
        pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:30 - postion timeout value"]
            #[inline(always)]
            pub fn timeout(&self) -> TIMEOUT_R {
                TIMEOUT_R::new(self.bits & 0x7fff_ffff)
            }
            #[doc = "Bit 31 - enable position timeout feature, if timeout, send valid again"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:30 - postion timeout value"]
            #[inline(always)]
            #[must_use]
            pub fn timeout(&mut self) -> TIMEOUT_W<POS_TIMEOUT_SPEC> {
                TIMEOUT_W::new(self, 0)
            }
            #[doc = "Bit 31 - enable position timeout feature, if timeout, send valid again"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<POS_TIMEOUT_SPEC> {
                ENABLE_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pos_timeout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_timeout::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_timeout::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POS_TIMEOUT_SPEC;
        impl crate::RegisterSpec for POS_TIMEOUT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pos_timeout::R`](R) reader structure"]
        impl crate::Readable for POS_TIMEOUT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pos_timeout::W`](W) writer structure"]
        impl crate::Writable for POS_TIMEOUT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pos_timeout to value 0"]
        impl crate::Resettable for POS_TIMEOUT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "QEI1"]
pub struct QEI1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for QEI1 {}
impl QEI1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const qei0::RegisterBlock = 0xf030_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const qei0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for QEI1 {
    type Target = qei0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for QEI1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("QEI1").finish()
    }
}
#[doc = "QEI1"]
pub use self::qei0 as qei1;
#[doc = "QEO0"]
pub struct QEO0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for QEO0 {}
impl QEO0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const qeo0::RegisterBlock = 0xf030_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const qeo0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for QEO0 {
    type Target = qeo0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for QEO0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("QEO0").finish()
    }
}
#[doc = "QEO0"]
pub mod qeo0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        wave_mode: WAVE_MODE,
        wave_resolution: WAVE_RESOLUTION,
        phase_shift_wave: [PHASE_SHIFT_WAVE; 3],
        vd_vq_inject: [VD_VQ_INJECT; 3],
        vd_vq_load: VD_VQ_LOAD,
        amplitude: [AMPLITUDE; 3],
        mid_point: [MID_POINT; 3],
        limit: [LIMIT; 3],
        deadzone_shift: [DEADZONE_SHIFT; 3],
        abz_mode: ABZ_MODE,
        abz_resolution: ABZ_RESOLUTION,
        phase_shift_abz: [PHASE_SHIFT_ABZ; 3],
        line_width: LINE_WIDTH,
        wdog_width: WDOG_WIDTH,
        postion_sync: POSTION_SYNC,
        mode: MODE,
        resolution: RESOLUTION,
        phase_shift: [PHASE_SHIFT; 4],
        phase_table: [PHASE_TABLE; 24],
        postion_software: POSTION_SOFTWARE,
        postion_sel: POSTION_SEL,
        status: STATUS,
        debug0: DEBUG0,
        debug1: DEBUG1,
        debug2: DEBUG2,
        debug3: DEBUG3,
    }
    impl RegisterBlock {
        #[doc = "0x00 - analog waves mode"]
        #[inline(always)]
        pub const fn wave_mode(&self) -> &WAVE_MODE {
            &self.wave_mode
        }
        #[doc = "0x04 - resolution of wave0/1/2"]
        #[inline(always)]
        pub const fn wave_resolution(&self) -> &WAVE_RESOLUTION {
            &self.wave_resolution
        }
        #[doc = "0x08..0x14 - no description available"]
        #[inline(always)]
        pub const fn phase_shift_wave(&self, n: usize) -> &PHASE_SHIFT_WAVE {
            &self.phase_shift_wave[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x08..0x14 - no description available"]
        #[inline(always)]
        pub fn phase_shift_wave_iter(&self) -> impl Iterator<Item = &PHASE_SHIFT_WAVE> {
            self.phase_shift_wave.iter()
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn phase_shift_wavewave0(&self) -> &PHASE_SHIFT_WAVE {
            self.phase_shift_wave(0)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn phase_shift_wavewave1(&self) -> &PHASE_SHIFT_WAVE {
            self.phase_shift_wave(1)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn phase_shift_wavewave2(&self) -> &PHASE_SHIFT_WAVE {
            self.phase_shift_wave(2)
        }
        #[doc = "0x14..0x20 - no description available"]
        #[inline(always)]
        pub const fn vd_vq_inject(&self, n: usize) -> &VD_VQ_INJECT {
            &self.vd_vq_inject[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x14..0x20 - no description available"]
        #[inline(always)]
        pub fn vd_vq_inject_iter(&self) -> impl Iterator<Item = &VD_VQ_INJECT> {
            self.vd_vq_inject.iter()
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn vd_vq_injectwave0(&self) -> &VD_VQ_INJECT {
            self.vd_vq_inject(0)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn vd_vq_injectwave1(&self) -> &VD_VQ_INJECT {
            self.vd_vq_inject(1)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn vd_vq_injectwave2(&self) -> &VD_VQ_INJECT {
            self.vd_vq_inject(2)
        }
        #[doc = "0x20 - load wave0/1/2 vd vq value"]
        #[inline(always)]
        pub const fn vd_vq_load(&self) -> &VD_VQ_LOAD {
            &self.vd_vq_load
        }
        #[doc = "0x24..0x30 - no description available"]
        #[inline(always)]
        pub const fn amplitude(&self, n: usize) -> &AMPLITUDE {
            &self.amplitude[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x24..0x30 - no description available"]
        #[inline(always)]
        pub fn amplitude_iter(&self) -> impl Iterator<Item = &AMPLITUDE> {
            self.amplitude.iter()
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn amplitudewave0(&self) -> &AMPLITUDE {
            self.amplitude(0)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn amplitudewave1(&self) -> &AMPLITUDE {
            self.amplitude(1)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn amplitudewave2(&self) -> &AMPLITUDE {
            self.amplitude(2)
        }
        #[doc = "0x30..0x3c - no description available"]
        #[inline(always)]
        pub const fn mid_point(&self, n: usize) -> &MID_POINT {
            &self.mid_point[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x30..0x3c - no description available"]
        #[inline(always)]
        pub fn mid_point_iter(&self) -> impl Iterator<Item = &MID_POINT> {
            self.mid_point.iter()
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn mid_pointwave0(&self) -> &MID_POINT {
            self.mid_point(0)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn mid_pointwave1(&self) -> &MID_POINT {
            self.mid_point(1)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn mid_pointwave2(&self) -> &MID_POINT {
            self.mid_point(2)
        }
        #[doc = "0x3c..0x54 - no description available"]
        #[inline(always)]
        pub const fn limit(&self, n: usize) -> &LIMIT {
            &self.limit[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x3c..0x54 - no description available"]
        #[inline(always)]
        pub fn limit_iter(&self) -> impl Iterator<Item = &LIMIT> {
            self.limit.iter()
        }
        #[doc = "0x3c..0x44 - no description available"]
        #[inline(always)]
        pub const fn limitwave0(&self) -> &LIMIT {
            self.limit(0)
        }
        #[doc = "0x44..0x4c - no description available"]
        #[inline(always)]
        pub const fn limitwave1(&self) -> &LIMIT {
            self.limit(1)
        }
        #[doc = "0x4c..0x54 - no description available"]
        #[inline(always)]
        pub const fn limitwave2(&self) -> &LIMIT {
            self.limit(2)
        }
        #[doc = "0x54..0x60 - no description available"]
        #[inline(always)]
        pub const fn deadzone_shift(&self, n: usize) -> &DEADZONE_SHIFT {
            &self.deadzone_shift[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x54..0x60 - no description available"]
        #[inline(always)]
        pub fn deadzone_shift_iter(&self) -> impl Iterator<Item = &DEADZONE_SHIFT> {
            self.deadzone_shift.iter()
        }
        #[doc = "0x54 - no description available"]
        #[inline(always)]
        pub const fn deadzone_shiftwave0(&self) -> &DEADZONE_SHIFT {
            self.deadzone_shift(0)
        }
        #[doc = "0x58 - no description available"]
        #[inline(always)]
        pub const fn deadzone_shiftwave1(&self) -> &DEADZONE_SHIFT {
            self.deadzone_shift(1)
        }
        #[doc = "0x5c - no description available"]
        #[inline(always)]
        pub const fn deadzone_shiftwave2(&self) -> &DEADZONE_SHIFT {
            self.deadzone_shift(2)
        }
        #[doc = "0x60 - wave_a/b/z output mode"]
        #[inline(always)]
        pub const fn abz_mode(&self) -> &ABZ_MODE {
            &self.abz_mode
        }
        #[doc = "0x64 - resolution of wave_a/b/z"]
        #[inline(always)]
        pub const fn abz_resolution(&self) -> &ABZ_RESOLUTION {
            &self.abz_resolution
        }
        #[doc = "0x68..0x74 - no description available"]
        #[inline(always)]
        pub const fn phase_shift_abz(&self, n: usize) -> &PHASE_SHIFT_ABZ {
            &self.phase_shift_abz[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x68..0x74 - no description available"]
        #[inline(always)]
        pub fn phase_shift_abz_iter(&self) -> impl Iterator<Item = &PHASE_SHIFT_ABZ> {
            self.phase_shift_abz.iter()
        }
        #[doc = "0x68 - no description available"]
        #[inline(always)]
        pub const fn phase_shift_abza(&self) -> &PHASE_SHIFT_ABZ {
            self.phase_shift_abz(0)
        }
        #[doc = "0x6c - no description available"]
        #[inline(always)]
        pub const fn phase_shift_abzb(&self) -> &PHASE_SHIFT_ABZ {
            self.phase_shift_abz(1)
        }
        #[doc = "0x70 - no description available"]
        #[inline(always)]
        pub const fn phase_shift_abzz(&self) -> &PHASE_SHIFT_ABZ {
            self.phase_shift_abz(2)
        }
        #[doc = "0x74 - Two-phase orthogonality wave 1/4 period"]
        #[inline(always)]
        pub const fn line_width(&self) -> &LINE_WIDTH {
            &self.line_width
        }
        #[doc = "0x78 - wdog width of qeo"]
        #[inline(always)]
        pub const fn wdog_width(&self) -> &WDOG_WIDTH {
            &self.wdog_width
        }
        #[doc = "0x7c - sync abz owned postion"]
        #[inline(always)]
        pub const fn postion_sync(&self) -> &POSTION_SYNC {
            &self.postion_sync
        }
        #[doc = "0x80 - pwm mode"]
        #[inline(always)]
        pub const fn mode(&self) -> &MODE {
            &self.mode
        }
        #[doc = "0x84 - resolution of pwm"]
        #[inline(always)]
        pub const fn resolution(&self) -> &RESOLUTION {
            &self.resolution
        }
        #[doc = "0x88..0x98 - no description available"]
        #[inline(always)]
        pub const fn phase_shift(&self, n: usize) -> &PHASE_SHIFT {
            &self.phase_shift[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x88..0x98 - no description available"]
        #[inline(always)]
        pub fn phase_shift_iter(&self) -> impl Iterator<Item = &PHASE_SHIFT> {
            self.phase_shift.iter()
        }
        #[doc = "0x88 - no description available"]
        #[inline(always)]
        pub const fn phase_shifta(&self) -> &PHASE_SHIFT {
            self.phase_shift(0)
        }
        #[doc = "0x8c - no description available"]
        #[inline(always)]
        pub const fn phase_shiftb(&self) -> &PHASE_SHIFT {
            self.phase_shift(1)
        }
        #[doc = "0x90 - no description available"]
        #[inline(always)]
        pub const fn phase_shiftc(&self) -> &PHASE_SHIFT {
            self.phase_shift(2)
        }
        #[doc = "0x94 - no description available"]
        #[inline(always)]
        pub const fn phase_shiftd(&self) -> &PHASE_SHIFT {
            self.phase_shift(3)
        }
        #[doc = "0x98..0xf8 - no description available"]
        #[inline(always)]
        pub const fn phase_table(&self, n: usize) -> &PHASE_TABLE {
            &self.phase_table[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x98..0xf8 - no description available"]
        #[inline(always)]
        pub fn phase_table_iter(&self) -> impl Iterator<Item = &PHASE_TABLE> {
            self.phase_table.iter()
        }
        #[doc = "0x98 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge0(&self) -> &PHASE_TABLE {
            self.phase_table(0)
        }
        #[doc = "0x9c - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge1(&self) -> &PHASE_TABLE {
            self.phase_table(1)
        }
        #[doc = "0xa0 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge2(&self) -> &PHASE_TABLE {
            self.phase_table(2)
        }
        #[doc = "0xa4 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge3(&self) -> &PHASE_TABLE {
            self.phase_table(3)
        }
        #[doc = "0xa8 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge4(&self) -> &PHASE_TABLE {
            self.phase_table(4)
        }
        #[doc = "0xac - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge5(&self) -> &PHASE_TABLE {
            self.phase_table(5)
        }
        #[doc = "0xb0 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge6(&self) -> &PHASE_TABLE {
            self.phase_table(6)
        }
        #[doc = "0xb4 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge7(&self) -> &PHASE_TABLE {
            self.phase_table(7)
        }
        #[doc = "0xb8 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge8(&self) -> &PHASE_TABLE {
            self.phase_table(8)
        }
        #[doc = "0xbc - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge9(&self) -> &PHASE_TABLE {
            self.phase_table(9)
        }
        #[doc = "0xc0 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge10(&self) -> &PHASE_TABLE {
            self.phase_table(10)
        }
        #[doc = "0xc4 - no description available"]
        #[inline(always)]
        pub const fn phase_tableposedge11(&self) -> &PHASE_TABLE {
            self.phase_table(11)
        }
        #[doc = "0xc8 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge0(&self) -> &PHASE_TABLE {
            self.phase_table(12)
        }
        #[doc = "0xcc - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge1(&self) -> &PHASE_TABLE {
            self.phase_table(13)
        }
        #[doc = "0xd0 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge2(&self) -> &PHASE_TABLE {
            self.phase_table(14)
        }
        #[doc = "0xd4 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge3(&self) -> &PHASE_TABLE {
            self.phase_table(15)
        }
        #[doc = "0xd8 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge4(&self) -> &PHASE_TABLE {
            self.phase_table(16)
        }
        #[doc = "0xdc - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge5(&self) -> &PHASE_TABLE {
            self.phase_table(17)
        }
        #[doc = "0xe0 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge6(&self) -> &PHASE_TABLE {
            self.phase_table(18)
        }
        #[doc = "0xe4 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge7(&self) -> &PHASE_TABLE {
            self.phase_table(19)
        }
        #[doc = "0xe8 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge8(&self) -> &PHASE_TABLE {
            self.phase_table(20)
        }
        #[doc = "0xec - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge9(&self) -> &PHASE_TABLE {
            self.phase_table(21)
        }
        #[doc = "0xf0 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge10(&self) -> &PHASE_TABLE {
            self.phase_table(22)
        }
        #[doc = "0xf4 - no description available"]
        #[inline(always)]
        pub const fn phase_tablenegedge11(&self) -> &PHASE_TABLE {
            self.phase_table(23)
        }
        #[doc = "0xf8 - softwave inject postion"]
        #[inline(always)]
        pub const fn postion_software(&self) -> &POSTION_SOFTWARE {
            &self.postion_software
        }
        #[doc = "0xfc - select softwave inject postion"]
        #[inline(always)]
        pub const fn postion_sel(&self) -> &POSTION_SEL {
            &self.postion_sel
        }
        #[doc = "0x100 - qeo status"]
        #[inline(always)]
        pub const fn status(&self) -> &STATUS {
            &self.status
        }
        #[doc = "0x104 - qeo debug 0"]
        #[inline(always)]
        pub const fn debug0(&self) -> &DEBUG0 {
            &self.debug0
        }
        #[doc = "0x108 - qeo debug 1"]
        #[inline(always)]
        pub const fn debug1(&self) -> &DEBUG1 {
            &self.debug1
        }
        #[doc = "0x10c - qeo debug 2"]
        #[inline(always)]
        pub const fn debug2(&self) -> &DEBUG2 {
            &self.debug2
        }
        #[doc = "0x110 - qeo debug 3"]
        #[inline(always)]
        pub const fn debug3(&self) -> &DEBUG3 {
            &self.debug3
        }
    }
    #[doc = "wave_mode (rw) register accessor: analog waves mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wave_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wave_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wave_mode`]
module"]
    pub type WAVE_MODE = crate::Reg<wave_mode::WAVE_MODE_SPEC>;
    #[doc = "analog waves mode"]
    pub mod wave_mode {
        #[doc = "Register `wave_mode` reader"]
        pub type R = crate::R<WAVE_MODE_SPEC>;
        #[doc = "Register `wave_mode` writer"]
        pub type W = crate::W<WAVE_MODE_SPEC>;
        #[doc = "Field `WAVES_OUTPUT_TYPE` reader - wave0/1/2 output mode. 0: cosine wave. 1: saddle wave. 2. abs cosine wave. 3. saw wave"]
        pub type WAVES_OUTPUT_TYPE_R = crate::FieldReader;
        #[doc = "Field `WAVES_OUTPUT_TYPE` writer - wave0/1/2 output mode. 0: cosine wave. 1: saddle wave. 2. abs cosine wave. 3. saw wave"]
        pub type WAVES_OUTPUT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `EN_WAVE0_VD_VQ_INJECT` reader - wave0 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
        pub type EN_WAVE0_VD_VQ_INJECT_R = crate::BitReader;
        #[doc = "Field `EN_WAVE0_VD_VQ_INJECT` writer - wave0 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
        pub type EN_WAVE0_VD_VQ_INJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_WAVE1_VD_VQ_INJECT` reader - wave1 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
        pub type EN_WAVE1_VD_VQ_INJECT_R = crate::BitReader;
        #[doc = "Field `EN_WAVE1_VD_VQ_INJECT` writer - wave1 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
        pub type EN_WAVE1_VD_VQ_INJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_WAVE2_VD_VQ_INJECT` reader - wave2 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
        pub type EN_WAVE2_VD_VQ_INJECT_R = crate::BitReader;
        #[doc = "Field `EN_WAVE2_VD_VQ_INJECT` writer - wave2 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
        pub type EN_WAVE2_VD_VQ_INJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SADDLE_TYPE` reader - saddle type seclect; 0:standard saddle. 1: triple-cos saddle."]
        pub type SADDLE_TYPE_R = crate::BitReader;
        #[doc = "Field `SADDLE_TYPE` writer - saddle type seclect; 0:standard saddle. 1: triple-cos saddle."]
        pub type SADDLE_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE0_BELOW_MIN_LIMIT` reader - wave0 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit0.level1_min_limit"]
        pub type WAVE0_BELOW_MIN_LIMIT_R = crate::FieldReader;
        #[doc = "Field `WAVE0_BELOW_MIN_LIMIT` writer - wave0 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit0.level1_min_limit"]
        pub type WAVE0_BELOW_MIN_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `WAVE0_LOW_AREA0_LIMIT` reader - wave0 low area0 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
        pub type WAVE0_LOW_AREA0_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE0_LOW_AREA0_LIMIT` writer - wave0 low area0 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
        pub type WAVE0_LOW_AREA0_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE0_LOW_AREA1_LIMIT` reader - wave0 low area1 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
        pub type WAVE0_LOW_AREA1_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE0_LOW_AREA1_LIMIT` writer - wave0 low area1 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
        pub type WAVE0_LOW_AREA1_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE0_HIGH_AREA0_LIMIT` reader - wave0 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
        pub type WAVE0_HIGH_AREA0_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE0_HIGH_AREA0_LIMIT` writer - wave0 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
        pub type WAVE0_HIGH_AREA0_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE0_HIGH_AREA1_LIMIT` reader - wave0 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
        pub type WAVE0_HIGH_AREA1_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE0_HIGH_AREA1_LIMIT` writer - wave0 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
        pub type WAVE0_HIGH_AREA1_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE0_ABOVE_MAX_LIMIT` reader - wave0 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit0.level0_max_limit"]
        pub type WAVE0_ABOVE_MAX_LIMIT_R = crate::FieldReader;
        #[doc = "Field `WAVE0_ABOVE_MAX_LIMIT` writer - wave0 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit0.level0_max_limit"]
        pub type WAVE0_ABOVE_MAX_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `WAVE1_BELOW_MIN_LIMIT` reader - wave1 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit1.level1_min_limit"]
        pub type WAVE1_BELOW_MIN_LIMIT_R = crate::FieldReader;
        #[doc = "Field `WAVE1_BELOW_MIN_LIMIT` writer - wave1 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit1.level1_min_limit"]
        pub type WAVE1_BELOW_MIN_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `WAVE1_LOW_AREA0_LIMIT` reader - wave1 low area0 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
        pub type WAVE1_LOW_AREA0_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE1_LOW_AREA0_LIMIT` writer - wave1 low area0 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
        pub type WAVE1_LOW_AREA0_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE1_LOW_AREA1_LIMIT` reader - wave1 low area1 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
        pub type WAVE1_LOW_AREA1_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE1_LOW_AREA1_LIMIT` writer - wave1 low area1 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
        pub type WAVE1_LOW_AREA1_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE1_HIGH_AREA0_LIMIT` reader - wave1 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
        pub type WAVE1_HIGH_AREA0_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE1_HIGH_AREA0_LIMIT` writer - wave1 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
        pub type WAVE1_HIGH_AREA0_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE1_HIGH_AREA1_LIMIT` reader - wave1 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
        pub type WAVE1_HIGH_AREA1_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE1_HIGH_AREA1_LIMIT` writer - wave1 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
        pub type WAVE1_HIGH_AREA1_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE1_ABOVE_MAX_LIMIT` reader - wave1 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit1.level0_max_limit"]
        pub type WAVE1_ABOVE_MAX_LIMIT_R = crate::FieldReader;
        #[doc = "Field `WAVE1_ABOVE_MAX_LIMIT` writer - wave1 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit1.level0_max_limit"]
        pub type WAVE1_ABOVE_MAX_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `WAVE2_BELOW_MIN_LIMIT` reader - wave2 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit2.level1_min_limit"]
        pub type WAVE2_BELOW_MIN_LIMIT_R = crate::FieldReader;
        #[doc = "Field `WAVE2_BELOW_MIN_LIMIT` writer - wave2 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit2.level1_min_limit"]
        pub type WAVE2_BELOW_MIN_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `WAVE2_LOW_AREA0_LIMIT` reader - wave2 low area0 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
        pub type WAVE2_LOW_AREA0_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE2_LOW_AREA0_LIMIT` writer - wave2 low area0 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
        pub type WAVE2_LOW_AREA0_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE2_LOW_AREA1_LIMIT` reader - wave2 low area1 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
        pub type WAVE2_LOW_AREA1_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE2_LOW_AREA1_LIMIT` writer - wave2 low area1 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
        pub type WAVE2_LOW_AREA1_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE2_HIGH_AREA0_LIMIT` reader - wave2 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
        pub type WAVE2_HIGH_AREA0_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE2_HIGH_AREA0_LIMIT` writer - wave2 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
        pub type WAVE2_HIGH_AREA0_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE2_HIGH_AREA1_LIMIT` reader - wave2 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
        pub type WAVE2_HIGH_AREA1_LIMIT_R = crate::BitReader;
        #[doc = "Field `WAVE2_HIGH_AREA1_LIMIT` writer - wave2 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
        pub type WAVE2_HIGH_AREA1_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WAVE2_ABOVE_MAX_LIMIT` reader - wave2 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit2.level0_max_limit"]
        pub type WAVE2_ABOVE_MAX_LIMIT_R = crate::FieldReader;
        #[doc = "Field `WAVE2_ABOVE_MAX_LIMIT` writer - wave2 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit2.level0_max_limit"]
        pub type WAVE2_ABOVE_MAX_LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bits 0:1 - wave0/1/2 output mode. 0: cosine wave. 1: saddle wave. 2. abs cosine wave. 3. saw wave"]
            #[inline(always)]
            pub fn waves_output_type(&self) -> WAVES_OUTPUT_TYPE_R {
                WAVES_OUTPUT_TYPE_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 4 - wave0 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
            #[inline(always)]
            pub fn en_wave0_vd_vq_inject(&self) -> EN_WAVE0_VD_VQ_INJECT_R {
                EN_WAVE0_VD_VQ_INJECT_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - wave1 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
            #[inline(always)]
            pub fn en_wave1_vd_vq_inject(&self) -> EN_WAVE1_VD_VQ_INJECT_R {
                EN_WAVE1_VD_VQ_INJECT_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - wave2 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
            #[inline(always)]
            pub fn en_wave2_vd_vq_inject(&self) -> EN_WAVE2_VD_VQ_INJECT_R {
                EN_WAVE2_VD_VQ_INJECT_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - saddle type seclect; 0:standard saddle. 1: triple-cos saddle."]
            #[inline(always)]
            pub fn saddle_type(&self) -> SADDLE_TYPE_R {
                SADDLE_TYPE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:9 - wave0 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit0.level1_min_limit"]
            #[inline(always)]
            pub fn wave0_below_min_limit(&self) -> WAVE0_BELOW_MIN_LIMIT_R {
                WAVE0_BELOW_MIN_LIMIT_R::new(((self.bits >> 8) & 3) as u8)
            }
            #[doc = "Bit 10 - wave0 low area0 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
            #[inline(always)]
            pub fn wave0_low_area0_limit(&self) -> WAVE0_LOW_AREA0_LIMIT_R {
                WAVE0_LOW_AREA0_LIMIT_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - wave0 low area1 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
            #[inline(always)]
            pub fn wave0_low_area1_limit(&self) -> WAVE0_LOW_AREA1_LIMIT_R {
                WAVE0_LOW_AREA1_LIMIT_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - wave0 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
            #[inline(always)]
            pub fn wave0_high_area0_limit(&self) -> WAVE0_HIGH_AREA0_LIMIT_R {
                WAVE0_HIGH_AREA0_LIMIT_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - wave0 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
            #[inline(always)]
            pub fn wave0_high_area1_limit(&self) -> WAVE0_HIGH_AREA1_LIMIT_R {
                WAVE0_HIGH_AREA1_LIMIT_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bits 14:15 - wave0 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit0.level0_max_limit"]
            #[inline(always)]
            pub fn wave0_above_max_limit(&self) -> WAVE0_ABOVE_MAX_LIMIT_R {
                WAVE0_ABOVE_MAX_LIMIT_R::new(((self.bits >> 14) & 3) as u8)
            }
            #[doc = "Bits 16:17 - wave1 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit1.level1_min_limit"]
            #[inline(always)]
            pub fn wave1_below_min_limit(&self) -> WAVE1_BELOW_MIN_LIMIT_R {
                WAVE1_BELOW_MIN_LIMIT_R::new(((self.bits >> 16) & 3) as u8)
            }
            #[doc = "Bit 18 - wave1 low area0 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
            #[inline(always)]
            pub fn wave1_low_area0_limit(&self) -> WAVE1_LOW_AREA0_LIMIT_R {
                WAVE1_LOW_AREA0_LIMIT_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - wave1 low area1 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
            #[inline(always)]
            pub fn wave1_low_area1_limit(&self) -> WAVE1_LOW_AREA1_LIMIT_R {
                WAVE1_LOW_AREA1_LIMIT_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - wave1 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
            #[inline(always)]
            pub fn wave1_high_area0_limit(&self) -> WAVE1_HIGH_AREA0_LIMIT_R {
                WAVE1_HIGH_AREA0_LIMIT_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - wave1 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
            #[inline(always)]
            pub fn wave1_high_area1_limit(&self) -> WAVE1_HIGH_AREA1_LIMIT_R {
                WAVE1_HIGH_AREA1_LIMIT_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bits 22:23 - wave1 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit1.level0_max_limit"]
            #[inline(always)]
            pub fn wave1_above_max_limit(&self) -> WAVE1_ABOVE_MAX_LIMIT_R {
                WAVE1_ABOVE_MAX_LIMIT_R::new(((self.bits >> 22) & 3) as u8)
            }
            #[doc = "Bits 24:25 - wave2 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit2.level1_min_limit"]
            #[inline(always)]
            pub fn wave2_below_min_limit(&self) -> WAVE2_BELOW_MIN_LIMIT_R {
                WAVE2_BELOW_MIN_LIMIT_R::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bit 26 - wave2 low area0 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
            #[inline(always)]
            pub fn wave2_low_area0_limit(&self) -> WAVE2_LOW_AREA0_LIMIT_R {
                WAVE2_LOW_AREA0_LIMIT_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - wave2 low area1 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
            #[inline(always)]
            pub fn wave2_low_area1_limit(&self) -> WAVE2_LOW_AREA1_LIMIT_R {
                WAVE2_LOW_AREA1_LIMIT_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - wave2 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
            #[inline(always)]
            pub fn wave2_high_area0_limit(&self) -> WAVE2_HIGH_AREA0_LIMIT_R {
                WAVE2_HIGH_AREA0_LIMIT_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - wave2 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
            #[inline(always)]
            pub fn wave2_high_area1_limit(&self) -> WAVE2_HIGH_AREA1_LIMIT_R {
                WAVE2_HIGH_AREA1_LIMIT_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bits 30:31 - wave2 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit2.level0_max_limit"]
            #[inline(always)]
            pub fn wave2_above_max_limit(&self) -> WAVE2_ABOVE_MAX_LIMIT_R {
                WAVE2_ABOVE_MAX_LIMIT_R::new(((self.bits >> 30) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - wave0/1/2 output mode. 0: cosine wave. 1: saddle wave. 2. abs cosine wave. 3. saw wave"]
            #[inline(always)]
            #[must_use]
            pub fn waves_output_type(&mut self) -> WAVES_OUTPUT_TYPE_W<WAVE_MODE_SPEC> {
                WAVES_OUTPUT_TYPE_W::new(self, 0)
            }
            #[doc = "Bit 4 - wave0 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
            #[inline(always)]
            #[must_use]
            pub fn en_wave0_vd_vq_inject(&mut self) -> EN_WAVE0_VD_VQ_INJECT_W<WAVE_MODE_SPEC> {
                EN_WAVE0_VD_VQ_INJECT_W::new(self, 4)
            }
            #[doc = "Bit 5 - wave1 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
            #[inline(always)]
            #[must_use]
            pub fn en_wave1_vd_vq_inject(&mut self) -> EN_WAVE1_VD_VQ_INJECT_W<WAVE_MODE_SPEC> {
                EN_WAVE1_VD_VQ_INJECT_W::new(self, 5)
            }
            #[doc = "Bit 6 - wave2 VdVq inject enable. 0: disable VdVq inject. 1: enable VdVq inject."]
            #[inline(always)]
            #[must_use]
            pub fn en_wave2_vd_vq_inject(&mut self) -> EN_WAVE2_VD_VQ_INJECT_W<WAVE_MODE_SPEC> {
                EN_WAVE2_VD_VQ_INJECT_W::new(self, 6)
            }
            #[doc = "Bit 7 - saddle type seclect; 0:standard saddle. 1: triple-cos saddle."]
            #[inline(always)]
            #[must_use]
            pub fn saddle_type(&mut self) -> SADDLE_TYPE_W<WAVE_MODE_SPEC> {
                SADDLE_TYPE_W::new(self, 7)
            }
            #[doc = "Bits 8:9 - wave0 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit0.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave0_below_min_limit(&mut self) -> WAVE0_BELOW_MIN_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE0_BELOW_MIN_LIMIT_W::new(self, 8)
            }
            #[doc = "Bit 10 - wave0 low area0 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave0_low_area0_limit(&mut self) -> WAVE0_LOW_AREA0_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE0_LOW_AREA0_LIMIT_W::new(self, 10)
            }
            #[doc = "Bit 11 - wave0 low area1 limit mode. 0: output 0. 1: output as level_min_limit0.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave0_low_area1_limit(&mut self) -> WAVE0_LOW_AREA1_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE0_LOW_AREA1_LIMIT_W::new(self, 11)
            }
            #[doc = "Bit 12 - wave0 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave0_high_area0_limit(&mut self) -> WAVE0_HIGH_AREA0_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE0_HIGH_AREA0_LIMIT_W::new(self, 12)
            }
            #[doc = "Bit 13 - wave0 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit0.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave0_high_area1_limit(&mut self) -> WAVE0_HIGH_AREA1_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE0_HIGH_AREA1_LIMIT_W::new(self, 13)
            }
            #[doc = "Bits 14:15 - wave0 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit0.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave0_above_max_limit(&mut self) -> WAVE0_ABOVE_MAX_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE0_ABOVE_MAX_LIMIT_W::new(self, 14)
            }
            #[doc = "Bits 16:17 - wave1 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit1.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave1_below_min_limit(&mut self) -> WAVE1_BELOW_MIN_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE1_BELOW_MIN_LIMIT_W::new(self, 16)
            }
            #[doc = "Bit 18 - wave1 low area0 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave1_low_area0_limit(&mut self) -> WAVE1_LOW_AREA0_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE1_LOW_AREA0_LIMIT_W::new(self, 18)
            }
            #[doc = "Bit 19 - wave1 low area1 limit mode. 0: output 0. 1: output as level_min_limit1.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave1_low_area1_limit(&mut self) -> WAVE1_LOW_AREA1_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE1_LOW_AREA1_LIMIT_W::new(self, 19)
            }
            #[doc = "Bit 20 - wave1 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave1_high_area0_limit(&mut self) -> WAVE1_HIGH_AREA0_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE1_HIGH_AREA0_LIMIT_W::new(self, 20)
            }
            #[doc = "Bit 21 - wave1 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit1.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave1_high_area1_limit(&mut self) -> WAVE1_HIGH_AREA1_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE1_HIGH_AREA1_LIMIT_W::new(self, 21)
            }
            #[doc = "Bits 22:23 - wave1 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit1.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave1_above_max_limit(&mut self) -> WAVE1_ABOVE_MAX_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE1_ABOVE_MAX_LIMIT_W::new(self, 22)
            }
            #[doc = "Bits 24:25 - wave2 below min limit mode. 0: output 0. 1: output 0xffff. 2: output as level_min_limit2.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave2_below_min_limit(&mut self) -> WAVE2_BELOW_MIN_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE2_BELOW_MIN_LIMIT_W::new(self, 24)
            }
            #[doc = "Bit 26 - wave2 low area0 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave2_low_area0_limit(&mut self) -> WAVE2_LOW_AREA0_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE2_LOW_AREA0_LIMIT_W::new(self, 26)
            }
            #[doc = "Bit 27 - wave2 low area1 limit mode. 0: output 0. 1: output as level_min_limit2.level1_min_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave2_low_area1_limit(&mut self) -> WAVE2_LOW_AREA1_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE2_LOW_AREA1_LIMIT_W::new(self, 27)
            }
            #[doc = "Bit 28 - wave2 high area0 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave2_high_area0_limit(&mut self) -> WAVE2_HIGH_AREA0_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE2_HIGH_AREA0_LIMIT_W::new(self, 28)
            }
            #[doc = "Bit 29 - wave2 high area1 limit mode. 0: output 0xffff. 1: output as level_max_limit2.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave2_high_area1_limit(&mut self) -> WAVE2_HIGH_AREA1_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE2_HIGH_AREA1_LIMIT_W::new(self, 29)
            }
            #[doc = "Bits 30:31 - wave2 above max limit mode. 0: output 0xffff. 1: output 0x0. 2: output as level_max_limit2.level0_max_limit"]
            #[inline(always)]
            #[must_use]
            pub fn wave2_above_max_limit(&mut self) -> WAVE2_ABOVE_MAX_LIMIT_W<WAVE_MODE_SPEC> {
                WAVE2_ABOVE_MAX_LIMIT_W::new(self, 30)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "analog waves mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wave_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wave_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WAVE_MODE_SPEC;
        impl crate::RegisterSpec for WAVE_MODE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wave_mode::R`](R) reader structure"]
        impl crate::Readable for WAVE_MODE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wave_mode::W`](W) writer structure"]
        impl crate::Writable for WAVE_MODE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets wave_mode to value 0"]
        impl crate::Resettable for WAVE_MODE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "wave_resolution (rw) register accessor: resolution of wave0/1/2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wave_resolution::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wave_resolution::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wave_resolution`]
module"]
    pub type WAVE_RESOLUTION = crate::Reg<wave_resolution::WAVE_RESOLUTION_SPEC>;
    #[doc = "resolution of wave0/1/2"]
    pub mod wave_resolution {
        #[doc = "Register `wave_resolution` reader"]
        pub type R = crate::R<WAVE_RESOLUTION_SPEC>;
        #[doc = "Register `wave_resolution` writer"]
        pub type W = crate::W<WAVE_RESOLUTION_SPEC>;
        #[doc = "Field `LINES` reader - wave0/1/2 resolution"]
        pub type LINES_R = crate::FieldReader<u32>;
        #[doc = "Field `LINES` writer - wave0/1/2 resolution"]
        pub type LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - wave0/1/2 resolution"]
            #[inline(always)]
            pub fn lines(&self) -> LINES_R {
                LINES_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - wave0/1/2 resolution"]
            #[inline(always)]
            #[must_use]
            pub fn lines(&mut self) -> LINES_W<WAVE_RESOLUTION_SPEC> {
                LINES_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "resolution of wave0/1/2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wave_resolution::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wave_resolution::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WAVE_RESOLUTION_SPEC;
        impl crate::RegisterSpec for WAVE_RESOLUTION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wave_resolution::R`](R) reader structure"]
        impl crate::Readable for WAVE_RESOLUTION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wave_resolution::W`](W) writer structure"]
        impl crate::Writable for WAVE_RESOLUTION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets wave_resolution to value 0"]
        impl crate::Resettable for WAVE_RESOLUTION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PHASE_SHIFT_WAVE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_shift_wave::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_shift_wave::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_shift_wave`]
module"]
    pub type PHASE_SHIFT_WAVE = crate::Reg<phase_shift_wave::PHASE_SHIFT_WAVE_SPEC>;
    #[doc = "no description available"]
    pub mod phase_shift_wave {
        #[doc = "Register `PHASE_SHIFT_WAVE[%s]` reader"]
        pub type R = crate::R<PHASE_SHIFT_WAVE_SPEC>;
        #[doc = "Register `PHASE_SHIFT_WAVE[%s]` writer"]
        pub type W = crate::W<PHASE_SHIFT_WAVE_SPEC>;
        #[doc = "Field `VAL` reader - wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
        pub type VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `VAL` writer - wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<PHASE_SHIFT_WAVE_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_shift_wave::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_shift_wave::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHASE_SHIFT_WAVE_SPEC;
        impl crate::RegisterSpec for PHASE_SHIFT_WAVE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phase_shift_wave::R`](R) reader structure"]
        impl crate::Readable for PHASE_SHIFT_WAVE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phase_shift_wave::W`](W) writer structure"]
        impl crate::Writable for PHASE_SHIFT_WAVE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PHASE_SHIFT_WAVE[%s]
to value 0"]
        impl crate::Resettable for PHASE_SHIFT_WAVE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "VD_VQ_INJECT (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vd_vq_inject::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vd_vq_inject::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_vq_inject`]
module"]
    pub type VD_VQ_INJECT = crate::Reg<vd_vq_inject::VD_VQ_INJECT_SPEC>;
    #[doc = "no description available"]
    pub mod vd_vq_inject {
        #[doc = "Register `VD_VQ_INJECT[%s]` reader"]
        pub type R = crate::R<VD_VQ_INJECT_SPEC>;
        #[doc = "Register `VD_VQ_INJECT[%s]` writer"]
        pub type W = crate::W<VD_VQ_INJECT_SPEC>;
        #[doc = "Field `VD_VAL` reader - Vd inject value"]
        pub type VD_VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `VD_VAL` writer - Vd inject value"]
        pub type VD_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `VQ_VAL` reader - Vq inject value"]
        pub type VQ_VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `VQ_VAL` writer - Vq inject value"]
        pub type VQ_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Vd inject value"]
            #[inline(always)]
            pub fn vd_val(&self) -> VD_VAL_R {
                VD_VAL_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - Vq inject value"]
            #[inline(always)]
            pub fn vq_val(&self) -> VQ_VAL_R {
                VQ_VAL_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Vd inject value"]
            #[inline(always)]
            #[must_use]
            pub fn vd_val(&mut self) -> VD_VAL_W<VD_VQ_INJECT_SPEC> {
                VD_VAL_W::new(self, 0)
            }
            #[doc = "Bits 16:31 - Vq inject value"]
            #[inline(always)]
            #[must_use]
            pub fn vq_val(&mut self) -> VQ_VAL_W<VD_VQ_INJECT_SPEC> {
                VQ_VAL_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vd_vq_inject::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vd_vq_inject::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct VD_VQ_INJECT_SPEC;
        impl crate::RegisterSpec for VD_VQ_INJECT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`vd_vq_inject::R`](R) reader structure"]
        impl crate::Readable for VD_VQ_INJECT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`vd_vq_inject::W`](W) writer structure"]
        impl crate::Writable for VD_VQ_INJECT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets VD_VQ_INJECT[%s]
to value 0"]
        impl crate::Resettable for VD_VQ_INJECT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "vd_vq_load (rw) register accessor: load wave0/1/2 vd vq value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vd_vq_load::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vd_vq_load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vd_vq_load`]
module"]
    pub type VD_VQ_LOAD = crate::Reg<vd_vq_load::VD_VQ_LOAD_SPEC>;
    #[doc = "load wave0/1/2 vd vq value"]
    pub mod vd_vq_load {
        #[doc = "Register `vd_vq_load` reader"]
        pub type R = crate::R<VD_VQ_LOAD_SPEC>;
        #[doc = "Register `vd_vq_load` writer"]
        pub type W = crate::W<VD_VQ_LOAD_SPEC>;
        #[doc = "Field `LOAD` writer - load wave0/1/2 vd vq value. always read 0 0: vd vq keep previous value. 1: load wave0/1/2 vd vq value at sametime."]
        pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - load wave0/1/2 vd vq value. always read 0 0: vd vq keep previous value. 1: load wave0/1/2 vd vq value at sametime."]
            #[inline(always)]
            #[must_use]
            pub fn load(&mut self) -> LOAD_W<VD_VQ_LOAD_SPEC> {
                LOAD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "load wave0/1/2 vd vq value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vd_vq_load::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vd_vq_load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct VD_VQ_LOAD_SPEC;
        impl crate::RegisterSpec for VD_VQ_LOAD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`vd_vq_load::R`](R) reader structure"]
        impl crate::Readable for VD_VQ_LOAD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`vd_vq_load::W`](W) writer structure"]
        impl crate::Writable for VD_VQ_LOAD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets vd_vq_load to value 0"]
        impl crate::Resettable for VD_VQ_LOAD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "AMPLITUDE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amplitude::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amplitude::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amplitude`]
module"]
    pub type AMPLITUDE = crate::Reg<amplitude::AMPLITUDE_SPEC>;
    #[doc = "no description available"]
    pub mod amplitude {
        #[doc = "Register `AMPLITUDE[%s]` reader"]
        pub type R = crate::R<AMPLITUDE_SPEC>;
        #[doc = "Register `AMPLITUDE[%s]` writer"]
        pub type W = crate::W<AMPLITUDE_SPEC>;
        #[doc = "Field `AMP_VAL` reader - amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value."]
        pub type AMP_VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `AMP_VAL` writer - amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value."]
        pub type AMP_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `EN_SCAL` reader - enable wave amplitude scaling. 0: disable; 1: enable"]
        pub type EN_SCAL_R = crate::BitReader;
        #[doc = "Field `EN_SCAL` writer - enable wave amplitude scaling. 0: disable; 1: enable"]
        pub type EN_SCAL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:15 - amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value."]
            #[inline(always)]
            pub fn amp_val(&self) -> AMP_VAL_R {
                AMP_VAL_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bit 16 - enable wave amplitude scaling. 0: disable; 1: enable"]
            #[inline(always)]
            pub fn en_scal(&self) -> EN_SCAL_R {
                EN_SCAL_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value."]
            #[inline(always)]
            #[must_use]
            pub fn amp_val(&mut self) -> AMP_VAL_W<AMPLITUDE_SPEC> {
                AMP_VAL_W::new(self, 0)
            }
            #[doc = "Bit 16 - enable wave amplitude scaling. 0: disable; 1: enable"]
            #[inline(always)]
            #[must_use]
            pub fn en_scal(&mut self) -> EN_SCAL_W<AMPLITUDE_SPEC> {
                EN_SCAL_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amplitude::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amplitude::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AMPLITUDE_SPEC;
        impl crate::RegisterSpec for AMPLITUDE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`amplitude::R`](R) reader structure"]
        impl crate::Readable for AMPLITUDE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`amplitude::W`](W) writer structure"]
        impl crate::Writable for AMPLITUDE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets AMPLITUDE[%s]
to value 0"]
        impl crate::Resettable for AMPLITUDE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "MID_POINT (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mid_point::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mid_point::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mid_point`]
module"]
    pub type MID_POINT = crate::Reg<mid_point::MID_POINT_SPEC>;
    #[doc = "no description available"]
    pub mod mid_point {
        #[doc = "Register `MID_POINT[%s]` reader"]
        pub type R = crate::R<MID_POINT_SPEC>;
        #[doc = "Register `MID_POINT[%s]` writer"]
        pub type W = crate::W<MID_POINT_SPEC>;
        #[doc = "Field `VAL` reader - wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value."]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value."]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value."]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value."]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<MID_POINT_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mid_point::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mid_point::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MID_POINT_SPEC;
        impl crate::RegisterSpec for MID_POINT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`mid_point::R`](R) reader structure"]
        impl crate::Readable for MID_POINT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`mid_point::W`](W) writer structure"]
        impl crate::Writable for MID_POINT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets MID_POINT[%s]
to value 0"]
        impl crate::Resettable for MID_POINT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::limit::LIMIT;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod limit {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct LIMIT {
            min: MIN,
            max: MAX,
        }
        impl LIMIT {
            #[doc = "0x00 - wave0 low area limit value"]
            #[inline(always)]
            pub const fn min(&self) -> &MIN {
                &self.min
            }
            #[doc = "0x04 - wave0 high area limit value"]
            #[inline(always)]
            pub const fn max(&self) -> &MAX {
                &self.max
            }
        }
        #[doc = "min (rw) register accessor: wave0 low area limit value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@min`]
module"]
        pub type MIN = crate::Reg<min::MIN_SPEC>;
        #[doc = "wave0 low area limit value"]
        pub mod min {
            #[doc = "Register `min` reader"]
            pub type R = crate::R<MIN_SPEC>;
            #[doc = "Register `min` writer"]
            pub type W = crate::W<MIN_SPEC>;
            #[doc = "Field `LIMIT0` reader - low area limit level0"]
            pub type LIMIT0_R = crate::FieldReader<u16>;
            #[doc = "Field `LIMIT0` writer - low area limit level0"]
            pub type LIMIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            #[doc = "Field `LIMIT1` reader - low area limit level1"]
            pub type LIMIT1_R = crate::FieldReader<u16>;
            #[doc = "Field `LIMIT1` writer - low area limit level1"]
            pub type LIMIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - low area limit level0"]
                #[inline(always)]
                pub fn limit0(&self) -> LIMIT0_R {
                    LIMIT0_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bits 16:31 - low area limit level1"]
                #[inline(always)]
                pub fn limit1(&self) -> LIMIT1_R {
                    LIMIT1_R::new(((self.bits >> 16) & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - low area limit level0"]
                #[inline(always)]
                #[must_use]
                pub fn limit0(&mut self) -> LIMIT0_W<MIN_SPEC> {
                    LIMIT0_W::new(self, 0)
                }
                #[doc = "Bits 16:31 - low area limit level1"]
                #[inline(always)]
                #[must_use]
                pub fn limit1(&mut self) -> LIMIT1_W<MIN_SPEC> {
                    LIMIT1_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "wave0 low area limit value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MIN_SPEC;
            impl crate::RegisterSpec for MIN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`min::R`](R) reader structure"]
            impl crate::Readable for MIN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`min::W`](W) writer structure"]
            impl crate::Writable for MIN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets min to value 0"]
            impl crate::Resettable for MIN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "max (rw) register accessor: wave0 high area limit value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max`]
module"]
        pub type MAX = crate::Reg<max::MAX_SPEC>;
        #[doc = "wave0 high area limit value"]
        pub mod max {
            #[doc = "Register `max` reader"]
            pub type R = crate::R<MAX_SPEC>;
            #[doc = "Register `max` writer"]
            pub type W = crate::W<MAX_SPEC>;
            #[doc = "Field `LIMIT0` reader - high area limit level0"]
            pub type LIMIT0_R = crate::FieldReader<u16>;
            #[doc = "Field `LIMIT0` writer - high area limit level0"]
            pub type LIMIT0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            #[doc = "Field `LIMIT1` reader - high area limit level1"]
            pub type LIMIT1_R = crate::FieldReader<u16>;
            #[doc = "Field `LIMIT1` writer - high area limit level1"]
            pub type LIMIT1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - high area limit level0"]
                #[inline(always)]
                pub fn limit0(&self) -> LIMIT0_R {
                    LIMIT0_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bits 16:31 - high area limit level1"]
                #[inline(always)]
                pub fn limit1(&self) -> LIMIT1_R {
                    LIMIT1_R::new(((self.bits >> 16) & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - high area limit level0"]
                #[inline(always)]
                #[must_use]
                pub fn limit0(&mut self) -> LIMIT0_W<MAX_SPEC> {
                    LIMIT0_W::new(self, 0)
                }
                #[doc = "Bits 16:31 - high area limit level1"]
                #[inline(always)]
                #[must_use]
                pub fn limit1(&mut self) -> LIMIT1_W<MAX_SPEC> {
                    LIMIT1_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "wave0 high area limit value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MAX_SPEC;
            impl crate::RegisterSpec for MAX_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`max::R`](R) reader structure"]
            impl crate::Readable for MAX_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`max::W`](W) writer structure"]
            impl crate::Writable for MAX_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets max to value 0xffff_ffff"]
            impl crate::Resettable for MAX_SPEC {
                const RESET_VALUE: u32 = 0xffff_ffff;
            }
        }
    }
    #[doc = "DEADZONE_SHIFT (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deadzone_shift::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deadzone_shift::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deadzone_shift`]
module"]
    pub type DEADZONE_SHIFT = crate::Reg<deadzone_shift::DEADZONE_SHIFT_SPEC>;
    #[doc = "no description available"]
    pub mod deadzone_shift {
        #[doc = "Register `DEADZONE_SHIFT[%s]` reader"]
        pub type R = crate::R<DEADZONE_SHIFT_SPEC>;
        #[doc = "Register `DEADZONE_SHIFT[%s]` writer"]
        pub type W = crate::W<DEADZONE_SHIFT_SPEC>;
        #[doc = "Field `VAL` reader - wave0 deadzone shifter value"]
        pub type VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `VAL` writer - wave0 deadzone shifter value"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - wave0 deadzone shifter value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - wave0 deadzone shifter value"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<DEADZONE_SHIFT_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deadzone_shift::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deadzone_shift::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DEADZONE_SHIFT_SPEC;
        impl crate::RegisterSpec for DEADZONE_SHIFT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`deadzone_shift::R`](R) reader structure"]
        impl crate::Readable for DEADZONE_SHIFT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`deadzone_shift::W`](W) writer structure"]
        impl crate::Writable for DEADZONE_SHIFT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DEADZONE_SHIFT[%s]
to value 0"]
        impl crate::Resettable for DEADZONE_SHIFT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "abz_mode (rw) register accessor: wave_a/b/z output mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abz_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abz_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abz_mode`]
module"]
    pub type ABZ_MODE = crate::Reg<abz_mode::ABZ_MODE_SPEC>;
    #[doc = "wave_a/b/z output mode"]
    pub mod abz_mode {
        #[doc = "Register `abz_mode` reader"]
        pub type R = crate::R<ABZ_MODE_SPEC>;
        #[doc = "Register `abz_mode` writer"]
        pub type W = crate::W<ABZ_MODE_SPEC>;
        #[doc = "Field `A_TYPE` reader - wave_a type: 0: Two-phase orthogonality wave_a. 1: pulse wave of pulse/reverse type. 2: up wave of up/down type. 3: Three-phase orthogonality wave_a."]
        pub type A_TYPE_R = crate::FieldReader;
        #[doc = "Field `A_TYPE` writer - wave_a type: 0: Two-phase orthogonality wave_a. 1: pulse wave of pulse/reverse type. 2: up wave of up/down type. 3: Three-phase orthogonality wave_a."]
        pub type A_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `B_TYPE` reader - wave_b type: 0: Two-phase orthogonality wave_b. 1: reverse wave of pulse/reverse type. 2: down wave of up/down type. 3: Three-phase orthogonality wave_b."]
        pub type B_TYPE_R = crate::FieldReader;
        #[doc = "Field `B_TYPE` writer - wave_b type: 0: Two-phase orthogonality wave_b. 1: reverse wave of pulse/reverse type. 2: down wave of up/down type. 3: Three-phase orthogonality wave_b."]
        pub type B_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `Z_TYPE` reader - wave_z type: 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. 1: zero pulse output high about 75% period. start from 0 to 75% period. 2: zero pulse output high about 100% period. 3: wave_z output as tree-phase wave same as wave_a/wave_b"]
        pub type Z_TYPE_R = crate::FieldReader;
        #[doc = "Field `Z_TYPE` writer - wave_z type: 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. 1: zero pulse output high about 75% period. start from 0 to 75% period. 2: zero pulse output high about 100% period. 3: wave_z output as tree-phase wave same as wave_a/wave_b"]
        pub type Z_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `A_POLARITY` reader - wave_a polarity. 0: normal output. 1: invert normal output"]
        pub type A_POLARITY_R = crate::BitReader;
        #[doc = "Field `A_POLARITY` writer - wave_a polarity. 0: normal output. 1: invert normal output"]
        pub type A_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `B_POLARITY` reader - wave_b polarity. 0: normal output. 1: invert normal output"]
        pub type B_POLARITY_R = crate::BitReader;
        #[doc = "Field `B_POLARITY` writer - wave_b polarity. 0: normal output. 1: invert normal output"]
        pub type B_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `Z_POLARITY` reader - wave_z polarity. 0: normal output. 1: invert normal output"]
        pub type Z_POLARITY_R = crate::BitReader;
        #[doc = "Field `Z_POLARITY` writer - wave_z polarity. 0: normal output. 1: invert normal output"]
        pub type Z_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_WDOG` reader - enable abz wdog: 0: disable abz wdog. 1: enable abz wdog."]
        pub type EN_WDOG_R = crate::BitReader;
        #[doc = "Field `EN_WDOG` writer - enable abz wdog: 0: disable abz wdog. 1: enable abz wdog."]
        pub type EN_WDOG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `REVERSE_EDGE_TYPE` reader - pulse reverse wave，reverse edge point: 0: between pulse's posedge and negedge, min period dedicated by the num line_width 1: edge change point flow pulse's negedge."]
        pub type REVERSE_EDGE_TYPE_R = crate::BitReader;
        #[doc = "Field `REVERSE_EDGE_TYPE` writer - pulse reverse wave，reverse edge point: 0: between pulse's posedge and negedge, min period dedicated by the num line_width 1: edge change point flow pulse's negedge."]
        pub type REVERSE_EDGE_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1 - wave_a type: 0: Two-phase orthogonality wave_a. 1: pulse wave of pulse/reverse type. 2: up wave of up/down type. 3: Three-phase orthogonality wave_a."]
            #[inline(always)]
            pub fn a_type(&self) -> A_TYPE_R {
                A_TYPE_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bits 4:5 - wave_b type: 0: Two-phase orthogonality wave_b. 1: reverse wave of pulse/reverse type. 2: down wave of up/down type. 3: Three-phase orthogonality wave_b."]
            #[inline(always)]
            pub fn b_type(&self) -> B_TYPE_R {
                B_TYPE_R::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bits 8:9 - wave_z type: 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. 1: zero pulse output high about 75% period. start from 0 to 75% period. 2: zero pulse output high about 100% period. 3: wave_z output as tree-phase wave same as wave_a/wave_b"]
            #[inline(always)]
            pub fn z_type(&self) -> Z_TYPE_R {
                Z_TYPE_R::new(((self.bits >> 8) & 3) as u8)
            }
            #[doc = "Bit 12 - wave_a polarity. 0: normal output. 1: invert normal output"]
            #[inline(always)]
            pub fn a_polarity(&self) -> A_POLARITY_R {
                A_POLARITY_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 16 - wave_b polarity. 0: normal output. 1: invert normal output"]
            #[inline(always)]
            pub fn b_polarity(&self) -> B_POLARITY_R {
                B_POLARITY_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 20 - wave_z polarity. 0: normal output. 1: invert normal output"]
            #[inline(always)]
            pub fn z_polarity(&self) -> Z_POLARITY_R {
                Z_POLARITY_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 24 - enable abz wdog: 0: disable abz wdog. 1: enable abz wdog."]
            #[inline(always)]
            pub fn en_wdog(&self) -> EN_WDOG_R {
                EN_WDOG_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 28 - pulse reverse wave，reverse edge point: 0: between pulse's posedge and negedge, min period dedicated by the num line_width 1: edge change point flow pulse's negedge."]
            #[inline(always)]
            pub fn reverse_edge_type(&self) -> REVERSE_EDGE_TYPE_R {
                REVERSE_EDGE_TYPE_R::new(((self.bits >> 28) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - wave_a type: 0: Two-phase orthogonality wave_a. 1: pulse wave of pulse/reverse type. 2: up wave of up/down type. 3: Three-phase orthogonality wave_a."]
            #[inline(always)]
            #[must_use]
            pub fn a_type(&mut self) -> A_TYPE_W<ABZ_MODE_SPEC> {
                A_TYPE_W::new(self, 0)
            }
            #[doc = "Bits 4:5 - wave_b type: 0: Two-phase orthogonality wave_b. 1: reverse wave of pulse/reverse type. 2: down wave of up/down type. 3: Three-phase orthogonality wave_b."]
            #[inline(always)]
            #[must_use]
            pub fn b_type(&mut self) -> B_TYPE_W<ABZ_MODE_SPEC> {
                B_TYPE_W::new(self, 4)
            }
            #[doc = "Bits 8:9 - wave_z type: 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. 1: zero pulse output high about 75% period. start from 0 to 75% period. 2: zero pulse output high about 100% period. 3: wave_z output as tree-phase wave same as wave_a/wave_b"]
            #[inline(always)]
            #[must_use]
            pub fn z_type(&mut self) -> Z_TYPE_W<ABZ_MODE_SPEC> {
                Z_TYPE_W::new(self, 8)
            }
            #[doc = "Bit 12 - wave_a polarity. 0: normal output. 1: invert normal output"]
            #[inline(always)]
            #[must_use]
            pub fn a_polarity(&mut self) -> A_POLARITY_W<ABZ_MODE_SPEC> {
                A_POLARITY_W::new(self, 12)
            }
            #[doc = "Bit 16 - wave_b polarity. 0: normal output. 1: invert normal output"]
            #[inline(always)]
            #[must_use]
            pub fn b_polarity(&mut self) -> B_POLARITY_W<ABZ_MODE_SPEC> {
                B_POLARITY_W::new(self, 16)
            }
            #[doc = "Bit 20 - wave_z polarity. 0: normal output. 1: invert normal output"]
            #[inline(always)]
            #[must_use]
            pub fn z_polarity(&mut self) -> Z_POLARITY_W<ABZ_MODE_SPEC> {
                Z_POLARITY_W::new(self, 20)
            }
            #[doc = "Bit 24 - enable abz wdog: 0: disable abz wdog. 1: enable abz wdog."]
            #[inline(always)]
            #[must_use]
            pub fn en_wdog(&mut self) -> EN_WDOG_W<ABZ_MODE_SPEC> {
                EN_WDOG_W::new(self, 24)
            }
            #[doc = "Bit 28 - pulse reverse wave，reverse edge point: 0: between pulse's posedge and negedge, min period dedicated by the num line_width 1: edge change point flow pulse's negedge."]
            #[inline(always)]
            #[must_use]
            pub fn reverse_edge_type(&mut self) -> REVERSE_EDGE_TYPE_W<ABZ_MODE_SPEC> {
                REVERSE_EDGE_TYPE_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wave_a/b/z output mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abz_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abz_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ABZ_MODE_SPEC;
        impl crate::RegisterSpec for ABZ_MODE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`abz_mode::R`](R) reader structure"]
        impl crate::Readable for ABZ_MODE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`abz_mode::W`](W) writer structure"]
        impl crate::Writable for ABZ_MODE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets abz_mode to value 0"]
        impl crate::Resettable for ABZ_MODE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "abz_resolution (rw) register accessor: resolution of wave_a/b/z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abz_resolution::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abz_resolution::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@abz_resolution`]
module"]
    pub type ABZ_RESOLUTION = crate::Reg<abz_resolution::ABZ_RESOLUTION_SPEC>;
    #[doc = "resolution of wave_a/b/z"]
    pub mod abz_resolution {
        #[doc = "Register `abz_resolution` reader"]
        pub type R = crate::R<ABZ_RESOLUTION_SPEC>;
        #[doc = "Register `abz_resolution` writer"]
        pub type W = crate::W<ABZ_RESOLUTION_SPEC>;
        #[doc = "Field `LINES` reader - wave_a/b/z resolution"]
        pub type LINES_R = crate::FieldReader<u32>;
        #[doc = "Field `LINES` writer - wave_a/b/z resolution"]
        pub type LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - wave_a/b/z resolution"]
            #[inline(always)]
            pub fn lines(&self) -> LINES_R {
                LINES_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - wave_a/b/z resolution"]
            #[inline(always)]
            #[must_use]
            pub fn lines(&mut self) -> LINES_W<ABZ_RESOLUTION_SPEC> {
                LINES_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "resolution of wave_a/b/z\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`abz_resolution::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`abz_resolution::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ABZ_RESOLUTION_SPEC;
        impl crate::RegisterSpec for ABZ_RESOLUTION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`abz_resolution::R`](R) reader structure"]
        impl crate::Readable for ABZ_RESOLUTION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`abz_resolution::W`](W) writer structure"]
        impl crate::Writable for ABZ_RESOLUTION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets abz_resolution to value 0"]
        impl crate::Resettable for ABZ_RESOLUTION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PHASE_SHIFT_ABZ (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_shift_abz::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_shift_abz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_shift_abz`]
module"]
    pub type PHASE_SHIFT_ABZ = crate::Reg<phase_shift_abz::PHASE_SHIFT_ABZ_SPEC>;
    #[doc = "no description available"]
    pub mod phase_shift_abz {
        #[doc = "Register `PHASE_SHIFT_ABZ[%s]` reader"]
        pub type R = crate::R<PHASE_SHIFT_ABZ_SPEC>;
        #[doc = "Register `PHASE_SHIFT_ABZ[%s]` writer"]
        pub type W = crate::W<PHASE_SHIFT_ABZ_SPEC>;
        #[doc = "Field `VAL` reader - wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period."]
        pub type VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `VAL` writer - wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period."]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period."]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period."]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<PHASE_SHIFT_ABZ_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_shift_abz::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_shift_abz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHASE_SHIFT_ABZ_SPEC;
        impl crate::RegisterSpec for PHASE_SHIFT_ABZ_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phase_shift_abz::R`](R) reader structure"]
        impl crate::Readable for PHASE_SHIFT_ABZ_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phase_shift_abz::W`](W) writer structure"]
        impl crate::Writable for PHASE_SHIFT_ABZ_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PHASE_SHIFT_ABZ[%s]
to value 0"]
        impl crate::Resettable for PHASE_SHIFT_ABZ_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "line_width (rw) register accessor: Two-phase orthogonality wave 1/4 period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`line_width::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`line_width::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@line_width`]
module"]
    pub type LINE_WIDTH = crate::Reg<line_width::LINE_WIDTH_SPEC>;
    #[doc = "Two-phase orthogonality wave 1/4 period"]
    pub mod line_width {
        #[doc = "Register `line_width` reader"]
        pub type R = crate::R<LINE_WIDTH_SPEC>;
        #[doc = "Register `line_width` writer"]
        pub type W = crate::W<LINE_WIDTH_SPEC>;
        #[doc = "Field `LINE` reader - the num of system clk by 1/4 period when using as Two-phase orthogonality."]
        pub type LINE_R = crate::FieldReader<u32>;
        #[doc = "Field `LINE` writer - the num of system clk by 1/4 period when using as Two-phase orthogonality."]
        pub type LINE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the num of system clk by 1/4 period when using as Two-phase orthogonality."]
            #[inline(always)]
            pub fn line(&self) -> LINE_R {
                LINE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the num of system clk by 1/4 period when using as Two-phase orthogonality."]
            #[inline(always)]
            #[must_use]
            pub fn line(&mut self) -> LINE_W<LINE_WIDTH_SPEC> {
                LINE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Two-phase orthogonality wave 1/4 period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`line_width::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`line_width::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LINE_WIDTH_SPEC;
        impl crate::RegisterSpec for LINE_WIDTH_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`line_width::R`](R) reader structure"]
        impl crate::Readable for LINE_WIDTH_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`line_width::W`](W) writer structure"]
        impl crate::Writable for LINE_WIDTH_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets line_width to value 0"]
        impl crate::Resettable for LINE_WIDTH_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "wdog_width (rw) register accessor: wdog width of qeo\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdog_width::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdog_width::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdog_width`]
module"]
    pub type WDOG_WIDTH = crate::Reg<wdog_width::WDOG_WIDTH_SPEC>;
    #[doc = "wdog width of qeo"]
    pub mod wdog_width {
        #[doc = "Register `wdog_width` reader"]
        pub type R = crate::R<WDOG_WIDTH_SPEC>;
        #[doc = "Register `wdog_width` writer"]
        pub type W = crate::W<WDOG_WIDTH_SPEC>;
        #[doc = "Field `WIDTH` reader - wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk."]
        pub type WIDTH_R = crate::FieldReader<u32>;
        #[doc = "Field `WIDTH` writer - wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk."]
        pub type WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk."]
            #[inline(always)]
            pub fn width(&self) -> WIDTH_R {
                WIDTH_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk."]
            #[inline(always)]
            #[must_use]
            pub fn width(&mut self) -> WIDTH_W<WDOG_WIDTH_SPEC> {
                WIDTH_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "wdog width of qeo\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdog_width::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdog_width::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WDOG_WIDTH_SPEC;
        impl crate::RegisterSpec for WDOG_WIDTH_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wdog_width::R`](R) reader structure"]
        impl crate::Readable for WDOG_WIDTH_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wdog_width::W`](W) writer structure"]
        impl crate::Writable for WDOG_WIDTH_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets wdog_width to value 0"]
        impl crate::Resettable for WDOG_WIDTH_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "postion_sync (rw) register accessor: sync abz owned postion\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`postion_sync::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`postion_sync::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@postion_sync`]
module"]
    pub type POSTION_SYNC = crate::Reg<postion_sync::POSTION_SYNC_SPEC>;
    #[doc = "sync abz owned postion"]
    pub mod postion_sync {
        #[doc = "Register `postion_sync` reader"]
        pub type R = crate::R<POSTION_SYNC_SPEC>;
        #[doc = "Register `postion_sync` writer"]
        pub type W = crate::W<POSTION_SYNC_SPEC>;
        #[doc = "Field `POSTION` writer - load next valid postion into abz owned postion. always read 0 0: sync abz owned postion with next valid postion. 1: not sync."]
        pub type POSTION_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - load next valid postion into abz owned postion. always read 0 0: sync abz owned postion with next valid postion. 1: not sync."]
            #[inline(always)]
            #[must_use]
            pub fn postion(&mut self) -> POSTION_W<POSTION_SYNC_SPEC> {
                POSTION_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "sync abz owned postion\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`postion_sync::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`postion_sync::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POSTION_SYNC_SPEC;
        impl crate::RegisterSpec for POSTION_SYNC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`postion_sync::R`](R) reader structure"]
        impl crate::Readable for POSTION_SYNC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`postion_sync::W`](W) writer structure"]
        impl crate::Writable for POSTION_SYNC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets postion_sync to value 0"]
        impl crate::Resettable for POSTION_SYNC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "mode (rw) register accessor: pwm mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`]
module"]
    pub type MODE = crate::Reg<mode::MODE_SPEC>;
    #[doc = "pwm mode"]
    pub mod mode {
        #[doc = "Register `mode` reader"]
        pub type R = crate::R<MODE_SPEC>;
        #[doc = "Register `mode` writer"]
        pub type W = crate::W<MODE_SPEC>;
        #[doc = "Field `PHASE_NUM` reader - pwm force phase number."]
        pub type PHASE_NUM_R = crate::FieldReader;
        #[doc = "Field `PHASE_NUM` writer - pwm force phase number."]
        pub type PHASE_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `REVISE_UP_DN` reader - exchange PWM pairs’ output 0: not exchange. 1: exchange."]
        pub type REVISE_UP_DN_R = crate::BitReader;
        #[doc = "Field `REVISE_UP_DN` writer - exchange PWM pairs’ output 0: not exchange. 1: exchange."]
        pub type REVISE_UP_DN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PWM_SAFETY_BYPASS` reader - PWM safety mode bypass 0: not bypass 1: bypass"]
        pub type PWM_SAFETY_BYPASS_R = crate::BitReader;
        #[doc = "Field `PWM_SAFETY_BYPASS` writer - PWM safety mode bypass 0: not bypass 1: bypass"]
        pub type PWM_SAFETY_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PWM_ENTER_SAFETY_MODE` reader - PWM enter safety mode 0: not enter 1: enter"]
        pub type PWM_ENTER_SAFETY_MODE_R = crate::BitReader;
        #[doc = "Field `PWM_ENTER_SAFETY_MODE` writer - PWM enter safety mode 0: not enter 1: enter"]
        pub type PWM_ENTER_SAFETY_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PWM0_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM0_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM0_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM0_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM1_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM1_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM1_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM1_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM2_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM2_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM2_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM2_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM3_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM3_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM3_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM3_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM4_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM4_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM4_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM4_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM5_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM5_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM5_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM5_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM6_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM6_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM6_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM6_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM7_SAFETY` reader - PWM safety mode phase table"]
        pub type PWM7_SAFETY_R = crate::FieldReader;
        #[doc = "Field `PWM7_SAFETY` writer - PWM safety mode phase table"]
        pub type PWM7_SAFETY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bits 0:3 - pwm force phase number."]
            #[inline(always)]
            pub fn phase_num(&self) -> PHASE_NUM_R {
                PHASE_NUM_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bit 4 - exchange PWM pairs’ output 0: not exchange. 1: exchange."]
            #[inline(always)]
            pub fn revise_up_dn(&self) -> REVISE_UP_DN_R {
                REVISE_UP_DN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 8 - PWM safety mode bypass 0: not bypass 1: bypass"]
            #[inline(always)]
            pub fn pwm_safety_bypass(&self) -> PWM_SAFETY_BYPASS_R {
                PWM_SAFETY_BYPASS_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - PWM enter safety mode 0: not enter 1: enter"]
            #[inline(always)]
            pub fn pwm_enter_safety_mode(&self) -> PWM_ENTER_SAFETY_MODE_R {
                PWM_ENTER_SAFETY_MODE_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bits 16:17 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm0_safety(&self) -> PWM0_SAFETY_R {
                PWM0_SAFETY_R::new(((self.bits >> 16) & 3) as u8)
            }
            #[doc = "Bits 18:19 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm1_safety(&self) -> PWM1_SAFETY_R {
                PWM1_SAFETY_R::new(((self.bits >> 18) & 3) as u8)
            }
            #[doc = "Bits 20:21 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm2_safety(&self) -> PWM2_SAFETY_R {
                PWM2_SAFETY_R::new(((self.bits >> 20) & 3) as u8)
            }
            #[doc = "Bits 22:23 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm3_safety(&self) -> PWM3_SAFETY_R {
                PWM3_SAFETY_R::new(((self.bits >> 22) & 3) as u8)
            }
            #[doc = "Bits 24:25 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm4_safety(&self) -> PWM4_SAFETY_R {
                PWM4_SAFETY_R::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bits 26:27 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm5_safety(&self) -> PWM5_SAFETY_R {
                PWM5_SAFETY_R::new(((self.bits >> 26) & 3) as u8)
            }
            #[doc = "Bits 28:29 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm6_safety(&self) -> PWM6_SAFETY_R {
                PWM6_SAFETY_R::new(((self.bits >> 28) & 3) as u8)
            }
            #[doc = "Bits 30:31 - PWM safety mode phase table"]
            #[inline(always)]
            pub fn pwm7_safety(&self) -> PWM7_SAFETY_R {
                PWM7_SAFETY_R::new(((self.bits >> 30) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - pwm force phase number."]
            #[inline(always)]
            #[must_use]
            pub fn phase_num(&mut self) -> PHASE_NUM_W<MODE_SPEC> {
                PHASE_NUM_W::new(self, 0)
            }
            #[doc = "Bit 4 - exchange PWM pairs’ output 0: not exchange. 1: exchange."]
            #[inline(always)]
            #[must_use]
            pub fn revise_up_dn(&mut self) -> REVISE_UP_DN_W<MODE_SPEC> {
                REVISE_UP_DN_W::new(self, 4)
            }
            #[doc = "Bit 8 - PWM safety mode bypass 0: not bypass 1: bypass"]
            #[inline(always)]
            #[must_use]
            pub fn pwm_safety_bypass(&mut self) -> PWM_SAFETY_BYPASS_W<MODE_SPEC> {
                PWM_SAFETY_BYPASS_W::new(self, 8)
            }
            #[doc = "Bit 9 - PWM enter safety mode 0: not enter 1: enter"]
            #[inline(always)]
            #[must_use]
            pub fn pwm_enter_safety_mode(&mut self) -> PWM_ENTER_SAFETY_MODE_W<MODE_SPEC> {
                PWM_ENTER_SAFETY_MODE_W::new(self, 9)
            }
            #[doc = "Bits 16:17 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm0_safety(&mut self) -> PWM0_SAFETY_W<MODE_SPEC> {
                PWM0_SAFETY_W::new(self, 16)
            }
            #[doc = "Bits 18:19 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm1_safety(&mut self) -> PWM1_SAFETY_W<MODE_SPEC> {
                PWM1_SAFETY_W::new(self, 18)
            }
            #[doc = "Bits 20:21 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm2_safety(&mut self) -> PWM2_SAFETY_W<MODE_SPEC> {
                PWM2_SAFETY_W::new(self, 20)
            }
            #[doc = "Bits 22:23 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm3_safety(&mut self) -> PWM3_SAFETY_W<MODE_SPEC> {
                PWM3_SAFETY_W::new(self, 22)
            }
            #[doc = "Bits 24:25 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm4_safety(&mut self) -> PWM4_SAFETY_W<MODE_SPEC> {
                PWM4_SAFETY_W::new(self, 24)
            }
            #[doc = "Bits 26:27 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm5_safety(&mut self) -> PWM5_SAFETY_W<MODE_SPEC> {
                PWM5_SAFETY_W::new(self, 26)
            }
            #[doc = "Bits 28:29 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm6_safety(&mut self) -> PWM6_SAFETY_W<MODE_SPEC> {
                PWM6_SAFETY_W::new(self, 28)
            }
            #[doc = "Bits 30:31 - PWM safety mode phase table"]
            #[inline(always)]
            #[must_use]
            pub fn pwm7_safety(&mut self) -> PWM7_SAFETY_W<MODE_SPEC> {
                PWM7_SAFETY_W::new(self, 30)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pwm mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MODE_SPEC;
        impl crate::RegisterSpec for MODE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`mode::R`](R) reader structure"]
        impl crate::Readable for MODE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
        impl crate::Writable for MODE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets mode to value 0"]
        impl crate::Resettable for MODE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "resolution (rw) register accessor: resolution of pwm\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resolution::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resolution::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resolution`]
module"]
    pub type RESOLUTION = crate::Reg<resolution::RESOLUTION_SPEC>;
    #[doc = "resolution of pwm"]
    pub mod resolution {
        #[doc = "Register `resolution` reader"]
        pub type R = crate::R<RESOLUTION_SPEC>;
        #[doc = "Register `resolution` writer"]
        pub type W = crate::W<RESOLUTION_SPEC>;
        #[doc = "Field `LINES` reader - pwm resolution"]
        pub type LINES_R = crate::FieldReader<u32>;
        #[doc = "Field `LINES` writer - pwm resolution"]
        pub type LINES_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - pwm resolution"]
            #[inline(always)]
            pub fn lines(&self) -> LINES_R {
                LINES_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - pwm resolution"]
            #[inline(always)]
            #[must_use]
            pub fn lines(&mut self) -> LINES_W<RESOLUTION_SPEC> {
                LINES_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "resolution of pwm\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resolution::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resolution::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RESOLUTION_SPEC;
        impl crate::RegisterSpec for RESOLUTION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`resolution::R`](R) reader structure"]
        impl crate::Readable for RESOLUTION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`resolution::W`](W) writer structure"]
        impl crate::Writable for RESOLUTION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets resolution to value 0"]
        impl crate::Resettable for RESOLUTION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PHASE_SHIFT (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_shift::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_shift::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_shift`]
module"]
    pub type PHASE_SHIFT = crate::Reg<phase_shift::PHASE_SHIFT_SPEC>;
    #[doc = "no description available"]
    pub mod phase_shift {
        #[doc = "Register `PHASE_SHIFT[%s]` reader"]
        pub type R = crate::R<PHASE_SHIFT_SPEC>;
        #[doc = "Register `PHASE_SHIFT[%s]` writer"]
        pub type W = crate::W<PHASE_SHIFT_SPEC>;
        #[doc = "Field `VAL` reader - pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
        pub type VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `VAL` writer - pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<PHASE_SHIFT_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_shift::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_shift::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHASE_SHIFT_SPEC;
        impl crate::RegisterSpec for PHASE_SHIFT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phase_shift::R`](R) reader structure"]
        impl crate::Readable for PHASE_SHIFT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phase_shift::W`](W) writer structure"]
        impl crate::Writable for PHASE_SHIFT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PHASE_SHIFT[%s]
to value 0"]
        impl crate::Resettable for PHASE_SHIFT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PHASE_TABLE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_table::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_table::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phase_table`]
module"]
    pub type PHASE_TABLE = crate::Reg<phase_table::PHASE_TABLE_SPEC>;
    #[doc = "no description available"]
    pub mod phase_table {
        #[doc = "Register `PHASE_TABLE[%s]` reader"]
        pub type R = crate::R<PHASE_TABLE_SPEC>;
        #[doc = "Register `PHASE_TABLE[%s]` writer"]
        pub type W = crate::W<PHASE_TABLE_SPEC>;
        #[doc = "Field `PWM0` reader - pwm phase table value"]
        pub type PWM0_R = crate::FieldReader;
        #[doc = "Field `PWM0` writer - pwm phase table value"]
        pub type PWM0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM1` reader - pwm phase table value"]
        pub type PWM1_R = crate::FieldReader;
        #[doc = "Field `PWM1` writer - pwm phase table value"]
        pub type PWM1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM2` reader - pwm phase table value"]
        pub type PWM2_R = crate::FieldReader;
        #[doc = "Field `PWM2` writer - pwm phase table value"]
        pub type PWM2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM3` reader - pwm phase table value"]
        pub type PWM3_R = crate::FieldReader;
        #[doc = "Field `PWM3` writer - pwm phase table value"]
        pub type PWM3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM4` reader - pwm phase table value"]
        pub type PWM4_R = crate::FieldReader;
        #[doc = "Field `PWM4` writer - pwm phase table value"]
        pub type PWM4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM5` reader - pwm phase table value"]
        pub type PWM5_R = crate::FieldReader;
        #[doc = "Field `PWM5` writer - pwm phase table value"]
        pub type PWM5_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM6` reader - pwm phase table value"]
        pub type PWM6_R = crate::FieldReader;
        #[doc = "Field `PWM6` writer - pwm phase table value"]
        pub type PWM6_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PWM7` reader - pwm phase table value"]
        pub type PWM7_R = crate::FieldReader;
        #[doc = "Field `PWM7` writer - pwm phase table value"]
        pub type PWM7_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bits 0:1 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm0(&self) -> PWM0_R {
                PWM0_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bits 2:3 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm1(&self) -> PWM1_R {
                PWM1_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bits 4:5 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm2(&self) -> PWM2_R {
                PWM2_R::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bits 6:7 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm3(&self) -> PWM3_R {
                PWM3_R::new(((self.bits >> 6) & 3) as u8)
            }
            #[doc = "Bits 8:9 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm4(&self) -> PWM4_R {
                PWM4_R::new(((self.bits >> 8) & 3) as u8)
            }
            #[doc = "Bits 10:11 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm5(&self) -> PWM5_R {
                PWM5_R::new(((self.bits >> 10) & 3) as u8)
            }
            #[doc = "Bits 12:13 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm6(&self) -> PWM6_R {
                PWM6_R::new(((self.bits >> 12) & 3) as u8)
            }
            #[doc = "Bits 14:15 - pwm phase table value"]
            #[inline(always)]
            pub fn pwm7(&self) -> PWM7_R {
                PWM7_R::new(((self.bits >> 14) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm0(&mut self) -> PWM0_W<PHASE_TABLE_SPEC> {
                PWM0_W::new(self, 0)
            }
            #[doc = "Bits 2:3 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm1(&mut self) -> PWM1_W<PHASE_TABLE_SPEC> {
                PWM1_W::new(self, 2)
            }
            #[doc = "Bits 4:5 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm2(&mut self) -> PWM2_W<PHASE_TABLE_SPEC> {
                PWM2_W::new(self, 4)
            }
            #[doc = "Bits 6:7 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm3(&mut self) -> PWM3_W<PHASE_TABLE_SPEC> {
                PWM3_W::new(self, 6)
            }
            #[doc = "Bits 8:9 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm4(&mut self) -> PWM4_W<PHASE_TABLE_SPEC> {
                PWM4_W::new(self, 8)
            }
            #[doc = "Bits 10:11 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm5(&mut self) -> PWM5_W<PHASE_TABLE_SPEC> {
                PWM5_W::new(self, 10)
            }
            #[doc = "Bits 12:13 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm6(&mut self) -> PWM6_W<PHASE_TABLE_SPEC> {
                PWM6_W::new(self, 12)
            }
            #[doc = "Bits 14:15 - pwm phase table value"]
            #[inline(always)]
            #[must_use]
            pub fn pwm7(&mut self) -> PWM7_W<PHASE_TABLE_SPEC> {
                PWM7_W::new(self, 14)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phase_table::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phase_table::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHASE_TABLE_SPEC;
        impl crate::RegisterSpec for PHASE_TABLE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phase_table::R`](R) reader structure"]
        impl crate::Readable for PHASE_TABLE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phase_table::W`](W) writer structure"]
        impl crate::Writable for PHASE_TABLE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PHASE_TABLE[%s]
to value 0"]
        impl crate::Resettable for PHASE_TABLE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "postion_software (rw) register accessor: softwave inject postion\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`postion_software::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`postion_software::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@postion_software`]
module"]
    pub type POSTION_SOFTWARE = crate::Reg<postion_software::POSTION_SOFTWARE_SPEC>;
    #[doc = "softwave inject postion"]
    pub mod postion_software {
        #[doc = "Register `postion_software` reader"]
        pub type R = crate::R<POSTION_SOFTWARE_SPEC>;
        #[doc = "Register `postion_software` writer"]
        pub type W = crate::W<POSTION_SOFTWARE_SPEC>;
        #[doc = "Field `POSTION_SOFTWAVE` reader - softwave inject postion"]
        pub type POSTION_SOFTWAVE_R = crate::FieldReader<u32>;
        #[doc = "Field `POSTION_SOFTWAVE` writer - softwave inject postion"]
        pub type POSTION_SOFTWAVE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - softwave inject postion"]
            #[inline(always)]
            pub fn postion_softwave(&self) -> POSTION_SOFTWAVE_R {
                POSTION_SOFTWAVE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - softwave inject postion"]
            #[inline(always)]
            #[must_use]
            pub fn postion_softwave(&mut self) -> POSTION_SOFTWAVE_W<POSTION_SOFTWARE_SPEC> {
                POSTION_SOFTWAVE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "softwave inject postion\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`postion_software::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`postion_software::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POSTION_SOFTWARE_SPEC;
        impl crate::RegisterSpec for POSTION_SOFTWARE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`postion_software::R`](R) reader structure"]
        impl crate::Readable for POSTION_SOFTWARE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`postion_software::W`](W) writer structure"]
        impl crate::Writable for POSTION_SOFTWARE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets postion_software to value 0"]
        impl crate::Resettable for POSTION_SOFTWARE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "postion_sel (rw) register accessor: select softwave inject postion\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`postion_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`postion_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@postion_sel`]
module"]
    pub type POSTION_SEL = crate::Reg<postion_sel::POSTION_SEL_SPEC>;
    #[doc = "select softwave inject postion"]
    pub mod postion_sel {
        #[doc = "Register `postion_sel` reader"]
        pub type R = crate::R<POSTION_SEL_SPEC>;
        #[doc = "Register `postion_sel` writer"]
        pub type W = crate::W<POSTION_SEL_SPEC>;
        #[doc = "Field `POSTION_SEL` reader - enable softwave inject postion. 0: disable. 1: enable."]
        pub type POSTION_SEL_R = crate::BitReader;
        #[doc = "Field `POSTION_SEL` writer - enable softwave inject postion. 0: disable. 1: enable."]
        pub type POSTION_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - enable softwave inject postion. 0: disable. 1: enable."]
            #[inline(always)]
            pub fn postion_sel(&self) -> POSTION_SEL_R {
                POSTION_SEL_R::new((self.bits & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - enable softwave inject postion. 0: disable. 1: enable."]
            #[inline(always)]
            #[must_use]
            pub fn postion_sel(&mut self) -> POSTION_SEL_W<POSTION_SEL_SPEC> {
                POSTION_SEL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "select softwave inject postion\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`postion_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`postion_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POSTION_SEL_SPEC;
        impl crate::RegisterSpec for POSTION_SEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`postion_sel::R`](R) reader structure"]
        impl crate::Readable for POSTION_SEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`postion_sel::W`](W) writer structure"]
        impl crate::Writable for POSTION_SEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets postion_sel to value 0"]
        impl crate::Resettable for POSTION_SEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "status (rw) register accessor: qeo status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
    pub type STATUS = crate::Reg<status::STATUS_SPEC>;
    #[doc = "qeo status"]
    pub mod status {
        #[doc = "Register `status` reader"]
        pub type R = crate::R<STATUS_SPEC>;
        #[doc = "Register `status` writer"]
        pub type W = crate::W<STATUS_SPEC>;
        #[doc = "Field `PWM_SAFETY` reader - pwm_fault status"]
        pub type PWM_SAFETY_R = crate::BitReader;
        #[doc = "Field `PWM_FOURCE` reader - qeo_pwm_force observe"]
        pub type PWM_FOURCE_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bit 0 - pwm_fault status"]
            #[inline(always)]
            pub fn pwm_safety(&self) -> PWM_SAFETY_R {
                PWM_SAFETY_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 16:31 - qeo_pwm_force observe"]
            #[inline(always)]
            pub fn pwm_fource(&self) -> PWM_FOURCE_R {
                PWM_FOURCE_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "qeo status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STATUS_SPEC;
        impl crate::RegisterSpec for STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`status::R`](R) reader structure"]
        impl crate::Readable for STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
        impl crate::Writable for STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets status to value 0"]
        impl crate::Resettable for STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "debug0 (rw) register accessor: qeo debug 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug0`]
module"]
    pub type DEBUG0 = crate::Reg<debug0::DEBUG0_SPEC>;
    #[doc = "qeo debug 0"]
    pub mod debug0 {
        #[doc = "Register `debug0` reader"]
        pub type R = crate::R<DEBUG0_SPEC>;
        #[doc = "Register `debug0` writer"]
        pub type W = crate::W<DEBUG0_SPEC>;
        #[doc = "Field `WAVE0` reader - wave0 observe"]
        pub type WAVE0_R = crate::FieldReader<u16>;
        #[doc = "Field `WAVE1` reader - wave1 observe"]
        pub type WAVE1_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - wave0 observe"]
            #[inline(always)]
            pub fn wave0(&self) -> WAVE0_R {
                WAVE0_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - wave1 observe"]
            #[inline(always)]
            pub fn wave1(&self) -> WAVE1_R {
                WAVE1_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "qeo debug 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DEBUG0_SPEC;
        impl crate::RegisterSpec for DEBUG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`debug0::R`](R) reader structure"]
        impl crate::Readable for DEBUG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`debug0::W`](W) writer structure"]
        impl crate::Writable for DEBUG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets debug0 to value 0"]
        impl crate::Resettable for DEBUG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "debug1 (rw) register accessor: qeo debug 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug1`]
module"]
    pub type DEBUG1 = crate::Reg<debug1::DEBUG1_SPEC>;
    #[doc = "qeo debug 1"]
    pub mod debug1 {
        #[doc = "Register `debug1` reader"]
        pub type R = crate::R<DEBUG1_SPEC>;
        #[doc = "Register `debug1` writer"]
        pub type W = crate::W<DEBUG1_SPEC>;
        #[doc = "Field `WAVE2` reader - wave2 observe"]
        pub type WAVE2_R = crate::FieldReader<u16>;
        #[doc = "Field `WAVE_A` reader - wave_a observe"]
        pub type WAVE_A_R = crate::BitReader;
        #[doc = "Field `WAVE_B` reader - wave_b observe"]
        pub type WAVE_B_R = crate::BitReader;
        #[doc = "Field `WAVE_Z` reader - wave_z observe"]
        pub type WAVE_Z_R = crate::BitReader;
        #[doc = "Field `QEO_FINISH` reader - qeo finish observe"]
        pub type QEO_FINISH_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:15 - wave2 observe"]
            #[inline(always)]
            pub fn wave2(&self) -> WAVE2_R {
                WAVE2_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bit 16 - wave_a observe"]
            #[inline(always)]
            pub fn wave_a(&self) -> WAVE_A_R {
                WAVE_A_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 20 - wave_b observe"]
            #[inline(always)]
            pub fn wave_b(&self) -> WAVE_B_R {
                WAVE_B_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 24 - wave_z observe"]
            #[inline(always)]
            pub fn wave_z(&self) -> WAVE_Z_R {
                WAVE_Z_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 28 - qeo finish observe"]
            #[inline(always)]
            pub fn qeo_finish(&self) -> QEO_FINISH_R {
                QEO_FINISH_R::new(((self.bits >> 28) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "qeo debug 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DEBUG1_SPEC;
        impl crate::RegisterSpec for DEBUG1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`debug1::R`](R) reader structure"]
        impl crate::Readable for DEBUG1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`debug1::W`](W) writer structure"]
        impl crate::Writable for DEBUG1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets debug1 to value 0"]
        impl crate::Resettable for DEBUG1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "debug2 (rw) register accessor: qeo debug 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug2`]
module"]
    pub type DEBUG2 = crate::Reg<debug2::DEBUG2_SPEC>;
    #[doc = "qeo debug 2"]
    pub mod debug2 {
        #[doc = "Register `debug2` reader"]
        pub type R = crate::R<DEBUG2_SPEC>;
        #[doc = "Register `debug2` writer"]
        pub type W = crate::W<DEBUG2_SPEC>;
        #[doc = "Field `ABZ_OWN_POSTION` reader - abz_own_postion observe"]
        pub type ABZ_OWN_POSTION_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - abz_own_postion observe"]
            #[inline(always)]
            pub fn abz_own_postion(&self) -> ABZ_OWN_POSTION_R {
                ABZ_OWN_POSTION_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "qeo debug 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DEBUG2_SPEC;
        impl crate::RegisterSpec for DEBUG2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`debug2::R`](R) reader structure"]
        impl crate::Readable for DEBUG2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`debug2::W`](W) writer structure"]
        impl crate::Writable for DEBUG2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets debug2 to value 0"]
        impl crate::Resettable for DEBUG2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "debug3 (rw) register accessor: qeo debug 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug3`]
module"]
    pub type DEBUG3 = crate::Reg<debug3::DEBUG3_SPEC>;
    #[doc = "qeo debug 3"]
    pub mod debug3 {
        #[doc = "Register `debug3` reader"]
        pub type R = crate::R<DEBUG3_SPEC>;
        #[doc = "Register `debug3` writer"]
        pub type W = crate::W<DEBUG3_SPEC>;
        #[doc = "Field `ABZ_OWN_POSTION` reader - abz_own_postion observe"]
        pub type ABZ_OWN_POSTION_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - abz_own_postion observe"]
            #[inline(always)]
            pub fn abz_own_postion(&self) -> ABZ_OWN_POSTION_R {
                ABZ_OWN_POSTION_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "qeo debug 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DEBUG3_SPEC;
        impl crate::RegisterSpec for DEBUG3_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`debug3::R`](R) reader structure"]
        impl crate::Readable for DEBUG3_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`debug3::W`](W) writer structure"]
        impl crate::Writable for DEBUG3_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets debug3 to value 0"]
        impl crate::Resettable for DEBUG3_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "QEO1"]
pub struct QEO1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for QEO1 {}
impl QEO1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const qeo0::RegisterBlock = 0xf030_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const qeo0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for QEO1 {
    type Target = qeo0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for QEO1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("QEO1").finish()
    }
}
#[doc = "QEO1"]
pub use self::qeo0 as qeo1;
#[doc = "MMC0"]
pub struct MMC0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MMC0 {}
impl MMC0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mmc0::RegisterBlock = 0xf031_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mmc0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MMC0 {
    type Target = mmc0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MMC0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MMC0").finish()
    }
}
#[doc = "MMC0"]
pub mod mmc0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        cr: CR,
        sta: STA,
        int_en: INT_EN,
        sysclk_freq: SYSCLK_FREQ,
        sysclk_period: SYSCLK_PERIOD,
        oosync_theta_thr: OOSYNC_THETA_THR,
        discrete_cfg0: DISCRETE_CFG0,
        discrete_cfg1: DISCRETE_CFG1,
        cont_cfg0: CONT_CFG0,
        ini_pos_time: INI_POS_TIME,
        ini_pos: INI_POS,
        ini_rev: INI_REV,
        ini_speed: INI_SPEED,
        ini_accel: INI_ACCEL,
        ini_coef_time: INI_COEF_TIME,
        ini_pcoef: INI_PCOEF,
        ini_icoef: INI_ICOEF,
        ini_acoef: INI_ACOEF,
        estm_tim: ESTM_TIM,
        estm_pos: ESTM_POS,
        estm_rev: ESTM_REV,
        estm_speed: ESTM_SPEED,
        estm_accel: ESTM_ACCEL,
        cur_pcoef: CUR_PCOEF,
        cur_icoef: CUR_ICOEF,
        cur_acoef: CUR_ACOEF,
        ini_delta_pos_time: INI_DELTA_POS_TIME,
        ini_delta_pos: INI_DELTA_POS,
        ini_delta_rev: INI_DELTA_REV,
        ini_delta_speed: INI_DELTA_SPEED,
        ini_delta_accel: INI_DELTA_ACCEL,
        _reserved31: [u8; 0x04],
        pos_trg_cfg: POS_TRG_CFG,
        pos_trg_pos_thr: POS_TRG_POS_THR,
        pos_trg_rev_thr: POS_TRG_REV_THR,
        speed_trg_cfg: SPEED_TRG_CFG,
        speed_trg_thr: SPEED_TRG_THR,
        _reserved36: [u8; 0x0c],
        coef_trg_cfg: [COEF_TRG_CFG; 3],
        _reserved37: [u8; 0x24],
        br: [BR; 2],
        bk0_timestamp: BK0_TIMESTAMP,
        bk0_position: BK0_POSITION,
        bk0_revolution: BK0_REVOLUTION,
        bk0_speed: BK0_SPEED,
        bk0_accelerator: BK0_ACCELERATOR,
        _reserved43: [u8; 0x0c],
        bk1_timestamp: BK1_TIMESTAMP,
        bk1_position: BK1_POSITION,
        bk1_revolution: BK1_REVOLUTION,
        bk1_speed: BK1_SPEED,
        bk1_accelerator: BK1_ACCELERATOR,
    }
    impl RegisterBlock {
        #[doc = "0x00 - Control Register"]
        #[inline(always)]
        pub const fn cr(&self) -> &CR {
            &self.cr
        }
        #[doc = "0x04 - Status Register"]
        #[inline(always)]
        pub const fn sta(&self) -> &STA {
            &self.sta
        }
        #[doc = "0x08 - Interrupt Enable Register"]
        #[inline(always)]
        pub const fn int_en(&self) -> &INT_EN {
            &self.int_en
        }
        #[doc = "0x0c - System Clock Frequency Register"]
        #[inline(always)]
        pub const fn sysclk_freq(&self) -> &SYSCLK_FREQ {
            &self.sysclk_freq
        }
        #[doc = "0x10 - System Clock Period Register"]
        #[inline(always)]
        pub const fn sysclk_period(&self) -> &SYSCLK_PERIOD {
            &self.sysclk_period
        }
        #[doc = "0x14 - Position Out-Of-Sync Threshold Regster"]
        #[inline(always)]
        pub const fn oosync_theta_thr(&self) -> &OOSYNC_THETA_THR {
            &self.oosync_theta_thr
        }
        #[doc = "0x18 - Discrete Mode Configuration 0 Register"]
        #[inline(always)]
        pub const fn discrete_cfg0(&self) -> &DISCRETE_CFG0 {
            &self.discrete_cfg0
        }
        #[doc = "0x1c - Discrete Mode Configuration 1 Register"]
        #[inline(always)]
        pub const fn discrete_cfg1(&self) -> &DISCRETE_CFG1 {
            &self.discrete_cfg1
        }
        #[doc = "0x20 - Continuous Mode Configuration 0 Register"]
        #[inline(always)]
        pub const fn cont_cfg0(&self) -> &CONT_CFG0 {
            &self.cont_cfg0
        }
        #[doc = "0x24 - The destined timestamp register for position initialization"]
        #[inline(always)]
        pub const fn ini_pos_time(&self) -> &INI_POS_TIME {
            &self.ini_pos_time
        }
        #[doc = "0x28 - The destined position register for position initialization"]
        #[inline(always)]
        pub const fn ini_pos(&self) -> &INI_POS {
            &self.ini_pos
        }
        #[doc = "0x2c - The destined revolution register for position initialization"]
        #[inline(always)]
        pub const fn ini_rev(&self) -> &INI_REV {
            &self.ini_rev
        }
        #[doc = "0x30 - The destined speed register for position initialization"]
        #[inline(always)]
        pub const fn ini_speed(&self) -> &INI_SPEED {
            &self.ini_speed
        }
        #[doc = "0x34 - The destined accelerator register for position initialization"]
        #[inline(always)]
        pub const fn ini_accel(&self) -> &INI_ACCEL {
            &self.ini_accel
        }
        #[doc = "0x38 - The destined timestamp register for coefficients initialization"]
        #[inline(always)]
        pub const fn ini_coef_time(&self) -> &INI_COEF_TIME {
            &self.ini_coef_time
        }
        #[doc = "0x3c - The destined coefficient P register for coefficients initialization"]
        #[inline(always)]
        pub const fn ini_pcoef(&self) -> &INI_PCOEF {
            &self.ini_pcoef
        }
        #[doc = "0x40 - The destined coefficient I register for coefficients initialization"]
        #[inline(always)]
        pub const fn ini_icoef(&self) -> &INI_ICOEF {
            &self.ini_icoef
        }
        #[doc = "0x44 - The destined coefficient A register for coefficients initialization"]
        #[inline(always)]
        pub const fn ini_acoef(&self) -> &INI_ACOEF {
            &self.ini_acoef
        }
        #[doc = "0x48 - The timestamp register for internal estimation"]
        #[inline(always)]
        pub const fn estm_tim(&self) -> &ESTM_TIM {
            &self.estm_tim
        }
        #[doc = "0x4c - The position register for the internal estimation"]
        #[inline(always)]
        pub const fn estm_pos(&self) -> &ESTM_POS {
            &self.estm_pos
        }
        #[doc = "0x50 - The revolution register for the internal estimation"]
        #[inline(always)]
        pub const fn estm_rev(&self) -> &ESTM_REV {
            &self.estm_rev
        }
        #[doc = "0x54 - The speed register for the internal estimation"]
        #[inline(always)]
        pub const fn estm_speed(&self) -> &ESTM_SPEED {
            &self.estm_speed
        }
        #[doc = "0x58 - The accelerator register for theinternal estimation"]
        #[inline(always)]
        pub const fn estm_accel(&self) -> &ESTM_ACCEL {
            &self.estm_accel
        }
        #[doc = "0x5c - The coefficient P register for the internal estimation"]
        #[inline(always)]
        pub const fn cur_pcoef(&self) -> &CUR_PCOEF {
            &self.cur_pcoef
        }
        #[doc = "0x60 - The coefficient I register for the internal estimation"]
        #[inline(always)]
        pub const fn cur_icoef(&self) -> &CUR_ICOEF {
            &self.cur_icoef
        }
        #[doc = "0x64 - The coefficient A register for the internal estimation"]
        #[inline(always)]
        pub const fn cur_acoef(&self) -> &CUR_ACOEF {
            &self.cur_acoef
        }
        #[doc = "0x68 - The destined timestamp register for delta position initialization"]
        #[inline(always)]
        pub const fn ini_delta_pos_time(&self) -> &INI_DELTA_POS_TIME {
            &self.ini_delta_pos_time
        }
        #[doc = "0x6c - The destined delta position register for delta position initialization"]
        #[inline(always)]
        pub const fn ini_delta_pos(&self) -> &INI_DELTA_POS {
            &self.ini_delta_pos
        }
        #[doc = "0x70 - The destined delta revolution register for delta position initialization"]
        #[inline(always)]
        pub const fn ini_delta_rev(&self) -> &INI_DELTA_REV {
            &self.ini_delta_rev
        }
        #[doc = "0x74 - The destined delta speed register for delta position initialization"]
        #[inline(always)]
        pub const fn ini_delta_speed(&self) -> &INI_DELTA_SPEED {
            &self.ini_delta_speed
        }
        #[doc = "0x78 - The destined delta accelerator register for delta position initialization"]
        #[inline(always)]
        pub const fn ini_delta_accel(&self) -> &INI_DELTA_ACCEL {
            &self.ini_delta_accel
        }
        #[doc = "0x80 - Tracking Configuration pos trigger cfg"]
        #[inline(always)]
        pub const fn pos_trg_cfg(&self) -> &POS_TRG_CFG {
            &self.pos_trg_cfg
        }
        #[doc = "0x84 - Tracking Configuration position threshold"]
        #[inline(always)]
        pub const fn pos_trg_pos_thr(&self) -> &POS_TRG_POS_THR {
            &self.pos_trg_pos_thr
        }
        #[doc = "0x88 - Tracking Configuration revolution threshold"]
        #[inline(always)]
        pub const fn pos_trg_rev_thr(&self) -> &POS_TRG_REV_THR {
            &self.pos_trg_rev_thr
        }
        #[doc = "0x8c - Tracking Configuration speed trigger cfg"]
        #[inline(always)]
        pub const fn speed_trg_cfg(&self) -> &SPEED_TRG_CFG {
            &self.speed_trg_cfg
        }
        #[doc = "0x90 - Tracking Configuration speed threshold"]
        #[inline(always)]
        pub const fn speed_trg_thr(&self) -> &SPEED_TRG_THR {
            &self.speed_trg_thr
        }
        #[doc = "0xa0..0xdc - no description available"]
        #[inline(always)]
        pub const fn coef_trg_cfg(&self, n: usize) -> &COEF_TRG_CFG {
            &self.coef_trg_cfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0xa0..0xdc - no description available"]
        #[inline(always)]
        pub fn coef_trg_cfg_iter(&self) -> impl Iterator<Item = &COEF_TRG_CFG> {
            self.coef_trg_cfg.iter()
        }
        #[doc = "0x100..0x300 - no description available"]
        #[inline(always)]
        pub const fn br(&self, n: usize) -> &BR {
            &self.br[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x100..0x300 - no description available"]
        #[inline(always)]
        pub fn br_iter(&self) -> impl Iterator<Item = &BR> {
            self.br.iter()
        }
        #[doc = "0x300 - Monitor of the just received input timestamp for tracing logic"]
        #[inline(always)]
        pub const fn bk0_timestamp(&self) -> &BK0_TIMESTAMP {
            &self.bk0_timestamp
        }
        #[doc = "0x304 - Monitor of the just received input position for tracing logic"]
        #[inline(always)]
        pub const fn bk0_position(&self) -> &BK0_POSITION {
            &self.bk0_position
        }
        #[doc = "0x308 - Monitor of the just received input revolution for tracing logic"]
        #[inline(always)]
        pub const fn bk0_revolution(&self) -> &BK0_REVOLUTION {
            &self.bk0_revolution
        }
        #[doc = "0x30c - Monitor of the just received input speed for tracing logic"]
        #[inline(always)]
        pub const fn bk0_speed(&self) -> &BK0_SPEED {
            &self.bk0_speed
        }
        #[doc = "0x310 - Monitor of the just received input acceleration for tracing logic"]
        #[inline(always)]
        pub const fn bk0_accelerator(&self) -> &BK0_ACCELERATOR {
            &self.bk0_accelerator
        }
        #[doc = "0x320 - Monitor of the previous received input timestamp for tracing logic"]
        #[inline(always)]
        pub const fn bk1_timestamp(&self) -> &BK1_TIMESTAMP {
            &self.bk1_timestamp
        }
        #[doc = "0x324 - Monitor of the previous received input position for tracing logic"]
        #[inline(always)]
        pub const fn bk1_position(&self) -> &BK1_POSITION {
            &self.bk1_position
        }
        #[doc = "0x328 - Monitor of the previous received input revolution for tracing logic"]
        #[inline(always)]
        pub const fn bk1_revolution(&self) -> &BK1_REVOLUTION {
            &self.bk1_revolution
        }
        #[doc = "0x32c - Monitor of the previous received input speed for tracing logic"]
        #[inline(always)]
        pub const fn bk1_speed(&self) -> &BK1_SPEED {
            &self.bk1_speed
        }
        #[doc = "0x330 - Monitor of the previous received input acceleration for tracing logic"]
        #[inline(always)]
        pub const fn bk1_accelerator(&self) -> &BK1_ACCELERATOR {
            &self.bk1_accelerator
        }
    }
    #[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
module"]
    pub type CR = crate::Reg<cr::CR_SPEC>;
    #[doc = "Control Register"]
    pub mod cr {
        #[doc = "Register `CR` reader"]
        pub type R = crate::R<CR_SPEC>;
        #[doc = "Register `CR` writer"]
        pub type W = crate::W<CR_SPEC>;
        #[doc = "Field `MOD_EN` reader - Module Enable"]
        pub type MOD_EN_R = crate::BitReader;
        #[doc = "Field `MOD_EN` writer - Module Enable"]
        pub type MOD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISCRETETRC` reader - 1: Discrete position input 0: Continuous position input"]
        pub type DISCRETETRC_R = crate::BitReader;
        #[doc = "Field `DISCRETETRC` writer - 1: Discrete position input 0: Continuous position input"]
        pub type DISCRETETRC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ADJOP` reader - 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. 0: Continuous tracking mode, without any boundary check"]
        pub type ADJOP_R = crate::BitReader;
        #[doc = "Field `ADJOP` writer - 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. 0: Continuous tracking mode, without any boundary check"]
        pub type ADJOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SHADOW_RD_REQ` reader - 1: Shadow Request for read of tracking parameters. Auto clear 0:"]
        pub type SHADOW_RD_REQ_R = crate::BitReader;
        #[doc = "Field `SHADOW_RD_REQ` writer - 1: Shadow Request for read of tracking parameters. Auto clear 0:"]
        pub type SHADOW_RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_COEFS_CMD` reader - 1: Command to reload the coefs. Auto clear 0:"]
        pub type INI_COEFS_CMD_R = crate::BitReader;
        #[doc = "Field `INI_COEFS_CMD` writer - 1: Command to reload the coefs. Auto clear 0:"]
        pub type INI_COEFS_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_COEFS_CMD_MSK` reader - 1: change 0: won't change bit 2: for ACOEF bit 1: for ICOEF bit 0: for PCOEF"]
        pub type INI_COEFS_CMD_MSK_R = crate::FieldReader;
        #[doc = "Field `INI_COEFS_CMD_MSK` writer - 1: change 0: won't change bit 2: for ACOEF bit 1: for ICOEF bit 0: for PCOEF"]
        pub type INI_COEFS_CMD_MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `INI_POS_REQ` reader - 1: Command to reload the positions. Auto clear 0:"]
        pub type INI_POS_REQ_R = crate::BitReader;
        #[doc = "Field `INI_POS_REQ` writer - 1: Command to reload the positions. Auto clear 0:"]
        pub type INI_POS_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_POS_CMD_MSK` reader - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
        pub type INI_POS_CMD_MSK_R = crate::FieldReader;
        #[doc = "Field `INI_POS_CMD_MSK` writer - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
        pub type INI_POS_CMD_MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `POS_TYPE` reader - 1: 32-bit for rev+pos, with each element occupying 16 bits 0: 32-bit for rev, and 32 bit for pos When CR\\[MANUAL_IO\\]==1, 1: means that the INI_POS is acting as INI_POS cmds 0: means that the INI_POS is simulating the input of iposition and itimestamp"]
        pub type POS_TYPE_R = crate::BitReader;
        #[doc = "Field `POS_TYPE` writer - 1: 32-bit for rev+pos, with each element occupying 16 bits 0: 32-bit for rev, and 32 bit for pos When CR\\[MANUAL_IO\\]==1, 1: means that the INI_POS is acting as INI_POS cmds 0: means that the INI_POS is simulating the input of iposition and itimestamp"]
        pub type POS_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OPEN_LOOP_MODE` reader - 1: in open loop mode 0: not in open loop mode"]
        pub type OPEN_LOOP_MODE_R = crate::BitReader;
        #[doc = "Field `OPEN_LOOP_MODE` writer - 1: in open loop mode 0: not in open loop mode"]
        pub type OPEN_LOOP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_DELTA_POS_REQ` reader - 1: Command to reload the delta pos. Auto clear 0:"]
        pub type INI_DELTA_POS_REQ_R = crate::BitReader;
        #[doc = "Field `INI_DELTA_POS_REQ` writer - 1: Command to reload the delta pos. Auto clear 0:"]
        pub type INI_DELTA_POS_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_DELTA_POS_CMD_MSK` reader - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
        pub type INI_DELTA_POS_CMD_MSK_R = crate::FieldReader;
        #[doc = "Field `INI_DELTA_POS_CMD_MSK` writer - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
        pub type INI_DELTA_POS_CMD_MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `INI_POS_TRG_TYPE` reader - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
        pub type INI_POS_TRG_TYPE_R = crate::FieldReader;
        #[doc = "Field `INI_POS_TRG_TYPE` writer - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
        pub type INI_POS_TRG_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `INI_DELTA_POS_TRG_TYPE` reader - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
        pub type INI_DELTA_POS_TRG_TYPE_R = crate::FieldReader;
        #[doc = "Field `INI_DELTA_POS_TRG_TYPE` writer - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
        pub type INI_DELTA_POS_TRG_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `MS_COEF_EN` reader - Multiple Coefficients Enable"]
        pub type MS_COEF_EN_R = crate::BitReader;
        #[doc = "Field `MS_COEF_EN` writer - Multiple Coefficients Enable"]
        pub type MS_COEF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FRCACCELZERO` reader - Zeroise the accelerator calculation."]
        pub type FRCACCELZERO_R = crate::BitReader;
        #[doc = "Field `FRCACCELZERO` writer - Zeroise the accelerator calculation."]
        pub type FRCACCELZERO_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_BR1_POS_REQ` reader - Auto clear. Only effective in open_loop mode."]
        pub type INI_BR1_POS_REQ_R = crate::BitReader;
        #[doc = "Field `INI_BR1_POS_REQ` writer - Auto clear. Only effective in open_loop mode."]
        pub type INI_BR1_POS_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_BR0_POS_REQ` reader - Auto clear. Only effective in open_loop mode."]
        pub type INI_BR0_POS_REQ_R = crate::BitReader;
        #[doc = "Field `INI_BR0_POS_REQ` writer - Auto clear. Only effective in open_loop mode."]
        pub type INI_BR0_POS_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SFTRST` reader - Software reset, high active. When write 1 ,all internal logical will be reset. 0b - No action 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected."]
        pub type SFTRST_R = crate::BitReader;
        #[doc = "Field `SFTRST` writer - Software reset, high active. When write 1 ,all internal logical will be reset. 0b - No action 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected."]
        pub type SFTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Module Enable"]
            #[inline(always)]
            pub fn mod_en(&self) -> MOD_EN_R {
                MOD_EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - 1: Discrete position input 0: Continuous position input"]
            #[inline(always)]
            pub fn discretetrc(&self) -> DISCRETETRC_R {
                DISCRETETRC_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. 0: Continuous tracking mode, without any boundary check"]
            #[inline(always)]
            pub fn adjop(&self) -> ADJOP_R {
                ADJOP_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - 1: Shadow Request for read of tracking parameters. Auto clear 0:"]
            #[inline(always)]
            pub fn shadow_rd_req(&self) -> SHADOW_RD_REQ_R {
                SHADOW_RD_REQ_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - 1: Command to reload the coefs. Auto clear 0:"]
            #[inline(always)]
            pub fn ini_coefs_cmd(&self) -> INI_COEFS_CMD_R {
                INI_COEFS_CMD_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bits 5:7 - 1: change 0: won't change bit 2: for ACOEF bit 1: for ICOEF bit 0: for PCOEF"]
            #[inline(always)]
            pub fn ini_coefs_cmd_msk(&self) -> INI_COEFS_CMD_MSK_R {
                INI_COEFS_CMD_MSK_R::new(((self.bits >> 5) & 7) as u8)
            }
            #[doc = "Bit 8 - 1: Command to reload the positions. Auto clear 0:"]
            #[inline(always)]
            pub fn ini_pos_req(&self) -> INI_POS_REQ_R {
                INI_POS_REQ_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bits 9:12 - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
            #[inline(always)]
            pub fn ini_pos_cmd_msk(&self) -> INI_POS_CMD_MSK_R {
                INI_POS_CMD_MSK_R::new(((self.bits >> 9) & 0x0f) as u8)
            }
            #[doc = "Bit 13 - 1: 32-bit for rev+pos, with each element occupying 16 bits 0: 32-bit for rev, and 32 bit for pos When CR\\[MANUAL_IO\\]==1, 1: means that the INI_POS is acting as INI_POS cmds 0: means that the INI_POS is simulating the input of iposition and itimestamp"]
            #[inline(always)]
            pub fn pos_type(&self) -> POS_TYPE_R {
                POS_TYPE_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - 1: in open loop mode 0: not in open loop mode"]
            #[inline(always)]
            pub fn open_loop_mode(&self) -> OPEN_LOOP_MODE_R {
                OPEN_LOOP_MODE_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - 1: Command to reload the delta pos. Auto clear 0:"]
            #[inline(always)]
            pub fn ini_delta_pos_req(&self) -> INI_DELTA_POS_REQ_R {
                INI_DELTA_POS_REQ_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bits 16:19 - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
            #[inline(always)]
            pub fn ini_delta_pos_cmd_msk(&self) -> INI_DELTA_POS_CMD_MSK_R {
                INI_DELTA_POS_CMD_MSK_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bits 20:22 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
            #[inline(always)]
            pub fn ini_pos_trg_type(&self) -> INI_POS_TRG_TYPE_R {
                INI_POS_TRG_TYPE_R::new(((self.bits >> 20) & 7) as u8)
            }
            #[doc = "Bits 23:25 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
            #[inline(always)]
            pub fn ini_delta_pos_trg_type(&self) -> INI_DELTA_POS_TRG_TYPE_R {
                INI_DELTA_POS_TRG_TYPE_R::new(((self.bits >> 23) & 7) as u8)
            }
            #[doc = "Bit 26 - Multiple Coefficients Enable"]
            #[inline(always)]
            pub fn ms_coef_en(&self) -> MS_COEF_EN_R {
                MS_COEF_EN_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - Zeroise the accelerator calculation."]
            #[inline(always)]
            pub fn frcaccelzero(&self) -> FRCACCELZERO_R {
                FRCACCELZERO_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - Auto clear. Only effective in open_loop mode."]
            #[inline(always)]
            pub fn ini_br1_pos_req(&self) -> INI_BR1_POS_REQ_R {
                INI_BR1_POS_REQ_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - Auto clear. Only effective in open_loop mode."]
            #[inline(always)]
            pub fn ini_br0_pos_req(&self) -> INI_BR0_POS_REQ_R {
                INI_BR0_POS_REQ_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 31 - Software reset, high active. When write 1 ,all internal logical will be reset. 0b - No action 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected."]
            #[inline(always)]
            pub fn sftrst(&self) -> SFTRST_R {
                SFTRST_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Module Enable"]
            #[inline(always)]
            #[must_use]
            pub fn mod_en(&mut self) -> MOD_EN_W<CR_SPEC> {
                MOD_EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - 1: Discrete position input 0: Continuous position input"]
            #[inline(always)]
            #[must_use]
            pub fn discretetrc(&mut self) -> DISCRETETRC_W<CR_SPEC> {
                DISCRETETRC_W::new(self, 1)
            }
            #[doc = "Bit 2 - 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. 0: Continuous tracking mode, without any boundary check"]
            #[inline(always)]
            #[must_use]
            pub fn adjop(&mut self) -> ADJOP_W<CR_SPEC> {
                ADJOP_W::new(self, 2)
            }
            #[doc = "Bit 3 - 1: Shadow Request for read of tracking parameters. Auto clear 0:"]
            #[inline(always)]
            #[must_use]
            pub fn shadow_rd_req(&mut self) -> SHADOW_RD_REQ_W<CR_SPEC> {
                SHADOW_RD_REQ_W::new(self, 3)
            }
            #[doc = "Bit 4 - 1: Command to reload the coefs. Auto clear 0:"]
            #[inline(always)]
            #[must_use]
            pub fn ini_coefs_cmd(&mut self) -> INI_COEFS_CMD_W<CR_SPEC> {
                INI_COEFS_CMD_W::new(self, 4)
            }
            #[doc = "Bits 5:7 - 1: change 0: won't change bit 2: for ACOEF bit 1: for ICOEF bit 0: for PCOEF"]
            #[inline(always)]
            #[must_use]
            pub fn ini_coefs_cmd_msk(&mut self) -> INI_COEFS_CMD_MSK_W<CR_SPEC> {
                INI_COEFS_CMD_MSK_W::new(self, 5)
            }
            #[doc = "Bit 8 - 1: Command to reload the positions. Auto clear 0:"]
            #[inline(always)]
            #[must_use]
            pub fn ini_pos_req(&mut self) -> INI_POS_REQ_W<CR_SPEC> {
                INI_POS_REQ_W::new(self, 8)
            }
            #[doc = "Bits 9:12 - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
            #[inline(always)]
            #[must_use]
            pub fn ini_pos_cmd_msk(&mut self) -> INI_POS_CMD_MSK_W<CR_SPEC> {
                INI_POS_CMD_MSK_W::new(self, 9)
            }
            #[doc = "Bit 13 - 1: 32-bit for rev+pos, with each element occupying 16 bits 0: 32-bit for rev, and 32 bit for pos When CR\\[MANUAL_IO\\]==1, 1: means that the INI_POS is acting as INI_POS cmds 0: means that the INI_POS is simulating the input of iposition and itimestamp"]
            #[inline(always)]
            #[must_use]
            pub fn pos_type(&mut self) -> POS_TYPE_W<CR_SPEC> {
                POS_TYPE_W::new(self, 13)
            }
            #[doc = "Bit 14 - 1: in open loop mode 0: not in open loop mode"]
            #[inline(always)]
            #[must_use]
            pub fn open_loop_mode(&mut self) -> OPEN_LOOP_MODE_W<CR_SPEC> {
                OPEN_LOOP_MODE_W::new(self, 14)
            }
            #[doc = "Bit 15 - 1: Command to reload the delta pos. Auto clear 0:"]
            #[inline(always)]
            #[must_use]
            pub fn ini_delta_pos_req(&mut self) -> INI_DELTA_POS_REQ_W<CR_SPEC> {
                INI_DELTA_POS_REQ_W::new(self, 15)
            }
            #[doc = "Bits 16:19 - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
            #[inline(always)]
            #[must_use]
            pub fn ini_delta_pos_cmd_msk(&mut self) -> INI_DELTA_POS_CMD_MSK_W<CR_SPEC> {
                INI_DELTA_POS_CMD_MSK_W::new(self, 16)
            }
            #[doc = "Bits 20:22 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
            #[inline(always)]
            #[must_use]
            pub fn ini_pos_trg_type(&mut self) -> INI_POS_TRG_TYPE_W<CR_SPEC> {
                INI_POS_TRG_TYPE_W::new(self, 20)
            }
            #[doc = "Bits 23:25 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: triggered by self position trigger 6: triggered by self speed trigger Otherser: no function"]
            #[inline(always)]
            #[must_use]
            pub fn ini_delta_pos_trg_type(&mut self) -> INI_DELTA_POS_TRG_TYPE_W<CR_SPEC> {
                INI_DELTA_POS_TRG_TYPE_W::new(self, 23)
            }
            #[doc = "Bit 26 - Multiple Coefficients Enable"]
            #[inline(always)]
            #[must_use]
            pub fn ms_coef_en(&mut self) -> MS_COEF_EN_W<CR_SPEC> {
                MS_COEF_EN_W::new(self, 26)
            }
            #[doc = "Bit 27 - Zeroise the accelerator calculation."]
            #[inline(always)]
            #[must_use]
            pub fn frcaccelzero(&mut self) -> FRCACCELZERO_W<CR_SPEC> {
                FRCACCELZERO_W::new(self, 27)
            }
            #[doc = "Bit 28 - Auto clear. Only effective in open_loop mode."]
            #[inline(always)]
            #[must_use]
            pub fn ini_br1_pos_req(&mut self) -> INI_BR1_POS_REQ_W<CR_SPEC> {
                INI_BR1_POS_REQ_W::new(self, 28)
            }
            #[doc = "Bit 29 - Auto clear. Only effective in open_loop mode."]
            #[inline(always)]
            #[must_use]
            pub fn ini_br0_pos_req(&mut self) -> INI_BR0_POS_REQ_W<CR_SPEC> {
                INI_BR0_POS_REQ_W::new(self, 29)
            }
            #[doc = "Bit 31 - Software reset, high active. When write 1 ,all internal logical will be reset. 0b - No action 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected."]
            #[inline(always)]
            #[must_use]
            pub fn sftrst(&mut self) -> SFTRST_W<CR_SPEC> {
                SFTRST_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CR_SPEC;
        impl crate::RegisterSpec for CR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cr::R`](R) reader structure"]
        impl crate::Readable for CR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cr::W`](W) writer structure"]
        impl crate::Writable for CR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CR to value 0"]
        impl crate::Resettable for CR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "STA (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sta`]
module"]
    pub type STA = crate::Reg<sta::STA_SPEC>;
    #[doc = "Status Register"]
    pub mod sta {
        #[doc = "Register `STA` reader"]
        pub type R = crate::R<STA_SPEC>;
        #[doc = "Register `STA` writer"]
        pub type W = crate::W<STA_SPEC>;
        #[doc = "Field `SHADOW_RD_DONE` reader - Shadow ready for read. Auto cleared by setting CR\\[SHADOW_RD_REQ\\]
as 1"]
        pub type SHADOW_RD_DONE_R = crate::BitReader;
        #[doc = "Field `INI_COEFS_CMD_DONE` writer - W1C"]
        pub type INI_COEFS_CMD_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_POS_REQ_CMD_DONE` writer - W1C"]
        pub type INI_POS_REQ_CMD_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OOSYNC` writer - Tracking module out-of sync. W1C"]
        pub type OOSYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IDLE` reader - Tracking Module in Idle status"]
        pub type IDLE_R = crate::BitReader;
        #[doc = "Field `INI_BR1_POS_REQ_CMD_DONE` writer - W1C"]
        pub type INI_BR1_POS_REQ_CMD_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_BR0_POS_REQ_CMD_DONE` writer - W1C"]
        pub type INI_BR0_POS_REQ_CMD_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_DELTA_POS_REQ_CMD_DONE` writer - W1C"]
        pub type INI_DELTA_POS_REQ_CMD_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS_TRG_VALID` writer - W1C"]
        pub type POS_TRG_VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SPEED_TRG_VALID` writer - W1C"]
        pub type SPEED_TRG_VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERR_ID` reader - Tracking ERR_ID"]
        pub type ERR_ID_R = crate::FieldReader;
        impl R {
            #[doc = "Bit 0 - Shadow ready for read. Auto cleared by setting CR\\[SHADOW_RD_REQ\\]
as 1"]
            #[inline(always)]
            pub fn shadow_rd_done(&self) -> SHADOW_RD_DONE_R {
                SHADOW_RD_DONE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 5 - Tracking Module in Idle status"]
            #[inline(always)]
            pub fn idle(&self) -> IDLE_R {
                IDLE_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bits 28:31 - Tracking ERR_ID"]
            #[inline(always)]
            pub fn err_id(&self) -> ERR_ID_R {
                ERR_ID_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 1 - W1C"]
            #[inline(always)]
            #[must_use]
            pub fn ini_coefs_cmd_done(&mut self) -> INI_COEFS_CMD_DONE_W<STA_SPEC> {
                INI_COEFS_CMD_DONE_W::new(self, 1)
            }
            #[doc = "Bit 2 - W1C"]
            #[inline(always)]
            #[must_use]
            pub fn ini_pos_req_cmd_done(&mut self) -> INI_POS_REQ_CMD_DONE_W<STA_SPEC> {
                INI_POS_REQ_CMD_DONE_W::new(self, 2)
            }
            #[doc = "Bit 4 - Tracking module out-of sync. W1C"]
            #[inline(always)]
            #[must_use]
            pub fn oosync(&mut self) -> OOSYNC_W<STA_SPEC> {
                OOSYNC_W::new(self, 4)
            }
            #[doc = "Bit 6 - W1C"]
            #[inline(always)]
            #[must_use]
            pub fn ini_br1_pos_req_cmd_done(&mut self) -> INI_BR1_POS_REQ_CMD_DONE_W<STA_SPEC> {
                INI_BR1_POS_REQ_CMD_DONE_W::new(self, 6)
            }
            #[doc = "Bit 7 - W1C"]
            #[inline(always)]
            #[must_use]
            pub fn ini_br0_pos_req_cmd_done(&mut self) -> INI_BR0_POS_REQ_CMD_DONE_W<STA_SPEC> {
                INI_BR0_POS_REQ_CMD_DONE_W::new(self, 7)
            }
            #[doc = "Bit 8 - W1C"]
            #[inline(always)]
            #[must_use]
            pub fn ini_delta_pos_req_cmd_done(&mut self) -> INI_DELTA_POS_REQ_CMD_DONE_W<STA_SPEC> {
                INI_DELTA_POS_REQ_CMD_DONE_W::new(self, 8)
            }
            #[doc = "Bit 9 - W1C"]
            #[inline(always)]
            #[must_use]
            pub fn pos_trg_valid(&mut self) -> POS_TRG_VALID_W<STA_SPEC> {
                POS_TRG_VALID_W::new(self, 9)
            }
            #[doc = "Bit 10 - W1C"]
            #[inline(always)]
            #[must_use]
            pub fn speed_trg_valid(&mut self) -> SPEED_TRG_VALID_W<STA_SPEC> {
                SPEED_TRG_VALID_W::new(self, 10)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STA_SPEC;
        impl crate::RegisterSpec for STA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sta::R`](R) reader structure"]
        impl crate::Readable for STA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sta::W`](W) writer structure"]
        impl crate::Writable for STA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets STA to value 0x20"]
        impl crate::Resettable for STA_SPEC {
            const RESET_VALUE: u32 = 0x20;
        }
    }
    #[doc = "INT_EN (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_en`]
module"]
    pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
    #[doc = "Interrupt Enable Register"]
    pub mod int_en {
        #[doc = "Register `INT_EN` reader"]
        pub type R = crate::R<INT_EN_SPEC>;
        #[doc = "Register `INT_EN` writer"]
        pub type W = crate::W<INT_EN_SPEC>;
        #[doc = "Field `SHADOW_RD_DONE_IE` reader - Interrupt Enable for SHADOW_RD_DONE"]
        pub type SHADOW_RD_DONE_IE_R = crate::BitReader;
        #[doc = "Field `SHADOW_RD_DONE_IE` writer - Interrupt Enable for SHADOW_RD_DONE"]
        pub type SHADOW_RD_DONE_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_COEFS_CMD_DONE_IE` reader - Interrupt Enable for INI_COEFS_CMD_DONE"]
        pub type INI_COEFS_CMD_DONE_IE_R = crate::BitReader;
        #[doc = "Field `INI_COEFS_CMD_DONE_IE` writer - Interrupt Enable for INI_COEFS_CMD_DONE"]
        pub type INI_COEFS_CMD_DONE_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_POS_REQ_CMD_DONE_IE` reader - Interrupt Enable for INI_POS_REQ_CMD_DONE"]
        pub type INI_POS_REQ_CMD_DONE_IE_R = crate::BitReader;
        #[doc = "Field `INI_POS_REQ_CMD_DONE_IE` writer - Interrupt Enable for INI_POS_REQ_CMD_DONE"]
        pub type INI_POS_REQ_CMD_DONE_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OOSYNC_IE` reader - Interrupt Enable for OOSYNC"]
        pub type OOSYNC_IE_R = crate::BitReader;
        #[doc = "Field `OOSYNC_IE` writer - Interrupt Enable for OOSYNC"]
        pub type OOSYNC_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_BR1_POS_REQ_CMD_DONE_IE` reader - Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE"]
        pub type INI_BR1_POS_REQ_CMD_DONE_IE_R = crate::BitReader;
        #[doc = "Field `INI_BR1_POS_REQ_CMD_DONE_IE` writer - Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE"]
        pub type INI_BR1_POS_REQ_CMD_DONE_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_BR0_POS_REQ_CMD_DONE_IE` reader - Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE"]
        pub type INI_BR0_POS_REQ_CMD_DONE_IE_R = crate::BitReader;
        #[doc = "Field `INI_BR0_POS_REQ_CMD_DONE_IE` writer - Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE"]
        pub type INI_BR0_POS_REQ_CMD_DONE_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INI_DELTA_POS_REQ_CMD_DONE_IE` reader - Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE"]
        pub type INI_DELTA_POS_REQ_CMD_DONE_IE_R = crate::BitReader;
        #[doc = "Field `INI_DELTA_POS_REQ_CMD_DONE_IE` writer - Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE"]
        pub type INI_DELTA_POS_REQ_CMD_DONE_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POS_TRG_VLD_IE` reader - Interrupt Enable for POS_TRG_VALID"]
        pub type POS_TRG_VLD_IE_R = crate::BitReader;
        #[doc = "Field `POS_TRG_VLD_IE` writer - Interrupt Enable for POS_TRG_VALID"]
        pub type POS_TRG_VLD_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SPEED_TRG_VLD_IE` reader - Interrupt Enable for SPEED_TRG_VALID"]
        pub type SPEED_TRG_VLD_IE_R = crate::BitReader;
        #[doc = "Field `SPEED_TRG_VLD_IE` writer - Interrupt Enable for SPEED_TRG_VALID"]
        pub type SPEED_TRG_VLD_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Interrupt Enable for SHADOW_RD_DONE"]
            #[inline(always)]
            pub fn shadow_rd_done_ie(&self) -> SHADOW_RD_DONE_IE_R {
                SHADOW_RD_DONE_IE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Interrupt Enable for INI_COEFS_CMD_DONE"]
            #[inline(always)]
            pub fn ini_coefs_cmd_done_ie(&self) -> INI_COEFS_CMD_DONE_IE_R {
                INI_COEFS_CMD_DONE_IE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Interrupt Enable for INI_POS_REQ_CMD_DONE"]
            #[inline(always)]
            pub fn ini_pos_req_cmd_done_ie(&self) -> INI_POS_REQ_CMD_DONE_IE_R {
                INI_POS_REQ_CMD_DONE_IE_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 4 - Interrupt Enable for OOSYNC"]
            #[inline(always)]
            pub fn oosync_ie(&self) -> OOSYNC_IE_R {
                OOSYNC_IE_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 6 - Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE"]
            #[inline(always)]
            pub fn ini_br1_pos_req_cmd_done_ie(&self) -> INI_BR1_POS_REQ_CMD_DONE_IE_R {
                INI_BR1_POS_REQ_CMD_DONE_IE_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE"]
            #[inline(always)]
            pub fn ini_br0_pos_req_cmd_done_ie(&self) -> INI_BR0_POS_REQ_CMD_DONE_IE_R {
                INI_BR0_POS_REQ_CMD_DONE_IE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE"]
            #[inline(always)]
            pub fn ini_delta_pos_req_cmd_done_ie(&self) -> INI_DELTA_POS_REQ_CMD_DONE_IE_R {
                INI_DELTA_POS_REQ_CMD_DONE_IE_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - Interrupt Enable for POS_TRG_VALID"]
            #[inline(always)]
            pub fn pos_trg_vld_ie(&self) -> POS_TRG_VLD_IE_R {
                POS_TRG_VLD_IE_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - Interrupt Enable for SPEED_TRG_VALID"]
            #[inline(always)]
            pub fn speed_trg_vld_ie(&self) -> SPEED_TRG_VLD_IE_R {
                SPEED_TRG_VLD_IE_R::new(((self.bits >> 10) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Interrupt Enable for SHADOW_RD_DONE"]
            #[inline(always)]
            #[must_use]
            pub fn shadow_rd_done_ie(&mut self) -> SHADOW_RD_DONE_IE_W<INT_EN_SPEC> {
                SHADOW_RD_DONE_IE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Interrupt Enable for INI_COEFS_CMD_DONE"]
            #[inline(always)]
            #[must_use]
            pub fn ini_coefs_cmd_done_ie(&mut self) -> INI_COEFS_CMD_DONE_IE_W<INT_EN_SPEC> {
                INI_COEFS_CMD_DONE_IE_W::new(self, 1)
            }
            #[doc = "Bit 2 - Interrupt Enable for INI_POS_REQ_CMD_DONE"]
            #[inline(always)]
            #[must_use]
            pub fn ini_pos_req_cmd_done_ie(&mut self) -> INI_POS_REQ_CMD_DONE_IE_W<INT_EN_SPEC> {
                INI_POS_REQ_CMD_DONE_IE_W::new(self, 2)
            }
            #[doc = "Bit 4 - Interrupt Enable for OOSYNC"]
            #[inline(always)]
            #[must_use]
            pub fn oosync_ie(&mut self) -> OOSYNC_IE_W<INT_EN_SPEC> {
                OOSYNC_IE_W::new(self, 4)
            }
            #[doc = "Bit 6 - Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE"]
            #[inline(always)]
            #[must_use]
            pub fn ini_br1_pos_req_cmd_done_ie(
                &mut self,
            ) -> INI_BR1_POS_REQ_CMD_DONE_IE_W<INT_EN_SPEC> {
                INI_BR1_POS_REQ_CMD_DONE_IE_W::new(self, 6)
            }
            #[doc = "Bit 7 - Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE"]
            #[inline(always)]
            #[must_use]
            pub fn ini_br0_pos_req_cmd_done_ie(
                &mut self,
            ) -> INI_BR0_POS_REQ_CMD_DONE_IE_W<INT_EN_SPEC> {
                INI_BR0_POS_REQ_CMD_DONE_IE_W::new(self, 7)
            }
            #[doc = "Bit 8 - Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE"]
            #[inline(always)]
            #[must_use]
            pub fn ini_delta_pos_req_cmd_done_ie(
                &mut self,
            ) -> INI_DELTA_POS_REQ_CMD_DONE_IE_W<INT_EN_SPEC> {
                INI_DELTA_POS_REQ_CMD_DONE_IE_W::new(self, 8)
            }
            #[doc = "Bit 9 - Interrupt Enable for POS_TRG_VALID"]
            #[inline(always)]
            #[must_use]
            pub fn pos_trg_vld_ie(&mut self) -> POS_TRG_VLD_IE_W<INT_EN_SPEC> {
                POS_TRG_VLD_IE_W::new(self, 9)
            }
            #[doc = "Bit 10 - Interrupt Enable for SPEED_TRG_VALID"]
            #[inline(always)]
            #[must_use]
            pub fn speed_trg_vld_ie(&mut self) -> SPEED_TRG_VLD_IE_W<INT_EN_SPEC> {
                SPEED_TRG_VLD_IE_W::new(self, 10)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_EN_SPEC;
        impl crate::RegisterSpec for INT_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_en::R`](R) reader structure"]
        impl crate::Readable for INT_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_en::W`](W) writer structure"]
        impl crate::Writable for INT_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INT_EN to value 0"]
        impl crate::Resettable for INT_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SYSCLK_FREQ (rw) register accessor: System Clock Frequency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysclk_freq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysclk_freq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysclk_freq`]
module"]
    pub type SYSCLK_FREQ = crate::Reg<sysclk_freq::SYSCLK_FREQ_SPEC>;
    #[doc = "System Clock Frequency Register"]
    pub mod sysclk_freq {
        #[doc = "Register `SYSCLK_FREQ` reader"]
        pub type R = crate::R<SYSCLK_FREQ_SPEC>;
        #[doc = "Register `SYSCLK_FREQ` writer"]
        pub type W = crate::W<SYSCLK_FREQ_SPEC>;
        #[doc = "Field `VAL` reader - system clock frequency, ufix&lt;32, 0>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - system clock frequency, ufix&lt;32, 0>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - system clock frequency, ufix&lt;32, 0>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - system clock frequency, ufix&lt;32, 0>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<SYSCLK_FREQ_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "System Clock Frequency Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysclk_freq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysclk_freq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SYSCLK_FREQ_SPEC;
        impl crate::RegisterSpec for SYSCLK_FREQ_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sysclk_freq::R`](R) reader structure"]
        impl crate::Readable for SYSCLK_FREQ_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sysclk_freq::W`](W) writer structure"]
        impl crate::Writable for SYSCLK_FREQ_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SYSCLK_FREQ to value 0"]
        impl crate::Resettable for SYSCLK_FREQ_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SYSCLK_PERIOD (rw) register accessor: System Clock Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysclk_period::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysclk_period::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysclk_period`]
module"]
    pub type SYSCLK_PERIOD = crate::Reg<sysclk_period::SYSCLK_PERIOD_SPEC>;
    #[doc = "System Clock Period Register"]
    pub mod sysclk_period {
        #[doc = "Register `SYSCLK_PERIOD` reader"]
        pub type R = crate::R<SYSCLK_PERIOD_SPEC>;
        #[doc = "Register `SYSCLK_PERIOD` writer"]
        pub type W = crate::W<SYSCLK_PERIOD_SPEC>;
        #[doc = "Field `VAL` reader - round( the value of clock period * (2^24)*(2^20) ), ufix&lt;32, 0>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - round( the value of clock period * (2^24)*(2^20) ), ufix&lt;32, 0>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - round( the value of clock period * (2^24)*(2^20) ), ufix&lt;32, 0>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - round( the value of clock period * (2^24)*(2^20) ), ufix&lt;32, 0>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<SYSCLK_PERIOD_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "System Clock Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysclk_period::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysclk_period::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SYSCLK_PERIOD_SPEC;
        impl crate::RegisterSpec for SYSCLK_PERIOD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sysclk_period::R`](R) reader structure"]
        impl crate::Readable for SYSCLK_PERIOD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sysclk_period::W`](W) writer structure"]
        impl crate::Writable for SYSCLK_PERIOD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SYSCLK_PERIOD to value 0"]
        impl crate::Resettable for SYSCLK_PERIOD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "OOSYNC_THETA_THR (rw) register accessor: Position Out-Of-Sync Threshold Regster\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oosync_theta_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oosync_theta_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@oosync_theta_thr`]
module"]
    pub type OOSYNC_THETA_THR = crate::Reg<oosync_theta_thr::OOSYNC_THETA_THR_SPEC>;
    #[doc = "Position Out-Of-Sync Threshold Regster"]
    pub mod oosync_theta_thr {
        #[doc = "Register `OOSYNC_THETA_THR` reader"]
        pub type R = crate::R<OOSYNC_THETA_THR_SPEC>;
        #[doc = "Register `OOSYNC_THETA_THR` writer"]
        pub type W = crate::W<OOSYNC_THETA_THR_SPEC>;
        #[doc = "Field `VAL` reader - the threshold of theta difference between actual and prediction for out-of-sync determination，ufix&lt;32, 32>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the threshold of theta difference between actual and prediction for out-of-sync determination，ufix&lt;32, 32>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the threshold of theta difference between actual and prediction for out-of-sync determination，ufix&lt;32, 32>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the threshold of theta difference between actual and prediction for out-of-sync determination，ufix&lt;32, 32>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<OOSYNC_THETA_THR_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Position Out-Of-Sync Threshold Regster\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`oosync_theta_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`oosync_theta_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct OOSYNC_THETA_THR_SPEC;
        impl crate::RegisterSpec for OOSYNC_THETA_THR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`oosync_theta_thr::R`](R) reader structure"]
        impl crate::Readable for OOSYNC_THETA_THR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`oosync_theta_thr::W`](W) writer structure"]
        impl crate::Writable for OOSYNC_THETA_THR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets OOSYNC_THETA_THR to value 0"]
        impl crate::Resettable for OOSYNC_THETA_THR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DiscreteCfg0 (rw) register accessor: Discrete Mode Configuration 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`discrete_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`discrete_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@discrete_cfg0`]
module"]
    pub type DISCRETE_CFG0 = crate::Reg<discrete_cfg0::DISCRETE_CFG0_SPEC>;
    #[doc = "Discrete Mode Configuration 0 Register"]
    pub mod discrete_cfg0 {
        #[doc = "Register `DiscreteCfg0` reader"]
        pub type R = crate::R<DISCRETE_CFG0_SPEC>;
        #[doc = "Register `DiscreteCfg0` writer"]
        pub type W = crate::W<DISCRETE_CFG0_SPEC>;
        #[doc = "Field `POSMAX` reader - Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix&lt;32, 0>"]
        pub type POSMAX_R = crate::FieldReader<u32>;
        #[doc = "Field `POSMAX` writer - Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix&lt;32, 0>"]
        pub type POSMAX_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        impl R {
            #[doc = "Bits 0:19 - Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix&lt;32, 0>"]
            #[inline(always)]
            pub fn posmax(&self) -> POSMAX_R {
                POSMAX_R::new(self.bits & 0x000f_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix&lt;32, 0>"]
            #[inline(always)]
            #[must_use]
            pub fn posmax(&mut self) -> POSMAX_W<DISCRETE_CFG0_SPEC> {
                POSMAX_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Discrete Mode Configuration 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`discrete_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`discrete_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DISCRETE_CFG0_SPEC;
        impl crate::RegisterSpec for DISCRETE_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`discrete_cfg0::R`](R) reader structure"]
        impl crate::Readable for DISCRETE_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`discrete_cfg0::W`](W) writer structure"]
        impl crate::Writable for DISCRETE_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DiscreteCfg0 to value 0"]
        impl crate::Resettable for DISCRETE_CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DiscreteCfg1 (rw) register accessor: Discrete Mode Configuration 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`discrete_cfg1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`discrete_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@discrete_cfg1`]
module"]
    pub type DISCRETE_CFG1 = crate::Reg<discrete_cfg1::DISCRETE_CFG1_SPEC>;
    #[doc = "Discrete Mode Configuration 1 Register"]
    pub mod discrete_cfg1 {
        #[doc = "Register `DiscreteCfg1` reader"]
        pub type R = crate::R<DISCRETE_CFG1_SPEC>;
        #[doc = "Register `DiscreteCfg1` writer"]
        pub type W = crate::W<DISCRETE_CFG1_SPEC>;
        #[doc = "Field `INV_POSMAX` reader - discrete mode: ufix&lt;32, 0> of 1/(Number Of Lines) continuous mode: the max delta for tracking from the last received position, ufix&lt;32, 32>"]
        pub type INV_POSMAX_R = crate::FieldReader<u32>;
        #[doc = "Field `INV_POSMAX` writer - discrete mode: ufix&lt;32, 0> of 1/(Number Of Lines) continuous mode: the max delta for tracking from the last received position, ufix&lt;32, 32>"]
        pub type INV_POSMAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - discrete mode: ufix&lt;32, 0> of 1/(Number Of Lines) continuous mode: the max delta for tracking from the last received position, ufix&lt;32, 32>"]
            #[inline(always)]
            pub fn inv_posmax(&self) -> INV_POSMAX_R {
                INV_POSMAX_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - discrete mode: ufix&lt;32, 0> of 1/(Number Of Lines) continuous mode: the max delta for tracking from the last received position, ufix&lt;32, 32>"]
            #[inline(always)]
            #[must_use]
            pub fn inv_posmax(&mut self) -> INV_POSMAX_W<DISCRETE_CFG1_SPEC> {
                INV_POSMAX_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Discrete Mode Configuration 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`discrete_cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`discrete_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DISCRETE_CFG1_SPEC;
        impl crate::RegisterSpec for DISCRETE_CFG1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`discrete_cfg1::R`](R) reader structure"]
        impl crate::Readable for DISCRETE_CFG1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`discrete_cfg1::W`](W) writer structure"]
        impl crate::Writable for DISCRETE_CFG1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DiscreteCfg1 to value 0"]
        impl crate::Resettable for DISCRETE_CFG1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ContCfg0 (rw) register accessor: Continuous Mode Configuration 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cont_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cont_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cont_cfg0`]
module"]
    pub type CONT_CFG0 = crate::Reg<cont_cfg0::CONT_CFG0_SPEC>;
    #[doc = "Continuous Mode Configuration 0 Register"]
    pub mod cont_cfg0 {
        #[doc = "Register `ContCfg0` reader"]
        pub type R = crate::R<CONT_CFG0_SPEC>;
        #[doc = "Register `ContCfg0` writer"]
        pub type W = crate::W<CONT_CFG0_SPEC>;
        #[doc = "Field `HALF_CIRC_THETA` reader - the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix&lt;32, 32>"]
        pub type HALF_CIRC_THETA_R = crate::FieldReader<u32>;
        #[doc = "Field `HALF_CIRC_THETA` writer - the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix&lt;32, 32>"]
        pub type HALF_CIRC_THETA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix&lt;32, 32>"]
            #[inline(always)]
            pub fn half_circ_theta(&self) -> HALF_CIRC_THETA_R {
                HALF_CIRC_THETA_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix&lt;32, 32>"]
            #[inline(always)]
            #[must_use]
            pub fn half_circ_theta(&mut self) -> HALF_CIRC_THETA_W<CONT_CFG0_SPEC> {
                HALF_CIRC_THETA_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Continuous Mode Configuration 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cont_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cont_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CONT_CFG0_SPEC;
        impl crate::RegisterSpec for CONT_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cont_cfg0::R`](R) reader structure"]
        impl crate::Readable for CONT_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cont_cfg0::W`](W) writer structure"]
        impl crate::Writable for CONT_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ContCfg0 to value 0"]
        impl crate::Resettable for CONT_CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_POS_TIME (rw) register accessor: The destined timestamp register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_pos_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_pos_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_pos_time`]
module"]
    pub type INI_POS_TIME = crate::Reg<ini_pos_time::INI_POS_TIME_SPEC>;
    #[doc = "The destined timestamp register for position initialization"]
    pub mod ini_pos_time {
        #[doc = "Register `INI_POS_TIME` reader"]
        pub type R = crate::R<INI_POS_TIME_SPEC>;
        #[doc = "Register `INI_POS_TIME` writer"]
        pub type W = crate::W<INI_POS_TIME_SPEC>;
        #[doc = "Field `VAL` reader - indicate the time to change the values. 0: instant change"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - indicate the time to change the values. 0: instant change"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_POS_TIME_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined timestamp register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_pos_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_pos_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_POS_TIME_SPEC;
        impl crate::RegisterSpec for INI_POS_TIME_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_pos_time::R`](R) reader structure"]
        impl crate::Readable for INI_POS_TIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_pos_time::W`](W) writer structure"]
        impl crate::Writable for INI_POS_TIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_POS_TIME to value 0"]
        impl crate::Resettable for INI_POS_TIME_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_POS (rw) register accessor: The destined position register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_pos`]
module"]
    pub type INI_POS = crate::Reg<ini_pos::INI_POS_SPEC>;
    #[doc = "The destined position register for position initialization"]
    pub mod ini_pos {
        #[doc = "Register `INI_POS` reader"]
        pub type R = crate::R<INI_POS_SPEC>;
        #[doc = "Register `INI_POS` writer"]
        pub type W = crate::W<INI_POS_SPEC>;
        #[doc = "Field `VAL` reader - the value； continuous mode: ufix&lt;32, 32>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value； continuous mode: ufix&lt;32, 32>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value； continuous mode: ufix&lt;32, 32>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value； continuous mode: ufix&lt;32, 32>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_POS_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined position register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_POS_SPEC;
        impl crate::RegisterSpec for INI_POS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_pos::R`](R) reader structure"]
        impl crate::Readable for INI_POS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_pos::W`](W) writer structure"]
        impl crate::Writable for INI_POS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_POS to value 0"]
        impl crate::Resettable for INI_POS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_REV (rw) register accessor: The destined revolution register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_rev`]
module"]
    pub type INI_REV = crate::Reg<ini_rev::INI_REV_SPEC>;
    #[doc = "The destined revolution register for position initialization"]
    pub mod ini_rev {
        #[doc = "Register `INI_REV` reader"]
        pub type R = crate::R<INI_REV_SPEC>;
        #[doc = "Register `INI_REV` writer"]
        pub type W = crate::W<INI_REV_SPEC>;
        #[doc = "Field `VAL` reader - the value； continuous mode: ufix&lt;32, 0>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value； continuous mode: ufix&lt;32, 0>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value； continuous mode: ufix&lt;32, 0>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value； continuous mode: ufix&lt;32, 0>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_REV_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined revolution register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_REV_SPEC;
        impl crate::RegisterSpec for INI_REV_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_rev::R`](R) reader structure"]
        impl crate::Readable for INI_REV_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_rev::W`](W) writer structure"]
        impl crate::Writable for INI_REV_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_REV to value 0"]
        impl crate::Resettable for INI_REV_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_SPEED (rw) register accessor: The destined speed register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_speed`]
module"]
    pub type INI_SPEED = crate::Reg<ini_speed::INI_SPEED_SPEC>;
    #[doc = "The destined speed register for position initialization"]
    pub mod ini_speed {
        #[doc = "Register `INI_SPEED` reader"]
        pub type R = crate::R<INI_SPEED_SPEC>;
        #[doc = "Register `INI_SPEED` writer"]
        pub type W = crate::W<INI_SPEED_SPEC>;
        #[doc = "Field `VAL` reader - the value; continuous mode: fix&lt;32, 19>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value; continuous mode: fix&lt;32, 19>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value; continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value; continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_SPEED_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined speed register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_SPEED_SPEC;
        impl crate::RegisterSpec for INI_SPEED_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_speed::R`](R) reader structure"]
        impl crate::Readable for INI_SPEED_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_speed::W`](W) writer structure"]
        impl crate::Writable for INI_SPEED_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_SPEED to value 0"]
        impl crate::Resettable for INI_SPEED_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_ACCEL (rw) register accessor: The destined accelerator register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_accel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_accel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_accel`]
module"]
    pub type INI_ACCEL = crate::Reg<ini_accel::INI_ACCEL_SPEC>;
    #[doc = "The destined accelerator register for position initialization"]
    pub mod ini_accel {
        #[doc = "Register `INI_ACCEL` reader"]
        pub type R = crate::R<INI_ACCEL_SPEC>;
        #[doc = "Register `INI_ACCEL` writer"]
        pub type W = crate::W<INI_ACCEL_SPEC>;
        #[doc = "Field `VAL` reader - the value continuous mode: fix&lt;32, 19>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value continuous mode: fix&lt;32, 19>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_ACCEL_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined accelerator register for position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_accel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_accel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_ACCEL_SPEC;
        impl crate::RegisterSpec for INI_ACCEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_accel::R`](R) reader structure"]
        impl crate::Readable for INI_ACCEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_accel::W`](W) writer structure"]
        impl crate::Writable for INI_ACCEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_ACCEL to value 0"]
        impl crate::Resettable for INI_ACCEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_COEF_TIME (rw) register accessor: The destined timestamp register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_coef_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_coef_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_coef_time`]
module"]
    pub type INI_COEF_TIME = crate::Reg<ini_coef_time::INI_COEF_TIME_SPEC>;
    #[doc = "The destined timestamp register for coefficients initialization"]
    pub mod ini_coef_time {
        #[doc = "Register `INI_COEF_TIME` reader"]
        pub type R = crate::R<INI_COEF_TIME_SPEC>;
        #[doc = "Register `INI_COEF_TIME` writer"]
        pub type W = crate::W<INI_COEF_TIME_SPEC>;
        #[doc = "Field `VAL` reader - indicate the time to change the values. 0: instant change"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - indicate the time to change the values. 0: instant change"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_COEF_TIME_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined timestamp register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_coef_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_coef_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_COEF_TIME_SPEC;
        impl crate::RegisterSpec for INI_COEF_TIME_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_coef_time::R`](R) reader structure"]
        impl crate::Readable for INI_COEF_TIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_coef_time::W`](W) writer structure"]
        impl crate::Writable for INI_COEF_TIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_COEF_TIME to value 0"]
        impl crate::Resettable for INI_COEF_TIME_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_PCOEF (rw) register accessor: The destined coefficient P register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_pcoef::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_pcoef::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_pcoef`]
module"]
    pub type INI_PCOEF = crate::Reg<ini_pcoef::INI_PCOEF_SPEC>;
    #[doc = "The destined coefficient P register for coefficients initialization"]
    pub mod ini_pcoef {
        #[doc = "Register `INI_PCOEF` reader"]
        pub type R = crate::R<INI_PCOEF_SPEC>;
        #[doc = "Register `INI_PCOEF` writer"]
        pub type W = crate::W<INI_PCOEF_SPEC>;
        #[doc = "Field `VAL` reader - the value, fix&lt;32, 15>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value, fix&lt;32, 15>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value, fix&lt;32, 15>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value, fix&lt;32, 15>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_PCOEF_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined coefficient P register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_pcoef::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_pcoef::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_PCOEF_SPEC;
        impl crate::RegisterSpec for INI_PCOEF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_pcoef::R`](R) reader structure"]
        impl crate::Readable for INI_PCOEF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_pcoef::W`](W) writer structure"]
        impl crate::Writable for INI_PCOEF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_PCOEF to value 0"]
        impl crate::Resettable for INI_PCOEF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_ICOEF (rw) register accessor: The destined coefficient I register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_icoef::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_icoef::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_icoef`]
module"]
    pub type INI_ICOEF = crate::Reg<ini_icoef::INI_ICOEF_SPEC>;
    #[doc = "The destined coefficient I register for coefficients initialization"]
    pub mod ini_icoef {
        #[doc = "Register `INI_ICOEF` reader"]
        pub type R = crate::R<INI_ICOEF_SPEC>;
        #[doc = "Register `INI_ICOEF` writer"]
        pub type W = crate::W<INI_ICOEF_SPEC>;
        #[doc = "Field `VAL` reader - the value, fix&lt;32, 21>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value, fix&lt;32, 21>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value, fix&lt;32, 21>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value, fix&lt;32, 21>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_ICOEF_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined coefficient I register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_icoef::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_icoef::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_ICOEF_SPEC;
        impl crate::RegisterSpec for INI_ICOEF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_icoef::R`](R) reader structure"]
        impl crate::Readable for INI_ICOEF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_icoef::W`](W) writer structure"]
        impl crate::Writable for INI_ICOEF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_ICOEF to value 0"]
        impl crate::Resettable for INI_ICOEF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_ACOEF (rw) register accessor: The destined coefficient A register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_acoef::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_acoef::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_acoef`]
module"]
    pub type INI_ACOEF = crate::Reg<ini_acoef::INI_ACOEF_SPEC>;
    #[doc = "The destined coefficient A register for coefficients initialization"]
    pub mod ini_acoef {
        #[doc = "Register `INI_ACOEF` reader"]
        pub type R = crate::R<INI_ACOEF_SPEC>;
        #[doc = "Register `INI_ACOEF` writer"]
        pub type W = crate::W<INI_ACOEF_SPEC>;
        #[doc = "Field `VAL` reader - the value, fix&lt;32, 19>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value, fix&lt;32, 19>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value, fix&lt;32, 19>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value, fix&lt;32, 19>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_ACOEF_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined coefficient A register for coefficients initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_acoef::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_acoef::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_ACOEF_SPEC;
        impl crate::RegisterSpec for INI_ACOEF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_acoef::R`](R) reader structure"]
        impl crate::Readable for INI_ACOEF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_acoef::W`](W) writer structure"]
        impl crate::Writable for INI_ACOEF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_ACOEF to value 0"]
        impl crate::Resettable for INI_ACOEF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ESTM_TIM (rw) register accessor: The timestamp register for internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_tim::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_tim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@estm_tim`]
module"]
    pub type ESTM_TIM = crate::Reg<estm_tim::ESTM_TIM_SPEC>;
    #[doc = "The timestamp register for internal estimation"]
    pub mod estm_tim {
        #[doc = "Register `ESTM_TIM` reader"]
        pub type R = crate::R<ESTM_TIM_SPEC>;
        #[doc = "Register `ESTM_TIM` writer"]
        pub type W = crate::W<ESTM_TIM_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The timestamp register for internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_tim::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_tim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ESTM_TIM_SPEC;
        impl crate::RegisterSpec for ESTM_TIM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`estm_tim::R`](R) reader structure"]
        impl crate::Readable for ESTM_TIM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`estm_tim::W`](W) writer structure"]
        impl crate::Writable for ESTM_TIM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ESTM_TIM to value 0"]
        impl crate::Resettable for ESTM_TIM_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ESTM_POS (rw) register accessor: The position register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@estm_pos`]
module"]
    pub type ESTM_POS = crate::Reg<estm_pos::ESTM_POS_SPEC>;
    #[doc = "The position register for the internal estimation"]
    pub mod estm_pos {
        #[doc = "Register `ESTM_POS` reader"]
        pub type R = crate::R<ESTM_POS_SPEC>;
        #[doc = "Register `ESTM_POS` writer"]
        pub type W = crate::W<ESTM_POS_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The position register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ESTM_POS_SPEC;
        impl crate::RegisterSpec for ESTM_POS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`estm_pos::R`](R) reader structure"]
        impl crate::Readable for ESTM_POS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`estm_pos::W`](W) writer structure"]
        impl crate::Writable for ESTM_POS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ESTM_POS to value 0"]
        impl crate::Resettable for ESTM_POS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ESTM_REV (rw) register accessor: The revolution register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@estm_rev`]
module"]
    pub type ESTM_REV = crate::Reg<estm_rev::ESTM_REV_SPEC>;
    #[doc = "The revolution register for the internal estimation"]
    pub mod estm_rev {
        #[doc = "Register `ESTM_REV` reader"]
        pub type R = crate::R<ESTM_REV_SPEC>;
        #[doc = "Register `ESTM_REV` writer"]
        pub type W = crate::W<ESTM_REV_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The revolution register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ESTM_REV_SPEC;
        impl crate::RegisterSpec for ESTM_REV_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`estm_rev::R`](R) reader structure"]
        impl crate::Readable for ESTM_REV_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`estm_rev::W`](W) writer structure"]
        impl crate::Writable for ESTM_REV_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ESTM_REV to value 0"]
        impl crate::Resettable for ESTM_REV_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ESTM_SPEED (rw) register accessor: The speed register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@estm_speed`]
module"]
    pub type ESTM_SPEED = crate::Reg<estm_speed::ESTM_SPEED_SPEC>;
    #[doc = "The speed register for the internal estimation"]
    pub mod estm_speed {
        #[doc = "Register `ESTM_SPEED` reader"]
        pub type R = crate::R<ESTM_SPEED_SPEC>;
        #[doc = "Register `ESTM_SPEED` writer"]
        pub type W = crate::W<ESTM_SPEED_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The speed register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ESTM_SPEED_SPEC;
        impl crate::RegisterSpec for ESTM_SPEED_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`estm_speed::R`](R) reader structure"]
        impl crate::Readable for ESTM_SPEED_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`estm_speed::W`](W) writer structure"]
        impl crate::Writable for ESTM_SPEED_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ESTM_SPEED to value 0"]
        impl crate::Resettable for ESTM_SPEED_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ESTM_ACCEL (rw) register accessor: The accelerator register for theinternal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_accel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_accel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@estm_accel`]
module"]
    pub type ESTM_ACCEL = crate::Reg<estm_accel::ESTM_ACCEL_SPEC>;
    #[doc = "The accelerator register for theinternal estimation"]
    pub mod estm_accel {
        #[doc = "Register `ESTM_ACCEL` reader"]
        pub type R = crate::R<ESTM_ACCEL_SPEC>;
        #[doc = "Register `ESTM_ACCEL` writer"]
        pub type W = crate::W<ESTM_ACCEL_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The accelerator register for theinternal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`estm_accel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`estm_accel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ESTM_ACCEL_SPEC;
        impl crate::RegisterSpec for ESTM_ACCEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`estm_accel::R`](R) reader structure"]
        impl crate::Readable for ESTM_ACCEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`estm_accel::W`](W) writer structure"]
        impl crate::Writable for ESTM_ACCEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ESTM_ACCEL to value 0"]
        impl crate::Resettable for ESTM_ACCEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CUR_PCOEF (rw) register accessor: The coefficient P register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cur_pcoef::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cur_pcoef::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cur_pcoef`]
module"]
    pub type CUR_PCOEF = crate::Reg<cur_pcoef::CUR_PCOEF_SPEC>;
    #[doc = "The coefficient P register for the internal estimation"]
    pub mod cur_pcoef {
        #[doc = "Register `CUR_PCOEF` reader"]
        pub type R = crate::R<CUR_PCOEF_SPEC>;
        #[doc = "Register `CUR_PCOEF` writer"]
        pub type W = crate::W<CUR_PCOEF_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The coefficient P register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cur_pcoef::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cur_pcoef::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CUR_PCOEF_SPEC;
        impl crate::RegisterSpec for CUR_PCOEF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cur_pcoef::R`](R) reader structure"]
        impl crate::Readable for CUR_PCOEF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cur_pcoef::W`](W) writer structure"]
        impl crate::Writable for CUR_PCOEF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CUR_PCOEF to value 0"]
        impl crate::Resettable for CUR_PCOEF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CUR_ICOEF (rw) register accessor: The coefficient I register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cur_icoef::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cur_icoef::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cur_icoef`]
module"]
    pub type CUR_ICOEF = crate::Reg<cur_icoef::CUR_ICOEF_SPEC>;
    #[doc = "The coefficient I register for the internal estimation"]
    pub mod cur_icoef {
        #[doc = "Register `CUR_ICOEF` reader"]
        pub type R = crate::R<CUR_ICOEF_SPEC>;
        #[doc = "Register `CUR_ICOEF` writer"]
        pub type W = crate::W<CUR_ICOEF_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The coefficient I register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cur_icoef::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cur_icoef::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CUR_ICOEF_SPEC;
        impl crate::RegisterSpec for CUR_ICOEF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cur_icoef::R`](R) reader structure"]
        impl crate::Readable for CUR_ICOEF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cur_icoef::W`](W) writer structure"]
        impl crate::Writable for CUR_ICOEF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CUR_ICOEF to value 0"]
        impl crate::Resettable for CUR_ICOEF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CUR_ACOEF (rw) register accessor: The coefficient A register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cur_acoef::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cur_acoef::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cur_acoef`]
module"]
    pub type CUR_ACOEF = crate::Reg<cur_acoef::CUR_ACOEF_SPEC>;
    #[doc = "The coefficient A register for the internal estimation"]
    pub mod cur_acoef {
        #[doc = "Register `CUR_ACOEF` reader"]
        pub type R = crate::R<CUR_ACOEF_SPEC>;
        #[doc = "Register `CUR_ACOEF` writer"]
        pub type W = crate::W<CUR_ACOEF_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The coefficient A register for the internal estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cur_acoef::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cur_acoef::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CUR_ACOEF_SPEC;
        impl crate::RegisterSpec for CUR_ACOEF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cur_acoef::R`](R) reader structure"]
        impl crate::Readable for CUR_ACOEF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cur_acoef::W`](W) writer structure"]
        impl crate::Writable for CUR_ACOEF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CUR_ACOEF to value 0"]
        impl crate::Resettable for CUR_ACOEF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_DELTA_POS_TIME (rw) register accessor: The destined timestamp register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_pos_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_pos_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_delta_pos_time`]
module"]
    pub type INI_DELTA_POS_TIME = crate::Reg<ini_delta_pos_time::INI_DELTA_POS_TIME_SPEC>;
    #[doc = "The destined timestamp register for delta position initialization"]
    pub mod ini_delta_pos_time {
        #[doc = "Register `INI_DELTA_POS_TIME` reader"]
        pub type R = crate::R<INI_DELTA_POS_TIME_SPEC>;
        #[doc = "Register `INI_DELTA_POS_TIME` writer"]
        pub type W = crate::W<INI_DELTA_POS_TIME_SPEC>;
        #[doc = "Field `VAL` reader - indicate the time to change the values. 0: instant change"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - indicate the time to change the values. 0: instant change"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_DELTA_POS_TIME_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined timestamp register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_pos_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_pos_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_DELTA_POS_TIME_SPEC;
        impl crate::RegisterSpec for INI_DELTA_POS_TIME_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_delta_pos_time::R`](R) reader structure"]
        impl crate::Readable for INI_DELTA_POS_TIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_delta_pos_time::W`](W) writer structure"]
        impl crate::Writable for INI_DELTA_POS_TIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_DELTA_POS_TIME to value 0"]
        impl crate::Resettable for INI_DELTA_POS_TIME_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_DELTA_POS (rw) register accessor: The destined delta position register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_delta_pos`]
module"]
    pub type INI_DELTA_POS = crate::Reg<ini_delta_pos::INI_DELTA_POS_SPEC>;
    #[doc = "The destined delta position register for delta position initialization"]
    pub mod ini_delta_pos {
        #[doc = "Register `INI_DELTA_POS` reader"]
        pub type R = crate::R<INI_DELTA_POS_SPEC>;
        #[doc = "Register `INI_DELTA_POS` writer"]
        pub type W = crate::W<INI_DELTA_POS_SPEC>;
        #[doc = "Field `VAL` reader - the value continuous mode: ufix &lt;32, 32>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value continuous mode: ufix &lt;32, 32>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value continuous mode: ufix &lt;32, 32>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value continuous mode: ufix &lt;32, 32>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_DELTA_POS_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined delta position register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_DELTA_POS_SPEC;
        impl crate::RegisterSpec for INI_DELTA_POS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_delta_pos::R`](R) reader structure"]
        impl crate::Readable for INI_DELTA_POS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_delta_pos::W`](W) writer structure"]
        impl crate::Writable for INI_DELTA_POS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_DELTA_POS to value 0"]
        impl crate::Resettable for INI_DELTA_POS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_DELTA_REV (rw) register accessor: The destined delta revolution register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_delta_rev`]
module"]
    pub type INI_DELTA_REV = crate::Reg<ini_delta_rev::INI_DELTA_REV_SPEC>;
    #[doc = "The destined delta revolution register for delta position initialization"]
    pub mod ini_delta_rev {
        #[doc = "Register `INI_DELTA_REV` reader"]
        pub type R = crate::R<INI_DELTA_REV_SPEC>;
        #[doc = "Register `INI_DELTA_REV` writer"]
        pub type W = crate::W<INI_DELTA_REV_SPEC>;
        #[doc = "Field `VAL` reader - the value continuous mode: fix&lt;32, 0>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value continuous mode: fix&lt;32, 0>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 0>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 0>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_DELTA_REV_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined delta revolution register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_DELTA_REV_SPEC;
        impl crate::RegisterSpec for INI_DELTA_REV_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_delta_rev::R`](R) reader structure"]
        impl crate::Readable for INI_DELTA_REV_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_delta_rev::W`](W) writer structure"]
        impl crate::Writable for INI_DELTA_REV_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_DELTA_REV to value 0"]
        impl crate::Resettable for INI_DELTA_REV_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_DELTA_SPEED (rw) register accessor: The destined delta speed register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_delta_speed`]
module"]
    pub type INI_DELTA_SPEED = crate::Reg<ini_delta_speed::INI_DELTA_SPEED_SPEC>;
    #[doc = "The destined delta speed register for delta position initialization"]
    pub mod ini_delta_speed {
        #[doc = "Register `INI_DELTA_SPEED` reader"]
        pub type R = crate::R<INI_DELTA_SPEED_SPEC>;
        #[doc = "Register `INI_DELTA_SPEED` writer"]
        pub type W = crate::W<INI_DELTA_SPEED_SPEC>;
        #[doc = "Field `VAL` reader - the value； continuous mode: fix&lt;32, 19>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value； continuous mode: fix&lt;32, 19>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value； continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value； continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_DELTA_SPEED_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined delta speed register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_DELTA_SPEED_SPEC;
        impl crate::RegisterSpec for INI_DELTA_SPEED_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_delta_speed::R`](R) reader structure"]
        impl crate::Readable for INI_DELTA_SPEED_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_delta_speed::W`](W) writer structure"]
        impl crate::Writable for INI_DELTA_SPEED_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_DELTA_SPEED to value 0"]
        impl crate::Resettable for INI_DELTA_SPEED_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INI_DELTA_ACCEL (rw) register accessor: The destined delta accelerator register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_accel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_accel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ini_delta_accel`]
module"]
    pub type INI_DELTA_ACCEL = crate::Reg<ini_delta_accel::INI_DELTA_ACCEL_SPEC>;
    #[doc = "The destined delta accelerator register for delta position initialization"]
    pub mod ini_delta_accel {
        #[doc = "Register `INI_DELTA_ACCEL` reader"]
        pub type R = crate::R<INI_DELTA_ACCEL_SPEC>;
        #[doc = "Register `INI_DELTA_ACCEL` writer"]
        pub type W = crate::W<INI_DELTA_ACCEL_SPEC>;
        #[doc = "Field `VAL` reader - the value continuous mode: fix&lt;32, 19>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - the value continuous mode: fix&lt;32, 19>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<INI_DELTA_ACCEL_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "The destined delta accelerator register for delta position initialization\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ini_delta_accel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ini_delta_accel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INI_DELTA_ACCEL_SPEC;
        impl crate::RegisterSpec for INI_DELTA_ACCEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ini_delta_accel::R`](R) reader structure"]
        impl crate::Readable for INI_DELTA_ACCEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ini_delta_accel::W`](W) writer structure"]
        impl crate::Writable for INI_DELTA_ACCEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INI_DELTA_ACCEL to value 0"]
        impl crate::Resettable for INI_DELTA_ACCEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pos_trg_cfg (rw) register accessor: Tracking Configuration pos trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_trg_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_trg_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_trg_cfg`]
module"]
    pub type POS_TRG_CFG = crate::Reg<pos_trg_cfg::POS_TRG_CFG_SPEC>;
    #[doc = "Tracking Configuration pos trigger cfg"]
    pub mod pos_trg_cfg {
        #[doc = "Register `pos_trg_cfg` reader"]
        pub type R = crate::R<POS_TRG_CFG_SPEC>;
        #[doc = "Register `pos_trg_cfg` writer"]
        pub type W = crate::W<POS_TRG_CFG_SPEC>;
        #[doc = "Field `EN` reader - 1-trigger valid; 0-Trigger not valid\""]
        pub type EN_R = crate::BitReader;
        #[doc = "Field `EN` writer - 1-trigger valid; 0-Trigger not valid\""]
        pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EDGE` reader - 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
        pub type EDGE_R = crate::BitReader;
        #[doc = "Field `EDGE` writer - 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
        pub type EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid\""]
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
            #[inline(always)]
            pub fn edge(&self) -> EDGE_R {
                EDGE_R::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid\""]
            #[inline(always)]
            #[must_use]
            pub fn en(&mut self) -> EN_W<POS_TRG_CFG_SPEC> {
                EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
            #[inline(always)]
            #[must_use]
            pub fn edge(&mut self) -> EDGE_W<POS_TRG_CFG_SPEC> {
                EDGE_W::new(self, 1)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Tracking Configuration pos trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_trg_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_trg_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POS_TRG_CFG_SPEC;
        impl crate::RegisterSpec for POS_TRG_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pos_trg_cfg::R`](R) reader structure"]
        impl crate::Readable for POS_TRG_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pos_trg_cfg::W`](W) writer structure"]
        impl crate::Writable for POS_TRG_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pos_trg_cfg to value 0"]
        impl crate::Resettable for POS_TRG_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pos_trg_pos_thr (rw) register accessor: Tracking Configuration position threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_trg_pos_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_trg_pos_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_trg_pos_thr`]
module"]
    pub type POS_TRG_POS_THR = crate::Reg<pos_trg_pos_thr::POS_TRG_POS_THR_SPEC>;
    #[doc = "Tracking Configuration position threshold"]
    pub mod pos_trg_pos_thr {
        #[doc = "Register `pos_trg_pos_thr` reader"]
        pub type R = crate::R<POS_TRG_POS_THR_SPEC>;
        #[doc = "Register `pos_trg_pos_thr` writer"]
        pub type W = crate::W<POS_TRG_POS_THR_SPEC>;
        #[doc = "Field `VAL` reader - For pos out trigger (pos). ufix&lt;32, 32>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - For pos out trigger (pos). ufix&lt;32, 32>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - For pos out trigger (pos). ufix&lt;32, 32>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - For pos out trigger (pos). ufix&lt;32, 32>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<POS_TRG_POS_THR_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Tracking Configuration position threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_trg_pos_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_trg_pos_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POS_TRG_POS_THR_SPEC;
        impl crate::RegisterSpec for POS_TRG_POS_THR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pos_trg_pos_thr::R`](R) reader structure"]
        impl crate::Readable for POS_TRG_POS_THR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pos_trg_pos_thr::W`](W) writer structure"]
        impl crate::Writable for POS_TRG_POS_THR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pos_trg_pos_thr to value 0"]
        impl crate::Resettable for POS_TRG_POS_THR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "pos_trg_rev_thr (rw) register accessor: Tracking Configuration revolution threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_trg_rev_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_trg_rev_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_trg_rev_thr`]
module"]
    pub type POS_TRG_REV_THR = crate::Reg<pos_trg_rev_thr::POS_TRG_REV_THR_SPEC>;
    #[doc = "Tracking Configuration revolution threshold"]
    pub mod pos_trg_rev_thr {
        #[doc = "Register `pos_trg_rev_thr` reader"]
        pub type R = crate::R<POS_TRG_REV_THR_SPEC>;
        #[doc = "Register `pos_trg_rev_thr` writer"]
        pub type W = crate::W<POS_TRG_REV_THR_SPEC>;
        #[doc = "Field `VAL` reader - For pos out trigger (rev) fix&lt;32, 0>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - For pos out trigger (rev) fix&lt;32, 0>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - For pos out trigger (rev) fix&lt;32, 0>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - For pos out trigger (rev) fix&lt;32, 0>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<POS_TRG_REV_THR_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Tracking Configuration revolution threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_trg_rev_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_trg_rev_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POS_TRG_REV_THR_SPEC;
        impl crate::RegisterSpec for POS_TRG_REV_THR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pos_trg_rev_thr::R`](R) reader structure"]
        impl crate::Readable for POS_TRG_REV_THR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pos_trg_rev_thr::W`](W) writer structure"]
        impl crate::Writable for POS_TRG_REV_THR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pos_trg_rev_thr to value 0"]
        impl crate::Resettable for POS_TRG_REV_THR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "speed_trg_cfg (rw) register accessor: Tracking Configuration speed trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`speed_trg_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`speed_trg_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@speed_trg_cfg`]
module"]
    pub type SPEED_TRG_CFG = crate::Reg<speed_trg_cfg::SPEED_TRG_CFG_SPEC>;
    #[doc = "Tracking Configuration speed trigger cfg"]
    pub mod speed_trg_cfg {
        #[doc = "Register `speed_trg_cfg` reader"]
        pub type R = crate::R<SPEED_TRG_CFG_SPEC>;
        #[doc = "Register `speed_trg_cfg` writer"]
        pub type W = crate::W<SPEED_TRG_CFG_SPEC>;
        #[doc = "Field `EN` reader - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
        pub type EN_R = crate::BitReader;
        #[doc = "Field `EN` writer - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
        pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EDGE` reader - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
        pub type EDGE_R = crate::BitReader;
        #[doc = "Field `EDGE` writer - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
        pub type EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COMP_TYPE` reader - 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
        pub type COMP_TYPE_R = crate::BitReader;
        #[doc = "Field `COMP_TYPE` writer - 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
        pub type COMP_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
            #[inline(always)]
            pub fn en(&self) -> EN_R {
                EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
            #[inline(always)]
            pub fn edge(&self) -> EDGE_R {
                EDGE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
            #[inline(always)]
            pub fn comp_type(&self) -> COMP_TYPE_R {
                COMP_TYPE_R::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
            #[inline(always)]
            #[must_use]
            pub fn en(&mut self) -> EN_W<SPEED_TRG_CFG_SPEC> {
                EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
            #[inline(always)]
            #[must_use]
            pub fn edge(&mut self) -> EDGE_W<SPEED_TRG_CFG_SPEC> {
                EDGE_W::new(self, 1)
            }
            #[doc = "Bit 2 - 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
            #[inline(always)]
            #[must_use]
            pub fn comp_type(&mut self) -> COMP_TYPE_W<SPEED_TRG_CFG_SPEC> {
                COMP_TYPE_W::new(self, 2)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Tracking Configuration speed trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`speed_trg_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`speed_trg_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SPEED_TRG_CFG_SPEC;
        impl crate::RegisterSpec for SPEED_TRG_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`speed_trg_cfg::R`](R) reader structure"]
        impl crate::Readable for SPEED_TRG_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`speed_trg_cfg::W`](W) writer structure"]
        impl crate::Writable for SPEED_TRG_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets speed_trg_cfg to value 0"]
        impl crate::Resettable for SPEED_TRG_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "speed_trg_thr (rw) register accessor: Tracking Configuration speed threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`speed_trg_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`speed_trg_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@speed_trg_thr`]
module"]
    pub type SPEED_TRG_THR = crate::Reg<speed_trg_thr::SPEED_TRG_THR_SPEC>;
    #[doc = "Tracking Configuration speed threshold"]
    pub mod speed_trg_thr {
        #[doc = "Register `speed_trg_thr` reader"]
        pub type R = crate::R<SPEED_TRG_THR_SPEC>;
        #[doc = "Register `speed_trg_thr` writer"]
        pub type W = crate::W<SPEED_TRG_THR_SPEC>;
        #[doc = "Field `VAL` reader - For speed trigger. continuous mode: fix&lt;32, 19>"]
        pub type VAL_R = crate::FieldReader<u32>;
        #[doc = "Field `VAL` writer - For speed trigger. continuous mode: fix&lt;32, 19>"]
        pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - For speed trigger. continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - For speed trigger. continuous mode: fix&lt;32, 19>"]
            #[inline(always)]
            #[must_use]
            pub fn val(&mut self) -> VAL_W<SPEED_TRG_THR_SPEC> {
                VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Tracking Configuration speed threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`speed_trg_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`speed_trg_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SPEED_TRG_THR_SPEC;
        impl crate::RegisterSpec for SPEED_TRG_THR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`speed_trg_thr::R`](R) reader structure"]
        impl crate::Readable for SPEED_TRG_THR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`speed_trg_thr::W`](W) writer structure"]
        impl crate::Writable for SPEED_TRG_THR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets speed_trg_thr to value 0"]
        impl crate::Resettable for SPEED_TRG_THR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::coef_trg_cfg::COEF_TRG_CFG;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod coef_trg_cfg {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct COEF_TRG_CFG {
            err_thr: ERR_THR,
            p: P,
            i: I,
            a: A,
            time: TIME,
        }
        impl COEF_TRG_CFG {
            #[doc = "0x00 - Tracking Configuration coef trigger cfg&amp;index0"]
            #[inline(always)]
            pub const fn err_thr(&self) -> &ERR_THR {
                &self.err_thr
            }
            #[doc = "0x04 - Tracking Configuration coef trigger cfg&amp;index0 P"]
            #[inline(always)]
            pub const fn p(&self) -> &P {
                &self.p
            }
            #[doc = "0x08 - Tracking Configuration coef trigger cfg&amp;index0 I"]
            #[inline(always)]
            pub const fn i(&self) -> &I {
                &self.i
            }
            #[doc = "0x0c - Tracking Configuration coef trigger cfg&amp;index0 A"]
            #[inline(always)]
            pub const fn a(&self) -> &A {
                &self.a
            }
            #[doc = "0x10 - Tracking Configuration coef trigger cfg&amp;index0 time"]
            #[inline(always)]
            pub const fn time(&self) -> &TIME {
                &self.time
            }
        }
        #[doc = "err_thr (rw) register accessor: Tracking Configuration coef trigger cfg&amp;index0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_thr`]
module"]
        pub type ERR_THR = crate::Reg<err_thr::ERR_THR_SPEC>;
        #[doc = "Tracking Configuration coef trigger cfg&amp;index0"]
        pub mod err_thr {
            #[doc = "Register `err_thr` reader"]
            pub type R = crate::R<ERR_THR_SPEC>;
            #[doc = "Register `err_thr` writer"]
            pub type W = crate::W<ERR_THR_SPEC>;
            #[doc = "Field `VAL` reader - ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) Note: ErrThr0>ErrThr1>ErrThr2 ufix&lt;31, 28>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) Note: ErrThr0>ErrThr1>ErrThr2 ufix&lt;31, 28>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) Note: ErrThr0>ErrThr1>ErrThr2 ufix&lt;31, 28>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) Note: ErrThr0>ErrThr1>ErrThr2 ufix&lt;31, 28>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<ERR_THR_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Tracking Configuration coef trigger cfg&amp;index0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct ERR_THR_SPEC;
            impl crate::RegisterSpec for ERR_THR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`err_thr::R`](R) reader structure"]
            impl crate::Readable for ERR_THR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`err_thr::W`](W) writer structure"]
            impl crate::Writable for ERR_THR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets err_thr to value 0"]
            impl crate::Resettable for ERR_THR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "P (rw) register accessor: Tracking Configuration coef trigger cfg&amp;index0 P\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`p::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`p::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@p`]
module"]
        pub type P = crate::Reg<p::P_SPEC>;
        #[doc = "Tracking Configuration coef trigger cfg&amp;index0 P"]
        pub mod p {
            #[doc = "Register `P` reader"]
            pub type R = crate::R<P_SPEC>;
            #[doc = "Register `P` writer"]
            pub type W = crate::W<P_SPEC>;
            #[doc = "Field `VAL` reader - P0_Coef, fix&lt;32, 15>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - P0_Coef, fix&lt;32, 15>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - P0_Coef, fix&lt;32, 15>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - P0_Coef, fix&lt;32, 15>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<P_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Tracking Configuration coef trigger cfg&amp;index0 P\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`p::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`p::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct P_SPEC;
            impl crate::RegisterSpec for P_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`p::R`](R) reader structure"]
            impl crate::Readable for P_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`p::W`](W) writer structure"]
            impl crate::Writable for P_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets P to value 0"]
            impl crate::Resettable for P_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "I (rw) register accessor: Tracking Configuration coef trigger cfg&amp;index0 I\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i`]
module"]
        pub type I = crate::Reg<i::I_SPEC>;
        #[doc = "Tracking Configuration coef trigger cfg&amp;index0 I"]
        pub mod i {
            #[doc = "Register `I` reader"]
            pub type R = crate::R<I_SPEC>;
            #[doc = "Register `I` writer"]
            pub type W = crate::W<I_SPEC>;
            #[doc = "Field `VAL` reader - I0_Coef, fix&lt;32, 21>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - I0_Coef, fix&lt;32, 21>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - I0_Coef, fix&lt;32, 21>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - I0_Coef, fix&lt;32, 21>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<I_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Tracking Configuration coef trigger cfg&amp;index0 I\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct I_SPEC;
            impl crate::RegisterSpec for I_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`i::R`](R) reader structure"]
            impl crate::Readable for I_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`i::W`](W) writer structure"]
            impl crate::Writable for I_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets I to value 0"]
            impl crate::Resettable for I_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "A (rw) register accessor: Tracking Configuration coef trigger cfg&amp;index0 A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@a`]
module"]
        pub type A = crate::Reg<a::A_SPEC>;
        #[doc = "Tracking Configuration coef trigger cfg&amp;index0 A"]
        pub mod a {
            #[doc = "Register `A` reader"]
            pub type R = crate::R<A_SPEC>;
            #[doc = "Register `A` writer"]
            pub type W = crate::W<A_SPEC>;
            #[doc = "Field `VAL` reader - A0_Coef，fix&lt;32, 19>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - A0_Coef，fix&lt;32, 19>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - A0_Coef，fix&lt;32, 19>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - A0_Coef，fix&lt;32, 19>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<A_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Tracking Configuration coef trigger cfg&amp;index0 A\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`a::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`a::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct A_SPEC;
            impl crate::RegisterSpec for A_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`a::R`](R) reader structure"]
            impl crate::Readable for A_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`a::W`](W) writer structure"]
            impl crate::Writable for A_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets A to value 0"]
            impl crate::Resettable for A_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TIME (rw) register accessor: Tracking Configuration coef trigger cfg&amp;index0 time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@time`]
module"]
        pub type TIME = crate::Reg<time::TIME_SPEC>;
        #[doc = "Tracking Configuration coef trigger cfg&amp;index0 time"]
        pub mod time {
            #[doc = "Register `TIME` reader"]
            pub type R = crate::R<TIME_SPEC>;
            #[doc = "Register `TIME` writer"]
            pub type W = crate::W<TIME_SPEC>;
            #[doc = "Field `VAL` reader - CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix&lt;32,0>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix&lt;32,0>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix&lt;32,0>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix&lt;32,0>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<TIME_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Tracking Configuration coef trigger cfg&amp;index0 time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TIME_SPEC;
            impl crate::RegisterSpec for TIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`time::R`](R) reader structure"]
            impl crate::Readable for TIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`time::W`](W) writer structure"]
            impl crate::Writable for TIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TIME to value 0"]
            impl crate::Resettable for TIME_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::br::BR;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod br {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct BR {
            br_ctrl: BR_CTRL,
            br_timeoff: BR_TIMEOFF,
            br_trg_period: BR_TRG_PERIOD,
            br_trg_f_time: BR_TRG_F_TIME,
            br_st: BR_ST,
            _reserved5: [u8; 0x2c],
            br_trg_pos_cfg: BR_TRG_POS_CFG,
            br_trg_pos_thr: BR_TRG_POS_THR,
            br_trg_rev_thr: BR_TRG_REV_THR,
            br_trg_speed_cfg: BR_TRG_SPEED_CFG,
            br_trg_speed_thr: BR_TRG_SPEED_THR,
            _reserved10: [u8; 0x6c],
            br_ini_pos_time: BR_INI_POS_TIME,
            br_ini_pos: BR_INI_POS,
            br_ini_rev: BR_INI_REV,
            br_ini_speed: BR_INI_SPEED,
            br_ini_accel: BR_INI_ACCEL,
            br_ini_delta_pos_time: BR_INI_DELTA_POS_TIME,
            br_ini_delta_pos: BR_INI_DELTA_POS,
            br_ini_delta_rev: BR_INI_DELTA_REV,
            br_ini_delta_speed: BR_INI_DELTA_SPEED,
            br_ini_delta_accel: BR_INI_DELTA_ACCEL,
            _reserved20: [u8; 0x04],
            br_cur_pos_time: BR_CUR_POS_TIME,
            br_cur_pos: BR_CUR_POS,
            br_cur_rev: BR_CUR_REV,
            br_cur_speed: BR_CUR_SPEED,
            br_cur_accel: BR_CUR_ACCEL,
        }
        impl BR {
            #[doc = "0x00 - Prediction Control Register"]
            #[inline(always)]
            pub const fn br_ctrl(&self) -> &BR_CTRL {
                &self.br_ctrl
            }
            #[doc = "0x04 - Prediction Timing Offset Register"]
            #[inline(always)]
            pub const fn br_timeoff(&self) -> &BR_TIMEOFF {
                &self.br_timeoff
            }
            #[doc = "0x08 - Prediction Triggering Period Offset Register"]
            #[inline(always)]
            pub const fn br_trg_period(&self) -> &BR_TRG_PERIOD {
                &self.br_trg_period
            }
            #[doc = "0x0c - Prediction Triggering First Offset Register"]
            #[inline(always)]
            pub const fn br_trg_f_time(&self) -> &BR_TRG_F_TIME {
                &self.br_trg_f_time
            }
            #[doc = "0x10 - Prediction Status Register"]
            #[inline(always)]
            pub const fn br_st(&self) -> &BR_ST {
                &self.br_st
            }
            #[doc = "0x40 - Prediction Configuration postion trigger cfg"]
            #[inline(always)]
            pub const fn br_trg_pos_cfg(&self) -> &BR_TRG_POS_CFG {
                &self.br_trg_pos_cfg
            }
            #[doc = "0x44 - Prediction Configuration postion threshold"]
            #[inline(always)]
            pub const fn br_trg_pos_thr(&self) -> &BR_TRG_POS_THR {
                &self.br_trg_pos_thr
            }
            #[doc = "0x48 - Prediction Configuration revolutiom threshold"]
            #[inline(always)]
            pub const fn br_trg_rev_thr(&self) -> &BR_TRG_REV_THR {
                &self.br_trg_rev_thr
            }
            #[doc = "0x4c - Prediction Configuration speed trigger cfg"]
            #[inline(always)]
            pub const fn br_trg_speed_cfg(&self) -> &BR_TRG_SPEED_CFG {
                &self.br_trg_speed_cfg
            }
            #[doc = "0x50 - Prediction Configuration speed threshold"]
            #[inline(always)]
            pub const fn br_trg_speed_thr(&self) -> &BR_TRG_SPEED_THR {
                &self.br_trg_speed_thr
            }
            #[doc = "0xc0 - Initialization timestamp for open-loop mode"]
            #[inline(always)]
            pub const fn br_ini_pos_time(&self) -> &BR_INI_POS_TIME {
                &self.br_ini_pos_time
            }
            #[doc = "0xc4 - Initialization position for open-loop mode"]
            #[inline(always)]
            pub const fn br_ini_pos(&self) -> &BR_INI_POS {
                &self.br_ini_pos
            }
            #[doc = "0xc8 - Initialization revolution for open-loop mode"]
            #[inline(always)]
            pub const fn br_ini_rev(&self) -> &BR_INI_REV {
                &self.br_ini_rev
            }
            #[doc = "0xcc - Initialization speed for open-loop mode"]
            #[inline(always)]
            pub const fn br_ini_speed(&self) -> &BR_INI_SPEED {
                &self.br_ini_speed
            }
            #[doc = "0xd0 - Initialization acceleration for open-loop mode"]
            #[inline(always)]
            pub const fn br_ini_accel(&self) -> &BR_INI_ACCEL {
                &self.br_ini_accel
            }
            #[doc = "0xd4 - Initialization timestamp for delta mode in prediction mode"]
            #[inline(always)]
            pub const fn br_ini_delta_pos_time(&self) -> &BR_INI_DELTA_POS_TIME {
                &self.br_ini_delta_pos_time
            }
            #[doc = "0xd8 - Initialization delta position for delta mode in prediction mode"]
            #[inline(always)]
            pub const fn br_ini_delta_pos(&self) -> &BR_INI_DELTA_POS {
                &self.br_ini_delta_pos
            }
            #[doc = "0xdc - Initialization delta revolution for delta mode in prediction mode"]
            #[inline(always)]
            pub const fn br_ini_delta_rev(&self) -> &BR_INI_DELTA_REV {
                &self.br_ini_delta_rev
            }
            #[doc = "0xe0 - Initialization delta speed for delta mode in prediction mode"]
            #[inline(always)]
            pub const fn br_ini_delta_speed(&self) -> &BR_INI_DELTA_SPEED {
                &self.br_ini_delta_speed
            }
            #[doc = "0xe4 - Initialization delta acceleration for delta mode in prediction mode"]
            #[inline(always)]
            pub const fn br_ini_delta_accel(&self) -> &BR_INI_DELTA_ACCEL {
                &self.br_ini_delta_accel
            }
            #[doc = "0xec - Monitor of the output timestamp"]
            #[inline(always)]
            pub const fn br_cur_pos_time(&self) -> &BR_CUR_POS_TIME {
                &self.br_cur_pos_time
            }
            #[doc = "0xf0 - Monitor of the output position"]
            #[inline(always)]
            pub const fn br_cur_pos(&self) -> &BR_CUR_POS {
                &self.br_cur_pos
            }
            #[doc = "0xf4 - Monitor of the output revolution"]
            #[inline(always)]
            pub const fn br_cur_rev(&self) -> &BR_CUR_REV {
                &self.br_cur_rev
            }
            #[doc = "0xf8 - Monitor of the output speed"]
            #[inline(always)]
            pub const fn br_cur_speed(&self) -> &BR_CUR_SPEED {
                &self.br_cur_speed
            }
            #[doc = "0xfc - Monitor of the output acceleration"]
            #[inline(always)]
            pub const fn br_cur_accel(&self) -> &BR_CUR_ACCEL {
                &self.br_cur_accel
            }
        }
        #[doc = "BR_CTRL (rw) register accessor: Prediction Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ctrl`]
module"]
        pub type BR_CTRL = crate::Reg<br_ctrl::BR_CTRL_SPEC>;
        #[doc = "Prediction Control Register"]
        pub mod br_ctrl {
            #[doc = "Register `BR_CTRL` reader"]
            pub type R = crate::R<BR_CTRL_SPEC>;
            #[doc = "Register `BR_CTRL` writer"]
            pub type W = crate::W<BR_CTRL_SPEC>;
            #[doc = "Field `BR_EN` reader - Branch Enable"]
            pub type BR_EN_R = crate::BitReader;
            #[doc = "Field `BR_EN` writer - Branch Enable"]
            pub type BR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `F_TRG_TYPE` reader - 1. First trigger by external trigger pin 0. First trigger by the timer When in CR\\[MANUAL_IO\\]=1 mode, it is the prediction trigger"]
            pub type F_TRG_TYPE_R = crate::BitReader;
            #[doc = "Field `F_TRG_TYPE` writer - 1. First trigger by external trigger pin 0. First trigger by the timer When in CR\\[MANUAL_IO\\]=1 mode, it is the prediction trigger"]
            pub type F_TRG_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `NF_TRG_TYPE` reader - 1. Each non-first trigger by external trigger pin 0. Each non-first trigger by the timer"]
            pub type NF_TRG_TYPE_R = crate::BitReader;
            #[doc = "Field `NF_TRG_TYPE` writer - 1. Each non-first trigger by external trigger pin 0. Each non-first trigger by the timer"]
            pub type NF_TRG_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PRED_MODE` reader - 1:continuously repeat pred, 0:cal the pred based on a definite time-stamp offset, 2:programed one-shot prediction mode"]
            pub type PRED_MODE_R = crate::FieldReader;
            #[doc = "Field `PRED_MODE` writer - 1:continuously repeat pred, 0:cal the pred based on a definite time-stamp offset, 2:programed one-shot prediction mode"]
            pub type PRED_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `OPEN_LOOP_MODE` reader - 1: in open loop mode 0: not in open loop mode"]
            pub type OPEN_LOOP_MODE_R = crate::BitReader;
            #[doc = "Field `OPEN_LOOP_MODE` writer - 1: in open loop mode 0: not in open loop mode"]
            pub type OPEN_LOOP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INI_DELTA_POS_REQ` reader - 1: Command to reload the delta pos. Auto clear 0:"]
            pub type INI_DELTA_POS_REQ_R = crate::BitReader;
            #[doc = "Field `INI_DELTA_POS_REQ` writer - 1: Command to reload the delta pos. Auto clear 0:"]
            pub type INI_DELTA_POS_REQ_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INI_DELTA_POS_CMD_MSK` reader - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
            pub type INI_DELTA_POS_CMD_MSK_R = crate::FieldReader;
            #[doc = "Field `INI_DELTA_POS_CMD_MSK` writer - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
            pub type INI_DELTA_POS_CMD_MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `INI_DELTA_POS_DONE_IE` reader - Interrupt Enable for INI_DELTA_POS_DONE"]
            pub type INI_DELTA_POS_DONE_IE_R = crate::BitReader;
            #[doc = "Field `INI_DELTA_POS_DONE_IE` writer - Interrupt Enable for INI_DELTA_POS_DONE"]
            pub type INI_DELTA_POS_DONE_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INI_DELTA_POS_TRG_TYPE` reader - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
            pub type INI_DELTA_POS_TRG_TYPE_R = crate::FieldReader;
            #[doc = "Field `INI_DELTA_POS_TRG_TYPE` writer - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
            pub type INI_DELTA_POS_TRG_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `INI_POS_CMD_MSK` reader - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
            pub type INI_POS_CMD_MSK_R = crate::FieldReader;
            #[doc = "Field `INI_POS_CMD_MSK` writer - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
            pub type INI_POS_CMD_MSK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `INI_POS_TRG_TYPE` reader - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
            pub type INI_POS_TRG_TYPE_R = crate::FieldReader;
            #[doc = "Field `INI_POS_TRG_TYPE` writer - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
            pub type INI_POS_TRG_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `POS_TRG_VALID_IE` reader - Interrupt Enable for POS_TRG_VALID"]
            pub type POS_TRG_VALID_IE_R = crate::BitReader;
            #[doc = "Field `POS_TRG_VALID_IE` writer - Interrupt Enable for POS_TRG_VALID"]
            pub type POS_TRG_VALID_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SPEED_TRG_VALID_IE` reader - Interrupt Enable for SPEED_TRG_VALID"]
            pub type SPEED_TRG_VALID_IE_R = crate::BitReader;
            #[doc = "Field `SPEED_TRG_VALID_IE` writer - Interrupt Enable for SPEED_TRG_VALID"]
            pub type SPEED_TRG_VALID_IE_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Branch Enable"]
                #[inline(always)]
                pub fn br_en(&self) -> BR_EN_R {
                    BR_EN_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - 1. First trigger by external trigger pin 0. First trigger by the timer When in CR\\[MANUAL_IO\\]=1 mode, it is the prediction trigger"]
                #[inline(always)]
                pub fn f_trg_type(&self) -> F_TRG_TYPE_R {
                    F_TRG_TYPE_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 2 - 1. Each non-first trigger by external trigger pin 0. Each non-first trigger by the timer"]
                #[inline(always)]
                pub fn nf_trg_type(&self) -> NF_TRG_TYPE_R {
                    NF_TRG_TYPE_R::new(((self.bits >> 2) & 1) != 0)
                }
                #[doc = "Bits 4:5 - 1:continuously repeat pred, 0:cal the pred based on a definite time-stamp offset, 2:programed one-shot prediction mode"]
                #[inline(always)]
                pub fn pred_mode(&self) -> PRED_MODE_R {
                    PRED_MODE_R::new(((self.bits >> 4) & 3) as u8)
                }
                #[doc = "Bit 7 - 1: in open loop mode 0: not in open loop mode"]
                #[inline(always)]
                pub fn open_loop_mode(&self) -> OPEN_LOOP_MODE_R {
                    OPEN_LOOP_MODE_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bit 8 - 1: Command to reload the delta pos. Auto clear 0:"]
                #[inline(always)]
                pub fn ini_delta_pos_req(&self) -> INI_DELTA_POS_REQ_R {
                    INI_DELTA_POS_REQ_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bits 9:12 - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
                #[inline(always)]
                pub fn ini_delta_pos_cmd_msk(&self) -> INI_DELTA_POS_CMD_MSK_R {
                    INI_DELTA_POS_CMD_MSK_R::new(((self.bits >> 9) & 0x0f) as u8)
                }
                #[doc = "Bit 13 - Interrupt Enable for INI_DELTA_POS_DONE"]
                #[inline(always)]
                pub fn ini_delta_pos_done_ie(&self) -> INI_DELTA_POS_DONE_IE_R {
                    INI_DELTA_POS_DONE_IE_R::new(((self.bits >> 13) & 1) != 0)
                }
                #[doc = "Bits 14:16 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
                #[inline(always)]
                pub fn ini_delta_pos_trg_type(&self) -> INI_DELTA_POS_TRG_TYPE_R {
                    INI_DELTA_POS_TRG_TYPE_R::new(((self.bits >> 14) & 7) as u8)
                }
                #[doc = "Bits 18:21 - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
                #[inline(always)]
                pub fn ini_pos_cmd_msk(&self) -> INI_POS_CMD_MSK_R {
                    INI_POS_CMD_MSK_R::new(((self.bits >> 18) & 0x0f) as u8)
                }
                #[doc = "Bits 23:25 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
                #[inline(always)]
                pub fn ini_pos_trg_type(&self) -> INI_POS_TRG_TYPE_R {
                    INI_POS_TRG_TYPE_R::new(((self.bits >> 23) & 7) as u8)
                }
                #[doc = "Bit 29 - Interrupt Enable for POS_TRG_VALID"]
                #[inline(always)]
                pub fn pos_trg_valid_ie(&self) -> POS_TRG_VALID_IE_R {
                    POS_TRG_VALID_IE_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 30 - Interrupt Enable for SPEED_TRG_VALID"]
                #[inline(always)]
                pub fn speed_trg_valid_ie(&self) -> SPEED_TRG_VALID_IE_R {
                    SPEED_TRG_VALID_IE_R::new(((self.bits >> 30) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Branch Enable"]
                #[inline(always)]
                #[must_use]
                pub fn br_en(&mut self) -> BR_EN_W<BR_CTRL_SPEC> {
                    BR_EN_W::new(self, 0)
                }
                #[doc = "Bit 1 - 1. First trigger by external trigger pin 0. First trigger by the timer When in CR\\[MANUAL_IO\\]=1 mode, it is the prediction trigger"]
                #[inline(always)]
                #[must_use]
                pub fn f_trg_type(&mut self) -> F_TRG_TYPE_W<BR_CTRL_SPEC> {
                    F_TRG_TYPE_W::new(self, 1)
                }
                #[doc = "Bit 2 - 1. Each non-first trigger by external trigger pin 0. Each non-first trigger by the timer"]
                #[inline(always)]
                #[must_use]
                pub fn nf_trg_type(&mut self) -> NF_TRG_TYPE_W<BR_CTRL_SPEC> {
                    NF_TRG_TYPE_W::new(self, 2)
                }
                #[doc = "Bits 4:5 - 1:continuously repeat pred, 0:cal the pred based on a definite time-stamp offset, 2:programed one-shot prediction mode"]
                #[inline(always)]
                #[must_use]
                pub fn pred_mode(&mut self) -> PRED_MODE_W<BR_CTRL_SPEC> {
                    PRED_MODE_W::new(self, 4)
                }
                #[doc = "Bit 7 - 1: in open loop mode 0: not in open loop mode"]
                #[inline(always)]
                #[must_use]
                pub fn open_loop_mode(&mut self) -> OPEN_LOOP_MODE_W<BR_CTRL_SPEC> {
                    OPEN_LOOP_MODE_W::new(self, 7)
                }
                #[doc = "Bit 8 - 1: Command to reload the delta pos. Auto clear 0:"]
                #[inline(always)]
                #[must_use]
                pub fn ini_delta_pos_req(&mut self) -> INI_DELTA_POS_REQ_W<BR_CTRL_SPEC> {
                    INI_DELTA_POS_REQ_W::new(self, 8)
                }
                #[doc = "Bits 9:12 - 1: change 0: won't change bit 3: for delta accel bit 2: for delta speed bit 1: for delta revolution bit 0: for delta position"]
                #[inline(always)]
                #[must_use]
                pub fn ini_delta_pos_cmd_msk(&mut self) -> INI_DELTA_POS_CMD_MSK_W<BR_CTRL_SPEC> {
                    INI_DELTA_POS_CMD_MSK_W::new(self, 9)
                }
                #[doc = "Bit 13 - Interrupt Enable for INI_DELTA_POS_DONE"]
                #[inline(always)]
                #[must_use]
                pub fn ini_delta_pos_done_ie(&mut self) -> INI_DELTA_POS_DONE_IE_W<BR_CTRL_SPEC> {
                    INI_DELTA_POS_DONE_IE_W::new(self, 13)
                }
                #[doc = "Bits 14:16 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
                #[inline(always)]
                #[must_use]
                pub fn ini_delta_pos_trg_type(&mut self) -> INI_DELTA_POS_TRG_TYPE_W<BR_CTRL_SPEC> {
                    INI_DELTA_POS_TRG_TYPE_W::new(self, 14)
                }
                #[doc = "Bits 18:21 - 1: change 0: won't change bit 3: for accel bit 2: for speed bit 1: for revolution bit 0: for position"]
                #[inline(always)]
                #[must_use]
                pub fn ini_pos_cmd_msk(&mut self) -> INI_POS_CMD_MSK_W<BR_CTRL_SPEC> {
                    INI_POS_CMD_MSK_W::new(self, 18)
                }
                #[doc = "Bits 23:25 - 0: Time Stamp in the configuration 1: Risedge of In Trg\\[0\\]
2: Risedge of In Trg\\[1\\]
3: Risedge of out trg\\[0\\]
4: Risedge of out trg\\[1\\]
5: Risedge of self pos trigger 6: Risedge of self speed trigger Others: no function"]
                #[inline(always)]
                #[must_use]
                pub fn ini_pos_trg_type(&mut self) -> INI_POS_TRG_TYPE_W<BR_CTRL_SPEC> {
                    INI_POS_TRG_TYPE_W::new(self, 23)
                }
                #[doc = "Bit 29 - Interrupt Enable for POS_TRG_VALID"]
                #[inline(always)]
                #[must_use]
                pub fn pos_trg_valid_ie(&mut self) -> POS_TRG_VALID_IE_W<BR_CTRL_SPEC> {
                    POS_TRG_VALID_IE_W::new(self, 29)
                }
                #[doc = "Bit 30 - Interrupt Enable for SPEED_TRG_VALID"]
                #[inline(always)]
                #[must_use]
                pub fn speed_trg_valid_ie(&mut self) -> SPEED_TRG_VALID_IE_W<BR_CTRL_SPEC> {
                    SPEED_TRG_VALID_IE_W::new(self, 30)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_CTRL_SPEC;
            impl crate::RegisterSpec for BR_CTRL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ctrl::R`](R) reader structure"]
            impl crate::Readable for BR_CTRL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ctrl::W`](W) writer structure"]
            impl crate::Writable for BR_CTRL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_CTRL to value 0"]
            impl crate::Resettable for BR_CTRL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TIMEOFF (rw) register accessor: Prediction Timing Offset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_timeoff::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_timeoff::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_timeoff`]
module"]
        pub type BR_TIMEOFF = crate::Reg<br_timeoff::BR_TIMEOFF_SPEC>;
        #[doc = "Prediction Timing Offset Register"]
        pub mod br_timeoff {
            #[doc = "Register `BR_TIMEOFF` reader"]
            pub type R = crate::R<BR_TIMEOFF_SPEC>;
            #[doc = "Register `BR_TIMEOFF` writer"]
            pub type W = crate::W<BR_TIMEOFF_SPEC>;
            #[doc = "Field `VAL` reader - ufix&lt;32, 0> time offset incycles from the trigger time"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - ufix&lt;32, 0> time offset incycles from the trigger time"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - ufix&lt;32, 0> time offset incycles from the trigger time"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - ufix&lt;32, 0> time offset incycles from the trigger time"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_TIMEOFF_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Timing Offset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_timeoff::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_timeoff::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TIMEOFF_SPEC;
            impl crate::RegisterSpec for BR_TIMEOFF_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_timeoff::R`](R) reader structure"]
            impl crate::Readable for BR_TIMEOFF_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_timeoff::W`](W) writer structure"]
            impl crate::Writable for BR_TIMEOFF_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TIMEOFF to value 0"]
            impl crate::Resettable for BR_TIMEOFF_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TRG_PERIOD (rw) register accessor: Prediction Triggering Period Offset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_period::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_period::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_trg_period`]
module"]
        pub type BR_TRG_PERIOD = crate::Reg<br_trg_period::BR_TRG_PERIOD_SPEC>;
        #[doc = "Prediction Triggering Period Offset Register"]
        pub mod br_trg_period {
            #[doc = "Register `BR_TRG_PERIOD` reader"]
            pub type R = crate::R<BR_TRG_PERIOD_SPEC>;
            #[doc = "Register `BR_TRG_PERIOD` writer"]
            pub type W = crate::W<BR_TRG_PERIOD_SPEC>;
            #[doc = "Field `VAL` reader - uifx&lt;32, 0>, time offset incycles between each trigger time"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - uifx&lt;32, 0>, time offset incycles between each trigger time"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - uifx&lt;32, 0>, time offset incycles between each trigger time"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - uifx&lt;32, 0>, time offset incycles between each trigger time"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_TRG_PERIOD_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Triggering Period Offset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_period::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_period::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TRG_PERIOD_SPEC;
            impl crate::RegisterSpec for BR_TRG_PERIOD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_trg_period::R`](R) reader structure"]
            impl crate::Readable for BR_TRG_PERIOD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_trg_period::W`](W) writer structure"]
            impl crate::Writable for BR_TRG_PERIOD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TRG_PERIOD to value 0"]
            impl crate::Resettable for BR_TRG_PERIOD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TRG_F_TIME (rw) register accessor: Prediction Triggering First Offset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_f_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_f_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_trg_f_time`]
module"]
        pub type BR_TRG_F_TIME = crate::Reg<br_trg_f_time::BR_TRG_F_TIME_SPEC>;
        #[doc = "Prediction Triggering First Offset Register"]
        pub mod br_trg_f_time {
            #[doc = "Register `BR_TRG_F_TIME` reader"]
            pub type R = crate::R<BR_TRG_F_TIME_SPEC>;
            #[doc = "Register `BR_TRG_F_TIME` writer"]
            pub type W = crate::W<BR_TRG_F_TIME_SPEC>;
            #[doc = "Field `VAL` reader - uifx&lt;32, 0> the time for the first trigger"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - uifx&lt;32, 0> the time for the first trigger"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - uifx&lt;32, 0> the time for the first trigger"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - uifx&lt;32, 0> the time for the first trigger"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_TRG_F_TIME_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Triggering First Offset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_f_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_f_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TRG_F_TIME_SPEC;
            impl crate::RegisterSpec for BR_TRG_F_TIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_trg_f_time::R`](R) reader structure"]
            impl crate::Readable for BR_TRG_F_TIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_trg_f_time::W`](W) writer structure"]
            impl crate::Writable for BR_TRG_F_TIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TRG_F_TIME to value 0"]
            impl crate::Resettable for BR_TRG_F_TIME_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_ST (rw) register accessor: Prediction Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_st::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_st::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_st`]
module"]
        pub type BR_ST = crate::Reg<br_st::BR_ST_SPEC>;
        #[doc = "Prediction Status Register"]
        pub mod br_st {
            #[doc = "Register `BR_ST` reader"]
            pub type R = crate::R<BR_ST_SPEC>;
            #[doc = "Register `BR_ST` writer"]
            pub type W = crate::W<BR_ST_SPEC>;
            #[doc = "Field `ERR_ID` reader - The module's error ID output"]
            pub type ERR_ID_R = crate::FieldReader;
            #[doc = "Field `IDLE` reader - 1: The prediction module is idle. 0: The prediction module is not idle."]
            pub type IDLE_R = crate::BitReader;
            #[doc = "Field `INI_DELTA_POS_DONE` writer - 1: the initialization of delta position command is done 0: the initialization of delta position command is not done"]
            pub type INI_DELTA_POS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `POS_TRG_VLD` writer - 1：self position trigger event found 0：self position trigger event not found yet"]
            pub type POS_TRG_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SPEED_TRG_VLD` writer - 1：self speed trigger event found 0：self speed trigger event not found yet"]
            pub type SPEED_TRG_VLD_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `OPEN_LOOP_ST` reader - 1：in open loop mode 0：in closed loop mode"]
            pub type OPEN_LOOP_ST_R = crate::BitReader;
            impl R {
                #[doc = "Bits 0:3 - The module's error ID output"]
                #[inline(always)]
                pub fn err_id(&self) -> ERR_ID_R {
                    ERR_ID_R::new((self.bits & 0x0f) as u8)
                }
                #[doc = "Bit 5 - 1: The prediction module is idle. 0: The prediction module is not idle."]
                #[inline(always)]
                pub fn idle(&self) -> IDLE_R {
                    IDLE_R::new(((self.bits >> 5) & 1) != 0)
                }
                #[doc = "Bit 10 - 1：in open loop mode 0：in closed loop mode"]
                #[inline(always)]
                pub fn open_loop_st(&self) -> OPEN_LOOP_ST_R {
                    OPEN_LOOP_ST_R::new(((self.bits >> 10) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 6 - 1: the initialization of delta position command is done 0: the initialization of delta position command is not done"]
                #[inline(always)]
                #[must_use]
                pub fn ini_delta_pos_done(&mut self) -> INI_DELTA_POS_DONE_W<BR_ST_SPEC> {
                    INI_DELTA_POS_DONE_W::new(self, 6)
                }
                #[doc = "Bit 8 - 1：self position trigger event found 0：self position trigger event not found yet"]
                #[inline(always)]
                #[must_use]
                pub fn pos_trg_vld(&mut self) -> POS_TRG_VLD_W<BR_ST_SPEC> {
                    POS_TRG_VLD_W::new(self, 8)
                }
                #[doc = "Bit 9 - 1：self speed trigger event found 0：self speed trigger event not found yet"]
                #[inline(always)]
                #[must_use]
                pub fn speed_trg_vld(&mut self) -> SPEED_TRG_VLD_W<BR_ST_SPEC> {
                    SPEED_TRG_VLD_W::new(self, 9)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_st::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_st::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_ST_SPEC;
            impl crate::RegisterSpec for BR_ST_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_st::R`](R) reader structure"]
            impl crate::Readable for BR_ST_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_st::W`](W) writer structure"]
            impl crate::Writable for BR_ST_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_ST to value 0"]
            impl crate::Resettable for BR_ST_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TRG_pos_cfg (rw) register accessor: Prediction Configuration postion trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_pos_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_pos_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_trg_pos_cfg`]
module"]
        pub type BR_TRG_POS_CFG = crate::Reg<br_trg_pos_cfg::BR_TRG_POS_CFG_SPEC>;
        #[doc = "Prediction Configuration postion trigger cfg"]
        pub mod br_trg_pos_cfg {
            #[doc = "Register `BR_TRG_pos_cfg` reader"]
            pub type R = crate::R<BR_TRG_POS_CFG_SPEC>;
            #[doc = "Register `BR_TRG_pos_cfg` writer"]
            pub type W = crate::W<BR_TRG_POS_CFG_SPEC>;
            #[doc = "Field `EN` reader - 1-trigger valid; 0-Trigger not valid"]
            pub type EN_R = crate::BitReader;
            #[doc = "Field `EN` writer - 1-trigger valid; 0-Trigger not valid"]
            pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `EDGE` reader - bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
            pub type EDGE_R = crate::BitReader;
            #[doc = "Field `EDGE` writer - bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
            pub type EDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid"]
                #[inline(always)]
                pub fn en(&self) -> EN_R {
                    EN_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
                #[inline(always)]
                pub fn edge(&self) -> EDGE_R {
                    EDGE_R::new(((self.bits >> 1) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid"]
                #[inline(always)]
                #[must_use]
                pub fn en(&mut self) -> EN_W<BR_TRG_POS_CFG_SPEC> {
                    EN_W::new(self, 0)
                }
                #[doc = "Bit 1 - bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than"]
                #[inline(always)]
                #[must_use]
                pub fn edge(&mut self) -> EDGE_W<BR_TRG_POS_CFG_SPEC> {
                    EDGE_W::new(self, 1)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Configuration postion trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_pos_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_pos_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TRG_POS_CFG_SPEC;
            impl crate::RegisterSpec for BR_TRG_POS_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_trg_pos_cfg::R`](R) reader structure"]
            impl crate::Readable for BR_TRG_POS_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_trg_pos_cfg::W`](W) writer structure"]
            impl crate::Writable for BR_TRG_POS_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TRG_pos_cfg to value 0"]
            impl crate::Resettable for BR_TRG_POS_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TRG_pos_thr (rw) register accessor: Prediction Configuration postion threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_pos_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_pos_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_trg_pos_thr`]
module"]
        pub type BR_TRG_POS_THR = crate::Reg<br_trg_pos_thr::BR_TRG_POS_THR_SPEC>;
        #[doc = "Prediction Configuration postion threshold"]
        pub mod br_trg_pos_thr {
            #[doc = "Register `BR_TRG_pos_thr` reader"]
            pub type R = crate::R<BR_TRG_POS_THR_SPEC>;
            #[doc = "Register `BR_TRG_pos_thr` writer"]
            pub type W = crate::W<BR_TRG_POS_THR_SPEC>;
            #[doc = "Field `VAL` reader - For pos out trigger (pos). ufix&lt;32, 32>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - For pos out trigger (pos). ufix&lt;32, 32>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - For pos out trigger (pos). ufix&lt;32, 32>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - For pos out trigger (pos). ufix&lt;32, 32>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_TRG_POS_THR_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Configuration postion threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_pos_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_pos_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TRG_POS_THR_SPEC;
            impl crate::RegisterSpec for BR_TRG_POS_THR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_trg_pos_thr::R`](R) reader structure"]
            impl crate::Readable for BR_TRG_POS_THR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_trg_pos_thr::W`](W) writer structure"]
            impl crate::Writable for BR_TRG_POS_THR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TRG_pos_thr to value 0"]
            impl crate::Resettable for BR_TRG_POS_THR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TRG_rev_thr (rw) register accessor: Prediction Configuration revolutiom threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_rev_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_rev_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_trg_rev_thr`]
module"]
        pub type BR_TRG_REV_THR = crate::Reg<br_trg_rev_thr::BR_TRG_REV_THR_SPEC>;
        #[doc = "Prediction Configuration revolutiom threshold"]
        pub mod br_trg_rev_thr {
            #[doc = "Register `BR_TRG_rev_thr` reader"]
            pub type R = crate::R<BR_TRG_REV_THR_SPEC>;
            #[doc = "Register `BR_TRG_rev_thr` writer"]
            pub type W = crate::W<BR_TRG_REV_THR_SPEC>;
            #[doc = "Field `VAL` reader - For pos out trigger (rev) ufix&lt;32, 0>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - For pos out trigger (rev) ufix&lt;32, 0>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - For pos out trigger (rev) ufix&lt;32, 0>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - For pos out trigger (rev) ufix&lt;32, 0>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_TRG_REV_THR_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Configuration revolutiom threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_rev_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_rev_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TRG_REV_THR_SPEC;
            impl crate::RegisterSpec for BR_TRG_REV_THR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_trg_rev_thr::R`](R) reader structure"]
            impl crate::Readable for BR_TRG_REV_THR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_trg_rev_thr::W`](W) writer structure"]
            impl crate::Writable for BR_TRG_REV_THR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TRG_rev_thr to value 0"]
            impl crate::Resettable for BR_TRG_REV_THR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TRG_speed_cfg (rw) register accessor: Prediction Configuration speed trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_speed_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_speed_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_trg_speed_cfg`]
module"]
        pub type BR_TRG_SPEED_CFG = crate::Reg<br_trg_speed_cfg::BR_TRG_SPEED_CFG_SPEC>;
        #[doc = "Prediction Configuration speed trigger cfg"]
        pub mod br_trg_speed_cfg {
            #[doc = "Register `BR_TRG_speed_cfg` reader"]
            pub type R = crate::R<BR_TRG_SPEED_CFG_SPEC>;
            #[doc = "Register `BR_TRG_speed_cfg` writer"]
            pub type W = crate::W<BR_TRG_SPEED_CFG_SPEC>;
            #[doc = "Field `EN` reader - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
            pub type EN_R = crate::BitReader;
            #[doc = "Field `EN` writer - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
            pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `EDGE_SEL` reader - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
            pub type EDGE_SEL_R = crate::BitReader;
            #[doc = "Field `EDGE_SEL` writer - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
            pub type EDGE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `COMP_TYPE` reader - Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
            pub type COMP_TYPE_R = crate::BitReader;
            #[doc = "Field `COMP_TYPE` writer - Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
            pub type COMP_TYPE_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
                #[inline(always)]
                pub fn en(&self) -> EN_R {
                    EN_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
                #[inline(always)]
                pub fn edge_sel(&self) -> EDGE_SEL_R {
                    EDGE_SEL_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 2 - Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
                #[inline(always)]
                pub fn comp_type(&self) -> COMP_TYPE_R {
                    COMP_TYPE_R::new(((self.bits >> 2) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - 1-trigger valid; 0-Trigger not valid Normally it means either the max pos speed, or the min negative speed."]
                #[inline(always)]
                #[must_use]
                pub fn en(&mut self) -> EN_W<BR_TRG_SPEED_CFG_SPEC> {
                    EN_W::new(self, 0)
                }
                #[doc = "Bit 1 - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than"]
                #[inline(always)]
                #[must_use]
                pub fn edge_sel(&mut self) -> EDGE_SEL_W<BR_TRG_SPEED_CFG_SPEC> {
                    EDGE_SEL_W::new(self, 1)
                }
                #[doc = "Bit 2 - Use abs value for comparion. 0: Use the speed with direction info (so not the abs value)"]
                #[inline(always)]
                #[must_use]
                pub fn comp_type(&mut self) -> COMP_TYPE_W<BR_TRG_SPEED_CFG_SPEC> {
                    COMP_TYPE_W::new(self, 2)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Configuration speed trigger cfg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_speed_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_speed_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TRG_SPEED_CFG_SPEC;
            impl crate::RegisterSpec for BR_TRG_SPEED_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_trg_speed_cfg::R`](R) reader structure"]
            impl crate::Readable for BR_TRG_SPEED_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_trg_speed_cfg::W`](W) writer structure"]
            impl crate::Writable for BR_TRG_SPEED_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TRG_speed_cfg to value 0"]
            impl crate::Resettable for BR_TRG_SPEED_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_TRG_speed_thr (rw) register accessor: Prediction Configuration speed threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_speed_thr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_speed_thr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_trg_speed_thr`]
module"]
        pub type BR_TRG_SPEED_THR = crate::Reg<br_trg_speed_thr::BR_TRG_SPEED_THR_SPEC>;
        #[doc = "Prediction Configuration speed threshold"]
        pub mod br_trg_speed_thr {
            #[doc = "Register `BR_TRG_speed_thr` reader"]
            pub type R = crate::R<BR_TRG_SPEED_THR_SPEC>;
            #[doc = "Register `BR_TRG_speed_thr` writer"]
            pub type W = crate::W<BR_TRG_SPEED_THR_SPEC>;
            #[doc = "Field `VAL` reader - For speed trigger. continuous mode: fix&lt;32, 19>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - For speed trigger. continuous mode: fix&lt;32, 19>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - For speed trigger. continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - For speed trigger. continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_TRG_SPEED_THR_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Prediction Configuration speed threshold\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_trg_speed_thr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_trg_speed_thr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_TRG_SPEED_THR_SPEC;
            impl crate::RegisterSpec for BR_TRG_SPEED_THR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_trg_speed_thr::R`](R) reader structure"]
            impl crate::Readable for BR_TRG_SPEED_THR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_trg_speed_thr::W`](W) writer structure"]
            impl crate::Writable for BR_TRG_SPEED_THR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_TRG_speed_thr to value 0"]
            impl crate::Resettable for BR_TRG_SPEED_THR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_POS_TIME (rw) register accessor: Initialization timestamp for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_pos_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_pos_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_pos_time`]
module"]
        pub type BR_INI_POS_TIME = crate::Reg<br_ini_pos_time::BR_INI_POS_TIME_SPEC>;
        #[doc = "Initialization timestamp for open-loop mode"]
        pub mod br_ini_pos_time {
            #[doc = "Register `BR_INI_POS_TIME` reader"]
            pub type R = crate::R<BR_INI_POS_TIME_SPEC>;
            #[doc = "Register `BR_INI_POS_TIME` writer"]
            pub type W = crate::W<BR_INI_POS_TIME_SPEC>;
            #[doc = "Field `VAL` reader - indicate the time to change the values. 0: instant change"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - indicate the time to change the values. 0: instant change"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_POS_TIME_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization timestamp for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_pos_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_pos_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_POS_TIME_SPEC;
            impl crate::RegisterSpec for BR_INI_POS_TIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_pos_time::R`](R) reader structure"]
            impl crate::Readable for BR_INI_POS_TIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_pos_time::W`](W) writer structure"]
            impl crate::Writable for BR_INI_POS_TIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_POS_TIME to value 0"]
            impl crate::Resettable for BR_INI_POS_TIME_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_POS (rw) register accessor: Initialization position for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_pos`]
module"]
        pub type BR_INI_POS = crate::Reg<br_ini_pos::BR_INI_POS_SPEC>;
        #[doc = "Initialization position for open-loop mode"]
        pub mod br_ini_pos {
            #[doc = "Register `BR_INI_POS` reader"]
            pub type R = crate::R<BR_INI_POS_SPEC>;
            #[doc = "Register `BR_INI_POS` writer"]
            pub type W = crate::W<BR_INI_POS_SPEC>;
            #[doc = "Field `VAL` reader - the value ufix&lt;32, 32>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value ufix&lt;32, 32>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value ufix&lt;32, 32>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value ufix&lt;32, 32>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_POS_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization position for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_POS_SPEC;
            impl crate::RegisterSpec for BR_INI_POS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_pos::R`](R) reader structure"]
            impl crate::Readable for BR_INI_POS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_pos::W`](W) writer structure"]
            impl crate::Writable for BR_INI_POS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_POS to value 0"]
            impl crate::Resettable for BR_INI_POS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_REV (rw) register accessor: Initialization revolution for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_rev`]
module"]
        pub type BR_INI_REV = crate::Reg<br_ini_rev::BR_INI_REV_SPEC>;
        #[doc = "Initialization revolution for open-loop mode"]
        pub mod br_ini_rev {
            #[doc = "Register `BR_INI_REV` reader"]
            pub type R = crate::R<BR_INI_REV_SPEC>;
            #[doc = "Register `BR_INI_REV` writer"]
            pub type W = crate::W<BR_INI_REV_SPEC>;
            #[doc = "Field `VAL` reader - the value ufix&lt;32, 0>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value ufix&lt;32, 0>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value ufix&lt;32, 0>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value ufix&lt;32, 0>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_REV_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization revolution for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_REV_SPEC;
            impl crate::RegisterSpec for BR_INI_REV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_rev::R`](R) reader structure"]
            impl crate::Readable for BR_INI_REV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_rev::W`](W) writer structure"]
            impl crate::Writable for BR_INI_REV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_REV to value 0"]
            impl crate::Resettable for BR_INI_REV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_SPEED (rw) register accessor: Initialization speed for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_speed`]
module"]
        pub type BR_INI_SPEED = crate::Reg<br_ini_speed::BR_INI_SPEED_SPEC>;
        #[doc = "Initialization speed for open-loop mode"]
        pub mod br_ini_speed {
            #[doc = "Register `BR_INI_SPEED` reader"]
            pub type R = crate::R<BR_INI_SPEED_SPEC>;
            #[doc = "Register `BR_INI_SPEED` writer"]
            pub type W = crate::W<BR_INI_SPEED_SPEC>;
            #[doc = "Field `VAL` reader - the value fix&lt;32, 19>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value fix&lt;32, 19>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value fix&lt;32, 19>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value fix&lt;32, 19>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_SPEED_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization speed for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_SPEED_SPEC;
            impl crate::RegisterSpec for BR_INI_SPEED_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_speed::R`](R) reader structure"]
            impl crate::Readable for BR_INI_SPEED_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_speed::W`](W) writer structure"]
            impl crate::Writable for BR_INI_SPEED_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_SPEED to value 0"]
            impl crate::Resettable for BR_INI_SPEED_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_ACCEL (rw) register accessor: Initialization acceleration for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_accel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_accel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_accel`]
module"]
        pub type BR_INI_ACCEL = crate::Reg<br_ini_accel::BR_INI_ACCEL_SPEC>;
        #[doc = "Initialization acceleration for open-loop mode"]
        pub mod br_ini_accel {
            #[doc = "Register `BR_INI_ACCEL` reader"]
            pub type R = crate::R<BR_INI_ACCEL_SPEC>;
            #[doc = "Register `BR_INI_ACCEL` writer"]
            pub type W = crate::W<BR_INI_ACCEL_SPEC>;
            #[doc = "Field `VAL` reader - the value continuous mode: fix&lt;32, 19>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value continuous mode: fix&lt;32, 19>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_ACCEL_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization acceleration for open-loop mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_accel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_accel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_ACCEL_SPEC;
            impl crate::RegisterSpec for BR_INI_ACCEL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_accel::R`](R) reader structure"]
            impl crate::Readable for BR_INI_ACCEL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_accel::W`](W) writer structure"]
            impl crate::Writable for BR_INI_ACCEL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_ACCEL to value 0"]
            impl crate::Resettable for BR_INI_ACCEL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_DELTA_POS_TIME (rw) register accessor: Initialization timestamp for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_pos_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_pos_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_delta_pos_time`]
module"]
        pub type BR_INI_DELTA_POS_TIME =
            crate::Reg<br_ini_delta_pos_time::BR_INI_DELTA_POS_TIME_SPEC>;
        #[doc = "Initialization timestamp for delta mode in prediction mode"]
        pub mod br_ini_delta_pos_time {
            #[doc = "Register `BR_INI_DELTA_POS_TIME` reader"]
            pub type R = crate::R<BR_INI_DELTA_POS_TIME_SPEC>;
            #[doc = "Register `BR_INI_DELTA_POS_TIME` writer"]
            pub type W = crate::W<BR_INI_DELTA_POS_TIME_SPEC>;
            #[doc = "Field `VAL` reader - indicate the time to change the values. 0: instant change"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - indicate the time to change the values. 0: instant change"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - indicate the time to change the values. 0: instant change"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_DELTA_POS_TIME_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization timestamp for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_pos_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_pos_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_DELTA_POS_TIME_SPEC;
            impl crate::RegisterSpec for BR_INI_DELTA_POS_TIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_delta_pos_time::R`](R) reader structure"]
            impl crate::Readable for BR_INI_DELTA_POS_TIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_delta_pos_time::W`](W) writer structure"]
            impl crate::Writable for BR_INI_DELTA_POS_TIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_DELTA_POS_TIME to value 0"]
            impl crate::Resettable for BR_INI_DELTA_POS_TIME_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_DELTA_POS (rw) register accessor: Initialization delta position for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_delta_pos`]
module"]
        pub type BR_INI_DELTA_POS = crate::Reg<br_ini_delta_pos::BR_INI_DELTA_POS_SPEC>;
        #[doc = "Initialization delta position for delta mode in prediction mode"]
        pub mod br_ini_delta_pos {
            #[doc = "Register `BR_INI_DELTA_POS` reader"]
            pub type R = crate::R<BR_INI_DELTA_POS_SPEC>;
            #[doc = "Register `BR_INI_DELTA_POS` writer"]
            pub type W = crate::W<BR_INI_DELTA_POS_SPEC>;
            #[doc = "Field `VAL` reader - the value continuous mode: ufix&lt;32, 32>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value continuous mode: ufix&lt;32, 32>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value continuous mode: ufix&lt;32, 32>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value continuous mode: ufix&lt;32, 32>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_DELTA_POS_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization delta position for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_DELTA_POS_SPEC;
            impl crate::RegisterSpec for BR_INI_DELTA_POS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_delta_pos::R`](R) reader structure"]
            impl crate::Readable for BR_INI_DELTA_POS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_delta_pos::W`](W) writer structure"]
            impl crate::Writable for BR_INI_DELTA_POS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_DELTA_POS to value 0"]
            impl crate::Resettable for BR_INI_DELTA_POS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_DELTA_REV (rw) register accessor: Initialization delta revolution for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_delta_rev`]
module"]
        pub type BR_INI_DELTA_REV = crate::Reg<br_ini_delta_rev::BR_INI_DELTA_REV_SPEC>;
        #[doc = "Initialization delta revolution for delta mode in prediction mode"]
        pub mod br_ini_delta_rev {
            #[doc = "Register `BR_INI_DELTA_REV` reader"]
            pub type R = crate::R<BR_INI_DELTA_REV_SPEC>;
            #[doc = "Register `BR_INI_DELTA_REV` writer"]
            pub type W = crate::W<BR_INI_DELTA_REV_SPEC>;
            #[doc = "Field `VAL` reader - the value continuous mode: fix&lt;32, 0>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value continuous mode: fix&lt;32, 0>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 0>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 0>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_DELTA_REV_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization delta revolution for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_DELTA_REV_SPEC;
            impl crate::RegisterSpec for BR_INI_DELTA_REV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_delta_rev::R`](R) reader structure"]
            impl crate::Readable for BR_INI_DELTA_REV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_delta_rev::W`](W) writer structure"]
            impl crate::Writable for BR_INI_DELTA_REV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_DELTA_REV to value 0"]
            impl crate::Resettable for BR_INI_DELTA_REV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_DELTA_SPEED (rw) register accessor: Initialization delta speed for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_delta_speed`]
module"]
        pub type BR_INI_DELTA_SPEED = crate::Reg<br_ini_delta_speed::BR_INI_DELTA_SPEED_SPEC>;
        #[doc = "Initialization delta speed for delta mode in prediction mode"]
        pub mod br_ini_delta_speed {
            #[doc = "Register `BR_INI_DELTA_SPEED` reader"]
            pub type R = crate::R<BR_INI_DELTA_SPEED_SPEC>;
            #[doc = "Register `BR_INI_DELTA_SPEED` writer"]
            pub type W = crate::W<BR_INI_DELTA_SPEED_SPEC>;
            #[doc = "Field `VAL` reader - the value continuous mode: fix&lt;32, 19>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value continuous mode: fix&lt;32, 19>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_DELTA_SPEED_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization delta speed for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_DELTA_SPEED_SPEC;
            impl crate::RegisterSpec for BR_INI_DELTA_SPEED_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_delta_speed::R`](R) reader structure"]
            impl crate::Readable for BR_INI_DELTA_SPEED_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_delta_speed::W`](W) writer structure"]
            impl crate::Writable for BR_INI_DELTA_SPEED_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_DELTA_SPEED to value 0"]
            impl crate::Resettable for BR_INI_DELTA_SPEED_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_INI_DELTA_ACCEL (rw) register accessor: Initialization delta acceleration for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_accel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_accel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_ini_delta_accel`]
module"]
        pub type BR_INI_DELTA_ACCEL = crate::Reg<br_ini_delta_accel::BR_INI_DELTA_ACCEL_SPEC>;
        #[doc = "Initialization delta acceleration for delta mode in prediction mode"]
        pub mod br_ini_delta_accel {
            #[doc = "Register `BR_INI_DELTA_ACCEL` reader"]
            pub type R = crate::R<BR_INI_DELTA_ACCEL_SPEC>;
            #[doc = "Register `BR_INI_DELTA_ACCEL` writer"]
            pub type W = crate::W<BR_INI_DELTA_ACCEL_SPEC>;
            #[doc = "Field `VAL` reader - the value continuous mode: fix&lt;32, 19>"]
            pub type VAL_R = crate::FieldReader<u32>;
            #[doc = "Field `VAL` writer - the value continuous mode: fix&lt;32, 19>"]
            pub type VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - the value continuous mode: fix&lt;32, 19>"]
                #[inline(always)]
                #[must_use]
                pub fn val(&mut self) -> VAL_W<BR_INI_DELTA_ACCEL_SPEC> {
                    VAL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Initialization delta acceleration for delta mode in prediction mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_ini_delta_accel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_ini_delta_accel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_INI_DELTA_ACCEL_SPEC;
            impl crate::RegisterSpec for BR_INI_DELTA_ACCEL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_ini_delta_accel::R`](R) reader structure"]
            impl crate::Readable for BR_INI_DELTA_ACCEL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_ini_delta_accel::W`](W) writer structure"]
            impl crate::Writable for BR_INI_DELTA_ACCEL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_INI_DELTA_ACCEL to value 0"]
            impl crate::Resettable for BR_INI_DELTA_ACCEL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_CUR_POS_TIME (rw) register accessor: Monitor of the output timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_pos_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_pos_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_cur_pos_time`]
module"]
        pub type BR_CUR_POS_TIME = crate::Reg<br_cur_pos_time::BR_CUR_POS_TIME_SPEC>;
        #[doc = "Monitor of the output timestamp"]
        pub mod br_cur_pos_time {
            #[doc = "Register `BR_CUR_POS_TIME` reader"]
            pub type R = crate::R<BR_CUR_POS_TIME_SPEC>;
            #[doc = "Register `BR_CUR_POS_TIME` writer"]
            pub type W = crate::W<BR_CUR_POS_TIME_SPEC>;
            #[doc = "Field `VAL` reader - the value"]
            pub type VAL_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - the value"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Monitor of the output timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_pos_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_pos_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_CUR_POS_TIME_SPEC;
            impl crate::RegisterSpec for BR_CUR_POS_TIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_cur_pos_time::R`](R) reader structure"]
            impl crate::Readable for BR_CUR_POS_TIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_cur_pos_time::W`](W) writer structure"]
            impl crate::Writable for BR_CUR_POS_TIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_CUR_POS_TIME to value 0"]
            impl crate::Resettable for BR_CUR_POS_TIME_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_CUR_POS (rw) register accessor: Monitor of the output position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_cur_pos`]
module"]
        pub type BR_CUR_POS = crate::Reg<br_cur_pos::BR_CUR_POS_SPEC>;
        #[doc = "Monitor of the output position"]
        pub mod br_cur_pos {
            #[doc = "Register `BR_CUR_POS` reader"]
            pub type R = crate::R<BR_CUR_POS_SPEC>;
            #[doc = "Register `BR_CUR_POS` writer"]
            pub type W = crate::W<BR_CUR_POS_SPEC>;
            #[doc = "Field `VAL` reader - the value"]
            pub type VAL_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - the value"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Monitor of the output position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_CUR_POS_SPEC;
            impl crate::RegisterSpec for BR_CUR_POS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_cur_pos::R`](R) reader structure"]
            impl crate::Readable for BR_CUR_POS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_cur_pos::W`](W) writer structure"]
            impl crate::Writable for BR_CUR_POS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_CUR_POS to value 0"]
            impl crate::Resettable for BR_CUR_POS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_CUR_REV (rw) register accessor: Monitor of the output revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_cur_rev`]
module"]
        pub type BR_CUR_REV = crate::Reg<br_cur_rev::BR_CUR_REV_SPEC>;
        #[doc = "Monitor of the output revolution"]
        pub mod br_cur_rev {
            #[doc = "Register `BR_CUR_REV` reader"]
            pub type R = crate::R<BR_CUR_REV_SPEC>;
            #[doc = "Register `BR_CUR_REV` writer"]
            pub type W = crate::W<BR_CUR_REV_SPEC>;
            #[doc = "Field `VAL` reader - the value"]
            pub type VAL_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - the value"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Monitor of the output revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_CUR_REV_SPEC;
            impl crate::RegisterSpec for BR_CUR_REV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_cur_rev::R`](R) reader structure"]
            impl crate::Readable for BR_CUR_REV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_cur_rev::W`](W) writer structure"]
            impl crate::Writable for BR_CUR_REV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_CUR_REV to value 0"]
            impl crate::Resettable for BR_CUR_REV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_CUR_SPEED (rw) register accessor: Monitor of the output speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_cur_speed`]
module"]
        pub type BR_CUR_SPEED = crate::Reg<br_cur_speed::BR_CUR_SPEED_SPEC>;
        #[doc = "Monitor of the output speed"]
        pub mod br_cur_speed {
            #[doc = "Register `BR_CUR_SPEED` reader"]
            pub type R = crate::R<BR_CUR_SPEED_SPEC>;
            #[doc = "Register `BR_CUR_SPEED` writer"]
            pub type W = crate::W<BR_CUR_SPEED_SPEC>;
            #[doc = "Field `VAL` reader - the value"]
            pub type VAL_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - the value"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Monitor of the output speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_CUR_SPEED_SPEC;
            impl crate::RegisterSpec for BR_CUR_SPEED_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_cur_speed::R`](R) reader structure"]
            impl crate::Readable for BR_CUR_SPEED_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_cur_speed::W`](W) writer structure"]
            impl crate::Writable for BR_CUR_SPEED_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_CUR_SPEED to value 0"]
            impl crate::Resettable for BR_CUR_SPEED_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BR_CUR_ACCEL (rw) register accessor: Monitor of the output acceleration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_accel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_accel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@br_cur_accel`]
module"]
        pub type BR_CUR_ACCEL = crate::Reg<br_cur_accel::BR_CUR_ACCEL_SPEC>;
        #[doc = "Monitor of the output acceleration"]
        pub mod br_cur_accel {
            #[doc = "Register `BR_CUR_ACCEL` reader"]
            pub type R = crate::R<BR_CUR_ACCEL_SPEC>;
            #[doc = "Register `BR_CUR_ACCEL` writer"]
            pub type W = crate::W<BR_CUR_ACCEL_SPEC>;
            #[doc = "Field `VAL` reader - the value"]
            pub type VAL_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - the value"]
                #[inline(always)]
                pub fn val(&self) -> VAL_R {
                    VAL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Monitor of the output acceleration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`br_cur_accel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`br_cur_accel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BR_CUR_ACCEL_SPEC;
            impl crate::RegisterSpec for BR_CUR_ACCEL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`br_cur_accel::R`](R) reader structure"]
            impl crate::Readable for BR_CUR_ACCEL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`br_cur_accel::W`](W) writer structure"]
            impl crate::Writable for BR_CUR_ACCEL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BR_CUR_ACCEL to value 0"]
            impl crate::Resettable for BR_CUR_ACCEL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "BK0_TIMESTAMP (rw) register accessor: Monitor of the just received input timestamp for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_timestamp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_timestamp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk0_timestamp`]
module"]
    pub type BK0_TIMESTAMP = crate::Reg<bk0_timestamp::BK0_TIMESTAMP_SPEC>;
    #[doc = "Monitor of the just received input timestamp for tracing logic"]
    pub mod bk0_timestamp {
        #[doc = "Register `BK0_TIMESTAMP` reader"]
        pub type R = crate::R<BK0_TIMESTAMP_SPEC>;
        #[doc = "Register `BK0_TIMESTAMP` writer"]
        pub type W = crate::W<BK0_TIMESTAMP_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the just received input timestamp for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_timestamp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_timestamp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK0_TIMESTAMP_SPEC;
        impl crate::RegisterSpec for BK0_TIMESTAMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk0_timestamp::R`](R) reader structure"]
        impl crate::Readable for BK0_TIMESTAMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk0_timestamp::W`](W) writer structure"]
        impl crate::Writable for BK0_TIMESTAMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK0_TIMESTAMP to value 0"]
        impl crate::Resettable for BK0_TIMESTAMP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK0_POSITION (rw) register accessor: Monitor of the just received input position for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_position::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_position::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk0_position`]
module"]
    pub type BK0_POSITION = crate::Reg<bk0_position::BK0_POSITION_SPEC>;
    #[doc = "Monitor of the just received input position for tracing logic"]
    pub mod bk0_position {
        #[doc = "Register `BK0_POSITION` reader"]
        pub type R = crate::R<BK0_POSITION_SPEC>;
        #[doc = "Register `BK0_POSITION` writer"]
        pub type W = crate::W<BK0_POSITION_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the just received input position for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_position::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_position::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK0_POSITION_SPEC;
        impl crate::RegisterSpec for BK0_POSITION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk0_position::R`](R) reader structure"]
        impl crate::Readable for BK0_POSITION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk0_position::W`](W) writer structure"]
        impl crate::Writable for BK0_POSITION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK0_POSITION to value 0"]
        impl crate::Resettable for BK0_POSITION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK0_REVOLUTION (rw) register accessor: Monitor of the just received input revolution for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_revolution::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_revolution::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk0_revolution`]
module"]
    pub type BK0_REVOLUTION = crate::Reg<bk0_revolution::BK0_REVOLUTION_SPEC>;
    #[doc = "Monitor of the just received input revolution for tracing logic"]
    pub mod bk0_revolution {
        #[doc = "Register `BK0_REVOLUTION` reader"]
        pub type R = crate::R<BK0_REVOLUTION_SPEC>;
        #[doc = "Register `BK0_REVOLUTION` writer"]
        pub type W = crate::W<BK0_REVOLUTION_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the just received input revolution for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_revolution::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_revolution::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK0_REVOLUTION_SPEC;
        impl crate::RegisterSpec for BK0_REVOLUTION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk0_revolution::R`](R) reader structure"]
        impl crate::Readable for BK0_REVOLUTION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk0_revolution::W`](W) writer structure"]
        impl crate::Writable for BK0_REVOLUTION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK0_REVOLUTION to value 0"]
        impl crate::Resettable for BK0_REVOLUTION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK0_SPEED (rw) register accessor: Monitor of the just received input speed for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk0_speed`]
module"]
    pub type BK0_SPEED = crate::Reg<bk0_speed::BK0_SPEED_SPEC>;
    #[doc = "Monitor of the just received input speed for tracing logic"]
    pub mod bk0_speed {
        #[doc = "Register `BK0_SPEED` reader"]
        pub type R = crate::R<BK0_SPEED_SPEC>;
        #[doc = "Register `BK0_SPEED` writer"]
        pub type W = crate::W<BK0_SPEED_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the just received input speed for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK0_SPEED_SPEC;
        impl crate::RegisterSpec for BK0_SPEED_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk0_speed::R`](R) reader structure"]
        impl crate::Readable for BK0_SPEED_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk0_speed::W`](W) writer structure"]
        impl crate::Writable for BK0_SPEED_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK0_SPEED to value 0"]
        impl crate::Resettable for BK0_SPEED_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK0_ACCELERATOR (rw) register accessor: Monitor of the just received input acceleration for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_accelerator::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_accelerator::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk0_accelerator`]
module"]
    pub type BK0_ACCELERATOR = crate::Reg<bk0_accelerator::BK0_ACCELERATOR_SPEC>;
    #[doc = "Monitor of the just received input acceleration for tracing logic"]
    pub mod bk0_accelerator {
        #[doc = "Register `BK0_ACCELERATOR` reader"]
        pub type R = crate::R<BK0_ACCELERATOR_SPEC>;
        #[doc = "Register `BK0_ACCELERATOR` writer"]
        pub type W = crate::W<BK0_ACCELERATOR_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the just received input acceleration for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk0_accelerator::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk0_accelerator::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK0_ACCELERATOR_SPEC;
        impl crate::RegisterSpec for BK0_ACCELERATOR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk0_accelerator::R`](R) reader structure"]
        impl crate::Readable for BK0_ACCELERATOR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk0_accelerator::W`](W) writer structure"]
        impl crate::Writable for BK0_ACCELERATOR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK0_ACCELERATOR to value 0"]
        impl crate::Resettable for BK0_ACCELERATOR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK1_TIMESTAMP (rw) register accessor: Monitor of the previous received input timestamp for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_timestamp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_timestamp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk1_timestamp`]
module"]
    pub type BK1_TIMESTAMP = crate::Reg<bk1_timestamp::BK1_TIMESTAMP_SPEC>;
    #[doc = "Monitor of the previous received input timestamp for tracing logic"]
    pub mod bk1_timestamp {
        #[doc = "Register `BK1_TIMESTAMP` reader"]
        pub type R = crate::R<BK1_TIMESTAMP_SPEC>;
        #[doc = "Register `BK1_TIMESTAMP` writer"]
        pub type W = crate::W<BK1_TIMESTAMP_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the previous received input timestamp for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_timestamp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_timestamp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK1_TIMESTAMP_SPEC;
        impl crate::RegisterSpec for BK1_TIMESTAMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk1_timestamp::R`](R) reader structure"]
        impl crate::Readable for BK1_TIMESTAMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk1_timestamp::W`](W) writer structure"]
        impl crate::Writable for BK1_TIMESTAMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK1_TIMESTAMP to value 0"]
        impl crate::Resettable for BK1_TIMESTAMP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK1_POSITION (rw) register accessor: Monitor of the previous received input position for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_position::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_position::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk1_position`]
module"]
    pub type BK1_POSITION = crate::Reg<bk1_position::BK1_POSITION_SPEC>;
    #[doc = "Monitor of the previous received input position for tracing logic"]
    pub mod bk1_position {
        #[doc = "Register `BK1_POSITION` reader"]
        pub type R = crate::R<BK1_POSITION_SPEC>;
        #[doc = "Register `BK1_POSITION` writer"]
        pub type W = crate::W<BK1_POSITION_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the previous received input position for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_position::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_position::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK1_POSITION_SPEC;
        impl crate::RegisterSpec for BK1_POSITION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk1_position::R`](R) reader structure"]
        impl crate::Readable for BK1_POSITION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk1_position::W`](W) writer structure"]
        impl crate::Writable for BK1_POSITION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK1_POSITION to value 0"]
        impl crate::Resettable for BK1_POSITION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK1_REVOLUTION (rw) register accessor: Monitor of the previous received input revolution for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_revolution::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_revolution::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk1_revolution`]
module"]
    pub type BK1_REVOLUTION = crate::Reg<bk1_revolution::BK1_REVOLUTION_SPEC>;
    #[doc = "Monitor of the previous received input revolution for tracing logic"]
    pub mod bk1_revolution {
        #[doc = "Register `BK1_REVOLUTION` reader"]
        pub type R = crate::R<BK1_REVOLUTION_SPEC>;
        #[doc = "Register `BK1_REVOLUTION` writer"]
        pub type W = crate::W<BK1_REVOLUTION_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the previous received input revolution for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_revolution::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_revolution::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK1_REVOLUTION_SPEC;
        impl crate::RegisterSpec for BK1_REVOLUTION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk1_revolution::R`](R) reader structure"]
        impl crate::Readable for BK1_REVOLUTION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk1_revolution::W`](W) writer structure"]
        impl crate::Writable for BK1_REVOLUTION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK1_REVOLUTION to value 0"]
        impl crate::Resettable for BK1_REVOLUTION_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK1_SPEED (rw) register accessor: Monitor of the previous received input speed for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_speed::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_speed::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk1_speed`]
module"]
    pub type BK1_SPEED = crate::Reg<bk1_speed::BK1_SPEED_SPEC>;
    #[doc = "Monitor of the previous received input speed for tracing logic"]
    pub mod bk1_speed {
        #[doc = "Register `BK1_SPEED` reader"]
        pub type R = crate::R<BK1_SPEED_SPEC>;
        #[doc = "Register `BK1_SPEED` writer"]
        pub type W = crate::W<BK1_SPEED_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the previous received input speed for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_speed::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_speed::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK1_SPEED_SPEC;
        impl crate::RegisterSpec for BK1_SPEED_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk1_speed::R`](R) reader structure"]
        impl crate::Readable for BK1_SPEED_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk1_speed::W`](W) writer structure"]
        impl crate::Writable for BK1_SPEED_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK1_SPEED to value 0"]
        impl crate::Resettable for BK1_SPEED_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BK1_ACCELERATOR (rw) register accessor: Monitor of the previous received input acceleration for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_accelerator::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_accelerator::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bk1_accelerator`]
module"]
    pub type BK1_ACCELERATOR = crate::Reg<bk1_accelerator::BK1_ACCELERATOR_SPEC>;
    #[doc = "Monitor of the previous received input acceleration for tracing logic"]
    pub mod bk1_accelerator {
        #[doc = "Register `BK1_ACCELERATOR` reader"]
        pub type R = crate::R<BK1_ACCELERATOR_SPEC>;
        #[doc = "Register `BK1_ACCELERATOR` writer"]
        pub type W = crate::W<BK1_ACCELERATOR_SPEC>;
        #[doc = "Field `VAL` reader - the value"]
        pub type VAL_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - the value"]
            #[inline(always)]
            pub fn val(&self) -> VAL_R {
                VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Monitor of the previous received input acceleration for tracing logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bk1_accelerator::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bk1_accelerator::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BK1_ACCELERATOR_SPEC;
        impl crate::RegisterSpec for BK1_ACCELERATOR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bk1_accelerator::R`](R) reader structure"]
        impl crate::Readable for BK1_ACCELERATOR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bk1_accelerator::W`](W) writer structure"]
        impl crate::Writable for BK1_ACCELERATOR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BK1_ACCELERATOR to value 0"]
        impl crate::Resettable for BK1_ACCELERATOR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "MMC1"]
pub struct MMC1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MMC1 {}
impl MMC1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mmc0::RegisterBlock = 0xf031_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mmc0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MMC1 {
    type Target = mmc0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MMC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MMC1").finish()
    }
}
#[doc = "MMC1"]
pub use self::mmc0 as mmc1;
#[doc = "PWM0"]
pub struct PWM0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PWM0 {}
impl PWM0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const pwm0::RegisterBlock = 0xf031_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const pwm0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PWM0 {
    type Target = pwm0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PWM0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWM0").finish()
    }
}
#[doc = "PWM0"]
pub mod pwm0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        unlk: UNLK,
        sta: STA,
        rld: RLD,
        cmp: [CMP; 24],
        _reserved4: [u8; 0x0c],
        frcmd: FRCMD,
        shlk: SHLK,
        chcfg: [CHCFG; 24],
        _reserved7: [u8; 0x10],
        gcr: GCR,
        shcr: SHCR,
        _reserved9: [u8; 0x08],
        cappos: [CAPPOS; 24],
        _reserved10: [u8; 0x10],
        cnt: CNT,
        _reserved11: [u8; 0x0c],
        capneg: [CAPNEG; 24],
        _reserved12: [u8; 0x10],
        cntcopy: CNTCOPY,
        _reserved13: [u8; 0x0c],
        pwmcfg: [PWMCFG; 8],
        sr: SR,
        irqen: IRQEN,
        _reserved16: [u8; 0x04],
        dmaen: DMAEN,
        cmpcfg: [CMPCFG; 24],
    }
    impl RegisterBlock {
        #[doc = "0x00 - Shadow registers unlock register"]
        #[inline(always)]
        pub const fn unlk(&self) -> &UNLK {
            &self.unlk
        }
        #[doc = "0x04 - Counter start register"]
        #[inline(always)]
        pub const fn sta(&self) -> &STA {
            &self.sta
        }
        #[doc = "0x08 - Counter reload register"]
        #[inline(always)]
        pub const fn rld(&self) -> &RLD {
            &self.rld
        }
        #[doc = "0x0c..0x6c - no description available"]
        #[inline(always)]
        pub const fn cmp(&self, n: usize) -> &CMP {
            &self.cmp[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x0c..0x6c - no description available"]
        #[inline(always)]
        pub fn cmp_iter(&self) -> impl Iterator<Item = &CMP> {
            self.cmp.iter()
        }
        #[doc = "0x78 - Force output mode register"]
        #[inline(always)]
        pub const fn frcmd(&self) -> &FRCMD {
            &self.frcmd
        }
        #[doc = "0x7c - Shadow registers lock register"]
        #[inline(always)]
        pub const fn shlk(&self) -> &SHLK {
            &self.shlk
        }
        #[doc = "0x80..0xe0 - no description available"]
        #[inline(always)]
        pub const fn chcfg(&self, n: usize) -> &CHCFG {
            &self.chcfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x80..0xe0 - no description available"]
        #[inline(always)]
        pub fn chcfg_iter(&self) -> impl Iterator<Item = &CHCFG> {
            self.chcfg.iter()
        }
        #[doc = "0xf0 - Global control register"]
        #[inline(always)]
        pub const fn gcr(&self) -> &GCR {
            &self.gcr
        }
        #[doc = "0xf4 - Shadow register control register"]
        #[inline(always)]
        pub const fn shcr(&self) -> &SHCR {
            &self.shcr
        }
        #[doc = "0x100..0x160 - no description available"]
        #[inline(always)]
        pub const fn cappos(&self, n: usize) -> &CAPPOS {
            &self.cappos[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x100..0x160 - no description available"]
        #[inline(always)]
        pub fn cappos_iter(&self) -> impl Iterator<Item = &CAPPOS> {
            self.cappos.iter()
        }
        #[doc = "0x170 - Counter"]
        #[inline(always)]
        pub const fn cnt(&self) -> &CNT {
            &self.cnt
        }
        #[doc = "0x180..0x1e0 - no description available"]
        #[inline(always)]
        pub const fn capneg(&self, n: usize) -> &CAPNEG {
            &self.capneg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x180..0x1e0 - no description available"]
        #[inline(always)]
        pub fn capneg_iter(&self) -> impl Iterator<Item = &CAPNEG> {
            self.capneg.iter()
        }
        #[doc = "0x1f0 - Counter copy"]
        #[inline(always)]
        pub const fn cntcopy(&self) -> &CNTCOPY {
            &self.cntcopy
        }
        #[doc = "0x200..0x220 - no description available"]
        #[inline(always)]
        pub const fn pwmcfg(&self, n: usize) -> &PWMCFG {
            &self.pwmcfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x200..0x220 - no description available"]
        #[inline(always)]
        pub fn pwmcfg_iter(&self) -> impl Iterator<Item = &PWMCFG> {
            self.pwmcfg.iter()
        }
        #[doc = "0x220 - Status register"]
        #[inline(always)]
        pub const fn sr(&self) -> &SR {
            &self.sr
        }
        #[doc = "0x224 - Interrupt request enable register"]
        #[inline(always)]
        pub const fn irqen(&self) -> &IRQEN {
            &self.irqen
        }
        #[doc = "0x22c - DMA request enable register"]
        #[inline(always)]
        pub const fn dmaen(&self) -> &DMAEN {
            &self.dmaen
        }
        #[doc = "0x230..0x290 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg(&self, n: usize) -> &CMPCFG {
            &self.cmpcfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x230..0x290 - no description available"]
        #[inline(always)]
        pub fn cmpcfg_iter(&self) -> impl Iterator<Item = &CMPCFG> {
            self.cmpcfg.iter()
        }
        #[doc = "0x230 - no description available"]
        #[inline(always)]
        pub const fn cmpcfgcmpcfg0(&self) -> &CMPCFG {
            self.cmpcfg(0)
        }
        #[doc = "0x234 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg1(&self) -> &CMPCFG {
            self.cmpcfg(1)
        }
        #[doc = "0x238 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg2(&self) -> &CMPCFG {
            self.cmpcfg(2)
        }
        #[doc = "0x23c - no description available"]
        #[inline(always)]
        pub const fn cmpcfg3(&self) -> &CMPCFG {
            self.cmpcfg(3)
        }
        #[doc = "0x240 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg4(&self) -> &CMPCFG {
            self.cmpcfg(4)
        }
        #[doc = "0x244 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg5(&self) -> &CMPCFG {
            self.cmpcfg(5)
        }
        #[doc = "0x248 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg6(&self) -> &CMPCFG {
            self.cmpcfg(6)
        }
        #[doc = "0x24c - no description available"]
        #[inline(always)]
        pub const fn cmpcfg7(&self) -> &CMPCFG {
            self.cmpcfg(7)
        }
        #[doc = "0x250 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg8(&self) -> &CMPCFG {
            self.cmpcfg(8)
        }
        #[doc = "0x254 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg9(&self) -> &CMPCFG {
            self.cmpcfg(9)
        }
        #[doc = "0x258 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg10(&self) -> &CMPCFG {
            self.cmpcfg(10)
        }
        #[doc = "0x25c - no description available"]
        #[inline(always)]
        pub const fn cmpcfg11(&self) -> &CMPCFG {
            self.cmpcfg(11)
        }
        #[doc = "0x260 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg12(&self) -> &CMPCFG {
            self.cmpcfg(12)
        }
        #[doc = "0x264 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg13(&self) -> &CMPCFG {
            self.cmpcfg(13)
        }
        #[doc = "0x268 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg14(&self) -> &CMPCFG {
            self.cmpcfg(14)
        }
        #[doc = "0x26c - no description available"]
        #[inline(always)]
        pub const fn cmpcfg15(&self) -> &CMPCFG {
            self.cmpcfg(15)
        }
        #[doc = "0x270 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg16(&self) -> &CMPCFG {
            self.cmpcfg(16)
        }
        #[doc = "0x274 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg17(&self) -> &CMPCFG {
            self.cmpcfg(17)
        }
        #[doc = "0x278 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg18(&self) -> &CMPCFG {
            self.cmpcfg(18)
        }
        #[doc = "0x27c - no description available"]
        #[inline(always)]
        pub const fn cmpcfg19(&self) -> &CMPCFG {
            self.cmpcfg(19)
        }
        #[doc = "0x280 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg20(&self) -> &CMPCFG {
            self.cmpcfg(20)
        }
        #[doc = "0x284 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg21(&self) -> &CMPCFG {
            self.cmpcfg(21)
        }
        #[doc = "0x288 - no description available"]
        #[inline(always)]
        pub const fn cmpcfg22(&self) -> &CMPCFG {
            self.cmpcfg(22)
        }
        #[doc = "0x28c - no description available"]
        #[inline(always)]
        pub const fn cmpcfg23(&self) -> &CMPCFG {
            self.cmpcfg(23)
        }
    }
    #[doc = "unlk (rw) register accessor: Shadow registers unlock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unlk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unlk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unlk`]
module"]
    pub type UNLK = crate::Reg<unlk::UNLK_SPEC>;
    #[doc = "Shadow registers unlock register"]
    pub mod unlk {
        #[doc = "Register `unlk` reader"]
        pub type R = crate::R<UNLK_SPEC>;
        #[doc = "Register `unlk` writer"]
        pub type W = crate::W<UNLK_SPEC>;
        #[doc = "Field `SHUNLK` reader - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written."]
        pub type SHUNLK_R = crate::FieldReader<u32>;
        #[doc = "Field `SHUNLK` writer - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written."]
        pub type SHUNLK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written."]
            #[inline(always)]
            pub fn shunlk(&self) -> SHUNLK_R {
                SHUNLK_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, otherwise the shadow registers can not be written."]
            #[inline(always)]
            #[must_use]
            pub fn shunlk(&mut self) -> SHUNLK_W<UNLK_SPEC> {
                SHUNLK_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Shadow registers unlock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unlk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unlk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UNLK_SPEC;
        impl crate::RegisterSpec for UNLK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`unlk::R`](R) reader structure"]
        impl crate::Readable for UNLK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`unlk::W`](W) writer structure"]
        impl crate::Writable for UNLK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets unlk to value 0"]
        impl crate::Resettable for UNLK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sta (rw) register accessor: Counter start register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sta`]
module"]
    pub type STA = crate::Reg<sta::STA_SPEC>;
    #[doc = "Counter start register"]
    pub mod sta {
        #[doc = "Register `sta` reader"]
        pub type R = crate::R<STA_SPEC>;
        #[doc = "Register `sta` writer"]
        pub type W = crate::W<STA_SPEC>;
        #[doc = "Field `STA` reader - pwm timer counter start value sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk"]
        pub type STA_R = crate::FieldReader<u32>;
        #[doc = "Field `STA` writer - pwm timer counter start value sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk"]
        pub type STA_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        #[doc = "Field `XSTA` reader - pwm timer counter extended start point, should back to this value after reach xrld"]
        pub type XSTA_R = crate::FieldReader;
        #[doc = "Field `XSTA` writer - pwm timer counter extended start point, should back to this value after reach xrld"]
        pub type XSTA_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 4:27 - pwm timer counter start value sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk"]
            #[inline(always)]
            pub fn sta(&self) -> STA_R {
                STA_R::new((self.bits >> 4) & 0x00ff_ffff)
            }
            #[doc = "Bits 28:31 - pwm timer counter extended start point, should back to this value after reach xrld"]
            #[inline(always)]
            pub fn xsta(&self) -> XSTA_R {
                XSTA_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 4:27 - pwm timer counter start value sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk"]
            #[inline(always)]
            #[must_use]
            pub fn sta(&mut self) -> STA_W<STA_SPEC> {
                STA_W::new(self, 4)
            }
            #[doc = "Bits 28:31 - pwm timer counter extended start point, should back to this value after reach xrld"]
            #[inline(always)]
            #[must_use]
            pub fn xsta(&mut self) -> XSTA_W<STA_SPEC> {
                XSTA_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Counter start register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STA_SPEC;
        impl crate::RegisterSpec for STA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sta::R`](R) reader structure"]
        impl crate::Readable for STA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sta::W`](W) writer structure"]
        impl crate::Writable for STA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sta to value 0"]
        impl crate::Resettable for STA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "rld (rw) register accessor: Counter reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rld::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rld::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rld`]
module"]
    pub type RLD = crate::Reg<rld::RLD_SPEC>;
    #[doc = "Counter reload register"]
    pub mod rld {
        #[doc = "Register `rld` reader"]
        pub type R = crate::R<RLD_SPEC>;
        #[doc = "Register `rld` writer"]
        pub type W = crate::W<RLD_SPEC>;
        #[doc = "Field `RLD` reader - pwm timer counter reload value"]
        pub type RLD_R = crate::FieldReader<u32>;
        #[doc = "Field `RLD` writer - pwm timer counter reload value"]
        pub type RLD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        #[doc = "Field `XRLD` reader - timeout counter extended reload point, counter will reload to xsta after reach this point"]
        pub type XRLD_R = crate::FieldReader;
        #[doc = "Field `XRLD` writer - timeout counter extended reload point, counter will reload to xsta after reach this point"]
        pub type XRLD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 4:27 - pwm timer counter reload value"]
            #[inline(always)]
            pub fn rld(&self) -> RLD_R {
                RLD_R::new((self.bits >> 4) & 0x00ff_ffff)
            }
            #[doc = "Bits 28:31 - timeout counter extended reload point, counter will reload to xsta after reach this point"]
            #[inline(always)]
            pub fn xrld(&self) -> XRLD_R {
                XRLD_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 4:27 - pwm timer counter reload value"]
            #[inline(always)]
            #[must_use]
            pub fn rld(&mut self) -> RLD_W<RLD_SPEC> {
                RLD_W::new(self, 4)
            }
            #[doc = "Bits 28:31 - timeout counter extended reload point, counter will reload to xsta after reach this point"]
            #[inline(always)]
            #[must_use]
            pub fn xrld(&mut self) -> XRLD_W<RLD_SPEC> {
                XRLD_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Counter reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rld::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rld::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RLD_SPEC;
        impl crate::RegisterSpec for RLD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rld::R`](R) reader structure"]
        impl crate::Readable for RLD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rld::W`](W) writer structure"]
        impl crate::Writable for RLD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets rld to value 0"]
        impl crate::Resettable for RLD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CMP (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp`]
module"]
    pub type CMP = crate::Reg<cmp::CMP_SPEC>;
    #[doc = "no description available"]
    pub mod cmp {
        #[doc = "Register `CMP[%s]` reader"]
        pub type R = crate::R<CMP_SPEC>;
        #[doc = "Register `CMP[%s]` writer"]
        pub type W = crate::W<CMP_SPEC>;
        #[doc = "Field `CMPJIT` reader - jitter counter compare value"]
        pub type CMPJIT_R = crate::FieldReader;
        #[doc = "Field `CMPJIT` writer - jitter counter compare value"]
        pub type CMPJIT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `CMPHLF` reader - half clock counter compare value"]
        pub type CMPHLF_R = crate::BitReader;
        #[doc = "Field `CMPHLF` writer - half clock counter compare value"]
        pub type CMPHLF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CMP` reader - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity."]
        pub type CMP_R = crate::FieldReader<u32>;
        #[doc = "Field `CMP` writer - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity."]
        pub type CMP_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        #[doc = "Field `XCMP` reader - extended counter compare value"]
        pub type XCMP_R = crate::FieldReader;
        #[doc = "Field `XCMP` writer - extended counter compare value"]
        pub type XCMP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:2 - jitter counter compare value"]
            #[inline(always)]
            pub fn cmpjit(&self) -> CMPJIT_R {
                CMPJIT_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 3 - half clock counter compare value"]
            #[inline(always)]
            pub fn cmphlf(&self) -> CMPHLF_R {
                CMPHLF_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 4:27 - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity."]
            #[inline(always)]
            pub fn cmp(&self) -> CMP_R {
                CMP_R::new((self.bits >> 4) & 0x00ff_ffff)
            }
            #[doc = "Bits 28:31 - extended counter compare value"]
            #[inline(always)]
            pub fn xcmp(&self) -> XCMP_R {
                XCMP_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - jitter counter compare value"]
            #[inline(always)]
            #[must_use]
            pub fn cmpjit(&mut self) -> CMPJIT_W<CMP_SPEC> {
                CMPJIT_W::new(self, 0)
            }
            #[doc = "Bit 3 - half clock counter compare value"]
            #[inline(always)]
            #[must_use]
            pub fn cmphlf(&mut self) -> CMPHLF_W<CMP_SPEC> {
                CMPHLF_W::new(self, 3)
            }
            #[doc = "Bits 4:27 - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity."]
            #[inline(always)]
            #[must_use]
            pub fn cmp(&mut self) -> CMP_W<CMP_SPEC> {
                CMP_W::new(self, 4)
            }
            #[doc = "Bits 28:31 - extended counter compare value"]
            #[inline(always)]
            #[must_use]
            pub fn xcmp(&mut self) -> XCMP_W<CMP_SPEC> {
                XCMP_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMP_SPEC;
        impl crate::RegisterSpec for CMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmp::R`](R) reader structure"]
        impl crate::Readable for CMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmp::W`](W) writer structure"]
        impl crate::Writable for CMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CMP[%s]
to value 0"]
        impl crate::Resettable for CMP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "frcmd (rw) register accessor: Force output mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frcmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frcmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frcmd`]
module"]
    pub type FRCMD = crate::Reg<frcmd::FRCMD_SPEC>;
    #[doc = "Force output mode register"]
    pub mod frcmd {
        #[doc = "Register `frcmd` reader"]
        pub type R = crate::R<FRCMD_SPEC>;
        #[doc = "Register `frcmd` writer"]
        pub type W = crate::W<FRCMD_SPEC>;
        #[doc = "Field `FRCMD` reader - 2bit for each PWM output channel (0-7); 00: force output 0 01: force output 1 10: output highz 11: no force"]
        pub type FRCMD_R = crate::FieldReader<u16>;
        #[doc = "Field `FRCMD` writer - 2bit for each PWM output channel (0-7); 00: force output 0 01: force output 1 10: output highz 11: no force"]
        pub type FRCMD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - 2bit for each PWM output channel (0-7); 00: force output 0 01: force output 1 10: output highz 11: no force"]
            #[inline(always)]
            pub fn frcmd(&self) -> FRCMD_R {
                FRCMD_R::new((self.bits & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - 2bit for each PWM output channel (0-7); 00: force output 0 01: force output 1 10: output highz 11: no force"]
            #[inline(always)]
            #[must_use]
            pub fn frcmd(&mut self) -> FRCMD_W<FRCMD_SPEC> {
                FRCMD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Force output mode register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frcmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frcmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FRCMD_SPEC;
        impl crate::RegisterSpec for FRCMD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`frcmd::R`](R) reader structure"]
        impl crate::Readable for FRCMD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`frcmd::W`](W) writer structure"]
        impl crate::Writable for FRCMD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets frcmd to value 0"]
        impl crate::Resettable for FRCMD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "shlk (rw) register accessor: Shadow registers lock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shlk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shlk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shlk`]
module"]
    pub type SHLK = crate::Reg<shlk::SHLK_SPEC>;
    #[doc = "Shadow registers lock register"]
    pub mod shlk {
        #[doc = "Register `shlk` reader"]
        pub type R = crate::R<SHLK_SPEC>;
        #[doc = "Register `shlk` writer"]
        pub type W = crate::W<SHLK_SPEC>;
        #[doc = "Field `SHLK` reader - write 1 to lock all shawdow register, wirte access is not permitted"]
        pub type SHLK_R = crate::BitReader;
        #[doc = "Field `SHLK` writer - write 1 to lock all shawdow register, wirte access is not permitted"]
        pub type SHLK_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 31 - write 1 to lock all shawdow register, wirte access is not permitted"]
            #[inline(always)]
            pub fn shlk(&self) -> SHLK_R {
                SHLK_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 31 - write 1 to lock all shawdow register, wirte access is not permitted"]
            #[inline(always)]
            #[must_use]
            pub fn shlk(&mut self) -> SHLK_W<SHLK_SPEC> {
                SHLK_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Shadow registers lock register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shlk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shlk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SHLK_SPEC;
        impl crate::RegisterSpec for SHLK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`shlk::R`](R) reader structure"]
        impl crate::Readable for SHLK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`shlk::W`](W) writer structure"]
        impl crate::Writable for SHLK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets shlk to value 0"]
        impl crate::Resettable for SHLK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CHCFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chcfg`]
module"]
    pub type CHCFG = crate::Reg<chcfg::CHCFG_SPEC>;
    #[doc = "no description available"]
    pub mod chcfg {
        #[doc = "Register `CHCFG[%s]` reader"]
        pub type R = crate::R<CHCFG_SPEC>;
        #[doc = "Register `CHCFG[%s]` writer"]
        pub type W = crate::W<CHCFG_SPEC>;
        #[doc = "Field `OUTPOL` reader - output polarity, set to 1 will invert the output"]
        pub type OUTPOL_R = crate::BitReader;
        #[doc = "Field `OUTPOL` writer - output polarity, set to 1 will invert the output"]
        pub type OUTPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CMPSELBEG` reader - assign the first comparator for this output channel"]
        pub type CMPSELBEG_R = crate::FieldReader;
        #[doc = "Field `CMPSELBEG` writer - assign the first comparator for this output channel"]
        pub type CMPSELBEG_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `CMPSELEND` reader - assign the last comparator for this output channel"]
        pub type CMPSELEND_R = crate::FieldReader;
        #[doc = "Field `CMPSELEND` writer - assign the last comparator for this output channel"]
        pub type CMPSELEND_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bit 1 - output polarity, set to 1 will invert the output"]
            #[inline(always)]
            pub fn outpol(&self) -> OUTPOL_R {
                OUTPOL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 16:20 - assign the first comparator for this output channel"]
            #[inline(always)]
            pub fn cmpselbeg(&self) -> CMPSELBEG_R {
                CMPSELBEG_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bits 24:28 - assign the last comparator for this output channel"]
            #[inline(always)]
            pub fn cmpselend(&self) -> CMPSELEND_R {
                CMPSELEND_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 1 - output polarity, set to 1 will invert the output"]
            #[inline(always)]
            #[must_use]
            pub fn outpol(&mut self) -> OUTPOL_W<CHCFG_SPEC> {
                OUTPOL_W::new(self, 1)
            }
            #[doc = "Bits 16:20 - assign the first comparator for this output channel"]
            #[inline(always)]
            #[must_use]
            pub fn cmpselbeg(&mut self) -> CMPSELBEG_W<CHCFG_SPEC> {
                CMPSELBEG_W::new(self, 16)
            }
            #[doc = "Bits 24:28 - assign the last comparator for this output channel"]
            #[inline(always)]
            #[must_use]
            pub fn cmpselend(&mut self) -> CMPSELEND_W<CHCFG_SPEC> {
                CMPSELEND_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CHCFG_SPEC;
        impl crate::RegisterSpec for CHCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`chcfg::R`](R) reader structure"]
        impl crate::Readable for CHCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`chcfg::W`](W) writer structure"]
        impl crate::Writable for CHCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CHCFG[%s]
to value 0"]
        impl crate::Resettable for CHCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "gcr (rw) register accessor: Global control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr`]
module"]
    pub type GCR = crate::Reg<gcr::GCR_SPEC>;
    #[doc = "Global control register"]
    pub mod gcr {
        #[doc = "Register `gcr` reader"]
        pub type R = crate::R<GCR_SPEC>;
        #[doc = "Register `gcr` writer"]
        pub type W = crate::W<GCR_SPEC>;
        #[doc = "Field `SWFRC` reader - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect"]
        pub type SWFRC_R = crate::BitReader;
        #[doc = "Field `SWFRC` writer - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect"]
        pub type SWFRC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FRCTIME` writer - This bit field select the force effective time 00: force immediately 01: force at main counter reload time 10: force at FRCSYNCI 11: no force"]
        pub type FRCTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TIMERRESET` reader - set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear"]
        pub type TIMERRESET_R = crate::BitReader;
        #[doc = "Field `TIMERRESET` writer - set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear"]
        pub type TIMERRESET_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `XRLDSYNCEN` reader - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled"]
        pub type XRLDSYNCEN_R = crate::BitReader;
        #[doc = "Field `XRLDSYNCEN` writer - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled"]
        pub type XRLDSYNCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTCLR` reader - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again."]
        pub type FAULTCLR_R = crate::BitReader;
        #[doc = "Field `FAULTCLR` writer - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again."]
        pub type FAULTCLR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CEN` reader - 1- enable the pwm timer counter 0- stop the pwm timer counter"]
        pub type CEN_R = crate::BitReader;
        #[doc = "Field `CEN` writer - 1- enable the pwm timer counter 0- stop the pwm timer counter"]
        pub type CEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RLDSYNCEN` reader - 1- pwm timer counter reset to reload value (rld) by synci is enabled"]
        pub type RLDSYNCEN_R = crate::BitReader;
        #[doc = "Field `RLDSYNCEN` writer - 1- pwm timer counter reset to reload value (rld) by synci is enabled"]
        pub type RLDSYNCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTEXPOL` reader - external fault polarity 1-active low 0-active high"]
        pub type FAULTEXPOL_R = crate::FieldReader;
        #[doc = "Field `FAULTEXPOL` writer - external fault polarity 1-active low 0-active high"]
        pub type FAULTEXPOL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `FAULTE0EN` reader - 1- enable the external fault input 0"]
        pub type FAULTE0EN_R = crate::BitReader;
        #[doc = "Field `FAULTE0EN` writer - 1- enable the external fault input 0"]
        pub type FAULTE0EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTE1EN` reader - 1- enable the external fault input 1"]
        pub type FAULTE1EN_R = crate::BitReader;
        #[doc = "Field `FAULTE1EN` writer - 1- enable the external fault input 1"]
        pub type FAULTE1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTRECHWSEL` reader - Selec one of the 24 comparators as fault output recover trigger."]
        pub type FAULTRECHWSEL_R = crate::FieldReader;
        #[doc = "Field `FAULTRECHWSEL` writer - Selec one of the 24 comparators as fault output recover trigger."]
        pub type FAULTRECHWSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `FAULTRECEDG` reader - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. 1- Falling edge 0- Rising edge"]
        pub type FAULTRECEDG_R = crate::BitReader;
        #[doc = "Field `FAULTRECEDG` writer - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. 1- Falling edge 0- Rising edge"]
        pub type FAULTRECEDG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CMPSHDWSEL` reader - This bitfield select one of the comparators as hardware event time to load comparator shadow registers"]
        pub type CMPSHDWSEL_R = crate::FieldReader;
        #[doc = "Field `CMPSHDWSEL` writer - This bitfield select one of the comparators as hardware event time to load comparator shadow registers"]
        pub type CMPSHDWSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `HWSHDWEDG` reader - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as compare shadow register hardware load event. 1- Falling edge 0- Rising edge"]
        pub type HWSHDWEDG_R = crate::BitReader;
        #[doc = "Field `HWSHDWEDG` writer - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as compare shadow register hardware load event. 1- Falling edge 0- Rising edge"]
        pub type HWSHDWEDG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FRCPOL` reader - polarity of input pwm_force, 1- active low 0- active high"]
        pub type FRCPOL_R = crate::BitReader;
        #[doc = "Field `FRCPOL` writer - polarity of input pwm_force, 1- active low 0- active high"]
        pub type FRCPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DEBUGFAULT` reader - 1- enable debug mode output protection"]
        pub type DEBUGFAULT_R = crate::BitReader;
        #[doc = "Field `DEBUGFAULT` writer - 1- enable debug mode output protection"]
        pub type DEBUGFAULT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTI0EN` reader - 1- enable the internal fault input 0"]
        pub type FAULTI0EN_R = crate::BitReader;
        #[doc = "Field `FAULTI0EN` writer - 1- enable the internal fault input 0"]
        pub type FAULTI0EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTI1EN` reader - 1- enable the internal fault input 1"]
        pub type FAULTI1EN_R = crate::BitReader;
        #[doc = "Field `FAULTI1EN` writer - 1- enable the internal fault input 1"]
        pub type FAULTI1EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTI2EN` reader - 1- enable the internal fault input 2"]
        pub type FAULTI2EN_R = crate::BitReader;
        #[doc = "Field `FAULTI2EN` writer - 1- enable the internal fault input 2"]
        pub type FAULTI2EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTI3EN` reader - 1- enable the internal fault input 3"]
        pub type FAULTI3EN_R = crate::BitReader;
        #[doc = "Field `FAULTI3EN` writer - 1- enable the internal fault input 3"]
        pub type FAULTI3EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect"]
            #[inline(always)]
            pub fn swfrc(&self) -> SWFRC_R {
                SWFRC_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 3 - set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear"]
            #[inline(always)]
            pub fn timerreset(&self) -> TIMERRESET_R {
                TIMERRESET_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 5 - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled"]
            #[inline(always)]
            pub fn xrldsyncen(&self) -> XRLDSYNCEN_R {
                XRLDSYNCEN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again."]
            #[inline(always)]
            pub fn faultclr(&self) -> FAULTCLR_R {
                FAULTCLR_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - 1- enable the pwm timer counter 0- stop the pwm timer counter"]
            #[inline(always)]
            pub fn cen(&self) -> CEN_R {
                CEN_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - 1- pwm timer counter reset to reload value (rld) by synci is enabled"]
            #[inline(always)]
            pub fn rldsyncen(&self) -> RLDSYNCEN_R {
                RLDSYNCEN_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bits 9:10 - external fault polarity 1-active low 0-active high"]
            #[inline(always)]
            pub fn faultexpol(&self) -> FAULTEXPOL_R {
                FAULTEXPOL_R::new(((self.bits >> 9) & 3) as u8)
            }
            #[doc = "Bit 11 - 1- enable the external fault input 0"]
            #[inline(always)]
            pub fn faulte0en(&self) -> FAULTE0EN_R {
                FAULTE0EN_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - 1- enable the external fault input 1"]
            #[inline(always)]
            pub fn faulte1en(&self) -> FAULTE1EN_R {
                FAULTE1EN_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bits 13:17 - Selec one of the 24 comparators as fault output recover trigger."]
            #[inline(always)]
            pub fn faultrechwsel(&self) -> FAULTRECHWSEL_R {
                FAULTRECHWSEL_R::new(((self.bits >> 13) & 0x1f) as u8)
            }
            #[doc = "Bit 18 - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. 1- Falling edge 0- Rising edge"]
            #[inline(always)]
            pub fn faultrecedg(&self) -> FAULTRECEDG_R {
                FAULTRECEDG_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bits 19:23 - This bitfield select one of the comparators as hardware event time to load comparator shadow registers"]
            #[inline(always)]
            pub fn cmpshdwsel(&self) -> CMPSHDWSEL_R {
                CMPSHDWSEL_R::new(((self.bits >> 19) & 0x1f) as u8)
            }
            #[doc = "Bit 24 - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as compare shadow register hardware load event. 1- Falling edge 0- Rising edge"]
            #[inline(always)]
            pub fn hwshdwedg(&self) -> HWSHDWEDG_R {
                HWSHDWEDG_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 26 - polarity of input pwm_force, 1- active low 0- active high"]
            #[inline(always)]
            pub fn frcpol(&self) -> FRCPOL_R {
                FRCPOL_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - 1- enable debug mode output protection"]
            #[inline(always)]
            pub fn debugfault(&self) -> DEBUGFAULT_R {
                DEBUGFAULT_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - 1- enable the internal fault input 0"]
            #[inline(always)]
            pub fn faulti0en(&self) -> FAULTI0EN_R {
                FAULTI0EN_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - 1- enable the internal fault input 1"]
            #[inline(always)]
            pub fn faulti1en(&self) -> FAULTI1EN_R {
                FAULTI1EN_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - 1- enable the internal fault input 2"]
            #[inline(always)]
            pub fn faulti2en(&self) -> FAULTI2EN_R {
                FAULTI2EN_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - 1- enable the internal fault input 3"]
            #[inline(always)]
            pub fn faulti3en(&self) -> FAULTI3EN_R {
                FAULTI3EN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect"]
            #[inline(always)]
            #[must_use]
            pub fn swfrc(&mut self) -> SWFRC_W<GCR_SPEC> {
                SWFRC_W::new(self, 0)
            }
            #[doc = "Bits 1:2 - This bit field select the force effective time 00: force immediately 01: force at main counter reload time 10: force at FRCSYNCI 11: no force"]
            #[inline(always)]
            #[must_use]
            pub fn frctime(&mut self) -> FRCTIME_W<GCR_SPEC> {
                FRCTIME_W::new(self, 1)
            }
            #[doc = "Bit 3 - set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear"]
            #[inline(always)]
            #[must_use]
            pub fn timerreset(&mut self) -> TIMERRESET_W<GCR_SPEC> {
                TIMERRESET_W::new(self, 3)
            }
            #[doc = "Bit 5 - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled"]
            #[inline(always)]
            #[must_use]
            pub fn xrldsyncen(&mut self) -> XRLDSYNCEN_W<GCR_SPEC> {
                XRLDSYNCEN_W::new(self, 5)
            }
            #[doc = "Bit 6 - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again."]
            #[inline(always)]
            #[must_use]
            pub fn faultclr(&mut self) -> FAULTCLR_W<GCR_SPEC> {
                FAULTCLR_W::new(self, 6)
            }
            #[doc = "Bit 7 - 1- enable the pwm timer counter 0- stop the pwm timer counter"]
            #[inline(always)]
            #[must_use]
            pub fn cen(&mut self) -> CEN_W<GCR_SPEC> {
                CEN_W::new(self, 7)
            }
            #[doc = "Bit 8 - 1- pwm timer counter reset to reload value (rld) by synci is enabled"]
            #[inline(always)]
            #[must_use]
            pub fn rldsyncen(&mut self) -> RLDSYNCEN_W<GCR_SPEC> {
                RLDSYNCEN_W::new(self, 8)
            }
            #[doc = "Bits 9:10 - external fault polarity 1-active low 0-active high"]
            #[inline(always)]
            #[must_use]
            pub fn faultexpol(&mut self) -> FAULTEXPOL_W<GCR_SPEC> {
                FAULTEXPOL_W::new(self, 9)
            }
            #[doc = "Bit 11 - 1- enable the external fault input 0"]
            #[inline(always)]
            #[must_use]
            pub fn faulte0en(&mut self) -> FAULTE0EN_W<GCR_SPEC> {
                FAULTE0EN_W::new(self, 11)
            }
            #[doc = "Bit 12 - 1- enable the external fault input 1"]
            #[inline(always)]
            #[must_use]
            pub fn faulte1en(&mut self) -> FAULTE1EN_W<GCR_SPEC> {
                FAULTE1EN_W::new(self, 12)
            }
            #[doc = "Bits 13:17 - Selec one of the 24 comparators as fault output recover trigger."]
            #[inline(always)]
            #[must_use]
            pub fn faultrechwsel(&mut self) -> FAULTRECHWSEL_W<GCR_SPEC> {
                FAULTRECHWSEL_W::new(self, 13)
            }
            #[doc = "Bit 18 - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. This bit assign its effective edge of fault recover trigger. 1- Falling edge 0- Rising edge"]
            #[inline(always)]
            #[must_use]
            pub fn faultrecedg(&mut self) -> FAULTRECEDG_W<GCR_SPEC> {
                FAULTRECEDG_W::new(self, 18)
            }
            #[doc = "Bits 19:23 - This bitfield select one of the comparators as hardware event time to load comparator shadow registers"]
            #[inline(always)]
            #[must_use]
            pub fn cmpshdwsel(&mut self) -> CMPSHDWSEL_W<GCR_SPEC> {
                CMPSHDWSEL_W::new(self, 19)
            }
            #[doc = "Bit 24 - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. This bit assign its which edge is used as compare shadow register hardware load event. 1- Falling edge 0- Rising edge"]
            #[inline(always)]
            #[must_use]
            pub fn hwshdwedg(&mut self) -> HWSHDWEDG_W<GCR_SPEC> {
                HWSHDWEDG_W::new(self, 24)
            }
            #[doc = "Bit 26 - polarity of input pwm_force, 1- active low 0- active high"]
            #[inline(always)]
            #[must_use]
            pub fn frcpol(&mut self) -> FRCPOL_W<GCR_SPEC> {
                FRCPOL_W::new(self, 26)
            }
            #[doc = "Bit 27 - 1- enable debug mode output protection"]
            #[inline(always)]
            #[must_use]
            pub fn debugfault(&mut self) -> DEBUGFAULT_W<GCR_SPEC> {
                DEBUGFAULT_W::new(self, 27)
            }
            #[doc = "Bit 28 - 1- enable the internal fault input 0"]
            #[inline(always)]
            #[must_use]
            pub fn faulti0en(&mut self) -> FAULTI0EN_W<GCR_SPEC> {
                FAULTI0EN_W::new(self, 28)
            }
            #[doc = "Bit 29 - 1- enable the internal fault input 1"]
            #[inline(always)]
            #[must_use]
            pub fn faulti1en(&mut self) -> FAULTI1EN_W<GCR_SPEC> {
                FAULTI1EN_W::new(self, 29)
            }
            #[doc = "Bit 30 - 1- enable the internal fault input 2"]
            #[inline(always)]
            #[must_use]
            pub fn faulti2en(&mut self) -> FAULTI2EN_W<GCR_SPEC> {
                FAULTI2EN_W::new(self, 30)
            }
            #[doc = "Bit 31 - 1- enable the internal fault input 3"]
            #[inline(always)]
            #[must_use]
            pub fn faulti3en(&mut self) -> FAULTI3EN_W<GCR_SPEC> {
                FAULTI3EN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Global control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GCR_SPEC;
        impl crate::RegisterSpec for GCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gcr::R`](R) reader structure"]
        impl crate::Readable for GCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gcr::W`](W) writer structure"]
        impl crate::Writable for GCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets gcr to value 0"]
        impl crate::Resettable for GCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "shcr (rw) register accessor: Shadow register control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shcr`]
module"]
    pub type SHCR = crate::Reg<shcr::SHCR_SPEC>;
    #[doc = "Shadow register control register"]
    pub mod shcr {
        #[doc = "Register `shcr` reader"]
        pub type R = crate::R<SHCR_SPEC>;
        #[doc = "Register `shcr` writer"]
        pub type W = crate::W<SHCR_SPEC>;
        #[doc = "Field `SHLKEN` reader - 1- enable shadow registers lock feature, 0- disable shadow registers lock, shlk bit will always be 0"]
        pub type SHLKEN_R = crate::BitReader;
        #[doc = "Field `SHLKEN` writer - 1- enable shadow registers lock feature, 0- disable shadow registers lock, shlk bit will always be 0"]
        pub type SHLKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CNTSHDWUPT` reader - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
        pub type CNTSHDWUPT_R = crate::FieldReader;
        #[doc = "Field `CNTSHDWUPT` writer - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
        pub type CNTSHDWUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `CNTSHDWSEL` reader - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD)"]
        pub type CNTSHDWSEL_R = crate::FieldReader;
        #[doc = "Field `CNTSHDWSEL` writer - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD)"]
        pub type CNTSHDWSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `FRCSHDWSEL` reader - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers"]
        pub type FRCSHDWSEL_R = crate::FieldReader;
        #[doc = "Field `FRCSHDWSEL` writer - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers"]
        pub type FRCSHDWSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bit 0 - 1- enable shadow registers lock feature, 0- disable shadow registers lock, shlk bit will always be 0"]
            #[inline(always)]
            pub fn shlken(&self) -> SHLKEN_R {
                SHLKEN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 1:2 - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
            #[inline(always)]
            pub fn cntshdwupt(&self) -> CNTSHDWUPT_R {
                CNTSHDWUPT_R::new(((self.bits >> 1) & 3) as u8)
            }
            #[doc = "Bits 3:7 - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD)"]
            #[inline(always)]
            pub fn cntshdwsel(&self) -> CNTSHDWSEL_R {
                CNTSHDWSEL_R::new(((self.bits >> 3) & 0x1f) as u8)
            }
            #[doc = "Bits 8:12 - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers"]
            #[inline(always)]
            pub fn frcshdwsel(&self) -> FRCSHDWSEL_R {
                FRCSHDWSEL_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - 1- enable shadow registers lock feature, 0- disable shadow registers lock, shlk bit will always be 0"]
            #[inline(always)]
            #[must_use]
            pub fn shlken(&mut self) -> SHLKEN_W<SHCR_SPEC> {
                SHLKEN_W::new(self, 0)
            }
            #[doc = "Bits 1:2 - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
            #[inline(always)]
            #[must_use]
            pub fn cntshdwupt(&mut self) -> CNTSHDWUPT_W<SHCR_SPEC> {
                CNTSHDWUPT_W::new(self, 1)
            }
            #[doc = "Bits 3:7 - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD)"]
            #[inline(always)]
            #[must_use]
            pub fn cntshdwsel(&mut self) -> CNTSHDWSEL_W<SHCR_SPEC> {
                CNTSHDWSEL_W::new(self, 3)
            }
            #[doc = "Bits 8:12 - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers"]
            #[inline(always)]
            #[must_use]
            pub fn frcshdwsel(&mut self) -> FRCSHDWSEL_W<SHCR_SPEC> {
                FRCSHDWSEL_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Shadow register control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SHCR_SPEC;
        impl crate::RegisterSpec for SHCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`shcr::R`](R) reader structure"]
        impl crate::Readable for SHCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`shcr::W`](W) writer structure"]
        impl crate::Writable for SHCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets shcr to value 0"]
        impl crate::Resettable for SHCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CAPPOS (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cappos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cappos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cappos`]
module"]
    pub type CAPPOS = crate::Reg<cappos::CAPPOS_SPEC>;
    #[doc = "no description available"]
    pub mod cappos {
        #[doc = "Register `CAPPOS[%s]` reader"]
        pub type R = crate::R<CAPPOS_SPEC>;
        #[doc = "Register `CAPPOS[%s]` writer"]
        pub type W = crate::W<CAPPOS_SPEC>;
        #[doc = "Field `CAPPOS` reader - counter value captured at input posedge"]
        pub type CAPPOS_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 4:31 - counter value captured at input posedge"]
            #[inline(always)]
            pub fn cappos(&self) -> CAPPOS_R {
                CAPPOS_R::new((self.bits >> 4) & 0x0fff_ffff)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cappos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cappos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CAPPOS_SPEC;
        impl crate::RegisterSpec for CAPPOS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cappos::R`](R) reader structure"]
        impl crate::Readable for CAPPOS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cappos::W`](W) writer structure"]
        impl crate::Writable for CAPPOS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CAPPOS[%s]
to value 0"]
        impl crate::Resettable for CAPPOS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cnt (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
    pub type CNT = crate::Reg<cnt::CNT_SPEC>;
    #[doc = "Counter"]
    pub mod cnt {
        #[doc = "Register `cnt` reader"]
        pub type R = crate::R<CNT_SPEC>;
        #[doc = "Register `cnt` writer"]
        pub type W = crate::W<CNT_SPEC>;
        #[doc = "Field `CNT` reader - current clock counter value"]
        pub type CNT_R = crate::FieldReader<u32>;
        #[doc = "Field `XCNT` reader - current extended counter value"]
        pub type XCNT_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 4:27 - current clock counter value"]
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits >> 4) & 0x00ff_ffff)
            }
            #[doc = "Bits 28:31 - current extended counter value"]
            #[inline(always)]
            pub fn xcnt(&self) -> XCNT_R {
                XCNT_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CNT_SPEC;
        impl crate::RegisterSpec for CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
        impl crate::Readable for CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
        impl crate::Writable for CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cnt to value 0"]
        impl crate::Resettable for CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CAPNEG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capneg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capneg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@capneg`]
module"]
    pub type CAPNEG = crate::Reg<capneg::CAPNEG_SPEC>;
    #[doc = "no description available"]
    pub mod capneg {
        #[doc = "Register `CAPNEG[%s]` reader"]
        pub type R = crate::R<CAPNEG_SPEC>;
        #[doc = "Register `CAPNEG[%s]` writer"]
        pub type W = crate::W<CAPNEG_SPEC>;
        #[doc = "Field `CAPNEG` reader - counter value captured at input signal falling edge"]
        pub type CAPNEG_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - counter value captured at input signal falling edge"]
            #[inline(always)]
            pub fn capneg(&self) -> CAPNEG_R {
                CAPNEG_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`capneg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`capneg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CAPNEG_SPEC;
        impl crate::RegisterSpec for CAPNEG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`capneg::R`](R) reader structure"]
        impl crate::Readable for CAPNEG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`capneg::W`](W) writer structure"]
        impl crate::Writable for CAPNEG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CAPNEG[%s]
to value 0"]
        impl crate::Resettable for CAPNEG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cntcopy (rw) register accessor: Counter copy\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntcopy::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntcopy::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cntcopy`]
module"]
    pub type CNTCOPY = crate::Reg<cntcopy::CNTCOPY_SPEC>;
    #[doc = "Counter copy"]
    pub mod cntcopy {
        #[doc = "Register `cntcopy` reader"]
        pub type R = crate::R<CNTCOPY_SPEC>;
        #[doc = "Register `cntcopy` writer"]
        pub type W = crate::W<CNTCOPY_SPEC>;
        #[doc = "Field `CNT` reader - current clock counter value"]
        pub type CNT_R = crate::FieldReader<u32>;
        #[doc = "Field `XCNT` reader - current extended counter value"]
        pub type XCNT_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 4:27 - current clock counter value"]
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new((self.bits >> 4) & 0x00ff_ffff)
            }
            #[doc = "Bits 28:31 - current extended counter value"]
            #[inline(always)]
            pub fn xcnt(&self) -> XCNT_R {
                XCNT_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Counter copy\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cntcopy::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cntcopy::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CNTCOPY_SPEC;
        impl crate::RegisterSpec for CNTCOPY_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cntcopy::R`](R) reader structure"]
        impl crate::Readable for CNTCOPY_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cntcopy::W`](W) writer structure"]
        impl crate::Writable for CNTCOPY_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cntcopy to value 0"]
        impl crate::Resettable for CNTCOPY_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PWMCFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmcfg`]
module"]
    pub type PWMCFG = crate::Reg<pwmcfg::PWMCFG_SPEC>;
    #[doc = "no description available"]
    pub mod pwmcfg {
        #[doc = "Register `PWMCFG[%s]` reader"]
        pub type R = crate::R<PWMCFG_SPEC>;
        #[doc = "Register `PWMCFG[%s]` writer"]
        pub type W = crate::W<PWMCFG_SPEC>;
        #[doc = "Field `DEADAREA` reader - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. Note: user should configure pair bit and this bitfield before PWM output is enabled."]
        pub type DEADAREA_R = crate::FieldReader<u32>;
        #[doc = "Field `DEADAREA` writer - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. Note: user should configure pair bit and this bitfield before PWM output is enabled."]
        pub type DEADAREA_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        #[doc = "Field `PAIR` reader - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. 0- PWM output is in indepandent mode."]
        pub type PAIR_R = crate::BitReader;
        #[doc = "Field `PAIR` writer - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. 0- PWM output is in indepandent mode."]
        pub type PAIR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FRCSRCSEL` reader - Select sources for force output 0- force output is enabled when FRCI assert 1- force output is enabled by software write swfrc to 1"]
        pub type FRCSRCSEL_R = crate::BitReader;
        #[doc = "Field `FRCSRCSEL` writer - Select sources for force output 0- force output is enabled when FRCI assert 1- force output is enabled by software write swfrc to 1"]
        pub type FRCSRCSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTRECTIME` reader - This bitfield select when to recover PWM output after fault condition removed. 00: immediately 01: after pwm timer counter reload time 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after software write faultclr bit in GCR register"]
        pub type FAULTRECTIME_R = crate::FieldReader;
        #[doc = "Field `FAULTRECTIME` writer - This bitfield select when to recover PWM output after fault condition removed. 00: immediately 01: after pwm timer counter reload time 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after software write faultclr bit in GCR register"]
        pub type FAULTRECTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `FAULTMODE` reader - This bitfield defines the PWM output status when fault condition happen 00: force output 0 01: force output 1 1x: output highz"]
        pub type FAULTMODE_R = crate::FieldReader;
        #[doc = "Field `FAULTMODE` writer - This bitfield defines the PWM output status when fault condition happen 00: force output 0 01: force output 1 1x: output highz"]
        pub type FAULTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `FRCSHDWUPT` reader - This bitfield select when the FRCMD shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
        pub type FRCSHDWUPT_R = crate::FieldReader;
        #[doc = "Field `FRCSHDWUPT` writer - This bitfield select when the FRCMD shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
        pub type FRCSHDWUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `OEN` reader - PWM output enable 1- output is enabled 0- output is disabled"]
        pub type OEN_R = crate::BitReader;
        #[doc = "Field `OEN` writer - PWM output enable 1- output is enabled 0- output is disabled"]
        pub type OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:19 - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. Note: user should configure pair bit and this bitfield before PWM output is enabled."]
            #[inline(always)]
            pub fn deadarea(&self) -> DEADAREA_R {
                DEADAREA_R::new(self.bits & 0x000f_ffff)
            }
            #[doc = "Bit 20 - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. 0- PWM output is in indepandent mode."]
            #[inline(always)]
            pub fn pair(&self) -> PAIR_R {
                PAIR_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Select sources for force output 0- force output is enabled when FRCI assert 1- force output is enabled by software write swfrc to 1"]
            #[inline(always)]
            pub fn frcsrcsel(&self) -> FRCSRCSEL_R {
                FRCSRCSEL_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bits 22:23 - This bitfield select when to recover PWM output after fault condition removed. 00: immediately 01: after pwm timer counter reload time 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after software write faultclr bit in GCR register"]
            #[inline(always)]
            pub fn faultrectime(&self) -> FAULTRECTIME_R {
                FAULTRECTIME_R::new(((self.bits >> 22) & 3) as u8)
            }
            #[doc = "Bits 24:25 - This bitfield defines the PWM output status when fault condition happen 00: force output 0 01: force output 1 1x: output highz"]
            #[inline(always)]
            pub fn faultmode(&self) -> FAULTMODE_R {
                FAULTMODE_R::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bits 26:27 - This bitfield select when the FRCMD shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
            #[inline(always)]
            pub fn frcshdwupt(&self) -> FRCSHDWUPT_R {
                FRCSHDWUPT_R::new(((self.bits >> 26) & 3) as u8)
            }
            #[doc = "Bit 28 - PWM output enable 1- output is enabled 0- output is disabled"]
            #[inline(always)]
            pub fn oen(&self) -> OEN_R {
                OEN_R::new(((self.bits >> 28) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. Note: user should configure pair bit and this bitfield before PWM output is enabled."]
            #[inline(always)]
            #[must_use]
            pub fn deadarea(&mut self) -> DEADAREA_W<PWMCFG_SPEC> {
                DEADAREA_W::new(self, 0)
            }
            #[doc = "Bit 20 - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. 0- PWM output is in indepandent mode."]
            #[inline(always)]
            #[must_use]
            pub fn pair(&mut self) -> PAIR_W<PWMCFG_SPEC> {
                PAIR_W::new(self, 20)
            }
            #[doc = "Bit 21 - Select sources for force output 0- force output is enabled when FRCI assert 1- force output is enabled by software write swfrc to 1"]
            #[inline(always)]
            #[must_use]
            pub fn frcsrcsel(&mut self) -> FRCSRCSEL_W<PWMCFG_SPEC> {
                FRCSRCSEL_W::new(self, 21)
            }
            #[doc = "Bits 22:23 - This bitfield select when to recover PWM output after fault condition removed. 00: immediately 01: after pwm timer counter reload time 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after software write faultclr bit in GCR register"]
            #[inline(always)]
            #[must_use]
            pub fn faultrectime(&mut self) -> FAULTRECTIME_W<PWMCFG_SPEC> {
                FAULTRECTIME_W::new(self, 22)
            }
            #[doc = "Bits 24:25 - This bitfield defines the PWM output status when fault condition happen 00: force output 0 01: force output 1 1x: output highz"]
            #[inline(always)]
            #[must_use]
            pub fn faultmode(&mut self) -> FAULTMODE_W<PWMCFG_SPEC> {
                FAULTMODE_W::new(self, 24)
            }
            #[doc = "Bits 26:27 - This bitfield select when the FRCMD shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
            #[inline(always)]
            #[must_use]
            pub fn frcshdwupt(&mut self) -> FRCSHDWUPT_W<PWMCFG_SPEC> {
                FRCSHDWUPT_W::new(self, 26)
            }
            #[doc = "Bit 28 - PWM output enable 1- output is enabled 0- output is disabled"]
            #[inline(always)]
            #[must_use]
            pub fn oen(&mut self) -> OEN_W<PWMCFG_SPEC> {
                OEN_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PWMCFG_SPEC;
        impl crate::RegisterSpec for PWMCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwmcfg::R`](R) reader structure"]
        impl crate::Readable for PWMCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pwmcfg::W`](W) writer structure"]
        impl crate::Writable for PWMCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PWMCFG[%s]
to value 0"]
        impl crate::Resettable for PWMCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sr (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
    pub type SR = crate::Reg<sr::SR_SPEC>;
    #[doc = "Status register"]
    pub mod sr {
        #[doc = "Register `sr` reader"]
        pub type R = crate::R<SR_SPEC>;
        #[doc = "Register `sr` writer"]
        pub type W = crate::W<SR_SPEC>;
        #[doc = "Field `CMPFX` writer - comparator output compare or input capture flag"]
        pub type CMPFX_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        #[doc = "Field `RLDF` writer - reload flag, this flag set when cnt count to rld value or when SYNCI assert"]
        pub type RLDF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HALFRLDF` writer - half reload flag, this flag set when cnt count to rld/2"]
        pub type HALFRLDF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `XRLDF` writer - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert"]
        pub type XRLDF_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTF` writer - fault condition flag"]
        pub type FAULTF_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bits 0:23 - comparator output compare or input capture flag"]
            #[inline(always)]
            #[must_use]
            pub fn cmpfx(&mut self) -> CMPFX_W<SR_SPEC> {
                CMPFX_W::new(self, 0)
            }
            #[doc = "Bit 24 - reload flag, this flag set when cnt count to rld value or when SYNCI assert"]
            #[inline(always)]
            #[must_use]
            pub fn rldf(&mut self) -> RLDF_W<SR_SPEC> {
                RLDF_W::new(self, 24)
            }
            #[doc = "Bit 25 - half reload flag, this flag set when cnt count to rld/2"]
            #[inline(always)]
            #[must_use]
            pub fn halfrldf(&mut self) -> HALFRLDF_W<SR_SPEC> {
                HALFRLDF_W::new(self, 25)
            }
            #[doc = "Bit 26 - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert"]
            #[inline(always)]
            #[must_use]
            pub fn xrldf(&mut self) -> XRLDF_W<SR_SPEC> {
                XRLDF_W::new(self, 26)
            }
            #[doc = "Bit 27 - fault condition flag"]
            #[inline(always)]
            #[must_use]
            pub fn faultf(&mut self) -> FAULTF_W<SR_SPEC> {
                FAULTF_W::new(self, 27)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SR_SPEC;
        impl crate::RegisterSpec for SR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sr::R`](R) reader structure"]
        impl crate::Readable for SR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
        impl crate::Writable for SR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sr to value 0"]
        impl crate::Resettable for SR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "irqen (rw) register accessor: Interrupt request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqen`]
module"]
    pub type IRQEN = crate::Reg<irqen::IRQEN_SPEC>;
    #[doc = "Interrupt request enable register"]
    pub mod irqen {
        #[doc = "Register `irqen` reader"]
        pub type R = crate::R<IRQEN_SPEC>;
        #[doc = "Register `irqen` writer"]
        pub type W = crate::W<IRQEN_SPEC>;
        #[doc = "Field `CMPIRQEX` reader - comparator output compare or input capture flag interrupt enable"]
        pub type CMPIRQEX_R = crate::FieldReader<u32>;
        #[doc = "Field `CMPIRQEX` writer - comparator output compare or input capture flag interrupt enable"]
        pub type CMPIRQEX_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        #[doc = "Field `RLDIRQE` reader - reload flag interrupt enable"]
        pub type RLDIRQE_R = crate::BitReader;
        #[doc = "Field `RLDIRQE` writer - reload flag interrupt enable"]
        pub type RLDIRQE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HALFRLDIRQE` reader - half reload flag interrupt enable"]
        pub type HALFRLDIRQE_R = crate::BitReader;
        #[doc = "Field `HALFRLDIRQE` writer - half reload flag interrupt enable"]
        pub type HALFRLDIRQE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `XRLDIRQE` reader - extended reload flag interrupt enable"]
        pub type XRLDIRQE_R = crate::BitReader;
        #[doc = "Field `XRLDIRQE` writer - extended reload flag interrupt enable"]
        pub type XRLDIRQE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTIRQE` reader - fault condition interrupt enable"]
        pub type FAULTIRQE_R = crate::BitReader;
        #[doc = "Field `FAULTIRQE` writer - fault condition interrupt enable"]
        pub type FAULTIRQE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:23 - comparator output compare or input capture flag interrupt enable"]
            #[inline(always)]
            pub fn cmpirqex(&self) -> CMPIRQEX_R {
                CMPIRQEX_R::new(self.bits & 0x00ff_ffff)
            }
            #[doc = "Bit 24 - reload flag interrupt enable"]
            #[inline(always)]
            pub fn rldirqe(&self) -> RLDIRQE_R {
                RLDIRQE_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - half reload flag interrupt enable"]
            #[inline(always)]
            pub fn halfrldirqe(&self) -> HALFRLDIRQE_R {
                HALFRLDIRQE_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - extended reload flag interrupt enable"]
            #[inline(always)]
            pub fn xrldirqe(&self) -> XRLDIRQE_R {
                XRLDIRQE_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - fault condition interrupt enable"]
            #[inline(always)]
            pub fn faultirqe(&self) -> FAULTIRQE_R {
                FAULTIRQE_R::new(((self.bits >> 27) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - comparator output compare or input capture flag interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn cmpirqex(&mut self) -> CMPIRQEX_W<IRQEN_SPEC> {
                CMPIRQEX_W::new(self, 0)
            }
            #[doc = "Bit 24 - reload flag interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn rldirqe(&mut self) -> RLDIRQE_W<IRQEN_SPEC> {
                RLDIRQE_W::new(self, 24)
            }
            #[doc = "Bit 25 - half reload flag interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn halfrldirqe(&mut self) -> HALFRLDIRQE_W<IRQEN_SPEC> {
                HALFRLDIRQE_W::new(self, 25)
            }
            #[doc = "Bit 26 - extended reload flag interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn xrldirqe(&mut self) -> XRLDIRQE_W<IRQEN_SPEC> {
                XRLDIRQE_W::new(self, 26)
            }
            #[doc = "Bit 27 - fault condition interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn faultirqe(&mut self) -> FAULTIRQE_W<IRQEN_SPEC> {
                FAULTIRQE_W::new(self, 27)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IRQEN_SPEC;
        impl crate::RegisterSpec for IRQEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`irqen::R`](R) reader structure"]
        impl crate::Readable for IRQEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`irqen::W`](W) writer structure"]
        impl crate::Writable for IRQEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets irqen to value 0"]
        impl crate::Resettable for IRQEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "dmaen (rw) register accessor: DMA request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaen`]
module"]
    pub type DMAEN = crate::Reg<dmaen::DMAEN_SPEC>;
    #[doc = "DMA request enable register"]
    pub mod dmaen {
        #[doc = "Register `dmaen` reader"]
        pub type R = crate::R<DMAEN_SPEC>;
        #[doc = "Register `dmaen` writer"]
        pub type W = crate::W<DMAEN_SPEC>;
        #[doc = "Field `CMPENX` reader - comparator output compare or input capture flag DMA request enable"]
        pub type CMPENX_R = crate::FieldReader<u32>;
        #[doc = "Field `CMPENX` writer - comparator output compare or input capture flag DMA request enable"]
        pub type CMPENX_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        #[doc = "Field `RLDEN` reader - reload flag DMA request enable"]
        pub type RLDEN_R = crate::BitReader;
        #[doc = "Field `RLDEN` writer - reload flag DMA request enable"]
        pub type RLDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HALFRLDEN` reader - half reload flag DMA request enable"]
        pub type HALFRLDEN_R = crate::BitReader;
        #[doc = "Field `HALFRLDEN` writer - half reload flag DMA request enable"]
        pub type HALFRLDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `XRLDEN` reader - extended reload flag DMA request enable"]
        pub type XRLDEN_R = crate::BitReader;
        #[doc = "Field `XRLDEN` writer - extended reload flag DMA request enable"]
        pub type XRLDEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FAULTEN` reader - fault condition DMA request enable"]
        pub type FAULTEN_R = crate::BitReader;
        #[doc = "Field `FAULTEN` writer - fault condition DMA request enable"]
        pub type FAULTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:23 - comparator output compare or input capture flag DMA request enable"]
            #[inline(always)]
            pub fn cmpenx(&self) -> CMPENX_R {
                CMPENX_R::new(self.bits & 0x00ff_ffff)
            }
            #[doc = "Bit 24 - reload flag DMA request enable"]
            #[inline(always)]
            pub fn rlden(&self) -> RLDEN_R {
                RLDEN_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - half reload flag DMA request enable"]
            #[inline(always)]
            pub fn halfrlden(&self) -> HALFRLDEN_R {
                HALFRLDEN_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - extended reload flag DMA request enable"]
            #[inline(always)]
            pub fn xrlden(&self) -> XRLDEN_R {
                XRLDEN_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - fault condition DMA request enable"]
            #[inline(always)]
            pub fn faulten(&self) -> FAULTEN_R {
                FAULTEN_R::new(((self.bits >> 27) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - comparator output compare or input capture flag DMA request enable"]
            #[inline(always)]
            #[must_use]
            pub fn cmpenx(&mut self) -> CMPENX_W<DMAEN_SPEC> {
                CMPENX_W::new(self, 0)
            }
            #[doc = "Bit 24 - reload flag DMA request enable"]
            #[inline(always)]
            #[must_use]
            pub fn rlden(&mut self) -> RLDEN_W<DMAEN_SPEC> {
                RLDEN_W::new(self, 24)
            }
            #[doc = "Bit 25 - half reload flag DMA request enable"]
            #[inline(always)]
            #[must_use]
            pub fn halfrlden(&mut self) -> HALFRLDEN_W<DMAEN_SPEC> {
                HALFRLDEN_W::new(self, 25)
            }
            #[doc = "Bit 26 - extended reload flag DMA request enable"]
            #[inline(always)]
            #[must_use]
            pub fn xrlden(&mut self) -> XRLDEN_W<DMAEN_SPEC> {
                XRLDEN_W::new(self, 26)
            }
            #[doc = "Bit 27 - fault condition DMA request enable"]
            #[inline(always)]
            #[must_use]
            pub fn faulten(&mut self) -> FAULTEN_W<DMAEN_SPEC> {
                FAULTEN_W::new(self, 27)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DMA request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DMAEN_SPEC;
        impl crate::RegisterSpec for DMAEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmaen::R`](R) reader structure"]
        impl crate::Readable for DMAEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dmaen::W`](W) writer structure"]
        impl crate::Writable for DMAEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets dmaen to value 0"]
        impl crate::Resettable for DMAEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CMPCFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmpcfg`]
module"]
    pub type CMPCFG = crate::Reg<cmpcfg::CMPCFG_SPEC>;
    #[doc = "no description available"]
    pub mod cmpcfg {
        #[doc = "Register `CMPCFG[%s]` reader"]
        pub type R = crate::R<CMPCFG_SPEC>;
        #[doc = "Register `CMPCFG[%s]` writer"]
        pub type W = crate::W<CMPCFG_SPEC>;
        #[doc = "Field `CMPMODE` reader - comparator mode 0- output compare mode 1- input capture mode"]
        pub type CMPMODE_R = crate::BitReader;
        #[doc = "Field `CMPMODE` writer - comparator mode 0- output compare mode 1- input capture mode"]
        pub type CMPMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CMPSHDWUPT` reader - This bitfield select when the comparator shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
        pub type CMPSHDWUPT_R = crate::FieldReader;
        #[doc = "Field `CMPSHDWUPT` writer - This bitfield select when the comparator shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
        pub type CMPSHDWUPT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `XCNTCMPEN` reader - This bitfield enable the comparator to compare xcmp with xcnt."]
        pub type XCNTCMPEN_R = crate::FieldReader;
        #[doc = "Field `XCNTCMPEN` writer - This bitfield enable the comparator to compare xcmp with xcnt."]
        pub type XCNTCMPEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bit 1 - comparator mode 0- output compare mode 1- input capture mode"]
            #[inline(always)]
            pub fn cmpmode(&self) -> CMPMODE_R {
                CMPMODE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 2:3 - This bitfield select when the comparator shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
            #[inline(always)]
            pub fn cmpshdwupt(&self) -> CMPSHDWUPT_R {
                CMPSHDWUPT_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bits 4:7 - This bitfield enable the comparator to compare xcmp with xcnt."]
            #[inline(always)]
            pub fn xcntcmpen(&self) -> XCNTCMPEN_R {
                XCNTCMPEN_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 1 - comparator mode 0- output compare mode 1- input capture mode"]
            #[inline(always)]
            #[must_use]
            pub fn cmpmode(&mut self) -> CMPMODE_W<CMPCFG_SPEC> {
                CMPMODE_W::new(self, 1)
            }
            #[doc = "Bits 2:3 - This bitfield select when the comparator shadow register will be loaded to its work register 00: after software set shlk bit of shlk register 01: immediately after the register being modified 10: after hardware event assert, user can select one of the comparators to generate this hardware event. The comparator can be either output compare mode or input capture mode. 11: after SHSYNCI assert"]
            #[inline(always)]
            #[must_use]
            pub fn cmpshdwupt(&mut self) -> CMPSHDWUPT_W<CMPCFG_SPEC> {
                CMPSHDWUPT_W::new(self, 2)
            }
            #[doc = "Bits 4:7 - This bitfield enable the comparator to compare xcmp with xcnt."]
            #[inline(always)]
            #[must_use]
            pub fn xcntcmpen(&mut self) -> XCNTCMPEN_W<CMPCFG_SPEC> {
                XCNTCMPEN_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmpcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmpcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMPCFG_SPEC;
        impl crate::RegisterSpec for CMPCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmpcfg::R`](R) reader structure"]
        impl crate::Readable for CMPCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmpcfg::W`](W) writer structure"]
        impl crate::Writable for CMPCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CMPCFG[%s]
to value 0"]
        impl crate::Resettable for CMPCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "PWM1"]
pub struct PWM1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PWM1 {}
impl PWM1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const pwm0::RegisterBlock = 0xf031_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const pwm0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PWM1 {
    type Target = pwm0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PWM1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PWM1").finish()
    }
}
#[doc = "PWM1"]
pub use self::pwm0 as pwm1;
#[doc = "RDC"]
pub struct RDC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for RDC {}
impl RDC {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const rdc::RegisterBlock = 0xf032_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const rdc::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for RDC {
    type Target = rdc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for RDC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RDC").finish()
    }
}
#[doc = "RDC"]
pub mod rdc {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        rdc_ctl: RDC_CTL,
        acc_i: ACC_I,
        acc_q: ACC_Q,
        in_ctl: IN_CTL,
        out_ctl: OUT_CTL,
        _reserved5: [u8; 0x20],
        exc_timming: EXC_TIMMING,
        exc_scaling: EXC_SCALING,
        exc_offset: EXC_OFFSET,
        pwm_scaling: PWM_SCALING,
        pwm_offset: PWM_OFFSET,
        trig_out0_cfg: TRIG_OUT0_CFG,
        trig_out1_cfg: TRIG_OUT1_CFG,
        pwm_dz: PWM_DZ,
        sync_out_ctrl: SYNC_OUT_CTRL,
        exc_sync_dly: EXC_SYNC_DLY,
        _reserved15: [u8; 0x14],
        max_i: MAX_I,
        min_i: MIN_I,
        max_q: MAX_Q,
        min_q: MIN_Q,
        thrs_i: THRS_I,
        thrs_q: THRS_Q,
        edg_det_ctl: EDG_DET_CTL,
        acc_scaling: ACC_SCALING,
        exc_period: EXC_PERIOD,
        _reserved24: [u8; 0x0c],
        sync_delay_i: SYNC_DELAY_I,
        _reserved25: [u8; 0x04],
        rise_delay_i: RISE_DELAY_I,
        fall_delay_i: FALL_DELAY_I,
        sample_rise_i: SAMPLE_RISE_I,
        sample_fall_i: SAMPLE_FALL_I,
        acc_cnt_i: ACC_CNT_I,
        sign_cnt_i: SIGN_CNT_I,
        sync_delay_q: SYNC_DELAY_Q,
        _reserved32: [u8; 0x04],
        rise_delay_q: RISE_DELAY_Q,
        fall_delay_q: FALL_DELAY_Q,
        sample_rise_q: SAMPLE_RISE_Q,
        sample_fall_q: SAMPLE_FALL_Q,
        acc_cnt_q: ACC_CNT_Q,
        sign_cnt_q: SIGN_CNT_Q,
        amp_max: AMP_MAX,
        amp_min: AMP_MIN,
        int_en: INT_EN,
        adc_int_state: ADC_INT_STATE,
    }
    impl RegisterBlock {
        #[doc = "0x00 - rdc control"]
        #[inline(always)]
        pub const fn rdc_ctl(&self) -> &RDC_CTL {
            &self.rdc_ctl
        }
        #[doc = "0x04 - accumulate result of i_channel"]
        #[inline(always)]
        pub const fn acc_i(&self) -> &ACC_I {
            &self.acc_i
        }
        #[doc = "0x08 - accumulate result of q_channel"]
        #[inline(always)]
        pub const fn acc_q(&self) -> &ACC_Q {
            &self.acc_q
        }
        #[doc = "0x0c - input channel selection"]
        #[inline(always)]
        pub const fn in_ctl(&self) -> &IN_CTL {
            &self.in_ctl
        }
        #[doc = "0x10 - output channel selection"]
        #[inline(always)]
        pub const fn out_ctl(&self) -> &OUT_CTL {
            &self.out_ctl
        }
        #[doc = "0x34 - excitation signal timming setting"]
        #[inline(always)]
        pub const fn exc_timming(&self) -> &EXC_TIMMING {
            &self.exc_timming
        }
        #[doc = "0x38 - amplitude scaling for excitation"]
        #[inline(always)]
        pub const fn exc_scaling(&self) -> &EXC_SCALING {
            &self.exc_scaling
        }
        #[doc = "0x3c - amplitude offset setting"]
        #[inline(always)]
        pub const fn exc_offset(&self) -> &EXC_OFFSET {
            &self.exc_offset
        }
        #[doc = "0x40 - amplitude scaling for excitation"]
        #[inline(always)]
        pub const fn pwm_scaling(&self) -> &PWM_SCALING {
            &self.pwm_scaling
        }
        #[doc = "0x44 - amplitude offset setting"]
        #[inline(always)]
        pub const fn pwm_offset(&self) -> &PWM_OFFSET {
            &self.pwm_offset
        }
        #[doc = "0x48 - Configuration for trigger out 0 in clock cycle"]
        #[inline(always)]
        pub const fn trig_out0_cfg(&self) -> &TRIG_OUT0_CFG {
            &self.trig_out0_cfg
        }
        #[doc = "0x4c - Configuration for trigger out 1 in clock cycle"]
        #[inline(always)]
        pub const fn trig_out1_cfg(&self) -> &TRIG_OUT1_CFG {
            &self.trig_out1_cfg
        }
        #[doc = "0x50 - pwm dead zone control in clock cycle"]
        #[inline(always)]
        pub const fn pwm_dz(&self) -> &PWM_DZ {
            &self.pwm_dz
        }
        #[doc = "0x54 - synchronize output signal control"]
        #[inline(always)]
        pub const fn sync_out_ctrl(&self) -> &SYNC_OUT_CTRL {
            &self.sync_out_ctrl
        }
        #[doc = "0x58 - trigger in delay timming in soc bus cycle"]
        #[inline(always)]
        pub const fn exc_sync_dly(&self) -> &EXC_SYNC_DLY {
            &self.exc_sync_dly
        }
        #[doc = "0x70 - max value of i_channel"]
        #[inline(always)]
        pub const fn max_i(&self) -> &MAX_I {
            &self.max_i
        }
        #[doc = "0x74 - min value of i_channel"]
        #[inline(always)]
        pub const fn min_i(&self) -> &MIN_I {
            &self.min_i
        }
        #[doc = "0x78 - max value of q_channel"]
        #[inline(always)]
        pub const fn max_q(&self) -> &MAX_Q {
            &self.max_q
        }
        #[doc = "0x7c - min value of q_channel"]
        #[inline(always)]
        pub const fn min_q(&self) -> &MIN_Q {
            &self.min_q
        }
        #[doc = "0x80 - the offset setting for edge detection of the i_channel"]
        #[inline(always)]
        pub const fn thrs_i(&self) -> &THRS_I {
            &self.thrs_i
        }
        #[doc = "0x84 - the offset setting for edge detection of the q_channel"]
        #[inline(always)]
        pub const fn thrs_q(&self) -> &THRS_Q {
            &self.thrs_q
        }
        #[doc = "0x88 - the control for edge detection"]
        #[inline(always)]
        pub const fn edg_det_ctl(&self) -> &EDG_DET_CTL {
            &self.edg_det_ctl
        }
        #[doc = "0x8c - scaling for accumulation result"]
        #[inline(always)]
        pub const fn acc_scaling(&self) -> &ACC_SCALING {
            &self.acc_scaling
        }
        #[doc = "0x90 - period of excitation"]
        #[inline(always)]
        pub const fn exc_period(&self) -> &EXC_PERIOD {
            &self.exc_period
        }
        #[doc = "0xa0 - delay setting in clock cycle for synchronous signal"]
        #[inline(always)]
        pub const fn sync_delay_i(&self) -> &SYNC_DELAY_I {
            &self.sync_delay_i
        }
        #[doc = "0xa8 - delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data"]
        #[inline(always)]
        pub const fn rise_delay_i(&self) -> &RISE_DELAY_I {
            &self.rise_delay_i
        }
        #[doc = "0xac - delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data"]
        #[inline(always)]
        pub const fn fall_delay_i(&self) -> &FALL_DELAY_I {
            &self.fall_delay_i
        }
        #[doc = "0xb0 - sample value on rising edge of rectify signal"]
        #[inline(always)]
        pub const fn sample_rise_i(&self) -> &SAMPLE_RISE_I {
            &self.sample_rise_i
        }
        #[doc = "0xb4 - sample value on falling edge of rectify signal"]
        #[inline(always)]
        pub const fn sample_fall_i(&self) -> &SAMPLE_FALL_I {
            &self.sample_fall_i
        }
        #[doc = "0xb8 - number of accumulation"]
        #[inline(always)]
        pub const fn acc_cnt_i(&self) -> &ACC_CNT_I {
            &self.acc_cnt_i
        }
        #[doc = "0xbc - sample counter of opposite sign with rectify signal"]
        #[inline(always)]
        pub const fn sign_cnt_i(&self) -> &SIGN_CNT_I {
            &self.sign_cnt_i
        }
        #[doc = "0xc0 - delay setting in clock cycle for synchronous signal"]
        #[inline(always)]
        pub const fn sync_delay_q(&self) -> &SYNC_DELAY_Q {
            &self.sync_delay_q
        }
        #[doc = "0xc8 - delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data"]
        #[inline(always)]
        pub const fn rise_delay_q(&self) -> &RISE_DELAY_Q {
            &self.rise_delay_q
        }
        #[doc = "0xcc - delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data"]
        #[inline(always)]
        pub const fn fall_delay_q(&self) -> &FALL_DELAY_Q {
            &self.fall_delay_q
        }
        #[doc = "0xd0 - sample value on rising edge of rectify signal"]
        #[inline(always)]
        pub const fn sample_rise_q(&self) -> &SAMPLE_RISE_Q {
            &self.sample_rise_q
        }
        #[doc = "0xd4 - sample value on falling edge of rectify signal"]
        #[inline(always)]
        pub const fn sample_fall_q(&self) -> &SAMPLE_FALL_Q {
            &self.sample_fall_q
        }
        #[doc = "0xd8 - number of accumulation"]
        #[inline(always)]
        pub const fn acc_cnt_q(&self) -> &ACC_CNT_Q {
            &self.acc_cnt_q
        }
        #[doc = "0xdc - sample counter of opposite sign with rectify signal"]
        #[inline(always)]
        pub const fn sign_cnt_q(&self) -> &SIGN_CNT_Q {
            &self.sign_cnt_q
        }
        #[doc = "0xe0 - the maximum of acc amplitude"]
        #[inline(always)]
        pub const fn amp_max(&self) -> &AMP_MAX {
            &self.amp_max
        }
        #[doc = "0xe4 - the minimum of acc amplitude"]
        #[inline(always)]
        pub const fn amp_min(&self) -> &AMP_MIN {
            &self.amp_min
        }
        #[doc = "0xe8 - the interrupt mask control"]
        #[inline(always)]
        pub const fn int_en(&self) -> &INT_EN {
            &self.int_en
        }
        #[doc = "0xec - the interrupt state"]
        #[inline(always)]
        pub const fn adc_int_state(&self) -> &ADC_INT_STATE {
            &self.adc_int_state
        }
    }
    #[doc = "rdc_ctl (rw) register accessor: rdc control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdc_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdc_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rdc_ctl`]
module"]
    pub type RDC_CTL = crate::Reg<rdc_ctl::RDC_CTL_SPEC>;
    #[doc = "rdc control"]
    pub mod rdc_ctl {
        #[doc = "Register `rdc_ctl` reader"]
        pub type R = crate::R<RDC_CTL_SPEC>;
        #[doc = "Register `rdc_ctl` writer"]
        pub type W = crate::W<RDC_CTL_SPEC>;
        #[doc = "Field `EXC_EN` reader - Enable rdc excite signal 0: rdc disable 1: rdc enable"]
        pub type EXC_EN_R = crate::BitReader;
        #[doc = "Field `EXC_EN` writer - Enable rdc excite signal 0: rdc disable 1: rdc enable"]
        pub type EXC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EXC_START` reader - Write 1 start excite signal, always read 0 0: no effect 1: start excite signal"]
        pub type EXC_START_R = crate::BitReader;
        #[doc = "Field `EXC_START` writer - Write 1 start excite signal, always read 0 0: no effect 1: start excite signal"]
        pub type EXC_START_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_EN` reader - Enable rdc accumulate 0: rdc disable 1: rdc enable"]
        pub type ACC_EN_R = crate::BitReader;
        #[doc = "Field `ACC_EN` writer - Enable rdc accumulate 0: rdc disable 1: rdc enable"]
        pub type ACC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RECTIFY_SEL` reader - Select reference point of rectify signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal 4: use value on external pin 5: use invert value on external pin"]
        pub type RECTIFY_SEL_R = crate::FieldReader;
        #[doc = "Field `RECTIFY_SEL` writer - Select reference point of rectify signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal 4: use value on external pin 5: use invert value on external pin"]
        pub type RECTIFY_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `ACC_LEN` reader - Accumulate time, support on the fly change 0：1 cycle 1：2 cycles … 255: 256 cycles"]
        pub type ACC_LEN_R = crate::FieldReader;
        #[doc = "Field `ACC_LEN` writer - Accumulate time, support on the fly change 0：1 cycle 1：2 cycles … 255: 256 cycles"]
        pub type ACC_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `TS_SEL` reader - Time stamp selection for accumulation 0: end of accumulation 1: start of accumulation 2: center of accumulation"]
        pub type TS_SEL_R = crate::FieldReader;
        #[doc = "Field `TS_SEL` writer - Time stamp selection for accumulation 0: end of accumulation 1: start of accumulation 2: center of accumulation"]
        pub type TS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bit 0 - Enable rdc excite signal 0: rdc disable 1: rdc enable"]
            #[inline(always)]
            pub fn exc_en(&self) -> EXC_EN_R {
                EXC_EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Write 1 start excite signal, always read 0 0: no effect 1: start excite signal"]
            #[inline(always)]
            pub fn exc_start(&self) -> EXC_START_R {
                EXC_START_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Enable rdc accumulate 0: rdc disable 1: rdc enable"]
            #[inline(always)]
            pub fn acc_en(&self) -> ACC_EN_R {
                ACC_EN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bits 4:6 - Select reference point of rectify signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal 4: use value on external pin 5: use invert value on external pin"]
            #[inline(always)]
            pub fn rectify_sel(&self) -> RECTIFY_SEL_R {
                RECTIFY_SEL_R::new(((self.bits >> 4) & 7) as u8)
            }
            #[doc = "Bits 12:19 - Accumulate time, support on the fly change 0：1 cycle 1：2 cycles … 255: 256 cycles"]
            #[inline(always)]
            pub fn acc_len(&self) -> ACC_LEN_R {
                ACC_LEN_R::new(((self.bits >> 12) & 0xff) as u8)
            }
            #[doc = "Bits 20:21 - Time stamp selection for accumulation 0: end of accumulation 1: start of accumulation 2: center of accumulation"]
            #[inline(always)]
            pub fn ts_sel(&self) -> TS_SEL_R {
                TS_SEL_R::new(((self.bits >> 20) & 3) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable rdc excite signal 0: rdc disable 1: rdc enable"]
            #[inline(always)]
            #[must_use]
            pub fn exc_en(&mut self) -> EXC_EN_W<RDC_CTL_SPEC> {
                EXC_EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - Write 1 start excite signal, always read 0 0: no effect 1: start excite signal"]
            #[inline(always)]
            #[must_use]
            pub fn exc_start(&mut self) -> EXC_START_W<RDC_CTL_SPEC> {
                EXC_START_W::new(self, 1)
            }
            #[doc = "Bit 2 - Enable rdc accumulate 0: rdc disable 1: rdc enable"]
            #[inline(always)]
            #[must_use]
            pub fn acc_en(&mut self) -> ACC_EN_W<RDC_CTL_SPEC> {
                ACC_EN_W::new(self, 2)
            }
            #[doc = "Bits 4:6 - Select reference point of rectify signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal 4: use value on external pin 5: use invert value on external pin"]
            #[inline(always)]
            #[must_use]
            pub fn rectify_sel(&mut self) -> RECTIFY_SEL_W<RDC_CTL_SPEC> {
                RECTIFY_SEL_W::new(self, 4)
            }
            #[doc = "Bits 12:19 - Accumulate time, support on the fly change 0：1 cycle 1：2 cycles … 255: 256 cycles"]
            #[inline(always)]
            #[must_use]
            pub fn acc_len(&mut self) -> ACC_LEN_W<RDC_CTL_SPEC> {
                ACC_LEN_W::new(self, 12)
            }
            #[doc = "Bits 20:21 - Time stamp selection for accumulation 0: end of accumulation 1: start of accumulation 2: center of accumulation"]
            #[inline(always)]
            #[must_use]
            pub fn ts_sel(&mut self) -> TS_SEL_W<RDC_CTL_SPEC> {
                TS_SEL_W::new(self, 20)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "rdc control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rdc_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rdc_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RDC_CTL_SPEC;
        impl crate::RegisterSpec for RDC_CTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rdc_ctl::R`](R) reader structure"]
        impl crate::Readable for RDC_CTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rdc_ctl::W`](W) writer structure"]
        impl crate::Writable for RDC_CTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets rdc_ctl to value 0"]
        impl crate::Resettable for RDC_CTL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "acc_i (rw) register accessor: accumulate result of i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acc_i`]
module"]
    pub type ACC_I = crate::Reg<acc_i::ACC_I_SPEC>;
    #[doc = "accumulate result of i_channel"]
    pub mod acc_i {
        #[doc = "Register `acc_i` reader"]
        pub type R = crate::R<ACC_I_SPEC>;
        #[doc = "Register `acc_i` writer"]
        pub type W = crate::W<ACC_I_SPEC>;
        #[doc = "Field `ACC` reader - accumulate result of i_channel, this is a signed number"]
        pub type ACC_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - accumulate result of i_channel, this is a signed number"]
            #[inline(always)]
            pub fn acc(&self) -> ACC_R {
                ACC_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "accumulate result of i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ACC_I_SPEC;
        impl crate::RegisterSpec for ACC_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`acc_i::R`](R) reader structure"]
        impl crate::Readable for ACC_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`acc_i::W`](W) writer structure"]
        impl crate::Writable for ACC_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets acc_i to value 0"]
        impl crate::Resettable for ACC_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "acc_q (rw) register accessor: accumulate result of q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acc_q`]
module"]
    pub type ACC_Q = crate::Reg<acc_q::ACC_Q_SPEC>;
    #[doc = "accumulate result of q_channel"]
    pub mod acc_q {
        #[doc = "Register `acc_q` reader"]
        pub type R = crate::R<ACC_Q_SPEC>;
        #[doc = "Register `acc_q` writer"]
        pub type W = crate::W<ACC_Q_SPEC>;
        #[doc = "Field `ACC` reader - accumulate result of q_channel, this is a signed number"]
        pub type ACC_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - accumulate result of q_channel, this is a signed number"]
            #[inline(always)]
            pub fn acc(&self) -> ACC_R {
                ACC_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "accumulate result of q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ACC_Q_SPEC;
        impl crate::RegisterSpec for ACC_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`acc_q::R`](R) reader structure"]
        impl crate::Readable for ACC_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`acc_q::W`](W) writer structure"]
        impl crate::Writable for ACC_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets acc_q to value 0"]
        impl crate::Resettable for ACC_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "in_ctl (rw) register accessor: input channel selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_ctl`]
module"]
    pub type IN_CTL = crate::Reg<in_ctl::IN_CTL_SPEC>;
    #[doc = "input channel selection"]
    pub mod in_ctl {
        #[doc = "Register `in_ctl` reader"]
        pub type R = crate::R<IN_CTL_SPEC>;
        #[doc = "Register `in_ctl` writer"]
        pub type W = crate::W<IN_CTL_SPEC>;
        #[doc = "Field `CH_I_SEL` reader - Input channel selection for i_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
        pub type CH_I_SEL_R = crate::FieldReader;
        #[doc = "Field `CH_I_SEL` writer - Input channel selection for i_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
        pub type CH_I_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `PORT_I_SEL` reader - Input port selection for i_channel, 0:sel port0 1:sel port1"]
        pub type PORT_I_SEL_R = crate::BitReader;
        #[doc = "Field `PORT_I_SEL` writer - Input port selection for i_channel, 0:sel port0 1:sel port1"]
        pub type PORT_I_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CH_Q_SEL` reader - Input channel selection for q_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
        pub type CH_Q_SEL_R = crate::FieldReader;
        #[doc = "Field `CH_Q_SEL` writer - Input channel selection for q_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
        pub type CH_Q_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `PORT_Q_SEL` reader - Input port selection for q_channel, 0:sel port0 1:sel port1"]
        pub type PORT_Q_SEL_R = crate::BitReader;
        #[doc = "Field `PORT_Q_SEL` writer - Input port selection for q_channel, 0:sel port0 1:sel port1"]
        pub type PORT_Q_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:4 - Input channel selection for i_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
            #[inline(always)]
            pub fn ch_i_sel(&self) -> CH_I_SEL_R {
                CH_I_SEL_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bit 8 - Input port selection for i_channel, 0:sel port0 1:sel port1"]
            #[inline(always)]
            pub fn port_i_sel(&self) -> PORT_I_SEL_R {
                PORT_I_SEL_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bits 12:16 - Input channel selection for q_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
            #[inline(always)]
            pub fn ch_q_sel(&self) -> CH_Q_SEL_R {
                CH_Q_SEL_R::new(((self.bits >> 12) & 0x1f) as u8)
            }
            #[doc = "Bit 20 - Input port selection for q_channel, 0:sel port0 1:sel port1"]
            #[inline(always)]
            pub fn port_q_sel(&self) -> PORT_Q_SEL_R {
                PORT_Q_SEL_R::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - Input channel selection for i_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
            #[inline(always)]
            #[must_use]
            pub fn ch_i_sel(&mut self) -> CH_I_SEL_W<IN_CTL_SPEC> {
                CH_I_SEL_W::new(self, 0)
            }
            #[doc = "Bit 8 - Input port selection for i_channel, 0:sel port0 1:sel port1"]
            #[inline(always)]
            #[must_use]
            pub fn port_i_sel(&mut self) -> PORT_I_SEL_W<IN_CTL_SPEC> {
                PORT_I_SEL_W::new(self, 8)
            }
            #[doc = "Bits 12:16 - Input channel selection for q_channel 0: channel 0 selected 1: channel 1 selected … 31: channel 31 selected"]
            #[inline(always)]
            #[must_use]
            pub fn ch_q_sel(&mut self) -> CH_Q_SEL_W<IN_CTL_SPEC> {
                CH_Q_SEL_W::new(self, 12)
            }
            #[doc = "Bit 20 - Input port selection for q_channel, 0:sel port0 1:sel port1"]
            #[inline(always)]
            #[must_use]
            pub fn port_q_sel(&mut self) -> PORT_Q_SEL_W<IN_CTL_SPEC> {
                PORT_Q_SEL_W::new(self, 20)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "input channel selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IN_CTL_SPEC;
        impl crate::RegisterSpec for IN_CTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`in_ctl::R`](R) reader structure"]
        impl crate::Readable for IN_CTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`in_ctl::W`](W) writer structure"]
        impl crate::Writable for IN_CTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets in_ctl to value 0"]
        impl crate::Resettable for IN_CTL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "out_ctl (rw) register accessor: output channel selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_ctl`]
module"]
    pub type OUT_CTL = crate::Reg<out_ctl::OUT_CTL_SPEC>;
    #[doc = "output channel selection"]
    pub mod out_ctl {
        #[doc = "Register `out_ctl` reader"]
        pub type R = crate::R<OUT_CTL_SPEC>;
        #[doc = "Register `out_ctl` writer"]
        pub type W = crate::W<OUT_CTL_SPEC>;
        #[doc = "Field `CH_I_SEL` reader - Output channel selection for i_channel"]
        pub type CH_I_SEL_R = crate::FieldReader;
        #[doc = "Field `CH_I_SEL` writer - Output channel selection for i_channel"]
        pub type CH_I_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `CH_Q_SEL` reader - Output channel selection for q_channel"]
        pub type CH_Q_SEL_R = crate::FieldReader;
        #[doc = "Field `CH_Q_SEL` writer - Output channel selection for q_channel"]
        pub type CH_Q_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:4 - Output channel selection for i_channel"]
            #[inline(always)]
            pub fn ch_i_sel(&self) -> CH_I_SEL_R {
                CH_I_SEL_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bits 8:12 - Output channel selection for q_channel"]
            #[inline(always)]
            pub fn ch_q_sel(&self) -> CH_Q_SEL_R {
                CH_Q_SEL_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - Output channel selection for i_channel"]
            #[inline(always)]
            #[must_use]
            pub fn ch_i_sel(&mut self) -> CH_I_SEL_W<OUT_CTL_SPEC> {
                CH_I_SEL_W::new(self, 0)
            }
            #[doc = "Bits 8:12 - Output channel selection for q_channel"]
            #[inline(always)]
            #[must_use]
            pub fn ch_q_sel(&mut self) -> CH_Q_SEL_W<OUT_CTL_SPEC> {
                CH_Q_SEL_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "output channel selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct OUT_CTL_SPEC;
        impl crate::RegisterSpec for OUT_CTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`out_ctl::R`](R) reader structure"]
        impl crate::Readable for OUT_CTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`out_ctl::W`](W) writer structure"]
        impl crate::Writable for OUT_CTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets out_ctl to value 0"]
        impl crate::Resettable for OUT_CTL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "exc_timming (rw) register accessor: excitation signal timming setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_timming::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_timming::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exc_timming`]
module"]
    pub type EXC_TIMMING = crate::Reg<exc_timming::EXC_TIMMING_SPEC>;
    #[doc = "excitation signal timming setting"]
    pub mod exc_timming {
        #[doc = "Register `exc_timming` reader"]
        pub type R = crate::R<EXC_TIMMING_SPEC>;
        #[doc = "Register `exc_timming` writer"]
        pub type W = crate::W<EXC_TIMMING_SPEC>;
        #[doc = "Field `SMP_RATE` reader - The period for excitation sample in clock cycle， 0: not allowed 1: 1 cycle 2: 2 cycles … 65535 : 65535 cycles"]
        pub type SMP_RATE_R = crate::FieldReader<u16>;
        #[doc = "Field `SMP_RATE` writer - The period for excitation sample in clock cycle， 0: not allowed 1: 1 cycle 2: 2 cycles … 65535 : 65535 cycles"]
        pub type SMP_RATE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `SMP_NUM` reader - Number of sample every excitation period 0: 4 point 1: 8 point … 8: 1024 point"]
        pub type SMP_NUM_R = crate::FieldReader;
        #[doc = "Field `SMP_NUM` writer - Number of sample every excitation period 0: 4 point 1: 8 point … 8: 1024 point"]
        pub type SMP_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `PWM_PRD` reader - Pwm period in samples， 0：1 sample period 1: 2 sample period ... 15: 16 sample period"]
        pub type PWM_PRD_R = crate::FieldReader;
        #[doc = "Field `PWM_PRD` writer - Pwm period in samples， 0：1 sample period 1: 2 sample period ... 15: 16 sample period"]
        pub type PWM_PRD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `SWAP` reader - Swap output of PWM and DAC 0: disable swap 1: swap output"]
        pub type SWAP_R = crate::BitReader;
        #[doc = "Field `SWAP` writer - Swap output of PWM and DAC 0: disable swap 1: swap output"]
        pub type SWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:15 - The period for excitation sample in clock cycle， 0: not allowed 1: 1 cycle 2: 2 cycles … 65535 : 65535 cycles"]
            #[inline(always)]
            pub fn smp_rate(&self) -> SMP_RATE_R {
                SMP_RATE_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:19 - Number of sample every excitation period 0: 4 point 1: 8 point … 8: 1024 point"]
            #[inline(always)]
            pub fn smp_num(&self) -> SMP_NUM_R {
                SMP_NUM_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bits 20:23 - Pwm period in samples， 0：1 sample period 1: 2 sample period ... 15: 16 sample period"]
            #[inline(always)]
            pub fn pwm_prd(&self) -> PWM_PRD_R {
                PWM_PRD_R::new(((self.bits >> 20) & 0x0f) as u8)
            }
            #[doc = "Bit 24 - Swap output of PWM and DAC 0: disable swap 1: swap output"]
            #[inline(always)]
            pub fn swap(&self) -> SWAP_R {
                SWAP_R::new(((self.bits >> 24) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - The period for excitation sample in clock cycle， 0: not allowed 1: 1 cycle 2: 2 cycles … 65535 : 65535 cycles"]
            #[inline(always)]
            #[must_use]
            pub fn smp_rate(&mut self) -> SMP_RATE_W<EXC_TIMMING_SPEC> {
                SMP_RATE_W::new(self, 0)
            }
            #[doc = "Bits 16:19 - Number of sample every excitation period 0: 4 point 1: 8 point … 8: 1024 point"]
            #[inline(always)]
            #[must_use]
            pub fn smp_num(&mut self) -> SMP_NUM_W<EXC_TIMMING_SPEC> {
                SMP_NUM_W::new(self, 16)
            }
            #[doc = "Bits 20:23 - Pwm period in samples， 0：1 sample period 1: 2 sample period ... 15: 16 sample period"]
            #[inline(always)]
            #[must_use]
            pub fn pwm_prd(&mut self) -> PWM_PRD_W<EXC_TIMMING_SPEC> {
                PWM_PRD_W::new(self, 20)
            }
            #[doc = "Bit 24 - Swap output of PWM and DAC 0: disable swap 1: swap output"]
            #[inline(always)]
            #[must_use]
            pub fn swap(&mut self) -> SWAP_W<EXC_TIMMING_SPEC> {
                SWAP_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "excitation signal timming setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_timming::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_timming::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EXC_TIMMING_SPEC;
        impl crate::RegisterSpec for EXC_TIMMING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`exc_timming::R`](R) reader structure"]
        impl crate::Readable for EXC_TIMMING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`exc_timming::W`](W) writer structure"]
        impl crate::Writable for EXC_TIMMING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets exc_timming to value 0x0004_00c8"]
        impl crate::Resettable for EXC_TIMMING_SPEC {
            const RESET_VALUE: u32 = 0x0004_00c8;
        }
    }
    #[doc = "exc_scaling (rw) register accessor: amplitude scaling for excitation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_scaling::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_scaling::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exc_scaling`]
module"]
    pub type EXC_SCALING = crate::Reg<exc_scaling::EXC_SCALING_SPEC>;
    #[doc = "amplitude scaling for excitation"]
    pub mod exc_scaling {
        #[doc = "Register `exc_scaling` reader"]
        pub type R = crate::R<EXC_SCALING_SPEC>;
        #[doc = "Register `exc_scaling` writer"]
        pub type W = crate::W<EXC_SCALING_SPEC>;
        #[doc = "Field `AMP_MAN` reader - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_MAN_R = crate::FieldReader;
        #[doc = "Field `AMP_MAN` writer - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_MAN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `AMP_EXP` reader - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_EXP_R = crate::FieldReader;
        #[doc = "Field `AMP_EXP` writer - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_EXP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            pub fn amp_man(&self) -> AMP_MAN_R {
                AMP_MAN_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:7 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            pub fn amp_exp(&self) -> AMP_EXP_R {
                AMP_EXP_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            #[must_use]
            pub fn amp_man(&mut self) -> AMP_MAN_W<EXC_SCALING_SPEC> {
                AMP_MAN_W::new(self, 0)
            }
            #[doc = "Bits 4:7 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            #[must_use]
            pub fn amp_exp(&mut self) -> AMP_EXP_W<EXC_SCALING_SPEC> {
                AMP_EXP_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "amplitude scaling for excitation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_scaling::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_scaling::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EXC_SCALING_SPEC;
        impl crate::RegisterSpec for EXC_SCALING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`exc_scaling::R`](R) reader structure"]
        impl crate::Readable for EXC_SCALING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`exc_scaling::W`](W) writer structure"]
        impl crate::Writable for EXC_SCALING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets exc_scaling to value 0x11"]
        impl crate::Resettable for EXC_SCALING_SPEC {
            const RESET_VALUE: u32 = 0x11;
        }
    }
    #[doc = "exc_offset (rw) register accessor: amplitude offset setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_offset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_offset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exc_offset`]
module"]
    pub type EXC_OFFSET = crate::Reg<exc_offset::EXC_OFFSET_SPEC>;
    #[doc = "amplitude offset setting"]
    pub mod exc_offset {
        #[doc = "Register `exc_offset` reader"]
        pub type R = crate::R<EXC_OFFSET_SPEC>;
        #[doc = "Register `exc_offset` writer"]
        pub type W = crate::W<EXC_OFFSET_SPEC>;
        #[doc = "Field `AMP_OFFSET` reader - Offset for excitation"]
        pub type AMP_OFFSET_R = crate::FieldReader<u32>;
        #[doc = "Field `AMP_OFFSET` writer - Offset for excitation"]
        pub type AMP_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 0:23 - Offset for excitation"]
            #[inline(always)]
            pub fn amp_offset(&self) -> AMP_OFFSET_R {
                AMP_OFFSET_R::new(self.bits & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - Offset for excitation"]
            #[inline(always)]
            #[must_use]
            pub fn amp_offset(&mut self) -> AMP_OFFSET_W<EXC_OFFSET_SPEC> {
                AMP_OFFSET_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "amplitude offset setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_offset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_offset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EXC_OFFSET_SPEC;
        impl crate::RegisterSpec for EXC_OFFSET_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`exc_offset::R`](R) reader structure"]
        impl crate::Readable for EXC_OFFSET_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`exc_offset::W`](W) writer structure"]
        impl crate::Writable for EXC_OFFSET_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets exc_offset to value 0x0080_0000"]
        impl crate::Resettable for EXC_OFFSET_SPEC {
            const RESET_VALUE: u32 = 0x0080_0000;
        }
    }
    #[doc = "pwm_scaling (rw) register accessor: amplitude scaling for excitation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_scaling::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_scaling::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_scaling`]
module"]
    pub type PWM_SCALING = crate::Reg<pwm_scaling::PWM_SCALING_SPEC>;
    #[doc = "amplitude scaling for excitation"]
    pub mod pwm_scaling {
        #[doc = "Register `pwm_scaling` reader"]
        pub type R = crate::R<PWM_SCALING_SPEC>;
        #[doc = "Register `pwm_scaling` writer"]
        pub type W = crate::W<PWM_SCALING_SPEC>;
        #[doc = "Field `AMP_MAN` reader - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_MAN_R = crate::FieldReader;
        #[doc = "Field `AMP_MAN` writer - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_MAN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `AMP_EXP` reader - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_EXP_R = crate::FieldReader;
        #[doc = "Field `AMP_EXP` writer - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
        pub type AMP_EXP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DITHER` reader - Enable dither of pwm 0: disable 1: enable"]
        pub type DITHER_R = crate::BitReader;
        #[doc = "Field `DITHER` writer - Enable dither of pwm 0: disable 1: enable"]
        pub type DITHER_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `P_POL` reader - Polarity of exc_p signal 0: high active 1: low active"]
        pub type P_POL_R = crate::BitReader;
        #[doc = "Field `P_POL` writer - Polarity of exc_p signal 0: high active 1: low active"]
        pub type P_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `N_POL` reader - Polarity of exc_n signal 0: high active 1: low active"]
        pub type N_POL_R = crate::BitReader;
        #[doc = "Field `N_POL` writer - Polarity of exc_n signal 0: high active 1: low active"]
        pub type N_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            pub fn amp_man(&self) -> AMP_MAN_R {
                AMP_MAN_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:7 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            pub fn amp_exp(&self) -> AMP_EXP_R {
                AMP_EXP_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            #[doc = "Bit 8 - Enable dither of pwm 0: disable 1: enable"]
            #[inline(always)]
            pub fn dither(&self) -> DITHER_R {
                DITHER_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 12 - Polarity of exc_p signal 0: high active 1: low active"]
            #[inline(always)]
            pub fn p_pol(&self) -> P_POL_R {
                P_POL_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - Polarity of exc_n signal 0: high active 1: low active"]
            #[inline(always)]
            pub fn n_pol(&self) -> N_POL_R {
                N_POL_R::new(((self.bits >> 13) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            #[must_use]
            pub fn amp_man(&mut self) -> AMP_MAN_W<PWM_SCALING_SPEC> {
                AMP_MAN_W::new(self, 0)
            }
            #[doc = "Bits 4:7 - Amplitude scaling for excitation, amplitude = \\[table value\\]
x man / 2^exp"]
            #[inline(always)]
            #[must_use]
            pub fn amp_exp(&mut self) -> AMP_EXP_W<PWM_SCALING_SPEC> {
                AMP_EXP_W::new(self, 4)
            }
            #[doc = "Bit 8 - Enable dither of pwm 0: disable 1: enable"]
            #[inline(always)]
            #[must_use]
            pub fn dither(&mut self) -> DITHER_W<PWM_SCALING_SPEC> {
                DITHER_W::new(self, 8)
            }
            #[doc = "Bit 12 - Polarity of exc_p signal 0: high active 1: low active"]
            #[inline(always)]
            #[must_use]
            pub fn p_pol(&mut self) -> P_POL_W<PWM_SCALING_SPEC> {
                P_POL_W::new(self, 12)
            }
            #[doc = "Bit 13 - Polarity of exc_n signal 0: high active 1: low active"]
            #[inline(always)]
            #[must_use]
            pub fn n_pol(&mut self) -> N_POL_W<PWM_SCALING_SPEC> {
                N_POL_W::new(self, 13)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "amplitude scaling for excitation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_scaling::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_scaling::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PWM_SCALING_SPEC;
        impl crate::RegisterSpec for PWM_SCALING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_scaling::R`](R) reader structure"]
        impl crate::Readable for PWM_SCALING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pwm_scaling::W`](W) writer structure"]
        impl crate::Writable for PWM_SCALING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pwm_scaling to value 0x0111"]
        impl crate::Resettable for PWM_SCALING_SPEC {
            const RESET_VALUE: u32 = 0x0111;
        }
    }
    #[doc = "pwm_offset (rw) register accessor: amplitude offset setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_offset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_offset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_offset`]
module"]
    pub type PWM_OFFSET = crate::Reg<pwm_offset::PWM_OFFSET_SPEC>;
    #[doc = "amplitude offset setting"]
    pub mod pwm_offset {
        #[doc = "Register `pwm_offset` reader"]
        pub type R = crate::R<PWM_OFFSET_SPEC>;
        #[doc = "Register `pwm_offset` writer"]
        pub type W = crate::W<PWM_OFFSET_SPEC>;
        #[doc = "Field `AMP_OFFSET` reader - Offset for excitation"]
        pub type AMP_OFFSET_R = crate::FieldReader<u32>;
        #[doc = "Field `AMP_OFFSET` writer - Offset for excitation"]
        pub type AMP_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 0:23 - Offset for excitation"]
            #[inline(always)]
            pub fn amp_offset(&self) -> AMP_OFFSET_R {
                AMP_OFFSET_R::new(self.bits & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - Offset for excitation"]
            #[inline(always)]
            #[must_use]
            pub fn amp_offset(&mut self) -> AMP_OFFSET_W<PWM_OFFSET_SPEC> {
                AMP_OFFSET_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "amplitude offset setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_offset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_offset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PWM_OFFSET_SPEC;
        impl crate::RegisterSpec for PWM_OFFSET_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_offset::R`](R) reader structure"]
        impl crate::Readable for PWM_OFFSET_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pwm_offset::W`](W) writer structure"]
        impl crate::Writable for PWM_OFFSET_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pwm_offset to value 0x64"]
        impl crate::Resettable for PWM_OFFSET_SPEC {
            const RESET_VALUE: u32 = 0x64;
        }
    }
    #[doc = "trig_out0_cfg (rw) register accessor: Configuration for trigger out 0 in clock cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trig_out0_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trig_out0_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trig_out0_cfg`]
module"]
    pub type TRIG_OUT0_CFG = crate::Reg<trig_out0_cfg::TRIG_OUT0_CFG_SPEC>;
    #[doc = "Configuration for trigger out 0 in clock cycle"]
    pub mod trig_out0_cfg {
        #[doc = "Register `trig_out0_cfg` reader"]
        pub type R = crate::R<TRIG_OUT0_CFG_SPEC>;
        #[doc = "Register `trig_out0_cfg` writer"]
        pub type W = crate::W<TRIG_OUT0_CFG_SPEC>;
        #[doc = "Field `LEAD_TIM` reader - Lead time for trigger out0 from center of low level , this is a signed value … 2: 2 cycle befor center of low level 1: 1 cycle before center of low level 0: center of low level -1: 1cycle after center of low level -2: 2cycle after center of low level"]
        pub type LEAD_TIM_R = crate::FieldReader<u32>;
        #[doc = "Field `LEAD_TIM` writer - Lead time for trigger out0 from center of low level , this is a signed value … 2: 2 cycle befor center of low level 1: 1 cycle before center of low level 0: center of low level -1: 1cycle after center of low level -2: 2cycle after center of low level"]
        pub type LEAD_TIM_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        #[doc = "Field `ENABLE` reader - Enable trigger out0 0: disable 1: enable"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `ENABLE` writer - Enable trigger out0 0: disable 1: enable"]
        pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:19 - Lead time for trigger out0 from center of low level , this is a signed value … 2: 2 cycle befor center of low level 1: 1 cycle before center of low level 0: center of low level -1: 1cycle after center of low level -2: 2cycle after center of low level"]
            #[inline(always)]
            pub fn lead_tim(&self) -> LEAD_TIM_R {
                LEAD_TIM_R::new(self.bits & 0x000f_ffff)
            }
            #[doc = "Bit 20 - Enable trigger out0 0: disable 1: enable"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - Lead time for trigger out0 from center of low level , this is a signed value … 2: 2 cycle befor center of low level 1: 1 cycle before center of low level 0: center of low level -1: 1cycle after center of low level -2: 2cycle after center of low level"]
            #[inline(always)]
            #[must_use]
            pub fn lead_tim(&mut self) -> LEAD_TIM_W<TRIG_OUT0_CFG_SPEC> {
                LEAD_TIM_W::new(self, 0)
            }
            #[doc = "Bit 20 - Enable trigger out0 0: disable 1: enable"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<TRIG_OUT0_CFG_SPEC> {
                ENABLE_W::new(self, 20)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Configuration for trigger out 0 in clock cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trig_out0_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trig_out0_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRIG_OUT0_CFG_SPEC;
        impl crate::RegisterSpec for TRIG_OUT0_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trig_out0_cfg::R`](R) reader structure"]
        impl crate::Readable for TRIG_OUT0_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trig_out0_cfg::W`](W) writer structure"]
        impl crate::Writable for TRIG_OUT0_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets trig_out0_cfg to value 0x0010_0019"]
        impl crate::Resettable for TRIG_OUT0_CFG_SPEC {
            const RESET_VALUE: u32 = 0x0010_0019;
        }
    }
    #[doc = "trig_out1_cfg (rw) register accessor: Configuration for trigger out 1 in clock cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trig_out1_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trig_out1_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trig_out1_cfg`]
module"]
    pub type TRIG_OUT1_CFG = crate::Reg<trig_out1_cfg::TRIG_OUT1_CFG_SPEC>;
    #[doc = "Configuration for trigger out 1 in clock cycle"]
    pub mod trig_out1_cfg {
        #[doc = "Register `trig_out1_cfg` reader"]
        pub type R = crate::R<TRIG_OUT1_CFG_SPEC>;
        #[doc = "Register `trig_out1_cfg` writer"]
        pub type W = crate::W<TRIG_OUT1_CFG_SPEC>;
        #[doc = "Field `LEAD_TIM` reader - Lead time for trigger out0 from center of hight level , this is a signed value … 2: 2 cycle befor center of hight level 1: 1 cycle before center of hight level 0: center of hight level -1: 1cycle after center of hight level -2: 2cycle after center of hight level"]
        pub type LEAD_TIM_R = crate::FieldReader<u32>;
        #[doc = "Field `LEAD_TIM` writer - Lead time for trigger out0 from center of hight level , this is a signed value … 2: 2 cycle befor center of hight level 1: 1 cycle before center of hight level 0: center of hight level -1: 1cycle after center of hight level -2: 2cycle after center of hight level"]
        pub type LEAD_TIM_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        #[doc = "Field `ENABLE` reader - Enable trigger out1 0: disable 1: enable"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `ENABLE` writer - Enable trigger out1 0: disable 1: enable"]
        pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:19 - Lead time for trigger out0 from center of hight level , this is a signed value … 2: 2 cycle befor center of hight level 1: 1 cycle before center of hight level 0: center of hight level -1: 1cycle after center of hight level -2: 2cycle after center of hight level"]
            #[inline(always)]
            pub fn lead_tim(&self) -> LEAD_TIM_R {
                LEAD_TIM_R::new(self.bits & 0x000f_ffff)
            }
            #[doc = "Bit 20 - Enable trigger out1 0: disable 1: enable"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - Lead time for trigger out0 from center of hight level , this is a signed value … 2: 2 cycle befor center of hight level 1: 1 cycle before center of hight level 0: center of hight level -1: 1cycle after center of hight level -2: 2cycle after center of hight level"]
            #[inline(always)]
            #[must_use]
            pub fn lead_tim(&mut self) -> LEAD_TIM_W<TRIG_OUT1_CFG_SPEC> {
                LEAD_TIM_W::new(self, 0)
            }
            #[doc = "Bit 20 - Enable trigger out1 0: disable 1: enable"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<TRIG_OUT1_CFG_SPEC> {
                ENABLE_W::new(self, 20)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Configuration for trigger out 1 in clock cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trig_out1_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trig_out1_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRIG_OUT1_CFG_SPEC;
        impl crate::RegisterSpec for TRIG_OUT1_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trig_out1_cfg::R`](R) reader structure"]
        impl crate::Readable for TRIG_OUT1_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trig_out1_cfg::W`](W) writer structure"]
        impl crate::Writable for TRIG_OUT1_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets trig_out1_cfg to value 0x0010_004b"]
        impl crate::Resettable for TRIG_OUT1_CFG_SPEC {
            const RESET_VALUE: u32 = 0x0010_004b;
        }
    }
    #[doc = "pwm_dz (rw) register accessor: pwm dead zone control in clock cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_dz::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_dz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_dz`]
module"]
    pub type PWM_DZ = crate::Reg<pwm_dz::PWM_DZ_SPEC>;
    #[doc = "pwm dead zone control in clock cycle"]
    pub mod pwm_dz {
        #[doc = "Register `pwm_dz` reader"]
        pub type R = crate::R<PWM_DZ_SPEC>;
        #[doc = "Register `pwm_dz` writer"]
        pub type W = crate::W<PWM_DZ_SPEC>;
        #[doc = "Field `DZ_P` reader - Exc_p dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
        pub type DZ_P_R = crate::FieldReader;
        #[doc = "Field `DZ_P` writer - Exc_p dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
        pub type DZ_P_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `DZ_N` reader - Exc_n dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
        pub type DZ_N_R = crate::FieldReader;
        #[doc = "Field `DZ_N` writer - Exc_n dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
        pub type DZ_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - Exc_p dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
            #[inline(always)]
            pub fn dz_p(&self) -> DZ_P_R {
                DZ_P_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - Exc_n dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
            #[inline(always)]
            pub fn dz_n(&self) -> DZ_N_R {
                DZ_N_R::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - Exc_p dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
            #[inline(always)]
            #[must_use]
            pub fn dz_p(&mut self) -> DZ_P_W<PWM_DZ_SPEC> {
                DZ_P_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - Exc_n dead zone in clock cycle before swap 0: no dead zone 1: 1 cycle dead zone 2: 2 cycle dead zone …"]
            #[inline(always)]
            #[must_use]
            pub fn dz_n(&mut self) -> DZ_N_W<PWM_DZ_SPEC> {
                DZ_N_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "pwm dead zone control in clock cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_dz::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_dz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PWM_DZ_SPEC;
        impl crate::RegisterSpec for PWM_DZ_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pwm_dz::R`](R) reader structure"]
        impl crate::Readable for PWM_DZ_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pwm_dz::W`](W) writer structure"]
        impl crate::Writable for PWM_DZ_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets pwm_dz to value 0"]
        impl crate::Resettable for PWM_DZ_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sync_out_ctrl (rw) register accessor: synchronize output signal control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_out_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_out_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_out_ctrl`]
module"]
    pub type SYNC_OUT_CTRL = crate::Reg<sync_out_ctrl::SYNC_OUT_CTRL_SPEC>;
    #[doc = "synchronize output signal control"]
    pub mod sync_out_ctrl {
        #[doc = "Register `sync_out_ctrl` reader"]
        pub type R = crate::R<SYNC_OUT_CTRL_SPEC>;
        #[doc = "Register `sync_out_ctrl` writer"]
        pub type W = crate::W<SYNC_OUT_CTRL_SPEC>;
        #[doc = "Field `SYNC_OUT_SEL` reader - Select output synchornize signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal"]
        pub type SYNC_OUT_SEL_R = crate::FieldReader;
        #[doc = "Field `SYNC_OUT_SEL` writer - Select output synchornize signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal"]
        pub type SYNC_OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `MAX2TRIG_EN` reader - Enable trigger out from the max point of exciting signal 1: enable 0: disable"]
        pub type MAX2TRIG_EN_R = crate::BitReader;
        #[doc = "Field `MAX2TRIG_EN` writer - Enable trigger out from the max point of exciting signal 1: enable 0: disable"]
        pub type MAX2TRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MIN2TRIG_EN` reader - Enable trigger out from the min point of exciting signal 1: enable 0: disable"]
        pub type MIN2TRIG_EN_R = crate::BitReader;
        #[doc = "Field `MIN2TRIG_EN` writer - Enable trigger out from the min point of exciting signal 1: enable 0: disable"]
        pub type MIN2TRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PWM_OUT_DLY` reader - Delay bettween the delyed trigger and the first pwm pulse in clock cycle 1: 1 cycle 2: 2 cycle …"]
        pub type PWM_OUT_DLY_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:1 - Select output synchornize signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal"]
            #[inline(always)]
            pub fn sync_out_sel(&self) -> SYNC_OUT_SEL_R {
                SYNC_OUT_SEL_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 4 - Enable trigger out from the max point of exciting signal 1: enable 0: disable"]
            #[inline(always)]
            pub fn max2trig_en(&self) -> MAX2TRIG_EN_R {
                MAX2TRIG_EN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Enable trigger out from the min point of exciting signal 1: enable 0: disable"]
            #[inline(always)]
            pub fn min2trig_en(&self) -> MIN2TRIG_EN_R {
                MIN2TRIG_EN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bits 16:31 - Delay bettween the delyed trigger and the first pwm pulse in clock cycle 1: 1 cycle 2: 2 cycle …"]
            #[inline(always)]
            pub fn pwm_out_dly(&self) -> PWM_OUT_DLY_R {
                PWM_OUT_DLY_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - Select output synchornize signal 0: 0 phase of internal exciting signal 1: 90 phase of internal exciting signal 2: 180 phase of internal exciting signal 3: 270 phase of internal exciting signal"]
            #[inline(always)]
            #[must_use]
            pub fn sync_out_sel(&mut self) -> SYNC_OUT_SEL_W<SYNC_OUT_CTRL_SPEC> {
                SYNC_OUT_SEL_W::new(self, 0)
            }
            #[doc = "Bit 4 - Enable trigger out from the max point of exciting signal 1: enable 0: disable"]
            #[inline(always)]
            #[must_use]
            pub fn max2trig_en(&mut self) -> MAX2TRIG_EN_W<SYNC_OUT_CTRL_SPEC> {
                MAX2TRIG_EN_W::new(self, 4)
            }
            #[doc = "Bit 5 - Enable trigger out from the min point of exciting signal 1: enable 0: disable"]
            #[inline(always)]
            #[must_use]
            pub fn min2trig_en(&mut self) -> MIN2TRIG_EN_W<SYNC_OUT_CTRL_SPEC> {
                MIN2TRIG_EN_W::new(self, 5)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "synchronize output signal control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_out_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_out_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SYNC_OUT_CTRL_SPEC;
        impl crate::RegisterSpec for SYNC_OUT_CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sync_out_ctrl::R`](R) reader structure"]
        impl crate::Readable for SYNC_OUT_CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sync_out_ctrl::W`](W) writer structure"]
        impl crate::Writable for SYNC_OUT_CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sync_out_ctrl to value 0"]
        impl crate::Resettable for SYNC_OUT_CTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "exc_sync_dly (rw) register accessor: trigger in delay timming in soc bus cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_sync_dly::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_sync_dly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exc_sync_dly`]
module"]
    pub type EXC_SYNC_DLY = crate::Reg<exc_sync_dly::EXC_SYNC_DLY_SPEC>;
    #[doc = "trigger in delay timming in soc bus cycle"]
    pub mod exc_sync_dly {
        #[doc = "Register `exc_sync_dly` reader"]
        pub type R = crate::R<EXC_SYNC_DLY_SPEC>;
        #[doc = "Register `exc_sync_dly` writer"]
        pub type W = crate::W<EXC_SYNC_DLY_SPEC>;
        #[doc = "Field `DELAY` reader - Trigger in delay timming in bus cycle from rising edge of trigger signal 0: 1 cycle 1: 2 cycle … 0xffffff: 2^24 cycle"]
        pub type DELAY_R = crate::FieldReader<u32>;
        #[doc = "Field `DELAY` writer - Trigger in delay timming in bus cycle from rising edge of trigger signal 0: 1 cycle 1: 2 cycle … 0xffffff: 2^24 cycle"]
        pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        #[doc = "Field `DISABLE` reader - Disable hardware trigger input 0: enable 1: disable"]
        pub type DISABLE_R = crate::BitReader;
        #[doc = "Field `DISABLE` writer - Disable hardware trigger input 0: enable 1: disable"]
        pub type DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:23 - Trigger in delay timming in bus cycle from rising edge of trigger signal 0: 1 cycle 1: 2 cycle … 0xffffff: 2^24 cycle"]
            #[inline(always)]
            pub fn delay(&self) -> DELAY_R {
                DELAY_R::new(self.bits & 0x00ff_ffff)
            }
            #[doc = "Bit 24 - Disable hardware trigger input 0: enable 1: disable"]
            #[inline(always)]
            pub fn disable(&self) -> DISABLE_R {
                DISABLE_R::new(((self.bits >> 24) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - Trigger in delay timming in bus cycle from rising edge of trigger signal 0: 1 cycle 1: 2 cycle … 0xffffff: 2^24 cycle"]
            #[inline(always)]
            #[must_use]
            pub fn delay(&mut self) -> DELAY_W<EXC_SYNC_DLY_SPEC> {
                DELAY_W::new(self, 0)
            }
            #[doc = "Bit 24 - Disable hardware trigger input 0: enable 1: disable"]
            #[inline(always)]
            #[must_use]
            pub fn disable(&mut self) -> DISABLE_W<EXC_SYNC_DLY_SPEC> {
                DISABLE_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "trigger in delay timming in soc bus cycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_sync_dly::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_sync_dly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EXC_SYNC_DLY_SPEC;
        impl crate::RegisterSpec for EXC_SYNC_DLY_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`exc_sync_dly::R`](R) reader structure"]
        impl crate::Readable for EXC_SYNC_DLY_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`exc_sync_dly::W`](W) writer structure"]
        impl crate::Writable for EXC_SYNC_DLY_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets exc_sync_dly to value 0x0100_0001"]
        impl crate::Resettable for EXC_SYNC_DLY_SPEC {
            const RESET_VALUE: u32 = 0x0100_0001;
        }
    }
    #[doc = "max_i (rw) register accessor: max value of i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max_i`]
module"]
    pub type MAX_I = crate::Reg<max_i::MAX_I_SPEC>;
    #[doc = "max value of i_channel"]
    pub mod max_i {
        #[doc = "Register `max_i` reader"]
        pub type R = crate::R<MAX_I_SPEC>;
        #[doc = "Register `max_i` writer"]
        pub type W = crate::W<MAX_I_SPEC>;
        #[doc = "Field `VALID` reader - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
        pub type VALID_R = crate::BitReader;
        #[doc = "Field `VALID` writer - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
        pub type VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MAX` reader - Max value of i_channel, write clear"]
        pub type MAX_R = crate::FieldReader<u32>;
        #[doc = "Field `MAX` writer - Max value of i_channel, write clear"]
        pub type MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bit 0 - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
            #[inline(always)]
            pub fn valid(&self) -> VALID_R {
                VALID_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 8:31 - Max value of i_channel, write clear"]
            #[inline(always)]
            pub fn max(&self) -> MAX_R {
                MAX_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bit 0 - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
            #[inline(always)]
            #[must_use]
            pub fn valid(&mut self) -> VALID_W<MAX_I_SPEC> {
                VALID_W::new(self, 0)
            }
            #[doc = "Bits 8:31 - Max value of i_channel, write clear"]
            #[inline(always)]
            #[must_use]
            pub fn max(&mut self) -> MAX_W<MAX_I_SPEC> {
                MAX_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "max value of i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MAX_I_SPEC;
        impl crate::RegisterSpec for MAX_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`max_i::R`](R) reader structure"]
        impl crate::Readable for MAX_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`max_i::W`](W) writer structure"]
        impl crate::Writable for MAX_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets max_i to value 0"]
        impl crate::Resettable for MAX_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "min_i (rw) register accessor: min value of i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@min_i`]
module"]
    pub type MIN_I = crate::Reg<min_i::MIN_I_SPEC>;
    #[doc = "min value of i_channel"]
    pub mod min_i {
        #[doc = "Register `min_i` reader"]
        pub type R = crate::R<MIN_I_SPEC>;
        #[doc = "Register `min_i` writer"]
        pub type W = crate::W<MIN_I_SPEC>;
        #[doc = "Field `VALID` reader - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
        pub type VALID_R = crate::BitReader;
        #[doc = "Field `VALID` writer - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
        pub type VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MIN` reader - Min value of i_channel, write clear"]
        pub type MIN_R = crate::FieldReader<u32>;
        #[doc = "Field `MIN` writer - Min value of i_channel, write clear"]
        pub type MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bit 0 - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
            #[inline(always)]
            pub fn valid(&self) -> VALID_R {
                VALID_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 8:31 - Min value of i_channel, write clear"]
            #[inline(always)]
            pub fn min(&self) -> MIN_R {
                MIN_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bit 0 - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
            #[inline(always)]
            #[must_use]
            pub fn valid(&mut self) -> VALID_W<MIN_I_SPEC> {
                VALID_W::new(self, 0)
            }
            #[doc = "Bits 8:31 - Min value of i_channel, write clear"]
            #[inline(always)]
            #[must_use]
            pub fn min(&mut self) -> MIN_W<MIN_I_SPEC> {
                MIN_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "min value of i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MIN_I_SPEC;
        impl crate::RegisterSpec for MIN_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`min_i::R`](R) reader structure"]
        impl crate::Readable for MIN_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`min_i::W`](W) writer structure"]
        impl crate::Writable for MIN_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets min_i to value 0"]
        impl crate::Resettable for MIN_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "max_q (rw) register accessor: max value of q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max_q`]
module"]
    pub type MAX_Q = crate::Reg<max_q::MAX_Q_SPEC>;
    #[doc = "max value of q_channel"]
    pub mod max_q {
        #[doc = "Register `max_q` reader"]
        pub type R = crate::R<MAX_Q_SPEC>;
        #[doc = "Register `max_q` writer"]
        pub type W = crate::W<MAX_Q_SPEC>;
        #[doc = "Field `VALID` reader - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
        pub type VALID_R = crate::BitReader;
        #[doc = "Field `VALID` writer - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
        pub type VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MAX` reader - Max value of q_channel, write clear"]
        pub type MAX_R = crate::FieldReader<u32>;
        #[doc = "Field `MAX` writer - Max value of q_channel, write clear"]
        pub type MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bit 0 - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
            #[inline(always)]
            pub fn valid(&self) -> VALID_R {
                VALID_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 8:31 - Max value of q_channel, write clear"]
            #[inline(always)]
            pub fn max(&self) -> MAX_R {
                MAX_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bit 0 - Max value valid, write clear 0: max value is not valid 1: max value is valid"]
            #[inline(always)]
            #[must_use]
            pub fn valid(&mut self) -> VALID_W<MAX_Q_SPEC> {
                VALID_W::new(self, 0)
            }
            #[doc = "Bits 8:31 - Max value of q_channel, write clear"]
            #[inline(always)]
            #[must_use]
            pub fn max(&mut self) -> MAX_W<MAX_Q_SPEC> {
                MAX_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "max value of q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MAX_Q_SPEC;
        impl crate::RegisterSpec for MAX_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`max_q::R`](R) reader structure"]
        impl crate::Readable for MAX_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`max_q::W`](W) writer structure"]
        impl crate::Writable for MAX_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets max_q to value 0"]
        impl crate::Resettable for MAX_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "min_q (rw) register accessor: min value of q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@min_q`]
module"]
    pub type MIN_Q = crate::Reg<min_q::MIN_Q_SPEC>;
    #[doc = "min value of q_channel"]
    pub mod min_q {
        #[doc = "Register `min_q` reader"]
        pub type R = crate::R<MIN_Q_SPEC>;
        #[doc = "Register `min_q` writer"]
        pub type W = crate::W<MIN_Q_SPEC>;
        #[doc = "Field `VALID` reader - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
        pub type VALID_R = crate::BitReader;
        #[doc = "Field `VALID` writer - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
        pub type VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MIN` reader - Min value of q_channel, write clear"]
        pub type MIN_R = crate::FieldReader<u32>;
        #[doc = "Field `MIN` writer - Min value of q_channel, write clear"]
        pub type MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bit 0 - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
            #[inline(always)]
            pub fn valid(&self) -> VALID_R {
                VALID_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 8:31 - Min value of q_channel, write clear"]
            #[inline(always)]
            pub fn min(&self) -> MIN_R {
                MIN_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bit 0 - Min value valid, write clear 0: min value is not valid 1: min value is valid"]
            #[inline(always)]
            #[must_use]
            pub fn valid(&mut self) -> VALID_W<MIN_Q_SPEC> {
                VALID_W::new(self, 0)
            }
            #[doc = "Bits 8:31 - Min value of q_channel, write clear"]
            #[inline(always)]
            #[must_use]
            pub fn min(&mut self) -> MIN_W<MIN_Q_SPEC> {
                MIN_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "min value of q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MIN_Q_SPEC;
        impl crate::RegisterSpec for MIN_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`min_q::R`](R) reader structure"]
        impl crate::Readable for MIN_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`min_q::W`](W) writer structure"]
        impl crate::Writable for MIN_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets min_q to value 0"]
        impl crate::Resettable for MIN_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "thrs_i (rw) register accessor: the offset setting for edge detection of the i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thrs_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thrs_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thrs_i`]
module"]
    pub type THRS_I = crate::Reg<thrs_i::THRS_I_SPEC>;
    #[doc = "the offset setting for edge detection of the i_channel"]
    pub mod thrs_i {
        #[doc = "Register `thrs_i` reader"]
        pub type R = crate::R<THRS_I_SPEC>;
        #[doc = "Register `thrs_i` writer"]
        pub type W = crate::W<THRS_I_SPEC>;
        #[doc = "Field `THRS` reader - The offset setting for edge detection of the i_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
        pub type THRS_R = crate::FieldReader<u32>;
        #[doc = "Field `THRS` writer - The offset setting for edge detection of the i_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
        pub type THRS_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 8:31 - The offset setting for edge detection of the i_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
            #[inline(always)]
            pub fn thrs(&self) -> THRS_R {
                THRS_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 8:31 - The offset setting for edge detection of the i_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
            #[inline(always)]
            #[must_use]
            pub fn thrs(&mut self) -> THRS_W<THRS_I_SPEC> {
                THRS_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "the offset setting for edge detection of the i_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thrs_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thrs_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct THRS_I_SPEC;
        impl crate::RegisterSpec for THRS_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`thrs_i::R`](R) reader structure"]
        impl crate::Readable for THRS_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`thrs_i::W`](W) writer structure"]
        impl crate::Writable for THRS_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets thrs_i to value 0"]
        impl crate::Resettable for THRS_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "thrs_q (rw) register accessor: the offset setting for edge detection of the q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thrs_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thrs_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@thrs_q`]
module"]
    pub type THRS_Q = crate::Reg<thrs_q::THRS_Q_SPEC>;
    #[doc = "the offset setting for edge detection of the q_channel"]
    pub mod thrs_q {
        #[doc = "Register `thrs_q` reader"]
        pub type R = crate::R<THRS_Q_SPEC>;
        #[doc = "Register `thrs_q` writer"]
        pub type W = crate::W<THRS_Q_SPEC>;
        #[doc = "Field `THRS` reader - The offset setting for edge detection of the q_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
        pub type THRS_R = crate::FieldReader<u32>;
        #[doc = "Field `THRS` writer - The offset setting for edge detection of the q_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
        pub type THRS_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 8:31 - The offset setting for edge detection of the q_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
            #[inline(always)]
            pub fn thrs(&self) -> THRS_R {
                THRS_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 8:31 - The offset setting for edge detection of the q_channel, signed number … 2: the offset is 0x800000+2 1: the offset is 0x800000+1 0: the offset is 0x800000 -1: the offset is 0x800000-1 -2: the offset is 0x800000-2 …"]
            #[inline(always)]
            #[must_use]
            pub fn thrs(&mut self) -> THRS_W<THRS_Q_SPEC> {
                THRS_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "the offset setting for edge detection of the q_channel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`thrs_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`thrs_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct THRS_Q_SPEC;
        impl crate::RegisterSpec for THRS_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`thrs_q::R`](R) reader structure"]
        impl crate::Readable for THRS_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`thrs_q::W`](W) writer structure"]
        impl crate::Writable for THRS_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets thrs_q to value 0"]
        impl crate::Resettable for THRS_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "edg_det_ctl (rw) register accessor: the control for edge detection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edg_det_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edg_det_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edg_det_ctl`]
module"]
    pub type EDG_DET_CTL = crate::Reg<edg_det_ctl::EDG_DET_CTL_SPEC>;
    #[doc = "the control for edge detection"]
    pub mod edg_det_ctl {
        #[doc = "Register `edg_det_ctl` reader"]
        pub type R = crate::R<EDG_DET_CTL_SPEC>;
        #[doc = "Register `edg_det_ctl` writer"]
        pub type W = crate::W<EDG_DET_CTL_SPEC>;
        #[doc = "Field `FILTER` reader - The continuous positive or negative number for edge detection 0: 1 1: 2 … 7: 8"]
        pub type FILTER_R = crate::FieldReader;
        #[doc = "Field `FILTER` writer - The continuous positive or negative number for edge detection 0: 1 1: 2 … 7: 8"]
        pub type FILTER_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `HOLD` reader - The minimum edge distance in sample 0:1 sample 1:2 sample 2:3 samples … 63:64 samples"]
        pub type HOLD_R = crate::FieldReader;
        #[doc = "Field `HOLD` writer - The minimum edge distance in sample 0:1 sample 1:2 sample 2:3 samples … 63:64 samples"]
        pub type HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:2 - The continuous positive or negative number for edge detection 0: 1 1: 2 … 7: 8"]
            #[inline(always)]
            pub fn filter(&self) -> FILTER_R {
                FILTER_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bits 4:9 - The minimum edge distance in sample 0:1 sample 1:2 sample 2:3 samples … 63:64 samples"]
            #[inline(always)]
            pub fn hold(&self) -> HOLD_R {
                HOLD_R::new(((self.bits >> 4) & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - The continuous positive or negative number for edge detection 0: 1 1: 2 … 7: 8"]
            #[inline(always)]
            #[must_use]
            pub fn filter(&mut self) -> FILTER_W<EDG_DET_CTL_SPEC> {
                FILTER_W::new(self, 0)
            }
            #[doc = "Bits 4:9 - The minimum edge distance in sample 0:1 sample 1:2 sample 2:3 samples … 63:64 samples"]
            #[inline(always)]
            #[must_use]
            pub fn hold(&mut self) -> HOLD_W<EDG_DET_CTL_SPEC> {
                HOLD_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "the control for edge detection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edg_det_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edg_det_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EDG_DET_CTL_SPEC;
        impl crate::RegisterSpec for EDG_DET_CTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`edg_det_ctl::R`](R) reader structure"]
        impl crate::Readable for EDG_DET_CTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`edg_det_ctl::W`](W) writer structure"]
        impl crate::Writable for EDG_DET_CTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets edg_det_ctl to value 0x80"]
        impl crate::Resettable for EDG_DET_CTL_SPEC {
            const RESET_VALUE: u32 = 0x80;
        }
    }
    #[doc = "acc_scaling (rw) register accessor: scaling for accumulation result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_scaling::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_scaling::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acc_scaling`]
module"]
    pub type ACC_SCALING = crate::Reg<acc_scaling::ACC_SCALING_SPEC>;
    #[doc = "scaling for accumulation result"]
    pub mod acc_scaling {
        #[doc = "Register `acc_scaling` reader"]
        pub type R = crate::R<ACC_SCALING_SPEC>;
        #[doc = "Register `acc_scaling` writer"]
        pub type W = crate::W<ACC_SCALING_SPEC>;
        #[doc = "Field `ACC_SHIFT` reader - Accumulation value shift control, this is a sign number. 0: {acc\\[39\\],acc\\[38:8\\]} 1: {acc\\[39\\],acc\\[37:7\\]} 2: {acc\\[39\\],acc\\[36:6\\]} … 7: {acc\\[39\\],acc\\[31:1\\]} 8: {acc\\[39\\],acc\\[30:0\\]} 9: acc/2^9 10: acc/2^10 … 15:acc/2^15"]
        pub type ACC_SHIFT_R = crate::FieldReader;
        #[doc = "Field `ACC_SHIFT` writer - Accumulation value shift control, this is a sign number. 0: {acc\\[39\\],acc\\[38:8\\]} 1: {acc\\[39\\],acc\\[37:7\\]} 2: {acc\\[39\\],acc\\[36:6\\]} … 7: {acc\\[39\\],acc\\[31:1\\]} 8: {acc\\[39\\],acc\\[30:0\\]} 9: acc/2^9 10: acc/2^10 … 15:acc/2^15"]
        pub type ACC_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `TOXIC_LK` reader - Toxic accumulation data be removed control 1: enable 0: disable"]
        pub type TOXIC_LK_R = crate::BitReader;
        #[doc = "Field `TOXIC_LK` writer - Toxic accumulation data be removed control 1: enable 0: disable"]
        pub type TOXIC_LK_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3 - Accumulation value shift control, this is a sign number. 0: {acc\\[39\\],acc\\[38:8\\]} 1: {acc\\[39\\],acc\\[37:7\\]} 2: {acc\\[39\\],acc\\[36:6\\]} … 7: {acc\\[39\\],acc\\[31:1\\]} 8: {acc\\[39\\],acc\\[30:0\\]} 9: acc/2^9 10: acc/2^10 … 15:acc/2^15"]
            #[inline(always)]
            pub fn acc_shift(&self) -> ACC_SHIFT_R {
                ACC_SHIFT_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bit 8 - Toxic accumulation data be removed control 1: enable 0: disable"]
            #[inline(always)]
            pub fn toxic_lk(&self) -> TOXIC_LK_R {
                TOXIC_LK_R::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - Accumulation value shift control, this is a sign number. 0: {acc\\[39\\],acc\\[38:8\\]} 1: {acc\\[39\\],acc\\[37:7\\]} 2: {acc\\[39\\],acc\\[36:6\\]} … 7: {acc\\[39\\],acc\\[31:1\\]} 8: {acc\\[39\\],acc\\[30:0\\]} 9: acc/2^9 10: acc/2^10 … 15:acc/2^15"]
            #[inline(always)]
            #[must_use]
            pub fn acc_shift(&mut self) -> ACC_SHIFT_W<ACC_SCALING_SPEC> {
                ACC_SHIFT_W::new(self, 0)
            }
            #[doc = "Bit 8 - Toxic accumulation data be removed control 1: enable 0: disable"]
            #[inline(always)]
            #[must_use]
            pub fn toxic_lk(&mut self) -> TOXIC_LK_W<ACC_SCALING_SPEC> {
                TOXIC_LK_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "scaling for accumulation result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_scaling::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_scaling::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ACC_SCALING_SPEC;
        impl crate::RegisterSpec for ACC_SCALING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`acc_scaling::R`](R) reader structure"]
        impl crate::Readable for ACC_SCALING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`acc_scaling::W`](W) writer structure"]
        impl crate::Writable for ACC_SCALING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets acc_scaling to value 0"]
        impl crate::Resettable for ACC_SCALING_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "exc_period (rw) register accessor: period of excitation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_period::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_period::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exc_period`]
module"]
    pub type EXC_PERIOD = crate::Reg<exc_period::EXC_PERIOD_SPEC>;
    #[doc = "period of excitation"]
    pub mod exc_period {
        #[doc = "Register `exc_period` reader"]
        pub type R = crate::R<EXC_PERIOD_SPEC>;
        #[doc = "Register `exc_period` writer"]
        pub type W = crate::W<EXC_PERIOD_SPEC>;
        #[doc = "Field `EXC_PERIOD` reader - The num in clock cycle for period of excitation 0: invalid value 1:1 cycle 2:2 cycles …"]
        pub type EXC_PERIOD_R = crate::FieldReader<u32>;
        #[doc = "Field `EXC_PERIOD` writer - The num in clock cycle for period of excitation 0: invalid value 1:1 cycle 2:2 cycles …"]
        pub type EXC_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - The num in clock cycle for period of excitation 0: invalid value 1:1 cycle 2:2 cycles …"]
            #[inline(always)]
            pub fn exc_period(&self) -> EXC_PERIOD_R {
                EXC_PERIOD_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - The num in clock cycle for period of excitation 0: invalid value 1:1 cycle 2:2 cycles …"]
            #[inline(always)]
            #[must_use]
            pub fn exc_period(&mut self) -> EXC_PERIOD_W<EXC_PERIOD_SPEC> {
                EXC_PERIOD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "period of excitation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exc_period::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exc_period::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EXC_PERIOD_SPEC;
        impl crate::RegisterSpec for EXC_PERIOD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`exc_period::R`](R) reader structure"]
        impl crate::Readable for EXC_PERIOD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`exc_period::W`](W) writer structure"]
        impl crate::Writable for EXC_PERIOD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets exc_period to value 0x1770"]
        impl crate::Resettable for EXC_PERIOD_SPEC {
            const RESET_VALUE: u32 = 0x1770;
        }
    }
    #[doc = "sync_delay_i (rw) register accessor: delay setting in clock cycle for synchronous signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_delay_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_delay_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_delay_i`]
module"]
    pub type SYNC_DELAY_I = crate::Reg<sync_delay_i::SYNC_DELAY_I_SPEC>;
    #[doc = "delay setting in clock cycle for synchronous signal"]
    pub mod sync_delay_i {
        #[doc = "Register `sync_delay_i` reader"]
        pub type R = crate::R<SYNC_DELAY_I_SPEC>;
        #[doc = "Register `sync_delay_i` writer"]
        pub type W = crate::W<SYNC_DELAY_I_SPEC>;
        #[doc = "Field `DELAY` reader - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
        pub type DELAY_R = crate::FieldReader<u32>;
        #[doc = "Field `DELAY` writer - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
        pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
            #[inline(always)]
            pub fn delay(&self) -> DELAY_R {
                DELAY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
            #[inline(always)]
            #[must_use]
            pub fn delay(&mut self) -> DELAY_W<SYNC_DELAY_I_SPEC> {
                DELAY_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "delay setting in clock cycle for synchronous signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_delay_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_delay_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SYNC_DELAY_I_SPEC;
        impl crate::RegisterSpec for SYNC_DELAY_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sync_delay_i::R`](R) reader structure"]
        impl crate::Readable for SYNC_DELAY_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sync_delay_i::W`](W) writer structure"]
        impl crate::Writable for SYNC_DELAY_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sync_delay_i to value 0x08"]
        impl crate::Resettable for SYNC_DELAY_I_SPEC {
            const RESET_VALUE: u32 = 0x08;
        }
    }
    #[doc = "rise_delay_i (rw) register accessor: delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rise_delay_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rise_delay_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rise_delay_i`]
module"]
    pub type RISE_DELAY_I = crate::Reg<rise_delay_i::RISE_DELAY_I_SPEC>;
    #[doc = "delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data"]
    pub mod rise_delay_i {
        #[doc = "Register `rise_delay_i` reader"]
        pub type R = crate::R<RISE_DELAY_I_SPEC>;
        #[doc = "Register `rise_delay_i` writer"]
        pub type W = crate::W<RISE_DELAY_I_SPEC>;
        #[doc = "Field `RISE_DELAY` reader - Delay value on rising edge of i_channel data 0: 1 cycle 1: 2 cycles …"]
        pub type RISE_DELAY_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Delay value on rising edge of i_channel data 0: 1 cycle 1: 2 cycles …"]
            #[inline(always)]
            pub fn rise_delay(&self) -> RISE_DELAY_R {
                RISE_DELAY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rise_delay_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rise_delay_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RISE_DELAY_I_SPEC;
        impl crate::RegisterSpec for RISE_DELAY_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rise_delay_i::R`](R) reader structure"]
        impl crate::Readable for RISE_DELAY_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rise_delay_i::W`](W) writer structure"]
        impl crate::Writable for RISE_DELAY_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets rise_delay_i to value 0"]
        impl crate::Resettable for RISE_DELAY_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "fall_delay_i (rw) register accessor: delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fall_delay_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fall_delay_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fall_delay_i`]
module"]
    pub type FALL_DELAY_I = crate::Reg<fall_delay_i::FALL_DELAY_I_SPEC>;
    #[doc = "delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data"]
    pub mod fall_delay_i {
        #[doc = "Register `fall_delay_i` reader"]
        pub type R = crate::R<FALL_DELAY_I_SPEC>;
        #[doc = "Register `fall_delay_i` writer"]
        pub type W = crate::W<FALL_DELAY_I_SPEC>;
        #[doc = "Field `FALL_DELAY` reader - Delay value on falling edge of i_channel data 0: 1 cycle 1: 2 cycles …"]
        pub type FALL_DELAY_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Delay value on falling edge of i_channel data 0: 1 cycle 1: 2 cycles …"]
            #[inline(always)]
            pub fn fall_delay(&self) -> FALL_DELAY_R {
                FALL_DELAY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fall_delay_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fall_delay_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FALL_DELAY_I_SPEC;
        impl crate::RegisterSpec for FALL_DELAY_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`fall_delay_i::R`](R) reader structure"]
        impl crate::Readable for FALL_DELAY_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`fall_delay_i::W`](W) writer structure"]
        impl crate::Writable for FALL_DELAY_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets fall_delay_i to value 0"]
        impl crate::Resettable for FALL_DELAY_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sample_rise_i (rw) register accessor: sample value on rising edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_rise_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_rise_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_rise_i`]
module"]
    pub type SAMPLE_RISE_I = crate::Reg<sample_rise_i::SAMPLE_RISE_I_SPEC>;
    #[doc = "sample value on rising edge of rectify signal"]
    pub mod sample_rise_i {
        #[doc = "Register `sample_rise_i` reader"]
        pub type R = crate::R<SAMPLE_RISE_I_SPEC>;
        #[doc = "Register `sample_rise_i` writer"]
        pub type W = crate::W<SAMPLE_RISE_I_SPEC>;
        #[doc = "Field `VALUE` reader - sample value on rising edge of rectify signal"]
        pub type VALUE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 8:31 - sample value on rising edge of rectify signal"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "sample value on rising edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_rise_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_rise_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SAMPLE_RISE_I_SPEC;
        impl crate::RegisterSpec for SAMPLE_RISE_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sample_rise_i::R`](R) reader structure"]
        impl crate::Readable for SAMPLE_RISE_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sample_rise_i::W`](W) writer structure"]
        impl crate::Writable for SAMPLE_RISE_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sample_rise_i to value 0"]
        impl crate::Resettable for SAMPLE_RISE_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sample_fall_i (rw) register accessor: sample value on falling edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_fall_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_fall_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_fall_i`]
module"]
    pub type SAMPLE_FALL_I = crate::Reg<sample_fall_i::SAMPLE_FALL_I_SPEC>;
    #[doc = "sample value on falling edge of rectify signal"]
    pub mod sample_fall_i {
        #[doc = "Register `sample_fall_i` reader"]
        pub type R = crate::R<SAMPLE_FALL_I_SPEC>;
        #[doc = "Register `sample_fall_i` writer"]
        pub type W = crate::W<SAMPLE_FALL_I_SPEC>;
        #[doc = "Field `VALUE` reader - sample value on falling edge of rectify signal"]
        pub type VALUE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 8:31 - sample value on falling edge of rectify signal"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "sample value on falling edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_fall_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_fall_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SAMPLE_FALL_I_SPEC;
        impl crate::RegisterSpec for SAMPLE_FALL_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sample_fall_i::R`](R) reader structure"]
        impl crate::Readable for SAMPLE_FALL_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sample_fall_i::W`](W) writer structure"]
        impl crate::Writable for SAMPLE_FALL_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sample_fall_i to value 0"]
        impl crate::Resettable for SAMPLE_FALL_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "acc_cnt_i (rw) register accessor: number of accumulation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_cnt_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_cnt_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acc_cnt_i`]
module"]
    pub type ACC_CNT_I = crate::Reg<acc_cnt_i::ACC_CNT_I_SPEC>;
    #[doc = "number of accumulation"]
    pub mod acc_cnt_i {
        #[doc = "Register `acc_cnt_i` reader"]
        pub type R = crate::R<ACC_CNT_I_SPEC>;
        #[doc = "Register `acc_cnt_i` writer"]
        pub type W = crate::W<ACC_CNT_I_SPEC>;
        #[doc = "Field `CNT_POS` reader - sample number during the positive of rectify signal 1: 1 2: 2 …"]
        pub type CNT_POS_R = crate::FieldReader<u16>;
        #[doc = "Field `CNT_NEG` reader - sample number during the negtive of rectify signal 1: 1 2: 2 …"]
        pub type CNT_NEG_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - sample number during the positive of rectify signal 1: 1 2: 2 …"]
            #[inline(always)]
            pub fn cnt_pos(&self) -> CNT_POS_R {
                CNT_POS_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - sample number during the negtive of rectify signal 1: 1 2: 2 …"]
            #[inline(always)]
            pub fn cnt_neg(&self) -> CNT_NEG_R {
                CNT_NEG_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "number of accumulation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_cnt_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_cnt_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ACC_CNT_I_SPEC;
        impl crate::RegisterSpec for ACC_CNT_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`acc_cnt_i::R`](R) reader structure"]
        impl crate::Readable for ACC_CNT_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`acc_cnt_i::W`](W) writer structure"]
        impl crate::Writable for ACC_CNT_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets acc_cnt_i to value 0"]
        impl crate::Resettable for ACC_CNT_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sign_cnt_i (rw) register accessor: sample counter of opposite sign with rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sign_cnt_i::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sign_cnt_i::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sign_cnt_i`]
module"]
    pub type SIGN_CNT_I = crate::Reg<sign_cnt_i::SIGN_CNT_I_SPEC>;
    #[doc = "sample counter of opposite sign with rectify signal"]
    pub mod sign_cnt_i {
        #[doc = "Register `sign_cnt_i` reader"]
        pub type R = crate::R<SIGN_CNT_I_SPEC>;
        #[doc = "Register `sign_cnt_i` writer"]
        pub type W = crate::W<SIGN_CNT_I_SPEC>;
        #[doc = "Field `CNT_POS` reader - Negative sample counter during positive rectify signal"]
        pub type CNT_POS_R = crate::FieldReader<u16>;
        #[doc = "Field `CNT_NEG` reader - Positive sample counter during negative rectify signal"]
        pub type CNT_NEG_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Negative sample counter during positive rectify signal"]
            #[inline(always)]
            pub fn cnt_pos(&self) -> CNT_POS_R {
                CNT_POS_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - Positive sample counter during negative rectify signal"]
            #[inline(always)]
            pub fn cnt_neg(&self) -> CNT_NEG_R {
                CNT_NEG_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "sample counter of opposite sign with rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sign_cnt_i::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sign_cnt_i::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SIGN_CNT_I_SPEC;
        impl crate::RegisterSpec for SIGN_CNT_I_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sign_cnt_i::R`](R) reader structure"]
        impl crate::Readable for SIGN_CNT_I_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sign_cnt_i::W`](W) writer structure"]
        impl crate::Writable for SIGN_CNT_I_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sign_cnt_i to value 0"]
        impl crate::Resettable for SIGN_CNT_I_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sync_delay_q (rw) register accessor: delay setting in clock cycle for synchronous signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_delay_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_delay_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sync_delay_q`]
module"]
    pub type SYNC_DELAY_Q = crate::Reg<sync_delay_q::SYNC_DELAY_Q_SPEC>;
    #[doc = "delay setting in clock cycle for synchronous signal"]
    pub mod sync_delay_q {
        #[doc = "Register `sync_delay_q` reader"]
        pub type R = crate::R<SYNC_DELAY_Q_SPEC>;
        #[doc = "Register `sync_delay_q` writer"]
        pub type W = crate::W<SYNC_DELAY_Q_SPEC>;
        #[doc = "Field `DELAY` reader - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
        pub type DELAY_R = crate::FieldReader<u32>;
        #[doc = "Field `DELAY` writer - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
        pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
            #[inline(always)]
            pub fn delay(&self) -> DELAY_R {
                DELAY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Delay in clock cycle for synchronous signal , the value shoud less than half of exc_period.exc_period. 0: invalid value 1: 1 cycles 2: 2 cycles ..."]
            #[inline(always)]
            #[must_use]
            pub fn delay(&mut self) -> DELAY_W<SYNC_DELAY_Q_SPEC> {
                DELAY_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "delay setting in clock cycle for synchronous signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sync_delay_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sync_delay_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SYNC_DELAY_Q_SPEC;
        impl crate::RegisterSpec for SYNC_DELAY_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sync_delay_q::R`](R) reader structure"]
        impl crate::Readable for SYNC_DELAY_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sync_delay_q::W`](W) writer structure"]
        impl crate::Writable for SYNC_DELAY_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sync_delay_q to value 0x08"]
        impl crate::Resettable for SYNC_DELAY_Q_SPEC {
            const RESET_VALUE: u32 = 0x08;
        }
    }
    #[doc = "rise_delay_q (rw) register accessor: delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rise_delay_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rise_delay_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rise_delay_q`]
module"]
    pub type RISE_DELAY_Q = crate::Reg<rise_delay_q::RISE_DELAY_Q_SPEC>;
    #[doc = "delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data"]
    pub mod rise_delay_q {
        #[doc = "Register `rise_delay_q` reader"]
        pub type R = crate::R<RISE_DELAY_Q_SPEC>;
        #[doc = "Register `rise_delay_q` writer"]
        pub type W = crate::W<RISE_DELAY_Q_SPEC>;
        #[doc = "Field `RISE_DELAY` reader - Delay value on rising edge of q_channel data 0: 1 cycle 1: 2 cycles …"]
        pub type RISE_DELAY_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Delay value on rising edge of q_channel data 0: 1 cycle 1: 2 cycles …"]
            #[inline(always)]
            pub fn rise_delay(&self) -> RISE_DELAY_R {
                RISE_DELAY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rise_delay_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rise_delay_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RISE_DELAY_Q_SPEC;
        impl crate::RegisterSpec for RISE_DELAY_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rise_delay_q::R`](R) reader structure"]
        impl crate::Readable for RISE_DELAY_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rise_delay_q::W`](W) writer structure"]
        impl crate::Writable for RISE_DELAY_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets rise_delay_q to value 0"]
        impl crate::Resettable for RISE_DELAY_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "fall_delay_q (rw) register accessor: delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fall_delay_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fall_delay_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fall_delay_q`]
module"]
    pub type FALL_DELAY_Q = crate::Reg<fall_delay_q::FALL_DELAY_Q_SPEC>;
    #[doc = "delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data"]
    pub mod fall_delay_q {
        #[doc = "Register `fall_delay_q` reader"]
        pub type R = crate::R<FALL_DELAY_Q_SPEC>;
        #[doc = "Register `fall_delay_q` writer"]
        pub type W = crate::W<FALL_DELAY_Q_SPEC>;
        #[doc = "Field `FALL_DELAY` reader - Delay value on falling edge of q_channel data 0: 1 cycle 1: 2 cycles …"]
        pub type FALL_DELAY_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - Delay value on falling edge of q_channel data 0: 1 cycle 1: 2 cycles …"]
            #[inline(always)]
            pub fn fall_delay(&self) -> FALL_DELAY_R {
                FALL_DELAY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fall_delay_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fall_delay_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FALL_DELAY_Q_SPEC;
        impl crate::RegisterSpec for FALL_DELAY_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`fall_delay_q::R`](R) reader structure"]
        impl crate::Readable for FALL_DELAY_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`fall_delay_q::W`](W) writer structure"]
        impl crate::Writable for FALL_DELAY_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets fall_delay_q to value 0"]
        impl crate::Resettable for FALL_DELAY_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sample_rise_q (rw) register accessor: sample value on rising edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_rise_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_rise_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_rise_q`]
module"]
    pub type SAMPLE_RISE_Q = crate::Reg<sample_rise_q::SAMPLE_RISE_Q_SPEC>;
    #[doc = "sample value on rising edge of rectify signal"]
    pub mod sample_rise_q {
        #[doc = "Register `sample_rise_q` reader"]
        pub type R = crate::R<SAMPLE_RISE_Q_SPEC>;
        #[doc = "Register `sample_rise_q` writer"]
        pub type W = crate::W<SAMPLE_RISE_Q_SPEC>;
        #[doc = "Field `VALUE` reader - sample value on rising edge of rectify signal"]
        pub type VALUE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 8:31 - sample value on rising edge of rectify signal"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "sample value on rising edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_rise_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_rise_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SAMPLE_RISE_Q_SPEC;
        impl crate::RegisterSpec for SAMPLE_RISE_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sample_rise_q::R`](R) reader structure"]
        impl crate::Readable for SAMPLE_RISE_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sample_rise_q::W`](W) writer structure"]
        impl crate::Writable for SAMPLE_RISE_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sample_rise_q to value 0"]
        impl crate::Resettable for SAMPLE_RISE_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sample_fall_q (rw) register accessor: sample value on falling edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_fall_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_fall_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_fall_q`]
module"]
    pub type SAMPLE_FALL_Q = crate::Reg<sample_fall_q::SAMPLE_FALL_Q_SPEC>;
    #[doc = "sample value on falling edge of rectify signal"]
    pub mod sample_fall_q {
        #[doc = "Register `sample_fall_q` reader"]
        pub type R = crate::R<SAMPLE_FALL_Q_SPEC>;
        #[doc = "Register `sample_fall_q` writer"]
        pub type W = crate::W<SAMPLE_FALL_Q_SPEC>;
        #[doc = "Field `VALUE` reader - sample value on falling edge of rectify signal"]
        pub type VALUE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 8:31 - sample value on falling edge of rectify signal"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new((self.bits >> 8) & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "sample value on falling edge of rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_fall_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_fall_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SAMPLE_FALL_Q_SPEC;
        impl crate::RegisterSpec for SAMPLE_FALL_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sample_fall_q::R`](R) reader structure"]
        impl crate::Readable for SAMPLE_FALL_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sample_fall_q::W`](W) writer structure"]
        impl crate::Writable for SAMPLE_FALL_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sample_fall_q to value 0"]
        impl crate::Resettable for SAMPLE_FALL_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "acc_cnt_q (rw) register accessor: number of accumulation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_cnt_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_cnt_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acc_cnt_q`]
module"]
    pub type ACC_CNT_Q = crate::Reg<acc_cnt_q::ACC_CNT_Q_SPEC>;
    #[doc = "number of accumulation"]
    pub mod acc_cnt_q {
        #[doc = "Register `acc_cnt_q` reader"]
        pub type R = crate::R<ACC_CNT_Q_SPEC>;
        #[doc = "Register `acc_cnt_q` writer"]
        pub type W = crate::W<ACC_CNT_Q_SPEC>;
        #[doc = "Field `CNT_POS` reader - sample number during the positive of rectify signal 1: 1 2: 2 …"]
        pub type CNT_POS_R = crate::FieldReader<u16>;
        #[doc = "Field `CNT_NEG` reader - sample number during the negtive of rectify signal 1: 1 2: 2 …"]
        pub type CNT_NEG_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - sample number during the positive of rectify signal 1: 1 2: 2 …"]
            #[inline(always)]
            pub fn cnt_pos(&self) -> CNT_POS_R {
                CNT_POS_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - sample number during the negtive of rectify signal 1: 1 2: 2 …"]
            #[inline(always)]
            pub fn cnt_neg(&self) -> CNT_NEG_R {
                CNT_NEG_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "number of accumulation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_cnt_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_cnt_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ACC_CNT_Q_SPEC;
        impl crate::RegisterSpec for ACC_CNT_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`acc_cnt_q::R`](R) reader structure"]
        impl crate::Readable for ACC_CNT_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`acc_cnt_q::W`](W) writer structure"]
        impl crate::Writable for ACC_CNT_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets acc_cnt_q to value 0"]
        impl crate::Resettable for ACC_CNT_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "sign_cnt_q (rw) register accessor: sample counter of opposite sign with rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sign_cnt_q::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sign_cnt_q::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sign_cnt_q`]
module"]
    pub type SIGN_CNT_Q = crate::Reg<sign_cnt_q::SIGN_CNT_Q_SPEC>;
    #[doc = "sample counter of opposite sign with rectify signal"]
    pub mod sign_cnt_q {
        #[doc = "Register `sign_cnt_q` reader"]
        pub type R = crate::R<SIGN_CNT_Q_SPEC>;
        #[doc = "Register `sign_cnt_q` writer"]
        pub type W = crate::W<SIGN_CNT_Q_SPEC>;
        #[doc = "Field `CNT_POS` reader - Negative sample counter during positive rectify signal"]
        pub type CNT_POS_R = crate::FieldReader<u16>;
        #[doc = "Field `CNT_NEG` reader - Positive sample counter during negative rectify signal"]
        pub type CNT_NEG_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bits 0:15 - Negative sample counter during positive rectify signal"]
            #[inline(always)]
            pub fn cnt_pos(&self) -> CNT_POS_R {
                CNT_POS_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - Positive sample counter during negative rectify signal"]
            #[inline(always)]
            pub fn cnt_neg(&self) -> CNT_NEG_R {
                CNT_NEG_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "sample counter of opposite sign with rectify signal\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sign_cnt_q::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sign_cnt_q::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SIGN_CNT_Q_SPEC;
        impl crate::RegisterSpec for SIGN_CNT_Q_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sign_cnt_q::R`](R) reader structure"]
        impl crate::Readable for SIGN_CNT_Q_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sign_cnt_q::W`](W) writer structure"]
        impl crate::Writable for SIGN_CNT_Q_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets sign_cnt_q to value 0"]
        impl crate::Resettable for SIGN_CNT_Q_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "amp_max (rw) register accessor: the maximum of acc amplitude\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_max::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amp_max`]
module"]
    pub type AMP_MAX = crate::Reg<amp_max::AMP_MAX_SPEC>;
    #[doc = "the maximum of acc amplitude"]
    pub mod amp_max {
        #[doc = "Register `amp_max` reader"]
        pub type R = crate::R<AMP_MAX_SPEC>;
        #[doc = "Register `amp_max` writer"]
        pub type W = crate::W<AMP_MAX_SPEC>;
        #[doc = "Field `MAX` reader - the maximum of acc amplitude"]
        pub type MAX_R = crate::FieldReader<u32>;
        #[doc = "Field `MAX` writer - the maximum of acc amplitude"]
        pub type MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the maximum of acc amplitude"]
            #[inline(always)]
            pub fn max(&self) -> MAX_R {
                MAX_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the maximum of acc amplitude"]
            #[inline(always)]
            #[must_use]
            pub fn max(&mut self) -> MAX_W<AMP_MAX_SPEC> {
                MAX_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "the maximum of acc amplitude\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_max::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AMP_MAX_SPEC;
        impl crate::RegisterSpec for AMP_MAX_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`amp_max::R`](R) reader structure"]
        impl crate::Readable for AMP_MAX_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`amp_max::W`](W) writer structure"]
        impl crate::Writable for AMP_MAX_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets amp_max to value 0x0100_0000"]
        impl crate::Resettable for AMP_MAX_SPEC {
            const RESET_VALUE: u32 = 0x0100_0000;
        }
    }
    #[doc = "amp_min (rw) register accessor: the minimum of acc amplitude\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_min::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amp_min`]
module"]
    pub type AMP_MIN = crate::Reg<amp_min::AMP_MIN_SPEC>;
    #[doc = "the minimum of acc amplitude"]
    pub mod amp_min {
        #[doc = "Register `amp_min` reader"]
        pub type R = crate::R<AMP_MIN_SPEC>;
        #[doc = "Register `amp_min` writer"]
        pub type W = crate::W<AMP_MIN_SPEC>;
        #[doc = "Field `MIN` reader - the minimum of acc amplitude"]
        pub type MIN_R = crate::FieldReader<u32>;
        #[doc = "Field `MIN` writer - the minimum of acc amplitude"]
        pub type MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - the minimum of acc amplitude"]
            #[inline(always)]
            pub fn min(&self) -> MIN_R {
                MIN_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - the minimum of acc amplitude"]
            #[inline(always)]
            #[must_use]
            pub fn min(&mut self) -> MIN_W<AMP_MIN_SPEC> {
                MIN_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "the minimum of acc amplitude\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amp_min::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amp_min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct AMP_MIN_SPEC;
        impl crate::RegisterSpec for AMP_MIN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`amp_min::R`](R) reader structure"]
        impl crate::Readable for AMP_MIN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`amp_min::W`](W) writer structure"]
        impl crate::Writable for AMP_MIN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets amp_min to value 0x0040_0000"]
        impl crate::Resettable for AMP_MIN_SPEC {
            const RESET_VALUE: u32 = 0x0040_0000;
        }
    }
    #[doc = "int_en (rw) register accessor: the interrupt mask control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_en`]
module"]
    pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
    #[doc = "the interrupt mask control"]
    pub mod int_en {
        #[doc = "Register `int_en` reader"]
        pub type R = crate::R<INT_EN_SPEC>;
        #[doc = "Register `int_en` writer"]
        pub type W = crate::W<INT_EN_SPEC>;
        #[doc = "Field `ACC_AMP_OVL_EN` reader - accumulate ample underflow interrupt enable"]
        pub type ACC_AMP_OVL_EN_R = crate::BitReader;
        #[doc = "Field `ACC_AMP_OVL_EN` writer - accumulate ample underflow interrupt enable"]
        pub type ACC_AMP_OVL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_AMP_OVH_EN` reader - accumulate ample overflow interrupt enable"]
        pub type ACC_AMP_OVH_EN_R = crate::BitReader;
        #[doc = "Field `ACC_AMP_OVH_EN` writer - accumulate ample overflow interrupt enable"]
        pub type ACC_AMP_OVH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_Q_OVL_EN` reader - q_channel accumulate underflow interrupt enable"]
        pub type ACC_VLD_Q_OVL_EN_R = crate::BitReader;
        #[doc = "Field `ACC_VLD_Q_OVL_EN` writer - q_channel accumulate underflow interrupt enable"]
        pub type ACC_VLD_Q_OVL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_I_OVL_EN` reader - i_channel accumulate underflow interrupt enable"]
        pub type ACC_VLD_I_OVL_EN_R = crate::BitReader;
        #[doc = "Field `ACC_VLD_I_OVL_EN` writer - i_channel accumulate underflow interrupt enable"]
        pub type ACC_VLD_I_OVL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_Q_OVH_EN` reader - q_channel accumulate overflow interrupt enable"]
        pub type ACC_VLD_Q_OVH_EN_R = crate::BitReader;
        #[doc = "Field `ACC_VLD_Q_OVH_EN` writer - q_channel accumulate overflow interrupt enable"]
        pub type ACC_VLD_Q_OVH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_I_OVH_EN` reader - i_channel accumulate overflow interrupt enable"]
        pub type ACC_VLD_I_OVH_EN_R = crate::BitReader;
        #[doc = "Field `ACC_VLD_I_OVH_EN` writer - i_channel accumulate overflow interrupt enable"]
        pub type ACC_VLD_I_OVH_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_FALLING_Q_EN` reader - q_channel falling edge interrupt enable"]
        pub type SAMPLE_FALLING_Q_EN_R = crate::BitReader;
        #[doc = "Field `SAMPLE_FALLING_Q_EN` writer - q_channel falling edge interrupt enable"]
        pub type SAMPLE_FALLING_Q_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_RISING_Q_EN` reader - q_channel rising edge interrupt enable"]
        pub type SAMPLE_RISING_Q_EN_R = crate::BitReader;
        #[doc = "Field `SAMPLE_RISING_Q_EN` writer - q_channel rising edge interrupt enable"]
        pub type SAMPLE_RISING_Q_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_FALLING_I_EN` reader - i_channel falling edge interrupt enable"]
        pub type SAMPLE_FALLING_I_EN_R = crate::BitReader;
        #[doc = "Field `SAMPLE_FALLING_I_EN` writer - i_channel falling edge interrupt enable"]
        pub type SAMPLE_FALLING_I_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_RISING_I_EN` reader - i_channel rising edge interrupt enable"]
        pub type SAMPLE_RISING_I_EN_R = crate::BitReader;
        #[doc = "Field `SAMPLE_RISING_I_EN` writer - i_channel rising edge interrupt enable"]
        pub type SAMPLE_RISING_I_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FALLING_DELAY_Q_EN` reader - q_channel delayed rectify signal falling edge interrupt enable"]
        pub type FALLING_DELAY_Q_EN_R = crate::BitReader;
        #[doc = "Field `FALLING_DELAY_Q_EN` writer - q_channel delayed rectify signal falling edge interrupt enable"]
        pub type FALLING_DELAY_Q_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RISING_DELAY_Q_EN` reader - q_channel delayed rectify signal rising edge interrupt enable"]
        pub type RISING_DELAY_Q_EN_R = crate::BitReader;
        #[doc = "Field `RISING_DELAY_Q_EN` writer - q_channel delayed rectify signal rising edge interrupt enable"]
        pub type RISING_DELAY_Q_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FALLING_DELAY_I_EN` reader - i_channel delayed rectify signal falling edge interrupt enable"]
        pub type FALLING_DELAY_I_EN_R = crate::BitReader;
        #[doc = "Field `FALLING_DELAY_I_EN` writer - i_channel delayed rectify signal falling edge interrupt enable"]
        pub type FALLING_DELAY_I_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RISING_DELAY_I_EN` reader - i_channel delayed rectify signal rising edge interrupt enable"]
        pub type RISING_DELAY_I_EN_R = crate::BitReader;
        #[doc = "Field `RISING_DELAY_I_EN` writer - i_channel delayed rectify signal rising edge interrupt enable"]
        pub type RISING_DELAY_I_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_Q_EN` reader - q_channel accumulate valid interrupt enable for i_channel"]
        pub type ACC_VLD_Q_EN_R = crate::BitReader;
        #[doc = "Field `ACC_VLD_Q_EN` writer - q_channel accumulate valid interrupt enable for i_channel"]
        pub type ACC_VLD_Q_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_I_EN` reader - i_channel accumulate valid interrupt enable for i_channel"]
        pub type ACC_VLD_I_EN_R = crate::BitReader;
        #[doc = "Field `ACC_VLD_I_EN` writer - i_channel accumulate valid interrupt enable for i_channel"]
        pub type ACC_VLD_I_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `INT_EN` reader - enable interrupt output"]
        pub type INT_EN_R = crate::BitReader;
        #[doc = "Field `INT_EN` writer - enable interrupt output"]
        pub type INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - accumulate ample underflow interrupt enable"]
            #[inline(always)]
            pub fn acc_amp_ovl_en(&self) -> ACC_AMP_OVL_EN_R {
                ACC_AMP_OVL_EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - accumulate ample overflow interrupt enable"]
            #[inline(always)]
            pub fn acc_amp_ovh_en(&self) -> ACC_AMP_OVH_EN_R {
                ACC_AMP_OVH_EN_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - q_channel accumulate underflow interrupt enable"]
            #[inline(always)]
            pub fn acc_vld_q_ovl_en(&self) -> ACC_VLD_Q_OVL_EN_R {
                ACC_VLD_Q_OVL_EN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - i_channel accumulate underflow interrupt enable"]
            #[inline(always)]
            pub fn acc_vld_i_ovl_en(&self) -> ACC_VLD_I_OVL_EN_R {
                ACC_VLD_I_OVL_EN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - q_channel accumulate overflow interrupt enable"]
            #[inline(always)]
            pub fn acc_vld_q_ovh_en(&self) -> ACC_VLD_Q_OVH_EN_R {
                ACC_VLD_Q_OVH_EN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - i_channel accumulate overflow interrupt enable"]
            #[inline(always)]
            pub fn acc_vld_i_ovh_en(&self) -> ACC_VLD_I_OVH_EN_R {
                ACC_VLD_I_OVH_EN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - q_channel falling edge interrupt enable"]
            #[inline(always)]
            pub fn sample_falling_q_en(&self) -> SAMPLE_FALLING_Q_EN_R {
                SAMPLE_FALLING_Q_EN_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - q_channel rising edge interrupt enable"]
            #[inline(always)]
            pub fn sample_rising_q_en(&self) -> SAMPLE_RISING_Q_EN_R {
                SAMPLE_RISING_Q_EN_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - i_channel falling edge interrupt enable"]
            #[inline(always)]
            pub fn sample_falling_i_en(&self) -> SAMPLE_FALLING_I_EN_R {
                SAMPLE_FALLING_I_EN_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - i_channel rising edge interrupt enable"]
            #[inline(always)]
            pub fn sample_rising_i_en(&self) -> SAMPLE_RISING_I_EN_R {
                SAMPLE_RISING_I_EN_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - q_channel delayed rectify signal falling edge interrupt enable"]
            #[inline(always)]
            pub fn falling_delay_q_en(&self) -> FALLING_DELAY_Q_EN_R {
                FALLING_DELAY_Q_EN_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - q_channel delayed rectify signal rising edge interrupt enable"]
            #[inline(always)]
            pub fn rising_delay_q_en(&self) -> RISING_DELAY_Q_EN_R {
                RISING_DELAY_Q_EN_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - i_channel delayed rectify signal falling edge interrupt enable"]
            #[inline(always)]
            pub fn falling_delay_i_en(&self) -> FALLING_DELAY_I_EN_R {
                FALLING_DELAY_I_EN_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - i_channel delayed rectify signal rising edge interrupt enable"]
            #[inline(always)]
            pub fn rising_delay_i_en(&self) -> RISING_DELAY_I_EN_R {
                RISING_DELAY_I_EN_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - q_channel accumulate valid interrupt enable for i_channel"]
            #[inline(always)]
            pub fn acc_vld_q_en(&self) -> ACC_VLD_Q_EN_R {
                ACC_VLD_Q_EN_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - i_channel accumulate valid interrupt enable for i_channel"]
            #[inline(always)]
            pub fn acc_vld_i_en(&self) -> ACC_VLD_I_EN_R {
                ACC_VLD_I_EN_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 31 - enable interrupt output"]
            #[inline(always)]
            pub fn int_en(&self) -> INT_EN_R {
                INT_EN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - accumulate ample underflow interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn acc_amp_ovl_en(&mut self) -> ACC_AMP_OVL_EN_W<INT_EN_SPEC> {
                ACC_AMP_OVL_EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - accumulate ample overflow interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn acc_amp_ovh_en(&mut self) -> ACC_AMP_OVH_EN_W<INT_EN_SPEC> {
                ACC_AMP_OVH_EN_W::new(self, 1)
            }
            #[doc = "Bit 2 - q_channel accumulate underflow interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_q_ovl_en(&mut self) -> ACC_VLD_Q_OVL_EN_W<INT_EN_SPEC> {
                ACC_VLD_Q_OVL_EN_W::new(self, 2)
            }
            #[doc = "Bit 3 - i_channel accumulate underflow interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_i_ovl_en(&mut self) -> ACC_VLD_I_OVL_EN_W<INT_EN_SPEC> {
                ACC_VLD_I_OVL_EN_W::new(self, 3)
            }
            #[doc = "Bit 4 - q_channel accumulate overflow interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_q_ovh_en(&mut self) -> ACC_VLD_Q_OVH_EN_W<INT_EN_SPEC> {
                ACC_VLD_Q_OVH_EN_W::new(self, 4)
            }
            #[doc = "Bit 5 - i_channel accumulate overflow interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_i_ovh_en(&mut self) -> ACC_VLD_I_OVH_EN_W<INT_EN_SPEC> {
                ACC_VLD_I_OVH_EN_W::new(self, 5)
            }
            #[doc = "Bit 6 - q_channel falling edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn sample_falling_q_en(&mut self) -> SAMPLE_FALLING_Q_EN_W<INT_EN_SPEC> {
                SAMPLE_FALLING_Q_EN_W::new(self, 6)
            }
            #[doc = "Bit 7 - q_channel rising edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn sample_rising_q_en(&mut self) -> SAMPLE_RISING_Q_EN_W<INT_EN_SPEC> {
                SAMPLE_RISING_Q_EN_W::new(self, 7)
            }
            #[doc = "Bit 8 - i_channel falling edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn sample_falling_i_en(&mut self) -> SAMPLE_FALLING_I_EN_W<INT_EN_SPEC> {
                SAMPLE_FALLING_I_EN_W::new(self, 8)
            }
            #[doc = "Bit 9 - i_channel rising edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn sample_rising_i_en(&mut self) -> SAMPLE_RISING_I_EN_W<INT_EN_SPEC> {
                SAMPLE_RISING_I_EN_W::new(self, 9)
            }
            #[doc = "Bit 10 - q_channel delayed rectify signal falling edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn falling_delay_q_en(&mut self) -> FALLING_DELAY_Q_EN_W<INT_EN_SPEC> {
                FALLING_DELAY_Q_EN_W::new(self, 10)
            }
            #[doc = "Bit 11 - q_channel delayed rectify signal rising edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn rising_delay_q_en(&mut self) -> RISING_DELAY_Q_EN_W<INT_EN_SPEC> {
                RISING_DELAY_Q_EN_W::new(self, 11)
            }
            #[doc = "Bit 12 - i_channel delayed rectify signal falling edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn falling_delay_i_en(&mut self) -> FALLING_DELAY_I_EN_W<INT_EN_SPEC> {
                FALLING_DELAY_I_EN_W::new(self, 12)
            }
            #[doc = "Bit 13 - i_channel delayed rectify signal rising edge interrupt enable"]
            #[inline(always)]
            #[must_use]
            pub fn rising_delay_i_en(&mut self) -> RISING_DELAY_I_EN_W<INT_EN_SPEC> {
                RISING_DELAY_I_EN_W::new(self, 13)
            }
            #[doc = "Bit 14 - q_channel accumulate valid interrupt enable for i_channel"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_q_en(&mut self) -> ACC_VLD_Q_EN_W<INT_EN_SPEC> {
                ACC_VLD_Q_EN_W::new(self, 14)
            }
            #[doc = "Bit 15 - i_channel accumulate valid interrupt enable for i_channel"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_i_en(&mut self) -> ACC_VLD_I_EN_W<INT_EN_SPEC> {
                ACC_VLD_I_EN_W::new(self, 15)
            }
            #[doc = "Bit 31 - enable interrupt output"]
            #[inline(always)]
            #[must_use]
            pub fn int_en(&mut self) -> INT_EN_W<INT_EN_SPEC> {
                INT_EN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "the interrupt mask control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_EN_SPEC;
        impl crate::RegisterSpec for INT_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_en::R`](R) reader structure"]
        impl crate::Readable for INT_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_en::W`](W) writer structure"]
        impl crate::Writable for INT_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets int_en to value 0"]
        impl crate::Resettable for INT_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adc_int_state (rw) register accessor: the interrupt state\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_int_state::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_int_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_int_state`]
module"]
    pub type ADC_INT_STATE = crate::Reg<adc_int_state::ADC_INT_STATE_SPEC>;
    #[doc = "the interrupt state"]
    pub mod adc_int_state {
        #[doc = "Register `adc_int_state` reader"]
        pub type R = crate::R<ADC_INT_STATE_SPEC>;
        #[doc = "Register `adc_int_state` writer"]
        pub type W = crate::W<ADC_INT_STATE_SPEC>;
        #[doc = "Field `ACC_AMP_OVL_STA` writer - accumulate ample underflow interrupt status"]
        pub type ACC_AMP_OVL_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_AMP_OVH_STA` writer - accumulate ample overflow interrupt status"]
        pub type ACC_AMP_OVH_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_Q_OVL_STA` writer - q_channel accumulate underflow interrupt status"]
        pub type ACC_VLD_Q_OVL_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_I_OVL_STA` writer - i_channel accumulate underflow interrupt status"]
        pub type ACC_VLD_I_OVL_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_Q_OVH_STA` writer - q_channel accumulate overflow interrupt status"]
        pub type ACC_VLD_Q_OVH_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_I_OVH_STA` writer - i_channel accumulate overflow interrupt status"]
        pub type ACC_VLD_I_OVH_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_FALLING_Q_STA` writer - q_channel falling edge interrupt status"]
        pub type SAMPLE_FALLING_Q_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_RISING_Q_STA` writer - q_channel rising edge interrupt status"]
        pub type SAMPLE_RISING_Q_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_FALLING_I_STA` writer - i_channel falling edge interrupt status"]
        pub type SAMPLE_FALLING_I_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SAMPLE_RISING_I_STA` writer - i_channel rising edge interrupt status"]
        pub type SAMPLE_RISING_I_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FALLING_DELAY_Q_STA` writer - q_channel delayed rectify signal falling edge interrupt status"]
        pub type FALLING_DELAY_Q_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RISING_DELAY_Q_STA` writer - q_channel delayed rectify signal rising edge interrupt status"]
        pub type RISING_DELAY_Q_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FALLING_DELAY_I_STA` writer - i_channel delayed rectify signal falling edge interrupt status"]
        pub type FALLING_DELAY_I_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RISING_DELAY_I_STA` writer - i_channel delayed rectify signal rising edge interrupt status"]
        pub type RISING_DELAY_I_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_Q_STA` writer - q_channel accumulate valid interrupt status for i_channel"]
        pub type ACC_VLD_Q_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ACC_VLD_I_STA` writer - i_channel accumulate valid interrupt status for i_channel"]
        pub type ACC_VLD_I_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - accumulate ample underflow interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn acc_amp_ovl_sta(&mut self) -> ACC_AMP_OVL_STA_W<ADC_INT_STATE_SPEC> {
                ACC_AMP_OVL_STA_W::new(self, 0)
            }
            #[doc = "Bit 1 - accumulate ample overflow interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn acc_amp_ovh_sta(&mut self) -> ACC_AMP_OVH_STA_W<ADC_INT_STATE_SPEC> {
                ACC_AMP_OVH_STA_W::new(self, 1)
            }
            #[doc = "Bit 2 - q_channel accumulate underflow interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_q_ovl_sta(&mut self) -> ACC_VLD_Q_OVL_STA_W<ADC_INT_STATE_SPEC> {
                ACC_VLD_Q_OVL_STA_W::new(self, 2)
            }
            #[doc = "Bit 3 - i_channel accumulate underflow interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_i_ovl_sta(&mut self) -> ACC_VLD_I_OVL_STA_W<ADC_INT_STATE_SPEC> {
                ACC_VLD_I_OVL_STA_W::new(self, 3)
            }
            #[doc = "Bit 4 - q_channel accumulate overflow interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_q_ovh_sta(&mut self) -> ACC_VLD_Q_OVH_STA_W<ADC_INT_STATE_SPEC> {
                ACC_VLD_Q_OVH_STA_W::new(self, 4)
            }
            #[doc = "Bit 5 - i_channel accumulate overflow interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_i_ovh_sta(&mut self) -> ACC_VLD_I_OVH_STA_W<ADC_INT_STATE_SPEC> {
                ACC_VLD_I_OVH_STA_W::new(self, 5)
            }
            #[doc = "Bit 6 - q_channel falling edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn sample_falling_q_sta(&mut self) -> SAMPLE_FALLING_Q_STA_W<ADC_INT_STATE_SPEC> {
                SAMPLE_FALLING_Q_STA_W::new(self, 6)
            }
            #[doc = "Bit 7 - q_channel rising edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn sample_rising_q_sta(&mut self) -> SAMPLE_RISING_Q_STA_W<ADC_INT_STATE_SPEC> {
                SAMPLE_RISING_Q_STA_W::new(self, 7)
            }
            #[doc = "Bit 8 - i_channel falling edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn sample_falling_i_sta(&mut self) -> SAMPLE_FALLING_I_STA_W<ADC_INT_STATE_SPEC> {
                SAMPLE_FALLING_I_STA_W::new(self, 8)
            }
            #[doc = "Bit 9 - i_channel rising edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn sample_rising_i_sta(&mut self) -> SAMPLE_RISING_I_STA_W<ADC_INT_STATE_SPEC> {
                SAMPLE_RISING_I_STA_W::new(self, 9)
            }
            #[doc = "Bit 10 - q_channel delayed rectify signal falling edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn falling_delay_q_sta(&mut self) -> FALLING_DELAY_Q_STA_W<ADC_INT_STATE_SPEC> {
                FALLING_DELAY_Q_STA_W::new(self, 10)
            }
            #[doc = "Bit 11 - q_channel delayed rectify signal rising edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn rising_delay_q_sta(&mut self) -> RISING_DELAY_Q_STA_W<ADC_INT_STATE_SPEC> {
                RISING_DELAY_Q_STA_W::new(self, 11)
            }
            #[doc = "Bit 12 - i_channel delayed rectify signal falling edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn falling_delay_i_sta(&mut self) -> FALLING_DELAY_I_STA_W<ADC_INT_STATE_SPEC> {
                FALLING_DELAY_I_STA_W::new(self, 12)
            }
            #[doc = "Bit 13 - i_channel delayed rectify signal rising edge interrupt status"]
            #[inline(always)]
            #[must_use]
            pub fn rising_delay_i_sta(&mut self) -> RISING_DELAY_I_STA_W<ADC_INT_STATE_SPEC> {
                RISING_DELAY_I_STA_W::new(self, 13)
            }
            #[doc = "Bit 14 - q_channel accumulate valid interrupt status for i_channel"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_q_sta(&mut self) -> ACC_VLD_Q_STA_W<ADC_INT_STATE_SPEC> {
                ACC_VLD_Q_STA_W::new(self, 14)
            }
            #[doc = "Bit 15 - i_channel accumulate valid interrupt status for i_channel"]
            #[inline(always)]
            #[must_use]
            pub fn acc_vld_i_sta(&mut self) -> ACC_VLD_I_STA_W<ADC_INT_STATE_SPEC> {
                ACC_VLD_I_STA_W::new(self, 15)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "the interrupt state\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_int_state::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_int_state::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADC_INT_STATE_SPEC;
        impl crate::RegisterSpec for ADC_INT_STATE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adc_int_state::R`](R) reader structure"]
        impl crate::Readable for ADC_INT_STATE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adc_int_state::W`](W) writer structure"]
        impl crate::Writable for ADC_INT_STATE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adc_int_state to value 0"]
        impl crate::Resettable for ADC_INT_STATE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "PLB"]
pub struct PLB {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PLB {}
impl PLB {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const plb::RegisterBlock = 0xf032_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const plb::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PLB {
    type Target = plb::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PLB {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PLB").finish()
    }
}
#[doc = "PLB"]
pub mod plb {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        type_a: (),
        _reserved1: [u8; 0x0400],
        type_b: [TYPE_B; 4],
    }
    impl RegisterBlock {
        #[doc = "0x00..0x50 - no description available"]
        #[inline(always)]
        pub const fn type_a(&self, n: usize) -> &TYPE_A {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe { &*(self as *const Self).cast::<u8>().add(0).add(32 * n).cast() }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x50 - no description available"]
        #[inline(always)]
        pub fn type_a_iter(&self) -> impl Iterator<Item = &TYPE_A> {
            (0..4).map(move |n| unsafe {
                &*(self as *const Self).cast::<u8>().add(0).add(32 * n).cast()
            })
        }
        #[doc = "0x400..0x480 - no description available"]
        #[inline(always)]
        pub const fn type_b(&self, n: usize) -> &TYPE_B {
            &self.type_b[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x400..0x480 - no description available"]
        #[inline(always)]
        pub fn type_b_iter(&self) -> impl Iterator<Item = &TYPE_B> {
            self.type_b.iter()
        }
    }
    #[doc = "no description available"]
    pub use self::type_a::TYPE_A;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod type_a {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct TYPE_A {
            lookup_table: [LOOKUP_TABLE; 4],
            sw_inject: SW_INJECT,
        }
        impl TYPE_A {
            #[doc = "0x00..0x10 - no description available"]
            #[inline(always)]
            pub const fn lookup_table(&self, n: usize) -> &LOOKUP_TABLE {
                &self.lookup_table[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x00..0x10 - no description available"]
            #[inline(always)]
            pub fn lookup_table_iter(&self) -> impl Iterator<Item = &LOOKUP_TABLE> {
                self.lookup_table.iter()
            }
            #[doc = "0x10 - TYPE A CHN&amp;index0 software inject"]
            #[inline(always)]
            pub const fn sw_inject(&self) -> &SW_INJECT {
                &self.sw_inject
            }
        }
        #[doc = "LOOKUP_TABLE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lookup_table::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lookup_table::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lookup_table`]
module"]
        pub type LOOKUP_TABLE = crate::Reg<lookup_table::LOOKUP_TABLE_SPEC>;
        #[doc = "no description available"]
        pub mod lookup_table {
            #[doc = "Register `LOOKUP_TABLE[%s]` reader"]
            pub type R = crate::R<LOOKUP_TABLE_SPEC>;
            #[doc = "Register `LOOKUP_TABLE[%s]` writer"]
            pub type W = crate::W<LOOKUP_TABLE_SPEC>;
            #[doc = "Field `LOOKUP_TABLE` reader - using 4 bit trig_in as lookup index. software can program this register as trig_in's true table."]
            pub type LOOKUP_TABLE_R = crate::FieldReader<u16>;
            #[doc = "Field `LOOKUP_TABLE` writer - using 4 bit trig_in as lookup index. software can program this register as trig_in's true table."]
            pub type LOOKUP_TABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - using 4 bit trig_in as lookup index. software can program this register as trig_in's true table."]
                #[inline(always)]
                pub fn lookup_table(&self) -> LOOKUP_TABLE_R {
                    LOOKUP_TABLE_R::new((self.bits & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - using 4 bit trig_in as lookup index. software can program this register as trig_in's true table."]
                #[inline(always)]
                #[must_use]
                pub fn lookup_table(&mut self) -> LOOKUP_TABLE_W<LOOKUP_TABLE_SPEC> {
                    LOOKUP_TABLE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lookup_table::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lookup_table::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LOOKUP_TABLE_SPEC;
            impl crate::RegisterSpec for LOOKUP_TABLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`lookup_table::R`](R) reader structure"]
            impl crate::Readable for LOOKUP_TABLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`lookup_table::W`](W) writer structure"]
            impl crate::Writable for LOOKUP_TABLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets LOOKUP_TABLE[%s]
to value 0"]
            impl crate::Resettable for LOOKUP_TABLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "sw_inject (rw) register accessor: TYPE A CHN&amp;index0 software inject\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_inject::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_inject::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_inject`]
module"]
        pub type SW_INJECT = crate::Reg<sw_inject::SW_INJECT_SPEC>;
        #[doc = "TYPE A CHN&amp;index0 software inject"]
        pub mod sw_inject {
            #[doc = "Register `sw_inject` reader"]
            pub type R = crate::R<SW_INJECT_SPEC>;
            #[doc = "Register `sw_inject` writer"]
            pub type W = crate::W<SW_INJECT_SPEC>;
            #[doc = "Field `SW_INJECT` reader - software can inject value to TYPEA's output"]
            pub type SW_INJECT_R = crate::FieldReader;
            #[doc = "Field `SW_INJECT` writer - software can inject value to TYPEA's output"]
            pub type SW_INJECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            impl R {
                #[doc = "Bits 0:3 - software can inject value to TYPEA's output"]
                #[inline(always)]
                pub fn sw_inject(&self) -> SW_INJECT_R {
                    SW_INJECT_R::new((self.bits & 0x0f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:3 - software can inject value to TYPEA's output"]
                #[inline(always)]
                #[must_use]
                pub fn sw_inject(&mut self) -> SW_INJECT_W<SW_INJECT_SPEC> {
                    SW_INJECT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "TYPE A CHN&amp;index0 software inject\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_inject::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_inject::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SW_INJECT_SPEC;
            impl crate::RegisterSpec for SW_INJECT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`sw_inject::R`](R) reader structure"]
            impl crate::Readable for SW_INJECT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`sw_inject::W`](W) writer structure"]
            impl crate::Writable for SW_INJECT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets sw_inject to value 0"]
            impl crate::Resettable for SW_INJECT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::type_b::TYPE_B;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod type_b {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct TYPE_B {
            lut: [LUT; 2],
            cmp: [CMP; 4],
            mode: MODE,
            sw_inject: SW_INJECT,
        }
        impl TYPE_B {
            #[doc = "0x00..0x08 - no description available"]
            #[inline(always)]
            pub const fn lut(&self, n: usize) -> &LUT {
                &self.lut[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x00..0x08 - no description available"]
            #[inline(always)]
            pub fn lut_iter(&self) -> impl Iterator<Item = &LUT> {
                self.lut.iter()
            }
            #[doc = "0x08..0x18 - no description available"]
            #[inline(always)]
            pub const fn cmp(&self, n: usize) -> &CMP {
                &self.cmp[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x08..0x18 - no description available"]
            #[inline(always)]
            pub fn cmp_iter(&self) -> impl Iterator<Item = &CMP> {
                self.cmp.iter()
            }
            #[doc = "0x18 - TYPE B CHN&amp;index0 mode ctrl"]
            #[inline(always)]
            pub const fn mode(&self) -> &MODE {
                &self.mode
            }
            #[doc = "0x1c - TYPE B CHN&amp;index0 software inject"]
            #[inline(always)]
            pub const fn sw_inject(&self) -> &SW_INJECT {
                &self.sw_inject
            }
        }
        #[doc = "LUT (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lut::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lut::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lut`]
module"]
        pub type LUT = crate::Reg<lut::LUT_SPEC>;
        #[doc = "no description available"]
        pub mod lut {
            #[doc = "Register `LUT[%s]` reader"]
            pub type R = crate::R<LUT_SPEC>;
            #[doc = "Register `LUT[%s]` writer"]
            pub type W = crate::W<LUT_SPEC>;
            #[doc = "Field `LOOKUP_TABLE` reader - lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in"]
            pub type LOOKUP_TABLE_R = crate::FieldReader<u32>;
            #[doc = "Field `LOOKUP_TABLE` writer - lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in"]
            pub type LOOKUP_TABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in"]
                #[inline(always)]
                pub fn lookup_table(&self) -> LOOKUP_TABLE_R {
                    LOOKUP_TABLE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in"]
                #[inline(always)]
                #[must_use]
                pub fn lookup_table(&mut self) -> LOOKUP_TABLE_W<LUT_SPEC> {
                    LOOKUP_TABLE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lut::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lut::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LUT_SPEC;
            impl crate::RegisterSpec for LUT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`lut::R`](R) reader structure"]
            impl crate::Readable for LUT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`lut::W`](W) writer structure"]
            impl crate::Writable for LUT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets LUT[%s]
to value 0"]
            impl crate::Resettable for LUT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CMP (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp`]
module"]
        pub type CMP = crate::Reg<cmp::CMP_SPEC>;
        #[doc = "no description available"]
        pub mod cmp {
            #[doc = "Register `CMP[%s]` reader"]
            pub type R = crate::R<CMP_SPEC>;
            #[doc = "Register `CMP[%s]` writer"]
            pub type W = crate::W<CMP_SPEC>;
            #[doc = "Field `CMP_VALUE` reader - cmp value, using as data unit operation"]
            pub type CMP_VALUE_R = crate::FieldReader<u32>;
            #[doc = "Field `CMP_VALUE` writer - cmp value, using as data unit operation"]
            pub type CMP_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - cmp value, using as data unit operation"]
                #[inline(always)]
                pub fn cmp_value(&self) -> CMP_VALUE_R {
                    CMP_VALUE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - cmp value, using as data unit operation"]
                #[inline(always)]
                #[must_use]
                pub fn cmp_value(&mut self) -> CMP_VALUE_W<CMP_SPEC> {
                    CMP_VALUE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CMP_SPEC;
            impl crate::RegisterSpec for CMP_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cmp::R`](R) reader structure"]
            impl crate::Readable for CMP_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cmp::W`](W) writer structure"]
            impl crate::Writable for CMP_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CMP[%s]
to value 0"]
            impl crate::Resettable for CMP_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "mode (rw) register accessor: TYPE B CHN&amp;index0 mode ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`]
module"]
        pub type MODE = crate::Reg<mode::MODE_SPEC>;
        #[doc = "TYPE B CHN&amp;index0 mode ctrl"]
        pub mod mode {
            #[doc = "Register `mode` reader"]
            pub type R = crate::R<MODE_SPEC>;
            #[doc = "Register `mode` writer"]
            pub type W = crate::W<MODE_SPEC>;
            #[doc = "Field `OUT0_SEL` reader - trig out 0 output type in current channel"]
            pub type OUT0_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT0_SEL` writer - trig out 0 output type in current channel"]
            pub type OUT0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `OUT1_SEL` reader - trig out 1 output type in current channel"]
            pub type OUT1_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT1_SEL` writer - trig out 1 output type in current channel"]
            pub type OUT1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `OUT2_SEL` reader - trig out 2 output type in current channel"]
            pub type OUT2_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT2_SEL` writer - trig out 2 output type in current channel"]
            pub type OUT2_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `OUT3_SEL` reader - trig out 3 output type in current channel"]
            pub type OUT3_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT3_SEL` writer - trig out 3 output type in current channel"]
            pub type OUT3_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            #[doc = "Field `OPT_SEL` reader - operation selection in data unit."]
            pub type OPT_SEL_R = crate::BitReader;
            #[doc = "Field `OPT_SEL` writer - operation selection in data unit."]
            pub type OPT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:3 - trig out 0 output type in current channel"]
                #[inline(always)]
                pub fn out0_sel(&self) -> OUT0_SEL_R {
                    OUT0_SEL_R::new((self.bits & 0x0f) as u8)
                }
                #[doc = "Bits 4:7 - trig out 1 output type in current channel"]
                #[inline(always)]
                pub fn out1_sel(&self) -> OUT1_SEL_R {
                    OUT1_SEL_R::new(((self.bits >> 4) & 0x0f) as u8)
                }
                #[doc = "Bits 8:11 - trig out 2 output type in current channel"]
                #[inline(always)]
                pub fn out2_sel(&self) -> OUT2_SEL_R {
                    OUT2_SEL_R::new(((self.bits >> 8) & 0x0f) as u8)
                }
                #[doc = "Bits 12:15 - trig out 3 output type in current channel"]
                #[inline(always)]
                pub fn out3_sel(&self) -> OUT3_SEL_R {
                    OUT3_SEL_R::new(((self.bits >> 12) & 0x0f) as u8)
                }
                #[doc = "Bit 16 - operation selection in data unit."]
                #[inline(always)]
                pub fn opt_sel(&self) -> OPT_SEL_R {
                    OPT_SEL_R::new(((self.bits >> 16) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:3 - trig out 0 output type in current channel"]
                #[inline(always)]
                #[must_use]
                pub fn out0_sel(&mut self) -> OUT0_SEL_W<MODE_SPEC> {
                    OUT0_SEL_W::new(self, 0)
                }
                #[doc = "Bits 4:7 - trig out 1 output type in current channel"]
                #[inline(always)]
                #[must_use]
                pub fn out1_sel(&mut self) -> OUT1_SEL_W<MODE_SPEC> {
                    OUT1_SEL_W::new(self, 4)
                }
                #[doc = "Bits 8:11 - trig out 2 output type in current channel"]
                #[inline(always)]
                #[must_use]
                pub fn out2_sel(&mut self) -> OUT2_SEL_W<MODE_SPEC> {
                    OUT2_SEL_W::new(self, 8)
                }
                #[doc = "Bits 12:15 - trig out 3 output type in current channel"]
                #[inline(always)]
                #[must_use]
                pub fn out3_sel(&mut self) -> OUT3_SEL_W<MODE_SPEC> {
                    OUT3_SEL_W::new(self, 12)
                }
                #[doc = "Bit 16 - operation selection in data unit."]
                #[inline(always)]
                #[must_use]
                pub fn opt_sel(&mut self) -> OPT_SEL_W<MODE_SPEC> {
                    OPT_SEL_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "TYPE B CHN&amp;index0 mode ctrl\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MODE_SPEC;
            impl crate::RegisterSpec for MODE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`mode::R`](R) reader structure"]
            impl crate::Readable for MODE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
            impl crate::Writable for MODE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets mode to value 0"]
            impl crate::Resettable for MODE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "sw_inject (rw) register accessor: TYPE B CHN&amp;index0 software inject\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_inject::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_inject::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_inject`]
module"]
        pub type SW_INJECT = crate::Reg<sw_inject::SW_INJECT_SPEC>;
        #[doc = "TYPE B CHN&amp;index0 software inject"]
        pub mod sw_inject {
            #[doc = "Register `sw_inject` reader"]
            pub type R = crate::R<SW_INJECT_SPEC>;
            #[doc = "Register `sw_inject` writer"]
            pub type W = crate::W<SW_INJECT_SPEC>;
            #[doc = "Field `SOFTWARE_INJECT` reader - data unit value can be changed if program this register"]
            pub type SOFTWARE_INJECT_R = crate::FieldReader<u32>;
            #[doc = "Field `SOFTWARE_INJECT` writer - data unit value can be changed if program this register"]
            pub type SOFTWARE_INJECT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - data unit value can be changed if program this register"]
                #[inline(always)]
                pub fn software_inject(&self) -> SOFTWARE_INJECT_R {
                    SOFTWARE_INJECT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - data unit value can be changed if program this register"]
                #[inline(always)]
                #[must_use]
                pub fn software_inject(&mut self) -> SOFTWARE_INJECT_W<SW_INJECT_SPEC> {
                    SOFTWARE_INJECT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "TYPE B CHN&amp;index0 software inject\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_inject::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_inject::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SW_INJECT_SPEC;
            impl crate::RegisterSpec for SW_INJECT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`sw_inject::R`](R) reader structure"]
            impl crate::Readable for SW_INJECT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`sw_inject::W`](W) writer structure"]
            impl crate::Writable for SW_INJECT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets sw_inject to value 0"]
            impl crate::Resettable for SW_INJECT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "SYNT"]
pub struct SYNT {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SYNT {}
impl SYNT {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const synt::RegisterBlock = 0xf032_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const synt::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SYNT {
    type Target = synt::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SYNT {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYNT").finish()
    }
}
#[doc = "SYNT"]
pub mod synt {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        gcr: GCR,
        rld: RLD,
        timestamp_new: TIMESTAMP_NEW,
        cnt: CNT,
        timestamp_sav: TIMESTAMP_SAV,
        timestamp_cur: TIMESTAMP_CUR,
        _reserved6: [u8; 0x08],
        cmp: [CMP; 4],
    }
    impl RegisterBlock {
        #[doc = "0x00 - Global control register"]
        #[inline(always)]
        pub const fn gcr(&self) -> &GCR {
            &self.gcr
        }
        #[doc = "0x04 - Counter reload register"]
        #[inline(always)]
        pub const fn rld(&self) -> &RLD {
            &self.rld
        }
        #[doc = "0x08 - timestamp new value register"]
        #[inline(always)]
        pub const fn timestamp_new(&self) -> &TIMESTAMP_NEW {
            &self.timestamp_new
        }
        #[doc = "0x0c - Counter"]
        #[inline(always)]
        pub const fn cnt(&self) -> &CNT {
            &self.cnt
        }
        #[doc = "0x10 - timestamp trig save value"]
        #[inline(always)]
        pub const fn timestamp_sav(&self) -> &TIMESTAMP_SAV {
            &self.timestamp_sav
        }
        #[doc = "0x14 - timestamp read value"]
        #[inline(always)]
        pub const fn timestamp_cur(&self) -> &TIMESTAMP_CUR {
            &self.timestamp_cur
        }
        #[doc = "0x20..0x30 - no description available"]
        #[inline(always)]
        pub const fn cmp(&self, n: usize) -> &CMP {
            &self.cmp[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x20..0x30 - no description available"]
        #[inline(always)]
        pub fn cmp_iter(&self) -> impl Iterator<Item = &CMP> {
            self.cmp.iter()
        }
    }
    #[doc = "gcr (rw) register accessor: Global control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr`]
module"]
    pub type GCR = crate::Reg<gcr::GCR_SPEC>;
    #[doc = "Global control register"]
    pub mod gcr {
        #[doc = "Register `gcr` reader"]
        pub type R = crate::R<GCR_SPEC>;
        #[doc = "Register `gcr` writer"]
        pub type W = crate::W<GCR_SPEC>;
        #[doc = "Field `CEN` reader - 1- Enable counter"]
        pub type CEN_R = crate::BitReader;
        #[doc = "Field `CEN` writer - 1- Enable counter"]
        pub type CEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CRST` reader - 1- Reset counter"]
        pub type CRST_R = crate::BitReader;
        #[doc = "Field `CRST` writer - 1- Reset counter"]
        pub type CRST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `COUNTER_DEBUG_EN` reader - set to enable cpu_debug_mode to stop the counter"]
        pub type COUNTER_DEBUG_EN_R = crate::BitReader;
        #[doc = "Field `COUNTER_DEBUG_EN` writer - set to enable cpu_debug_mode to stop the counter"]
        pub type COUNTER_DEBUG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIMESTAMP_ENABLE` reader - set to enable the timesamp , clr to stop"]
        pub type TIMESTAMP_ENABLE_R = crate::BitReader;
        #[doc = "Field `TIMESTAMP_ENABLE` writer - set to enable the timesamp , clr to stop"]
        pub type TIMESTAMP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIMESTAMP_DEBUG_EN` reader - set to enable cpu_debug_mode to stop the timesamp"]
        pub type TIMESTAMP_DEBUG_EN_R = crate::BitReader;
        #[doc = "Field `TIMESTAMP_DEBUG_EN` writer - set to enable cpu_debug_mode to stop the timesamp"]
        pub type TIMESTAMP_DEBUG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIMESTAMP_RESET` writer - reset timesamp to 0, auto clr"]
        pub type TIMESTAMP_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIMESTAMP_SET_NEW` writer - set the timesamp to new value, auto clr"]
        pub type TIMESTAMP_SET_NEW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIMESTAMP_DEC_NEW` writer - set to decrease the timesamp with new value, auto clr"]
        pub type TIMESTAMP_DEC_NEW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIMESTAMP_INC_NEW` writer - set to increase the timesamp with new value, auto clr"]
        pub type TIMESTAMP_INC_NEW_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - 1- Enable counter"]
            #[inline(always)]
            pub fn cen(&self) -> CEN_R {
                CEN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - 1- Reset counter"]
            #[inline(always)]
            pub fn crst(&self) -> CRST_R {
                CRST_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - set to enable cpu_debug_mode to stop the counter"]
            #[inline(always)]
            pub fn counter_debug_en(&self) -> COUNTER_DEBUG_EN_R {
                COUNTER_DEBUG_EN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 4 - set to enable the timesamp , clr to stop"]
            #[inline(always)]
            pub fn timestamp_enable(&self) -> TIMESTAMP_ENABLE_R {
                TIMESTAMP_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - set to enable cpu_debug_mode to stop the timesamp"]
            #[inline(always)]
            pub fn timestamp_debug_en(&self) -> TIMESTAMP_DEBUG_EN_R {
                TIMESTAMP_DEBUG_EN_R::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - 1- Enable counter"]
            #[inline(always)]
            #[must_use]
            pub fn cen(&mut self) -> CEN_W<GCR_SPEC> {
                CEN_W::new(self, 0)
            }
            #[doc = "Bit 1 - 1- Reset counter"]
            #[inline(always)]
            #[must_use]
            pub fn crst(&mut self) -> CRST_W<GCR_SPEC> {
                CRST_W::new(self, 1)
            }
            #[doc = "Bit 2 - set to enable cpu_debug_mode to stop the counter"]
            #[inline(always)]
            #[must_use]
            pub fn counter_debug_en(&mut self) -> COUNTER_DEBUG_EN_W<GCR_SPEC> {
                COUNTER_DEBUG_EN_W::new(self, 2)
            }
            #[doc = "Bit 4 - set to enable the timesamp , clr to stop"]
            #[inline(always)]
            #[must_use]
            pub fn timestamp_enable(&mut self) -> TIMESTAMP_ENABLE_W<GCR_SPEC> {
                TIMESTAMP_ENABLE_W::new(self, 4)
            }
            #[doc = "Bit 5 - set to enable cpu_debug_mode to stop the timesamp"]
            #[inline(always)]
            #[must_use]
            pub fn timestamp_debug_en(&mut self) -> TIMESTAMP_DEBUG_EN_W<GCR_SPEC> {
                TIMESTAMP_DEBUG_EN_W::new(self, 5)
            }
            #[doc = "Bit 28 - reset timesamp to 0, auto clr"]
            #[inline(always)]
            #[must_use]
            pub fn timestamp_reset(&mut self) -> TIMESTAMP_RESET_W<GCR_SPEC> {
                TIMESTAMP_RESET_W::new(self, 28)
            }
            #[doc = "Bit 29 - set the timesamp to new value, auto clr"]
            #[inline(always)]
            #[must_use]
            pub fn timestamp_set_new(&mut self) -> TIMESTAMP_SET_NEW_W<GCR_SPEC> {
                TIMESTAMP_SET_NEW_W::new(self, 29)
            }
            #[doc = "Bit 30 - set to decrease the timesamp with new value, auto clr"]
            #[inline(always)]
            #[must_use]
            pub fn timestamp_dec_new(&mut self) -> TIMESTAMP_DEC_NEW_W<GCR_SPEC> {
                TIMESTAMP_DEC_NEW_W::new(self, 30)
            }
            #[doc = "Bit 31 - set to increase the timesamp with new value, auto clr"]
            #[inline(always)]
            #[must_use]
            pub fn timestamp_inc_new(&mut self) -> TIMESTAMP_INC_NEW_W<GCR_SPEC> {
                TIMESTAMP_INC_NEW_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Global control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GCR_SPEC;
        impl crate::RegisterSpec for GCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gcr::R`](R) reader structure"]
        impl crate::Readable for GCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gcr::W`](W) writer structure"]
        impl crate::Writable for GCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets gcr to value 0"]
        impl crate::Resettable for GCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "rld (rw) register accessor: Counter reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rld::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rld::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rld`]
module"]
    pub type RLD = crate::Reg<rld::RLD_SPEC>;
    #[doc = "Counter reload register"]
    pub mod rld {
        #[doc = "Register `rld` reader"]
        pub type R = crate::R<RLD_SPEC>;
        #[doc = "Register `rld` writer"]
        pub type W = crate::W<RLD_SPEC>;
        #[doc = "Field `RLD` reader - counter reload value"]
        pub type RLD_R = crate::FieldReader<u32>;
        #[doc = "Field `RLD` writer - counter reload value"]
        pub type RLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - counter reload value"]
            #[inline(always)]
            pub fn rld(&self) -> RLD_R {
                RLD_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - counter reload value"]
            #[inline(always)]
            #[must_use]
            pub fn rld(&mut self) -> RLD_W<RLD_SPEC> {
                RLD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Counter reload register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rld::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rld::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RLD_SPEC;
        impl crate::RegisterSpec for RLD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rld::R`](R) reader structure"]
        impl crate::Readable for RLD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rld::W`](W) writer structure"]
        impl crate::Writable for RLD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets rld to value 0"]
        impl crate::Resettable for RLD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "timestamp_new (rw) register accessor: timestamp new value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_new::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_new::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_new`]
module"]
    pub type TIMESTAMP_NEW = crate::Reg<timestamp_new::TIMESTAMP_NEW_SPEC>;
    #[doc = "timestamp new value register"]
    pub mod timestamp_new {
        #[doc = "Register `timestamp_new` reader"]
        pub type R = crate::R<TIMESTAMP_NEW_SPEC>;
        #[doc = "Register `timestamp_new` writer"]
        pub type W = crate::W<TIMESTAMP_NEW_SPEC>;
        #[doc = "Field `VALUE` reader - new value for timesamp , can be used as set/inc/dec"]
        pub type VALUE_R = crate::FieldReader<u32>;
        #[doc = "Field `VALUE` writer - new value for timesamp , can be used as set/inc/dec"]
        pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - new value for timesamp , can be used as set/inc/dec"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - new value for timesamp , can be used as set/inc/dec"]
            #[inline(always)]
            #[must_use]
            pub fn value(&mut self) -> VALUE_W<TIMESTAMP_NEW_SPEC> {
                VALUE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp new value register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_new::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_new::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TIMESTAMP_NEW_SPEC;
        impl crate::RegisterSpec for TIMESTAMP_NEW_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timestamp_new::R`](R) reader structure"]
        impl crate::Readable for TIMESTAMP_NEW_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`timestamp_new::W`](W) writer structure"]
        impl crate::Writable for TIMESTAMP_NEW_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets timestamp_new to value 0"]
        impl crate::Resettable for TIMESTAMP_NEW_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cnt (rw) register accessor: Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt`]
module"]
    pub type CNT = crate::Reg<cnt::CNT_SPEC>;
    #[doc = "Counter"]
    pub mod cnt {
        #[doc = "Register `cnt` reader"]
        pub type R = crate::R<CNT_SPEC>;
        #[doc = "Register `cnt` writer"]
        pub type W = crate::W<CNT_SPEC>;
        #[doc = "Field `CNT` reader - counter"]
        pub type CNT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - counter"]
            #[inline(always)]
            pub fn cnt(&self) -> CNT_R {
                CNT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CNT_SPEC;
        impl crate::RegisterSpec for CNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cnt::R`](R) reader structure"]
        impl crate::Readable for CNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cnt::W`](W) writer structure"]
        impl crate::Writable for CNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cnt to value 0"]
        impl crate::Resettable for CNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "timestamp_sav (rw) register accessor: timestamp trig save value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_sav::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_sav::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_sav`]
module"]
    pub type TIMESTAMP_SAV = crate::Reg<timestamp_sav::TIMESTAMP_SAV_SPEC>;
    #[doc = "timestamp trig save value"]
    pub mod timestamp_sav {
        #[doc = "Register `timestamp_sav` reader"]
        pub type R = crate::R<TIMESTAMP_SAV_SPEC>;
        #[doc = "Register `timestamp_sav` writer"]
        pub type W = crate::W<TIMESTAMP_SAV_SPEC>;
        #[doc = "Field `VALUE` reader - use the trigger to save timesamp here"]
        pub type VALUE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - use the trigger to save timesamp here"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp trig save value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_sav::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_sav::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TIMESTAMP_SAV_SPEC;
        impl crate::RegisterSpec for TIMESTAMP_SAV_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timestamp_sav::R`](R) reader structure"]
        impl crate::Readable for TIMESTAMP_SAV_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`timestamp_sav::W`](W) writer structure"]
        impl crate::Writable for TIMESTAMP_SAV_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets timestamp_sav to value 0"]
        impl crate::Resettable for TIMESTAMP_SAV_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "timestamp_cur (rw) register accessor: timestamp read value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_cur::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_cur::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_cur`]
module"]
    pub type TIMESTAMP_CUR = crate::Reg<timestamp_cur::TIMESTAMP_CUR_SPEC>;
    #[doc = "timestamp read value"]
    pub mod timestamp_cur {
        #[doc = "Register `timestamp_cur` reader"]
        pub type R = crate::R<TIMESTAMP_CUR_SPEC>;
        #[doc = "Register `timestamp_cur` writer"]
        pub type W = crate::W<TIMESTAMP_CUR_SPEC>;
        #[doc = "Field `VALUE` reader - current timesamp value"]
        pub type VALUE_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - current timesamp value"]
            #[inline(always)]
            pub fn value(&self) -> VALUE_R {
                VALUE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "timestamp read value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_cur::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_cur::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TIMESTAMP_CUR_SPEC;
        impl crate::RegisterSpec for TIMESTAMP_CUR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`timestamp_cur::R`](R) reader structure"]
        impl crate::Readable for TIMESTAMP_CUR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`timestamp_cur::W`](W) writer structure"]
        impl crate::Writable for TIMESTAMP_CUR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets timestamp_cur to value 0"]
        impl crate::Resettable for TIMESTAMP_CUR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CMP (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp`]
module"]
    pub type CMP = crate::Reg<cmp::CMP_SPEC>;
    #[doc = "no description available"]
    pub mod cmp {
        #[doc = "Register `CMP[%s]` reader"]
        pub type R = crate::R<CMP_SPEC>;
        #[doc = "Register `CMP[%s]` writer"]
        pub type W = crate::W<CMP_SPEC>;
        #[doc = "Field `CMP` reader - comparator value, the output will assert when counter count to this value"]
        pub type CMP_R = crate::FieldReader<u32>;
        #[doc = "Field `CMP` writer - comparator value, the output will assert when counter count to this value"]
        pub type CMP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - comparator value, the output will assert when counter count to this value"]
            #[inline(always)]
            pub fn cmp(&self) -> CMP_R {
                CMP_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - comparator value, the output will assert when counter count to this value"]
            #[inline(always)]
            #[must_use]
            pub fn cmp(&mut self) -> CMP_W<CMP_SPEC> {
                CMP_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMP_SPEC;
        impl crate::RegisterSpec for CMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmp::R`](R) reader structure"]
        impl crate::Readable for CMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmp::W`](W) writer structure"]
        impl crate::Writable for CMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CMP[%s]
to value 0"]
        impl crate::Resettable for CMP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "SEI"]
pub struct SEI {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SEI {}
impl SEI {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const sei::RegisterBlock = 0xf032_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const sei::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SEI {
    type Target = sei::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SEI {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEI").finish()
    }
}
#[doc = "SEI"]
pub mod sei {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        ctrl: (),
        _reserved1: [u8; 0x3400],
        instr: [INSTR; 64],
        _reserved2: [u8; 0x0300],
        dat: (),
    }
    impl RegisterBlock {
        #[doc = "0x00..0x640 - no description available"]
        #[inline(always)]
        pub const fn ctrl(&self, n: usize) -> &CTRL {
            #[allow(clippy::no_effect)]
            [(); 2][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(0)
                    .add(1024 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x640 - no description available"]
        #[inline(always)]
        pub fn ctrl_iter(&self) -> impl Iterator<Item = &CTRL> {
            (0..2).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(0)
                    .add(1024 * n)
                    .cast()
            })
        }
        #[doc = "0x3400..0x3500 - no description available"]
        #[inline(always)]
        pub const fn instr(&self, n: usize) -> &INSTR {
            &self.instr[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x3400..0x3500 - no description available"]
        #[inline(always)]
        pub fn instr_iter(&self) -> impl Iterator<Item = &INSTR> {
            self.instr.iter()
        }
        #[doc = "0x3800..0x3a58 - no description available"]
        #[inline(always)]
        pub const fn dat(&self, n: usize) -> &DAT {
            #[allow(clippy::no_effect)]
            [(); 10][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(14336)
                    .add(64 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x3800..0x3a58 - no description available"]
        #[inline(always)]
        pub fn dat_iter(&self) -> impl Iterator<Item = &DAT> {
            (0..10).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(14336)
                    .add(64 * n)
                    .cast()
            })
        }
    }
    #[doc = "no description available"]
    pub use self::ctrl::CTRL;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod ctrl {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct CTRL {
            engine_ctrl: ENGINE_CTRL,
            ptr_cfg: PTR_CFG,
            wdg_cfg: WDG_CFG,
            _reserved3: [u8; 0x04],
            exe_sta: EXE_STA,
            exe_ptr: EXE_PTR,
            exe_inst: EXE_INST,
            wdg_sta: WDG_STA,
            xcvr_ctrl: XCVR_CTRL,
            type_cfg: TYPE_CFG,
            baud_cfg: BAUD_CFG,
            data_cfg: DATA_CFG,
            clk_cfg: CLK_CFG,
            _reserved12: [u8; 0x04],
            pin: PIN,
            state: STATE,
            in_cfg: IN_CFG,
            sw: SW,
            trg_prd_cfg: TRG_PRD_CFG,
            prd: PRD,
            out_cfg: OUT_CFG,
            _reserved19: [u8; 0x0c],
            prd_sts: PRD_STS,
            prd_cnt: PRD_CNT,
            _reserved21: [u8; 0x18],
            trg_table_cmd: [TRG_TABLE_CMD; 4],
            _reserved22: [u8; 0x10],
            time: [TIME; 4],
            _reserved23: [u8; 0x10],
            mode: MODE,
            idx: IDX,
            gold: GOLD,
            crcinit: CRCINIT,
            crcpoly: CRCPOLY,
            _reserved28: [u8; 0x0c],
            cmd: CMD,
            set: SET,
            clr: CLR,
            inv: INV,
            in_: IN,
            out: OUT,
            sts: STS,
            _reserved35: [u8; 0x04],
            cmd_table: (),
            _reserved36: [u8; 0x0100],
            latch: [LATCH; 4],
            smp_en: SMP_EN,
            smp_cfg: SMP_CFG,
            smp_dat: SMP_DAT,
            _reserved40: [u8; 0x04],
            smp_pos: SMP_POS,
            smp_rev: SMP_REV,
            smp_spd: SMP_SPD,
            smp_acc: SMP_ACC,
            upd_en: UPD_EN,
            upd_cfg: UPD_CFG,
            upd_dat: UPD_DAT,
            upd_time: UPD_TIME,
            upd_pos: UPD_POS,
            upd_rev: UPD_REV,
            upd_spd: UPD_SPD,
            upd_acc: UPD_ACC,
            smp_val: SMP_VAL,
            smp_sts: SMP_STS,
            _reserved54: [u8; 0x04],
            time_in: TIME_IN,
            pos_in: POS_IN,
            rev_in: REV_IN,
            spd_in: SPD_IN,
            acc_in: ACC_IN,
            _reserved59: [u8; 0x04],
            upd_sts: UPD_STS,
            _reserved60: [u8; 0x18],
            int_en: INT_EN,
            int_flag: INT_FLAG,
            int_sts: INT_STS,
            _reserved63: [u8; 0x04],
            pointer0: POINTER0,
            pointer1: POINTER1,
            instr0: INSTR0,
            instr1: INSTR1,
        }
        impl CTRL {
            #[doc = "0x00 - Engine control register"]
            #[inline(always)]
            pub const fn engine_ctrl(&self) -> &ENGINE_CTRL {
                &self.engine_ctrl
            }
            #[doc = "0x04 - Pointer configuration register"]
            #[inline(always)]
            pub const fn ptr_cfg(&self) -> &PTR_CFG {
                &self.ptr_cfg
            }
            #[doc = "0x08 - Watch dog configuration register"]
            #[inline(always)]
            pub const fn wdg_cfg(&self) -> &WDG_CFG {
                &self.wdg_cfg
            }
            #[doc = "0x10 - Execution status"]
            #[inline(always)]
            pub const fn exe_sta(&self) -> &EXE_STA {
                &self.exe_sta
            }
            #[doc = "0x14 - Execution pointer"]
            #[inline(always)]
            pub const fn exe_ptr(&self) -> &EXE_PTR {
                &self.exe_ptr
            }
            #[doc = "0x18 - Execution instruction"]
            #[inline(always)]
            pub const fn exe_inst(&self) -> &EXE_INST {
                &self.exe_inst
            }
            #[doc = "0x1c - Watch dog status"]
            #[inline(always)]
            pub const fn wdg_sta(&self) -> &WDG_STA {
                &self.wdg_sta
            }
            #[doc = "0x20 - Transceiver control register"]
            #[inline(always)]
            pub const fn xcvr_ctrl(&self) -> &XCVR_CTRL {
                &self.xcvr_ctrl
            }
            #[doc = "0x24 - Transceiver configuration register"]
            #[inline(always)]
            pub const fn type_cfg(&self) -> &TYPE_CFG {
                &self.type_cfg
            }
            #[doc = "0x28 - Transceiver baud rate register"]
            #[inline(always)]
            pub const fn baud_cfg(&self) -> &BAUD_CFG {
                &self.baud_cfg
            }
            #[doc = "0x2c - Transceiver data timing configuration"]
            #[inline(always)]
            pub const fn data_cfg(&self) -> &DATA_CFG {
                &self.data_cfg
            }
            #[doc = "0x30 - Transceiver clock timing configuration"]
            #[inline(always)]
            pub const fn clk_cfg(&self) -> &CLK_CFG {
                &self.clk_cfg
            }
            #[doc = "0x38 - Transceiver pin status"]
            #[inline(always)]
            pub const fn pin(&self) -> &PIN {
                &self.pin
            }
            #[doc = "0x3c - FSM of asynchronous"]
            #[inline(always)]
            pub const fn state(&self) -> &STATE {
                &self.state
            }
            #[doc = "0x40 - Trigger input configuration"]
            #[inline(always)]
            pub const fn in_cfg(&self) -> &IN_CFG {
                &self.in_cfg
            }
            #[doc = "0x44 - Software trigger"]
            #[inline(always)]
            pub const fn sw(&self) -> &SW {
                &self.sw
            }
            #[doc = "0x48 - Period trigger configuration"]
            #[inline(always)]
            pub const fn trg_prd_cfg(&self) -> &TRG_PRD_CFG {
                &self.trg_prd_cfg
            }
            #[doc = "0x4c - Trigger period"]
            #[inline(always)]
            pub const fn prd(&self) -> &PRD {
                &self.prd
            }
            #[doc = "0x50 - Trigger output configuration"]
            #[inline(always)]
            pub const fn out_cfg(&self) -> &OUT_CFG {
                &self.out_cfg
            }
            #[doc = "0x60 - Period trigger status"]
            #[inline(always)]
            pub const fn prd_sts(&self) -> &PRD_STS {
                &self.prd_sts
            }
            #[doc = "0x64 - Period trigger counter"]
            #[inline(always)]
            pub const fn prd_cnt(&self) -> &PRD_CNT {
                &self.prd_cnt
            }
            #[doc = "0x80..0x90 - no description available"]
            #[inline(always)]
            pub const fn trg_table_cmd(&self, n: usize) -> &TRG_TABLE_CMD {
                &self.trg_table_cmd[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x80..0x90 - no description available"]
            #[inline(always)]
            pub fn trg_table_cmd_iter(&self) -> impl Iterator<Item = &TRG_TABLE_CMD> {
                self.trg_table_cmd.iter()
            }
            #[doc = "0xa0..0xb0 - no description available"]
            #[inline(always)]
            pub const fn time(&self, n: usize) -> &TIME {
                &self.time[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0xa0..0xb0 - no description available"]
            #[inline(always)]
            pub fn time_iter(&self) -> impl Iterator<Item = &TIME> {
                self.time.iter()
            }
            #[doc = "0xc0 - command register mode"]
            #[inline(always)]
            pub const fn mode(&self) -> &MODE {
                &self.mode
            }
            #[doc = "0xc4 - command register configuration"]
            #[inline(always)]
            pub const fn idx(&self) -> &IDX {
                &self.idx
            }
            #[doc = "0xc8 - Command gold value"]
            #[inline(always)]
            pub const fn gold(&self) -> &GOLD {
                &self.gold
            }
            #[doc = "0xcc - Command Initial value"]
            #[inline(always)]
            pub const fn crcinit(&self) -> &CRCINIT {
                &self.crcinit
            }
            #[doc = "0xd0 - Command CRC polymial"]
            #[inline(always)]
            pub const fn crcpoly(&self) -> &CRCPOLY {
                &self.crcpoly
            }
            #[doc = "0xe0 - command"]
            #[inline(always)]
            pub const fn cmd(&self) -> &CMD {
                &self.cmd
            }
            #[doc = "0xe4 - command bit set register"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0xe8 - command bit clear register"]
            #[inline(always)]
            pub const fn clr(&self) -> &CLR {
                &self.clr
            }
            #[doc = "0xec - command bit invert register"]
            #[inline(always)]
            pub const fn inv(&self) -> &INV {
                &self.inv
            }
            #[doc = "0xf0 - Commad input"]
            #[inline(always)]
            pub const fn in_(&self) -> &IN {
                &self.in_
            }
            #[doc = "0xf4 - Command output"]
            #[inline(always)]
            pub const fn out(&self) -> &OUT {
                &self.out
            }
            #[doc = "0xf8 - Command status"]
            #[inline(always)]
            pub const fn sts(&self) -> &STS {
                &self.sts
            }
            #[doc = "0x100..0x1c0 - no description available"]
            #[inline(always)]
            pub const fn cmd_table(&self, n: usize) -> &CMD_TABLE {
                #[allow(clippy::no_effect)]
                [(); 8][n];
                unsafe {
                    &*(self as *const Self)
                        .cast::<u8>()
                        .add(256)
                        .add(32 * n)
                        .cast()
                }
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x100..0x1c0 - no description available"]
            #[inline(always)]
            pub fn cmd_table_iter(&self) -> impl Iterator<Item = &CMD_TABLE> {
                (0..8).map(move |n| unsafe {
                    &*(self as *const Self)
                        .cast::<u8>()
                        .add(256)
                        .add(32 * n)
                        .cast()
                })
            }
            #[doc = "0x200..0x280 - no description available"]
            #[inline(always)]
            pub const fn latch(&self, n: usize) -> &LATCH {
                &self.latch[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x200..0x280 - no description available"]
            #[inline(always)]
            pub fn latch_iter(&self) -> impl Iterator<Item = &LATCH> {
                self.latch.iter()
            }
            #[doc = "0x280 - Sample selection register"]
            #[inline(always)]
            pub const fn smp_en(&self) -> &SMP_EN {
                &self.smp_en
            }
            #[doc = "0x284 - Sample configuration"]
            #[inline(always)]
            pub const fn smp_cfg(&self) -> &SMP_CFG {
                &self.smp_cfg
            }
            #[doc = "0x288 - Sample data"]
            #[inline(always)]
            pub const fn smp_dat(&self) -> &SMP_DAT {
                &self.smp_dat
            }
            #[doc = "0x290 - Sample override position"]
            #[inline(always)]
            pub const fn smp_pos(&self) -> &SMP_POS {
                &self.smp_pos
            }
            #[doc = "0x294 - Sample override revolution"]
            #[inline(always)]
            pub const fn smp_rev(&self) -> &SMP_REV {
                &self.smp_rev
            }
            #[doc = "0x298 - Sample override speed"]
            #[inline(always)]
            pub const fn smp_spd(&self) -> &SMP_SPD {
                &self.smp_spd
            }
            #[doc = "0x29c - Sample override accelerate"]
            #[inline(always)]
            pub const fn smp_acc(&self) -> &SMP_ACC {
                &self.smp_acc
            }
            #[doc = "0x2a0 - Update configuration"]
            #[inline(always)]
            pub const fn upd_en(&self) -> &UPD_EN {
                &self.upd_en
            }
            #[doc = "0x2a4 - Update configuration"]
            #[inline(always)]
            pub const fn upd_cfg(&self) -> &UPD_CFG {
                &self.upd_cfg
            }
            #[doc = "0x2a8 - Update data"]
            #[inline(always)]
            pub const fn upd_dat(&self) -> &UPD_DAT {
                &self.upd_dat
            }
            #[doc = "0x2ac - Update overide time"]
            #[inline(always)]
            pub const fn upd_time(&self) -> &UPD_TIME {
                &self.upd_time
            }
            #[doc = "0x2b0 - Update override position"]
            #[inline(always)]
            pub const fn upd_pos(&self) -> &UPD_POS {
                &self.upd_pos
            }
            #[doc = "0x2b4 - Update override revolution"]
            #[inline(always)]
            pub const fn upd_rev(&self) -> &UPD_REV {
                &self.upd_rev
            }
            #[doc = "0x2b8 - Update override speed"]
            #[inline(always)]
            pub const fn upd_spd(&self) -> &UPD_SPD {
                &self.upd_spd
            }
            #[doc = "0x2bc - Update override accelerate"]
            #[inline(always)]
            pub const fn upd_acc(&self) -> &UPD_ACC {
                &self.upd_acc
            }
            #[doc = "0x2c0 - Sample valid"]
            #[inline(always)]
            pub const fn smp_val(&self) -> &SMP_VAL {
                &self.smp_val
            }
            #[doc = "0x2c4 - Sample status"]
            #[inline(always)]
            pub const fn smp_sts(&self) -> &SMP_STS {
                &self.smp_sts
            }
            #[doc = "0x2cc - input time"]
            #[inline(always)]
            pub const fn time_in(&self) -> &TIME_IN {
                &self.time_in
            }
            #[doc = "0x2d0 - Input position"]
            #[inline(always)]
            pub const fn pos_in(&self) -> &POS_IN {
                &self.pos_in
            }
            #[doc = "0x2d4 - Input revolution"]
            #[inline(always)]
            pub const fn rev_in(&self) -> &REV_IN {
                &self.rev_in
            }
            #[doc = "0x2d8 - Input speed"]
            #[inline(always)]
            pub const fn spd_in(&self) -> &SPD_IN {
                &self.spd_in
            }
            #[doc = "0x2dc - Input accelerate"]
            #[inline(always)]
            pub const fn acc_in(&self) -> &ACC_IN {
                &self.acc_in
            }
            #[doc = "0x2e4 - Update status"]
            #[inline(always)]
            pub const fn upd_sts(&self) -> &UPD_STS {
                &self.upd_sts
            }
            #[doc = "0x300 - Interrupt Enable"]
            #[inline(always)]
            pub const fn int_en(&self) -> &INT_EN {
                &self.int_en
            }
            #[doc = "0x304 - Interrupt flag"]
            #[inline(always)]
            pub const fn int_flag(&self) -> &INT_FLAG {
                &self.int_flag
            }
            #[doc = "0x308 - Interrupt status"]
            #[inline(always)]
            pub const fn int_sts(&self) -> &INT_STS {
                &self.int_sts
            }
            #[doc = "0x310 - Match pointer 0"]
            #[inline(always)]
            pub const fn pointer0(&self) -> &POINTER0 {
                &self.pointer0
            }
            #[doc = "0x314 - Match pointer 1"]
            #[inline(always)]
            pub const fn pointer1(&self) -> &POINTER1 {
                &self.pointer1
            }
            #[doc = "0x318 - Match instruction 0"]
            #[inline(always)]
            pub const fn instr0(&self) -> &INSTR0 {
                &self.instr0
            }
            #[doc = "0x31c - Match instruction 1"]
            #[inline(always)]
            pub const fn instr1(&self) -> &INSTR1 {
                &self.instr1
            }
        }
        #[doc = "ENGINE_CTRL (rw) register accessor: Engine control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`engine_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`engine_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@engine_ctrl`]
module"]
        pub type ENGINE_CTRL = crate::Reg<engine_ctrl::ENGINE_CTRL_SPEC>;
        #[doc = "Engine control register"]
        pub mod engine_ctrl {
            #[doc = "Register `ENGINE_CTRL` reader"]
            pub type R = crate::R<ENGINE_CTRL_SPEC>;
            #[doc = "Register `ENGINE_CTRL` writer"]
            pub type W = crate::W<ENGINE_CTRL_SPEC>;
            #[doc = "Field `ENABLE` reader - Enable 0: disable 1: enable"]
            pub type ENABLE_R = crate::BitReader;
            #[doc = "Field `ENABLE` writer - Enable 0: disable 1: enable"]
            pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `REWIND` reader - Rewind execution pointer 0: run 1: clean status and rewind"]
            pub type REWIND_R = crate::BitReader;
            #[doc = "Field `REWIND` writer - Rewind execution pointer 0: run 1: clean status and rewind"]
            pub type REWIND_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `EXCEPT` reader - Explain timout as exception 0: when timeout, pointer move to next instruction 1: when timeout, pointer jump to timeout vector"]
            pub type EXCEPT_R = crate::BitReader;
            #[doc = "Field `EXCEPT` writer - Explain timout as exception 0: when timeout, pointer move to next instruction 1: when timeout, pointer jump to timeout vector"]
            pub type EXCEPT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `ARMING` reader - Wait for trigger before excuting 0: Execute on enable 1: Wait trigger before exection after enabled"]
            pub type ARMING_R = crate::BitReader;
            #[doc = "Field `ARMING` writer - Wait for trigger before excuting 0: Execute on enable 1: Wait trigger before exection after enabled"]
            pub type ARMING_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WATCH` reader - Enable watch dog 0: Watch dog disabled 1: Watch dog enabled"]
            pub type WATCH_R = crate::BitReader;
            #[doc = "Field `WATCH` writer - Enable watch dog 0: Watch dog disabled 1: Watch dog enabled"]
            pub type WATCH_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Enable 0: disable 1: enable"]
                #[inline(always)]
                pub fn enable(&self) -> ENABLE_R {
                    ENABLE_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 4 - Rewind execution pointer 0: run 1: clean status and rewind"]
                #[inline(always)]
                pub fn rewind(&self) -> REWIND_R {
                    REWIND_R::new(((self.bits >> 4) & 1) != 0)
                }
                #[doc = "Bit 8 - Explain timout as exception 0: when timeout, pointer move to next instruction 1: when timeout, pointer jump to timeout vector"]
                #[inline(always)]
                pub fn except(&self) -> EXCEPT_R {
                    EXCEPT_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 16 - Wait for trigger before excuting 0: Execute on enable 1: Wait trigger before exection after enabled"]
                #[inline(always)]
                pub fn arming(&self) -> ARMING_R {
                    ARMING_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 24 - Enable watch dog 0: Watch dog disabled 1: Watch dog enabled"]
                #[inline(always)]
                pub fn watch(&self) -> WATCH_R {
                    WATCH_R::new(((self.bits >> 24) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Enable 0: disable 1: enable"]
                #[inline(always)]
                #[must_use]
                pub fn enable(&mut self) -> ENABLE_W<ENGINE_CTRL_SPEC> {
                    ENABLE_W::new(self, 0)
                }
                #[doc = "Bit 4 - Rewind execution pointer 0: run 1: clean status and rewind"]
                #[inline(always)]
                #[must_use]
                pub fn rewind(&mut self) -> REWIND_W<ENGINE_CTRL_SPEC> {
                    REWIND_W::new(self, 4)
                }
                #[doc = "Bit 8 - Explain timout as exception 0: when timeout, pointer move to next instruction 1: when timeout, pointer jump to timeout vector"]
                #[inline(always)]
                #[must_use]
                pub fn except(&mut self) -> EXCEPT_W<ENGINE_CTRL_SPEC> {
                    EXCEPT_W::new(self, 8)
                }
                #[doc = "Bit 16 - Wait for trigger before excuting 0: Execute on enable 1: Wait trigger before exection after enabled"]
                #[inline(always)]
                #[must_use]
                pub fn arming(&mut self) -> ARMING_W<ENGINE_CTRL_SPEC> {
                    ARMING_W::new(self, 16)
                }
                #[doc = "Bit 24 - Enable watch dog 0: Watch dog disabled 1: Watch dog enabled"]
                #[inline(always)]
                #[must_use]
                pub fn watch(&mut self) -> WATCH_W<ENGINE_CTRL_SPEC> {
                    WATCH_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Engine control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`engine_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`engine_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct ENGINE_CTRL_SPEC;
            impl crate::RegisterSpec for ENGINE_CTRL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`engine_ctrl::R`](R) reader structure"]
            impl crate::Readable for ENGINE_CTRL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`engine_ctrl::W`](W) writer structure"]
            impl crate::Writable for ENGINE_CTRL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ENGINE_CTRL to value 0"]
            impl crate::Resettable for ENGINE_CTRL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "PTR_CFG (rw) register accessor: Pointer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ptr_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ptr_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ptr_cfg`]
module"]
        pub type PTR_CFG = crate::Reg<ptr_cfg::PTR_CFG_SPEC>;
        #[doc = "Pointer configuration register"]
        pub mod ptr_cfg {
            #[doc = "Register `PTR_CFG` reader"]
            pub type R = crate::R<PTR_CFG_SPEC>;
            #[doc = "Register `PTR_CFG` writer"]
            pub type W = crate::W<PTR_CFG_SPEC>;
            #[doc = "Field `POINTER_INIT` reader - Initial execute pointer"]
            pub type POINTER_INIT_R = crate::FieldReader;
            #[doc = "Field `POINTER_INIT` writer - Initial execute pointer"]
            pub type POINTER_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `POINTER_WDOG` reader - Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME"]
            pub type POINTER_WDOG_R = crate::FieldReader;
            #[doc = "Field `POINTER_WDOG` writer - Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME"]
            pub type POINTER_WDOG_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `DAT_BASE` reader - Bias for data register access, if calculated index bigger than 32, index will wrap around 0: real data index 1: access index is 1 greater than instruction address 2: access index is 2 greater than instruction address ... 31: access index is 31 greater than instruction address"]
            pub type DAT_BASE_R = crate::FieldReader;
            #[doc = "Field `DAT_BASE` writer - Bias for data register access, if calculated index bigger than 32, index will wrap around 0: real data index 1: access index is 1 greater than instruction address 2: access index is 2 greater than instruction address ... 31: access index is 31 greater than instruction address"]
            pub type DAT_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `DAT_CDM` reader - Select DATA register to receive CDM bit in BiSSC slave mode 0: ignore 1: command 2: data register 2 3: data register 3 ... 29:data register 29 30: value 0 when send, ignore in receive 31: value1 when send, ignore in receive"]
            pub type DAT_CDM_R = crate::FieldReader;
            #[doc = "Field `DAT_CDM` writer - Select DATA register to receive CDM bit in BiSSC slave mode 0: ignore 1: command 2: data register 2 3: data register 3 ... 29:data register 29 30: value 0 when send, ignore in receive 31: value1 when send, ignore in receive"]
            pub type DAT_CDM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            impl R {
                #[doc = "Bits 0:7 - Initial execute pointer"]
                #[inline(always)]
                pub fn pointer_init(&self) -> POINTER_INIT_R {
                    POINTER_INIT_R::new((self.bits & 0xff) as u8)
                }
                #[doc = "Bits 8:15 - Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME"]
                #[inline(always)]
                pub fn pointer_wdog(&self) -> POINTER_WDOG_R {
                    POINTER_WDOG_R::new(((self.bits >> 8) & 0xff) as u8)
                }
                #[doc = "Bits 16:20 - Bias for data register access, if calculated index bigger than 32, index will wrap around 0: real data index 1: access index is 1 greater than instruction address 2: access index is 2 greater than instruction address ... 31: access index is 31 greater than instruction address"]
                #[inline(always)]
                pub fn dat_base(&self) -> DAT_BASE_R {
                    DAT_BASE_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - Select DATA register to receive CDM bit in BiSSC slave mode 0: ignore 1: command 2: data register 2 3: data register 3 ... 29:data register 29 30: value 0 when send, ignore in receive 31: value1 when send, ignore in receive"]
                #[inline(always)]
                pub fn dat_cdm(&self) -> DAT_CDM_R {
                    DAT_CDM_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - Initial execute pointer"]
                #[inline(always)]
                #[must_use]
                pub fn pointer_init(&mut self) -> POINTER_INIT_W<PTR_CFG_SPEC> {
                    POINTER_INIT_W::new(self, 0)
                }
                #[doc = "Bits 8:15 - Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME"]
                #[inline(always)]
                #[must_use]
                pub fn pointer_wdog(&mut self) -> POINTER_WDOG_W<PTR_CFG_SPEC> {
                    POINTER_WDOG_W::new(self, 8)
                }
                #[doc = "Bits 16:20 - Bias for data register access, if calculated index bigger than 32, index will wrap around 0: real data index 1: access index is 1 greater than instruction address 2: access index is 2 greater than instruction address ... 31: access index is 31 greater than instruction address"]
                #[inline(always)]
                #[must_use]
                pub fn dat_base(&mut self) -> DAT_BASE_W<PTR_CFG_SPEC> {
                    DAT_BASE_W::new(self, 16)
                }
                #[doc = "Bits 24:28 - Select DATA register to receive CDM bit in BiSSC slave mode 0: ignore 1: command 2: data register 2 3: data register 3 ... 29:data register 29 30: value 0 when send, ignore in receive 31: value1 when send, ignore in receive"]
                #[inline(always)]
                #[must_use]
                pub fn dat_cdm(&mut self) -> DAT_CDM_W<PTR_CFG_SPEC> {
                    DAT_CDM_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Pointer configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ptr_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ptr_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PTR_CFG_SPEC;
            impl crate::RegisterSpec for PTR_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ptr_cfg::R`](R) reader structure"]
            impl crate::Readable for PTR_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ptr_cfg::W`](W) writer structure"]
            impl crate::Writable for PTR_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PTR_CFG to value 0"]
            impl crate::Resettable for PTR_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "WDG_CFG (rw) register accessor: Watch dog configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdg_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdg_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdg_cfg`]
module"]
        pub type WDG_CFG = crate::Reg<wdg_cfg::WDG_CFG_SPEC>;
        #[doc = "Watch dog configuration register"]
        pub mod wdg_cfg {
            #[doc = "Register `WDG_CFG` reader"]
            pub type R = crate::R<WDG_CFG_SPEC>;
            #[doc = "Register `WDG_CFG` writer"]
            pub type W = crate::W<WDG_CFG_SPEC>;
            #[doc = "Field `WDOG_TIME` reader - Time out count for each instruction, counter in bit time."]
            pub type WDOG_TIME_R = crate::FieldReader<u16>;
            #[doc = "Field `WDOG_TIME` writer - Time out count for each instruction, counter in bit time."]
            pub type WDOG_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - Time out count for each instruction, counter in bit time."]
                #[inline(always)]
                pub fn wdog_time(&self) -> WDOG_TIME_R {
                    WDOG_TIME_R::new((self.bits & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - Time out count for each instruction, counter in bit time."]
                #[inline(always)]
                #[must_use]
                pub fn wdog_time(&mut self) -> WDOG_TIME_W<WDG_CFG_SPEC> {
                    WDOG_TIME_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Watch dog configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdg_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdg_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct WDG_CFG_SPEC;
            impl crate::RegisterSpec for WDG_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`wdg_cfg::R`](R) reader structure"]
            impl crate::Readable for WDG_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`wdg_cfg::W`](W) writer structure"]
            impl crate::Writable for WDG_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets WDG_CFG to value 0"]
            impl crate::Resettable for WDG_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "EXE_STA (rw) register accessor: Execution status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exe_sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exe_sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exe_sta`]
module"]
        pub type EXE_STA = crate::Reg<exe_sta::EXE_STA_SPEC>;
        #[doc = "Execution status"]
        pub mod exe_sta {
            #[doc = "Register `EXE_STA` reader"]
            pub type R = crate::R<EXE_STA_SPEC>;
            #[doc = "Register `EXE_STA` writer"]
            pub type W = crate::W<EXE_STA_SPEC>;
            #[doc = "Field `STALL` reader - Program finished 0: Program is executing 1: Program finished"]
            pub type STALL_R = crate::BitReader;
            #[doc = "Field `EXPIRE` reader - Watchdog timer expired 0: Not expired 1: Expired"]
            pub type EXPIRE_R = crate::BitReader;
            #[doc = "Field `ARMED` reader - Waiting for trigger for execution 0: Not in waiting status 1: In waiting status"]
            pub type ARMED_R = crate::BitReader;
            #[doc = "Field `TRIGERED` reader - Execution has been triggered 0: Execution not triggered 1: Execution triggered"]
            pub type TRIGERED_R = crate::BitReader;
            impl R {
                #[doc = "Bit 0 - Program finished 0: Program is executing 1: Program finished"]
                #[inline(always)]
                pub fn stall(&self) -> STALL_R {
                    STALL_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 8 - Watchdog timer expired 0: Not expired 1: Expired"]
                #[inline(always)]
                pub fn expire(&self) -> EXPIRE_R {
                    EXPIRE_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 16 - Waiting for trigger for execution 0: Not in waiting status 1: In waiting status"]
                #[inline(always)]
                pub fn armed(&self) -> ARMED_R {
                    ARMED_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 20 - Execution has been triggered 0: Execution not triggered 1: Execution triggered"]
                #[inline(always)]
                pub fn trigered(&self) -> TRIGERED_R {
                    TRIGERED_R::new(((self.bits >> 20) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Execution status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exe_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exe_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct EXE_STA_SPEC;
            impl crate::RegisterSpec for EXE_STA_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`exe_sta::R`](R) reader structure"]
            impl crate::Readable for EXE_STA_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`exe_sta::W`](W) writer structure"]
            impl crate::Writable for EXE_STA_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets EXE_STA to value 0"]
            impl crate::Resettable for EXE_STA_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "EXE_PTR (rw) register accessor: Execution pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exe_ptr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exe_ptr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exe_ptr`]
module"]
        pub type EXE_PTR = crate::Reg<exe_ptr::EXE_PTR_SPEC>;
        #[doc = "Execution pointer"]
        pub mod exe_ptr {
            #[doc = "Register `EXE_PTR` reader"]
            pub type R = crate::R<EXE_PTR_SPEC>;
            #[doc = "Register `EXE_PTR` writer"]
            pub type W = crate::W<EXE_PTR_SPEC>;
            #[doc = "Field `POINTER` reader - Current program pointer"]
            pub type POINTER_R = crate::FieldReader;
            #[doc = "Field `BIT_CNT` reader - Bit count in send and receive instruction execution"]
            pub type BIT_CNT_R = crate::FieldReader;
            #[doc = "Field `HALT_CNT` reader - Halt count in halt instrution"]
            pub type HALT_CNT_R = crate::FieldReader;
            impl R {
                #[doc = "Bits 0:7 - Current program pointer"]
                #[inline(always)]
                pub fn pointer(&self) -> POINTER_R {
                    POINTER_R::new((self.bits & 0xff) as u8)
                }
                #[doc = "Bits 16:20 - Bit count in send and receive instruction execution"]
                #[inline(always)]
                pub fn bit_cnt(&self) -> BIT_CNT_R {
                    BIT_CNT_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - Halt count in halt instrution"]
                #[inline(always)]
                pub fn halt_cnt(&self) -> HALT_CNT_R {
                    HALT_CNT_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Execution pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exe_ptr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exe_ptr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct EXE_PTR_SPEC;
            impl crate::RegisterSpec for EXE_PTR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`exe_ptr::R`](R) reader structure"]
            impl crate::Readable for EXE_PTR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`exe_ptr::W`](W) writer structure"]
            impl crate::Writable for EXE_PTR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets EXE_PTR to value 0"]
            impl crate::Resettable for EXE_PTR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "EXE_INST (rw) register accessor: Execution instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exe_inst::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exe_inst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exe_inst`]
module"]
        pub type EXE_INST = crate::Reg<exe_inst::EXE_INST_SPEC>;
        #[doc = "Execution instruction"]
        pub mod exe_inst {
            #[doc = "Register `EXE_INST` reader"]
            pub type R = crate::R<EXE_INST_SPEC>;
            #[doc = "Register `EXE_INST` writer"]
            pub type W = crate::W<EXE_INST_SPEC>;
            #[doc = "Field `INST` reader - Current instruction"]
            pub type INST_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Current instruction"]
                #[inline(always)]
                pub fn inst(&self) -> INST_R {
                    INST_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Execution instruction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`exe_inst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exe_inst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct EXE_INST_SPEC;
            impl crate::RegisterSpec for EXE_INST_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`exe_inst::R`](R) reader structure"]
            impl crate::Readable for EXE_INST_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`exe_inst::W`](W) writer structure"]
            impl crate::Writable for EXE_INST_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets EXE_INST to value 0"]
            impl crate::Resettable for EXE_INST_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "WDG_STA (rw) register accessor: Watch dog status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdg_sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdg_sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdg_sta`]
module"]
        pub type WDG_STA = crate::Reg<wdg_sta::WDG_STA_SPEC>;
        #[doc = "Watch dog status"]
        pub mod wdg_sta {
            #[doc = "Register `WDG_STA` reader"]
            pub type R = crate::R<WDG_STA_SPEC>;
            #[doc = "Register `WDG_STA` writer"]
            pub type W = crate::W<WDG_STA_SPEC>;
            #[doc = "Field `WDOG_CNT` reader - Current watch dog counter value"]
            pub type WDOG_CNT_R = crate::FieldReader<u16>;
            impl R {
                #[doc = "Bits 0:15 - Current watch dog counter value"]
                #[inline(always)]
                pub fn wdog_cnt(&self) -> WDOG_CNT_R {
                    WDOG_CNT_R::new((self.bits & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Watch dog status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdg_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdg_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct WDG_STA_SPEC;
            impl crate::RegisterSpec for WDG_STA_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`wdg_sta::R`](R) reader structure"]
            impl crate::Readable for WDG_STA_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`wdg_sta::W`](W) writer structure"]
            impl crate::Writable for WDG_STA_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets WDG_STA to value 0"]
            impl crate::Resettable for WDG_STA_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "XCVR_CTRL (rw) register accessor: Transceiver control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xcvr_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xcvr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xcvr_ctrl`]
module"]
        pub type XCVR_CTRL = crate::Reg<xcvr_ctrl::XCVR_CTRL_SPEC>;
        #[doc = "Transceiver control register"]
        pub mod xcvr_ctrl {
            #[doc = "Register `XCVR_CTRL` reader"]
            pub type R = crate::R<XCVR_CTRL_SPEC>;
            #[doc = "Register `XCVR_CTRL` writer"]
            pub type W = crate::W<XCVR_CTRL_SPEC>;
            #[doc = "Field `MODE` reader - Tranceiver mode 0: synchronous maaster 1: synchronous slave 2: asynchronous mode 3: asynchronous mode"]
            pub type MODE_R = crate::FieldReader;
            #[doc = "Field `MODE` writer - Tranceiver mode 0: synchronous maaster 1: synchronous slave 2: asynchronous mode 3: asynchronous mode"]
            pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `RESTART` writer - Restart tranceiver, this is a self clear bit 0: no effect 1: reset tranceiver"]
            pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PAR_CLR` writer - Clear parity error, this is a self clear bit 0: no effect 1: clear parity error"]
            pub type PAR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRISMP` reader - Tipple sampe 0: sample 1 time for data transition 1: sample 3 times in receive and result in 2oo3"]
            pub type TRISMP_R = crate::BitReader;
            #[doc = "Field `TRISMP` writer - Tipple sampe 0: sample 1 time for data transition 1: sample 3 times in receive and result in 2oo3"]
            pub type TRISMP_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:1 - Tranceiver mode 0: synchronous maaster 1: synchronous slave 2: asynchronous mode 3: asynchronous mode"]
                #[inline(always)]
                pub fn mode(&self) -> MODE_R {
                    MODE_R::new((self.bits & 3) as u8)
                }
                #[doc = "Bit 12 - Tipple sampe 0: sample 1 time for data transition 1: sample 3 times in receive and result in 2oo3"]
                #[inline(always)]
                pub fn trismp(&self) -> TRISMP_R {
                    TRISMP_R::new(((self.bits >> 12) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:1 - Tranceiver mode 0: synchronous maaster 1: synchronous slave 2: asynchronous mode 3: asynchronous mode"]
                #[inline(always)]
                #[must_use]
                pub fn mode(&mut self) -> MODE_W<XCVR_CTRL_SPEC> {
                    MODE_W::new(self, 0)
                }
                #[doc = "Bit 4 - Restart tranceiver, this is a self clear bit 0: no effect 1: reset tranceiver"]
                #[inline(always)]
                #[must_use]
                pub fn restart(&mut self) -> RESTART_W<XCVR_CTRL_SPEC> {
                    RESTART_W::new(self, 4)
                }
                #[doc = "Bit 8 - Clear parity error, this is a self clear bit 0: no effect 1: clear parity error"]
                #[inline(always)]
                #[must_use]
                pub fn par_clr(&mut self) -> PAR_CLR_W<XCVR_CTRL_SPEC> {
                    PAR_CLR_W::new(self, 8)
                }
                #[doc = "Bit 12 - Tipple sampe 0: sample 1 time for data transition 1: sample 3 times in receive and result in 2oo3"]
                #[inline(always)]
                #[must_use]
                pub fn trismp(&mut self) -> TRISMP_W<XCVR_CTRL_SPEC> {
                    TRISMP_W::new(self, 12)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Transceiver control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xcvr_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xcvr_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct XCVR_CTRL_SPEC;
            impl crate::RegisterSpec for XCVR_CTRL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`xcvr_ctrl::R`](R) reader structure"]
            impl crate::Readable for XCVR_CTRL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`xcvr_ctrl::W`](W) writer structure"]
            impl crate::Writable for XCVR_CTRL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets XCVR_CTRL to value 0"]
            impl crate::Resettable for XCVR_CTRL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TYPE_CFG (rw) register accessor: Transceiver configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`type_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`type_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@type_cfg`]
module"]
        pub type TYPE_CFG = crate::Reg<type_cfg::TYPE_CFG_SPEC>;
        #[doc = "Transceiver configuration register"]
        pub mod type_cfg {
            #[doc = "Register `TYPE_CFG` reader"]
            pub type R = crate::R<TYPE_CFG_SPEC>;
            #[doc = "Register `TYPE_CFG` writer"]
            pub type W = crate::W<TYPE_CFG_SPEC>;
            #[doc = "Field `CK_IDLEV` reader - Idle state value of clock line 0: data'0' 1: data'1'"]
            pub type CK_IDLEV_R = crate::BitReader;
            #[doc = "Field `CK_IDLEV` writer - Idle state value of clock line 0: data'0' 1: data'1'"]
            pub type CK_IDLEV_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DA_IDLEV` reader - Idle state value of data line 0: data'0' 1: data'1'"]
            pub type DA_IDLEV_R = crate::BitReader;
            #[doc = "Field `DA_IDLEV` writer - Idle state value of data line 0: data'0' 1: data'1'"]
            pub type DA_IDLEV_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CK_IDLEZ` reader - Idle state driver of clock line 0: output 1: high-Z"]
            pub type CK_IDLEZ_R = crate::BitReader;
            #[doc = "Field `CK_IDLEZ` writer - Idle state driver of clock line 0: output 1: high-Z"]
            pub type CK_IDLEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DA_IDLEZ` reader - Idle state driver of data line 0: output 1: high-Z"]
            pub type DA_IDLEZ_R = crate::BitReader;
            #[doc = "Field `DA_IDLEZ` writer - Idle state driver of data line 0: output 1: high-Z"]
            pub type DA_IDLEZ_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PAR_EN` reader - enable parity check for asynchronous mode 0: disable 1: enable"]
            pub type PAR_EN_R = crate::BitReader;
            #[doc = "Field `PAR_EN` writer - enable parity check for asynchronous mode 0: disable 1: enable"]
            pub type PAR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PAR_POL` reader - Polarity of parity for asynchronous mode 0: even 1: odd"]
            pub type PAR_POL_R = crate::BitReader;
            #[doc = "Field `PAR_POL` writer - Polarity of parity for asynchronous mode 0: even 1: odd"]
            pub type PAR_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DATA_LEN` reader - Number of data bit for asynchronous mode 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type DATA_LEN_R = crate::FieldReader;
            #[doc = "Field `DATA_LEN` writer - Number of data bit for asynchronous mode 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type DATA_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `WAIT_LEN` reader - Number of extra stop bit for asynchronous mode 0: 1 bit 1: 2 bit ... 255: 256 bit"]
            pub type WAIT_LEN_R = crate::FieldReader;
            #[doc = "Field `WAIT_LEN` writer - Number of extra stop bit for asynchronous mode 0: 1 bit 1: 2 bit ... 255: 256 bit"]
            pub type WAIT_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bit 0 - Idle state value of clock line 0: data'0' 1: data'1'"]
                #[inline(always)]
                pub fn ck_idlev(&self) -> CK_IDLEV_R {
                    CK_IDLEV_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - Idle state value of data line 0: data'0' 1: data'1'"]
                #[inline(always)]
                pub fn da_idlev(&self) -> DA_IDLEV_R {
                    DA_IDLEV_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 2 - Idle state driver of clock line 0: output 1: high-Z"]
                #[inline(always)]
                pub fn ck_idlez(&self) -> CK_IDLEZ_R {
                    CK_IDLEZ_R::new(((self.bits >> 2) & 1) != 0)
                }
                #[doc = "Bit 3 - Idle state driver of data line 0: output 1: high-Z"]
                #[inline(always)]
                pub fn da_idlez(&self) -> DA_IDLEZ_R {
                    DA_IDLEZ_R::new(((self.bits >> 3) & 1) != 0)
                }
                #[doc = "Bit 8 - enable parity check for asynchronous mode 0: disable 1: enable"]
                #[inline(always)]
                pub fn par_en(&self) -> PAR_EN_R {
                    PAR_EN_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - Polarity of parity for asynchronous mode 0: even 1: odd"]
                #[inline(always)]
                pub fn par_pol(&self) -> PAR_POL_R {
                    PAR_POL_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bits 16:20 - Number of data bit for asynchronous mode 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                pub fn data_len(&self) -> DATA_LEN_R {
                    DATA_LEN_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:31 - Number of extra stop bit for asynchronous mode 0: 1 bit 1: 2 bit ... 255: 256 bit"]
                #[inline(always)]
                pub fn wait_len(&self) -> WAIT_LEN_R {
                    WAIT_LEN_R::new(((self.bits >> 24) & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bit 0 - Idle state value of clock line 0: data'0' 1: data'1'"]
                #[inline(always)]
                #[must_use]
                pub fn ck_idlev(&mut self) -> CK_IDLEV_W<TYPE_CFG_SPEC> {
                    CK_IDLEV_W::new(self, 0)
                }
                #[doc = "Bit 1 - Idle state value of data line 0: data'0' 1: data'1'"]
                #[inline(always)]
                #[must_use]
                pub fn da_idlev(&mut self) -> DA_IDLEV_W<TYPE_CFG_SPEC> {
                    DA_IDLEV_W::new(self, 1)
                }
                #[doc = "Bit 2 - Idle state driver of clock line 0: output 1: high-Z"]
                #[inline(always)]
                #[must_use]
                pub fn ck_idlez(&mut self) -> CK_IDLEZ_W<TYPE_CFG_SPEC> {
                    CK_IDLEZ_W::new(self, 2)
                }
                #[doc = "Bit 3 - Idle state driver of data line 0: output 1: high-Z"]
                #[inline(always)]
                #[must_use]
                pub fn da_idlez(&mut self) -> DA_IDLEZ_W<TYPE_CFG_SPEC> {
                    DA_IDLEZ_W::new(self, 3)
                }
                #[doc = "Bit 8 - enable parity check for asynchronous mode 0: disable 1: enable"]
                #[inline(always)]
                #[must_use]
                pub fn par_en(&mut self) -> PAR_EN_W<TYPE_CFG_SPEC> {
                    PAR_EN_W::new(self, 8)
                }
                #[doc = "Bit 9 - Polarity of parity for asynchronous mode 0: even 1: odd"]
                #[inline(always)]
                #[must_use]
                pub fn par_pol(&mut self) -> PAR_POL_W<TYPE_CFG_SPEC> {
                    PAR_POL_W::new(self, 9)
                }
                #[doc = "Bits 16:20 - Number of data bit for asynchronous mode 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                #[must_use]
                pub fn data_len(&mut self) -> DATA_LEN_W<TYPE_CFG_SPEC> {
                    DATA_LEN_W::new(self, 16)
                }
                #[doc = "Bits 24:31 - Number of extra stop bit for asynchronous mode 0: 1 bit 1: 2 bit ... 255: 256 bit"]
                #[inline(always)]
                #[must_use]
                pub fn wait_len(&mut self) -> WAIT_LEN_W<TYPE_CFG_SPEC> {
                    WAIT_LEN_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Transceiver configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`type_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`type_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TYPE_CFG_SPEC;
            impl crate::RegisterSpec for TYPE_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`type_cfg::R`](R) reader structure"]
            impl crate::Readable for TYPE_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`type_cfg::W`](W) writer structure"]
            impl crate::Writable for TYPE_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TYPE_CFG to value 0"]
            impl crate::Resettable for TYPE_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "BAUD_CFG (rw) register accessor: Transceiver baud rate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@baud_cfg`]
module"]
        pub type BAUD_CFG = crate::Reg<baud_cfg::BAUD_CFG_SPEC>;
        #[doc = "Transceiver baud rate register"]
        pub mod baud_cfg {
            #[doc = "Register `BAUD_CFG` reader"]
            pub type R = crate::R<BAUD_CFG_SPEC>;
            #[doc = "Register `BAUD_CFG` writer"]
            pub type W = crate::W<BAUD_CFG_SPEC>;
            #[doc = "Field `BAUD_DIV` reader - Baud rate, bit time in system clock cycle"]
            pub type BAUD_DIV_R = crate::FieldReader<u16>;
            #[doc = "Field `BAUD_DIV` writer - Baud rate, bit time in system clock cycle"]
            pub type BAUD_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            #[doc = "Field `SYNC_POINT` reader - Baud synchronous time, minmum bit time"]
            pub type SYNC_POINT_R = crate::FieldReader<u16>;
            #[doc = "Field `SYNC_POINT` writer - Baud synchronous time, minmum bit time"]
            pub type SYNC_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - Baud rate, bit time in system clock cycle"]
                #[inline(always)]
                pub fn baud_div(&self) -> BAUD_DIV_R {
                    BAUD_DIV_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bits 16:31 - Baud synchronous time, minmum bit time"]
                #[inline(always)]
                pub fn sync_point(&self) -> SYNC_POINT_R {
                    SYNC_POINT_R::new(((self.bits >> 16) & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - Baud rate, bit time in system clock cycle"]
                #[inline(always)]
                #[must_use]
                pub fn baud_div(&mut self) -> BAUD_DIV_W<BAUD_CFG_SPEC> {
                    BAUD_DIV_W::new(self, 0)
                }
                #[doc = "Bits 16:31 - Baud synchronous time, minmum bit time"]
                #[inline(always)]
                #[must_use]
                pub fn sync_point(&mut self) -> SYNC_POINT_W<BAUD_CFG_SPEC> {
                    SYNC_POINT_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Transceiver baud rate register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`baud_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`baud_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct BAUD_CFG_SPEC;
            impl crate::RegisterSpec for BAUD_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`baud_cfg::R`](R) reader structure"]
            impl crate::Readable for BAUD_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`baud_cfg::W`](W) writer structure"]
            impl crate::Writable for BAUD_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets BAUD_CFG to value 0"]
            impl crate::Resettable for BAUD_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "DATA_CFG (rw) register accessor: Transceiver data timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data_cfg`]
module"]
        pub type DATA_CFG = crate::Reg<data_cfg::DATA_CFG_SPEC>;
        #[doc = "Transceiver data timing configuration"]
        pub mod data_cfg {
            #[doc = "Register `DATA_CFG` reader"]
            pub type R = crate::R<DATA_CFG_SPEC>;
            #[doc = "Register `DATA_CFG` writer"]
            pub type W = crate::W<DATA_CFG_SPEC>;
            #[doc = "Field `RXD_POINT` reader - data receive point in system clcok cycle"]
            pub type RXD_POINT_R = crate::FieldReader<u16>;
            #[doc = "Field `RXD_POINT` writer - data receive point in system clcok cycle"]
            pub type RXD_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            #[doc = "Field `TXD_POINT` reader - data transmit point in system clcok cycle"]
            pub type TXD_POINT_R = crate::FieldReader<u16>;
            #[doc = "Field `TXD_POINT` writer - data transmit point in system clcok cycle"]
            pub type TXD_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - data receive point in system clcok cycle"]
                #[inline(always)]
                pub fn rxd_point(&self) -> RXD_POINT_R {
                    RXD_POINT_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bits 16:31 - data transmit point in system clcok cycle"]
                #[inline(always)]
                pub fn txd_point(&self) -> TXD_POINT_R {
                    TXD_POINT_R::new(((self.bits >> 16) & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - data receive point in system clcok cycle"]
                #[inline(always)]
                #[must_use]
                pub fn rxd_point(&mut self) -> RXD_POINT_W<DATA_CFG_SPEC> {
                    RXD_POINT_W::new(self, 0)
                }
                #[doc = "Bits 16:31 - data transmit point in system clcok cycle"]
                #[inline(always)]
                #[must_use]
                pub fn txd_point(&mut self) -> TXD_POINT_W<DATA_CFG_SPEC> {
                    TXD_POINT_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Transceiver data timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct DATA_CFG_SPEC;
            impl crate::RegisterSpec for DATA_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`data_cfg::R`](R) reader structure"]
            impl crate::Readable for DATA_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`data_cfg::W`](W) writer structure"]
            impl crate::Writable for DATA_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets DATA_CFG to value 0"]
            impl crate::Resettable for DATA_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLK_CFG (rw) register accessor: Transceiver clock timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_cfg`]
module"]
        pub type CLK_CFG = crate::Reg<clk_cfg::CLK_CFG_SPEC>;
        #[doc = "Transceiver clock timing configuration"]
        pub mod clk_cfg {
            #[doc = "Register `CLK_CFG` reader"]
            pub type R = crate::R<CLK_CFG_SPEC>;
            #[doc = "Register `CLK_CFG` writer"]
            pub type W = crate::W<CLK_CFG_SPEC>;
            #[doc = "Field `CK0_POINT` reader - clock point 0 in system clcok cycle"]
            pub type CK0_POINT_R = crate::FieldReader<u16>;
            #[doc = "Field `CK0_POINT` writer - clock point 0 in system clcok cycle"]
            pub type CK0_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            #[doc = "Field `CK1_POINT` reader - clock point 1 in system clcok cycle"]
            pub type CK1_POINT_R = crate::FieldReader<u16>;
            #[doc = "Field `CK1_POINT` writer - clock point 1 in system clcok cycle"]
            pub type CK1_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - clock point 0 in system clcok cycle"]
                #[inline(always)]
                pub fn ck0_point(&self) -> CK0_POINT_R {
                    CK0_POINT_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bits 16:31 - clock point 1 in system clcok cycle"]
                #[inline(always)]
                pub fn ck1_point(&self) -> CK1_POINT_R {
                    CK1_POINT_R::new(((self.bits >> 16) & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - clock point 0 in system clcok cycle"]
                #[inline(always)]
                #[must_use]
                pub fn ck0_point(&mut self) -> CK0_POINT_W<CLK_CFG_SPEC> {
                    CK0_POINT_W::new(self, 0)
                }
                #[doc = "Bits 16:31 - clock point 1 in system clcok cycle"]
                #[inline(always)]
                #[must_use]
                pub fn ck1_point(&mut self) -> CK1_POINT_W<CLK_CFG_SPEC> {
                    CK1_POINT_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Transceiver clock timing configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLK_CFG_SPEC;
            impl crate::RegisterSpec for CLK_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clk_cfg::R`](R) reader structure"]
            impl crate::Readable for CLK_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clk_cfg::W`](W) writer structure"]
            impl crate::Writable for CLK_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLK_CFG to value 0"]
            impl crate::Resettable for CLK_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "PIN (rw) register accessor: Transceiver pin status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin`]
module"]
        pub type PIN = crate::Reg<pin::PIN_SPEC>;
        #[doc = "Transceiver pin status"]
        pub mod pin {
            #[doc = "Register `PIN` reader"]
            pub type R = crate::R<PIN_SPEC>;
            #[doc = "Register `PIN` writer"]
            pub type W = crate::W<PIN_SPEC>;
            #[doc = "Field `DO_TX` reader - TX output 0: data 0 1: data 1"]
            pub type DO_TX_R = crate::BitReader;
            #[doc = "Field `DI_TX` reader - TX state 0: data 0 1: data 1"]
            pub type DI_TX_R = crate::BitReader;
            #[doc = "Field `OE_TX` reader - TX drive state 0: input 1: output"]
            pub type OE_TX_R = crate::BitReader;
            #[doc = "Field `DO_DE` reader - DE output 0: data 0 1: data 1"]
            pub type DO_DE_R = crate::BitReader;
            #[doc = "Field `DI_DE` reader - DE state 0: data 0 1: data 1"]
            pub type DI_DE_R = crate::BitReader;
            #[doc = "Field `OE_DE` reader - DE drive state 0: input 1: output"]
            pub type OE_DE_R = crate::BitReader;
            #[doc = "Field `DO_RX` reader - RX output 0: data 0 1: data 1"]
            pub type DO_RX_R = crate::BitReader;
            #[doc = "Field `DI_RX` reader - RX state 0: data 0 1: data 1"]
            pub type DI_RX_R = crate::BitReader;
            #[doc = "Field `OE_RX` reader - RX drive state 0: input 1: output"]
            pub type OE_RX_R = crate::BitReader;
            #[doc = "Field `DO_CK` reader - CK output 0: data 0 1: data 1"]
            pub type DO_CK_R = crate::BitReader;
            #[doc = "Field `DI_CK` reader - CK state 0: data 0 1: data 1"]
            pub type DI_CK_R = crate::BitReader;
            #[doc = "Field `OE_CK` reader - CK drive state 0: input 1: output"]
            pub type OE_CK_R = crate::BitReader;
            impl R {
                #[doc = "Bit 0 - TX output 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn do_tx(&self) -> DO_TX_R {
                    DO_TX_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - TX state 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn di_tx(&self) -> DI_TX_R {
                    DI_TX_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 2 - TX drive state 0: input 1: output"]
                #[inline(always)]
                pub fn oe_tx(&self) -> OE_TX_R {
                    OE_TX_R::new(((self.bits >> 2) & 1) != 0)
                }
                #[doc = "Bit 8 - DE output 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn do_de(&self) -> DO_DE_R {
                    DO_DE_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - DE state 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn di_de(&self) -> DI_DE_R {
                    DI_DE_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - DE drive state 0: input 1: output"]
                #[inline(always)]
                pub fn oe_de(&self) -> OE_DE_R {
                    OE_DE_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 16 - RX output 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn do_rx(&self) -> DO_RX_R {
                    DO_RX_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 17 - RX state 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn di_rx(&self) -> DI_RX_R {
                    DI_RX_R::new(((self.bits >> 17) & 1) != 0)
                }
                #[doc = "Bit 18 - RX drive state 0: input 1: output"]
                #[inline(always)]
                pub fn oe_rx(&self) -> OE_RX_R {
                    OE_RX_R::new(((self.bits >> 18) & 1) != 0)
                }
                #[doc = "Bit 24 - CK output 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn do_ck(&self) -> DO_CK_R {
                    DO_CK_R::new(((self.bits >> 24) & 1) != 0)
                }
                #[doc = "Bit 25 - CK state 0: data 0 1: data 1"]
                #[inline(always)]
                pub fn di_ck(&self) -> DI_CK_R {
                    DI_CK_R::new(((self.bits >> 25) & 1) != 0)
                }
                #[doc = "Bit 26 - CK drive state 0: input 1: output"]
                #[inline(always)]
                pub fn oe_ck(&self) -> OE_CK_R {
                    OE_CK_R::new(((self.bits >> 26) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Transceiver pin status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pin::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PIN_SPEC;
            impl crate::RegisterSpec for PIN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pin::R`](R) reader structure"]
            impl crate::Readable for PIN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"]
            impl crate::Writable for PIN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PIN to value 0"]
            impl crate::Resettable for PIN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "STATE (rw) register accessor: FSM of asynchronous\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"]
        pub type STATE = crate::Reg<state::STATE_SPEC>;
        #[doc = "FSM of asynchronous"]
        pub mod state {
            #[doc = "Register `STATE` reader"]
            pub type R = crate::R<STATE_SPEC>;
            #[doc = "Register `STATE` writer"]
            pub type W = crate::W<STATE_SPEC>;
            #[doc = "Field `SEND_STATE` reader - FSM of asynchronous transmit"]
            pub type SEND_STATE_R = crate::FieldReader;
            #[doc = "Field `RECV_STATE` reader - FSM of asynchronous receive"]
            pub type RECV_STATE_R = crate::FieldReader;
            impl R {
                #[doc = "Bits 16:18 - FSM of asynchronous transmit"]
                #[inline(always)]
                pub fn send_state(&self) -> SEND_STATE_R {
                    SEND_STATE_R::new(((self.bits >> 16) & 7) as u8)
                }
                #[doc = "Bits 24:26 - FSM of asynchronous receive"]
                #[inline(always)]
                pub fn recv_state(&self) -> RECV_STATE_R {
                    RECV_STATE_R::new(((self.bits >> 24) & 7) as u8)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "FSM of asynchronous\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`state::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct STATE_SPEC;
            impl crate::RegisterSpec for STATE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`state::R`](R) reader structure"]
            impl crate::Readable for STATE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`state::W`](W) writer structure"]
            impl crate::Writable for STATE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets STATE to value 0"]
            impl crate::Resettable for STATE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "IN_CFG (rw) register accessor: Trigger input configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_cfg`]
module"]
        pub type IN_CFG = crate::Reg<in_cfg::IN_CFG_SPEC>;
        #[doc = "Trigger input configuration"]
        pub mod in_cfg {
            #[doc = "Register `IN_CFG` reader"]
            pub type R = crate::R<IN_CFG_SPEC>;
            #[doc = "Register `IN_CFG` writer"]
            pub type W = crate::W<IN_CFG_SPEC>;
            #[doc = "Field `IN0_SEL` reader - Trigger 0 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
            pub type IN0_SEL_R = crate::FieldReader;
            #[doc = "Field `IN0_SEL` writer - Trigger 0 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
            pub type IN0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `IN0_EN` reader - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
            pub type IN0_EN_R = crate::BitReader;
            #[doc = "Field `IN0_EN` writer - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
            pub type IN0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `IN1_SEL` reader - Trigger 1 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
            pub type IN1_SEL_R = crate::FieldReader;
            #[doc = "Field `IN1_SEL` writer - Trigger 1 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
            pub type IN1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `IN1_EN` reader - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
            pub type IN1_EN_R = crate::BitReader;
            #[doc = "Field `IN1_EN` writer - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
            pub type IN1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SYNC_SEL` reader - Synchronize sigal selection (tigger 2) 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
            pub type SYNC_SEL_R = crate::FieldReader;
            #[doc = "Field `SYNC_SEL` writer - Synchronize sigal selection (tigger 2) 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
            pub type SYNC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `PRD_EN` reader - Enable period trigger (tigger 2) 0: periodical trigger disabled 1: periodical trigger enabled"]
            pub type PRD_EN_R = crate::BitReader;
            #[doc = "Field `PRD_EN` writer - Enable period trigger (tigger 2) 0: periodical trigger disabled 1: periodical trigger enabled"]
            pub type PRD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:2 - Trigger 0 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
                #[inline(always)]
                pub fn in0_sel(&self) -> IN0_SEL_R {
                    IN0_SEL_R::new((self.bits & 7) as u8)
                }
                #[doc = "Bit 7 - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                pub fn in0_en(&self) -> IN0_EN_R {
                    IN0_EN_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bits 8:10 - Trigger 1 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
                #[inline(always)]
                pub fn in1_sel(&self) -> IN1_SEL_R {
                    IN1_SEL_R::new(((self.bits >> 8) & 7) as u8)
                }
                #[doc = "Bit 15 - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                pub fn in1_en(&self) -> IN1_EN_R {
                    IN1_EN_R::new(((self.bits >> 15) & 1) != 0)
                }
                #[doc = "Bits 16:18 - Synchronize sigal selection (tigger 2) 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
                #[inline(always)]
                pub fn sync_sel(&self) -> SYNC_SEL_R {
                    SYNC_SEL_R::new(((self.bits >> 16) & 7) as u8)
                }
                #[doc = "Bit 23 - Enable period trigger (tigger 2) 0: periodical trigger disabled 1: periodical trigger enabled"]
                #[inline(always)]
                pub fn prd_en(&self) -> PRD_EN_R {
                    PRD_EN_R::new(((self.bits >> 23) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:2 - Trigger 0 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
                #[inline(always)]
                #[must_use]
                pub fn in0_sel(&mut self) -> IN0_SEL_W<IN_CFG_SPEC> {
                    IN0_SEL_W::new(self, 0)
                }
                #[doc = "Bit 7 - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                #[must_use]
                pub fn in0_en(&mut self) -> IN0_EN_W<IN_CFG_SPEC> {
                    IN0_EN_W::new(self, 7)
                }
                #[doc = "Bits 8:10 - Trigger 1 sigal selection 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
                #[inline(always)]
                #[must_use]
                pub fn in1_sel(&mut self) -> IN1_SEL_W<IN_CFG_SPEC> {
                    IN1_SEL_W::new(self, 8)
                }
                #[doc = "Bit 15 - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                #[must_use]
                pub fn in1_en(&mut self) -> IN1_EN_W<IN_CFG_SPEC> {
                    IN1_EN_W::new(self, 15)
                }
                #[doc = "Bits 16:18 - Synchronize sigal selection (tigger 2) 0: trigger in 0 1: trigger in 1 ... 7: trigger in 7"]
                #[inline(always)]
                #[must_use]
                pub fn sync_sel(&mut self) -> SYNC_SEL_W<IN_CFG_SPEC> {
                    SYNC_SEL_W::new(self, 16)
                }
                #[doc = "Bit 23 - Enable period trigger (tigger 2) 0: periodical trigger disabled 1: periodical trigger enabled"]
                #[inline(always)]
                #[must_use]
                pub fn prd_en(&mut self) -> PRD_EN_W<IN_CFG_SPEC> {
                    PRD_EN_W::new(self, 23)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Trigger input configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct IN_CFG_SPEC;
            impl crate::RegisterSpec for IN_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`in_cfg::R`](R) reader structure"]
            impl crate::Readable for IN_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`in_cfg::W`](W) writer structure"]
            impl crate::Writable for IN_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets IN_CFG to value 0"]
            impl crate::Resettable for IN_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SW (rw) register accessor: Software trigger\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw`]
module"]
        pub type SW = crate::Reg<sw::SW_SPEC>;
        #[doc = "Software trigger"]
        pub mod sw {
            #[doc = "Register `SW` reader"]
            pub type R = crate::R<SW_SPEC>;
            #[doc = "Register `SW` writer"]
            pub type W = crate::W<SW_SPEC>;
            #[doc = "Field `SOFT` writer - Software trigger (tigger 3). this bit is self-clear 0: trigger source disabled 1: trigger source enabled"]
            pub type SOFT_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl W {
                #[doc = "Bit 0 - Software trigger (tigger 3). this bit is self-clear 0: trigger source disabled 1: trigger source enabled"]
                #[inline(always)]
                #[must_use]
                pub fn soft(&mut self) -> SOFT_W<SW_SPEC> {
                    SOFT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Software trigger\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SW_SPEC;
            impl crate::RegisterSpec for SW_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`sw::R`](R) reader structure"]
            impl crate::Readable for SW_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`sw::W`](W) writer structure"]
            impl crate::Writable for SW_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SW to value 0"]
            impl crate::Resettable for SW_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TRG_PRD_CFG (rw) register accessor: Period trigger configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_prd_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_prd_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trg_prd_cfg`]
module"]
        pub type TRG_PRD_CFG = crate::Reg<trg_prd_cfg::TRG_PRD_CFG_SPEC>;
        #[doc = "Period trigger configuration"]
        pub mod trg_prd_cfg {
            #[doc = "Register `TRG_PRD_CFG` reader"]
            pub type R = crate::R<TRG_PRD_CFG_SPEC>;
            #[doc = "Register `TRG_PRD_CFG` writer"]
            pub type W = crate::W<TRG_PRD_CFG_SPEC>;
            #[doc = "Field `SYNC` reader - Synchronous 0: Not synchronous 1: Synchronous every trigger source"]
            pub type SYNC_R = crate::BitReader;
            #[doc = "Field `SYNC` writer - Synchronous 0: Not synchronous 1: Synchronous every trigger source"]
            pub type SYNC_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `ARMING` reader - Wait for trigger synchronous before trigger 0: Trigger directly 1: Wait trigger source before period trigger"]
            pub type ARMING_R = crate::BitReader;
            #[doc = "Field `ARMING` writer - Wait for trigger synchronous before trigger 0: Trigger directly 1: Wait trigger source before period trigger"]
            pub type ARMING_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Synchronous 0: Not synchronous 1: Synchronous every trigger source"]
                #[inline(always)]
                pub fn sync(&self) -> SYNC_R {
                    SYNC_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 16 - Wait for trigger synchronous before trigger 0: Trigger directly 1: Wait trigger source before period trigger"]
                #[inline(always)]
                pub fn arming(&self) -> ARMING_R {
                    ARMING_R::new(((self.bits >> 16) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Synchronous 0: Not synchronous 1: Synchronous every trigger source"]
                #[inline(always)]
                #[must_use]
                pub fn sync(&mut self) -> SYNC_W<TRG_PRD_CFG_SPEC> {
                    SYNC_W::new(self, 0)
                }
                #[doc = "Bit 16 - Wait for trigger synchronous before trigger 0: Trigger directly 1: Wait trigger source before period trigger"]
                #[inline(always)]
                #[must_use]
                pub fn arming(&mut self) -> ARMING_W<TRG_PRD_CFG_SPEC> {
                    ARMING_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Period trigger configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_prd_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_prd_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TRG_PRD_CFG_SPEC;
            impl crate::RegisterSpec for TRG_PRD_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`trg_prd_cfg::R`](R) reader structure"]
            impl crate::Readable for TRG_PRD_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`trg_prd_cfg::W`](W) writer structure"]
            impl crate::Writable for TRG_PRD_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TRG_PRD_CFG to value 0"]
            impl crate::Resettable for TRG_PRD_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "PRD (rw) register accessor: Trigger period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prd`]
module"]
        pub type PRD = crate::Reg<prd::PRD_SPEC>;
        #[doc = "Trigger period"]
        pub mod prd {
            #[doc = "Register `PRD` reader"]
            pub type R = crate::R<PRD_SPEC>;
            #[doc = "Register `PRD` writer"]
            pub type W = crate::W<PRD_SPEC>;
            #[doc = "Field `PERIOD` reader - Trigger period"]
            pub type PERIOD_R = crate::FieldReader<u32>;
            #[doc = "Field `PERIOD` writer - Trigger period"]
            pub type PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Trigger period"]
                #[inline(always)]
                pub fn period(&self) -> PERIOD_R {
                    PERIOD_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Trigger period"]
                #[inline(always)]
                #[must_use]
                pub fn period(&mut self) -> PERIOD_W<PRD_SPEC> {
                    PERIOD_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Trigger period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PRD_SPEC;
            impl crate::RegisterSpec for PRD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`prd::R`](R) reader structure"]
            impl crate::Readable for PRD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`prd::W`](W) writer structure"]
            impl crate::Writable for PRD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PRD to value 0"]
            impl crate::Resettable for PRD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "OUT_CFG (rw) register accessor: Trigger output configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out_cfg`]
module"]
        pub type OUT_CFG = crate::Reg<out_cfg::OUT_CFG_SPEC>;
        #[doc = "Trigger output configuration"]
        pub mod out_cfg {
            #[doc = "Register `OUT_CFG` reader"]
            pub type R = crate::R<OUT_CFG_SPEC>;
            #[doc = "Register `OUT_CFG` writer"]
            pub type W = crate::W<OUT_CFG_SPEC>;
            #[doc = "Field `OUT0_SEL` reader - Trigger 0 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT0_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT0_SEL` writer - Trigger 0 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `OUT0_EN` reader - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
            pub type OUT0_EN_R = crate::BitReader;
            #[doc = "Field `OUT0_EN` writer - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
            pub type OUT0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `OUT1_SEL` reader - Trigger 1 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT1_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT1_SEL` writer - Trigger 1 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `OUT1_EN` reader - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
            pub type OUT1_EN_R = crate::BitReader;
            #[doc = "Field `OUT1_EN` writer - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
            pub type OUT1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `OUT2_SEL` reader - Trigger 2 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT2_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT2_SEL` writer - Trigger 2 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT2_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `OUT2_EN` reader - Enable trigger 2 0: disable trigger 2 1: enable trigger 2"]
            pub type OUT2_EN_R = crate::BitReader;
            #[doc = "Field `OUT2_EN` writer - Enable trigger 2 0: disable trigger 2 1: enable trigger 2"]
            pub type OUT2_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `OUT3_SEL` reader - Trigger 3 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT3_SEL_R = crate::FieldReader;
            #[doc = "Field `OUT3_SEL` writer - Trigger 3 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
            pub type OUT3_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `OUT3_EN` reader - Enable trigger 3 0: disable trigger 3 1: enable trigger 3"]
            pub type OUT3_EN_R = crate::BitReader;
            #[doc = "Field `OUT3_EN` writer - Enable trigger 3 0: disable trigger 3 1: enable trigger 3"]
            pub type OUT3_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:2 - Trigger 0 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                pub fn out0_sel(&self) -> OUT0_SEL_R {
                    OUT0_SEL_R::new((self.bits & 7) as u8)
                }
                #[doc = "Bit 7 - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                pub fn out0_en(&self) -> OUT0_EN_R {
                    OUT0_EN_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bits 8:10 - Trigger 1 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                pub fn out1_sel(&self) -> OUT1_SEL_R {
                    OUT1_SEL_R::new(((self.bits >> 8) & 7) as u8)
                }
                #[doc = "Bit 15 - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                pub fn out1_en(&self) -> OUT1_EN_R {
                    OUT1_EN_R::new(((self.bits >> 15) & 1) != 0)
                }
                #[doc = "Bits 16:18 - Trigger 2 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                pub fn out2_sel(&self) -> OUT2_SEL_R {
                    OUT2_SEL_R::new(((self.bits >> 16) & 7) as u8)
                }
                #[doc = "Bit 23 - Enable trigger 2 0: disable trigger 2 1: enable trigger 2"]
                #[inline(always)]
                pub fn out2_en(&self) -> OUT2_EN_R {
                    OUT2_EN_R::new(((self.bits >> 23) & 1) != 0)
                }
                #[doc = "Bits 24:26 - Trigger 3 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                pub fn out3_sel(&self) -> OUT3_SEL_R {
                    OUT3_SEL_R::new(((self.bits >> 24) & 7) as u8)
                }
                #[doc = "Bit 31 - Enable trigger 3 0: disable trigger 3 1: enable trigger 3"]
                #[inline(always)]
                pub fn out3_en(&self) -> OUT3_EN_R {
                    OUT3_EN_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:2 - Trigger 0 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                #[must_use]
                pub fn out0_sel(&mut self) -> OUT0_SEL_W<OUT_CFG_SPEC> {
                    OUT0_SEL_W::new(self, 0)
                }
                #[doc = "Bit 7 - Enable trigger 0 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                #[must_use]
                pub fn out0_en(&mut self) -> OUT0_EN_W<OUT_CFG_SPEC> {
                    OUT0_EN_W::new(self, 7)
                }
                #[doc = "Bits 8:10 - Trigger 1 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                #[must_use]
                pub fn out1_sel(&mut self) -> OUT1_SEL_W<OUT_CFG_SPEC> {
                    OUT1_SEL_W::new(self, 8)
                }
                #[doc = "Bit 15 - Enable trigger 1 0: disable trigger 1 1: enable trigger 1"]
                #[inline(always)]
                #[must_use]
                pub fn out1_en(&mut self) -> OUT1_EN_W<OUT_CFG_SPEC> {
                    OUT1_EN_W::new(self, 15)
                }
                #[doc = "Bits 16:18 - Trigger 2 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                #[must_use]
                pub fn out2_sel(&mut self) -> OUT2_SEL_W<OUT_CFG_SPEC> {
                    OUT2_SEL_W::new(self, 16)
                }
                #[doc = "Bit 23 - Enable trigger 2 0: disable trigger 2 1: enable trigger 2"]
                #[inline(always)]
                #[must_use]
                pub fn out2_en(&mut self) -> OUT2_EN_W<OUT_CFG_SPEC> {
                    OUT2_EN_W::new(self, 23)
                }
                #[doc = "Bits 24:26 - Trigger 3 sigal selection 0: trigger out 0 1: trigger out 1 ... 7: trigger out 7"]
                #[inline(always)]
                #[must_use]
                pub fn out3_sel(&mut self) -> OUT3_SEL_W<OUT_CFG_SPEC> {
                    OUT3_SEL_W::new(self, 24)
                }
                #[doc = "Bit 31 - Enable trigger 3 0: disable trigger 3 1: enable trigger 3"]
                #[inline(always)]
                #[must_use]
                pub fn out3_en(&mut self) -> OUT3_EN_W<OUT_CFG_SPEC> {
                    OUT3_EN_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Trigger output configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct OUT_CFG_SPEC;
            impl crate::RegisterSpec for OUT_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`out_cfg::R`](R) reader structure"]
            impl crate::Readable for OUT_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`out_cfg::W`](W) writer structure"]
            impl crate::Writable for OUT_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets OUT_CFG to value 0"]
            impl crate::Resettable for OUT_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "PRD_STS (rw) register accessor: Period trigger status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prd_sts`]
module"]
        pub type PRD_STS = crate::Reg<prd_sts::PRD_STS_SPEC>;
        #[doc = "Period trigger status"]
        pub mod prd_sts {
            #[doc = "Register `PRD_STS` reader"]
            pub type R = crate::R<PRD_STS_SPEC>;
            #[doc = "Register `PRD_STS` writer"]
            pub type W = crate::W<PRD_STS_SPEC>;
            #[doc = "Field `ARMED` reader - Waiting for trigger 0: Not in waiting status 1: In waiting status"]
            pub type ARMED_R = crate::BitReader;
            #[doc = "Field `TRIGERED` reader - Period has been triggered 0: Not triggered 1: Triggered"]
            pub type TRIGERED_R = crate::BitReader;
            impl R {
                #[doc = "Bit 16 - Waiting for trigger 0: Not in waiting status 1: In waiting status"]
                #[inline(always)]
                pub fn armed(&self) -> ARMED_R {
                    ARMED_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 20 - Period has been triggered 0: Not triggered 1: Triggered"]
                #[inline(always)]
                pub fn trigered(&self) -> TRIGERED_R {
                    TRIGERED_R::new(((self.bits >> 20) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Period trigger status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PRD_STS_SPEC;
            impl crate::RegisterSpec for PRD_STS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`prd_sts::R`](R) reader structure"]
            impl crate::Readable for PRD_STS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`prd_sts::W`](W) writer structure"]
            impl crate::Writable for PRD_STS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PRD_STS to value 0"]
            impl crate::Resettable for PRD_STS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "PRD_CNT (rw) register accessor: Period trigger counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_cnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prd_cnt`]
module"]
        pub type PRD_CNT = crate::Reg<prd_cnt::PRD_CNT_SPEC>;
        #[doc = "Period trigger counter"]
        pub mod prd_cnt {
            #[doc = "Register `PRD_CNT` reader"]
            pub type R = crate::R<PRD_CNT_SPEC>;
            #[doc = "Register `PRD_CNT` writer"]
            pub type W = crate::W<PRD_CNT_SPEC>;
            #[doc = "Field `PERIOD_CNT` reader - Trigger period counter"]
            pub type PERIOD_CNT_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Trigger period counter"]
                #[inline(always)]
                pub fn period_cnt(&self) -> PERIOD_CNT_R {
                    PERIOD_CNT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Period trigger counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_cnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PRD_CNT_SPEC;
            impl crate::RegisterSpec for PRD_CNT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`prd_cnt::R`](R) reader structure"]
            impl crate::Readable for PRD_CNT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`prd_cnt::W`](W) writer structure"]
            impl crate::Writable for PRD_CNT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PRD_CNT to value 0"]
            impl crate::Resettable for PRD_CNT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TRG_TABLE_CMD (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_table_cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_table_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trg_table_cmd`]
module"]
        pub type TRG_TABLE_CMD = crate::Reg<trg_table_cmd::TRG_TABLE_CMD_SPEC>;
        #[doc = "no description available"]
        pub mod trg_table_cmd {
            #[doc = "Register `TRG_TABLE_CMD[%s]` reader"]
            pub type R = crate::R<TRG_TABLE_CMD_SPEC>;
            #[doc = "Register `TRG_TABLE_CMD[%s]` writer"]
            pub type W = crate::W<TRG_TABLE_CMD_SPEC>;
            #[doc = "Field `CMD_TRIGGER0` reader - Trigger command"]
            pub type CMD_TRIGGER0_R = crate::FieldReader<u32>;
            #[doc = "Field `CMD_TRIGGER0` writer - Trigger command"]
            pub type CMD_TRIGGER0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Trigger command"]
                #[inline(always)]
                pub fn cmd_trigger0(&self) -> CMD_TRIGGER0_R {
                    CMD_TRIGGER0_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Trigger command"]
                #[inline(always)]
                #[must_use]
                pub fn cmd_trigger0(&mut self) -> CMD_TRIGGER0_W<TRG_TABLE_CMD_SPEC> {
                    CMD_TRIGGER0_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_table_cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_table_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TRG_TABLE_CMD_SPEC;
            impl crate::RegisterSpec for TRG_TABLE_CMD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`trg_table_cmd::R`](R) reader structure"]
            impl crate::Readable for TRG_TABLE_CMD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`trg_table_cmd::W`](W) writer structure"]
            impl crate::Writable for TRG_TABLE_CMD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TRG_TABLE_CMD[%s]
to value 0"]
            impl crate::Resettable for TRG_TABLE_CMD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TIME (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@time`]
module"]
        pub type TIME = crate::Reg<time::TIME_SPEC>;
        #[doc = "no description available"]
        pub mod time {
            #[doc = "Register `TIME[%s]` reader"]
            pub type R = crate::R<TIME_SPEC>;
            #[doc = "Register `TIME[%s]` writer"]
            pub type W = crate::W<TIME_SPEC>;
            #[doc = "Field `TRIGGER0_TIME` reader - Trigger time"]
            pub type TRIGGER0_TIME_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Trigger time"]
                #[inline(always)]
                pub fn trigger0_time(&self) -> TRIGGER0_TIME_R {
                    TRIGGER0_TIME_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TIME_SPEC;
            impl crate::RegisterSpec for TIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`time::R`](R) reader structure"]
            impl crate::Readable for TIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`time::W`](W) writer structure"]
            impl crate::Writable for TIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TIME[%s]
to value 0"]
            impl crate::Resettable for TIME_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "MODE (rw) register accessor: command register mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`]
module"]
        pub type MODE = crate::Reg<mode::MODE_SPEC>;
        #[doc = "command register mode"]
        pub mod mode {
            #[doc = "Register `MODE` reader"]
            pub type R = crate::R<MODE_SPEC>;
            #[doc = "Register `MODE` writer"]
            pub type W = crate::W<MODE_SPEC>;
            #[doc = "Field `MODE` reader - Data mode 0: data mode 1: check mode 2: CRC mode"]
            pub type MODE_R = crate::FieldReader;
            #[doc = "Field `MODE` writer - Data mode 0: data mode 1: check mode 2: CRC mode"]
            pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `REWIND` writer - Write 1 to rewind read/write pointer, this is a self clear bit"]
            pub type REWIND_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SIGNED` reader - Signed 0: unsigned value 1: signed value"]
            pub type SIGNED_R = crate::BitReader;
            #[doc = "Field `SIGNED` writer - Signed 0: unsigned value 1: signed value"]
            pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `BORDER` reader - bit order 0: LSB first 1: MSB first"]
            pub type BORDER_R = crate::BitReader;
            #[doc = "Field `BORDER` writer - bit order 0: LSB first 1: MSB first"]
            pub type BORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WORDER` reader - word order 0: sample as bit order 1: different from bit order"]
            pub type WORDER_R = crate::BitReader;
            #[doc = "Field `WORDER` writer - word order 0: sample as bit order 1: different from bit order"]
            pub type WORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WLEN` reader - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type WLEN_R = crate::FieldReader;
            #[doc = "Field `WLEN` writer - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type WLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            impl R {
                #[doc = "Bits 0:1 - Data mode 0: data mode 1: check mode 2: CRC mode"]
                #[inline(always)]
                pub fn mode(&self) -> MODE_R {
                    MODE_R::new((self.bits & 3) as u8)
                }
                #[doc = "Bit 9 - Signed 0: unsigned value 1: signed value"]
                #[inline(always)]
                pub fn signed(&self) -> SIGNED_R {
                    SIGNED_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - bit order 0: LSB first 1: MSB first"]
                #[inline(always)]
                pub fn border(&self) -> BORDER_R {
                    BORDER_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 11 - word order 0: sample as bit order 1: different from bit order"]
                #[inline(always)]
                pub fn worder(&self) -> WORDER_R {
                    WORDER_R::new(((self.bits >> 11) & 1) != 0)
                }
                #[doc = "Bits 16:20 - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                pub fn wlen(&self) -> WLEN_R {
                    WLEN_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:1 - Data mode 0: data mode 1: check mode 2: CRC mode"]
                #[inline(always)]
                #[must_use]
                pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
                    MODE_W::new(self, 0)
                }
                #[doc = "Bit 8 - Write 1 to rewind read/write pointer, this is a self clear bit"]
                #[inline(always)]
                #[must_use]
                pub fn rewind(&mut self) -> REWIND_W<MODE_SPEC> {
                    REWIND_W::new(self, 8)
                }
                #[doc = "Bit 9 - Signed 0: unsigned value 1: signed value"]
                #[inline(always)]
                #[must_use]
                pub fn signed(&mut self) -> SIGNED_W<MODE_SPEC> {
                    SIGNED_W::new(self, 9)
                }
                #[doc = "Bit 10 - bit order 0: LSB first 1: MSB first"]
                #[inline(always)]
                #[must_use]
                pub fn border(&mut self) -> BORDER_W<MODE_SPEC> {
                    BORDER_W::new(self, 10)
                }
                #[doc = "Bit 11 - word order 0: sample as bit order 1: different from bit order"]
                #[inline(always)]
                #[must_use]
                pub fn worder(&mut self) -> WORDER_W<MODE_SPEC> {
                    WORDER_W::new(self, 11)
                }
                #[doc = "Bits 16:20 - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                #[must_use]
                pub fn wlen(&mut self) -> WLEN_W<MODE_SPEC> {
                    WLEN_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "command register mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MODE_SPEC;
            impl crate::RegisterSpec for MODE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`mode::R`](R) reader structure"]
            impl crate::Readable for MODE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
            impl crate::Writable for MODE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets MODE to value 0"]
            impl crate::Resettable for MODE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "IDX (rw) register accessor: command register configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idx::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idx`]
module"]
        pub type IDX = crate::Reg<idx::IDX_SPEC>;
        #[doc = "command register configuration"]
        pub mod idx {
            #[doc = "Register `IDX` reader"]
            pub type R = crate::R<IDX_SPEC>;
            #[doc = "Register `IDX` writer"]
            pub type W = crate::W<IDX_SPEC>;
            #[doc = "Field `MIN_BIT` reader - Lowest bit index"]
            pub type MIN_BIT_R = crate::FieldReader;
            #[doc = "Field `MIN_BIT` writer - Lowest bit index"]
            pub type MIN_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `MAX_BIT` reader - Highest bit index"]
            pub type MAX_BIT_R = crate::FieldReader;
            #[doc = "Field `MAX_BIT` writer - Highest bit index"]
            pub type MAX_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `FIRST_BIT` reader - First bit index for tranceive"]
            pub type FIRST_BIT_R = crate::FieldReader;
            #[doc = "Field `FIRST_BIT` writer - First bit index for tranceive"]
            pub type FIRST_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `LAST_BIT` reader - Last bit index for tranceive"]
            pub type LAST_BIT_R = crate::FieldReader;
            #[doc = "Field `LAST_BIT` writer - Last bit index for tranceive"]
            pub type LAST_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            impl R {
                #[doc = "Bits 0:4 - Lowest bit index"]
                #[inline(always)]
                pub fn min_bit(&self) -> MIN_BIT_R {
                    MIN_BIT_R::new((self.bits & 0x1f) as u8)
                }
                #[doc = "Bits 8:12 - Highest bit index"]
                #[inline(always)]
                pub fn max_bit(&self) -> MAX_BIT_R {
                    MAX_BIT_R::new(((self.bits >> 8) & 0x1f) as u8)
                }
                #[doc = "Bits 16:20 - First bit index for tranceive"]
                #[inline(always)]
                pub fn first_bit(&self) -> FIRST_BIT_R {
                    FIRST_BIT_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - Last bit index for tranceive"]
                #[inline(always)]
                pub fn last_bit(&self) -> LAST_BIT_R {
                    LAST_BIT_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:4 - Lowest bit index"]
                #[inline(always)]
                #[must_use]
                pub fn min_bit(&mut self) -> MIN_BIT_W<IDX_SPEC> {
                    MIN_BIT_W::new(self, 0)
                }
                #[doc = "Bits 8:12 - Highest bit index"]
                #[inline(always)]
                #[must_use]
                pub fn max_bit(&mut self) -> MAX_BIT_W<IDX_SPEC> {
                    MAX_BIT_W::new(self, 8)
                }
                #[doc = "Bits 16:20 - First bit index for tranceive"]
                #[inline(always)]
                #[must_use]
                pub fn first_bit(&mut self) -> FIRST_BIT_W<IDX_SPEC> {
                    FIRST_BIT_W::new(self, 16)
                }
                #[doc = "Bits 24:28 - Last bit index for tranceive"]
                #[inline(always)]
                #[must_use]
                pub fn last_bit(&mut self) -> LAST_BIT_W<IDX_SPEC> {
                    LAST_BIT_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "command register configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idx::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct IDX_SPEC;
            impl crate::RegisterSpec for IDX_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`idx::R`](R) reader structure"]
            impl crate::Readable for IDX_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`idx::W`](W) writer structure"]
            impl crate::Writable for IDX_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets IDX to value 0"]
            impl crate::Resettable for IDX_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "GOLD (rw) register accessor: Command gold value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gold::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gold`]
module"]
        pub type GOLD = crate::Reg<gold::GOLD_SPEC>;
        #[doc = "Command gold value"]
        pub mod gold {
            #[doc = "Register `GOLD` reader"]
            pub type R = crate::R<GOLD_SPEC>;
            #[doc = "Register `GOLD` writer"]
            pub type W = crate::W<GOLD_SPEC>;
            #[doc = "Field `GOLD_VALUE` reader - Gold value for check mode"]
            pub type GOLD_VALUE_R = crate::FieldReader<u32>;
            #[doc = "Field `GOLD_VALUE` writer - Gold value for check mode"]
            pub type GOLD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Gold value for check mode"]
                #[inline(always)]
                pub fn gold_value(&self) -> GOLD_VALUE_R {
                    GOLD_VALUE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Gold value for check mode"]
                #[inline(always)]
                #[must_use]
                pub fn gold_value(&mut self) -> GOLD_VALUE_W<GOLD_SPEC> {
                    GOLD_VALUE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Command gold value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gold::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct GOLD_SPEC;
            impl crate::RegisterSpec for GOLD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`gold::R`](R) reader structure"]
            impl crate::Readable for GOLD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`gold::W`](W) writer structure"]
            impl crate::Writable for GOLD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets GOLD to value 0"]
            impl crate::Resettable for GOLD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CRCINIT (rw) register accessor: Command Initial value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcinit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcinit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcinit`]
module"]
        pub type CRCINIT = crate::Reg<crcinit::CRCINIT_SPEC>;
        #[doc = "Command Initial value"]
        pub mod crcinit {
            #[doc = "Register `CRCINIT` reader"]
            pub type R = crate::R<CRCINIT_SPEC>;
            #[doc = "Register `CRCINIT` writer"]
            pub type W = crate::W<CRCINIT_SPEC>;
            #[doc = "Field `CRC_INIT` reader - CRC initial value"]
            pub type CRC_INIT_R = crate::FieldReader<u32>;
            #[doc = "Field `CRC_INIT` writer - CRC initial value"]
            pub type CRC_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - CRC initial value"]
                #[inline(always)]
                pub fn crc_init(&self) -> CRC_INIT_R {
                    CRC_INIT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - CRC initial value"]
                #[inline(always)]
                #[must_use]
                pub fn crc_init(&mut self) -> CRC_INIT_W<CRCINIT_SPEC> {
                    CRC_INIT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Command Initial value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcinit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcinit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CRCINIT_SPEC;
            impl crate::RegisterSpec for CRCINIT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`crcinit::R`](R) reader structure"]
            impl crate::Readable for CRCINIT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`crcinit::W`](W) writer structure"]
            impl crate::Writable for CRCINIT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CRCINIT to value 0"]
            impl crate::Resettable for CRCINIT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CRCPOLY (rw) register accessor: Command CRC polymial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcpoly::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcpoly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcpoly`]
module"]
        pub type CRCPOLY = crate::Reg<crcpoly::CRCPOLY_SPEC>;
        #[doc = "Command CRC polymial"]
        pub mod crcpoly {
            #[doc = "Register `CRCPOLY` reader"]
            pub type R = crate::R<CRCPOLY_SPEC>;
            #[doc = "Register `CRCPOLY` writer"]
            pub type W = crate::W<CRCPOLY_SPEC>;
            #[doc = "Field `CRC_POLY` reader - CRC polymonial"]
            pub type CRC_POLY_R = crate::FieldReader<u32>;
            #[doc = "Field `CRC_POLY` writer - CRC polymonial"]
            pub type CRC_POLY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - CRC polymonial"]
                #[inline(always)]
                pub fn crc_poly(&self) -> CRC_POLY_R {
                    CRC_POLY_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - CRC polymonial"]
                #[inline(always)]
                #[must_use]
                pub fn crc_poly(&mut self) -> CRC_POLY_W<CRCPOLY_SPEC> {
                    CRC_POLY_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Command CRC polymial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcpoly::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcpoly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CRCPOLY_SPEC;
            impl crate::RegisterSpec for CRCPOLY_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`crcpoly::R`](R) reader structure"]
            impl crate::Readable for CRCPOLY_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`crcpoly::W`](W) writer structure"]
            impl crate::Writable for CRCPOLY_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CRCPOLY to value 0"]
            impl crate::Resettable for CRCPOLY_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CMD (rw) register accessor: command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"]
        pub type CMD = crate::Reg<cmd::CMD_SPEC>;
        #[doc = "command"]
        pub mod cmd {
            #[doc = "Register `CMD` reader"]
            pub type R = crate::R<CMD_SPEC>;
            #[doc = "Register `CMD` writer"]
            pub type W = crate::W<CMD_SPEC>;
            #[doc = "Field `DATA` reader - DATA"]
            pub type DATA_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA` writer - DATA"]
            pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA"]
                #[inline(always)]
                pub fn data(&self) -> DATA_R {
                    DATA_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA"]
                #[inline(always)]
                #[must_use]
                pub fn data(&mut self) -> DATA_W<CMD_SPEC> {
                    DATA_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CMD_SPEC;
            impl crate::RegisterSpec for CMD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
            impl crate::Readable for CMD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
            impl crate::Writable for CMD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CMD to value 0"]
            impl crate::Resettable for CMD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: command bit set register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "command bit set register"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `DATA_SET` reader - DATA bit set"]
            pub type DATA_SET_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA_SET` writer - DATA bit set"]
            pub type DATA_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA bit set"]
                #[inline(always)]
                pub fn data_set(&self) -> DATA_SET_R {
                    DATA_SET_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA bit set"]
                #[inline(always)]
                #[must_use]
                pub fn data_set(&mut self) -> DATA_SET_W<SET_SPEC> {
                    DATA_SET_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "command bit set register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLR (rw) register accessor: command bit clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr`]
module"]
        pub type CLR = crate::Reg<clr::CLR_SPEC>;
        #[doc = "command bit clear register"]
        pub mod clr {
            #[doc = "Register `CLR` reader"]
            pub type R = crate::R<CLR_SPEC>;
            #[doc = "Register `CLR` writer"]
            pub type W = crate::W<CLR_SPEC>;
            #[doc = "Field `DATA_CLR` reader - DATA bit clear"]
            pub type DATA_CLR_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA_CLR` writer - DATA bit clear"]
            pub type DATA_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA bit clear"]
                #[inline(always)]
                pub fn data_clr(&self) -> DATA_CLR_R {
                    DATA_CLR_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA bit clear"]
                #[inline(always)]
                #[must_use]
                pub fn data_clr(&mut self) -> DATA_CLR_W<CLR_SPEC> {
                    DATA_CLR_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "command bit clear register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLR_SPEC;
            impl crate::RegisterSpec for CLR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clr::R`](R) reader structure"]
            impl crate::Readable for CLR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
            impl crate::Writable for CLR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLR to value 0"]
            impl crate::Resettable for CLR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "INV (rw) register accessor: command bit invert register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inv`]
module"]
        pub type INV = crate::Reg<inv::INV_SPEC>;
        #[doc = "command bit invert register"]
        pub mod inv {
            #[doc = "Register `INV` reader"]
            pub type R = crate::R<INV_SPEC>;
            #[doc = "Register `INV` writer"]
            pub type W = crate::W<INV_SPEC>;
            #[doc = "Field `DATA_TGL` reader - DATA bit toggle"]
            pub type DATA_TGL_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA_TGL` writer - DATA bit toggle"]
            pub type DATA_TGL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA bit toggle"]
                #[inline(always)]
                pub fn data_tgl(&self) -> DATA_TGL_R {
                    DATA_TGL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA bit toggle"]
                #[inline(always)]
                #[must_use]
                pub fn data_tgl(&mut self) -> DATA_TGL_W<INV_SPEC> {
                    DATA_TGL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "command bit invert register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INV_SPEC;
            impl crate::RegisterSpec for INV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`inv::R`](R) reader structure"]
            impl crate::Readable for INV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`inv::W`](W) writer structure"]
            impl crate::Writable for INV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INV to value 0"]
            impl crate::Resettable for INV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "IN (rw) register accessor: Commad input\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_`]
module"]
        pub type IN = crate::Reg<in_::IN_SPEC>;
        #[doc = "Commad input"]
        pub mod in_ {
            #[doc = "Register `IN` reader"]
            pub type R = crate::R<IN_SPEC>;
            #[doc = "Register `IN` writer"]
            pub type W = crate::W<IN_SPEC>;
            #[doc = "Field `DATA_IN` reader - Commad input"]
            pub type DATA_IN_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Commad input"]
                #[inline(always)]
                pub fn data_in(&self) -> DATA_IN_R {
                    DATA_IN_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Commad input\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct IN_SPEC;
            impl crate::RegisterSpec for IN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`in_::R`](R) reader structure"]
            impl crate::Readable for IN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`in_::W`](W) writer structure"]
            impl crate::Writable for IN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets IN to value 0"]
            impl crate::Resettable for IN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "OUT (rw) register accessor: Command output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`]
module"]
        pub type OUT = crate::Reg<out::OUT_SPEC>;
        #[doc = "Command output"]
        pub mod out {
            #[doc = "Register `OUT` reader"]
            pub type R = crate::R<OUT_SPEC>;
            #[doc = "Register `OUT` writer"]
            pub type W = crate::W<OUT_SPEC>;
            #[doc = "Field `DATA_OUT` reader - Command output"]
            pub type DATA_OUT_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Command output"]
                #[inline(always)]
                pub fn data_out(&self) -> DATA_OUT_R {
                    DATA_OUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Command output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct OUT_SPEC;
            impl crate::RegisterSpec for OUT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`out::R`](R) reader structure"]
            impl crate::Readable for OUT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"]
            impl crate::Writable for OUT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets OUT to value 0"]
            impl crate::Resettable for OUT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "STS (rw) register accessor: Command status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sts`]
module"]
        pub type STS = crate::Reg<sts::STS_SPEC>;
        #[doc = "Command status"]
        pub mod sts {
            #[doc = "Register `STS` reader"]
            pub type R = crate::R<STS_SPEC>;
            #[doc = "Register `STS` writer"]
            pub type W = crate::W<STS_SPEC>;
            #[doc = "Field `BIT_IDX` reader - Bit index"]
            pub type BIT_IDX_R = crate::FieldReader;
            #[doc = "Field `WORD_CNT` reader - Word counter"]
            pub type WORD_CNT_R = crate::FieldReader;
            #[doc = "Field `WORD_IDX` reader - Word index"]
            pub type WORD_IDX_R = crate::FieldReader;
            #[doc = "Field `CRC_IDX` reader - CRC index"]
            pub type CRC_IDX_R = crate::FieldReader;
            impl R {
                #[doc = "Bits 0:4 - Bit index"]
                #[inline(always)]
                pub fn bit_idx(&self) -> BIT_IDX_R {
                    BIT_IDX_R::new((self.bits & 0x1f) as u8)
                }
                #[doc = "Bits 8:12 - Word counter"]
                #[inline(always)]
                pub fn word_cnt(&self) -> WORD_CNT_R {
                    WORD_CNT_R::new(((self.bits >> 8) & 0x1f) as u8)
                }
                #[doc = "Bits 16:20 - Word index"]
                #[inline(always)]
                pub fn word_idx(&self) -> WORD_IDX_R {
                    WORD_IDX_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - CRC index"]
                #[inline(always)]
                pub fn crc_idx(&self) -> CRC_IDX_R {
                    CRC_IDX_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Command status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct STS_SPEC;
            impl crate::RegisterSpec for STS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`sts::R`](R) reader structure"]
            impl crate::Readable for STS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`sts::W`](W) writer structure"]
            impl crate::Writable for STS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets STS to value 0"]
            impl crate::Resettable for STS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "no description available"]
        pub use self::cmd_table::CMD_TABLE;
        #[doc = r"Cluster"]
        #[doc = "no description available"]
        pub mod cmd_table {
            #[doc = r"Register block"]
            #[repr(C)]
            pub struct CMD_TABLE {
                min: MIN,
                max: MAX,
                msk: MSK,
                _reserved3: [u8; 0x04],
                pta: PTA,
                ptb: PTB,
            }
            impl CMD_TABLE {
                #[doc = "0x00 - command start value"]
                #[inline(always)]
                pub const fn min(&self) -> &MIN {
                    &self.min
                }
                #[doc = "0x04 - command end value"]
                #[inline(always)]
                pub const fn max(&self) -> &MAX {
                    &self.max
                }
                #[doc = "0x08 - command compare bit enable"]
                #[inline(always)]
                pub const fn msk(&self) -> &MSK {
                    &self.msk
                }
                #[doc = "0x10 - command pointer 0 - 3"]
                #[inline(always)]
                pub const fn pta(&self) -> &PTA {
                    &self.pta
                }
                #[doc = "0x14 - command pointer 4 - 7"]
                #[inline(always)]
                pub const fn ptb(&self) -> &PTB {
                    &self.ptb
                }
            }
            #[doc = "MIN (rw) register accessor: command start value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@min`]
module"]
            pub type MIN = crate::Reg<min::MIN_SPEC>;
            #[doc = "command start value"]
            pub mod min {
                #[doc = "Register `MIN` reader"]
                pub type R = crate::R<MIN_SPEC>;
                #[doc = "Register `MIN` writer"]
                pub type W = crate::W<MIN_SPEC>;
                #[doc = "Field `CMD_MIN` reader - minimum command value"]
                pub type CMD_MIN_R = crate::FieldReader<u32>;
                #[doc = "Field `CMD_MIN` writer - minimum command value"]
                pub type CMD_MIN_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
                impl R {
                    #[doc = "Bits 0:31 - minimum command value"]
                    #[inline(always)]
                    pub fn cmd_min(&self) -> CMD_MIN_R {
                        CMD_MIN_R::new(self.bits)
                    }
                }
                impl W {
                    #[doc = "Bits 0:31 - minimum command value"]
                    #[inline(always)]
                    #[must_use]
                    pub fn cmd_min(&mut self) -> CMD_MIN_W<MIN_SPEC> {
                        CMD_MIN_W::new(self, 0)
                    }
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "command start value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`min::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`min::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct MIN_SPEC;
                impl crate::RegisterSpec for MIN_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`min::R`](R) reader structure"]
                impl crate::Readable for MIN_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`min::W`](W) writer structure"]
                impl crate::Writable for MIN_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets MIN to value 0"]
                impl crate::Resettable for MIN_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
            #[doc = "MAX (rw) register accessor: command end value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@max`]
module"]
            pub type MAX = crate::Reg<max::MAX_SPEC>;
            #[doc = "command end value"]
            pub mod max {
                #[doc = "Register `MAX` reader"]
                pub type R = crate::R<MAX_SPEC>;
                #[doc = "Register `MAX` writer"]
                pub type W = crate::W<MAX_SPEC>;
                #[doc = "Field `CMD_MAX` reader - maximum command value"]
                pub type CMD_MAX_R = crate::FieldReader<u32>;
                #[doc = "Field `CMD_MAX` writer - maximum command value"]
                pub type CMD_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
                impl R {
                    #[doc = "Bits 0:31 - maximum command value"]
                    #[inline(always)]
                    pub fn cmd_max(&self) -> CMD_MAX_R {
                        CMD_MAX_R::new(self.bits)
                    }
                }
                impl W {
                    #[doc = "Bits 0:31 - maximum command value"]
                    #[inline(always)]
                    #[must_use]
                    pub fn cmd_max(&mut self) -> CMD_MAX_W<MAX_SPEC> {
                        CMD_MAX_W::new(self, 0)
                    }
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "command end value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`max::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`max::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct MAX_SPEC;
                impl crate::RegisterSpec for MAX_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`max::R`](R) reader structure"]
                impl crate::Readable for MAX_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`max::W`](W) writer structure"]
                impl crate::Writable for MAX_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets MAX to value 0"]
                impl crate::Resettable for MAX_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
            #[doc = "MSK (rw) register accessor: command compare bit enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msk`]
module"]
            pub type MSK = crate::Reg<msk::MSK_SPEC>;
            #[doc = "command compare bit enable"]
            pub mod msk {
                #[doc = "Register `MSK` reader"]
                pub type R = crate::R<MSK_SPEC>;
                #[doc = "Register `MSK` writer"]
                pub type W = crate::W<MSK_SPEC>;
                #[doc = "Field `CMD_MASK` reader - compare mask"]
                pub type CMD_MASK_R = crate::FieldReader<u32>;
                #[doc = "Field `CMD_MASK` writer - compare mask"]
                pub type CMD_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
                impl R {
                    #[doc = "Bits 0:31 - compare mask"]
                    #[inline(always)]
                    pub fn cmd_mask(&self) -> CMD_MASK_R {
                        CMD_MASK_R::new(self.bits)
                    }
                }
                impl W {
                    #[doc = "Bits 0:31 - compare mask"]
                    #[inline(always)]
                    #[must_use]
                    pub fn cmd_mask(&mut self) -> CMD_MASK_W<MSK_SPEC> {
                        CMD_MASK_W::new(self, 0)
                    }
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "command compare bit enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct MSK_SPEC;
                impl crate::RegisterSpec for MSK_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`msk::R`](R) reader structure"]
                impl crate::Readable for MSK_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`msk::W`](W) writer structure"]
                impl crate::Writable for MSK_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets MSK to value 0"]
                impl crate::Resettable for MSK_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
            #[doc = "PTA (rw) register accessor: command pointer 0 - 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pta`]
module"]
            pub type PTA = crate::Reg<pta::PTA_SPEC>;
            #[doc = "command pointer 0 - 3"]
            pub mod pta {
                #[doc = "Register `PTA` reader"]
                pub type R = crate::R<PTA_SPEC>;
                #[doc = "Register `PTA` writer"]
                pub type W = crate::W<PTA_SPEC>;
                #[doc = "Field `PTR0` reader - pointer0"]
                pub type PTR0_R = crate::FieldReader;
                #[doc = "Field `PTR0` writer - pointer0"]
                pub type PTR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                #[doc = "Field `PTR1` reader - pointer1"]
                pub type PTR1_R = crate::FieldReader;
                #[doc = "Field `PTR1` writer - pointer1"]
                pub type PTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                #[doc = "Field `PTR2` reader - pointer2"]
                pub type PTR2_R = crate::FieldReader;
                #[doc = "Field `PTR2` writer - pointer2"]
                pub type PTR2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                #[doc = "Field `PTR3` reader - pointer3"]
                pub type PTR3_R = crate::FieldReader;
                #[doc = "Field `PTR3` writer - pointer3"]
                pub type PTR3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                impl R {
                    #[doc = "Bits 0:7 - pointer0"]
                    #[inline(always)]
                    pub fn ptr0(&self) -> PTR0_R {
                        PTR0_R::new((self.bits & 0xff) as u8)
                    }
                    #[doc = "Bits 8:15 - pointer1"]
                    #[inline(always)]
                    pub fn ptr1(&self) -> PTR1_R {
                        PTR1_R::new(((self.bits >> 8) & 0xff) as u8)
                    }
                    #[doc = "Bits 16:23 - pointer2"]
                    #[inline(always)]
                    pub fn ptr2(&self) -> PTR2_R {
                        PTR2_R::new(((self.bits >> 16) & 0xff) as u8)
                    }
                    #[doc = "Bits 24:31 - pointer3"]
                    #[inline(always)]
                    pub fn ptr3(&self) -> PTR3_R {
                        PTR3_R::new(((self.bits >> 24) & 0xff) as u8)
                    }
                }
                impl W {
                    #[doc = "Bits 0:7 - pointer0"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr0(&mut self) -> PTR0_W<PTA_SPEC> {
                        PTR0_W::new(self, 0)
                    }
                    #[doc = "Bits 8:15 - pointer1"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr1(&mut self) -> PTR1_W<PTA_SPEC> {
                        PTR1_W::new(self, 8)
                    }
                    #[doc = "Bits 16:23 - pointer2"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr2(&mut self) -> PTR2_W<PTA_SPEC> {
                        PTR2_W::new(self, 16)
                    }
                    #[doc = "Bits 24:31 - pointer3"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr3(&mut self) -> PTR3_W<PTA_SPEC> {
                        PTR3_W::new(self, 24)
                    }
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "command pointer 0 - 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct PTA_SPEC;
                impl crate::RegisterSpec for PTA_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`pta::R`](R) reader structure"]
                impl crate::Readable for PTA_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`pta::W`](W) writer structure"]
                impl crate::Writable for PTA_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets PTA to value 0"]
                impl crate::Resettable for PTA_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
            #[doc = "PTB (rw) register accessor: command pointer 4 - 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ptb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ptb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ptb`]
module"]
            pub type PTB = crate::Reg<ptb::PTB_SPEC>;
            #[doc = "command pointer 4 - 7"]
            pub mod ptb {
                #[doc = "Register `PTB` reader"]
                pub type R = crate::R<PTB_SPEC>;
                #[doc = "Register `PTB` writer"]
                pub type W = crate::W<PTB_SPEC>;
                #[doc = "Field `PTR4` reader - pointer4"]
                pub type PTR4_R = crate::FieldReader;
                #[doc = "Field `PTR4` writer - pointer4"]
                pub type PTR4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                #[doc = "Field `PTR5` reader - pointer5"]
                pub type PTR5_R = crate::FieldReader;
                #[doc = "Field `PTR5` writer - pointer5"]
                pub type PTR5_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                #[doc = "Field `PTR6` reader - pointer6"]
                pub type PTR6_R = crate::FieldReader;
                #[doc = "Field `PTR6` writer - pointer6"]
                pub type PTR6_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                #[doc = "Field `PTR7` reader - pointer7"]
                pub type PTR7_R = crate::FieldReader;
                #[doc = "Field `PTR7` writer - pointer7"]
                pub type PTR7_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                impl R {
                    #[doc = "Bits 0:7 - pointer4"]
                    #[inline(always)]
                    pub fn ptr4(&self) -> PTR4_R {
                        PTR4_R::new((self.bits & 0xff) as u8)
                    }
                    #[doc = "Bits 8:15 - pointer5"]
                    #[inline(always)]
                    pub fn ptr5(&self) -> PTR5_R {
                        PTR5_R::new(((self.bits >> 8) & 0xff) as u8)
                    }
                    #[doc = "Bits 16:23 - pointer6"]
                    #[inline(always)]
                    pub fn ptr6(&self) -> PTR6_R {
                        PTR6_R::new(((self.bits >> 16) & 0xff) as u8)
                    }
                    #[doc = "Bits 24:31 - pointer7"]
                    #[inline(always)]
                    pub fn ptr7(&self) -> PTR7_R {
                        PTR7_R::new(((self.bits >> 24) & 0xff) as u8)
                    }
                }
                impl W {
                    #[doc = "Bits 0:7 - pointer4"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr4(&mut self) -> PTR4_W<PTB_SPEC> {
                        PTR4_W::new(self, 0)
                    }
                    #[doc = "Bits 8:15 - pointer5"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr5(&mut self) -> PTR5_W<PTB_SPEC> {
                        PTR5_W::new(self, 8)
                    }
                    #[doc = "Bits 16:23 - pointer6"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr6(&mut self) -> PTR6_W<PTB_SPEC> {
                        PTR6_W::new(self, 16)
                    }
                    #[doc = "Bits 24:31 - pointer7"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ptr7(&mut self) -> PTR7_W<PTB_SPEC> {
                        PTR7_W::new(self, 24)
                    }
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "command pointer 4 - 7\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ptb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ptb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct PTB_SPEC;
                impl crate::RegisterSpec for PTB_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`ptb::R`](R) reader structure"]
                impl crate::Readable for PTB_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`ptb::W`](W) writer structure"]
                impl crate::Writable for PTB_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets PTB to value 0"]
                impl crate::Resettable for PTB_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
        }
        #[doc = "no description available"]
        pub use self::latch::LATCH;
        #[doc = r"Cluster"]
        #[doc = "no description available"]
        pub mod latch {
            #[doc = r"Register block"]
            #[repr(C)]
            pub struct LATCH {
                tran: [TRAN; 4],
                cfg: CFG,
                _reserved2: [u8; 0x04],
                time: TIME,
                sts: STS,
            }
            impl LATCH {
                #[doc = "0x00..0x10 - no description available"]
                #[inline(always)]
                pub const fn tran(&self, n: usize) -> &TRAN {
                    &self.tran[n]
                }
                #[doc = "Iterator for array of:"]
                #[doc = "0x00..0x10 - no description available"]
                #[inline(always)]
                pub fn tran_iter(&self) -> impl Iterator<Item = &TRAN> {
                    self.tran.iter()
                }
                #[doc = "0x00 - no description available"]
                #[inline(always)]
                pub const fn tran0_1(&self) -> &TRAN {
                    self.tran(0)
                }
                #[doc = "0x04 - no description available"]
                #[inline(always)]
                pub const fn tran1_2(&self) -> &TRAN {
                    self.tran(1)
                }
                #[doc = "0x08 - no description available"]
                #[inline(always)]
                pub const fn tran2_3(&self) -> &TRAN {
                    self.tran(2)
                }
                #[doc = "0x0c - no description available"]
                #[inline(always)]
                pub const fn tran3_0(&self) -> &TRAN {
                    self.tran(3)
                }
                #[doc = "0x10 - Latch configuration"]
                #[inline(always)]
                pub const fn cfg(&self) -> &CFG {
                    &self.cfg
                }
                #[doc = "0x18 - Latch time"]
                #[inline(always)]
                pub const fn time(&self) -> &TIME {
                    &self.time
                }
                #[doc = "0x1c - Latch status"]
                #[inline(always)]
                pub const fn sts(&self) -> &STS {
                    &self.sts
                }
            }
            #[doc = "TRAN (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tran::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tran::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tran`]
module"]
            pub type TRAN = crate::Reg<tran::TRAN_SPEC>;
            #[doc = "no description available"]
            pub mod tran {
                #[doc = "Register `TRAN[%s]` reader"]
                pub type R = crate::R<TRAN_SPEC>;
                #[doc = "Register `TRAN[%s]` writer"]
                pub type W = crate::W<TRAN_SPEC>;
                #[doc = "Field `OV_PTR` reader - override pointer check"]
                pub type OV_PTR_R = crate::BitReader;
                #[doc = "Field `OV_PTR` writer - override pointer check"]
                pub type OV_PTR_W<'a, REG> = crate::BitWriter<'a, REG>;
                #[doc = "Field `OV_CLK` reader - override clock check"]
                pub type OV_CLK_R = crate::BitReader;
                #[doc = "Field `OV_CLK` writer - override clock check"]
                pub type OV_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
                #[doc = "Field `OV_TXD` reader - override TX data check"]
                pub type OV_TXD_R = crate::BitReader;
                #[doc = "Field `OV_TXD` writer - override TX data check"]
                pub type OV_TXD_W<'a, REG> = crate::BitWriter<'a, REG>;
                #[doc = "Field `OV_TM` reader - override timeout check"]
                pub type OV_TM_R = crate::BitReader;
                #[doc = "Field `OV_TM` writer - override timeout check"]
                pub type OV_TM_W<'a, REG> = crate::BitWriter<'a, REG>;
                #[doc = "Field `CFG_PTR` reader - pointer 0: match 1: not match 2:entry 3:leave"]
                pub type CFG_PTR_R = crate::FieldReader;
                #[doc = "Field `CFG_PTR` writer - pointer 0: match 1: not match 2:entry 3:leave"]
                pub type CFG_PTR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
                #[doc = "Field `CFG_CLK` reader - clock 0: high 1: low 2: rise 3: fall"]
                pub type CFG_CLK_R = crate::FieldReader;
                #[doc = "Field `CFG_CLK` writer - clock 0: high 1: low 2: rise 3: fall"]
                pub type CFG_CLK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
                #[doc = "Field `CFG_TXD` reader - data send 0: high 1: low 2: rise 3: fall"]
                pub type CFG_TXD_R = crate::FieldReader;
                #[doc = "Field `CFG_TXD` writer - data send 0: high 1: low 2: rise 3: fall"]
                pub type CFG_TXD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
                #[doc = "Field `CFG_TM` reader - timeout 0: high 1: low 2: rise 3: fall"]
                pub type CFG_TM_R = crate::FieldReader;
                #[doc = "Field `CFG_TM` writer - timeout 0: high 1: low 2: rise 3: fall"]
                pub type CFG_TM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
                #[doc = "Field `POINTER` reader - pointer"]
                pub type POINTER_R = crate::FieldReader;
                #[doc = "Field `POINTER` writer - pointer"]
                pub type POINTER_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
                impl R {
                    #[doc = "Bit 0 - override pointer check"]
                    #[inline(always)]
                    pub fn ov_ptr(&self) -> OV_PTR_R {
                        OV_PTR_R::new((self.bits & 1) != 0)
                    }
                    #[doc = "Bit 1 - override clock check"]
                    #[inline(always)]
                    pub fn ov_clk(&self) -> OV_CLK_R {
                        OV_CLK_R::new(((self.bits >> 1) & 1) != 0)
                    }
                    #[doc = "Bit 2 - override TX data check"]
                    #[inline(always)]
                    pub fn ov_txd(&self) -> OV_TXD_R {
                        OV_TXD_R::new(((self.bits >> 2) & 1) != 0)
                    }
                    #[doc = "Bit 4 - override timeout check"]
                    #[inline(always)]
                    pub fn ov_tm(&self) -> OV_TM_R {
                        OV_TM_R::new(((self.bits >> 4) & 1) != 0)
                    }
                    #[doc = "Bits 8:9 - pointer 0: match 1: not match 2:entry 3:leave"]
                    #[inline(always)]
                    pub fn cfg_ptr(&self) -> CFG_PTR_R {
                        CFG_PTR_R::new(((self.bits >> 8) & 3) as u8)
                    }
                    #[doc = "Bits 10:11 - clock 0: high 1: low 2: rise 3: fall"]
                    #[inline(always)]
                    pub fn cfg_clk(&self) -> CFG_CLK_R {
                        CFG_CLK_R::new(((self.bits >> 10) & 3) as u8)
                    }
                    #[doc = "Bits 12:13 - data send 0: high 1: low 2: rise 3: fall"]
                    #[inline(always)]
                    pub fn cfg_txd(&self) -> CFG_TXD_R {
                        CFG_TXD_R::new(((self.bits >> 12) & 3) as u8)
                    }
                    #[doc = "Bits 16:17 - timeout 0: high 1: low 2: rise 3: fall"]
                    #[inline(always)]
                    pub fn cfg_tm(&self) -> CFG_TM_R {
                        CFG_TM_R::new(((self.bits >> 16) & 3) as u8)
                    }
                    #[doc = "Bits 24:31 - pointer"]
                    #[inline(always)]
                    pub fn pointer(&self) -> POINTER_R {
                        POINTER_R::new(((self.bits >> 24) & 0xff) as u8)
                    }
                }
                impl W {
                    #[doc = "Bit 0 - override pointer check"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ov_ptr(&mut self) -> OV_PTR_W<TRAN_SPEC> {
                        OV_PTR_W::new(self, 0)
                    }
                    #[doc = "Bit 1 - override clock check"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ov_clk(&mut self) -> OV_CLK_W<TRAN_SPEC> {
                        OV_CLK_W::new(self, 1)
                    }
                    #[doc = "Bit 2 - override TX data check"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ov_txd(&mut self) -> OV_TXD_W<TRAN_SPEC> {
                        OV_TXD_W::new(self, 2)
                    }
                    #[doc = "Bit 4 - override timeout check"]
                    #[inline(always)]
                    #[must_use]
                    pub fn ov_tm(&mut self) -> OV_TM_W<TRAN_SPEC> {
                        OV_TM_W::new(self, 4)
                    }
                    #[doc = "Bits 8:9 - pointer 0: match 1: not match 2:entry 3:leave"]
                    #[inline(always)]
                    #[must_use]
                    pub fn cfg_ptr(&mut self) -> CFG_PTR_W<TRAN_SPEC> {
                        CFG_PTR_W::new(self, 8)
                    }
                    #[doc = "Bits 10:11 - clock 0: high 1: low 2: rise 3: fall"]
                    #[inline(always)]
                    #[must_use]
                    pub fn cfg_clk(&mut self) -> CFG_CLK_W<TRAN_SPEC> {
                        CFG_CLK_W::new(self, 10)
                    }
                    #[doc = "Bits 12:13 - data send 0: high 1: low 2: rise 3: fall"]
                    #[inline(always)]
                    #[must_use]
                    pub fn cfg_txd(&mut self) -> CFG_TXD_W<TRAN_SPEC> {
                        CFG_TXD_W::new(self, 12)
                    }
                    #[doc = "Bits 16:17 - timeout 0: high 1: low 2: rise 3: fall"]
                    #[inline(always)]
                    #[must_use]
                    pub fn cfg_tm(&mut self) -> CFG_TM_W<TRAN_SPEC> {
                        CFG_TM_W::new(self, 16)
                    }
                    #[doc = "Bits 24:31 - pointer"]
                    #[inline(always)]
                    #[must_use]
                    pub fn pointer(&mut self) -> POINTER_W<TRAN_SPEC> {
                        POINTER_W::new(self, 24)
                    }
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tran::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tran::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct TRAN_SPEC;
                impl crate::RegisterSpec for TRAN_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`tran::R`](R) reader structure"]
                impl crate::Readable for TRAN_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`tran::W`](W) writer structure"]
                impl crate::Writable for TRAN_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets TRAN[%s]
to value 0"]
                impl crate::Resettable for TRAN_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
            #[doc = "CFG (rw) register accessor: Latch configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub type CFG = crate::Reg<cfg::CFG_SPEC>;
            #[doc = "Latch configuration"]
            pub mod cfg {
                #[doc = "Register `CFG` reader"]
                pub type R = crate::R<CFG_SPEC>;
                #[doc = "Register `CFG` writer"]
                pub type W = crate::W<CFG_SPEC>;
                #[doc = "Field `DELAY` reader - Delay in system clock cycle, for state transition"]
                pub type DELAY_R = crate::FieldReader<u16>;
                #[doc = "Field `DELAY` writer - Delay in system clock cycle, for state transition"]
                pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
                #[doc = "Field `SELECT` reader - Output select 0: state0-state1 1: state1-state2 2: state2-state3 3: state3-state0"]
                pub type SELECT_R = crate::FieldReader;
                #[doc = "Field `SELECT` writer - Output select 0: state0-state1 1: state1-state2 2: state2-state3 3: state3-state0"]
                pub type SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
                #[doc = "Field `EN` reader - Enable latch 0: disable 1: enable"]
                pub type EN_R = crate::BitReader;
                #[doc = "Field `EN` writer - Enable latch 0: disable 1: enable"]
                pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
                impl R {
                    #[doc = "Bits 0:15 - Delay in system clock cycle, for state transition"]
                    #[inline(always)]
                    pub fn delay(&self) -> DELAY_R {
                        DELAY_R::new((self.bits & 0xffff) as u16)
                    }
                    #[doc = "Bits 24:26 - Output select 0: state0-state1 1: state1-state2 2: state2-state3 3: state3-state0"]
                    #[inline(always)]
                    pub fn select(&self) -> SELECT_R {
                        SELECT_R::new(((self.bits >> 24) & 7) as u8)
                    }
                    #[doc = "Bit 31 - Enable latch 0: disable 1: enable"]
                    #[inline(always)]
                    pub fn en(&self) -> EN_R {
                        EN_R::new(((self.bits >> 31) & 1) != 0)
                    }
                }
                impl W {
                    #[doc = "Bits 0:15 - Delay in system clock cycle, for state transition"]
                    #[inline(always)]
                    #[must_use]
                    pub fn delay(&mut self) -> DELAY_W<CFG_SPEC> {
                        DELAY_W::new(self, 0)
                    }
                    #[doc = "Bits 24:26 - Output select 0: state0-state1 1: state1-state2 2: state2-state3 3: state3-state0"]
                    #[inline(always)]
                    #[must_use]
                    pub fn select(&mut self) -> SELECT_W<CFG_SPEC> {
                        SELECT_W::new(self, 24)
                    }
                    #[doc = "Bit 31 - Enable latch 0: disable 1: enable"]
                    #[inline(always)]
                    #[must_use]
                    pub fn en(&mut self) -> EN_W<CFG_SPEC> {
                        EN_W::new(self, 31)
                    }
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "Latch configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct CFG_SPEC;
                impl crate::RegisterSpec for CFG_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
                impl crate::Readable for CFG_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
                impl crate::Writable for CFG_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets CFG to value 0"]
                impl crate::Resettable for CFG_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
            #[doc = "TIME (rw) register accessor: Latch time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@time`]
module"]
            pub type TIME = crate::Reg<time::TIME_SPEC>;
            #[doc = "Latch time"]
            pub mod time {
                #[doc = "Register `TIME` reader"]
                pub type R = crate::R<TIME_SPEC>;
                #[doc = "Register `TIME` writer"]
                pub type W = crate::W<TIME_SPEC>;
                #[doc = "Field `LAT_TIME` reader - Latch time"]
                pub type LAT_TIME_R = crate::FieldReader<u32>;
                impl R {
                    #[doc = "Bits 0:31 - Latch time"]
                    #[inline(always)]
                    pub fn lat_time(&self) -> LAT_TIME_R {
                        LAT_TIME_R::new(self.bits)
                    }
                }
                impl W {
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "Latch time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct TIME_SPEC;
                impl crate::RegisterSpec for TIME_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`time::R`](R) reader structure"]
                impl crate::Readable for TIME_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`time::W`](W) writer structure"]
                impl crate::Writable for TIME_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets TIME to value 0"]
                impl crate::Resettable for TIME_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
            #[doc = "STS (rw) register accessor: Latch status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sts`]
module"]
            pub type STS = crate::Reg<sts::STS_SPEC>;
            #[doc = "Latch status"]
            pub mod sts {
                #[doc = "Register `STS` reader"]
                pub type R = crate::R<STS_SPEC>;
                #[doc = "Register `STS` writer"]
                pub type W = crate::W<STS_SPEC>;
                #[doc = "Field `LAT_CNT` reader - Latch counter"]
                pub type LAT_CNT_R = crate::FieldReader<u16>;
                #[doc = "Field `STATE` reader - State"]
                pub type STATE_R = crate::FieldReader;
                impl R {
                    #[doc = "Bits 0:15 - Latch counter"]
                    #[inline(always)]
                    pub fn lat_cnt(&self) -> LAT_CNT_R {
                        LAT_CNT_R::new((self.bits & 0xffff) as u16)
                    }
                    #[doc = "Bits 24:26 - State"]
                    #[inline(always)]
                    pub fn state(&self) -> STATE_R {
                        STATE_R::new(((self.bits >> 24) & 7) as u8)
                    }
                }
                impl W {
                    #[doc = r" Writes raw bits to the register."]
                    #[doc = r""]
                    #[doc = r" # Safety"]
                    #[doc = r""]
                    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                    #[inline(always)]
                    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                        self.bits = bits;
                        self
                    }
                }
                #[doc = "Latch status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
                pub struct STS_SPEC;
                impl crate::RegisterSpec for STS_SPEC {
                    type Ux = u32;
                }
                #[doc = "`read()` method returns [`sts::R`](R) reader structure"]
                impl crate::Readable for STS_SPEC {}
                #[doc = "`write(|w| ..)` method takes [`sts::W`](W) writer structure"]
                impl crate::Writable for STS_SPEC {
                    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                }
                #[doc = "`reset()` method sets STS to value 0"]
                impl crate::Resettable for STS_SPEC {
                    const RESET_VALUE: u32 = 0;
                }
            }
        }
        #[doc = "SMP_EN (rw) register accessor: Sample selection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_en`]
module"]
        pub type SMP_EN = crate::Reg<smp_en::SMP_EN_SPEC>;
        #[doc = "Sample selection register"]
        pub mod smp_en {
            #[doc = "Register `SMP_EN` reader"]
            pub type R = crate::R<SMP_EN_SPEC>;
            #[doc = "Register `SMP_EN` writer"]
            pub type W = crate::W<SMP_EN_SPEC>;
            #[doc = "Field `POS_SEL` reader - Data register for position transfer"]
            pub type POS_SEL_R = crate::FieldReader;
            #[doc = "Field `POS_SEL` writer - Data register for position transfer"]
            pub type POS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `POS_EN` reader - Position include position"]
            pub type POS_EN_R = crate::BitReader;
            #[doc = "Field `POS_EN` writer - Position include position"]
            pub type POS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `REV_SEL` reader - Data register for revolution transfer"]
            pub type REV_SEL_R = crate::FieldReader;
            #[doc = "Field `REV_SEL` writer - Data register for revolution transfer"]
            pub type REV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `REV_EN` reader - Position include revolution"]
            pub type REV_EN_R = crate::BitReader;
            #[doc = "Field `REV_EN` writer - Position include revolution"]
            pub type REV_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SPD_SEL` reader - Data register for speed transfer"]
            pub type SPD_SEL_R = crate::FieldReader;
            #[doc = "Field `SPD_SEL` writer - Data register for speed transfer"]
            pub type SPD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `SPD_EN` reader - Position include speed"]
            pub type SPD_EN_R = crate::BitReader;
            #[doc = "Field `SPD_EN` writer - Position include speed"]
            pub type SPD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `ACC_SEL` reader - Data register for acceleration transfer"]
            pub type ACC_SEL_R = crate::FieldReader;
            #[doc = "Field `ACC_SEL` writer - Data register for acceleration transfer"]
            pub type ACC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `ACC_EN` reader - Position include acceleration"]
            pub type ACC_EN_R = crate::BitReader;
            #[doc = "Field `ACC_EN` writer - Position include acceleration"]
            pub type ACC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:4 - Data register for position transfer"]
                #[inline(always)]
                pub fn pos_sel(&self) -> POS_SEL_R {
                    POS_SEL_R::new((self.bits & 0x1f) as u8)
                }
                #[doc = "Bit 7 - Position include position"]
                #[inline(always)]
                pub fn pos_en(&self) -> POS_EN_R {
                    POS_EN_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bits 8:12 - Data register for revolution transfer"]
                #[inline(always)]
                pub fn rev_sel(&self) -> REV_SEL_R {
                    REV_SEL_R::new(((self.bits >> 8) & 0x1f) as u8)
                }
                #[doc = "Bit 15 - Position include revolution"]
                #[inline(always)]
                pub fn rev_en(&self) -> REV_EN_R {
                    REV_EN_R::new(((self.bits >> 15) & 1) != 0)
                }
                #[doc = "Bits 16:20 - Data register for speed transfer"]
                #[inline(always)]
                pub fn spd_sel(&self) -> SPD_SEL_R {
                    SPD_SEL_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bit 23 - Position include speed"]
                #[inline(always)]
                pub fn spd_en(&self) -> SPD_EN_R {
                    SPD_EN_R::new(((self.bits >> 23) & 1) != 0)
                }
                #[doc = "Bits 24:28 - Data register for acceleration transfer"]
                #[inline(always)]
                pub fn acc_sel(&self) -> ACC_SEL_R {
                    ACC_SEL_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
                #[doc = "Bit 31 - Position include acceleration"]
                #[inline(always)]
                pub fn acc_en(&self) -> ACC_EN_R {
                    ACC_EN_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:4 - Data register for position transfer"]
                #[inline(always)]
                #[must_use]
                pub fn pos_sel(&mut self) -> POS_SEL_W<SMP_EN_SPEC> {
                    POS_SEL_W::new(self, 0)
                }
                #[doc = "Bit 7 - Position include position"]
                #[inline(always)]
                #[must_use]
                pub fn pos_en(&mut self) -> POS_EN_W<SMP_EN_SPEC> {
                    POS_EN_W::new(self, 7)
                }
                #[doc = "Bits 8:12 - Data register for revolution transfer"]
                #[inline(always)]
                #[must_use]
                pub fn rev_sel(&mut self) -> REV_SEL_W<SMP_EN_SPEC> {
                    REV_SEL_W::new(self, 8)
                }
                #[doc = "Bit 15 - Position include revolution"]
                #[inline(always)]
                #[must_use]
                pub fn rev_en(&mut self) -> REV_EN_W<SMP_EN_SPEC> {
                    REV_EN_W::new(self, 15)
                }
                #[doc = "Bits 16:20 - Data register for speed transfer"]
                #[inline(always)]
                #[must_use]
                pub fn spd_sel(&mut self) -> SPD_SEL_W<SMP_EN_SPEC> {
                    SPD_SEL_W::new(self, 16)
                }
                #[doc = "Bit 23 - Position include speed"]
                #[inline(always)]
                #[must_use]
                pub fn spd_en(&mut self) -> SPD_EN_W<SMP_EN_SPEC> {
                    SPD_EN_W::new(self, 23)
                }
                #[doc = "Bits 24:28 - Data register for acceleration transfer"]
                #[inline(always)]
                #[must_use]
                pub fn acc_sel(&mut self) -> ACC_SEL_W<SMP_EN_SPEC> {
                    ACC_SEL_W::new(self, 24)
                }
                #[doc = "Bit 31 - Position include acceleration"]
                #[inline(always)]
                #[must_use]
                pub fn acc_en(&mut self) -> ACC_EN_W<SMP_EN_SPEC> {
                    ACC_EN_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample selection register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_EN_SPEC;
            impl crate::RegisterSpec for SMP_EN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_en::R`](R) reader structure"]
            impl crate::Readable for SMP_EN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_en::W`](W) writer structure"]
            impl crate::Writable for SMP_EN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_EN to value 0"]
            impl crate::Resettable for SMP_EN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_CFG (rw) register accessor: Sample configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_cfg`]
module"]
        pub type SMP_CFG = crate::Reg<smp_cfg::SMP_CFG_SPEC>;
        #[doc = "Sample configuration"]
        pub mod smp_cfg {
            #[doc = "Register `SMP_CFG` reader"]
            pub type R = crate::R<SMP_CFG_SPEC>;
            #[doc = "Register `SMP_CFG` writer"]
            pub type W = crate::W<SMP_CFG_SPEC>;
            #[doc = "Field `WINDOW` reader - Sample window, in clock cycle"]
            pub type WINDOW_R = crate::FieldReader<u16>;
            #[doc = "Field `WINDOW` writer - Sample window, in clock cycle"]
            pub type WINDOW_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            #[doc = "Field `LAT_SEL` reader - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
            pub type LAT_SEL_R = crate::FieldReader;
            #[doc = "Field `LAT_SEL` writer - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
            pub type LAT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `ONCE` reader - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
            pub type ONCE_R = crate::BitReader;
            #[doc = "Field `ONCE` writer - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
            pub type ONCE_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:15 - Sample window, in clock cycle"]
                #[inline(always)]
                pub fn window(&self) -> WINDOW_R {
                    WINDOW_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bits 16:17 - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
                #[inline(always)]
                pub fn lat_sel(&self) -> LAT_SEL_R {
                    LAT_SEL_R::new(((self.bits >> 16) & 3) as u8)
                }
                #[doc = "Bit 24 - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
                #[inline(always)]
                pub fn once(&self) -> ONCE_R {
                    ONCE_R::new(((self.bits >> 24) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - Sample window, in clock cycle"]
                #[inline(always)]
                #[must_use]
                pub fn window(&mut self) -> WINDOW_W<SMP_CFG_SPEC> {
                    WINDOW_W::new(self, 0)
                }
                #[doc = "Bits 16:17 - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
                #[inline(always)]
                #[must_use]
                pub fn lat_sel(&mut self) -> LAT_SEL_W<SMP_CFG_SPEC> {
                    LAT_SEL_W::new(self, 16)
                }
                #[doc = "Bit 24 - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
                #[inline(always)]
                #[must_use]
                pub fn once(&mut self) -> ONCE_W<SMP_CFG_SPEC> {
                    ONCE_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_CFG_SPEC;
            impl crate::RegisterSpec for SMP_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_cfg::R`](R) reader structure"]
            impl crate::Readable for SMP_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_cfg::W`](W) writer structure"]
            impl crate::Writable for SMP_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_CFG to value 0"]
            impl crate::Resettable for SMP_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_DAT (rw) register accessor: Sample data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_dat::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_dat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_dat`]
module"]
        pub type SMP_DAT = crate::Reg<smp_dat::SMP_DAT_SPEC>;
        #[doc = "Sample data"]
        pub mod smp_dat {
            #[doc = "Register `SMP_DAT` reader"]
            pub type R = crate::R<SMP_DAT_SPEC>;
            #[doc = "Register `SMP_DAT` writer"]
            pub type W = crate::W<SMP_DAT_SPEC>;
            #[doc = "Field `DAT_SEL` reader - Data register sampled, each bit represent a data register"]
            pub type DAT_SEL_R = crate::FieldReader<u32>;
            #[doc = "Field `DAT_SEL` writer - Data register sampled, each bit represent a data register"]
            pub type DAT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Data register sampled, each bit represent a data register"]
                #[inline(always)]
                pub fn dat_sel(&self) -> DAT_SEL_R {
                    DAT_SEL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Data register sampled, each bit represent a data register"]
                #[inline(always)]
                #[must_use]
                pub fn dat_sel(&mut self) -> DAT_SEL_W<SMP_DAT_SPEC> {
                    DAT_SEL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_dat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_dat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_DAT_SPEC;
            impl crate::RegisterSpec for SMP_DAT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_dat::R`](R) reader structure"]
            impl crate::Readable for SMP_DAT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_dat::W`](W) writer structure"]
            impl crate::Writable for SMP_DAT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_DAT to value 0"]
            impl crate::Resettable for SMP_DAT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_POS (rw) register accessor: Sample override position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_pos`]
module"]
        pub type SMP_POS = crate::Reg<smp_pos::SMP_POS_SPEC>;
        #[doc = "Sample override position"]
        pub mod smp_pos {
            #[doc = "Register `SMP_POS` reader"]
            pub type R = crate::R<SMP_POS_SPEC>;
            #[doc = "Register `SMP_POS` writer"]
            pub type W = crate::W<SMP_POS_SPEC>;
            #[doc = "Field `POS` reader - Sample override position"]
            pub type POS_R = crate::FieldReader<u32>;
            #[doc = "Field `POS` writer - Sample override position"]
            pub type POS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Sample override position"]
                #[inline(always)]
                pub fn pos(&self) -> POS_R {
                    POS_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Sample override position"]
                #[inline(always)]
                #[must_use]
                pub fn pos(&mut self) -> POS_W<SMP_POS_SPEC> {
                    POS_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample override position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_POS_SPEC;
            impl crate::RegisterSpec for SMP_POS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_pos::R`](R) reader structure"]
            impl crate::Readable for SMP_POS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_pos::W`](W) writer structure"]
            impl crate::Writable for SMP_POS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_POS to value 0"]
            impl crate::Resettable for SMP_POS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_REV (rw) register accessor: Sample override revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_rev`]
module"]
        pub type SMP_REV = crate::Reg<smp_rev::SMP_REV_SPEC>;
        #[doc = "Sample override revolution"]
        pub mod smp_rev {
            #[doc = "Register `SMP_REV` reader"]
            pub type R = crate::R<SMP_REV_SPEC>;
            #[doc = "Register `SMP_REV` writer"]
            pub type W = crate::W<SMP_REV_SPEC>;
            #[doc = "Field `REV` reader - Sample override revolution"]
            pub type REV_R = crate::FieldReader<u32>;
            #[doc = "Field `REV` writer - Sample override revolution"]
            pub type REV_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Sample override revolution"]
                #[inline(always)]
                pub fn rev(&self) -> REV_R {
                    REV_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Sample override revolution"]
                #[inline(always)]
                #[must_use]
                pub fn rev(&mut self) -> REV_W<SMP_REV_SPEC> {
                    REV_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample override revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_REV_SPEC;
            impl crate::RegisterSpec for SMP_REV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_rev::R`](R) reader structure"]
            impl crate::Readable for SMP_REV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_rev::W`](W) writer structure"]
            impl crate::Writable for SMP_REV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_REV to value 0"]
            impl crate::Resettable for SMP_REV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_SPD (rw) register accessor: Sample override speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_spd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_spd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_spd`]
module"]
        pub type SMP_SPD = crate::Reg<smp_spd::SMP_SPD_SPEC>;
        #[doc = "Sample override speed"]
        pub mod smp_spd {
            #[doc = "Register `SMP_SPD` reader"]
            pub type R = crate::R<SMP_SPD_SPEC>;
            #[doc = "Register `SMP_SPD` writer"]
            pub type W = crate::W<SMP_SPD_SPEC>;
            #[doc = "Field `SPD` reader - Sample override speed"]
            pub type SPD_R = crate::FieldReader<u32>;
            #[doc = "Field `SPD` writer - Sample override speed"]
            pub type SPD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Sample override speed"]
                #[inline(always)]
                pub fn spd(&self) -> SPD_R {
                    SPD_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Sample override speed"]
                #[inline(always)]
                #[must_use]
                pub fn spd(&mut self) -> SPD_W<SMP_SPD_SPEC> {
                    SPD_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample override speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_spd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_spd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_SPD_SPEC;
            impl crate::RegisterSpec for SMP_SPD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_spd::R`](R) reader structure"]
            impl crate::Readable for SMP_SPD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_spd::W`](W) writer structure"]
            impl crate::Writable for SMP_SPD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_SPD to value 0"]
            impl crate::Resettable for SMP_SPD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_ACC (rw) register accessor: Sample override accelerate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_acc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_acc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_acc`]
module"]
        pub type SMP_ACC = crate::Reg<smp_acc::SMP_ACC_SPEC>;
        #[doc = "Sample override accelerate"]
        pub mod smp_acc {
            #[doc = "Register `SMP_ACC` reader"]
            pub type R = crate::R<SMP_ACC_SPEC>;
            #[doc = "Register `SMP_ACC` writer"]
            pub type W = crate::W<SMP_ACC_SPEC>;
            #[doc = "Field `ACC` reader - Sample override accelerate"]
            pub type ACC_R = crate::FieldReader<u32>;
            #[doc = "Field `ACC` writer - Sample override accelerate"]
            pub type ACC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Sample override accelerate"]
                #[inline(always)]
                pub fn acc(&self) -> ACC_R {
                    ACC_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Sample override accelerate"]
                #[inline(always)]
                #[must_use]
                pub fn acc(&mut self) -> ACC_W<SMP_ACC_SPEC> {
                    ACC_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample override accelerate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_acc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_acc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_ACC_SPEC;
            impl crate::RegisterSpec for SMP_ACC_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_acc::R`](R) reader structure"]
            impl crate::Readable for SMP_ACC_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_acc::W`](W) writer structure"]
            impl crate::Writable for SMP_ACC_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_ACC to value 0"]
            impl crate::Resettable for SMP_ACC_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_EN (rw) register accessor: Update configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_en`]
module"]
        pub type UPD_EN = crate::Reg<upd_en::UPD_EN_SPEC>;
        #[doc = "Update configuration"]
        pub mod upd_en {
            #[doc = "Register `UPD_EN` reader"]
            pub type R = crate::R<UPD_EN_SPEC>;
            #[doc = "Register `UPD_EN` writer"]
            pub type W = crate::W<UPD_EN_SPEC>;
            #[doc = "Field `POS_SEL` reader - Data register for position transfer"]
            pub type POS_SEL_R = crate::FieldReader;
            #[doc = "Field `POS_SEL` writer - Data register for position transfer"]
            pub type POS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `POS_EN` reader - Position include position"]
            pub type POS_EN_R = crate::BitReader;
            #[doc = "Field `POS_EN` writer - Position include position"]
            pub type POS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `REV_SEL` reader - Data register for revolution transfer"]
            pub type REV_SEL_R = crate::FieldReader;
            #[doc = "Field `REV_SEL` writer - Data register for revolution transfer"]
            pub type REV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `REV_EN` reader - Position include revolution"]
            pub type REV_EN_R = crate::BitReader;
            #[doc = "Field `REV_EN` writer - Position include revolution"]
            pub type REV_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SPD_SEL` reader - Data register for speed transfer"]
            pub type SPD_SEL_R = crate::FieldReader;
            #[doc = "Field `SPD_SEL` writer - Data register for speed transfer"]
            pub type SPD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `SPD_EN` reader - Position include speed"]
            pub type SPD_EN_R = crate::BitReader;
            #[doc = "Field `SPD_EN` writer - Position include speed"]
            pub type SPD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `ACC_SEL` reader - Data register for acceleration transfer"]
            pub type ACC_SEL_R = crate::FieldReader;
            #[doc = "Field `ACC_SEL` writer - Data register for acceleration transfer"]
            pub type ACC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `ACC_EN` reader - Position include acceleration"]
            pub type ACC_EN_R = crate::BitReader;
            #[doc = "Field `ACC_EN` writer - Position include acceleration"]
            pub type ACC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:4 - Data register for position transfer"]
                #[inline(always)]
                pub fn pos_sel(&self) -> POS_SEL_R {
                    POS_SEL_R::new((self.bits & 0x1f) as u8)
                }
                #[doc = "Bit 7 - Position include position"]
                #[inline(always)]
                pub fn pos_en(&self) -> POS_EN_R {
                    POS_EN_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bits 8:12 - Data register for revolution transfer"]
                #[inline(always)]
                pub fn rev_sel(&self) -> REV_SEL_R {
                    REV_SEL_R::new(((self.bits >> 8) & 0x1f) as u8)
                }
                #[doc = "Bit 15 - Position include revolution"]
                #[inline(always)]
                pub fn rev_en(&self) -> REV_EN_R {
                    REV_EN_R::new(((self.bits >> 15) & 1) != 0)
                }
                #[doc = "Bits 16:20 - Data register for speed transfer"]
                #[inline(always)]
                pub fn spd_sel(&self) -> SPD_SEL_R {
                    SPD_SEL_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bit 23 - Position include speed"]
                #[inline(always)]
                pub fn spd_en(&self) -> SPD_EN_R {
                    SPD_EN_R::new(((self.bits >> 23) & 1) != 0)
                }
                #[doc = "Bits 24:28 - Data register for acceleration transfer"]
                #[inline(always)]
                pub fn acc_sel(&self) -> ACC_SEL_R {
                    ACC_SEL_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
                #[doc = "Bit 31 - Position include acceleration"]
                #[inline(always)]
                pub fn acc_en(&self) -> ACC_EN_R {
                    ACC_EN_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:4 - Data register for position transfer"]
                #[inline(always)]
                #[must_use]
                pub fn pos_sel(&mut self) -> POS_SEL_W<UPD_EN_SPEC> {
                    POS_SEL_W::new(self, 0)
                }
                #[doc = "Bit 7 - Position include position"]
                #[inline(always)]
                #[must_use]
                pub fn pos_en(&mut self) -> POS_EN_W<UPD_EN_SPEC> {
                    POS_EN_W::new(self, 7)
                }
                #[doc = "Bits 8:12 - Data register for revolution transfer"]
                #[inline(always)]
                #[must_use]
                pub fn rev_sel(&mut self) -> REV_SEL_W<UPD_EN_SPEC> {
                    REV_SEL_W::new(self, 8)
                }
                #[doc = "Bit 15 - Position include revolution"]
                #[inline(always)]
                #[must_use]
                pub fn rev_en(&mut self) -> REV_EN_W<UPD_EN_SPEC> {
                    REV_EN_W::new(self, 15)
                }
                #[doc = "Bits 16:20 - Data register for speed transfer"]
                #[inline(always)]
                #[must_use]
                pub fn spd_sel(&mut self) -> SPD_SEL_W<UPD_EN_SPEC> {
                    SPD_SEL_W::new(self, 16)
                }
                #[doc = "Bit 23 - Position include speed"]
                #[inline(always)]
                #[must_use]
                pub fn spd_en(&mut self) -> SPD_EN_W<UPD_EN_SPEC> {
                    SPD_EN_W::new(self, 23)
                }
                #[doc = "Bits 24:28 - Data register for acceleration transfer"]
                #[inline(always)]
                #[must_use]
                pub fn acc_sel(&mut self) -> ACC_SEL_W<UPD_EN_SPEC> {
                    ACC_SEL_W::new(self, 24)
                }
                #[doc = "Bit 31 - Position include acceleration"]
                #[inline(always)]
                #[must_use]
                pub fn acc_en(&mut self) -> ACC_EN_W<UPD_EN_SPEC> {
                    ACC_EN_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_EN_SPEC;
            impl crate::RegisterSpec for UPD_EN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_en::R`](R) reader structure"]
            impl crate::Readable for UPD_EN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_en::W`](W) writer structure"]
            impl crate::Writable for UPD_EN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_EN to value 0"]
            impl crate::Resettable for UPD_EN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_CFG (rw) register accessor: Update configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_cfg`]
module"]
        pub type UPD_CFG = crate::Reg<upd_cfg::UPD_CFG_SPEC>;
        #[doc = "Update configuration"]
        pub mod upd_cfg {
            #[doc = "Register `UPD_CFG` reader"]
            pub type R = crate::R<UPD_CFG_SPEC>;
            #[doc = "Register `UPD_CFG` writer"]
            pub type W = crate::W<UPD_CFG_SPEC>;
            #[doc = "Field `LAT_SEL` reader - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
            pub type LAT_SEL_R = crate::FieldReader;
            #[doc = "Field `LAT_SEL` writer - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
            pub type LAT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `ONERR` reader - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
            pub type ONERR_R = crate::BitReader;
            #[doc = "Field `ONERR` writer - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
            pub type ONERR_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TIME_OVRD` reader - Use override time 0: use time sample from motor group 1: use override time"]
            pub type TIME_OVRD_R = crate::BitReader;
            #[doc = "Field `TIME_OVRD` writer - Use override time 0: use time sample from motor group 1: use override time"]
            pub type TIME_OVRD_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 16:17 - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
                #[inline(always)]
                pub fn lat_sel(&self) -> LAT_SEL_R {
                    LAT_SEL_R::new(((self.bits >> 16) & 3) as u8)
                }
                #[doc = "Bit 24 - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
                #[inline(always)]
                pub fn onerr(&self) -> ONERR_R {
                    ONERR_R::new(((self.bits >> 24) & 1) != 0)
                }
                #[doc = "Bit 31 - Use override time 0: use time sample from motor group 1: use override time"]
                #[inline(always)]
                pub fn time_ovrd(&self) -> TIME_OVRD_R {
                    TIME_OVRD_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 16:17 - Latch selection 0: latch 0 1: latch 1 2: latch 2 3: latch 3"]
                #[inline(always)]
                #[must_use]
                pub fn lat_sel(&mut self) -> LAT_SEL_W<UPD_CFG_SPEC> {
                    LAT_SEL_W::new(self, 16)
                }
                #[doc = "Bit 24 - Sample one time 0: Sample during windows time 1: Close sample window after first sample"]
                #[inline(always)]
                #[must_use]
                pub fn onerr(&mut self) -> ONERR_W<UPD_CFG_SPEC> {
                    ONERR_W::new(self, 24)
                }
                #[doc = "Bit 31 - Use override time 0: use time sample from motor group 1: use override time"]
                #[inline(always)]
                #[must_use]
                pub fn time_ovrd(&mut self) -> TIME_OVRD_W<UPD_CFG_SPEC> {
                    TIME_OVRD_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_CFG_SPEC;
            impl crate::RegisterSpec for UPD_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_cfg::R`](R) reader structure"]
            impl crate::Readable for UPD_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_cfg::W`](W) writer structure"]
            impl crate::Writable for UPD_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_CFG to value 0"]
            impl crate::Resettable for UPD_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_DAT (rw) register accessor: Update data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_dat::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_dat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_dat`]
module"]
        pub type UPD_DAT = crate::Reg<upd_dat::UPD_DAT_SPEC>;
        #[doc = "Update data"]
        pub mod upd_dat {
            #[doc = "Register `UPD_DAT` reader"]
            pub type R = crate::R<UPD_DAT_SPEC>;
            #[doc = "Register `UPD_DAT` writer"]
            pub type W = crate::W<UPD_DAT_SPEC>;
            #[doc = "Field `DAT_SEL` reader - Data register sampled, each bit represent a data register"]
            pub type DAT_SEL_R = crate::FieldReader<u32>;
            #[doc = "Field `DAT_SEL` writer - Data register sampled, each bit represent a data register"]
            pub type DAT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Data register sampled, each bit represent a data register"]
                #[inline(always)]
                pub fn dat_sel(&self) -> DAT_SEL_R {
                    DAT_SEL_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Data register sampled, each bit represent a data register"]
                #[inline(always)]
                #[must_use]
                pub fn dat_sel(&mut self) -> DAT_SEL_W<UPD_DAT_SPEC> {
                    DAT_SEL_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_dat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_dat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_DAT_SPEC;
            impl crate::RegisterSpec for UPD_DAT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_dat::R`](R) reader structure"]
            impl crate::Readable for UPD_DAT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_dat::W`](W) writer structure"]
            impl crate::Writable for UPD_DAT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_DAT to value 0"]
            impl crate::Resettable for UPD_DAT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_TIME (rw) register accessor: Update overide time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_time`]
module"]
        pub type UPD_TIME = crate::Reg<upd_time::UPD_TIME_SPEC>;
        #[doc = "Update overide time"]
        pub mod upd_time {
            #[doc = "Register `UPD_TIME` reader"]
            pub type R = crate::R<UPD_TIME_SPEC>;
            #[doc = "Register `UPD_TIME` writer"]
            pub type W = crate::W<UPD_TIME_SPEC>;
            #[doc = "Field `TIME` reader - Update override time"]
            pub type TIME_R = crate::FieldReader<u32>;
            #[doc = "Field `TIME` writer - Update override time"]
            pub type TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Update override time"]
                #[inline(always)]
                pub fn time(&self) -> TIME_R {
                    TIME_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Update override time"]
                #[inline(always)]
                #[must_use]
                pub fn time(&mut self) -> TIME_W<UPD_TIME_SPEC> {
                    TIME_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update overide time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_TIME_SPEC;
            impl crate::RegisterSpec for UPD_TIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_time::R`](R) reader structure"]
            impl crate::Readable for UPD_TIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_time::W`](W) writer structure"]
            impl crate::Writable for UPD_TIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_TIME to value 0"]
            impl crate::Resettable for UPD_TIME_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_POS (rw) register accessor: Update override position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_pos::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_pos::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_pos`]
module"]
        pub type UPD_POS = crate::Reg<upd_pos::UPD_POS_SPEC>;
        #[doc = "Update override position"]
        pub mod upd_pos {
            #[doc = "Register `UPD_POS` reader"]
            pub type R = crate::R<UPD_POS_SPEC>;
            #[doc = "Register `UPD_POS` writer"]
            pub type W = crate::W<UPD_POS_SPEC>;
            #[doc = "Field `POS` reader - Update override position"]
            pub type POS_R = crate::FieldReader<u32>;
            #[doc = "Field `POS` writer - Update override position"]
            pub type POS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Update override position"]
                #[inline(always)]
                pub fn pos(&self) -> POS_R {
                    POS_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Update override position"]
                #[inline(always)]
                #[must_use]
                pub fn pos(&mut self) -> POS_W<UPD_POS_SPEC> {
                    POS_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update override position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_pos::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_pos::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_POS_SPEC;
            impl crate::RegisterSpec for UPD_POS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_pos::R`](R) reader structure"]
            impl crate::Readable for UPD_POS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_pos::W`](W) writer structure"]
            impl crate::Writable for UPD_POS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_POS to value 0"]
            impl crate::Resettable for UPD_POS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_REV (rw) register accessor: Update override revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_rev::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_rev::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_rev`]
module"]
        pub type UPD_REV = crate::Reg<upd_rev::UPD_REV_SPEC>;
        #[doc = "Update override revolution"]
        pub mod upd_rev {
            #[doc = "Register `UPD_REV` reader"]
            pub type R = crate::R<UPD_REV_SPEC>;
            #[doc = "Register `UPD_REV` writer"]
            pub type W = crate::W<UPD_REV_SPEC>;
            #[doc = "Field `REV` reader - Update override revolution"]
            pub type REV_R = crate::FieldReader<u32>;
            #[doc = "Field `REV` writer - Update override revolution"]
            pub type REV_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Update override revolution"]
                #[inline(always)]
                pub fn rev(&self) -> REV_R {
                    REV_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Update override revolution"]
                #[inline(always)]
                #[must_use]
                pub fn rev(&mut self) -> REV_W<UPD_REV_SPEC> {
                    REV_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update override revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_rev::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_rev::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_REV_SPEC;
            impl crate::RegisterSpec for UPD_REV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_rev::R`](R) reader structure"]
            impl crate::Readable for UPD_REV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_rev::W`](W) writer structure"]
            impl crate::Writable for UPD_REV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_REV to value 0"]
            impl crate::Resettable for UPD_REV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_SPD (rw) register accessor: Update override speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_spd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_spd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_spd`]
module"]
        pub type UPD_SPD = crate::Reg<upd_spd::UPD_SPD_SPEC>;
        #[doc = "Update override speed"]
        pub mod upd_spd {
            #[doc = "Register `UPD_SPD` reader"]
            pub type R = crate::R<UPD_SPD_SPEC>;
            #[doc = "Register `UPD_SPD` writer"]
            pub type W = crate::W<UPD_SPD_SPEC>;
            #[doc = "Field `SPD` reader - Update override speed"]
            pub type SPD_R = crate::FieldReader<u32>;
            #[doc = "Field `SPD` writer - Update override speed"]
            pub type SPD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Update override speed"]
                #[inline(always)]
                pub fn spd(&self) -> SPD_R {
                    SPD_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Update override speed"]
                #[inline(always)]
                #[must_use]
                pub fn spd(&mut self) -> SPD_W<UPD_SPD_SPEC> {
                    SPD_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update override speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_spd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_spd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_SPD_SPEC;
            impl crate::RegisterSpec for UPD_SPD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_spd::R`](R) reader structure"]
            impl crate::Readable for UPD_SPD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_spd::W`](W) writer structure"]
            impl crate::Writable for UPD_SPD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_SPD to value 0"]
            impl crate::Resettable for UPD_SPD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_ACC (rw) register accessor: Update override accelerate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_acc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_acc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_acc`]
module"]
        pub type UPD_ACC = crate::Reg<upd_acc::UPD_ACC_SPEC>;
        #[doc = "Update override accelerate"]
        pub mod upd_acc {
            #[doc = "Register `UPD_ACC` reader"]
            pub type R = crate::R<UPD_ACC_SPEC>;
            #[doc = "Register `UPD_ACC` writer"]
            pub type W = crate::W<UPD_ACC_SPEC>;
            #[doc = "Field `ACC` reader - Update override accelerate"]
            pub type ACC_R = crate::FieldReader<u32>;
            #[doc = "Field `ACC` writer - Update override accelerate"]
            pub type ACC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Update override accelerate"]
                #[inline(always)]
                pub fn acc(&self) -> ACC_R {
                    ACC_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Update override accelerate"]
                #[inline(always)]
                #[must_use]
                pub fn acc(&mut self) -> ACC_W<UPD_ACC_SPEC> {
                    ACC_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update override accelerate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_acc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_acc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_ACC_SPEC;
            impl crate::RegisterSpec for UPD_ACC_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_acc::R`](R) reader structure"]
            impl crate::Readable for UPD_ACC_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_acc::W`](W) writer structure"]
            impl crate::Writable for UPD_ACC_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_ACC to value 0"]
            impl crate::Resettable for UPD_ACC_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_VAL (rw) register accessor: Sample valid\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_val::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_val::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_val`]
module"]
        pub type SMP_VAL = crate::Reg<smp_val::SMP_VAL_SPEC>;
        #[doc = "Sample valid"]
        pub mod smp_val {
            #[doc = "Register `SMP_VAL` reader"]
            pub type R = crate::R<SMP_VAL_SPEC>;
            #[doc = "Register `SMP_VAL` writer"]
            pub type W = crate::W<SMP_VAL_SPEC>;
            #[doc = "Field `POS` reader - Position include position"]
            pub type POS_R = crate::BitReader;
            #[doc = "Field `REV` reader - Position include revolution"]
            pub type REV_R = crate::BitReader;
            #[doc = "Field `SPD` reader - Position include speed"]
            pub type SPD_R = crate::BitReader;
            #[doc = "Field `ACC` reader - Position include acceleration"]
            pub type ACC_R = crate::BitReader;
            impl R {
                #[doc = "Bit 7 - Position include position"]
                #[inline(always)]
                pub fn pos(&self) -> POS_R {
                    POS_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bit 15 - Position include revolution"]
                #[inline(always)]
                pub fn rev(&self) -> REV_R {
                    REV_R::new(((self.bits >> 15) & 1) != 0)
                }
                #[doc = "Bit 23 - Position include speed"]
                #[inline(always)]
                pub fn spd(&self) -> SPD_R {
                    SPD_R::new(((self.bits >> 23) & 1) != 0)
                }
                #[doc = "Bit 31 - Position include acceleration"]
                #[inline(always)]
                pub fn acc(&self) -> ACC_R {
                    ACC_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample valid\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_val::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_val::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_VAL_SPEC;
            impl crate::RegisterSpec for SMP_VAL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_val::R`](R) reader structure"]
            impl crate::Readable for SMP_VAL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_val::W`](W) writer structure"]
            impl crate::Writable for SMP_VAL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_VAL to value 0"]
            impl crate::Resettable for SMP_VAL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SMP_STS (rw) register accessor: Sample status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smp_sts`]
module"]
        pub type SMP_STS = crate::Reg<smp_sts::SMP_STS_SPEC>;
        #[doc = "Sample status"]
        pub mod smp_sts {
            #[doc = "Register `SMP_STS` reader"]
            pub type R = crate::R<SMP_STS_SPEC>;
            #[doc = "Register `SMP_STS` writer"]
            pub type W = crate::W<SMP_STS_SPEC>;
            #[doc = "Field `WIN_CNT` reader - Sample window counter"]
            pub type WIN_CNT_R = crate::FieldReader<u16>;
            #[doc = "Field `OCCUR` reader - Sample occured 0: Sample not happened 1: Sample occured"]
            pub type OCCUR_R = crate::BitReader;
            impl R {
                #[doc = "Bits 0:15 - Sample window counter"]
                #[inline(always)]
                pub fn win_cnt(&self) -> WIN_CNT_R {
                    WIN_CNT_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bit 24 - Sample occured 0: Sample not happened 1: Sample occured"]
                #[inline(always)]
                pub fn occur(&self) -> OCCUR_R {
                    OCCUR_R::new(((self.bits >> 24) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Sample status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smp_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smp_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SMP_STS_SPEC;
            impl crate::RegisterSpec for SMP_STS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`smp_sts::R`](R) reader structure"]
            impl crate::Readable for SMP_STS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`smp_sts::W`](W) writer structure"]
            impl crate::Writable for SMP_STS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SMP_STS to value 0"]
            impl crate::Resettable for SMP_STS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TIME_IN (rw) register accessor: input time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_in::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@time_in`]
module"]
        pub type TIME_IN = crate::Reg<time_in::TIME_IN_SPEC>;
        #[doc = "input time"]
        pub mod time_in {
            #[doc = "Register `TIME_IN` reader"]
            pub type R = crate::R<TIME_IN_SPEC>;
            #[doc = "Register `TIME_IN` writer"]
            pub type W = crate::W<TIME_IN_SPEC>;
            #[doc = "Field `TIME` reader - input time"]
            pub type TIME_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - input time"]
                #[inline(always)]
                pub fn time(&self) -> TIME_R {
                    TIME_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "input time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`time_in::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`time_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TIME_IN_SPEC;
            impl crate::RegisterSpec for TIME_IN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`time_in::R`](R) reader structure"]
            impl crate::Readable for TIME_IN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`time_in::W`](W) writer structure"]
            impl crate::Writable for TIME_IN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TIME_IN to value 0"]
            impl crate::Resettable for TIME_IN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "POS_IN (rw) register accessor: Input position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_in::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_in`]
module"]
        pub type POS_IN = crate::Reg<pos_in::POS_IN_SPEC>;
        #[doc = "Input position"]
        pub mod pos_in {
            #[doc = "Register `POS_IN` reader"]
            pub type R = crate::R<POS_IN_SPEC>;
            #[doc = "Register `POS_IN` writer"]
            pub type W = crate::W<POS_IN_SPEC>;
            #[doc = "Field `POS` reader - Input position"]
            pub type POS_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Input position"]
                #[inline(always)]
                pub fn pos(&self) -> POS_R {
                    POS_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Input position\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_in::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct POS_IN_SPEC;
            impl crate::RegisterSpec for POS_IN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pos_in::R`](R) reader structure"]
            impl crate::Readable for POS_IN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pos_in::W`](W) writer structure"]
            impl crate::Writable for POS_IN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets POS_IN to value 0"]
            impl crate::Resettable for POS_IN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "REV_IN (rw) register accessor: Input revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rev_in::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rev_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rev_in`]
module"]
        pub type REV_IN = crate::Reg<rev_in::REV_IN_SPEC>;
        #[doc = "Input revolution"]
        pub mod rev_in {
            #[doc = "Register `REV_IN` reader"]
            pub type R = crate::R<REV_IN_SPEC>;
            #[doc = "Register `REV_IN` writer"]
            pub type W = crate::W<REV_IN_SPEC>;
            #[doc = "Field `REV` reader - Input revolution"]
            pub type REV_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Input revolution"]
                #[inline(always)]
                pub fn rev(&self) -> REV_R {
                    REV_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Input revolution\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rev_in::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rev_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct REV_IN_SPEC;
            impl crate::RegisterSpec for REV_IN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`rev_in::R`](R) reader structure"]
            impl crate::Readable for REV_IN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`rev_in::W`](W) writer structure"]
            impl crate::Writable for REV_IN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets REV_IN to value 0"]
            impl crate::Resettable for REV_IN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SPD_IN (rw) register accessor: Input speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spd_in::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spd_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spd_in`]
module"]
        pub type SPD_IN = crate::Reg<spd_in::SPD_IN_SPEC>;
        #[doc = "Input speed"]
        pub mod spd_in {
            #[doc = "Register `SPD_IN` reader"]
            pub type R = crate::R<SPD_IN_SPEC>;
            #[doc = "Register `SPD_IN` writer"]
            pub type W = crate::W<SPD_IN_SPEC>;
            #[doc = "Field `SPD` reader - Input speed"]
            pub type SPD_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Input speed"]
                #[inline(always)]
                pub fn spd(&self) -> SPD_R {
                    SPD_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Input speed\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spd_in::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spd_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SPD_IN_SPEC;
            impl crate::RegisterSpec for SPD_IN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`spd_in::R`](R) reader structure"]
            impl crate::Readable for SPD_IN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`spd_in::W`](W) writer structure"]
            impl crate::Writable for SPD_IN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SPD_IN to value 0"]
            impl crate::Resettable for SPD_IN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "ACC_IN (rw) register accessor: Input accelerate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_in::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@acc_in`]
module"]
        pub type ACC_IN = crate::Reg<acc_in::ACC_IN_SPEC>;
        #[doc = "Input accelerate"]
        pub mod acc_in {
            #[doc = "Register `ACC_IN` reader"]
            pub type R = crate::R<ACC_IN_SPEC>;
            #[doc = "Register `ACC_IN` writer"]
            pub type W = crate::W<ACC_IN_SPEC>;
            #[doc = "Field `ACC` reader - Input accelerate"]
            pub type ACC_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Input accelerate"]
                #[inline(always)]
                pub fn acc(&self) -> ACC_R {
                    ACC_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Input accelerate\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`acc_in::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`acc_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct ACC_IN_SPEC;
            impl crate::RegisterSpec for ACC_IN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`acc_in::R`](R) reader structure"]
            impl crate::Readable for ACC_IN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`acc_in::W`](W) writer structure"]
            impl crate::Writable for ACC_IN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ACC_IN to value 0"]
            impl crate::Resettable for ACC_IN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "UPD_STS (rw) register accessor: Update status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@upd_sts`]
module"]
        pub type UPD_STS = crate::Reg<upd_sts::UPD_STS_SPEC>;
        #[doc = "Update status"]
        pub mod upd_sts {
            #[doc = "Register `UPD_STS` reader"]
            pub type R = crate::R<UPD_STS_SPEC>;
            #[doc = "Register `UPD_STS` writer"]
            pub type W = crate::W<UPD_STS_SPEC>;
            #[doc = "Field `UPD_ERR` reader - Update error 0: data receive normally 1: data receive error"]
            pub type UPD_ERR_R = crate::BitReader;
            impl R {
                #[doc = "Bit 24 - Update error 0: data receive normally 1: data receive error"]
                #[inline(always)]
                pub fn upd_err(&self) -> UPD_ERR_R {
                    UPD_ERR_R::new(((self.bits >> 24) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Update status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`upd_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`upd_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct UPD_STS_SPEC;
            impl crate::RegisterSpec for UPD_STS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`upd_sts::R`](R) reader structure"]
            impl crate::Readable for UPD_STS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`upd_sts::W`](W) writer structure"]
            impl crate::Writable for UPD_STS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets UPD_STS to value 0"]
            impl crate::Resettable for UPD_STS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "INT_EN (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_en`]
module"]
        pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
        #[doc = "Interrupt Enable"]
        pub mod int_en {
            #[doc = "Register `INT_EN` reader"]
            pub type R = crate::R<INT_EN_SPEC>;
            #[doc = "Register `INT_EN` writer"]
            pub type W = crate::W<INT_EN_SPEC>;
            #[doc = "Field `STALL` reader - Stall"]
            pub type STALL_R = crate::BitReader;
            #[doc = "Field `STALL` writer - Stall"]
            pub type STALL_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `EXECPT` reader - Exception"]
            pub type EXECPT_R = crate::BitReader;
            #[doc = "Field `EXECPT` writer - Exception"]
            pub type EXECPT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WDOG` reader - Watch dog"]
            pub type WDOG_R = crate::BitReader;
            #[doc = "Field `WDOG` writer - Watch dog"]
            pub type WDOG_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR0_ST` reader - Pointer 0 start"]
            pub type PTR0_ST_R = crate::BitReader;
            #[doc = "Field `PTR0_ST` writer - Pointer 0 start"]
            pub type PTR0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR1_ST` reader - Pointer 1 start"]
            pub type PTR1_ST_R = crate::BitReader;
            #[doc = "Field `PTR1_ST` writer - Pointer 1 start"]
            pub type PTR1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR0_ST` reader - Instruction 0 start"]
            pub type INSTR0_ST_R = crate::BitReader;
            #[doc = "Field `INSTR0_ST` writer - Instruction 0 start"]
            pub type INSTR0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR1_ST` reader - Instruction 1 start"]
            pub type INSTR1_ST_R = crate::BitReader;
            #[doc = "Field `INSTR1_ST` writer - Instruction 1 start"]
            pub type INSTR1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR0_END` reader - Pointer 0 end"]
            pub type PTR0_END_R = crate::BitReader;
            #[doc = "Field `PTR0_END` writer - Pointer 0 end"]
            pub type PTR0_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR1_END` reader - Pointer 1 end"]
            pub type PTR1_END_R = crate::BitReader;
            #[doc = "Field `PTR1_END` writer - Pointer 1 end"]
            pub type PTR1_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR0_END` reader - Instruction 0 end"]
            pub type INSTR0_END_R = crate::BitReader;
            #[doc = "Field `INSTR0_END` writer - Instruction 0 end"]
            pub type INSTR0_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR1_END` reader - Instruction 1 end"]
            pub type INSTR1_END_R = crate::BitReader;
            #[doc = "Field `INSTR1_END` writer - Instruction 1 end"]
            pub type INSTR1_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRX_ERR` reader - Transfer error"]
            pub type TRX_ERR_R = crate::BitReader;
            #[doc = "Field `TRX_ERR` writer - Transfer error"]
            pub type TRX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TIMEOUT` reader - Timeout"]
            pub type TIMEOUT_R = crate::BitReader;
            #[doc = "Field `TIMEOUT` writer - Timeout"]
            pub type TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH0` reader - Latch0"]
            pub type LATCH0_R = crate::BitReader;
            #[doc = "Field `LATCH0` writer - Latch0"]
            pub type LATCH0_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH1` reader - Latch1"]
            pub type LATCH1_R = crate::BitReader;
            #[doc = "Field `LATCH1` writer - Latch1"]
            pub type LATCH1_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH2` reader - Latch2"]
            pub type LATCH2_R = crate::BitReader;
            #[doc = "Field `LATCH2` writer - Latch2"]
            pub type LATCH2_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH3` reader - Latch3"]
            pub type LATCH3_R = crate::BitReader;
            #[doc = "Field `LATCH3` writer - Latch3"]
            pub type LATCH3_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SMP_ERR` reader - Sample error"]
            pub type SMP_ERR_R = crate::BitReader;
            #[doc = "Field `SMP_ERR` writer - Sample error"]
            pub type SMP_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER0` reader - Trigger0"]
            pub type TRIGER0_R = crate::BitReader;
            #[doc = "Field `TRIGER0` writer - Trigger0"]
            pub type TRIGER0_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER1` reader - Trigger1"]
            pub type TRIGER1_R = crate::BitReader;
            #[doc = "Field `TRIGER1` writer - Trigger1"]
            pub type TRIGER1_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER2` reader - Trigger2"]
            pub type TRIGER2_R = crate::BitReader;
            #[doc = "Field `TRIGER2` writer - Trigger2"]
            pub type TRIGER2_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER3` reader - Trigger3"]
            pub type TRIGER3_R = crate::BitReader;
            #[doc = "Field `TRIGER3` writer - Trigger3"]
            pub type TRIGER3_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR0` reader - Trigger0 failed"]
            pub type TRG_ERR0_R = crate::BitReader;
            #[doc = "Field `TRG_ERR0` writer - Trigger0 failed"]
            pub type TRG_ERR0_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR1` reader - Trigger1 failed"]
            pub type TRG_ERR1_R = crate::BitReader;
            #[doc = "Field `TRG_ERR1` writer - Trigger1 failed"]
            pub type TRG_ERR1_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR2` reader - Trigger2 failed"]
            pub type TRG_ERR2_R = crate::BitReader;
            #[doc = "Field `TRG_ERR2` writer - Trigger2 failed"]
            pub type TRG_ERR2_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR3` reader - Trigger3 failed"]
            pub type TRG_ERR3_R = crate::BitReader;
            #[doc = "Field `TRG_ERR3` writer - Trigger3 failed"]
            pub type TRG_ERR3_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Stall"]
                #[inline(always)]
                pub fn stall(&self) -> STALL_R {
                    STALL_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - Exception"]
                #[inline(always)]
                pub fn execpt(&self) -> EXECPT_R {
                    EXECPT_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 2 - Watch dog"]
                #[inline(always)]
                pub fn wdog(&self) -> WDOG_R {
                    WDOG_R::new(((self.bits >> 2) & 1) != 0)
                }
                #[doc = "Bit 4 - Pointer 0 start"]
                #[inline(always)]
                pub fn ptr0_st(&self) -> PTR0_ST_R {
                    PTR0_ST_R::new(((self.bits >> 4) & 1) != 0)
                }
                #[doc = "Bit 5 - Pointer 1 start"]
                #[inline(always)]
                pub fn ptr1_st(&self) -> PTR1_ST_R {
                    PTR1_ST_R::new(((self.bits >> 5) & 1) != 0)
                }
                #[doc = "Bit 6 - Instruction 0 start"]
                #[inline(always)]
                pub fn instr0_st(&self) -> INSTR0_ST_R {
                    INSTR0_ST_R::new(((self.bits >> 6) & 1) != 0)
                }
                #[doc = "Bit 7 - Instruction 1 start"]
                #[inline(always)]
                pub fn instr1_st(&self) -> INSTR1_ST_R {
                    INSTR1_ST_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bit 8 - Pointer 0 end"]
                #[inline(always)]
                pub fn ptr0_end(&self) -> PTR0_END_R {
                    PTR0_END_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - Pointer 1 end"]
                #[inline(always)]
                pub fn ptr1_end(&self) -> PTR1_END_R {
                    PTR1_END_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - Instruction 0 end"]
                #[inline(always)]
                pub fn instr0_end(&self) -> INSTR0_END_R {
                    INSTR0_END_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 11 - Instruction 1 end"]
                #[inline(always)]
                pub fn instr1_end(&self) -> INSTR1_END_R {
                    INSTR1_END_R::new(((self.bits >> 11) & 1) != 0)
                }
                #[doc = "Bit 12 - Transfer error"]
                #[inline(always)]
                pub fn trx_err(&self) -> TRX_ERR_R {
                    TRX_ERR_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bit 13 - Timeout"]
                #[inline(always)]
                pub fn timeout(&self) -> TIMEOUT_R {
                    TIMEOUT_R::new(((self.bits >> 13) & 1) != 0)
                }
                #[doc = "Bit 16 - Latch0"]
                #[inline(always)]
                pub fn latch0(&self) -> LATCH0_R {
                    LATCH0_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 17 - Latch1"]
                #[inline(always)]
                pub fn latch1(&self) -> LATCH1_R {
                    LATCH1_R::new(((self.bits >> 17) & 1) != 0)
                }
                #[doc = "Bit 18 - Latch2"]
                #[inline(always)]
                pub fn latch2(&self) -> LATCH2_R {
                    LATCH2_R::new(((self.bits >> 18) & 1) != 0)
                }
                #[doc = "Bit 19 - Latch3"]
                #[inline(always)]
                pub fn latch3(&self) -> LATCH3_R {
                    LATCH3_R::new(((self.bits >> 19) & 1) != 0)
                }
                #[doc = "Bit 20 - Sample error"]
                #[inline(always)]
                pub fn smp_err(&self) -> SMP_ERR_R {
                    SMP_ERR_R::new(((self.bits >> 20) & 1) != 0)
                }
                #[doc = "Bit 24 - Trigger0"]
                #[inline(always)]
                pub fn triger0(&self) -> TRIGER0_R {
                    TRIGER0_R::new(((self.bits >> 24) & 1) != 0)
                }
                #[doc = "Bit 25 - Trigger1"]
                #[inline(always)]
                pub fn triger1(&self) -> TRIGER1_R {
                    TRIGER1_R::new(((self.bits >> 25) & 1) != 0)
                }
                #[doc = "Bit 26 - Trigger2"]
                #[inline(always)]
                pub fn triger2(&self) -> TRIGER2_R {
                    TRIGER2_R::new(((self.bits >> 26) & 1) != 0)
                }
                #[doc = "Bit 27 - Trigger3"]
                #[inline(always)]
                pub fn triger3(&self) -> TRIGER3_R {
                    TRIGER3_R::new(((self.bits >> 27) & 1) != 0)
                }
                #[doc = "Bit 28 - Trigger0 failed"]
                #[inline(always)]
                pub fn trg_err0(&self) -> TRG_ERR0_R {
                    TRG_ERR0_R::new(((self.bits >> 28) & 1) != 0)
                }
                #[doc = "Bit 29 - Trigger1 failed"]
                #[inline(always)]
                pub fn trg_err1(&self) -> TRG_ERR1_R {
                    TRG_ERR1_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 30 - Trigger2 failed"]
                #[inline(always)]
                pub fn trg_err2(&self) -> TRG_ERR2_R {
                    TRG_ERR2_R::new(((self.bits >> 30) & 1) != 0)
                }
                #[doc = "Bit 31 - Trigger3 failed"]
                #[inline(always)]
                pub fn trg_err3(&self) -> TRG_ERR3_R {
                    TRG_ERR3_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Stall"]
                #[inline(always)]
                #[must_use]
                pub fn stall(&mut self) -> STALL_W<INT_EN_SPEC> {
                    STALL_W::new(self, 0)
                }
                #[doc = "Bit 1 - Exception"]
                #[inline(always)]
                #[must_use]
                pub fn execpt(&mut self) -> EXECPT_W<INT_EN_SPEC> {
                    EXECPT_W::new(self, 1)
                }
                #[doc = "Bit 2 - Watch dog"]
                #[inline(always)]
                #[must_use]
                pub fn wdog(&mut self) -> WDOG_W<INT_EN_SPEC> {
                    WDOG_W::new(self, 2)
                }
                #[doc = "Bit 4 - Pointer 0 start"]
                #[inline(always)]
                #[must_use]
                pub fn ptr0_st(&mut self) -> PTR0_ST_W<INT_EN_SPEC> {
                    PTR0_ST_W::new(self, 4)
                }
                #[doc = "Bit 5 - Pointer 1 start"]
                #[inline(always)]
                #[must_use]
                pub fn ptr1_st(&mut self) -> PTR1_ST_W<INT_EN_SPEC> {
                    PTR1_ST_W::new(self, 5)
                }
                #[doc = "Bit 6 - Instruction 0 start"]
                #[inline(always)]
                #[must_use]
                pub fn instr0_st(&mut self) -> INSTR0_ST_W<INT_EN_SPEC> {
                    INSTR0_ST_W::new(self, 6)
                }
                #[doc = "Bit 7 - Instruction 1 start"]
                #[inline(always)]
                #[must_use]
                pub fn instr1_st(&mut self) -> INSTR1_ST_W<INT_EN_SPEC> {
                    INSTR1_ST_W::new(self, 7)
                }
                #[doc = "Bit 8 - Pointer 0 end"]
                #[inline(always)]
                #[must_use]
                pub fn ptr0_end(&mut self) -> PTR0_END_W<INT_EN_SPEC> {
                    PTR0_END_W::new(self, 8)
                }
                #[doc = "Bit 9 - Pointer 1 end"]
                #[inline(always)]
                #[must_use]
                pub fn ptr1_end(&mut self) -> PTR1_END_W<INT_EN_SPEC> {
                    PTR1_END_W::new(self, 9)
                }
                #[doc = "Bit 10 - Instruction 0 end"]
                #[inline(always)]
                #[must_use]
                pub fn instr0_end(&mut self) -> INSTR0_END_W<INT_EN_SPEC> {
                    INSTR0_END_W::new(self, 10)
                }
                #[doc = "Bit 11 - Instruction 1 end"]
                #[inline(always)]
                #[must_use]
                pub fn instr1_end(&mut self) -> INSTR1_END_W<INT_EN_SPEC> {
                    INSTR1_END_W::new(self, 11)
                }
                #[doc = "Bit 12 - Transfer error"]
                #[inline(always)]
                #[must_use]
                pub fn trx_err(&mut self) -> TRX_ERR_W<INT_EN_SPEC> {
                    TRX_ERR_W::new(self, 12)
                }
                #[doc = "Bit 13 - Timeout"]
                #[inline(always)]
                #[must_use]
                pub fn timeout(&mut self) -> TIMEOUT_W<INT_EN_SPEC> {
                    TIMEOUT_W::new(self, 13)
                }
                #[doc = "Bit 16 - Latch0"]
                #[inline(always)]
                #[must_use]
                pub fn latch0(&mut self) -> LATCH0_W<INT_EN_SPEC> {
                    LATCH0_W::new(self, 16)
                }
                #[doc = "Bit 17 - Latch1"]
                #[inline(always)]
                #[must_use]
                pub fn latch1(&mut self) -> LATCH1_W<INT_EN_SPEC> {
                    LATCH1_W::new(self, 17)
                }
                #[doc = "Bit 18 - Latch2"]
                #[inline(always)]
                #[must_use]
                pub fn latch2(&mut self) -> LATCH2_W<INT_EN_SPEC> {
                    LATCH2_W::new(self, 18)
                }
                #[doc = "Bit 19 - Latch3"]
                #[inline(always)]
                #[must_use]
                pub fn latch3(&mut self) -> LATCH3_W<INT_EN_SPEC> {
                    LATCH3_W::new(self, 19)
                }
                #[doc = "Bit 20 - Sample error"]
                #[inline(always)]
                #[must_use]
                pub fn smp_err(&mut self) -> SMP_ERR_W<INT_EN_SPEC> {
                    SMP_ERR_W::new(self, 20)
                }
                #[doc = "Bit 24 - Trigger0"]
                #[inline(always)]
                #[must_use]
                pub fn triger0(&mut self) -> TRIGER0_W<INT_EN_SPEC> {
                    TRIGER0_W::new(self, 24)
                }
                #[doc = "Bit 25 - Trigger1"]
                #[inline(always)]
                #[must_use]
                pub fn triger1(&mut self) -> TRIGER1_W<INT_EN_SPEC> {
                    TRIGER1_W::new(self, 25)
                }
                #[doc = "Bit 26 - Trigger2"]
                #[inline(always)]
                #[must_use]
                pub fn triger2(&mut self) -> TRIGER2_W<INT_EN_SPEC> {
                    TRIGER2_W::new(self, 26)
                }
                #[doc = "Bit 27 - Trigger3"]
                #[inline(always)]
                #[must_use]
                pub fn triger3(&mut self) -> TRIGER3_W<INT_EN_SPEC> {
                    TRIGER3_W::new(self, 27)
                }
                #[doc = "Bit 28 - Trigger0 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err0(&mut self) -> TRG_ERR0_W<INT_EN_SPEC> {
                    TRG_ERR0_W::new(self, 28)
                }
                #[doc = "Bit 29 - Trigger1 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err1(&mut self) -> TRG_ERR1_W<INT_EN_SPEC> {
                    TRG_ERR1_W::new(self, 29)
                }
                #[doc = "Bit 30 - Trigger2 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err2(&mut self) -> TRG_ERR2_W<INT_EN_SPEC> {
                    TRG_ERR2_W::new(self, 30)
                }
                #[doc = "Bit 31 - Trigger3 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err3(&mut self) -> TRG_ERR3_W<INT_EN_SPEC> {
                    TRG_ERR3_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INT_EN_SPEC;
            impl crate::RegisterSpec for INT_EN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`int_en::R`](R) reader structure"]
            impl crate::Readable for INT_EN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`int_en::W`](W) writer structure"]
            impl crate::Writable for INT_EN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INT_EN to value 0"]
            impl crate::Resettable for INT_EN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "INT_FLAG (rw) register accessor: Interrupt flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_flag::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_flag::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_flag`]
module"]
        pub type INT_FLAG = crate::Reg<int_flag::INT_FLAG_SPEC>;
        #[doc = "Interrupt flag"]
        pub mod int_flag {
            #[doc = "Register `INT_FLAG` reader"]
            pub type R = crate::R<INT_FLAG_SPEC>;
            #[doc = "Register `INT_FLAG` writer"]
            pub type W = crate::W<INT_FLAG_SPEC>;
            #[doc = "Field `STALL` writer - Stall"]
            pub type STALL_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `EXECPT` writer - Exception"]
            pub type EXECPT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WDOG` writer - Watch dog"]
            pub type WDOG_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR0_ST` writer - Pointer 0 start"]
            pub type PTR0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR1_ST` writer - Pointer 1 start"]
            pub type PTR1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR0_ST` writer - Instruction 0 start"]
            pub type INSTR0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR1_ST` writer - Instruction 1 start"]
            pub type INSTR1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR0_END` writer - Pointer 0 end"]
            pub type PTR0_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PTR1_END` writer - Pointer 1 end"]
            pub type PTR1_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR0_END` writer - Instruction 0 end"]
            pub type INSTR0_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `INSTR1_END` writer - Instruction 1 end"]
            pub type INSTR1_END_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRX_ERR` writer - Transfer error"]
            pub type TRX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TIMEOUT` writer - Timeout"]
            pub type TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH0` writer - Latch0"]
            pub type LATCH0_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH1` writer - Latch1"]
            pub type LATCH1_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH2` writer - Latch2"]
            pub type LATCH2_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LATCH3` writer - Latch3"]
            pub type LATCH3_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SMP_ERR` writer - Sample error"]
            pub type SMP_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER0` writer - Trigger0"]
            pub type TRIGER0_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER1` writer - Trigger1"]
            pub type TRIGER1_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER2` writer - Trigger2"]
            pub type TRIGER2_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRIGER3` writer - Trigger3"]
            pub type TRIGER3_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR0` writer - Trigger0 failed"]
            pub type TRG_ERR0_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR1` writer - Trigger1 failed"]
            pub type TRG_ERR1_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR2` writer - Trigger2 failed"]
            pub type TRG_ERR2_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `TRG_ERR3` writer - Trigger3 failed"]
            pub type TRG_ERR3_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl W {
                #[doc = "Bit 0 - Stall"]
                #[inline(always)]
                #[must_use]
                pub fn stall(&mut self) -> STALL_W<INT_FLAG_SPEC> {
                    STALL_W::new(self, 0)
                }
                #[doc = "Bit 1 - Exception"]
                #[inline(always)]
                #[must_use]
                pub fn execpt(&mut self) -> EXECPT_W<INT_FLAG_SPEC> {
                    EXECPT_W::new(self, 1)
                }
                #[doc = "Bit 2 - Watch dog"]
                #[inline(always)]
                #[must_use]
                pub fn wdog(&mut self) -> WDOG_W<INT_FLAG_SPEC> {
                    WDOG_W::new(self, 2)
                }
                #[doc = "Bit 4 - Pointer 0 start"]
                #[inline(always)]
                #[must_use]
                pub fn ptr0_st(&mut self) -> PTR0_ST_W<INT_FLAG_SPEC> {
                    PTR0_ST_W::new(self, 4)
                }
                #[doc = "Bit 5 - Pointer 1 start"]
                #[inline(always)]
                #[must_use]
                pub fn ptr1_st(&mut self) -> PTR1_ST_W<INT_FLAG_SPEC> {
                    PTR1_ST_W::new(self, 5)
                }
                #[doc = "Bit 6 - Instruction 0 start"]
                #[inline(always)]
                #[must_use]
                pub fn instr0_st(&mut self) -> INSTR0_ST_W<INT_FLAG_SPEC> {
                    INSTR0_ST_W::new(self, 6)
                }
                #[doc = "Bit 7 - Instruction 1 start"]
                #[inline(always)]
                #[must_use]
                pub fn instr1_st(&mut self) -> INSTR1_ST_W<INT_FLAG_SPEC> {
                    INSTR1_ST_W::new(self, 7)
                }
                #[doc = "Bit 8 - Pointer 0 end"]
                #[inline(always)]
                #[must_use]
                pub fn ptr0_end(&mut self) -> PTR0_END_W<INT_FLAG_SPEC> {
                    PTR0_END_W::new(self, 8)
                }
                #[doc = "Bit 9 - Pointer 1 end"]
                #[inline(always)]
                #[must_use]
                pub fn ptr1_end(&mut self) -> PTR1_END_W<INT_FLAG_SPEC> {
                    PTR1_END_W::new(self, 9)
                }
                #[doc = "Bit 10 - Instruction 0 end"]
                #[inline(always)]
                #[must_use]
                pub fn instr0_end(&mut self) -> INSTR0_END_W<INT_FLAG_SPEC> {
                    INSTR0_END_W::new(self, 10)
                }
                #[doc = "Bit 11 - Instruction 1 end"]
                #[inline(always)]
                #[must_use]
                pub fn instr1_end(&mut self) -> INSTR1_END_W<INT_FLAG_SPEC> {
                    INSTR1_END_W::new(self, 11)
                }
                #[doc = "Bit 12 - Transfer error"]
                #[inline(always)]
                #[must_use]
                pub fn trx_err(&mut self) -> TRX_ERR_W<INT_FLAG_SPEC> {
                    TRX_ERR_W::new(self, 12)
                }
                #[doc = "Bit 13 - Timeout"]
                #[inline(always)]
                #[must_use]
                pub fn timeout(&mut self) -> TIMEOUT_W<INT_FLAG_SPEC> {
                    TIMEOUT_W::new(self, 13)
                }
                #[doc = "Bit 16 - Latch0"]
                #[inline(always)]
                #[must_use]
                pub fn latch0(&mut self) -> LATCH0_W<INT_FLAG_SPEC> {
                    LATCH0_W::new(self, 16)
                }
                #[doc = "Bit 17 - Latch1"]
                #[inline(always)]
                #[must_use]
                pub fn latch1(&mut self) -> LATCH1_W<INT_FLAG_SPEC> {
                    LATCH1_W::new(self, 17)
                }
                #[doc = "Bit 18 - Latch2"]
                #[inline(always)]
                #[must_use]
                pub fn latch2(&mut self) -> LATCH2_W<INT_FLAG_SPEC> {
                    LATCH2_W::new(self, 18)
                }
                #[doc = "Bit 19 - Latch3"]
                #[inline(always)]
                #[must_use]
                pub fn latch3(&mut self) -> LATCH3_W<INT_FLAG_SPEC> {
                    LATCH3_W::new(self, 19)
                }
                #[doc = "Bit 20 - Sample error"]
                #[inline(always)]
                #[must_use]
                pub fn smp_err(&mut self) -> SMP_ERR_W<INT_FLAG_SPEC> {
                    SMP_ERR_W::new(self, 20)
                }
                #[doc = "Bit 24 - Trigger0"]
                #[inline(always)]
                #[must_use]
                pub fn triger0(&mut self) -> TRIGER0_W<INT_FLAG_SPEC> {
                    TRIGER0_W::new(self, 24)
                }
                #[doc = "Bit 25 - Trigger1"]
                #[inline(always)]
                #[must_use]
                pub fn triger1(&mut self) -> TRIGER1_W<INT_FLAG_SPEC> {
                    TRIGER1_W::new(self, 25)
                }
                #[doc = "Bit 26 - Trigger2"]
                #[inline(always)]
                #[must_use]
                pub fn triger2(&mut self) -> TRIGER2_W<INT_FLAG_SPEC> {
                    TRIGER2_W::new(self, 26)
                }
                #[doc = "Bit 27 - Trigger3"]
                #[inline(always)]
                #[must_use]
                pub fn triger3(&mut self) -> TRIGER3_W<INT_FLAG_SPEC> {
                    TRIGER3_W::new(self, 27)
                }
                #[doc = "Bit 28 - Trigger0 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err0(&mut self) -> TRG_ERR0_W<INT_FLAG_SPEC> {
                    TRG_ERR0_W::new(self, 28)
                }
                #[doc = "Bit 29 - Trigger1 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err1(&mut self) -> TRG_ERR1_W<INT_FLAG_SPEC> {
                    TRG_ERR1_W::new(self, 29)
                }
                #[doc = "Bit 30 - Trigger2 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err2(&mut self) -> TRG_ERR2_W<INT_FLAG_SPEC> {
                    TRG_ERR2_W::new(self, 30)
                }
                #[doc = "Bit 31 - Trigger3 failed"]
                #[inline(always)]
                #[must_use]
                pub fn trg_err3(&mut self) -> TRG_ERR3_W<INT_FLAG_SPEC> {
                    TRG_ERR3_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Interrupt flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_flag::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_flag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INT_FLAG_SPEC;
            impl crate::RegisterSpec for INT_FLAG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`int_flag::R`](R) reader structure"]
            impl crate::Readable for INT_FLAG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`int_flag::W`](W) writer structure"]
            impl crate::Writable for INT_FLAG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INT_FLAG to value 0"]
            impl crate::Resettable for INT_FLAG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "INT_STS (rw) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_sts`]
module"]
        pub type INT_STS = crate::Reg<int_sts::INT_STS_SPEC>;
        #[doc = "Interrupt status"]
        pub mod int_sts {
            #[doc = "Register `INT_STS` reader"]
            pub type R = crate::R<INT_STS_SPEC>;
            #[doc = "Register `INT_STS` writer"]
            pub type W = crate::W<INT_STS_SPEC>;
            #[doc = "Field `STALL` reader - Stall"]
            pub type STALL_R = crate::BitReader;
            #[doc = "Field `EXECPT` reader - Exception"]
            pub type EXECPT_R = crate::BitReader;
            #[doc = "Field `WDOG` reader - Watch dog"]
            pub type WDOG_R = crate::BitReader;
            #[doc = "Field `PTR0_ST` reader - Pointer 0 start"]
            pub type PTR0_ST_R = crate::BitReader;
            #[doc = "Field `PTR1_ST` reader - Pointer 1 start"]
            pub type PTR1_ST_R = crate::BitReader;
            #[doc = "Field `INSTR0_ST` reader - Instruction 0 start"]
            pub type INSTR0_ST_R = crate::BitReader;
            #[doc = "Field `INSTR1_ST` reader - Instruction 1 start"]
            pub type INSTR1_ST_R = crate::BitReader;
            #[doc = "Field `PTR0_END` reader - Pointer 0 end"]
            pub type PTR0_END_R = crate::BitReader;
            #[doc = "Field `PTR1_END` reader - Pointer 1 end"]
            pub type PTR1_END_R = crate::BitReader;
            #[doc = "Field `INSTR0_END` reader - Instruction 0 end"]
            pub type INSTR0_END_R = crate::BitReader;
            #[doc = "Field `INSTR1_END` reader - Instruction 1 end"]
            pub type INSTR1_END_R = crate::BitReader;
            #[doc = "Field `TRX_ERR` reader - Transfer error"]
            pub type TRX_ERR_R = crate::BitReader;
            #[doc = "Field `TIMEOUT` reader - Timeout"]
            pub type TIMEOUT_R = crate::BitReader;
            #[doc = "Field `LATCH0` reader - Latch0"]
            pub type LATCH0_R = crate::BitReader;
            #[doc = "Field `LATCH1` reader - Latch1"]
            pub type LATCH1_R = crate::BitReader;
            #[doc = "Field `LATCH2` reader - Latch2"]
            pub type LATCH2_R = crate::BitReader;
            #[doc = "Field `LATCH3` reader - Latch3"]
            pub type LATCH3_R = crate::BitReader;
            #[doc = "Field `SMP_ERR` reader - Sample error"]
            pub type SMP_ERR_R = crate::BitReader;
            #[doc = "Field `TRIGER0` reader - Trigger0"]
            pub type TRIGER0_R = crate::BitReader;
            #[doc = "Field `TRIGER1` reader - Trigger1"]
            pub type TRIGER1_R = crate::BitReader;
            #[doc = "Field `TRIGER2` reader - Trigger2"]
            pub type TRIGER2_R = crate::BitReader;
            #[doc = "Field `TRIGER3` reader - Trigger3"]
            pub type TRIGER3_R = crate::BitReader;
            #[doc = "Field `TRG_ERR0` reader - Trigger0 failed"]
            pub type TRG_ERR0_R = crate::BitReader;
            #[doc = "Field `TRG_ERR1` reader - Trigger1 failed"]
            pub type TRG_ERR1_R = crate::BitReader;
            #[doc = "Field `TRG_ERR2` reader - Trigger2 failed"]
            pub type TRG_ERR2_R = crate::BitReader;
            #[doc = "Field `TRG_ERR3` reader - Trigger3 failed"]
            pub type TRG_ERR3_R = crate::BitReader;
            impl R {
                #[doc = "Bit 0 - Stall"]
                #[inline(always)]
                pub fn stall(&self) -> STALL_R {
                    STALL_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - Exception"]
                #[inline(always)]
                pub fn execpt(&self) -> EXECPT_R {
                    EXECPT_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bit 2 - Watch dog"]
                #[inline(always)]
                pub fn wdog(&self) -> WDOG_R {
                    WDOG_R::new(((self.bits >> 2) & 1) != 0)
                }
                #[doc = "Bit 4 - Pointer 0 start"]
                #[inline(always)]
                pub fn ptr0_st(&self) -> PTR0_ST_R {
                    PTR0_ST_R::new(((self.bits >> 4) & 1) != 0)
                }
                #[doc = "Bit 5 - Pointer 1 start"]
                #[inline(always)]
                pub fn ptr1_st(&self) -> PTR1_ST_R {
                    PTR1_ST_R::new(((self.bits >> 5) & 1) != 0)
                }
                #[doc = "Bit 6 - Instruction 0 start"]
                #[inline(always)]
                pub fn instr0_st(&self) -> INSTR0_ST_R {
                    INSTR0_ST_R::new(((self.bits >> 6) & 1) != 0)
                }
                #[doc = "Bit 7 - Instruction 1 start"]
                #[inline(always)]
                pub fn instr1_st(&self) -> INSTR1_ST_R {
                    INSTR1_ST_R::new(((self.bits >> 7) & 1) != 0)
                }
                #[doc = "Bit 8 - Pointer 0 end"]
                #[inline(always)]
                pub fn ptr0_end(&self) -> PTR0_END_R {
                    PTR0_END_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - Pointer 1 end"]
                #[inline(always)]
                pub fn ptr1_end(&self) -> PTR1_END_R {
                    PTR1_END_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - Instruction 0 end"]
                #[inline(always)]
                pub fn instr0_end(&self) -> INSTR0_END_R {
                    INSTR0_END_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 11 - Instruction 1 end"]
                #[inline(always)]
                pub fn instr1_end(&self) -> INSTR1_END_R {
                    INSTR1_END_R::new(((self.bits >> 11) & 1) != 0)
                }
                #[doc = "Bit 12 - Transfer error"]
                #[inline(always)]
                pub fn trx_err(&self) -> TRX_ERR_R {
                    TRX_ERR_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bit 13 - Timeout"]
                #[inline(always)]
                pub fn timeout(&self) -> TIMEOUT_R {
                    TIMEOUT_R::new(((self.bits >> 13) & 1) != 0)
                }
                #[doc = "Bit 16 - Latch0"]
                #[inline(always)]
                pub fn latch0(&self) -> LATCH0_R {
                    LATCH0_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 17 - Latch1"]
                #[inline(always)]
                pub fn latch1(&self) -> LATCH1_R {
                    LATCH1_R::new(((self.bits >> 17) & 1) != 0)
                }
                #[doc = "Bit 18 - Latch2"]
                #[inline(always)]
                pub fn latch2(&self) -> LATCH2_R {
                    LATCH2_R::new(((self.bits >> 18) & 1) != 0)
                }
                #[doc = "Bit 19 - Latch3"]
                #[inline(always)]
                pub fn latch3(&self) -> LATCH3_R {
                    LATCH3_R::new(((self.bits >> 19) & 1) != 0)
                }
                #[doc = "Bit 20 - Sample error"]
                #[inline(always)]
                pub fn smp_err(&self) -> SMP_ERR_R {
                    SMP_ERR_R::new(((self.bits >> 20) & 1) != 0)
                }
                #[doc = "Bit 24 - Trigger0"]
                #[inline(always)]
                pub fn triger0(&self) -> TRIGER0_R {
                    TRIGER0_R::new(((self.bits >> 24) & 1) != 0)
                }
                #[doc = "Bit 25 - Trigger1"]
                #[inline(always)]
                pub fn triger1(&self) -> TRIGER1_R {
                    TRIGER1_R::new(((self.bits >> 25) & 1) != 0)
                }
                #[doc = "Bit 26 - Trigger2"]
                #[inline(always)]
                pub fn triger2(&self) -> TRIGER2_R {
                    TRIGER2_R::new(((self.bits >> 26) & 1) != 0)
                }
                #[doc = "Bit 27 - Trigger3"]
                #[inline(always)]
                pub fn triger3(&self) -> TRIGER3_R {
                    TRIGER3_R::new(((self.bits >> 27) & 1) != 0)
                }
                #[doc = "Bit 28 - Trigger0 failed"]
                #[inline(always)]
                pub fn trg_err0(&self) -> TRG_ERR0_R {
                    TRG_ERR0_R::new(((self.bits >> 28) & 1) != 0)
                }
                #[doc = "Bit 29 - Trigger1 failed"]
                #[inline(always)]
                pub fn trg_err1(&self) -> TRG_ERR1_R {
                    TRG_ERR1_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 30 - Trigger2 failed"]
                #[inline(always)]
                pub fn trg_err2(&self) -> TRG_ERR2_R {
                    TRG_ERR2_R::new(((self.bits >> 30) & 1) != 0)
                }
                #[doc = "Bit 31 - Trigger3 failed"]
                #[inline(always)]
                pub fn trg_err3(&self) -> TRG_ERR3_R {
                    TRG_ERR3_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INT_STS_SPEC;
            impl crate::RegisterSpec for INT_STS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`int_sts::R`](R) reader structure"]
            impl crate::Readable for INT_STS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`int_sts::W`](W) writer structure"]
            impl crate::Writable for INT_STS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INT_STS to value 0"]
            impl crate::Resettable for INT_STS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "POINTER0 (rw) register accessor: Match pointer 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pointer0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pointer0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pointer0`]
module"]
        pub type POINTER0 = crate::Reg<pointer0::POINTER0_SPEC>;
        #[doc = "Match pointer 0"]
        pub mod pointer0 {
            #[doc = "Register `POINTER0` reader"]
            pub type R = crate::R<POINTER0_SPEC>;
            #[doc = "Register `POINTER0` writer"]
            pub type W = crate::W<POINTER0_SPEC>;
            #[doc = "Field `POINTER` reader - Match pointer 0"]
            pub type POINTER_R = crate::FieldReader;
            #[doc = "Field `POINTER` writer - Match pointer 0"]
            pub type POINTER_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bits 0:7 - Match pointer 0"]
                #[inline(always)]
                pub fn pointer(&self) -> POINTER_R {
                    POINTER_R::new((self.bits & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - Match pointer 0"]
                #[inline(always)]
                #[must_use]
                pub fn pointer(&mut self) -> POINTER_W<POINTER0_SPEC> {
                    POINTER_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Match pointer 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pointer0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pointer0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct POINTER0_SPEC;
            impl crate::RegisterSpec for POINTER0_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pointer0::R`](R) reader structure"]
            impl crate::Readable for POINTER0_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pointer0::W`](W) writer structure"]
            impl crate::Writable for POINTER0_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets POINTER0 to value 0"]
            impl crate::Resettable for POINTER0_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "POINTER1 (rw) register accessor: Match pointer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pointer1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pointer1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pointer1`]
module"]
        pub type POINTER1 = crate::Reg<pointer1::POINTER1_SPEC>;
        #[doc = "Match pointer 1"]
        pub mod pointer1 {
            #[doc = "Register `POINTER1` reader"]
            pub type R = crate::R<POINTER1_SPEC>;
            #[doc = "Register `POINTER1` writer"]
            pub type W = crate::W<POINTER1_SPEC>;
            #[doc = "Field `POINTER` reader - Match pointer 1"]
            pub type POINTER_R = crate::FieldReader;
            #[doc = "Field `POINTER` writer - Match pointer 1"]
            pub type POINTER_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bits 0:7 - Match pointer 1"]
                #[inline(always)]
                pub fn pointer(&self) -> POINTER_R {
                    POINTER_R::new((self.bits & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - Match pointer 1"]
                #[inline(always)]
                #[must_use]
                pub fn pointer(&mut self) -> POINTER_W<POINTER1_SPEC> {
                    POINTER_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Match pointer 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pointer1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pointer1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct POINTER1_SPEC;
            impl crate::RegisterSpec for POINTER1_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pointer1::R`](R) reader structure"]
            impl crate::Readable for POINTER1_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pointer1::W`](W) writer structure"]
            impl crate::Writable for POINTER1_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets POINTER1 to value 0"]
            impl crate::Resettable for POINTER1_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "INSTR0 (rw) register accessor: Match instruction 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`instr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@instr0`]
module"]
        pub type INSTR0 = crate::Reg<instr0::INSTR0_SPEC>;
        #[doc = "Match instruction 0"]
        pub mod instr0 {
            #[doc = "Register `INSTR0` reader"]
            pub type R = crate::R<INSTR0_SPEC>;
            #[doc = "Register `INSTR0` writer"]
            pub type W = crate::W<INSTR0_SPEC>;
            #[doc = "Field `INSTR` reader - Match instruction 0"]
            pub type INSTR_R = crate::FieldReader<u32>;
            #[doc = "Field `INSTR` writer - Match instruction 0"]
            pub type INSTR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Match instruction 0"]
                #[inline(always)]
                pub fn instr(&self) -> INSTR_R {
                    INSTR_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Match instruction 0"]
                #[inline(always)]
                #[must_use]
                pub fn instr(&mut self) -> INSTR_W<INSTR0_SPEC> {
                    INSTR_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Match instruction 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`instr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INSTR0_SPEC;
            impl crate::RegisterSpec for INSTR0_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`instr0::R`](R) reader structure"]
            impl crate::Readable for INSTR0_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`instr0::W`](W) writer structure"]
            impl crate::Writable for INSTR0_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INSTR0 to value 0"]
            impl crate::Resettable for INSTR0_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "INSTR1 (rw) register accessor: Match instruction 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`instr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@instr1`]
module"]
        pub type INSTR1 = crate::Reg<instr1::INSTR1_SPEC>;
        #[doc = "Match instruction 1"]
        pub mod instr1 {
            #[doc = "Register `INSTR1` reader"]
            pub type R = crate::R<INSTR1_SPEC>;
            #[doc = "Register `INSTR1` writer"]
            pub type W = crate::W<INSTR1_SPEC>;
            #[doc = "Field `INSTR` reader - Match instruction 1"]
            pub type INSTR_R = crate::FieldReader<u32>;
            #[doc = "Field `INSTR` writer - Match instruction 1"]
            pub type INSTR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Match instruction 1"]
                #[inline(always)]
                pub fn instr(&self) -> INSTR_R {
                    INSTR_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Match instruction 1"]
                #[inline(always)]
                #[must_use]
                pub fn instr(&mut self) -> INSTR_W<INSTR1_SPEC> {
                    INSTR_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Match instruction 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`instr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INSTR1_SPEC;
            impl crate::RegisterSpec for INSTR1_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`instr1::R`](R) reader structure"]
            impl crate::Readable for INSTR1_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`instr1::W`](W) writer structure"]
            impl crate::Writable for INSTR1_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INSTR1 to value 0"]
            impl crate::Resettable for INSTR1_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "INSTR (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`instr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@instr`]
module"]
    pub type INSTR = crate::Reg<instr::INSTR_SPEC>;
    #[doc = "no description available"]
    pub mod instr {
        #[doc = "Register `INSTR[%s]` reader"]
        pub type R = crate::R<INSTR_SPEC>;
        #[doc = "Register `INSTR[%s]` writer"]
        pub type W = crate::W<INSTR_SPEC>;
        #[doc = "Field `OPR` reader - 1\\]
When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. \\[2\\]
When OP is 1, this area is the the pointer to the command table. OPR\\[4\\]=1, OPR\\[3:0\\]
value is CMD_TABLE instruct pointer; OPR\\[4\\]=0, OPR\\[3:0\\]=0 is INIT_POINTER; OPR\\[4\\]=0, OPR\\[3:0\\]=1 is WDG_POINTER. \\[3\\]
When OP is 2-7, this area is the data length as fellow: 0: 1 bit 1: 2 bit ... 31: 32 bit"]
        pub type OPR_R = crate::FieldReader;
        #[doc = "Field `OPR` writer - 1\\]
When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. \\[2\\]
When OP is 1, this area is the the pointer to the command table. OPR\\[4\\]=1, OPR\\[3:0\\]
value is CMD_TABLE instruct pointer; OPR\\[4\\]=0, OPR\\[3:0\\]=0 is INIT_POINTER; OPR\\[4\\]=0, OPR\\[3:0\\]=1 is WDG_POINTER. \\[3\\]
When OP is 2-7, this area is the data length as fellow: 0: 1 bit 1: 2 bit ... 31: 32 bit"]
        pub type OPR_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `DAT` reader - DATA register 0: ignore data 1: command 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
        pub type DAT_R = crate::FieldReader;
        #[doc = "Field `DAT` writer - DATA register 0: ignore data 1: command 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
        pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `CRC` reader - CRC register 0: don't calculate CRC 1: do not set this value 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
        pub type CRC_R = crate::FieldReader;
        #[doc = "Field `CRC` writer - CRC register 0: don't calculate CRC 1: do not set this value 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
        pub type CRC_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `CK` reader - clock 0: low 1: rise-fall 2: fall-rise 3: high"]
        pub type CK_R = crate::FieldReader;
        #[doc = "Field `CK` writer - clock 0: low 1: rise-fall 2: fall-rise 3: high"]
        pub type CK_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `OP` reader - operation 0: halt 1: jump 2: send with timeout check 3: send without timout check 4: wait with timeout check 5: wait without timout check 6: receive with timeout check 7: receive without timout check"]
        pub type OP_R = crate::FieldReader;
        #[doc = "Field `OP` writer - operation 0: halt 1: jump 2: send with timeout check 3: send without timout check 4: wait with timeout check 5: wait without timout check 6: receive with timeout check 7: receive without timout check"]
        pub type OP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:4 - 1\\]
When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. \\[2\\]
When OP is 1, this area is the the pointer to the command table. OPR\\[4\\]=1, OPR\\[3:0\\]
value is CMD_TABLE instruct pointer; OPR\\[4\\]=0, OPR\\[3:0\\]=0 is INIT_POINTER; OPR\\[4\\]=0, OPR\\[3:0\\]=1 is WDG_POINTER. \\[3\\]
When OP is 2-7, this area is the data length as fellow: 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            #[inline(always)]
            pub fn opr(&self) -> OPR_R {
                OPR_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bits 8:12 - DATA register 0: ignore data 1: command 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
            #[inline(always)]
            pub fn dat(&self) -> DAT_R {
                DAT_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:20 - CRC register 0: don't calculate CRC 1: do not set this value 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
            #[inline(always)]
            pub fn crc(&self) -> CRC_R {
                CRC_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bits 24:25 - clock 0: low 1: rise-fall 2: fall-rise 3: high"]
            #[inline(always)]
            pub fn ck(&self) -> CK_R {
                CK_R::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bits 26:28 - operation 0: halt 1: jump 2: send with timeout check 3: send without timout check 4: wait with timeout check 5: wait without timout check 6: receive with timeout check 7: receive without timout check"]
            #[inline(always)]
            pub fn op(&self) -> OP_R {
                OP_R::new(((self.bits >> 26) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - 1\\]
When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. \\[2\\]
When OP is 1, this area is the the pointer to the command table. OPR\\[4\\]=1, OPR\\[3:0\\]
value is CMD_TABLE instruct pointer; OPR\\[4\\]=0, OPR\\[3:0\\]=0 is INIT_POINTER; OPR\\[4\\]=0, OPR\\[3:0\\]=1 is WDG_POINTER. \\[3\\]
When OP is 2-7, this area is the data length as fellow: 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            #[inline(always)]
            #[must_use]
            pub fn opr(&mut self) -> OPR_W<INSTR_SPEC> {
                OPR_W::new(self, 0)
            }
            #[doc = "Bits 8:12 - DATA register 0: ignore data 1: command 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
            #[inline(always)]
            #[must_use]
            pub fn dat(&mut self) -> DAT_W<INSTR_SPEC> {
                DAT_W::new(self, 8)
            }
            #[doc = "Bits 16:20 - CRC register 0: don't calculate CRC 1: do not set this value 2: data register 2 3: data register 3 ... 29: data register 29 30: value 0 when send, wait 0 in receive 31: value1 when send, wait 1 in receive"]
            #[inline(always)]
            #[must_use]
            pub fn crc(&mut self) -> CRC_W<INSTR_SPEC> {
                CRC_W::new(self, 16)
            }
            #[doc = "Bits 24:25 - clock 0: low 1: rise-fall 2: fall-rise 3: high"]
            #[inline(always)]
            #[must_use]
            pub fn ck(&mut self) -> CK_W<INSTR_SPEC> {
                CK_W::new(self, 24)
            }
            #[doc = "Bits 26:28 - operation 0: halt 1: jump 2: send with timeout check 3: send without timout check 4: wait with timeout check 5: wait without timout check 6: receive with timeout check 7: receive without timout check"]
            #[inline(always)]
            #[must_use]
            pub fn op(&mut self) -> OP_W<INSTR_SPEC> {
                OP_W::new(self, 26)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`instr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`instr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INSTR_SPEC;
        impl crate::RegisterSpec for INSTR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`instr::R`](R) reader structure"]
        impl crate::Readable for INSTR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`instr::W`](W) writer structure"]
        impl crate::Writable for INSTR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INSTR[%s]
to value 0"]
        impl crate::Resettable for INSTR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::dat::DAT;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod dat {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct DAT {
            mode: MODE,
            idx: IDX,
            gold: GOLD,
            crcinit: CRCINIT,
            crcpoly: CRCPOLY,
            _reserved5: [u8; 0x0c],
            data: DATA,
            set: SET,
            clr: CLR,
            inv: INV,
            in_: IN,
            out: OUT,
            sts: STS,
        }
        impl DAT {
            #[doc = "0x00 - No description avaiable"]
            #[inline(always)]
            pub const fn mode(&self) -> &MODE {
                &self.mode
            }
            #[doc = "0x04 - Data register bit index"]
            #[inline(always)]
            pub const fn idx(&self) -> &IDX {
                &self.idx
            }
            #[doc = "0x08 - Gold data for data check"]
            #[inline(always)]
            pub const fn gold(&self) -> &GOLD {
                &self.gold
            }
            #[doc = "0x0c - CRC calculation initial vector"]
            #[inline(always)]
            pub const fn crcinit(&self) -> &CRCINIT {
                &self.crcinit
            }
            #[doc = "0x10 - CRC calculation polynomial"]
            #[inline(always)]
            pub const fn crcpoly(&self) -> &CRCPOLY {
                &self.crcpoly
            }
            #[doc = "0x20 - Data value"]
            #[inline(always)]
            pub const fn data(&self) -> &DATA {
                &self.data
            }
            #[doc = "0x24 - Data bit set"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x28 - Data bit clear"]
            #[inline(always)]
            pub const fn clr(&self) -> &CLR {
                &self.clr
            }
            #[doc = "0x2c - Data bit invert"]
            #[inline(always)]
            pub const fn inv(&self) -> &INV {
                &self.inv
            }
            #[doc = "0x30 - Data input"]
            #[inline(always)]
            pub const fn in_(&self) -> &IN {
                &self.in_
            }
            #[doc = "0x34 - Data output"]
            #[inline(always)]
            pub const fn out(&self) -> &OUT {
                &self.out
            }
            #[doc = "0x38 - Data status"]
            #[inline(always)]
            pub const fn sts(&self) -> &STS {
                &self.sts
            }
        }
        #[doc = "MODE (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`]
module"]
        pub type MODE = crate::Reg<mode::MODE_SPEC>;
        #[doc = "No description avaiable"]
        pub mod mode {
            #[doc = "Register `MODE` reader"]
            pub type R = crate::R<MODE_SPEC>;
            #[doc = "Register `MODE` writer"]
            pub type W = crate::W<MODE_SPEC>;
            #[doc = "Field `MODE` reader - Data mode 0: data mode 1: check mode 2: CRC mode"]
            pub type MODE_R = crate::FieldReader;
            #[doc = "Field `MODE` writer - Data mode 0: data mode 1: check mode 2: CRC mode"]
            pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `REWIND` reader - Write 1 to rewind read/write pointer, this is a self clear bit"]
            pub type REWIND_R = crate::BitReader;
            #[doc = "Field `REWIND` writer - Write 1 to rewind read/write pointer, this is a self clear bit"]
            pub type REWIND_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SIGNED` reader - Signed 0: unsigned value 1: signed value"]
            pub type SIGNED_R = crate::BitReader;
            #[doc = "Field `SIGNED` writer - Signed 0: unsigned value 1: signed value"]
            pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `BORDER` reader - bit order 0: LSB first 1: MSB first"]
            pub type BORDER_R = crate::BitReader;
            #[doc = "Field `BORDER` writer - bit order 0: LSB first 1: MSB first"]
            pub type BORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WORDER` reader - word order 0: sample as bit order 1: different from bit order"]
            pub type WORDER_R = crate::BitReader;
            #[doc = "Field `WORDER` writer - word order 0: sample as bit order 1: different from bit order"]
            pub type WORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CRC_INV` reader - CRC invert 0: use CRC 1: use inverted CRC"]
            pub type CRC_INV_R = crate::BitReader;
            #[doc = "Field `CRC_INV` writer - CRC invert 0: use CRC 1: use inverted CRC"]
            pub type CRC_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CRC_SHIFT` reader - CRC shift mode, this mode is used to perform repeat code check 0: CRC 1: shift mode"]
            pub type CRC_SHIFT_R = crate::BitReader;
            #[doc = "Field `CRC_SHIFT` writer - CRC shift mode, this mode is used to perform repeat code check 0: CRC 1: shift mode"]
            pub type CRC_SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WLEN` reader - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type WLEN_R = crate::FieldReader;
            #[doc = "Field `WLEN` writer - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type WLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `CRC_LEN` reader - CRC length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type CRC_LEN_R = crate::FieldReader;
            #[doc = "Field `CRC_LEN` writer - CRC length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
            pub type CRC_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            impl R {
                #[doc = "Bits 0:1 - Data mode 0: data mode 1: check mode 2: CRC mode"]
                #[inline(always)]
                pub fn mode(&self) -> MODE_R {
                    MODE_R::new((self.bits & 3) as u8)
                }
                #[doc = "Bit 8 - Write 1 to rewind read/write pointer, this is a self clear bit"]
                #[inline(always)]
                pub fn rewind(&self) -> REWIND_R {
                    REWIND_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - Signed 0: unsigned value 1: signed value"]
                #[inline(always)]
                pub fn signed(&self) -> SIGNED_R {
                    SIGNED_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - bit order 0: LSB first 1: MSB first"]
                #[inline(always)]
                pub fn border(&self) -> BORDER_R {
                    BORDER_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 11 - word order 0: sample as bit order 1: different from bit order"]
                #[inline(always)]
                pub fn worder(&self) -> WORDER_R {
                    WORDER_R::new(((self.bits >> 11) & 1) != 0)
                }
                #[doc = "Bit 12 - CRC invert 0: use CRC 1: use inverted CRC"]
                #[inline(always)]
                pub fn crc_inv(&self) -> CRC_INV_R {
                    CRC_INV_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bit 13 - CRC shift mode, this mode is used to perform repeat code check 0: CRC 1: shift mode"]
                #[inline(always)]
                pub fn crc_shift(&self) -> CRC_SHIFT_R {
                    CRC_SHIFT_R::new(((self.bits >> 13) & 1) != 0)
                }
                #[doc = "Bits 16:20 - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                pub fn wlen(&self) -> WLEN_R {
                    WLEN_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - CRC length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                pub fn crc_len(&self) -> CRC_LEN_R {
                    CRC_LEN_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:1 - Data mode 0: data mode 1: check mode 2: CRC mode"]
                #[inline(always)]
                #[must_use]
                pub fn mode(&mut self) -> MODE_W<MODE_SPEC> {
                    MODE_W::new(self, 0)
                }
                #[doc = "Bit 8 - Write 1 to rewind read/write pointer, this is a self clear bit"]
                #[inline(always)]
                #[must_use]
                pub fn rewind(&mut self) -> REWIND_W<MODE_SPEC> {
                    REWIND_W::new(self, 8)
                }
                #[doc = "Bit 9 - Signed 0: unsigned value 1: signed value"]
                #[inline(always)]
                #[must_use]
                pub fn signed(&mut self) -> SIGNED_W<MODE_SPEC> {
                    SIGNED_W::new(self, 9)
                }
                #[doc = "Bit 10 - bit order 0: LSB first 1: MSB first"]
                #[inline(always)]
                #[must_use]
                pub fn border(&mut self) -> BORDER_W<MODE_SPEC> {
                    BORDER_W::new(self, 10)
                }
                #[doc = "Bit 11 - word order 0: sample as bit order 1: different from bit order"]
                #[inline(always)]
                #[must_use]
                pub fn worder(&mut self) -> WORDER_W<MODE_SPEC> {
                    WORDER_W::new(self, 11)
                }
                #[doc = "Bit 12 - CRC invert 0: use CRC 1: use inverted CRC"]
                #[inline(always)]
                #[must_use]
                pub fn crc_inv(&mut self) -> CRC_INV_W<MODE_SPEC> {
                    CRC_INV_W::new(self, 12)
                }
                #[doc = "Bit 13 - CRC shift mode, this mode is used to perform repeat code check 0: CRC 1: shift mode"]
                #[inline(always)]
                #[must_use]
                pub fn crc_shift(&mut self) -> CRC_SHIFT_W<MODE_SPEC> {
                    CRC_SHIFT_W::new(self, 13)
                }
                #[doc = "Bits 16:20 - word length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                #[must_use]
                pub fn wlen(&mut self) -> WLEN_W<MODE_SPEC> {
                    WLEN_W::new(self, 16)
                }
                #[doc = "Bits 24:28 - CRC length 0: 1 bit 1: 2 bit ... 31: 32 bit"]
                #[inline(always)]
                #[must_use]
                pub fn crc_len(&mut self) -> CRC_LEN_W<MODE_SPEC> {
                    CRC_LEN_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MODE_SPEC;
            impl crate::RegisterSpec for MODE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`mode::R`](R) reader structure"]
            impl crate::Readable for MODE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`mode::W`](W) writer structure"]
            impl crate::Writable for MODE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets MODE to value 0"]
            impl crate::Resettable for MODE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "IDX (rw) register accessor: Data register bit index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idx::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idx`]
module"]
        pub type IDX = crate::Reg<idx::IDX_SPEC>;
        #[doc = "Data register bit index"]
        pub mod idx {
            #[doc = "Register `IDX` reader"]
            pub type R = crate::R<IDX_SPEC>;
            #[doc = "Register `IDX` writer"]
            pub type W = crate::W<IDX_SPEC>;
            #[doc = "Field `MIN_BIT` reader - Lowest bit index"]
            pub type MIN_BIT_R = crate::FieldReader;
            #[doc = "Field `MIN_BIT` writer - Lowest bit index"]
            pub type MIN_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `MAX_BIT` reader - Highest bit index"]
            pub type MAX_BIT_R = crate::FieldReader;
            #[doc = "Field `MAX_BIT` writer - Highest bit index"]
            pub type MAX_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `FIRST_BIT` reader - First bit index for tranceive"]
            pub type FIRST_BIT_R = crate::FieldReader;
            #[doc = "Field `FIRST_BIT` writer - First bit index for tranceive"]
            pub type FIRST_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `LAST_BIT` reader - Last bit index for tranceive"]
            pub type LAST_BIT_R = crate::FieldReader;
            #[doc = "Field `LAST_BIT` writer - Last bit index for tranceive"]
            pub type LAST_BIT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            impl R {
                #[doc = "Bits 0:4 - Lowest bit index"]
                #[inline(always)]
                pub fn min_bit(&self) -> MIN_BIT_R {
                    MIN_BIT_R::new((self.bits & 0x1f) as u8)
                }
                #[doc = "Bits 8:12 - Highest bit index"]
                #[inline(always)]
                pub fn max_bit(&self) -> MAX_BIT_R {
                    MAX_BIT_R::new(((self.bits >> 8) & 0x1f) as u8)
                }
                #[doc = "Bits 16:20 - First bit index for tranceive"]
                #[inline(always)]
                pub fn first_bit(&self) -> FIRST_BIT_R {
                    FIRST_BIT_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - Last bit index for tranceive"]
                #[inline(always)]
                pub fn last_bit(&self) -> LAST_BIT_R {
                    LAST_BIT_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:4 - Lowest bit index"]
                #[inline(always)]
                #[must_use]
                pub fn min_bit(&mut self) -> MIN_BIT_W<IDX_SPEC> {
                    MIN_BIT_W::new(self, 0)
                }
                #[doc = "Bits 8:12 - Highest bit index"]
                #[inline(always)]
                #[must_use]
                pub fn max_bit(&mut self) -> MAX_BIT_W<IDX_SPEC> {
                    MAX_BIT_W::new(self, 8)
                }
                #[doc = "Bits 16:20 - First bit index for tranceive"]
                #[inline(always)]
                #[must_use]
                pub fn first_bit(&mut self) -> FIRST_BIT_W<IDX_SPEC> {
                    FIRST_BIT_W::new(self, 16)
                }
                #[doc = "Bits 24:28 - Last bit index for tranceive"]
                #[inline(always)]
                #[must_use]
                pub fn last_bit(&mut self) -> LAST_BIT_W<IDX_SPEC> {
                    LAST_BIT_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data register bit index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idx::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct IDX_SPEC;
            impl crate::RegisterSpec for IDX_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`idx::R`](R) reader structure"]
            impl crate::Readable for IDX_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`idx::W`](W) writer structure"]
            impl crate::Writable for IDX_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets IDX to value 0"]
            impl crate::Resettable for IDX_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "GOLD (rw) register accessor: Gold data for data check\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gold::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gold`]
module"]
        pub type GOLD = crate::Reg<gold::GOLD_SPEC>;
        #[doc = "Gold data for data check"]
        pub mod gold {
            #[doc = "Register `GOLD` reader"]
            pub type R = crate::R<GOLD_SPEC>;
            #[doc = "Register `GOLD` writer"]
            pub type W = crate::W<GOLD_SPEC>;
            #[doc = "Field `GOLD_VALUE` reader - Gold value for check mode"]
            pub type GOLD_VALUE_R = crate::FieldReader<u32>;
            #[doc = "Field `GOLD_VALUE` writer - Gold value for check mode"]
            pub type GOLD_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - Gold value for check mode"]
                #[inline(always)]
                pub fn gold_value(&self) -> GOLD_VALUE_R {
                    GOLD_VALUE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - Gold value for check mode"]
                #[inline(always)]
                #[must_use]
                pub fn gold_value(&mut self) -> GOLD_VALUE_W<GOLD_SPEC> {
                    GOLD_VALUE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Gold data for data check\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gold::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct GOLD_SPEC;
            impl crate::RegisterSpec for GOLD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`gold::R`](R) reader structure"]
            impl crate::Readable for GOLD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`gold::W`](W) writer structure"]
            impl crate::Writable for GOLD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets GOLD to value 0"]
            impl crate::Resettable for GOLD_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CRCINIT (rw) register accessor: CRC calculation initial vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcinit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcinit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcinit`]
module"]
        pub type CRCINIT = crate::Reg<crcinit::CRCINIT_SPEC>;
        #[doc = "CRC calculation initial vector"]
        pub mod crcinit {
            #[doc = "Register `CRCINIT` reader"]
            pub type R = crate::R<CRCINIT_SPEC>;
            #[doc = "Register `CRCINIT` writer"]
            pub type W = crate::W<CRCINIT_SPEC>;
            #[doc = "Field `CRC_INIT` reader - CRC initial value"]
            pub type CRC_INIT_R = crate::FieldReader<u32>;
            #[doc = "Field `CRC_INIT` writer - CRC initial value"]
            pub type CRC_INIT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - CRC initial value"]
                #[inline(always)]
                pub fn crc_init(&self) -> CRC_INIT_R {
                    CRC_INIT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - CRC initial value"]
                #[inline(always)]
                #[must_use]
                pub fn crc_init(&mut self) -> CRC_INIT_W<CRCINIT_SPEC> {
                    CRC_INIT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "CRC calculation initial vector\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcinit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcinit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CRCINIT_SPEC;
            impl crate::RegisterSpec for CRCINIT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`crcinit::R`](R) reader structure"]
            impl crate::Readable for CRCINIT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`crcinit::W`](W) writer structure"]
            impl crate::Writable for CRCINIT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CRCINIT to value 0"]
            impl crate::Resettable for CRCINIT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CRCPOLY (rw) register accessor: CRC calculation polynomial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcpoly::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcpoly::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcpoly`]
module"]
        pub type CRCPOLY = crate::Reg<crcpoly::CRCPOLY_SPEC>;
        #[doc = "CRC calculation polynomial"]
        pub mod crcpoly {
            #[doc = "Register `CRCPOLY` reader"]
            pub type R = crate::R<CRCPOLY_SPEC>;
            #[doc = "Register `CRCPOLY` writer"]
            pub type W = crate::W<CRCPOLY_SPEC>;
            #[doc = "Field `CRC_POLY` reader - CRC polymonial"]
            pub type CRC_POLY_R = crate::FieldReader<u32>;
            #[doc = "Field `CRC_POLY` writer - CRC polymonial"]
            pub type CRC_POLY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - CRC polymonial"]
                #[inline(always)]
                pub fn crc_poly(&self) -> CRC_POLY_R {
                    CRC_POLY_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - CRC polymonial"]
                #[inline(always)]
                #[must_use]
                pub fn crc_poly(&mut self) -> CRC_POLY_W<CRCPOLY_SPEC> {
                    CRC_POLY_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "CRC calculation polynomial\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcpoly::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcpoly::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CRCPOLY_SPEC;
            impl crate::RegisterSpec for CRCPOLY_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`crcpoly::R`](R) reader structure"]
            impl crate::Readable for CRCPOLY_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`crcpoly::W`](W) writer structure"]
            impl crate::Writable for CRCPOLY_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CRCPOLY to value 0"]
            impl crate::Resettable for CRCPOLY_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "DATA (rw) register accessor: Data value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
        pub type DATA = crate::Reg<data::DATA_SPEC>;
        #[doc = "Data value"]
        pub mod data {
            #[doc = "Register `DATA` reader"]
            pub type R = crate::R<DATA_SPEC>;
            #[doc = "Register `DATA` writer"]
            pub type W = crate::W<DATA_SPEC>;
            #[doc = "Field `DATA` reader - DATA"]
            pub type DATA_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA` writer - DATA"]
            pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA"]
                #[inline(always)]
                pub fn data(&self) -> DATA_R {
                    DATA_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA"]
                #[inline(always)]
                #[must_use]
                pub fn data(&mut self) -> DATA_W<DATA_SPEC> {
                    DATA_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct DATA_SPEC;
            impl crate::RegisterSpec for DATA_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`data::R`](R) reader structure"]
            impl crate::Readable for DATA_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
            impl crate::Writable for DATA_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets DATA to value 0"]
            impl crate::Resettable for DATA_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: Data bit set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "Data bit set"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `DATA_SET` reader - DATA bit set"]
            pub type DATA_SET_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA_SET` writer - DATA bit set"]
            pub type DATA_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA bit set"]
                #[inline(always)]
                pub fn data_set(&self) -> DATA_SET_R {
                    DATA_SET_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA bit set"]
                #[inline(always)]
                #[must_use]
                pub fn data_set(&mut self) -> DATA_SET_W<SET_SPEC> {
                    DATA_SET_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data bit set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLR (rw) register accessor: Data bit clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clr`]
module"]
        pub type CLR = crate::Reg<clr::CLR_SPEC>;
        #[doc = "Data bit clear"]
        pub mod clr {
            #[doc = "Register `CLR` reader"]
            pub type R = crate::R<CLR_SPEC>;
            #[doc = "Register `CLR` writer"]
            pub type W = crate::W<CLR_SPEC>;
            #[doc = "Field `DATA_CLR` reader - DATA bit clear"]
            pub type DATA_CLR_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA_CLR` writer - DATA bit clear"]
            pub type DATA_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA bit clear"]
                #[inline(always)]
                pub fn data_clr(&self) -> DATA_CLR_R {
                    DATA_CLR_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA bit clear"]
                #[inline(always)]
                #[must_use]
                pub fn data_clr(&mut self) -> DATA_CLR_W<CLR_SPEC> {
                    DATA_CLR_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data bit clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLR_SPEC;
            impl crate::RegisterSpec for CLR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clr::R`](R) reader structure"]
            impl crate::Readable for CLR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
            impl crate::Writable for CLR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLR to value 0"]
            impl crate::Resettable for CLR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "INV (rw) register accessor: Data bit invert\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inv`]
module"]
        pub type INV = crate::Reg<inv::INV_SPEC>;
        #[doc = "Data bit invert"]
        pub mod inv {
            #[doc = "Register `INV` reader"]
            pub type R = crate::R<INV_SPEC>;
            #[doc = "Register `INV` writer"]
            pub type W = crate::W<INV_SPEC>;
            #[doc = "Field `DATA_INV` reader - DATA bit toggle"]
            pub type DATA_INV_R = crate::FieldReader<u32>;
            #[doc = "Field `DATA_INV` writer - DATA bit toggle"]
            pub type DATA_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - DATA bit toggle"]
                #[inline(always)]
                pub fn data_inv(&self) -> DATA_INV_R {
                    DATA_INV_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - DATA bit toggle"]
                #[inline(always)]
                #[must_use]
                pub fn data_inv(&mut self) -> DATA_INV_W<INV_SPEC> {
                    DATA_INV_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data bit invert\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`inv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct INV_SPEC;
            impl crate::RegisterSpec for INV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`inv::R`](R) reader structure"]
            impl crate::Readable for INV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`inv::W`](W) writer structure"]
            impl crate::Writable for INV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets INV to value 0"]
            impl crate::Resettable for INV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "IN (rw) register accessor: Data input\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@in_`]
module"]
        pub type IN = crate::Reg<in_::IN_SPEC>;
        #[doc = "Data input"]
        pub mod in_ {
            #[doc = "Register `IN` reader"]
            pub type R = crate::R<IN_SPEC>;
            #[doc = "Register `IN` writer"]
            pub type W = crate::W<IN_SPEC>;
            #[doc = "Field `DATA_IN` reader - Data input"]
            pub type DATA_IN_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Data input"]
                #[inline(always)]
                pub fn data_in(&self) -> DATA_IN_R {
                    DATA_IN_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data input\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`in_::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`in_::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct IN_SPEC;
            impl crate::RegisterSpec for IN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`in_::R`](R) reader structure"]
            impl crate::Readable for IN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`in_::W`](W) writer structure"]
            impl crate::Writable for IN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets IN to value 0"]
            impl crate::Resettable for IN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "OUT (rw) register accessor: Data output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@out`]
module"]
        pub type OUT = crate::Reg<out::OUT_SPEC>;
        #[doc = "Data output"]
        pub mod out {
            #[doc = "Register `OUT` reader"]
            pub type R = crate::R<OUT_SPEC>;
            #[doc = "Register `OUT` writer"]
            pub type W = crate::W<OUT_SPEC>;
            #[doc = "Field `DATA_OUT` reader - Data output"]
            pub type DATA_OUT_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - Data output"]
                #[inline(always)]
                pub fn data_out(&self) -> DATA_OUT_R {
                    DATA_OUT_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct OUT_SPEC;
            impl crate::RegisterSpec for OUT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`out::R`](R) reader structure"]
            impl crate::Readable for OUT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`out::W`](W) writer structure"]
            impl crate::Writable for OUT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets OUT to value 0"]
            impl crate::Resettable for OUT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "STS (rw) register accessor: Data status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sts`]
module"]
        pub type STS = crate::Reg<sts::STS_SPEC>;
        #[doc = "Data status"]
        pub mod sts {
            #[doc = "Register `STS` reader"]
            pub type R = crate::R<STS_SPEC>;
            #[doc = "Register `STS` writer"]
            pub type W = crate::W<STS_SPEC>;
            #[doc = "Field `BIT_IDX` reader - Bit index"]
            pub type BIT_IDX_R = crate::FieldReader;
            #[doc = "Field `WORD_CNT` reader - Word counter"]
            pub type WORD_CNT_R = crate::FieldReader;
            #[doc = "Field `WORD_IDX` reader - Word index"]
            pub type WORD_IDX_R = crate::FieldReader;
            #[doc = "Field `CRC_IDX` reader - CRC index"]
            pub type CRC_IDX_R = crate::FieldReader;
            impl R {
                #[doc = "Bits 0:4 - Bit index"]
                #[inline(always)]
                pub fn bit_idx(&self) -> BIT_IDX_R {
                    BIT_IDX_R::new((self.bits & 0x1f) as u8)
                }
                #[doc = "Bits 8:12 - Word counter"]
                #[inline(always)]
                pub fn word_cnt(&self) -> WORD_CNT_R {
                    WORD_CNT_R::new(((self.bits >> 8) & 0x1f) as u8)
                }
                #[doc = "Bits 16:20 - Word index"]
                #[inline(always)]
                pub fn word_idx(&self) -> WORD_IDX_R {
                    WORD_IDX_R::new(((self.bits >> 16) & 0x1f) as u8)
                }
                #[doc = "Bits 24:28 - CRC index"]
                #[inline(always)]
                pub fn crc_idx(&self) -> CRC_IDX_R {
                    CRC_IDX_R::new(((self.bits >> 24) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Data status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct STS_SPEC;
            impl crate::RegisterSpec for STS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`sts::R`](R) reader structure"]
            impl crate::Readable for STS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`sts::W`](W) writer structure"]
            impl crate::Writable for STS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets STS to value 0"]
            impl crate::Resettable for STS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "TRGM0"]
pub struct TRGM0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for TRGM0 {}
impl TRGM0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const trgm0::RegisterBlock = 0xf033_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const trgm0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for TRGM0 {
    type Target = trgm0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for TRGM0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("TRGM0").finish()
    }
}
#[doc = "TRGM0"]
pub mod trgm0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        filtcfg: [FILTCFG; 28],
        _reserved1: [u8; 0x90],
        trgocfg: [TRGOCFG; 137],
        _reserved2: [u8; 0xdc],
        dmacfg: [DMACFG; 8],
        _reserved3: [u8; 0xe0],
        gcr: GCR,
        _reserved4: [u8; 0x0c],
        adc_matrix_sel: ADC_MATRIX_SEL,
        dac_matrix_sel: DAC_MATRIX_SEL,
        pos_matrix_sel0: POS_MATRIX_SEL0,
        pos_matrix_sel1: POS_MATRIX_SEL1,
        _reserved8: [u8; 0xe0],
        trgm_in: [TRGM_IN; 4],
        _reserved9: [u8; 0x10],
        trgm_out: [TRGM_OUT; 5],
    }
    impl RegisterBlock {
        #[doc = "0x00..0x70 - no description available"]
        #[inline(always)]
        pub const fn filtcfg(&self, n: usize) -> &FILTCFG {
            &self.filtcfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x70 - no description available"]
        #[inline(always)]
        pub fn filtcfg_iter(&self) -> impl Iterator<Item = &FILTCFG> {
            self.filtcfg.iter()
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in0(&self) -> &FILTCFG {
            self.filtcfg(0)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in1(&self) -> &FILTCFG {
            self.filtcfg(1)
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in2(&self) -> &FILTCFG {
            self.filtcfg(2)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in3(&self) -> &FILTCFG {
            self.filtcfg(3)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in4(&self) -> &FILTCFG {
            self.filtcfg(4)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in5(&self) -> &FILTCFG {
            self.filtcfg(5)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in6(&self) -> &FILTCFG {
            self.filtcfg(6)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_in7(&self) -> &FILTCFG {
            self.filtcfg(7)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in0(&self) -> &FILTCFG {
            self.filtcfg(8)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in1(&self) -> &FILTCFG {
            self.filtcfg(9)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in2(&self) -> &FILTCFG {
            self.filtcfg(10)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in3(&self) -> &FILTCFG {
            self.filtcfg(11)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in4(&self) -> &FILTCFG {
            self.filtcfg(12)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in5(&self) -> &FILTCFG {
            self.filtcfg(13)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in6(&self) -> &FILTCFG {
            self.filtcfg(14)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_in7(&self) -> &FILTCFG {
            self.filtcfg(15)
        }
        #[doc = "0x40 - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in0(&self) -> &FILTCFG {
            self.filtcfg(16)
        }
        #[doc = "0x44 - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in1(&self) -> &FILTCFG {
            self.filtcfg(17)
        }
        #[doc = "0x48 - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in2(&self) -> &FILTCFG {
            self.filtcfg(18)
        }
        #[doc = "0x4c - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in3(&self) -> &FILTCFG {
            self.filtcfg(19)
        }
        #[doc = "0x50 - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in4(&self) -> &FILTCFG {
            self.filtcfg(20)
        }
        #[doc = "0x54 - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in5(&self) -> &FILTCFG {
            self.filtcfg(21)
        }
        #[doc = "0x58 - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in6(&self) -> &FILTCFG {
            self.filtcfg(22)
        }
        #[doc = "0x5c - no description available"]
        #[inline(always)]
        pub const fn filtcfgmoto_gpio_in7(&self) -> &FILTCFG {
            self.filtcfg(23)
        }
        #[doc = "0x60 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_fault0(&self) -> &FILTCFG {
            self.filtcfg(24)
        }
        #[doc = "0x64 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm0_fault1(&self) -> &FILTCFG {
            self.filtcfg(25)
        }
        #[doc = "0x68 - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_fault0(&self) -> &FILTCFG {
            self.filtcfg(26)
        }
        #[doc = "0x6c - no description available"]
        #[inline(always)]
        pub const fn filtcfgpwm1_fault1(&self) -> &FILTCFG {
            self.filtcfg(27)
        }
        #[doc = "0x100..0x324 - no description available"]
        #[inline(always)]
        pub const fn trgocfg(&self, n: usize) -> &TRGOCFG {
            &self.trgocfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x100..0x324 - no description available"]
        #[inline(always)]
        pub fn trgocfg_iter(&self) -> impl Iterator<Item = &TRGOCFG> {
            self.trgocfg.iter()
        }
        #[doc = "0x100 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_0(&self) -> &TRGOCFG {
            self.trgocfg(0)
        }
        #[doc = "0x104 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_1(&self) -> &TRGOCFG {
            self.trgocfg(1)
        }
        #[doc = "0x108 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_2(&self) -> &TRGOCFG {
            self.trgocfg(2)
        }
        #[doc = "0x10c - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_3(&self) -> &TRGOCFG {
            self.trgocfg(3)
        }
        #[doc = "0x110 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_4(&self) -> &TRGOCFG {
            self.trgocfg(4)
        }
        #[doc = "0x114 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_5(&self) -> &TRGOCFG {
            self.trgocfg(5)
        }
        #[doc = "0x118 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_6(&self) -> &TRGOCFG {
            self.trgocfg(6)
        }
        #[doc = "0x11c - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp0_7(&self) -> &TRGOCFG {
            self.trgocfg(7)
        }
        #[doc = "0x120 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_0(&self) -> &TRGOCFG {
            self.trgocfg(8)
        }
        #[doc = "0x124 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_1(&self) -> &TRGOCFG {
            self.trgocfg(9)
        }
        #[doc = "0x128 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_2(&self) -> &TRGOCFG {
            self.trgocfg(10)
        }
        #[doc = "0x12c - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_3(&self) -> &TRGOCFG {
            self.trgocfg(11)
        }
        #[doc = "0x130 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_4(&self) -> &TRGOCFG {
            self.trgocfg(12)
        }
        #[doc = "0x134 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_5(&self) -> &TRGOCFG {
            self.trgocfg(13)
        }
        #[doc = "0x138 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_6(&self) -> &TRGOCFG {
            self.trgocfg(14)
        }
        #[doc = "0x13c - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot2opamp1_7(&self) -> &TRGOCFG {
            self.trgocfg(15)
        }
        #[doc = "0x140 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr0_in2(&self) -> &TRGOCFG {
            self.trgocfg(16)
        }
        #[doc = "0x144 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr0_in3(&self) -> &TRGOCFG {
            self.trgocfg(17)
        }
        #[doc = "0x148 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr0_synci(&self) -> &TRGOCFG {
            self.trgocfg(18)
        }
        #[doc = "0x14c - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr1_in2(&self) -> &TRGOCFG {
            self.trgocfg(19)
        }
        #[doc = "0x150 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr1_in3(&self) -> &TRGOCFG {
            self.trgocfg(20)
        }
        #[doc = "0x154 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr1_synci(&self) -> &TRGOCFG {
            self.trgocfg(21)
        }
        #[doc = "0x158 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr2_in2(&self) -> &TRGOCFG {
            self.trgocfg(22)
        }
        #[doc = "0x15c - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr2_in3(&self) -> &TRGOCFG {
            self.trgocfg(23)
        }
        #[doc = "0x160 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr2_synci(&self) -> &TRGOCFG {
            self.trgocfg(24)
        }
        #[doc = "0x164 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr3_in2(&self) -> &TRGOCFG {
            self.trgocfg(25)
        }
        #[doc = "0x168 - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr3_in3(&self) -> &TRGOCFG {
            self.trgocfg(26)
        }
        #[doc = "0x16c - no description available"]
        #[inline(always)]
        pub const fn trgocfggptmr3_synci(&self) -> &TRGOCFG {
            self.trgocfg(27)
        }
        #[doc = "0x170 - no description available"]
        #[inline(always)]
        pub const fn trgocfgcmp0_win(&self) -> &TRGOCFG {
            self.trgocfg(28)
        }
        #[doc = "0x174 - no description available"]
        #[inline(always)]
        pub const fn trgocfgcmp1_win(&self) -> &TRGOCFG {
            self.trgocfg(29)
        }
        #[doc = "0x178 - no description available"]
        #[inline(always)]
        pub const fn trgocfgdac0_buftrg(&self) -> &TRGOCFG {
            self.trgocfg(30)
        }
        #[doc = "0x17c - no description available"]
        #[inline(always)]
        pub const fn trgocfgdac1_buftrg(&self) -> &TRGOCFG {
            self.trgocfg(31)
        }
        #[doc = "0x180 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadc0_strgi(&self) -> &TRGOCFG {
            self.trgocfg(32)
        }
        #[doc = "0x184 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadc1_strgi(&self) -> &TRGOCFG {
            self.trgocfg(33)
        }
        #[doc = "0x188 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi0a(&self) -> &TRGOCFG {
            self.trgocfg(34)
        }
        #[doc = "0x18c - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi0b(&self) -> &TRGOCFG {
            self.trgocfg(35)
        }
        #[doc = "0x190 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi0c(&self) -> &TRGOCFG {
            self.trgocfg(36)
        }
        #[doc = "0x194 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi1a(&self) -> &TRGOCFG {
            self.trgocfg(37)
        }
        #[doc = "0x198 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi1b(&self) -> &TRGOCFG {
            self.trgocfg(38)
        }
        #[doc = "0x19c - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi1c(&self) -> &TRGOCFG {
            self.trgocfg(39)
        }
        #[doc = "0x1a0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi2a(&self) -> &TRGOCFG {
            self.trgocfg(40)
        }
        #[doc = "0x1a4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi2b(&self) -> &TRGOCFG {
            self.trgocfg(41)
        }
        #[doc = "0x1a8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi2c(&self) -> &TRGOCFG {
            self.trgocfg(42)
        }
        #[doc = "0x1ac - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi3a(&self) -> &TRGOCFG {
            self.trgocfg(43)
        }
        #[doc = "0x1b0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi3b(&self) -> &TRGOCFG {
            self.trgocfg(44)
        }
        #[doc = "0x1b4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgadcx_ptrgi3c(&self) -> &TRGOCFG {
            self.trgocfg(45)
        }
        #[doc = "0x1b8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgcan_ptpc0_cap(&self) -> &TRGOCFG {
            self.trgocfg(46)
        }
        #[doc = "0x1bc - no description available"]
        #[inline(always)]
        pub const fn trgocfgcan_ptpc1_cap(&self) -> &TRGOCFG {
            self.trgocfg(47)
        }
        #[doc = "0x1c0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgqeo0_trig_in0(&self) -> &TRGOCFG {
            self.trgocfg(48)
        }
        #[doc = "0x1c4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgqeo0_trig_in1(&self) -> &TRGOCFG {
            self.trgocfg(49)
        }
        #[doc = "0x1c8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgqeo1_trig_in0(&self) -> &TRGOCFG {
            self.trgocfg(50)
        }
        #[doc = "0x1cc - no description available"]
        #[inline(always)]
        pub const fn trgocfgqeo1_trig_in1(&self) -> &TRGOCFG {
            self.trgocfg(51)
        }
        #[doc = "0x1d0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in0(&self) -> &TRGOCFG {
            self.trgocfg(52)
        }
        #[doc = "0x1d4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in1(&self) -> &TRGOCFG {
            self.trgocfg(53)
        }
        #[doc = "0x1d8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in2(&self) -> &TRGOCFG {
            self.trgocfg(54)
        }
        #[doc = "0x1dc - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in3(&self) -> &TRGOCFG {
            self.trgocfg(55)
        }
        #[doc = "0x1e0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in4(&self) -> &TRGOCFG {
            self.trgocfg(56)
        }
        #[doc = "0x1e4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in5(&self) -> &TRGOCFG {
            self.trgocfg(57)
        }
        #[doc = "0x1e8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in6(&self) -> &TRGOCFG {
            self.trgocfg(58)
        }
        #[doc = "0x1ec - no description available"]
        #[inline(always)]
        pub const fn trgocfgsei_trig_in7(&self) -> &TRGOCFG {
            self.trgocfg(59)
        }
        #[doc = "0x1f0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmmc0_trig_in0(&self) -> &TRGOCFG {
            self.trgocfg(60)
        }
        #[doc = "0x1f4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmmc0_trig_in1(&self) -> &TRGOCFG {
            self.trgocfg(61)
        }
        #[doc = "0x1f8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmmc1_trig_in0(&self) -> &TRGOCFG {
            self.trgocfg(62)
        }
        #[doc = "0x1fc - no description available"]
        #[inline(always)]
        pub const fn trgocfgmmc1_trig_in1(&self) -> &TRGOCFG {
            self.trgocfg(63)
        }
        #[doc = "0x200 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_00(&self) -> &TRGOCFG {
            self.trgocfg(64)
        }
        #[doc = "0x204 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_01(&self) -> &TRGOCFG {
            self.trgocfg(65)
        }
        #[doc = "0x208 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_02(&self) -> &TRGOCFG {
            self.trgocfg(66)
        }
        #[doc = "0x20c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_03(&self) -> &TRGOCFG {
            self.trgocfg(67)
        }
        #[doc = "0x210 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_04(&self) -> &TRGOCFG {
            self.trgocfg(68)
        }
        #[doc = "0x214 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_05(&self) -> &TRGOCFG {
            self.trgocfg(69)
        }
        #[doc = "0x218 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_06(&self) -> &TRGOCFG {
            self.trgocfg(70)
        }
        #[doc = "0x21c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_07(&self) -> &TRGOCFG {
            self.trgocfg(71)
        }
        #[doc = "0x220 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_08(&self) -> &TRGOCFG {
            self.trgocfg(72)
        }
        #[doc = "0x224 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_09(&self) -> &TRGOCFG {
            self.trgocfg(73)
        }
        #[doc = "0x228 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_10(&self) -> &TRGOCFG {
            self.trgocfg(74)
        }
        #[doc = "0x22c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_11(&self) -> &TRGOCFG {
            self.trgocfg(75)
        }
        #[doc = "0x230 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_12(&self) -> &TRGOCFG {
            self.trgocfg(76)
        }
        #[doc = "0x234 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_13(&self) -> &TRGOCFG {
            self.trgocfg(77)
        }
        #[doc = "0x238 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_14(&self) -> &TRGOCFG {
            self.trgocfg(78)
        }
        #[doc = "0x23c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_15(&self) -> &TRGOCFG {
            self.trgocfg(79)
        }
        #[doc = "0x240 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_16(&self) -> &TRGOCFG {
            self.trgocfg(80)
        }
        #[doc = "0x244 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_17(&self) -> &TRGOCFG {
            self.trgocfg(81)
        }
        #[doc = "0x248 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_18(&self) -> &TRGOCFG {
            self.trgocfg(82)
        }
        #[doc = "0x24c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_19(&self) -> &TRGOCFG {
            self.trgocfg(83)
        }
        #[doc = "0x250 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_20(&self) -> &TRGOCFG {
            self.trgocfg(84)
        }
        #[doc = "0x254 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_21(&self) -> &TRGOCFG {
            self.trgocfg(85)
        }
        #[doc = "0x258 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_22(&self) -> &TRGOCFG {
            self.trgocfg(86)
        }
        #[doc = "0x25c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_23(&self) -> &TRGOCFG {
            self.trgocfg(87)
        }
        #[doc = "0x260 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_24(&self) -> &TRGOCFG {
            self.trgocfg(88)
        }
        #[doc = "0x264 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_25(&self) -> &TRGOCFG {
            self.trgocfg(89)
        }
        #[doc = "0x268 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_26(&self) -> &TRGOCFG {
            self.trgocfg(90)
        }
        #[doc = "0x26c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_27(&self) -> &TRGOCFG {
            self.trgocfg(91)
        }
        #[doc = "0x270 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_28(&self) -> &TRGOCFG {
            self.trgocfg(92)
        }
        #[doc = "0x274 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_29(&self) -> &TRGOCFG {
            self.trgocfg(93)
        }
        #[doc = "0x278 - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_30(&self) -> &TRGOCFG {
            self.trgocfg(94)
        }
        #[doc = "0x27c - no description available"]
        #[inline(always)]
        pub const fn trgocfgplb_in_31(&self) -> &TRGOCFG {
            self.trgocfg(95)
        }
        #[doc = "0x280 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio0(&self) -> &TRGOCFG {
            self.trgocfg(96)
        }
        #[doc = "0x284 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio1(&self) -> &TRGOCFG {
            self.trgocfg(97)
        }
        #[doc = "0x288 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio2(&self) -> &TRGOCFG {
            self.trgocfg(98)
        }
        #[doc = "0x28c - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio3(&self) -> &TRGOCFG {
            self.trgocfg(99)
        }
        #[doc = "0x290 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio4(&self) -> &TRGOCFG {
            self.trgocfg(100)
        }
        #[doc = "0x294 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio5(&self) -> &TRGOCFG {
            self.trgocfg(101)
        }
        #[doc = "0x298 - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio6(&self) -> &TRGOCFG {
            self.trgocfg(102)
        }
        #[doc = "0x29c - no description available"]
        #[inline(always)]
        pub const fn trgocfgmot_gpio7(&self) -> &TRGOCFG {
            self.trgocfg(103)
        }
        #[doc = "0x2a0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in8(&self) -> &TRGOCFG {
            self.trgocfg(104)
        }
        #[doc = "0x2a4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in9(&self) -> &TRGOCFG {
            self.trgocfg(105)
        }
        #[doc = "0x2a8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in10(&self) -> &TRGOCFG {
            self.trgocfg(106)
        }
        #[doc = "0x2ac - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in11(&self) -> &TRGOCFG {
            self.trgocfg(107)
        }
        #[doc = "0x2b0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in12(&self) -> &TRGOCFG {
            self.trgocfg(108)
        }
        #[doc = "0x2b4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in13(&self) -> &TRGOCFG {
            self.trgocfg(109)
        }
        #[doc = "0x2b8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in14(&self) -> &TRGOCFG {
            self.trgocfg(110)
        }
        #[doc = "0x2bc - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm_in15(&self) -> &TRGOCFG {
            self.trgocfg(111)
        }
        #[doc = "0x2c0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm0_frci(&self) -> &TRGOCFG {
            self.trgocfg(112)
        }
        #[doc = "0x2c4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm0_frcsynci(&self) -> &TRGOCFG {
            self.trgocfg(113)
        }
        #[doc = "0x2c8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm0_synci(&self) -> &TRGOCFG {
            self.trgocfg(114)
        }
        #[doc = "0x2cc - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm0_shrldsynci(&self) -> &TRGOCFG {
            self.trgocfg(115)
        }
        #[doc = "0x2d0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm0_faulti0(&self) -> &TRGOCFG {
            self.trgocfg(116)
        }
        #[doc = "0x2d4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm0_faulti1(&self) -> &TRGOCFG {
            self.trgocfg(117)
        }
        #[doc = "0x2d8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm1_frci(&self) -> &TRGOCFG {
            self.trgocfg(118)
        }
        #[doc = "0x2dc - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm1_frcsynci(&self) -> &TRGOCFG {
            self.trgocfg(119)
        }
        #[doc = "0x2e0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm1_synci(&self) -> &TRGOCFG {
            self.trgocfg(120)
        }
        #[doc = "0x2e4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm1_shrldsynci(&self) -> &TRGOCFG {
            self.trgocfg(121)
        }
        #[doc = "0x2e8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm1_faulti0(&self) -> &TRGOCFG {
            self.trgocfg(122)
        }
        #[doc = "0x2ec - no description available"]
        #[inline(always)]
        pub const fn trgocfgpwm1_faulti1(&self) -> &TRGOCFG {
            self.trgocfg(123)
        }
        #[doc = "0x2f0 - no description available"]
        #[inline(always)]
        pub const fn trgocfgrdc_trig_in0(&self) -> &TRGOCFG {
            self.trgocfg(124)
        }
        #[doc = "0x2f4 - no description available"]
        #[inline(always)]
        pub const fn trgocfgrdc_trig_in1(&self) -> &TRGOCFG {
            self.trgocfg(125)
        }
        #[doc = "0x2f8 - no description available"]
        #[inline(always)]
        pub const fn trgocfgsynctimer_trig(&self) -> &TRGOCFG {
            self.trgocfg(126)
        }
        #[doc = "0x2fc - no description available"]
        #[inline(always)]
        pub const fn trgocfgqei0_trig_in(&self) -> &TRGOCFG {
            self.trgocfg(127)
        }
        #[doc = "0x300 - no description available"]
        #[inline(always)]
        pub const fn trgocfgqei1_trig_in(&self) -> &TRGOCFG {
            self.trgocfg(128)
        }
        #[doc = "0x304 - no description available"]
        #[inline(always)]
        pub const fn trgocfgqei0_pause(&self) -> &TRGOCFG {
            self.trgocfg(129)
        }
        #[doc = "0x308 - no description available"]
        #[inline(always)]
        pub const fn trgocfgqei1_pause(&self) -> &TRGOCFG {
            self.trgocfg(130)
        }
        #[doc = "0x30c - no description available"]
        #[inline(always)]
        pub const fn trgocfguart_trig0(&self) -> &TRGOCFG {
            self.trgocfg(131)
        }
        #[doc = "0x310 - no description available"]
        #[inline(always)]
        pub const fn trgocfguart_trig1(&self) -> &TRGOCFG {
            self.trgocfg(132)
        }
        #[doc = "0x314 - no description available"]
        #[inline(always)]
        pub const fn trgocfgtrgm_irq0(&self) -> &TRGOCFG {
            self.trgocfg(133)
        }
        #[doc = "0x318 - no description available"]
        #[inline(always)]
        pub const fn trgocfgtrgm_irq1(&self) -> &TRGOCFG {
            self.trgocfg(134)
        }
        #[doc = "0x31c - no description available"]
        #[inline(always)]
        pub const fn trgocfgtrgm_dma0(&self) -> &TRGOCFG {
            self.trgocfg(135)
        }
        #[doc = "0x320 - no description available"]
        #[inline(always)]
        pub const fn trgocfgtrgm_dma1(&self) -> &TRGOCFG {
            self.trgocfg(136)
        }
        #[doc = "0x400..0x420 - no description available"]
        #[inline(always)]
        pub const fn dmacfg(&self, n: usize) -> &DMACFG {
            &self.dmacfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x400..0x420 - no description available"]
        #[inline(always)]
        pub fn dmacfg_iter(&self) -> impl Iterator<Item = &DMACFG> {
            self.dmacfg.iter()
        }
        #[doc = "0x500 - General Control Register"]
        #[inline(always)]
        pub const fn gcr(&self) -> &GCR {
            &self.gcr
        }
        #[doc = "0x510 - adc matrix select register"]
        #[inline(always)]
        pub const fn adc_matrix_sel(&self) -> &ADC_MATRIX_SEL {
            &self.adc_matrix_sel
        }
        #[doc = "0x514 - dac matrix select register"]
        #[inline(always)]
        pub const fn dac_matrix_sel(&self) -> &DAC_MATRIX_SEL {
            &self.dac_matrix_sel
        }
        #[doc = "0x518 - position matrix select register0"]
        #[inline(always)]
        pub const fn pos_matrix_sel0(&self) -> &POS_MATRIX_SEL0 {
            &self.pos_matrix_sel0
        }
        #[doc = "0x51c - position matrix select register1"]
        #[inline(always)]
        pub const fn pos_matrix_sel1(&self) -> &POS_MATRIX_SEL1 {
            &self.pos_matrix_sel1
        }
        #[doc = "0x600..0x610 - no description available"]
        #[inline(always)]
        pub const fn trgm_in(&self, n: usize) -> &TRGM_IN {
            &self.trgm_in[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x600..0x610 - no description available"]
        #[inline(always)]
        pub fn trgm_in_iter(&self) -> impl Iterator<Item = &TRGM_IN> {
            self.trgm_in.iter()
        }
        #[doc = "0x620..0x634 - no description available"]
        #[inline(always)]
        pub const fn trgm_out(&self, n: usize) -> &TRGM_OUT {
            &self.trgm_out[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x620..0x634 - no description available"]
        #[inline(always)]
        pub fn trgm_out_iter(&self) -> impl Iterator<Item = &TRGM_OUT> {
            self.trgm_out.iter()
        }
    }
    #[doc = "FILTCFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filtcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filtcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filtcfg`]
module"]
    pub type FILTCFG = crate::Reg<filtcfg::FILTCFG_SPEC>;
    #[doc = "no description available"]
    pub mod filtcfg {
        #[doc = "Register `FILTCFG[%s]` reader"]
        pub type R = crate::R<FILTCFG_SPEC>;
        #[doc = "Register `FILTCFG[%s]` writer"]
        pub type W = crate::W<FILTCFG_SPEC>;
        #[doc = "Field `FILTLEN` reader - This bitfields defines the filter counter length."]
        pub type FILTLEN_R = crate::FieldReader<u16>;
        #[doc = "Field `FILTLEN` writer - This bitfields defines the filter counter length."]
        pub type FILTLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `SYNCEN` reader - set to enable sychronization input signal with TRGM clock"]
        pub type SYNCEN_R = crate::BitReader;
        #[doc = "Field `SYNCEN` writer - set to enable sychronization input signal with TRGM clock"]
        pub type SYNCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MODE` reader - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stalbe low mode; 111-stable high mode"]
        pub type MODE_R = crate::FieldReader;
        #[doc = "Field `MODE` writer - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stalbe low mode; 111-stable high mode"]
        pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `OUTINV` reader - 1- Filter will invert the output 0- Filter will not invert the output"]
        pub type OUTINV_R = crate::BitReader;
        #[doc = "Field `OUTINV` writer - 1- Filter will invert the output 0- Filter will not invert the output"]
        pub type OUTINV_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:11 - This bitfields defines the filter counter length."]
            #[inline(always)]
            pub fn filtlen(&self) -> FILTLEN_R {
                FILTLEN_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bit 12 - set to enable sychronization input signal with TRGM clock"]
            #[inline(always)]
            pub fn syncen(&self) -> SYNCEN_R {
                SYNCEN_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bits 13:15 - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stalbe low mode; 111-stable high mode"]
            #[inline(always)]
            pub fn mode(&self) -> MODE_R {
                MODE_R::new(((self.bits >> 13) & 7) as u8)
            }
            #[doc = "Bit 16 - 1- Filter will invert the output 0- Filter will not invert the output"]
            #[inline(always)]
            pub fn outinv(&self) -> OUTINV_R {
                OUTINV_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - This bitfields defines the filter counter length."]
            #[inline(always)]
            #[must_use]
            pub fn filtlen(&mut self) -> FILTLEN_W<FILTCFG_SPEC> {
                FILTLEN_W::new(self, 0)
            }
            #[doc = "Bit 12 - set to enable sychronization input signal with TRGM clock"]
            #[inline(always)]
            #[must_use]
            pub fn syncen(&mut self) -> SYNCEN_W<FILTCFG_SPEC> {
                SYNCEN_W::new(self, 12)
            }
            #[doc = "Bits 13:15 - This bitfields defines the filter mode 000-bypass; 100-rapid change mode; 101-delay filter mode; 110-stalbe low mode; 111-stable high mode"]
            #[inline(always)]
            #[must_use]
            pub fn mode(&mut self) -> MODE_W<FILTCFG_SPEC> {
                MODE_W::new(self, 13)
            }
            #[doc = "Bit 16 - 1- Filter will invert the output 0- Filter will not invert the output"]
            #[inline(always)]
            #[must_use]
            pub fn outinv(&mut self) -> OUTINV_W<FILTCFG_SPEC> {
                OUTINV_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filtcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filtcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FILTCFG_SPEC;
        impl crate::RegisterSpec for FILTCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`filtcfg::R`](R) reader structure"]
        impl crate::Readable for FILTCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`filtcfg::W`](W) writer structure"]
        impl crate::Writable for FILTCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FILTCFG[%s]
to value 0"]
        impl crate::Resettable for FILTCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TRGOCFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgocfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgocfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trgocfg`]
module"]
    pub type TRGOCFG = crate::Reg<trgocfg::TRGOCFG_SPEC>;
    #[doc = "no description available"]
    pub mod trgocfg {
        #[doc = "Register `TRGOCFG[%s]` reader"]
        pub type R = crate::R<TRGOCFG_SPEC>;
        #[doc = "Register `TRGOCFG[%s]` writer"]
        pub type W = crate::W<TRGOCFG_SPEC>;
        #[doc = "Field `TRIGOSEL` reader - This bitfield selects one of the TRGM inputs as output."]
        pub type TRIGOSEL_R = crate::FieldReader;
        #[doc = "Field `TRIGOSEL` writer - This bitfield selects one of the TRGM inputs as output."]
        pub type TRIGOSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `REDG2PEN` reader - 1- The selected input signal rising edge will be convert to an pulse on output."]
        pub type REDG2PEN_R = crate::BitReader;
        #[doc = "Field `REDG2PEN` writer - 1- The selected input signal rising edge will be convert to an pulse on output."]
        pub type REDG2PEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FEDG2PEN` reader - 1- The selected input signal falling edge will be convert to an pulse on output."]
        pub type FEDG2PEN_R = crate::BitReader;
        #[doc = "Field `FEDG2PEN` writer - 1- The selected input signal falling edge will be convert to an pulse on output."]
        pub type FEDG2PEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OUTINV` reader - 1- Invert the output"]
        pub type OUTINV_R = crate::BitReader;
        #[doc = "Field `OUTINV` writer - 1- Invert the output"]
        pub type OUTINV_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:6 - This bitfield selects one of the TRGM inputs as output."]
            #[inline(always)]
            pub fn trigosel(&self) -> TRIGOSEL_R {
                TRIGOSEL_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bit 9 - 1- The selected input signal rising edge will be convert to an pulse on output."]
            #[inline(always)]
            pub fn redg2pen(&self) -> REDG2PEN_R {
                REDG2PEN_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - 1- The selected input signal falling edge will be convert to an pulse on output."]
            #[inline(always)]
            pub fn fedg2pen(&self) -> FEDG2PEN_R {
                FEDG2PEN_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - 1- Invert the output"]
            #[inline(always)]
            pub fn outinv(&self) -> OUTINV_R {
                OUTINV_R::new(((self.bits >> 11) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - This bitfield selects one of the TRGM inputs as output."]
            #[inline(always)]
            #[must_use]
            pub fn trigosel(&mut self) -> TRIGOSEL_W<TRGOCFG_SPEC> {
                TRIGOSEL_W::new(self, 0)
            }
            #[doc = "Bit 9 - 1- The selected input signal rising edge will be convert to an pulse on output."]
            #[inline(always)]
            #[must_use]
            pub fn redg2pen(&mut self) -> REDG2PEN_W<TRGOCFG_SPEC> {
                REDG2PEN_W::new(self, 9)
            }
            #[doc = "Bit 10 - 1- The selected input signal falling edge will be convert to an pulse on output."]
            #[inline(always)]
            #[must_use]
            pub fn fedg2pen(&mut self) -> FEDG2PEN_W<TRGOCFG_SPEC> {
                FEDG2PEN_W::new(self, 10)
            }
            #[doc = "Bit 11 - 1- Invert the output"]
            #[inline(always)]
            #[must_use]
            pub fn outinv(&mut self) -> OUTINV_W<TRGOCFG_SPEC> {
                OUTINV_W::new(self, 11)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgocfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgocfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRGOCFG_SPEC;
        impl crate::RegisterSpec for TRGOCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trgocfg::R`](R) reader structure"]
        impl crate::Readable for TRGOCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trgocfg::W`](W) writer structure"]
        impl crate::Writable for TRGOCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TRGOCFG[%s]
to value 0"]
        impl crate::Resettable for TRGOCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DMACFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmacfg`]
module"]
    pub type DMACFG = crate::Reg<dmacfg::DMACFG_SPEC>;
    #[doc = "no description available"]
    pub mod dmacfg {
        #[doc = "Register `DMACFG[%s]` reader"]
        pub type R = crate::R<DMACFG_SPEC>;
        #[doc = "Register `DMACFG[%s]` writer"]
        pub type W = crate::W<DMACFG_SPEC>;
        #[doc = "Field `DMASRCSEL` reader - This field selects one of the DMA requests as the DMA request output."]
        pub type DMASRCSEL_R = crate::FieldReader;
        #[doc = "Field `DMASRCSEL` writer - This field selects one of the DMA requests as the DMA request output."]
        pub type DMASRCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `DMAMUX_EN` reader - No description avaiable"]
        pub type DMAMUX_EN_R = crate::BitReader;
        #[doc = "Field `DMAMUX_EN` writer - No description avaiable"]
        pub type DMAMUX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:5 - This field selects one of the DMA requests as the DMA request output."]
            #[inline(always)]
            pub fn dmasrcsel(&self) -> DMASRCSEL_R {
                DMASRCSEL_R::new((self.bits & 0x3f) as u8)
            }
            #[doc = "Bit 31 - No description avaiable"]
            #[inline(always)]
            pub fn dmamux_en(&self) -> DMAMUX_EN_R {
                DMAMUX_EN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:5 - This field selects one of the DMA requests as the DMA request output."]
            #[inline(always)]
            #[must_use]
            pub fn dmasrcsel(&mut self) -> DMASRCSEL_W<DMACFG_SPEC> {
                DMASRCSEL_W::new(self, 0)
            }
            #[doc = "Bit 31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dmamux_en(&mut self) -> DMAMUX_EN_W<DMACFG_SPEC> {
                DMAMUX_EN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmacfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmacfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DMACFG_SPEC;
        impl crate::RegisterSpec for DMACFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dmacfg::R`](R) reader structure"]
        impl crate::Readable for DMACFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dmacfg::W`](W) writer structure"]
        impl crate::Writable for DMACFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DMACFG[%s]
to value 0"]
        impl crate::Resettable for DMACFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GCR (rw) register accessor: General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gcr`]
module"]
    pub type GCR = crate::Reg<gcr::GCR_SPEC>;
    #[doc = "General Control Register"]
    pub mod gcr {
        #[doc = "Register `GCR` reader"]
        pub type R = crate::R<GCR_SPEC>;
        #[doc = "Register `GCR` writer"]
        pub type W = crate::W<GCR_SPEC>;
        #[doc = "Field `TRGOPEN` reader - The bitfield enable the TRGM outputs."]
        pub type TRGOPEN_R = crate::FieldReader;
        #[doc = "Field `TRGOPEN` writer - The bitfield enable the TRGM outputs."]
        pub type TRGOPEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - The bitfield enable the TRGM outputs."]
            #[inline(always)]
            pub fn trgopen(&self) -> TRGOPEN_R {
                TRGOPEN_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - The bitfield enable the TRGM outputs."]
            #[inline(always)]
            #[must_use]
            pub fn trgopen(&mut self) -> TRGOPEN_W<GCR_SPEC> {
                TRGOPEN_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "General Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GCR_SPEC;
        impl crate::RegisterSpec for GCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gcr::R`](R) reader structure"]
        impl crate::Readable for GCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gcr::W`](W) writer structure"]
        impl crate::Writable for GCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GCR to value 0"]
        impl crate::Resettable for GCR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ADC_MATRIX_SEL (rw) register accessor: adc matrix select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_matrix_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_matrix_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_matrix_sel`]
module"]
    pub type ADC_MATRIX_SEL = crate::Reg<adc_matrix_sel::ADC_MATRIX_SEL_SPEC>;
    #[doc = "adc matrix select register"]
    pub mod adc_matrix_sel {
        #[doc = "Register `ADC_MATRIX_SEL` reader"]
        pub type R = crate::R<ADC_MATRIX_SEL_SPEC>;
        #[doc = "Register `ADC_MATRIX_SEL` writer"]
        pub type W = crate::W<ADC_MATRIX_SEL_SPEC>;
        #[doc = "Field `QEI0_ADC0_SEL` reader - No description avaiable"]
        pub type QEI0_ADC0_SEL_R = crate::FieldReader;
        #[doc = "Field `QEI0_ADC0_SEL` writer - No description avaiable"]
        pub type QEI0_ADC0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `QEI0_ADC1_SEL` reader - No description avaiable"]
        pub type QEI0_ADC1_SEL_R = crate::FieldReader;
        #[doc = "Field `QEI0_ADC1_SEL` writer - No description avaiable"]
        pub type QEI0_ADC1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `QEI1_ADC0_SEL` reader - No description avaiable"]
        pub type QEI1_ADC0_SEL_R = crate::FieldReader;
        #[doc = "Field `QEI1_ADC0_SEL` writer - No description avaiable"]
        pub type QEI1_ADC0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `QEI1_ADC1_SEL` reader - 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; bit7 is used to invert adc_value; others reserved"]
        pub type QEI1_ADC1_SEL_R = crate::FieldReader;
        #[doc = "Field `QEI1_ADC1_SEL` writer - 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; bit7 is used to invert adc_value; others reserved"]
        pub type QEI1_ADC1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            pub fn qei0_adc0_sel(&self) -> QEI0_ADC0_SEL_R {
                QEI0_ADC0_SEL_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            pub fn qei0_adc1_sel(&self) -> QEI0_ADC1_SEL_R {
                QEI0_ADC1_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - No description avaiable"]
            #[inline(always)]
            pub fn qei1_adc0_sel(&self) -> QEI1_ADC0_SEL_R {
                QEI1_ADC0_SEL_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bits 24:31 - 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; bit7 is used to invert adc_value; others reserved"]
            #[inline(always)]
            pub fn qei1_adc1_sel(&self) -> QEI1_ADC1_SEL_R {
                QEI1_ADC1_SEL_R::new(((self.bits >> 24) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn qei0_adc0_sel(&mut self) -> QEI0_ADC0_SEL_W<ADC_MATRIX_SEL_SPEC> {
                QEI0_ADC0_SEL_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn qei0_adc1_sel(&mut self) -> QEI0_ADC1_SEL_W<ADC_MATRIX_SEL_SPEC> {
                QEI0_ADC1_SEL_W::new(self, 8)
            }
            #[doc = "Bits 16:23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn qei1_adc0_sel(&mut self) -> QEI1_ADC0_SEL_W<ADC_MATRIX_SEL_SPEC> {
                QEI1_ADC0_SEL_W::new(self, 16)
            }
            #[doc = "Bits 24:31 - 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; bit7 is used to invert adc_value; others reserved"]
            #[inline(always)]
            #[must_use]
            pub fn qei1_adc1_sel(&mut self) -> QEI1_ADC1_SEL_W<ADC_MATRIX_SEL_SPEC> {
                QEI1_ADC1_SEL_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "adc matrix select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_matrix_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_matrix_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADC_MATRIX_SEL_SPEC;
        impl crate::RegisterSpec for ADC_MATRIX_SEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adc_matrix_sel::R`](R) reader structure"]
        impl crate::Readable for ADC_MATRIX_SEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adc_matrix_sel::W`](W) writer structure"]
        impl crate::Writable for ADC_MATRIX_SEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ADC_MATRIX_SEL to value 0"]
        impl crate::Resettable for ADC_MATRIX_SEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DAC_MATRIX_SEL (rw) register accessor: dac matrix select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac_matrix_sel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dac_matrix_sel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac_matrix_sel`]
module"]
    pub type DAC_MATRIX_SEL = crate::Reg<dac_matrix_sel::DAC_MATRIX_SEL_SPEC>;
    #[doc = "dac matrix select register"]
    pub mod dac_matrix_sel {
        #[doc = "Register `DAC_MATRIX_SEL` reader"]
        pub type R = crate::R<DAC_MATRIX_SEL_SPEC>;
        #[doc = "Register `DAC_MATRIX_SEL` writer"]
        pub type W = crate::W<DAC_MATRIX_SEL_SPEC>;
        #[doc = "Field `ACMP0_DAC_SEL` reader - No description avaiable"]
        pub type ACMP0_DAC_SEL_R = crate::FieldReader;
        #[doc = "Field `ACMP0_DAC_SEL` writer - No description avaiable"]
        pub type ACMP0_DAC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `ACMP1_DAC_SEL` reader - No description avaiable"]
        pub type ACMP1_DAC_SEL_R = crate::FieldReader;
        #[doc = "Field `ACMP1_DAC_SEL` writer - No description avaiable"]
        pub type ACMP1_DAC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `DAC0_DAC_SEL` reader - No description avaiable"]
        pub type DAC0_DAC_SEL_R = crate::FieldReader;
        #[doc = "Field `DAC0_DAC_SEL` writer - No description avaiable"]
        pub type DAC0_DAC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `DAC1_DAC_SEL` reader - 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; 3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; 6-rdc_dac0; 7-rdc_dac1; bit7 is used to invert dac_value; others reserved"]
        pub type DAC1_DAC_SEL_R = crate::FieldReader;
        #[doc = "Field `DAC1_DAC_SEL` writer - 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; 3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; 6-rdc_dac0; 7-rdc_dac1; bit7 is used to invert dac_value; others reserved"]
        pub type DAC1_DAC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            pub fn acmp0_dac_sel(&self) -> ACMP0_DAC_SEL_R {
                ACMP0_DAC_SEL_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            pub fn acmp1_dac_sel(&self) -> ACMP1_DAC_SEL_R {
                ACMP1_DAC_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - No description avaiable"]
            #[inline(always)]
            pub fn dac0_dac_sel(&self) -> DAC0_DAC_SEL_R {
                DAC0_DAC_SEL_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bits 24:31 - 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; 3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; 6-rdc_dac0; 7-rdc_dac1; bit7 is used to invert dac_value; others reserved"]
            #[inline(always)]
            pub fn dac1_dac_sel(&self) -> DAC1_DAC_SEL_R {
                DAC1_DAC_SEL_R::new(((self.bits >> 24) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn acmp0_dac_sel(&mut self) -> ACMP0_DAC_SEL_W<DAC_MATRIX_SEL_SPEC> {
                ACMP0_DAC_SEL_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn acmp1_dac_sel(&mut self) -> ACMP1_DAC_SEL_W<DAC_MATRIX_SEL_SPEC> {
                ACMP1_DAC_SEL_W::new(self, 8)
            }
            #[doc = "Bits 16:23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dac0_dac_sel(&mut self) -> DAC0_DAC_SEL_W<DAC_MATRIX_SEL_SPEC> {
                DAC0_DAC_SEL_W::new(self, 16)
            }
            #[doc = "Bits 24:31 - 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; 3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; 6-rdc_dac0; 7-rdc_dac1; bit7 is used to invert dac_value; others reserved"]
            #[inline(always)]
            #[must_use]
            pub fn dac1_dac_sel(&mut self) -> DAC1_DAC_SEL_W<DAC_MATRIX_SEL_SPEC> {
                DAC1_DAC_SEL_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "dac matrix select register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac_matrix_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dac_matrix_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DAC_MATRIX_SEL_SPEC;
        impl crate::RegisterSpec for DAC_MATRIX_SEL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dac_matrix_sel::R`](R) reader structure"]
        impl crate::Readable for DAC_MATRIX_SEL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dac_matrix_sel::W`](W) writer structure"]
        impl crate::Writable for DAC_MATRIX_SEL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DAC_MATRIX_SEL to value 0"]
        impl crate::Resettable for DAC_MATRIX_SEL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "POS_MATRIX_SEL0 (rw) register accessor: position matrix select register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_matrix_sel0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_matrix_sel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_matrix_sel0`]
module"]
    pub type POS_MATRIX_SEL0 = crate::Reg<pos_matrix_sel0::POS_MATRIX_SEL0_SPEC>;
    #[doc = "position matrix select register0"]
    pub mod pos_matrix_sel0 {
        #[doc = "Register `POS_MATRIX_SEL0` reader"]
        pub type R = crate::R<POS_MATRIX_SEL0_SPEC>;
        #[doc = "Register `POS_MATRIX_SEL0` writer"]
        pub type W = crate::W<POS_MATRIX_SEL0_SPEC>;
        #[doc = "Field `SEI_POSIN0_SEL` reader - No description avaiable"]
        pub type SEI_POSIN0_SEL_R = crate::FieldReader;
        #[doc = "Field `SEI_POSIN0_SEL` writer - No description avaiable"]
        pub type SEI_POSIN0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `SEI_POSIN1_SEL` reader - No description avaiable"]
        pub type SEI_POSIN1_SEL_R = crate::FieldReader;
        #[doc = "Field `SEI_POSIN1_SEL` writer - No description avaiable"]
        pub type SEI_POSIN1_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `MMC0_POSIN_SEL` reader - No description avaiable"]
        pub type MMC0_POSIN_SEL_R = crate::FieldReader;
        #[doc = "Field `MMC0_POSIN_SEL` writer - No description avaiable"]
        pub type MMC0_POSIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `MMC1_POSIN_SEL` reader - 0-sei_pos_out0; 1-sei_pos_out1; 2-qei0_pos; 3-qei1_pos; 4-mmc0_pos_out0; 5-mmc0_pos_out1; 6-mmc1_pos_out0; 7-mmc1_pos_out1; bit7 is used to invert position value; others reserved"]
        pub type MMC1_POSIN_SEL_R = crate::FieldReader;
        #[doc = "Field `MMC1_POSIN_SEL` writer - 0-sei_pos_out0; 1-sei_pos_out1; 2-qei0_pos; 3-qei1_pos; 4-mmc0_pos_out0; 5-mmc0_pos_out1; 6-mmc1_pos_out0; 7-mmc1_pos_out1; bit7 is used to invert position value; others reserved"]
        pub type MMC1_POSIN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            pub fn sei_posin0_sel(&self) -> SEI_POSIN0_SEL_R {
                SEI_POSIN0_SEL_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            pub fn sei_posin1_sel(&self) -> SEI_POSIN1_SEL_R {
                SEI_POSIN1_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - No description avaiable"]
            #[inline(always)]
            pub fn mmc0_posin_sel(&self) -> MMC0_POSIN_SEL_R {
                MMC0_POSIN_SEL_R::new(((self.bits >> 16) & 0xff) as u8)
            }
            #[doc = "Bits 24:31 - 0-sei_pos_out0; 1-sei_pos_out1; 2-qei0_pos; 3-qei1_pos; 4-mmc0_pos_out0; 5-mmc0_pos_out1; 6-mmc1_pos_out0; 7-mmc1_pos_out1; bit7 is used to invert position value; others reserved"]
            #[inline(always)]
            pub fn mmc1_posin_sel(&self) -> MMC1_POSIN_SEL_R {
                MMC1_POSIN_SEL_R::new(((self.bits >> 24) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn sei_posin0_sel(&mut self) -> SEI_POSIN0_SEL_W<POS_MATRIX_SEL0_SPEC> {
                SEI_POSIN0_SEL_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn sei_posin1_sel(&mut self) -> SEI_POSIN1_SEL_W<POS_MATRIX_SEL0_SPEC> {
                SEI_POSIN1_SEL_W::new(self, 8)
            }
            #[doc = "Bits 16:23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn mmc0_posin_sel(&mut self) -> MMC0_POSIN_SEL_W<POS_MATRIX_SEL0_SPEC> {
                MMC0_POSIN_SEL_W::new(self, 16)
            }
            #[doc = "Bits 24:31 - 0-sei_pos_out0; 1-sei_pos_out1; 2-qei0_pos; 3-qei1_pos; 4-mmc0_pos_out0; 5-mmc0_pos_out1; 6-mmc1_pos_out0; 7-mmc1_pos_out1; bit7 is used to invert position value; others reserved"]
            #[inline(always)]
            #[must_use]
            pub fn mmc1_posin_sel(&mut self) -> MMC1_POSIN_SEL_W<POS_MATRIX_SEL0_SPEC> {
                MMC1_POSIN_SEL_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "position matrix select register0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_matrix_sel0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_matrix_sel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POS_MATRIX_SEL0_SPEC;
        impl crate::RegisterSpec for POS_MATRIX_SEL0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pos_matrix_sel0::R`](R) reader structure"]
        impl crate::Readable for POS_MATRIX_SEL0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pos_matrix_sel0::W`](W) writer structure"]
        impl crate::Writable for POS_MATRIX_SEL0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets POS_MATRIX_SEL0 to value 0"]
        impl crate::Resettable for POS_MATRIX_SEL0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "POS_MATRIX_SEL1 (rw) register accessor: position matrix select register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_matrix_sel1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_matrix_sel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pos_matrix_sel1`]
module"]
    pub type POS_MATRIX_SEL1 = crate::Reg<pos_matrix_sel1::POS_MATRIX_SEL1_SPEC>;
    #[doc = "position matrix select register1"]
    pub mod pos_matrix_sel1 {
        #[doc = "Register `POS_MATRIX_SEL1` reader"]
        pub type R = crate::R<POS_MATRIX_SEL1_SPEC>;
        #[doc = "Register `POS_MATRIX_SEL1` writer"]
        pub type W = crate::W<POS_MATRIX_SEL1_SPEC>;
        #[doc = "Field `QEO0_POS_SEL` reader - No description avaiable"]
        pub type QEO0_POS_SEL_R = crate::FieldReader;
        #[doc = "Field `QEO0_POS_SEL` writer - No description avaiable"]
        pub type QEO0_POS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `QEO1_POS_SEL` reader - No description avaiable"]
        pub type QEO1_POS_SEL_R = crate::FieldReader;
        #[doc = "Field `QEO1_POS_SEL` writer - No description avaiable"]
        pub type QEO1_POS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            pub fn qeo0_pos_sel(&self) -> QEO0_POS_SEL_R {
                QEO0_POS_SEL_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            pub fn qeo1_pos_sel(&self) -> QEO1_POS_SEL_R {
                QEO1_POS_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn qeo0_pos_sel(&mut self) -> QEO0_POS_SEL_W<POS_MATRIX_SEL1_SPEC> {
                QEO0_POS_SEL_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn qeo1_pos_sel(&mut self) -> QEO1_POS_SEL_W<POS_MATRIX_SEL1_SPEC> {
                QEO1_POS_SEL_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "position matrix select register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pos_matrix_sel1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pos_matrix_sel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POS_MATRIX_SEL1_SPEC;
        impl crate::RegisterSpec for POS_MATRIX_SEL1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pos_matrix_sel1::R`](R) reader structure"]
        impl crate::Readable for POS_MATRIX_SEL1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pos_matrix_sel1::W`](W) writer structure"]
        impl crate::Writable for POS_MATRIX_SEL1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets POS_MATRIX_SEL1 to value 0"]
        impl crate::Resettable for POS_MATRIX_SEL1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TRGM_IN (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgm_in::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgm_in::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trgm_in`]
module"]
    pub type TRGM_IN = crate::Reg<trgm_in::TRGM_IN_SPEC>;
    #[doc = "no description available"]
    pub mod trgm_in {
        #[doc = "Register `TRGM_IN[%s]` reader"]
        pub type R = crate::R<TRGM_IN_SPEC>;
        #[doc = "Register `TRGM_IN[%s]` writer"]
        pub type W = crate::W<TRGM_IN_SPEC>;
        #[doc = "Field `TRGM_IN` reader - mmc1_trig_out\\[1:0\\], mmc0_trig_out\\[1:0\\],sync_pulse\\[3:0\\],moto_gpio_in_sync\\[7:0\\],//31:16 gtmr3_to_motor_sync\\[1:0\\],gtmr2_to_motor_sync\\[1:0\\],gtmr1_to_motor_sync\\[1:0\\],gtmr0_to_motor_sync\\[1:0\\], //15:8 acmp_out_sync\\[1:0\\],can2mot_event_sync\\[1:0\\],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0"]
        pub type TRGM_IN_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - mmc1_trig_out\\[1:0\\], mmc0_trig_out\\[1:0\\],sync_pulse\\[3:0\\],moto_gpio_in_sync\\[7:0\\],//31:16 gtmr3_to_motor_sync\\[1:0\\],gtmr2_to_motor_sync\\[1:0\\],gtmr1_to_motor_sync\\[1:0\\],gtmr0_to_motor_sync\\[1:0\\], //15:8 acmp_out_sync\\[1:0\\],can2mot_event_sync\\[1:0\\],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0"]
            #[inline(always)]
            pub fn trgm_in(&self) -> TRGM_IN_R {
                TRGM_IN_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgm_in::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgm_in::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRGM_IN_SPEC;
        impl crate::RegisterSpec for TRGM_IN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trgm_in::R`](R) reader structure"]
        impl crate::Readable for TRGM_IN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trgm_in::W`](W) writer structure"]
        impl crate::Writable for TRGM_IN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TRGM_IN[%s]
to value 0"]
        impl crate::Resettable for TRGM_IN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TRGM_OUT (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgm_out::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgm_out::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trgm_out`]
module"]
    pub type TRGM_OUT = crate::Reg<trgm_out::TRGM_OUT_SPEC>;
    #[doc = "no description available"]
    pub mod trgm_out {
        #[doc = "Register `TRGM_OUT[%s]` reader"]
        pub type R = crate::R<TRGM_OUT_SPEC>;
        #[doc = "Register `TRGM_OUT[%s]` writer"]
        pub type W = crate::W<TRGM_OUT_SPEC>;
        #[doc = "Field `TRGM_OUT` reader - motor_to_opamp0\\[7:0\\]
= trig_mux_out\\[7:0\\]; motor_to_opamp1\\[7:0\\]
= trig_mux_out\\[15:8\\]; motor_to_gtmr0_capt\\[1:0\\]
= trig_mux_out\\[17:16\\]; motor_to_gtmr0_sync = trig_mux_out\\[18\\]; motor_to_gtmr1_capt\\[1:0\\]
= trig_mux_out\\[20:19\\]; motor_to_gtmr1_sync = trig_mux_out\\[21\\]; motor_to_gtmr2_capt\\[1:0\\]
= trig_mux_out\\[23:22\\]; motor_to_gtmr2_sync = trig_mux_out\\[24\\]; motor_to_gtmr3_capt\\[1:0\\]
= trig_mux_out\\[26:25\\]; motor_to_gtmr3_sync = trig_mux_out\\[27\\]; acmp_window\\[1:0\\]
= trig_mux_out\\[29:28\\]; dac0_buf_trigger = trig_mux_out\\[30\\]; dac1_buf_trigger = trig_mux_out\\[31\\]; dac0_step_trigger\\[3:0\\]
= {trig_mux_out\\[24:22\\],trig_mux_out\\[30\\]};//use same buf_trig, and gtmr2 dac1_step_trigger\\[3:0\\]
= {trig_mux_out\\[27:25\\],trig_mux_out\\[31\\]}; //use same buf_trig, and gtmr3"]
        pub type TRGM_OUT_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - motor_to_opamp0\\[7:0\\]
= trig_mux_out\\[7:0\\]; motor_to_opamp1\\[7:0\\]
= trig_mux_out\\[15:8\\]; motor_to_gtmr0_capt\\[1:0\\]
= trig_mux_out\\[17:16\\]; motor_to_gtmr0_sync = trig_mux_out\\[18\\]; motor_to_gtmr1_capt\\[1:0\\]
= trig_mux_out\\[20:19\\]; motor_to_gtmr1_sync = trig_mux_out\\[21\\]; motor_to_gtmr2_capt\\[1:0\\]
= trig_mux_out\\[23:22\\]; motor_to_gtmr2_sync = trig_mux_out\\[24\\]; motor_to_gtmr3_capt\\[1:0\\]
= trig_mux_out\\[26:25\\]; motor_to_gtmr3_sync = trig_mux_out\\[27\\]; acmp_window\\[1:0\\]
= trig_mux_out\\[29:28\\]; dac0_buf_trigger = trig_mux_out\\[30\\]; dac1_buf_trigger = trig_mux_out\\[31\\]; dac0_step_trigger\\[3:0\\]
= {trig_mux_out\\[24:22\\],trig_mux_out\\[30\\]};//use same buf_trig, and gtmr2 dac1_step_trigger\\[3:0\\]
= {trig_mux_out\\[27:25\\],trig_mux_out\\[31\\]}; //use same buf_trig, and gtmr3"]
            #[inline(always)]
            pub fn trgm_out(&self) -> TRGM_OUT_R {
                TRGM_OUT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trgm_out::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trgm_out::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRGM_OUT_SPEC;
        impl crate::RegisterSpec for TRGM_OUT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trgm_out::R`](R) reader structure"]
        impl crate::Readable for TRGM_OUT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trgm_out::W`](W) writer structure"]
        impl crate::Writable for TRGM_OUT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TRGM_OUT[%s]
to value 0"]
        impl crate::Resettable for TRGM_OUT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "USB0"]
pub struct USB0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for USB0 {}
impl USB0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const usb0::RegisterBlock = 0xf300_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const usb0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for USB0 {
    type Target = usb0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for USB0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("USB0").finish()
    }
}
#[doc = "USB0"]
pub mod usb0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        _reserved0: [u8; 0x80],
        gptimer0ld: GPTIMER0LD,
        gptimer0ctrl: GPTIMER0CTRL,
        gptimer1ld: GPTIMER1LD,
        gptimer1ctrl: GPTIMER1CTRL,
        sbuscfg: SBUSCFG,
        _reserved5: [u8; 0xac],
        usbcmd: USBCMD,
        usbsts: USBSTS,
        usbintr: USBINTR,
        frindex: FRINDEX,
        _reserved9: [u8; 0x04],
        _reserved_9_deviceaddr: [u8; 0x04],
        _reserved_10_asynclistaddr: [u8; 0x04],
        _reserved11: [u8; 0x04],
        burstsize: BURSTSIZE,
        txfilltuning: TXFILLTUNING,
        _reserved13: [u8; 0x10],
        endptnak: ENDPTNAK,
        endptnaken: ENDPTNAKEN,
        _reserved15: [u8; 0x04],
        portsc1: PORTSC1,
        _reserved16: [u8; 0x1c],
        otgsc: OTGSC,
        usbmode: USBMODE,
        endptsetupstat: ENDPTSETUPSTAT,
        endptprime: ENDPTPRIME,
        endptflush: ENDPTFLUSH,
        endptstat: ENDPTSTAT,
        endptcomplete: ENDPTCOMPLETE,
        endptctrl: [ENDPTCTRL; 8],
        _reserved24: [u8; 0x20],
        otg_ctrl0: OTG_CTRL0,
        _reserved25: [u8; 0x0c],
        phy_ctrl0: PHY_CTRL0,
        phy_ctrl1: PHY_CTRL1,
        _reserved27: [u8; 0x08],
        top_status: TOP_STATUS,
        phy_status: PHY_STATUS,
    }
    impl RegisterBlock {
        #[doc = "0x80 - General Purpose Timer #0 Load Register"]
        #[inline(always)]
        pub const fn gptimer0ld(&self) -> &GPTIMER0LD {
            &self.gptimer0ld
        }
        #[doc = "0x84 - General Purpose Timer #0 Controller Register"]
        #[inline(always)]
        pub const fn gptimer0ctrl(&self) -> &GPTIMER0CTRL {
            &self.gptimer0ctrl
        }
        #[doc = "0x88 - General Purpose Timer #1 Load Register"]
        #[inline(always)]
        pub const fn gptimer1ld(&self) -> &GPTIMER1LD {
            &self.gptimer1ld
        }
        #[doc = "0x8c - General Purpose Timer #1 Controller Register"]
        #[inline(always)]
        pub const fn gptimer1ctrl(&self) -> &GPTIMER1CTRL {
            &self.gptimer1ctrl
        }
        #[doc = "0x90 - System Bus Config Register"]
        #[inline(always)]
        pub const fn sbuscfg(&self) -> &SBUSCFG {
            &self.sbuscfg
        }
        #[doc = "0x140 - USB Command Register"]
        #[inline(always)]
        pub const fn usbcmd(&self) -> &USBCMD {
            &self.usbcmd
        }
        #[doc = "0x144 - USB Status Register"]
        #[inline(always)]
        pub const fn usbsts(&self) -> &USBSTS {
            &self.usbsts
        }
        #[doc = "0x148 - Interrupt Enable Register"]
        #[inline(always)]
        pub const fn usbintr(&self) -> &USBINTR {
            &self.usbintr
        }
        #[doc = "0x14c - USB Frame Index Register"]
        #[inline(always)]
        pub const fn frindex(&self) -> &FRINDEX {
            &self.frindex
        }
        #[doc = "0x154 - Frame List Base Address Register"]
        #[inline(always)]
        pub const fn periodiclistbase(&self) -> &PERIODICLISTBASE {
            unsafe { &*(self as *const Self).cast::<u8>().add(340).cast() }
        }
        #[doc = "0x154 - Device Address Register"]
        #[inline(always)]
        pub const fn deviceaddr(&self) -> &DEVICEADDR {
            unsafe { &*(self as *const Self).cast::<u8>().add(340).cast() }
        }
        #[doc = "0x158 - Endpoint List Address Register"]
        #[inline(always)]
        pub const fn endptlistaddr(&self) -> &ENDPTLISTADDR {
            unsafe { &*(self as *const Self).cast::<u8>().add(344).cast() }
        }
        #[doc = "0x158 - Next Asynch. Address Register"]
        #[inline(always)]
        pub const fn asynclistaddr(&self) -> &ASYNCLISTADDR {
            unsafe { &*(self as *const Self).cast::<u8>().add(344).cast() }
        }
        #[doc = "0x160 - Programmable Burst Size Register"]
        #[inline(always)]
        pub const fn burstsize(&self) -> &BURSTSIZE {
            &self.burstsize
        }
        #[doc = "0x164 - TX FIFO Fill Tuning Register"]
        #[inline(always)]
        pub const fn txfilltuning(&self) -> &TXFILLTUNING {
            &self.txfilltuning
        }
        #[doc = "0x178 - Endpoint NAK Register"]
        #[inline(always)]
        pub const fn endptnak(&self) -> &ENDPTNAK {
            &self.endptnak
        }
        #[doc = "0x17c - Endpoint NAK Enable Register"]
        #[inline(always)]
        pub const fn endptnaken(&self) -> &ENDPTNAKEN {
            &self.endptnaken
        }
        #[doc = "0x184 - Port Status &amp; Control"]
        #[inline(always)]
        pub const fn portsc1(&self) -> &PORTSC1 {
            &self.portsc1
        }
        #[doc = "0x1a4 - On-The-Go Status &amp; control Register"]
        #[inline(always)]
        pub const fn otgsc(&self) -> &OTGSC {
            &self.otgsc
        }
        #[doc = "0x1a8 - USB Device Mode Register"]
        #[inline(always)]
        pub const fn usbmode(&self) -> &USBMODE {
            &self.usbmode
        }
        #[doc = "0x1ac - Endpoint Setup Status Register"]
        #[inline(always)]
        pub const fn endptsetupstat(&self) -> &ENDPTSETUPSTAT {
            &self.endptsetupstat
        }
        #[doc = "0x1b0 - Endpoint Prime Register"]
        #[inline(always)]
        pub const fn endptprime(&self) -> &ENDPTPRIME {
            &self.endptprime
        }
        #[doc = "0x1b4 - Endpoint Flush Register"]
        #[inline(always)]
        pub const fn endptflush(&self) -> &ENDPTFLUSH {
            &self.endptflush
        }
        #[doc = "0x1b8 - Endpoint Status Register"]
        #[inline(always)]
        pub const fn endptstat(&self) -> &ENDPTSTAT {
            &self.endptstat
        }
        #[doc = "0x1bc - Endpoint Complete Register"]
        #[inline(always)]
        pub const fn endptcomplete(&self) -> &ENDPTCOMPLETE {
            &self.endptcomplete
        }
        #[doc = "0x1c0..0x1e0 - no description available"]
        #[inline(always)]
        pub const fn endptctrl(&self, n: usize) -> &ENDPTCTRL {
            &self.endptctrl[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1c0..0x1e0 - no description available"]
        #[inline(always)]
        pub fn endptctrl_iter(&self) -> impl Iterator<Item = &ENDPTCTRL> {
            self.endptctrl.iter()
        }
        #[doc = "0x1c0 - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl0(&self) -> &ENDPTCTRL {
            self.endptctrl(0)
        }
        #[doc = "0x1c4 - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl1(&self) -> &ENDPTCTRL {
            self.endptctrl(1)
        }
        #[doc = "0x1c8 - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl2(&self) -> &ENDPTCTRL {
            self.endptctrl(2)
        }
        #[doc = "0x1cc - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl3(&self) -> &ENDPTCTRL {
            self.endptctrl(3)
        }
        #[doc = "0x1d0 - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl4(&self) -> &ENDPTCTRL {
            self.endptctrl(4)
        }
        #[doc = "0x1d4 - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl5(&self) -> &ENDPTCTRL {
            self.endptctrl(5)
        }
        #[doc = "0x1d8 - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl6(&self) -> &ENDPTCTRL {
            self.endptctrl(6)
        }
        #[doc = "0x1dc - no description available"]
        #[inline(always)]
        pub const fn endptctrlendptctrl7(&self) -> &ENDPTCTRL {
            self.endptctrl(7)
        }
        #[doc = "0x200 - No description avaiable"]
        #[inline(always)]
        pub const fn otg_ctrl0(&self) -> &OTG_CTRL0 {
            &self.otg_ctrl0
        }
        #[doc = "0x210 - No description avaiable"]
        #[inline(always)]
        pub const fn phy_ctrl0(&self) -> &PHY_CTRL0 {
            &self.phy_ctrl0
        }
        #[doc = "0x214 - No description avaiable"]
        #[inline(always)]
        pub const fn phy_ctrl1(&self) -> &PHY_CTRL1 {
            &self.phy_ctrl1
        }
        #[doc = "0x220 - No description avaiable"]
        #[inline(always)]
        pub const fn top_status(&self) -> &TOP_STATUS {
            &self.top_status
        }
        #[doc = "0x224 - No description avaiable"]
        #[inline(always)]
        pub const fn phy_status(&self) -> &PHY_STATUS {
            &self.phy_status
        }
    }
    #[doc = "GPTIMER0LD (rw) register accessor: General Purpose Timer #0 Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer0ld::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer0ld::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer0ld`]
module"]
    pub type GPTIMER0LD = crate::Reg<gptimer0ld::GPTIMER0LD_SPEC>;
    #[doc = "General Purpose Timer #0 Load Register"]
    pub mod gptimer0ld {
        #[doc = "Register `GPTIMER0LD` reader"]
        pub type R = crate::R<GPTIMER0LD_SPEC>;
        #[doc = "Register `GPTIMER0LD` writer"]
        pub type W = crate::W<GPTIMER0LD_SPEC>;
        #[doc = "Field `GPTLD` reader - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
        pub type GPTLD_R = crate::FieldReader<u32>;
        #[doc = "Field `GPTLD` writer - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
        pub type GPTLD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 0:23 - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
            #[inline(always)]
            pub fn gptld(&self) -> GPTLD_R {
                GPTLD_R::new(self.bits & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
            #[inline(always)]
            #[must_use]
            pub fn gptld(&mut self) -> GPTLD_W<GPTIMER0LD_SPEC> {
                GPTLD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "General Purpose Timer #0 Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer0ld::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer0ld::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GPTIMER0LD_SPEC;
        impl crate::RegisterSpec for GPTIMER0LD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gptimer0ld::R`](R) reader structure"]
        impl crate::Readable for GPTIMER0LD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gptimer0ld::W`](W) writer structure"]
        impl crate::Writable for GPTIMER0LD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GPTIMER0LD to value 0"]
        impl crate::Resettable for GPTIMER0LD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GPTIMER0CTRL (rw) register accessor: General Purpose Timer #0 Controller Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer0ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer0ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer0ctrl`]
module"]
    pub type GPTIMER0CTRL = crate::Reg<gptimer0ctrl::GPTIMER0CTRL_SPEC>;
    #[doc = "General Purpose Timer #0 Controller Register"]
    pub mod gptimer0ctrl {
        #[doc = "Register `GPTIMER0CTRL` reader"]
        pub type R = crate::R<GPTIMER0CTRL_SPEC>;
        #[doc = "Register `GPTIMER0CTRL` writer"]
        pub type W = crate::W<GPTIMER0CTRL_SPEC>;
        #[doc = "Field `GPTCNT` reader - GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer."]
        pub type GPTCNT_R = crate::FieldReader<u32>;
        #[doc = "Field `GPTMODE` reader - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
        pub type GPTMODE_R = crate::BitReader;
        #[doc = "Field `GPTMODE` writer - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
        pub type GPTMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GPTRST` writer - GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in n_GPTIMER0LD"]
        pub type GPTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GPTRUN` reader - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
        pub type GPTRUN_R = crate::BitReader;
        #[doc = "Field `GPTRUN` writer - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
        pub type GPTRUN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:23 - GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer."]
            #[inline(always)]
            pub fn gptcnt(&self) -> GPTCNT_R {
                GPTCNT_R::new(self.bits & 0x00ff_ffff)
            }
            #[doc = "Bit 24 - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
            #[inline(always)]
            pub fn gptmode(&self) -> GPTMODE_R {
                GPTMODE_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 31 - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
            #[inline(always)]
            pub fn gptrun(&self) -> GPTRUN_R {
                GPTRUN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 24 - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
            #[inline(always)]
            #[must_use]
            pub fn gptmode(&mut self) -> GPTMODE_W<GPTIMER0CTRL_SPEC> {
                GPTMODE_W::new(self, 24)
            }
            #[doc = "Bit 30 - GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in n_GPTIMER0LD"]
            #[inline(always)]
            #[must_use]
            pub fn gptrst(&mut self) -> GPTRST_W<GPTIMER0CTRL_SPEC> {
                GPTRST_W::new(self, 30)
            }
            #[doc = "Bit 31 - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
            #[inline(always)]
            #[must_use]
            pub fn gptrun(&mut self) -> GPTRUN_W<GPTIMER0CTRL_SPEC> {
                GPTRUN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "General Purpose Timer #0 Controller Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer0ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer0ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GPTIMER0CTRL_SPEC;
        impl crate::RegisterSpec for GPTIMER0CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gptimer0ctrl::R`](R) reader structure"]
        impl crate::Readable for GPTIMER0CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gptimer0ctrl::W`](W) writer structure"]
        impl crate::Writable for GPTIMER0CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GPTIMER0CTRL to value 0"]
        impl crate::Resettable for GPTIMER0CTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GPTIMER1LD (rw) register accessor: General Purpose Timer #1 Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer1ld::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer1ld::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer1ld`]
module"]
    pub type GPTIMER1LD = crate::Reg<gptimer1ld::GPTIMER1LD_SPEC>;
    #[doc = "General Purpose Timer #1 Load Register"]
    pub mod gptimer1ld {
        #[doc = "Register `GPTIMER1LD` reader"]
        pub type R = crate::R<GPTIMER1LD_SPEC>;
        #[doc = "Register `GPTIMER1LD` writer"]
        pub type W = crate::W<GPTIMER1LD_SPEC>;
        #[doc = "Field `GPTLD` reader - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
        pub type GPTLD_R = crate::FieldReader<u32>;
        #[doc = "Field `GPTLD` writer - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
        pub type GPTLD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
        impl R {
            #[doc = "Bits 0:23 - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
            #[inline(always)]
            pub fn gptld(&self) -> GPTLD_R {
                GPTLD_R::new(self.bits & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:23 - GPTLD General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. This value represents the time in microseconds minus 1 for the timer duration. Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. NOTE: Max value is 0xFFFFFF or 16.777215 seconds."]
            #[inline(always)]
            #[must_use]
            pub fn gptld(&mut self) -> GPTLD_W<GPTIMER1LD_SPEC> {
                GPTLD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "General Purpose Timer #1 Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer1ld::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer1ld::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GPTIMER1LD_SPEC;
        impl crate::RegisterSpec for GPTIMER1LD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gptimer1ld::R`](R) reader structure"]
        impl crate::Readable for GPTIMER1LD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gptimer1ld::W`](W) writer structure"]
        impl crate::Writable for GPTIMER1LD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GPTIMER1LD to value 0"]
        impl crate::Resettable for GPTIMER1LD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "GPTIMER1CTRL (rw) register accessor: General Purpose Timer #1 Controller Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer1ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer1ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gptimer1ctrl`]
module"]
    pub type GPTIMER1CTRL = crate::Reg<gptimer1ctrl::GPTIMER1CTRL_SPEC>;
    #[doc = "General Purpose Timer #1 Controller Register"]
    pub mod gptimer1ctrl {
        #[doc = "Register `GPTIMER1CTRL` reader"]
        pub type R = crate::R<GPTIMER1CTRL_SPEC>;
        #[doc = "Register `GPTIMER1CTRL` writer"]
        pub type W = crate::W<GPTIMER1CTRL_SPEC>;
        #[doc = "Field `GPTCNT` reader - GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer."]
        pub type GPTCNT_R = crate::FieldReader<u32>;
        #[doc = "Field `GPTMODE` reader - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
        pub type GPTMODE_R = crate::BitReader;
        #[doc = "Field `GPTMODE` writer - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
        pub type GPTMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GPTRST` writer - GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD"]
        pub type GPTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GPTRUN` reader - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
        pub type GPTRUN_R = crate::BitReader;
        #[doc = "Field `GPTRUN` writer - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
        pub type GPTRUN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:23 - GPTCNT General Purpose Timer Counter. This field is the count value of the countdown timer."]
            #[inline(always)]
            pub fn gptcnt(&self) -> GPTCNT_R {
                GPTCNT_R::new(self.bits & 0x00ff_ffff)
            }
            #[doc = "Bit 24 - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
            #[inline(always)]
            pub fn gptmode(&self) -> GPTMODE_R {
                GPTMODE_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 31 - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
            #[inline(always)]
            pub fn gptrun(&self) -> GPTRUN_R {
                GPTRUN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 24 - GPTMODE General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again. 0 - One Shot Mode 1 - Repeat Mode"]
            #[inline(always)]
            #[must_use]
            pub fn gptmode(&mut self) -> GPTMODE_W<GPTIMER1CTRL_SPEC> {
                GPTMODE_W::new(self, 24)
            }
            #[doc = "Bit 30 - GPTRST General Purpose Timer Reset 0 - No action 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD"]
            #[inline(always)]
            #[must_use]
            pub fn gptrst(&mut self) -> GPTRST_W<GPTIMER1CTRL_SPEC> {
                GPTRST_W::new(self, 30)
            }
            #[doc = "Bit 31 - GPTRUN General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. 0 - Stop counting 1 - Run"]
            #[inline(always)]
            #[must_use]
            pub fn gptrun(&mut self) -> GPTRUN_W<GPTIMER1CTRL_SPEC> {
                GPTRUN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "General Purpose Timer #1 Controller Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gptimer1ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gptimer1ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GPTIMER1CTRL_SPEC;
        impl crate::RegisterSpec for GPTIMER1CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`gptimer1ctrl::R`](R) reader structure"]
        impl crate::Readable for GPTIMER1CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`gptimer1ctrl::W`](W) writer structure"]
        impl crate::Writable for GPTIMER1CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets GPTIMER1CTRL to value 0"]
        impl crate::Resettable for GPTIMER1CTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SBUSCFG (rw) register accessor: System Bus Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbuscfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbuscfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sbuscfg`]
module"]
    pub type SBUSCFG = crate::Reg<sbuscfg::SBUSCFG_SPEC>;
    #[doc = "System Bus Config Register"]
    pub mod sbuscfg {
        #[doc = "Register `SBUSCFG` reader"]
        pub type R = crate::R<SBUSCFG_SPEC>;
        #[doc = "Register `SBUSCFG` writer"]
        pub type W = crate::W<SBUSCFG_SPEC>;
        #[doc = "Field `AHBBRST` reader - AHBBRST AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority). NOTE: This register overrides n_BURSTSIZE register when its value is not zero. 000 - Incremental burst of unspecified length only 001 - INCR4 burst, then single transfer 010 - INCR8 burst, INCR4 burst, then single transfer 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 100 - Reserved, don't use 101 - INCR4 burst, then incremental burst of unspecified length 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length"]
        pub type AHBBRST_R = crate::FieldReader;
        #[doc = "Field `AHBBRST` writer - AHBBRST AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority). NOTE: This register overrides n_BURSTSIZE register when its value is not zero. 000 - Incremental burst of unspecified length only 001 - INCR4 burst, then single transfer 010 - INCR8 burst, INCR4 burst, then single transfer 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 100 - Reserved, don't use 101 - INCR4 burst, then incremental burst of unspecified length 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length"]
        pub type AHBBRST_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:2 - AHBBRST AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority). NOTE: This register overrides n_BURSTSIZE register when its value is not zero. 000 - Incremental burst of unspecified length only 001 - INCR4 burst, then single transfer 010 - INCR8 burst, INCR4 burst, then single transfer 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 100 - Reserved, don't use 101 - INCR4 burst, then incremental burst of unspecified length 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length"]
            #[inline(always)]
            pub fn ahbbrst(&self) -> AHBBRST_R {
                AHBBRST_R::new((self.bits & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - AHBBRST AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority). NOTE: This register overrides n_BURSTSIZE register when its value is not zero. 000 - Incremental burst of unspecified length only 001 - INCR4 burst, then single transfer 010 - INCR8 burst, INCR4 burst, then single transfer 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer 100 - Reserved, don't use 101 - INCR4 burst, then incremental burst of unspecified length 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length"]
            #[inline(always)]
            #[must_use]
            pub fn ahbbrst(&mut self) -> AHBBRST_W<SBUSCFG_SPEC> {
                AHBBRST_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "System Bus Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sbuscfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sbuscfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SBUSCFG_SPEC;
        impl crate::RegisterSpec for SBUSCFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sbuscfg::R`](R) reader structure"]
        impl crate::Readable for SBUSCFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sbuscfg::W`](W) writer structure"]
        impl crate::Writable for SBUSCFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SBUSCFG to value 0"]
        impl crate::Resettable for SBUSCFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "USBCMD (rw) register accessor: USB Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbcmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbcmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbcmd`]
module"]
    pub type USBCMD = crate::Reg<usbcmd::USBCMD_SPEC>;
    #[doc = "USB Command Register"]
    pub mod usbcmd {
        #[doc = "Register `USBCMD` reader"]
        pub type R = crate::R<USBCMD_SPEC>;
        #[doc = "Register `USBCMD` writer"]
        pub type W = crate::W<USBCMD_SPEC>;
        #[doc = "Field `RS` reader - RS Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. Host operation mode: When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). Device operation mode: Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event."]
        pub type RS_R = crate::BitReader;
        #[doc = "Field `RS` writer - RS Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. Host operation mode: When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). Device operation mode: Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event."]
        pub type RS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RST` reader - RST Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Host operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Device operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
        pub type RST_R = crate::BitReader;
        #[doc = "Field `RST` writer - RST Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Host operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Device operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
        pub type RST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FS_1` reader - FS_1 See description at bit 15"]
        pub type FS_1_R = crate::FieldReader;
        #[doc = "Field `FS_1` writer - FS_1 See description at bit 15"]
        pub type FS_1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `PSE` reader - PSE Periodic Schedule Enable- Read/Write. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Periodic Schedule 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule."]
        pub type PSE_R = crate::BitReader;
        #[doc = "Field `PSE` writer - PSE Periodic Schedule Enable- Read/Write. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Periodic Schedule 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule."]
        pub type PSE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASE` reader - ASE Asynchronous Schedule Enable - Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Asynchronous Schedule. 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule."]
        pub type ASE_R = crate::BitReader;
        #[doc = "Field `ASE` writer - ASE Asynchronous Schedule Enable - Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Asynchronous Schedule. 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule."]
        pub type ASE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IAA` reader - IAA Interrupt on Async Advance Doorbell - Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results."]
        pub type IAA_R = crate::BitReader;
        #[doc = "Field `IAA` writer - IAA Interrupt on Async Advance Doorbell - Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results."]
        pub type IAA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASP` reader - ASP Asynchronous Schedule Park Mode Count - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. This field is set to 3h in all controller core."]
        pub type ASP_R = crate::FieldReader;
        #[doc = "Field `ASP` writer - ASP Asynchronous Schedule Park Mode Count - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. This field is set to 3h in all controller core."]
        pub type ASP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ASPE` reader - ASPE Asynchronous Schedule Park Mode Enable - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. NOTE: ASPE bit reset value: '0b' for OTG controller ."]
        pub type ASPE_R = crate::BitReader;
        #[doc = "Field `ASPE` writer - ASPE Asynchronous Schedule Park Mode Enable - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. NOTE: ASPE bit reset value: '0b' for OTG controller ."]
        pub type ASPE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SUTW` reader - SUTW Setup TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. This bit would also be cleared by hardware when a hazard detected."]
        pub type SUTW_R = crate::BitReader;
        #[doc = "Field `SUTW` writer - SUTW Setup TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. This bit would also be cleared by hardware when a hazard detected."]
        pub type SUTW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ATDTW` reader - ATDTW Add dTD TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
        pub type ATDTW_R = crate::BitReader;
        #[doc = "Field `ATDTW` writer - ATDTW Add dTD TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
        pub type ATDTW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FS_2` reader - FS_2 Frame List Size - (Read/Write or Read Only). \\[host mode only\\]
This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. NOTE: This field is made up from USBCMD bits 15, 3 and 2. Value Meaning 0b000 - 1024 elements (4096 bytes) Default value 0b001 - 512 elements (2048 bytes) 0b010 - 256 elements (1024 bytes) 0b011 - 128 elements (512 bytes) 0b100 - 64 elements (256 bytes) 0b101 - 32 elements (128 bytes) 0b110 - 16 elements (64 bytes) 0b111 - 8 elements (32 bytes)"]
        pub type FS_2_R = crate::BitReader;
        #[doc = "Field `FS_2` writer - FS_2 Frame List Size - (Read/Write or Read Only). \\[host mode only\\]
This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. NOTE: This field is made up from USBCMD bits 15, 3 and 2. Value Meaning 0b000 - 1024 elements (4096 bytes) Default value 0b001 - 512 elements (2048 bytes) 0b010 - 256 elements (1024 bytes) 0b011 - 128 elements (512 bytes) 0b100 - 64 elements (256 bytes) 0b101 - 32 elements (128 bytes) 0b110 - 16 elements (64 bytes) 0b111 - 8 elements (32 bytes)"]
        pub type FS_2_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ITC` reader - ITC Interrupt Threshold Control -Read/Write. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. Value Maximum Interrupt Interval 00000000 - Immediate (no threshold) 00000001 - 1 micro-frame 00000010 - 2 micro-frames 00000100 - 4 micro-frames 00001000 - 8 micro-frames 00010000 - 16 micro-frames 00100000 - 32 micro-frames 01000000 - 64 micro-frames"]
        pub type ITC_R = crate::FieldReader;
        #[doc = "Field `ITC` writer - ITC Interrupt Threshold Control -Read/Write. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. Value Maximum Interrupt Interval 00000000 - Immediate (no threshold) 00000001 - 1 micro-frame 00000010 - 2 micro-frames 00000100 - 4 micro-frames 00001000 - 8 micro-frames 00010000 - 16 micro-frames 00100000 - 32 micro-frames 01000000 - 64 micro-frames"]
        pub type ITC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bit 0 - RS Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. Host operation mode: When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). Device operation mode: Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event."]
            #[inline(always)]
            pub fn rs(&self) -> RS_R {
                RS_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - RST Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Host operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Device operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
            #[inline(always)]
            pub fn rst(&self) -> RST_R {
                RST_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 2:3 - FS_1 See description at bit 15"]
            #[inline(always)]
            pub fn fs_1(&self) -> FS_1_R {
                FS_1_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bit 4 - PSE Periodic Schedule Enable- Read/Write. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Periodic Schedule 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule."]
            #[inline(always)]
            pub fn pse(&self) -> PSE_R {
                PSE_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - ASE Asynchronous Schedule Enable - Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Asynchronous Schedule. 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule."]
            #[inline(always)]
            pub fn ase(&self) -> ASE_R {
                ASE_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - IAA Interrupt on Async Advance Doorbell - Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results."]
            #[inline(always)]
            pub fn iaa(&self) -> IAA_R {
                IAA_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bits 8:9 - ASP Asynchronous Schedule Park Mode Count - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. This field is set to 3h in all controller core."]
            #[inline(always)]
            pub fn asp(&self) -> ASP_R {
                ASP_R::new(((self.bits >> 8) & 3) as u8)
            }
            #[doc = "Bit 11 - ASPE Asynchronous Schedule Park Mode Enable - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. NOTE: ASPE bit reset value: '0b' for OTG controller ."]
            #[inline(always)]
            pub fn aspe(&self) -> ASPE_R {
                ASPE_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 13 - SUTW Setup TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. This bit would also be cleared by hardware when a hazard detected."]
            #[inline(always)]
            pub fn sutw(&self) -> SUTW_R {
                SUTW_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - ATDTW Add dTD TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
            #[inline(always)]
            pub fn atdtw(&self) -> ATDTW_R {
                ATDTW_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - FS_2 Frame List Size - (Read/Write or Read Only). \\[host mode only\\]
This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. NOTE: This field is made up from USBCMD bits 15, 3 and 2. Value Meaning 0b000 - 1024 elements (4096 bytes) Default value 0b001 - 512 elements (2048 bytes) 0b010 - 256 elements (1024 bytes) 0b011 - 128 elements (512 bytes) 0b100 - 64 elements (256 bytes) 0b101 - 32 elements (128 bytes) 0b110 - 16 elements (64 bytes) 0b111 - 8 elements (32 bytes)"]
            #[inline(always)]
            pub fn fs_2(&self) -> FS_2_R {
                FS_2_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bits 16:23 - ITC Interrupt Threshold Control -Read/Write. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. Value Maximum Interrupt Interval 00000000 - Immediate (no threshold) 00000001 - 1 micro-frame 00000010 - 2 micro-frames 00000100 - 4 micro-frames 00001000 - 8 micro-frames 00010000 - 16 micro-frames 00100000 - 32 micro-frames 01000000 - 64 micro-frames"]
            #[inline(always)]
            pub fn itc(&self) -> ITC_R {
                ITC_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - RS Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. Host operation mode: When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). Device operation mode: Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event."]
            #[inline(always)]
            #[must_use]
            pub fn rs(&mut self) -> RS_W<USBCMD_SPEC> {
                RS_W::new(self, 0)
            }
            #[doc = "Bit 1 - RST Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. Host operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior. Device operation mode: When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0."]
            #[inline(always)]
            #[must_use]
            pub fn rst(&mut self) -> RST_W<USBCMD_SPEC> {
                RST_W::new(self, 1)
            }
            #[doc = "Bits 2:3 - FS_1 See description at bit 15"]
            #[inline(always)]
            #[must_use]
            pub fn fs_1(&mut self) -> FS_1_W<USBCMD_SPEC> {
                FS_1_W::new(self, 2)
            }
            #[doc = "Bit 4 - PSE Periodic Schedule Enable- Read/Write. Default 0b. This bit controls whether the host controller skips processing the Periodic Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Periodic Schedule 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule."]
            #[inline(always)]
            #[must_use]
            pub fn pse(&mut self) -> PSE_W<USBCMD_SPEC> {
                PSE_W::new(self, 4)
            }
            #[doc = "Bit 5 - ASE Asynchronous Schedule Enable - Read/Write. Default 0b. This bit controls whether the host controller skips processing the Asynchronous Schedule. Only the host controller uses this bit. Values Meaning 0 - Do not process the Asynchronous Schedule. 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule."]
            #[inline(always)]
            #[must_use]
            pub fn ase(&mut self) -> ASE_W<USBCMD_SPEC> {
                ASE_W::new(self, 5)
            }
            #[doc = "Bit 6 - IAA Interrupt on Async Advance Doorbell - Read/Write. This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule states, it sets the Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results."]
            #[inline(always)]
            #[must_use]
            pub fn iaa(&mut self) -> IAA_W<USBCMD_SPEC> {
                IAA_W::new(self, 6)
            }
            #[doc = "Bits 8:9 - ASP Asynchronous Schedule Park Mode Count - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. This field is set to 3h in all controller core."]
            #[inline(always)]
            #[must_use]
            pub fn asp(&mut self) -> ASP_W<USBCMD_SPEC> {
                ASP_W::new(self, 8)
            }
            #[doc = "Bit 11 - ASPE Asynchronous Schedule Park Mode Enable - Read/Write. If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. NOTE: ASPE bit reset value: '0b' for OTG controller ."]
            #[inline(always)]
            #[must_use]
            pub fn aspe(&mut self) -> ASPE_W<USBCMD_SPEC> {
                ASPE_W::new(self, 11)
            }
            #[doc = "Bit 13 - SUTW Setup TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then there is a hazard when new setup data arrives while the DCD is copying the setup data payload from the QH for a previous setup packet. This bit is set and cleared by software. This bit would also be cleared by hardware when a hazard detected."]
            #[inline(always)]
            #[must_use]
            pub fn sutw(&mut self) -> SUTW_W<USBCMD_SPEC> {
                SUTW_W::new(self, 13)
            }
            #[doc = "Bit 14 - ATDTW Add dTD TripWire - Read/Write. \\[device mode only\\]
This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's linked list. This bit is set and cleared by software. This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD to a primed endpoint may go unrecognized."]
            #[inline(always)]
            #[must_use]
            pub fn atdtw(&mut self) -> ATDTW_W<USBCMD_SPEC> {
                ATDTW_W::new(self, 14)
            }
            #[doc = "Bit 15 - FS_2 Frame List Size - (Read/Write or Read Only). \\[host mode only\\]
This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. NOTE: This field is made up from USBCMD bits 15, 3 and 2. Value Meaning 0b000 - 1024 elements (4096 bytes) Default value 0b001 - 512 elements (2048 bytes) 0b010 - 256 elements (1024 bytes) 0b011 - 128 elements (512 bytes) 0b100 - 64 elements (256 bytes) 0b101 - 32 elements (128 bytes) 0b110 - 16 elements (64 bytes) 0b111 - 8 elements (32 bytes)"]
            #[inline(always)]
            #[must_use]
            pub fn fs_2(&mut self) -> FS_2_W<USBCMD_SPEC> {
                FS_2_W::new(self, 15)
            }
            #[doc = "Bits 16:23 - ITC Interrupt Threshold Control -Read/Write. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below. Value Maximum Interrupt Interval 00000000 - Immediate (no threshold) 00000001 - 1 micro-frame 00000010 - 2 micro-frames 00000100 - 4 micro-frames 00001000 - 8 micro-frames 00010000 - 16 micro-frames 00100000 - 32 micro-frames 01000000 - 64 micro-frames"]
            #[inline(always)]
            #[must_use]
            pub fn itc(&mut self) -> ITC_W<USBCMD_SPEC> {
                ITC_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "USB Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbcmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbcmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct USBCMD_SPEC;
        impl crate::RegisterSpec for USBCMD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`usbcmd::R`](R) reader structure"]
        impl crate::Readable for USBCMD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`usbcmd::W`](W) writer structure"]
        impl crate::Writable for USBCMD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets USBCMD to value 0x0008_0000"]
        impl crate::Resettable for USBCMD_SPEC {
            const RESET_VALUE: u32 = 0x0008_0000;
        }
    }
    #[doc = "USBSTS (rw) register accessor: USB Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbsts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbsts`]
module"]
    pub type USBSTS = crate::Reg<usbsts::USBSTS_SPEC>;
    #[doc = "USB Status Register"]
    pub mod usbsts {
        #[doc = "Register `USBSTS` reader"]
        pub type R = crate::R<USBSTS_SPEC>;
        #[doc = "Register `USBSTS` writer"]
        pub type W = crate::W<USBSTS_SPEC>;
        #[doc = "Field `UI` reader - UI USB Interrupt (USBINT) - R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
        pub type UI_R = crate::BitReader;
        #[doc = "Field `UI` writer - UI USB Interrupt (USBINT) - R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
        pub type UI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UEI` reader - UEI USB Error Interrupt (USBERRINT) - R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
        pub type UEI_R = crate::BitReader;
        #[doc = "Field `UEI` writer - UEI USB Error Interrupt (USBERRINT) - R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
        pub type UEI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PCI` reader - PCI Port Change Detect - R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively."]
        pub type PCI_R = crate::BitReader;
        #[doc = "Field `PCI` writer - PCI Port Change Detect - R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively."]
        pub type PCI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FRI` reader - FRI Frame List Rollover - R/WC. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\]
toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX \\[12\\]
toggles. Only used in host operation mode."]
        pub type FRI_R = crate::BitReader;
        #[doc = "Field `FRI` writer - FRI Frame List Rollover - R/WC. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\]
toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX \\[12\\]
toggles. Only used in host operation mode."]
        pub type FRI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEI` reader - System Error – RWC. Default = 0b. In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP\\[1:0\\]=ERROR)"]
        pub type SEI_R = crate::BitReader;
        #[doc = "Field `SEI` writer - System Error – RWC. Default = 0b. In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP\\[1:0\\]=ERROR)"]
        pub type SEI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AAI` reader - AAI Interrupt on Async Advance - R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. Only used in host operation mode."]
        pub type AAI_R = crate::BitReader;
        #[doc = "Field `AAI` writer - AAI Interrupt on Async Advance - R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. Only used in host operation mode."]
        pub type AAI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `URI` reader - URI USB Reset Received - R/WC. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used in device operation mode."]
        pub type URI_R = crate::BitReader;
        #[doc = "Field `URI` writer - URI USB Reset Received - R/WC. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used in device operation mode."]
        pub type URI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SRI` reader - SRI SOF Received - R/WC. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it."]
        pub type SRI_R = crate::BitReader;
        #[doc = "Field `SRI` writer - SRI SOF Received - R/WC. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it."]
        pub type SRI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLI` reader - SLI DCSuspend - R/WC. When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used in device operation mode."]
        pub type SLI_R = crate::BitReader;
        #[doc = "Field `SLI` writer - SLI DCSuspend - R/WC. When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used in device operation mode."]
        pub type SLI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HCH` reader - HCH HCHaIted - Read Only. This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). Only used in the host operation mode. Default value is '0b' for OTG core . This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE register. NOTE: HCH bit reset value: '0b' for OTG controller core ."]
        pub type HCH_R = crate::BitReader;
        #[doc = "Field `RCL` reader - RCL Reclamation - Read Only. This is a read-only status bit used to detect an empty asynchronous schedule. Only used in the host operation mode."]
        pub type RCL_R = crate::BitReader;
        #[doc = "Field `PS` reader - PS Periodic Schedule Status - Read Only. This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Only used in the host operation mode."]
        pub type PS_R = crate::BitReader;
        #[doc = "Field `AS` reader - AS Asynchronous Schedule Status - Read Only. This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used in the host operation mode."]
        pub type AS_R = crate::BitReader;
        #[doc = "Field `NAKI` reader - NAKI NAK Interrupt Bit--RO. This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when all Enabled TX/RX Endpoint NAK bits are cleared."]
        pub type NAKI_R = crate::BitReader;
        #[doc = "Field `UAI` reader - USB Host Asynchronous Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero"]
        pub type UAI_R = crate::BitReader;
        #[doc = "Field `UAI` writer - USB Host Asynchronous Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero"]
        pub type UAI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UPI` reader - USB Host Periodic Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero."]
        pub type UPI_R = crate::BitReader;
        #[doc = "Field `UPI` writer - USB Host Periodic Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero."]
        pub type UPI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TI0` reader - TI0 General Purpose Timer Interrupt 0(GPTINT0)--R/WC. This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this bit clears it."]
        pub type TI0_R = crate::BitReader;
        #[doc = "Field `TI0` writer - TI0 General Purpose Timer Interrupt 0(GPTINT0)--R/WC. This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this bit clears it."]
        pub type TI0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TI1` reader - TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC. This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this bit will clear it."]
        pub type TI1_R = crate::BitReader;
        #[doc = "Field `TI1` writer - TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC. This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this bit will clear it."]
        pub type TI1_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - UI USB Interrupt (USBINT) - R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
            #[inline(always)]
            pub fn ui(&self) -> UI_R {
                UI_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - UEI USB Error Interrupt (USBERRINT) - R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
            #[inline(always)]
            pub fn uei(&self) -> UEI_R {
                UEI_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - PCI Port Change Detect - R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively."]
            #[inline(always)]
            pub fn pci(&self) -> PCI_R {
                PCI_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - FRI Frame List Rollover - R/WC. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\]
toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX \\[12\\]
toggles. Only used in host operation mode."]
            #[inline(always)]
            pub fn fri(&self) -> FRI_R {
                FRI_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - System Error – RWC. Default = 0b. In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP\\[1:0\\]=ERROR)"]
            #[inline(always)]
            pub fn sei(&self) -> SEI_R {
                SEI_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - AAI Interrupt on Async Advance - R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. Only used in host operation mode."]
            #[inline(always)]
            pub fn aai(&self) -> AAI_R {
                AAI_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - URI USB Reset Received - R/WC. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used in device operation mode."]
            #[inline(always)]
            pub fn uri(&self) -> URI_R {
                URI_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - SRI SOF Received - R/WC. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it."]
            #[inline(always)]
            pub fn sri(&self) -> SRI_R {
                SRI_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - SLI DCSuspend - R/WC. When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used in device operation mode."]
            #[inline(always)]
            pub fn sli(&self) -> SLI_R {
                SLI_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 12 - HCH HCHaIted - Read Only. This bit is a zero whenever the Run/Stop bit is a one. The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, either by software or by the Controller hardware (for example, an internal error). Only used in the host operation mode. Default value is '0b' for OTG core . This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE register. NOTE: HCH bit reset value: '0b' for OTG controller core ."]
            #[inline(always)]
            pub fn hch(&self) -> HCH_R {
                HCH_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - RCL Reclamation - Read Only. This is a read-only status bit used to detect an empty asynchronous schedule. Only used in the host operation mode."]
            #[inline(always)]
            pub fn rcl(&self) -> RCL_R {
                RCL_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - PS Periodic Schedule Status - Read Only. This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). Only used in the host operation mode."]
            #[inline(always)]
            pub fn ps(&self) -> PS_R {
                PS_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 15 - AS Asynchronous Schedule Status - Read Only. This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). Only used in the host operation mode."]
            #[inline(always)]
            pub fn as_(&self) -> AS_R {
                AS_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - NAKI NAK Interrupt Bit--RO. This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when all Enabled TX/RX Endpoint NAK bits are cleared."]
            #[inline(always)]
            pub fn naki(&self) -> NAKI_R {
                NAKI_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 18 - USB Host Asynchronous Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero"]
            #[inline(always)]
            pub fn uai(&self) -> UAI_R {
                UAI_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - USB Host Periodic Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero."]
            #[inline(always)]
            pub fn upi(&self) -> UPI_R {
                UPI_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 24 - TI0 General Purpose Timer Interrupt 0(GPTINT0)--R/WC. This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this bit clears it."]
            #[inline(always)]
            pub fn ti0(&self) -> TI0_R {
                TI0_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC. This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this bit will clear it."]
            #[inline(always)]
            pub fn ti1(&self) -> TI1_R {
                TI1_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - UI USB Interrupt (USBINT) - R/WC. This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when the actual number of bytes received was less than the expected number of bytes."]
            #[inline(always)]
            #[must_use]
            pub fn ui(&mut self) -> UI_W<USBSTS_SPEC> {
                UI_W::new(self, 0)
            }
            #[doc = "Bit 1 - UEI USB Error Interrupt (USBERRINT) - R/WC. When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set."]
            #[inline(always)]
            #[must_use]
            pub fn uei(&mut self) -> UEI_W<USBSTS_SPEC> {
                UEI_W::new(self, 1)
            }
            #[doc = "Bit 2 - PCI Port Change Detect - R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. When the port controller exits the full or high-speed operation states due to Reset or Suspend events, the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively."]
            #[inline(always)]
            #[must_use]
            pub fn pci(&mut self) -> PCI_W<USBSTS_SPEC> {
                PCI_W::new(self, 2)
            }
            #[doc = "Bit 3 - FRI Frame List Rollover - R/WC. The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX \\[13\\]
toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FHINDEX \\[12\\]
toggles. Only used in host operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn fri(&mut self) -> FRI_W<USBSTS_SPEC> {
                FRI_W::new(self, 3)
            }
            #[doc = "Bit 4 - System Error – RWC. Default = 0b. In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP\\[1:0\\]=ERROR)"]
            #[inline(always)]
            #[must_use]
            pub fn sei(&mut self) -> SEI_W<USBSTS_SPEC> {
                SEI_W::new(self, 4)
            }
            #[doc = "Bit 5 - AAI Interrupt on Async Advance - R/WC. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. Only used in host operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn aai(&mut self) -> AAI_W<USBSTS_SPEC> {
                AAI_W::new(self, 5)
            }
            #[doc = "Bit 6 - URI USB Reset Received - R/WC. When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. Software can write a 1 to this bit to clear the USB Reset Received status bit. Only used in device operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn uri(&mut self) -> URI_W<USBSTS_SPEC> {
                URI_W::new(self, 6)
            }
            #[doc = "Bit 7 - SRI SOF Received - R/WC. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. Software writes a 1 to this bit to clear it."]
            #[inline(always)]
            #[must_use]
            pub fn sri(&mut self) -> SRI_W<USBSTS_SPEC> {
                SRI_W::new(self, 7)
            }
            #[doc = "Bit 8 - SLI DCSuspend - R/WC. When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. Only used in device operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn sli(&mut self) -> SLI_W<USBSTS_SPEC> {
                SLI_W::new(self, 8)
            }
            #[doc = "Bit 18 - USB Host Asynchronous Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero"]
            #[inline(always)]
            #[must_use]
            pub fn uai(&mut self) -> UAI_W<USBSTS_SPEC> {
                UAI_W::new(self, 18)
            }
            #[doc = "Bit 19 - USB Host Periodic Interrupt – RWC. Default = 0b. This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. A short packet is when the actual number of bytes received was less than expected. This bit is not used by the device controller and will always be zero."]
            #[inline(always)]
            #[must_use]
            pub fn upi(&mut self) -> UPI_W<USBSTS_SPEC> {
                UPI_W::new(self, 19)
            }
            #[doc = "Bit 24 - TI0 General Purpose Timer Interrupt 0(GPTINT0)--R/WC. This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this bit clears it."]
            #[inline(always)]
            #[must_use]
            pub fn ti0(&mut self) -> TI0_W<USBSTS_SPEC> {
                TI0_W::new(self, 24)
            }
            #[doc = "Bit 25 - TI1 General Purpose Timer Interrupt 1(GPTINT1)--R/WC. This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this bit will clear it."]
            #[inline(always)]
            #[must_use]
            pub fn ti1(&mut self) -> TI1_W<USBSTS_SPEC> {
                TI1_W::new(self, 25)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "USB Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbsts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct USBSTS_SPEC;
        impl crate::RegisterSpec for USBSTS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`usbsts::R`](R) reader structure"]
        impl crate::Readable for USBSTS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`usbsts::W`](W) writer structure"]
        impl crate::Writable for USBSTS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets USBSTS to value 0"]
        impl crate::Resettable for USBSTS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "USBINTR (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbintr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbintr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbintr`]
module"]
    pub type USBINTR = crate::Reg<usbintr::USBINTR_SPEC>;
    #[doc = "Interrupt Enable Register"]
    pub mod usbintr {
        #[doc = "Register `USBINTR` reader"]
        pub type R = crate::R<USBINTR_SPEC>;
        #[doc = "Register `USBINTR` writer"]
        pub type W = crate::W<USBINTR_SPEC>;
        #[doc = "Field `UE` reader - UE USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type UE_R = crate::BitReader;
        #[doc = "Field `UE` writer - UE USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type UE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UEE` reader - UEE USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type UEE_R = crate::BitReader;
        #[doc = "Field `UEE` writer - UEE USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type UEE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PCE` reader - PCE Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type PCE_R = crate::BitReader;
        #[doc = "Field `PCE` writer - PCE Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type PCE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FRE` reader - FRE Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
        pub type FRE_R = crate::BitReader;
        #[doc = "Field `FRE` writer - FRE Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
        pub type FRE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEE` reader - SEE System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
        pub type SEE_R = crate::BitReader;
        #[doc = "Field `SEE` writer - SEE System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
        pub type SEE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AAE` reader - AAE Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
        pub type AAE_R = crate::BitReader;
        #[doc = "Field `AAE` writer - AAE Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
        pub type AAE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `URE` reader - URE USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
        pub type URE_R = crate::BitReader;
        #[doc = "Field `URE` writer - URE USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
        pub type URE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SRE` reader - SRE SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type SRE_R = crate::BitReader;
        #[doc = "Field `SRE` writer - SRE SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type SRE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLE` reader - SLE Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
        pub type SLE_R = crate::BitReader;
        #[doc = "Field `SLE` writer - SLE Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
        pub type SLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NAKE` reader - NAKE NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type NAKE_R = crate::BitReader;
        #[doc = "Field `UAIE` reader - UAIE USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
        pub type UAIE_R = crate::BitReader;
        #[doc = "Field `UAIE` writer - UAIE USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
        pub type UAIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UPIE` reader - UPIE USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
        pub type UPIE_R = crate::BitReader;
        #[doc = "Field `UPIE` writer - UPIE USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
        pub type UPIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIE0` reader - TIE0 General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type TIE0_R = crate::BitReader;
        #[doc = "Field `TIE0` writer - TIE0 General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type TIE0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TIE1` reader - TIE1 General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type TIE1_R = crate::BitReader;
        #[doc = "Field `TIE1` writer - TIE1 General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt."]
        pub type TIE1_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - UE USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            pub fn ue(&self) -> UE_R {
                UE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - UEE USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            pub fn uee(&self) -> UEE_R {
                UEE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - PCE Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            pub fn pce(&self) -> PCE_R {
                PCE_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - FRE Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
            #[inline(always)]
            pub fn fre(&self) -> FRE_R {
                FRE_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - SEE System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
            #[inline(always)]
            pub fn see(&self) -> SEE_R {
                SEE_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - AAE Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
            #[inline(always)]
            pub fn aae(&self) -> AAE_R {
                AAE_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - URE USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
            #[inline(always)]
            pub fn ure(&self) -> URE_R {
                URE_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - SRE SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            pub fn sre(&self) -> SRE_R {
                SRE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - SLE Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
            #[inline(always)]
            pub fn sle(&self) -> SLE_R {
                SLE_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 16 - NAKE NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            pub fn nake(&self) -> NAKE_R {
                NAKE_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 18 - UAIE USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
            #[inline(always)]
            pub fn uaie(&self) -> UAIE_R {
                UAIE_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - UPIE USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
            #[inline(always)]
            pub fn upie(&self) -> UPIE_R {
                UPIE_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 24 - TIE0 General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            pub fn tie0(&self) -> TIE0_R {
                TIE0_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - TIE1 General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            pub fn tie1(&self) -> TIE1_R {
                TIE1_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - UE USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn ue(&mut self) -> UE_W<USBINTR_SPEC> {
                UE_W::new(self, 0)
            }
            #[doc = "Bit 1 - UEE USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn uee(&mut self) -> UEE_W<USBINTR_SPEC> {
                UEE_W::new(self, 1)
            }
            #[doc = "Bit 2 - PCE Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn pce(&mut self) -> PCE_W<USBINTR_SPEC> {
                PCE_W::new(self, 2)
            }
            #[doc = "Bit 3 - FRE Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn fre(&mut self) -> FRE_W<USBINTR_SPEC> {
                FRE_W::new(self, 3)
            }
            #[doc = "Bit 4 - SEE System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn see(&mut self) -> SEE_W<USBINTR_SPEC> {
                SEE_W::new(self, 4)
            }
            #[doc = "Bit 5 - AAE Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in host operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn aae(&mut self) -> AAE_W<USBINTR_SPEC> {
                AAE_W::new(self, 5)
            }
            #[doc = "Bit 6 - URE USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn ure(&mut self) -> URE_W<USBINTR_SPEC> {
                URE_W::new(self, 6)
            }
            #[doc = "Bit 7 - SRE SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn sre(&mut self) -> SRE_W<USBINTR_SPEC> {
                SRE_W::new(self, 7)
            }
            #[doc = "Bit 8 - SLE Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. Only used in device operation mode."]
            #[inline(always)]
            #[must_use]
            pub fn sle(&mut self) -> SLE_W<USBINTR_SPEC> {
                SLE_W::new(self, 8)
            }
            #[doc = "Bit 18 - UAIE USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
            #[inline(always)]
            #[must_use]
            pub fn uaie(&mut self) -> UAIE_W<USBINTR_SPEC> {
                UAIE_W::new(self, 18)
            }
            #[doc = "Bit 19 - UPIE USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold."]
            #[inline(always)]
            #[must_use]
            pub fn upie(&mut self) -> UPIE_W<USBINTR_SPEC> {
                UPIE_W::new(self, 19)
            }
            #[doc = "Bit 24 - TIE0 General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn tie0(&mut self) -> TIE0_W<USBINTR_SPEC> {
                TIE0_W::new(self, 24)
            }
            #[doc = "Bit 25 - TIE1 General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn tie1(&mut self) -> TIE1_W<USBINTR_SPEC> {
                TIE1_W::new(self, 25)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbintr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbintr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct USBINTR_SPEC;
        impl crate::RegisterSpec for USBINTR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`usbintr::R`](R) reader structure"]
        impl crate::Readable for USBINTR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`usbintr::W`](W) writer structure"]
        impl crate::Writable for USBINTR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets USBINTR to value 0"]
        impl crate::Resettable for USBINTR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "FRINDEX (rw) register accessor: USB Frame Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frindex::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frindex::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frindex`]
module"]
    pub type FRINDEX = crate::Reg<frindex::FRINDEX_SPEC>;
    #[doc = "USB Frame Index Register"]
    pub mod frindex {
        #[doc = "Register `FRINDEX` reader"]
        pub type R = crate::R<FRINDEX_SPEC>;
        #[doc = "Register `FRINDEX` writer"]
        pub type W = crate::W<FRINDEX_SPEC>;
        #[doc = "Field `FRINDEX` reader - FRINDEX Frame Index. The value, in this register, increments at the end of each time frame (micro-frame). Bits \\[N: 3\\]
are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. USBCMD \\[Frame List Size\\]
Number Elements N In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. In either mode bits 2:0 indicate the current microframe. The bit field values description below is represented as (Frame List Size) Number Elements N. 00000000000000 - (1024) 12 00000000000001 - (512) 11 00000000000010 - (256) 10 00000000000011 - (128) 9 00000000000100 - (64) 8 00000000000101 - (32) 7 00000000000110 - (16) 6 00000000000111 - (8) 5"]
        pub type FRINDEX_R = crate::FieldReader<u16>;
        #[doc = "Field `FRINDEX` writer - FRINDEX Frame Index. The value, in this register, increments at the end of each time frame (micro-frame). Bits \\[N: 3\\]
are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. USBCMD \\[Frame List Size\\]
Number Elements N In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. In either mode bits 2:0 indicate the current microframe. The bit field values description below is represented as (Frame List Size) Number Elements N. 00000000000000 - (1024) 12 00000000000001 - (512) 11 00000000000010 - (256) 10 00000000000011 - (128) 9 00000000000100 - (64) 8 00000000000101 - (32) 7 00000000000110 - (16) 6 00000000000111 - (8) 5"]
        pub type FRINDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        impl R {
            #[doc = "Bits 0:13 - FRINDEX Frame Index. The value, in this register, increments at the end of each time frame (micro-frame). Bits \\[N: 3\\]
are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. USBCMD \\[Frame List Size\\]
Number Elements N In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. In either mode bits 2:0 indicate the current microframe. The bit field values description below is represented as (Frame List Size) Number Elements N. 00000000000000 - (1024) 12 00000000000001 - (512) 11 00000000000010 - (256) 10 00000000000011 - (128) 9 00000000000100 - (64) 8 00000000000101 - (32) 7 00000000000110 - (16) 6 00000000000111 - (8) 5"]
            #[inline(always)]
            pub fn frindex(&self) -> FRINDEX_R {
                FRINDEX_R::new((self.bits & 0x3fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:13 - FRINDEX Frame Index. The value, in this register, increments at the end of each time frame (micro-frame). Bits \\[N: 3\\]
are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. USBCMD \\[Frame List Size\\]
Number Elements N In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. In either mode bits 2:0 indicate the current microframe. The bit field values description below is represented as (Frame List Size) Number Elements N. 00000000000000 - (1024) 12 00000000000001 - (512) 11 00000000000010 - (256) 10 00000000000011 - (128) 9 00000000000100 - (64) 8 00000000000101 - (32) 7 00000000000110 - (16) 6 00000000000111 - (8) 5"]
            #[inline(always)]
            #[must_use]
            pub fn frindex(&mut self) -> FRINDEX_W<FRINDEX_SPEC> {
                FRINDEX_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "USB Frame Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frindex::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frindex::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FRINDEX_SPEC;
        impl crate::RegisterSpec for FRINDEX_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`frindex::R`](R) reader structure"]
        impl crate::Readable for FRINDEX_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`frindex::W`](W) writer structure"]
        impl crate::Writable for FRINDEX_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FRINDEX to value 0"]
        impl crate::Resettable for FRINDEX_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DEVICEADDR (rw) register accessor: Device Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deviceaddr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deviceaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@deviceaddr`]
module"]
    pub type DEVICEADDR = crate::Reg<deviceaddr::DEVICEADDR_SPEC>;
    #[doc = "Device Address Register"]
    pub mod deviceaddr {
        #[doc = "Register `DEVICEADDR` reader"]
        pub type R = crate::R<DEVICEADDR_SPEC>;
        #[doc = "Register `DEVICEADDR` writer"]
        pub type W = crate::W<DEVICEADDR_SPEC>;
        #[doc = "Field `USBADRA` reader - USBADRA Device Address Advance. Default=0. When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3) Device Reset occurs (USBADR is reset to 0). NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement."]
        pub type USBADRA_R = crate::BitReader;
        #[doc = "Field `USBADRA` writer - USBADRA Device Address Advance. Default=0. When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3) Device Reset occurs (USBADR is reset to 0). NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement."]
        pub type USBADRA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `USBADR` reader - USBADR Device Address. These bits correspond to the USB device address"]
        pub type USBADR_R = crate::FieldReader;
        #[doc = "Field `USBADR` writer - USBADR Device Address. These bits correspond to the USB device address"]
        pub type USBADR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bit 24 - USBADRA Device Address Advance. Default=0. When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3) Device Reset occurs (USBADR is reset to 0). NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement."]
            #[inline(always)]
            pub fn usbadra(&self) -> USBADRA_R {
                USBADRA_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bits 25:31 - USBADR Device Address. These bits correspond to the USB device address"]
            #[inline(always)]
            pub fn usbadr(&self) -> USBADR_R {
                USBADR_R::new(((self.bits >> 25) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bit 24 - USBADRA Device Address Advance. Default=0. When this bit is '0', any writes to USBADR are instantaneous. When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. Hardware will automatically clear this bit on the following conditions: 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). 3) Device Reset occurs (USBADR is reset to 0). NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement."]
            #[inline(always)]
            #[must_use]
            pub fn usbadra(&mut self) -> USBADRA_W<DEVICEADDR_SPEC> {
                USBADRA_W::new(self, 24)
            }
            #[doc = "Bits 25:31 - USBADR Device Address. These bits correspond to the USB device address"]
            #[inline(always)]
            #[must_use]
            pub fn usbadr(&mut self) -> USBADR_W<DEVICEADDR_SPEC> {
                USBADR_W::new(self, 25)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Device Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`deviceaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`deviceaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DEVICEADDR_SPEC;
        impl crate::RegisterSpec for DEVICEADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`deviceaddr::R`](R) reader structure"]
        impl crate::Readable for DEVICEADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`deviceaddr::W`](W) writer structure"]
        impl crate::Writable for DEVICEADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DEVICEADDR to value 0"]
        impl crate::Resettable for DEVICEADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PERIODICLISTBASE (rw) register accessor: Frame List Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periodiclistbase::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periodiclistbase::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periodiclistbase`]
module"]
    pub type PERIODICLISTBASE = crate::Reg<periodiclistbase::PERIODICLISTBASE_SPEC>;
    #[doc = "Frame List Base Address Register"]
    pub mod periodiclistbase {
        #[doc = "Register `PERIODICLISTBASE` reader"]
        pub type R = crate::R<PERIODICLISTBASE_SPEC>;
        #[doc = "Register `PERIODICLISTBASE` writer"]
        pub type W = crate::W<PERIODICLISTBASE_SPEC>;
        #[doc = "Field `BASEADR` reader - BASEADR Base Address (Low). These bits correspond to memory address signals \\[31:12\\], respectively. Only used by the host controller."]
        pub type BASEADR_R = crate::FieldReader<u32>;
        #[doc = "Field `BASEADR` writer - BASEADR Base Address (Low). These bits correspond to memory address signals \\[31:12\\], respectively. Only used by the host controller."]
        pub type BASEADR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        impl R {
            #[doc = "Bits 12:31 - BASEADR Base Address (Low). These bits correspond to memory address signals \\[31:12\\], respectively. Only used by the host controller."]
            #[inline(always)]
            pub fn baseadr(&self) -> BASEADR_R {
                BASEADR_R::new((self.bits >> 12) & 0x000f_ffff)
            }
        }
        impl W {
            #[doc = "Bits 12:31 - BASEADR Base Address (Low). These bits correspond to memory address signals \\[31:12\\], respectively. Only used by the host controller."]
            #[inline(always)]
            #[must_use]
            pub fn baseadr(&mut self) -> BASEADR_W<PERIODICLISTBASE_SPEC> {
                BASEADR_W::new(self, 12)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Frame List Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periodiclistbase::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periodiclistbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PERIODICLISTBASE_SPEC;
        impl crate::RegisterSpec for PERIODICLISTBASE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`periodiclistbase::R`](R) reader structure"]
        impl crate::Readable for PERIODICLISTBASE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`periodiclistbase::W`](W) writer structure"]
        impl crate::Writable for PERIODICLISTBASE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PERIODICLISTBASE to value 0"]
        impl crate::Resettable for PERIODICLISTBASE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ASYNCLISTADDR (rw) register accessor: Next Asynch. Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`asynclistaddr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`asynclistaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@asynclistaddr`]
module"]
    pub type ASYNCLISTADDR = crate::Reg<asynclistaddr::ASYNCLISTADDR_SPEC>;
    #[doc = "Next Asynch. Address Register"]
    pub mod asynclistaddr {
        #[doc = "Register `ASYNCLISTADDR` reader"]
        pub type R = crate::R<ASYNCLISTADDR_SPEC>;
        #[doc = "Register `ASYNCLISTADDR` writer"]
        pub type W = crate::W<ASYNCLISTADDR_SPEC>;
        #[doc = "Field `ASYBASE` reader - ASYBASE Link Pointer Low (LPL). These bits correspond to memory address signals \\[31:5\\], respectively. This field may only reference a Queue Head (QH). Only used by the host controller."]
        pub type ASYBASE_R = crate::FieldReader<u32>;
        #[doc = "Field `ASYBASE` writer - ASYBASE Link Pointer Low (LPL). These bits correspond to memory address signals \\[31:5\\], respectively. This field may only reference a Queue Head (QH). Only used by the host controller."]
        pub type ASYBASE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>;
        impl R {
            #[doc = "Bits 5:31 - ASYBASE Link Pointer Low (LPL). These bits correspond to memory address signals \\[31:5\\], respectively. This field may only reference a Queue Head (QH). Only used by the host controller."]
            #[inline(always)]
            pub fn asybase(&self) -> ASYBASE_R {
                ASYBASE_R::new((self.bits >> 5) & 0x07ff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 5:31 - ASYBASE Link Pointer Low (LPL). These bits correspond to memory address signals \\[31:5\\], respectively. This field may only reference a Queue Head (QH). Only used by the host controller."]
            #[inline(always)]
            #[must_use]
            pub fn asybase(&mut self) -> ASYBASE_W<ASYNCLISTADDR_SPEC> {
                ASYBASE_W::new(self, 5)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Next Asynch. Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`asynclistaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`asynclistaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ASYNCLISTADDR_SPEC;
        impl crate::RegisterSpec for ASYNCLISTADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`asynclistaddr::R`](R) reader structure"]
        impl crate::Readable for ASYNCLISTADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`asynclistaddr::W`](W) writer structure"]
        impl crate::Writable for ASYNCLISTADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ASYNCLISTADDR to value 0"]
        impl crate::Resettable for ASYNCLISTADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTLISTADDR (rw) register accessor: Endpoint List Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptlistaddr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptlistaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptlistaddr`]
module"]
    pub type ENDPTLISTADDR = crate::Reg<endptlistaddr::ENDPTLISTADDR_SPEC>;
    #[doc = "Endpoint List Address Register"]
    pub mod endptlistaddr {
        #[doc = "Register `ENDPTLISTADDR` reader"]
        pub type R = crate::R<ENDPTLISTADDR_SPEC>;
        #[doc = "Register `ENDPTLISTADDR` writer"]
        pub type W = crate::W<ENDPTLISTADDR_SPEC>;
        #[doc = "Field `EPBASE` reader - EPBASE Endpoint List Pointer(Low). These bits correspond to memory address signals \\[31:11\\], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint &amp; direction)."]
        pub type EPBASE_R = crate::FieldReader<u32>;
        #[doc = "Field `EPBASE` writer - EPBASE Endpoint List Pointer(Low). These bits correspond to memory address signals \\[31:11\\], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint &amp; direction)."]
        pub type EPBASE_W<'a, REG> = crate::FieldWriter<'a, REG, 21, u32>;
        impl R {
            #[doc = "Bits 11:31 - EPBASE Endpoint List Pointer(Low). These bits correspond to memory address signals \\[31:11\\], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint &amp; direction)."]
            #[inline(always)]
            pub fn epbase(&self) -> EPBASE_R {
                EPBASE_R::new((self.bits >> 11) & 0x001f_ffff)
            }
        }
        impl W {
            #[doc = "Bits 11:31 - EPBASE Endpoint List Pointer(Low). These bits correspond to memory address signals \\[31:11\\], respectively. This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint &amp; direction)."]
            #[inline(always)]
            #[must_use]
            pub fn epbase(&mut self) -> EPBASE_W<ENDPTLISTADDR_SPEC> {
                EPBASE_W::new(self, 11)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint List Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptlistaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptlistaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTLISTADDR_SPEC;
        impl crate::RegisterSpec for ENDPTLISTADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptlistaddr::R`](R) reader structure"]
        impl crate::Readable for ENDPTLISTADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptlistaddr::W`](W) writer structure"]
        impl crate::Writable for ENDPTLISTADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTLISTADDR to value 0"]
        impl crate::Resettable for ENDPTLISTADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BURSTSIZE (rw) register accessor: Programmable Burst Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`burstsize::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`burstsize::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@burstsize`]
module"]
    pub type BURSTSIZE = crate::Reg<burstsize::BURSTSIZE_SPEC>;
    #[doc = "Programmable Burst Size Register"]
    pub mod burstsize {
        #[doc = "Register `BURSTSIZE` reader"]
        pub type R = crate::R<BURSTSIZE_SPEC>;
        #[doc = "Register `BURSTSIZE` writer"]
        pub type W = crate::W<BURSTSIZE_SPEC>;
        #[doc = "Field `RXPBURST` reader - RXPBURST Programmable RX Burst Size. Default value is determined by TXBURST bits in n_HWRXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory."]
        pub type RXPBURST_R = crate::FieldReader;
        #[doc = "Field `RXPBURST` writer - RXPBURST Programmable RX Burst Size. Default value is determined by TXBURST bits in n_HWRXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory."]
        pub type RXPBURST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `TXPBURST` reader - TXPBURST Programmable TX Burst Size. Default value is determined by TXBURST bits in n_HWTXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus."]
        pub type TXPBURST_R = crate::FieldReader;
        #[doc = "Field `TXPBURST` writer - TXPBURST Programmable TX Burst Size. Default value is determined by TXBURST bits in n_HWTXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus."]
        pub type TXPBURST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - RXPBURST Programmable RX Burst Size. Default value is determined by TXBURST bits in n_HWRXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory."]
            #[inline(always)]
            pub fn rxpburst(&self) -> RXPBURST_R {
                RXPBURST_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:15 - TXPBURST Programmable TX Burst Size. Default value is determined by TXBURST bits in n_HWTXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus."]
            #[inline(always)]
            pub fn txpburst(&self) -> TXPBURST_R {
                TXPBURST_R::new(((self.bits >> 8) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - RXPBURST Programmable RX Burst Size. Default value is determined by TXBURST bits in n_HWRXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from the USB bus to system memory."]
            #[inline(always)]
            #[must_use]
            pub fn rxpburst(&mut self) -> RXPBURST_W<BURSTSIZE_SPEC> {
                RXPBURST_W::new(self, 0)
            }
            #[doc = "Bits 8:15 - TXPBURST Programmable TX Burst Size. Default value is determined by TXBURST bits in n_HWTXBUF. This register represents the maximum length of a the burst in 32-bit words while moving data from system memory to the USB bus."]
            #[inline(always)]
            #[must_use]
            pub fn txpburst(&mut self) -> TXPBURST_W<BURSTSIZE_SPEC> {
                TXPBURST_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Programmable Burst Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`burstsize::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`burstsize::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BURSTSIZE_SPEC;
        impl crate::RegisterSpec for BURSTSIZE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`burstsize::R`](R) reader structure"]
        impl crate::Readable for BURSTSIZE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`burstsize::W`](W) writer structure"]
        impl crate::Writable for BURSTSIZE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BURSTSIZE to value 0"]
        impl crate::Resettable for BURSTSIZE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TXFILLTUNING (rw) register accessor: TX FIFO Fill Tuning Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfilltuning::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfilltuning::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfilltuning`]
module"]
    pub type TXFILLTUNING = crate::Reg<txfilltuning::TXFILLTUNING_SPEC>;
    #[doc = "TX FIFO Fill Tuning Register"]
    pub mod txfilltuning {
        #[doc = "Register `TXFILLTUNING` reader"]
        pub type R = crate::R<TXFILLTUNING_SPEC>;
        #[doc = "Register `TXFILLTUNING` writer"]
        pub type W = crate::W<TXFILLTUNING_SPEC>;
        #[doc = "Field `TXSCHOH` reader - TXSCHOH Scheduler Overhead. (Read/Write) \\[Default = 0\\]
This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. Default value is '08h' for OTG controller core ."]
        pub type TXSCHOH_R = crate::FieldReader;
        #[doc = "Field `TXSCHOH` writer - TXSCHOH Scheduler Overhead. (Read/Write) \\[Default = 0\\]
This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. Default value is '08h' for OTG controller core ."]
        pub type TXSCHOH_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `TXSCHHEALTH` reader - TXSCHHEALTH Scheduler Health Counter. (Read/Write To Clear) Table continues on the next page This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31."]
        pub type TXSCHHEALTH_R = crate::FieldReader;
        #[doc = "Field `TXSCHHEALTH` writer - TXSCHHEALTH Scheduler Health Counter. (Read/Write To Clear) Table continues on the next page This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31."]
        pub type TXSCHHEALTH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `TXFIFOTHRES` reader - TXFIFOTHRES FIFO Burst Threshold. (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set."]
        pub type TXFIFOTHRES_R = crate::FieldReader;
        #[doc = "Field `TXFIFOTHRES` writer - TXFIFOTHRES FIFO Burst Threshold. (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set."]
        pub type TXFIFOTHRES_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        impl R {
            #[doc = "Bits 0:6 - TXSCHOH Scheduler Overhead. (Read/Write) \\[Default = 0\\]
This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. Default value is '08h' for OTG controller core ."]
            #[inline(always)]
            pub fn txschoh(&self) -> TXSCHOH_R {
                TXSCHOH_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bits 8:12 - TXSCHHEALTH Scheduler Health Counter. (Read/Write To Clear) Table continues on the next page This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31."]
            #[inline(always)]
            pub fn txschhealth(&self) -> TXSCHHEALTH_R {
                TXSCHHEALTH_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:21 - TXFIFOTHRES FIFO Burst Threshold. (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set."]
            #[inline(always)]
            pub fn txfifothres(&self) -> TXFIFOTHRES_R {
                TXFIFOTHRES_R::new(((self.bits >> 16) & 0x3f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - TXSCHOH Scheduler Overhead. (Read/Write) \\[Default = 0\\]
This register adds an additional fixed offset to the schedule time estimator described above as Tff. As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. Default value is '08h' for OTG controller core ."]
            #[inline(always)]
            #[must_use]
            pub fn txschoh(&mut self) -> TXSCHOH_W<TXFILLTUNING_SPEC> {
                TXSCHOH_W::new(self, 0)
            }
            #[doc = "Bits 8:12 - TXSCHHEALTH Scheduler Health Counter. (Read/Write To Clear) Table continues on the next page This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame. This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. Writing to this register will clear the counter and this counter will max. at 31."]
            #[inline(always)]
            #[must_use]
            pub fn txschhealth(&mut self) -> TXSCHHEALTH_W<TXFILLTUNING_SPEC> {
                TXSCHHEALTH_W::new(self, 8)
            }
            #[doc = "Bits 16:21 - TXFIFOTHRES FIFO Burst Threshold. (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. The minimum value is 2 and this value should be a low as possible to maximize USB performance. A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set."]
            #[inline(always)]
            #[must_use]
            pub fn txfifothres(&mut self) -> TXFIFOTHRES_W<TXFILLTUNING_SPEC> {
                TXFIFOTHRES_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "TX FIFO Fill Tuning Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfilltuning::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfilltuning::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TXFILLTUNING_SPEC;
        impl crate::RegisterSpec for TXFILLTUNING_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`txfilltuning::R`](R) reader structure"]
        impl crate::Readable for TXFILLTUNING_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`txfilltuning::W`](W) writer structure"]
        impl crate::Writable for TXFILLTUNING_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TXFILLTUNING to value 0"]
        impl crate::Resettable for TXFILLTUNING_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTNAK (rw) register accessor: Endpoint NAK Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptnak::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptnak::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptnak`]
module"]
    pub type ENDPTNAK = crate::Reg<endptnak::ENDPTNAK_SPEC>;
    #[doc = "Endpoint NAK Register"]
    pub mod endptnak {
        #[doc = "Register `ENDPTNAK` reader"]
        pub type R = crate::R<ENDPTNAK_SPEC>;
        #[doc = "Register `ENDPTNAK` writer"]
        pub type W = crate::W<ENDPTNAK_SPEC>;
        #[doc = "Field `EPRN` reader - EPRN RX Endpoint NAK - R/WC. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPRN_R = crate::FieldReader;
        #[doc = "Field `EPRN` writer - EPRN RX Endpoint NAK - R/WC. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPRN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `EPTN` reader - EPTN TX Endpoint NAK - R/WC. Each TX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPTN_R = crate::FieldReader;
        #[doc = "Field `EPTN` writer - EPTN TX Endpoint NAK - R/WC. Each TX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPTN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - EPRN RX Endpoint NAK - R/WC. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            pub fn eprn(&self) -> EPRN_R {
                EPRN_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - EPTN TX Endpoint NAK - R/WC. Each TX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            pub fn eptn(&self) -> EPTN_R {
                EPTN_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - EPRN RX Endpoint NAK - R/WC. Each RX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            #[must_use]
            pub fn eprn(&mut self) -> EPRN_W<ENDPTNAK_SPEC> {
                EPRN_W::new(self, 0)
            }
            #[doc = "Bits 16:23 - EPTN TX Endpoint NAK - R/WC. Each TX endpoint has 1 bit in this field. The bit is set when the device sends a NAK handshake on a received IN token for the corresponding endpoint. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            #[must_use]
            pub fn eptn(&mut self) -> EPTN_W<ENDPTNAK_SPEC> {
                EPTN_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint NAK Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptnak::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptnak::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTNAK_SPEC;
        impl crate::RegisterSpec for ENDPTNAK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptnak::R`](R) reader structure"]
        impl crate::Readable for ENDPTNAK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptnak::W`](W) writer structure"]
        impl crate::Writable for ENDPTNAK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTNAK to value 0"]
        impl crate::Resettable for ENDPTNAK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTNAKEN (rw) register accessor: Endpoint NAK Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptnaken::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptnaken::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptnaken`]
module"]
    pub type ENDPTNAKEN = crate::Reg<endptnaken::ENDPTNAKEN_SPEC>;
    #[doc = "Endpoint NAK Enable Register"]
    pub mod endptnaken {
        #[doc = "Register `ENDPTNAKEN` reader"]
        pub type R = crate::R<ENDPTNAKEN_SPEC>;
        #[doc = "Register `ENDPTNAKEN` writer"]
        pub type W = crate::W<ENDPTNAKEN_SPEC>;
        #[doc = "Field `EPRNE` reader - EPRNE RX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPRNE_R = crate::FieldReader;
        #[doc = "Field `EPRNE` writer - EPRNE RX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPRNE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `EPTNE` reader - EPTNE TX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPTNE_R = crate::FieldReader;
        #[doc = "Field `EPTNE` writer - EPTNE TX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
        pub type EPTNE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - EPRNE RX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            pub fn eprne(&self) -> EPRNE_R {
                EPRNE_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - EPTNE TX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            pub fn eptne(&self) -> EPTNE_R {
                EPTNE_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - EPRNE RX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            #[must_use]
            pub fn eprne(&mut self) -> EPRNE_W<ENDPTNAKEN_SPEC> {
                EPRNE_W::new(self, 0)
            }
            #[doc = "Bits 16:23 - EPTNE TX Endpoint NAK Enable - R/W. Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. Bit \\[N\\]
- Endpoint #\\[N\\], N is 0-7"]
            #[inline(always)]
            #[must_use]
            pub fn eptne(&mut self) -> EPTNE_W<ENDPTNAKEN_SPEC> {
                EPTNE_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint NAK Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptnaken::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptnaken::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTNAKEN_SPEC;
        impl crate::RegisterSpec for ENDPTNAKEN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptnaken::R`](R) reader structure"]
        impl crate::Readable for ENDPTNAKEN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptnaken::W`](W) writer structure"]
        impl crate::Writable for ENDPTNAKEN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTNAKEN to value 0"]
        impl crate::Resettable for ENDPTNAKEN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PORTSC1 (rw) register accessor: Port Status &amp; Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`portsc1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`portsc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@portsc1`]
module"]
    pub type PORTSC1 = crate::Reg<portsc1::PORTSC1_SPEC>;
    #[doc = "Port Status &amp; Control"]
    pub mod portsc1 {
        #[doc = "Register `PORTSC1` reader"]
        pub type R = crate::R<PORTSC1_SPEC>;
        #[doc = "Register `PORTSC1` writer"]
        pub type W = crate::W<PORTSC1_SPEC>;
        #[doc = "Field `CCS` reader - CCS Current Connect Status-Read Only. In Host Mode: 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended."]
        pub type CCS_R = crate::BitReader;
        #[doc = "Field `CCS` writer - CCS Current Connect Status-Read Only. In Host Mode: 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended."]
        pub type CCS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CSC` reader - CSC Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: This bit is undefined in device controller mode."]
        pub type CSC_R = crate::BitReader;
        #[doc = "Field `CSC` writer - CSC Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: This bit is undefined in device controller mode."]
        pub type CSC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PE` reader - PE Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: The device port is always enabled, so this bit is always '1b'."]
        pub type PE_R = crate::BitReader;
        #[doc = "Field `PE` writer - PE Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: The device port is always enabled, so this bit is always '1b'."]
        pub type PE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PEC` reader - PEC Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. In Host Mode: For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PORTSC1) is zero. In Device mode: The device port is always enabled, so this bit is always '0b'."]
        pub type PEC_R = crate::BitReader;
        #[doc = "Field `PEC` writer - PEC Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. In Host Mode: For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PORTSC1) is zero. In Device mode: The device port is always enabled, so this bit is always '0b'."]
        pub type PEC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OCA` reader - OCA Over-current Active-Read Only. Default 0. This bit will automatically transition from one to zero when the over current condition is removed. 0 - This port does not have an over-current condition. 1 - This port currently has an over-current condition"]
        pub type OCA_R = crate::BitReader;
        #[doc = "Field `OCC` reader - OCC Over-current Change-R/WC. Default=0. This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position."]
        pub type OCC_R = crate::BitReader;
        #[doc = "Field `OCC` writer - OCC Over-current Change-R/WC. Default=0. This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position."]
        pub type OCC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FPR` reader - FPR Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. This field is zero if Port Power(PORTSC1) is zero in host mode. This bit is not-EHCI compatible. In Device mode: After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one."]
        pub type FPR_R = crate::BitReader;
        #[doc = "Field `FPR` writer - FPR Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. This field is zero if Port Power(PORTSC1) is zero in host mode. This bit is not-EHCI compatible. In Device mode: After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one."]
        pub type FPR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SUSP` reader - SUSP Suspend - Read/Write or Read Only. Default = 0b. 1=Port in suspend state. 0=Port not in suspend state. In Host Mode: Read/Write. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits \\[Port Enabled, Suspend\\]
Port State 0x Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: Read Only. In device mode this bit is a read only status bit."]
        pub type SUSP_R = crate::BitReader;
        #[doc = "Field `SUSP` writer - SUSP Suspend - Read/Write or Read Only. Default = 0b. 1=Port in suspend state. 0=Port not in suspend state. In Host Mode: Read/Write. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits \\[Port Enabled, Suspend\\]
Port State 0x Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: Read Only. In device mode this bit is a read only status bit."]
        pub type SUSP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PR` reader - PR Port Reset - Read/Write or Read Only. Default = 0b. In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register."]
        pub type PR_R = crate::BitReader;
        #[doc = "Field `PR` writer - PR Port Reset - Read/Write or Read Only. Default = 0b. In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register."]
        pub type PR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HSP` reader - HSP High-Speed Port - Read Only. Default = 0b. When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility."]
        pub type HSP_R = crate::BitReader;
        #[doc = "Field `LS` reader - LS Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In device mode, the use of linestate by the device controller driver is not necessary. The encoding of the bits are: Bits \\[11:10\\]
Meaning 00 - SE0 01 - K-state 10 - J-state 11 - Undefined"]
        pub type LS_R = crate::FieldReader;
        #[doc = "Field `PP` reader - PP Port Power (PP)-Read/Write or Read Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: PPC PP Operation 0 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. 1 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). This feature is implemented in all controller cores (PPC = 1)."]
        pub type PP_R = crate::BitReader;
        #[doc = "Field `PP` writer - PP Port Power (PP)-Read/Write or Read Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: PPC PP Operation 0 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. 1 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). This feature is implemented in all controller cores (PPC = 1)."]
        pub type PP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PTC` reader - PTC Port Test Control - Read/Write. Default = 0000b. Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. NOTE: Low speed operations are not supported as a peripheral device. Any other value than zero indicates that the port is operating in test mode. Value Specific Test 0000 - TEST_MODE_DISABLE 0001 - J_STATE 0010 - K_STATE 0011 - SE0 (host) / NAK (device) 0100 - Packet 0101 - FORCE_ENABLE_HS 0110 - FORCE_ENABLE_FS 0111 - FORCE_ENABLE_LS 1000-1111 - Reserved"]
        pub type PTC_R = crate::FieldReader;
        #[doc = "Field `PTC` writer - PTC Port Test Control - Read/Write. Default = 0000b. Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. NOTE: Low speed operations are not supported as a peripheral device. Any other value than zero indicates that the port is operating in test mode. Value Specific Test 0000 - TEST_MODE_DISABLE 0001 - J_STATE 0010 - K_STATE 0011 - SE0 (host) / NAK (device) 0100 - Packet 0101 - FORCE_ENABLE_HS 0110 - FORCE_ENABLE_FS 0111 - FORCE_ENABLE_LS 1000-1111 - Reserved"]
        pub type PTC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `WKCN` reader - WKCN Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
        pub type WKCN_R = crate::BitReader;
        #[doc = "Field `WKCN` writer - WKCN Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
        pub type WKCN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WKDC` reader - WKDC Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
        pub type WKDC_R = crate::BitReader;
        #[doc = "Field `WKDC` writer - WKDC Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
        pub type WKDC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WKOC` reader - WKOC Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power(PORTSC1) is zero."]
        pub type WKOC_R = crate::BitReader;
        #[doc = "Field `WKOC` writer - WKOC Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power(PORTSC1) is zero."]
        pub type WKOC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PHCD` reader - PHCD PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend will be cleared automatically when the host initials resume. Before forcing a resume from the device, the device controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 - Enable PHY clock 1 - Disable PHY clock"]
        pub type PHCD_R = crate::BitReader;
        #[doc = "Field `PHCD` writer - PHCD PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend will be cleared automatically when the host initials resume. Before forcing a resume from the device, the device controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 - Enable PHY clock 1 - Disable PHY clock"]
        pub type PHCD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PFSC` reader - PFSC Port Force Full Speed Connect - Read/Write. Default = 0b. When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp sequence that allows the port to identify itself as High Speed. 0 - Normal operation 1 - Forced to full speed"]
        pub type PFSC_R = crate::BitReader;
        #[doc = "Field `PFSC` writer - PFSC Port Force Full Speed Connect - Read/Write. Default = 0b. When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp sequence that allows the port to identify itself as High Speed. 0 - Normal operation 1 - Forced to full speed"]
        pub type PFSC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PSPD` reader - PSPD Port Speed - Read Only. This register field indicates the speed at which the port is operating. 00 - Full Speed 01 - Low Speed 10 - High Speed 11 - Undefined"]
        pub type PSPD_R = crate::FieldReader;
        #[doc = "Field `PTW` reader - PTW Parallel Transceiver Width This bit has no effect if serial interface engine is used. 0 - Select the 8-bit UTMI interface \\[60MHz\\]
1 - Select the 16-bit UTMI interface \\[30MHz\\]"]
        pub type PTW_R = crate::BitReader;
        #[doc = "Field `PTW` writer - PTW Parallel Transceiver Width This bit has no effect if serial interface engine is used. 0 - Select the 8-bit UTMI interface \\[60MHz\\]
1 - Select the 16-bit UTMI interface \\[30MHz\\]"]
        pub type PTW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STS` reader - STS Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. When this bit is set '1b', serial interface engine will be used instead of parallel interface signals."]
        pub type STS_R = crate::BitReader;
        #[doc = "Field `STS` writer - STS Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. When this bit is set '1b', serial interface engine will be used instead of parallel interface signals."]
        pub type STS_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - CCS Current Connect Status-Read Only. In Host Mode: 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended."]
            #[inline(always)]
            pub fn ccs(&self) -> CCS_R {
                CCS_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - CSC Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: This bit is undefined in device controller mode."]
            #[inline(always)]
            pub fn csc(&self) -> CSC_R {
                CSC_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - PE Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: The device port is always enabled, so this bit is always '1b'."]
            #[inline(always)]
            pub fn pe(&self) -> PE_R {
                PE_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - PEC Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. In Host Mode: For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PORTSC1) is zero. In Device mode: The device port is always enabled, so this bit is always '0b'."]
            #[inline(always)]
            pub fn pec(&self) -> PEC_R {
                PEC_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - OCA Over-current Active-Read Only. Default 0. This bit will automatically transition from one to zero when the over current condition is removed. 0 - This port does not have an over-current condition. 1 - This port currently has an over-current condition"]
            #[inline(always)]
            pub fn oca(&self) -> OCA_R {
                OCA_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - OCC Over-current Change-R/WC. Default=0. This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position."]
            #[inline(always)]
            pub fn occ(&self) -> OCC_R {
                OCC_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - FPR Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. This field is zero if Port Power(PORTSC1) is zero in host mode. This bit is not-EHCI compatible. In Device mode: After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one."]
            #[inline(always)]
            pub fn fpr(&self) -> FPR_R {
                FPR_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - SUSP Suspend - Read/Write or Read Only. Default = 0b. 1=Port in suspend state. 0=Port not in suspend state. In Host Mode: Read/Write. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits \\[Port Enabled, Suspend\\]
Port State 0x Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: Read Only. In device mode this bit is a read only status bit."]
            #[inline(always)]
            pub fn susp(&self) -> SUSP_R {
                SUSP_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - PR Port Reset - Read/Write or Read Only. Default = 0b. In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register."]
            #[inline(always)]
            pub fn pr(&self) -> PR_R {
                PR_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - HSP High-Speed Port - Read Only. Default = 0b. When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility."]
            #[inline(always)]
            pub fn hsp(&self) -> HSP_R {
                HSP_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bits 10:11 - LS Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because the port controller state machine and the port routing manage the connection of LS and FS. In device mode, the use of linestate by the device controller driver is not necessary. The encoding of the bits are: Bits \\[11:10\\]
Meaning 00 - SE0 01 - K-state 10 - J-state 11 - Undefined"]
            #[inline(always)]
            pub fn ls(&self) -> LS_R {
                LS_R::new(((self.bits >> 10) & 3) as u8)
            }
            #[doc = "Bit 12 - PP Port Power (PP)-Read/Write or Read Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: PPC PP Operation 0 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. 1 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). This feature is implemented in all controller cores (PPC = 1)."]
            #[inline(always)]
            pub fn pp(&self) -> PP_R {
                PP_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bits 16:19 - PTC Port Test Control - Read/Write. Default = 0000b. Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. NOTE: Low speed operations are not supported as a peripheral device. Any other value than zero indicates that the port is operating in test mode. Value Specific Test 0000 - TEST_MODE_DISABLE 0001 - J_STATE 0010 - K_STATE 0011 - SE0 (host) / NAK (device) 0100 - Packet 0101 - FORCE_ENABLE_HS 0110 - FORCE_ENABLE_FS 0111 - FORCE_ENABLE_LS 1000-1111 - Reserved"]
            #[inline(always)]
            pub fn ptc(&self) -> PTC_R {
                PTC_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bit 20 - WKCN Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
            #[inline(always)]
            pub fn wkcn(&self) -> WKCN_R {
                WKCN_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - WKDC Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
            #[inline(always)]
            pub fn wkdc(&self) -> WKDC_R {
                WKDC_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - WKOC Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power(PORTSC1) is zero."]
            #[inline(always)]
            pub fn wkoc(&self) -> WKOC_R {
                WKOC_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - PHCD PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend will be cleared automatically when the host initials resume. Before forcing a resume from the device, the device controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 - Enable PHY clock 1 - Disable PHY clock"]
            #[inline(always)]
            pub fn phcd(&self) -> PHCD_R {
                PHCD_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - PFSC Port Force Full Speed Connect - Read/Write. Default = 0b. When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp sequence that allows the port to identify itself as High Speed. 0 - Normal operation 1 - Forced to full speed"]
            #[inline(always)]
            pub fn pfsc(&self) -> PFSC_R {
                PFSC_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bits 26:27 - PSPD Port Speed - Read Only. This register field indicates the speed at which the port is operating. 00 - Full Speed 01 - Low Speed 10 - High Speed 11 - Undefined"]
            #[inline(always)]
            pub fn pspd(&self) -> PSPD_R {
                PSPD_R::new(((self.bits >> 26) & 3) as u8)
            }
            #[doc = "Bit 28 - PTW Parallel Transceiver Width This bit has no effect if serial interface engine is used. 0 - Select the 8-bit UTMI interface \\[60MHz\\]
1 - Select the 16-bit UTMI interface \\[30MHz\\]"]
            #[inline(always)]
            pub fn ptw(&self) -> PTW_R {
                PTW_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - STS Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. When this bit is set '1b', serial interface engine will be used instead of parallel interface signals."]
            #[inline(always)]
            pub fn sts(&self) -> STS_R {
                STS_R::new(((self.bits >> 29) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - CCS Current Connect Status-Read Only. In Host Mode: 1=Device is present on port. 0=No device is present. Default = 0. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: 1=Attached. 0=Not Attached. Default=0. A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or Suspended."]
            #[inline(always)]
            #[must_use]
            pub fn ccs(&mut self) -> CCS_W<PORTSC1_SPEC> {
                CCS_W::new(self, 0)
            }
            #[doc = "Bit 1 - CSC Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. In Host Mode: Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: This bit is undefined in device controller mode."]
            #[inline(always)]
            #[must_use]
            pub fn csc(&mut self) -> CSC_W<PORTSC1_SPEC> {
                CSC_W::new(self, 1)
            }
            #[doc = "Bit 2 - PE Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. In Host Mode: Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: The device port is always enabled, so this bit is always '1b'."]
            #[inline(always)]
            #[must_use]
            pub fn pe(&mut self) -> PE_W<PORTSC1_SPEC> {
                PE_W::new(self, 2)
            }
            #[doc = "Bit 3 - PEC Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. In Host Mode: For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PORTSC1) is zero. In Device mode: The device port is always enabled, so this bit is always '0b'."]
            #[inline(always)]
            #[must_use]
            pub fn pec(&mut self) -> PEC_W<PORTSC1_SPEC> {
                PEC_W::new(self, 3)
            }
            #[doc = "Bit 5 - OCC Over-current Change-R/WC. Default=0. This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position."]
            #[inline(always)]
            #[must_use]
            pub fn occ(&mut self) -> OCC_W<PORTSC1_SPEC> {
                OCC_W::new(self, 5)
            }
            #[doc = "Bit 6 - FPR Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. In Host Mode: Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. This field is zero if Port Power(PORTSC1) is zero in host mode. This bit is not-EHCI compatible. In Device mode: After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one."]
            #[inline(always)]
            #[must_use]
            pub fn fpr(&mut self) -> FPR_W<PORTSC1_SPEC> {
                FPR_W::new(self, 6)
            }
            #[doc = "Bit 7 - SUSP Suspend - Read/Write or Read Only. Default = 0b. 1=Port in suspend state. 0=Port not in suspend state. In Host Mode: Read/Write. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits \\[Port Enabled, Suspend\\]
Port State 0x Disable 10 Enable 11 Suspend When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PORTSC1) is zero in host mode. In Device Mode: Read Only. In device mode this bit is a read only status bit."]
            #[inline(always)]
            #[must_use]
            pub fn susp(&mut self) -> SUSP_W<PORTSC1_SPEC> {
                SUSP_W::new(self, 7)
            }
            #[doc = "Bit 8 - PR Port Reset - Read/Write or Read Only. Default = 0b. In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register."]
            #[inline(always)]
            #[must_use]
            pub fn pr(&mut self) -> PR_W<PORTSC1_SPEC> {
                PR_W::new(self, 8)
            }
            #[doc = "Bit 12 - PP Port Power (PP)-Read/Write or Read Only. The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: PPC PP Operation 0 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. 1 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). This feature is implemented in all controller cores (PPC = 1)."]
            #[inline(always)]
            #[must_use]
            pub fn pp(&mut self) -> PP_W<PORTSC1_SPEC> {
                PP_W::new(self, 12)
            }
            #[doc = "Bits 16:19 - PTC Port Test Control - Read/Write. Default = 0000b. Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. NOTE: Low speed operations are not supported as a peripheral device. Any other value than zero indicates that the port is operating in test mode. Value Specific Test 0000 - TEST_MODE_DISABLE 0001 - J_STATE 0010 - K_STATE 0011 - SE0 (host) / NAK (device) 0100 - Packet 0101 - FORCE_ENABLE_HS 0110 - FORCE_ENABLE_FS 0111 - FORCE_ENABLE_LS 1000-1111 - Reserved"]
            #[inline(always)]
            #[must_use]
            pub fn ptc(&mut self) -> PTC_W<PORTSC1_SPEC> {
                PTC_W::new(self, 16)
            }
            #[doc = "Bit 20 - WKCN Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
            #[inline(always)]
            #[must_use]
            pub fn wkcn(&mut self) -> WKCN_W<PORTSC1_SPEC> {
                WKCN_W::new(self, 20)
            }
            #[doc = "Bit 21 - WKDC Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PORTSC1) is zero or in device mode."]
            #[inline(always)]
            #[must_use]
            pub fn wkdc(&mut self) -> WKDC_W<PORTSC1_SPEC> {
                WKDC_W::new(self, 21)
            }
            #[doc = "Bit 22 - WKOC Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. This field is zero if Port Power(PORTSC1) is zero."]
            #[inline(always)]
            #[must_use]
            pub fn wkoc(&mut self) -> WKOC_W<PORTSC1_SPEC> {
                WKOC_W::new(self, 22)
            }
            #[doc = "Bit 23 - PHCD PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY clock. NOTE: The PHY clock cannot be disabled if it is being used as the system clock. In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend will be cleared automatically when the host initials resume. Before forcing a resume from the device, the device controller driver must clear this bit. In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software. 0 - Enable PHY clock 1 - Disable PHY clock"]
            #[inline(always)]
            #[must_use]
            pub fn phcd(&mut self) -> PHCD_W<PORTSC1_SPEC> {
                PHCD_W::new(self, 23)
            }
            #[doc = "Bit 24 - PFSC Port Force Full Speed Connect - Read/Write. Default = 0b. When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp sequence that allows the port to identify itself as High Speed. 0 - Normal operation 1 - Forced to full speed"]
            #[inline(always)]
            #[must_use]
            pub fn pfsc(&mut self) -> PFSC_W<PORTSC1_SPEC> {
                PFSC_W::new(self, 24)
            }
            #[doc = "Bit 28 - PTW Parallel Transceiver Width This bit has no effect if serial interface engine is used. 0 - Select the 8-bit UTMI interface \\[60MHz\\]
1 - Select the 16-bit UTMI interface \\[30MHz\\]"]
            #[inline(always)]
            #[must_use]
            pub fn ptw(&mut self) -> PTW_W<PORTSC1_SPEC> {
                PTW_W::new(self, 28)
            }
            #[doc = "Bit 29 - STS Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. When this bit is set '1b', serial interface engine will be used instead of parallel interface signals."]
            #[inline(always)]
            #[must_use]
            pub fn sts(&mut self) -> STS_W<PORTSC1_SPEC> {
                STS_W::new(self, 29)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Port Status &amp; Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`portsc1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`portsc1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PORTSC1_SPEC;
        impl crate::RegisterSpec for PORTSC1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`portsc1::R`](R) reader structure"]
        impl crate::Readable for PORTSC1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`portsc1::W`](W) writer structure"]
        impl crate::Writable for PORTSC1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PORTSC1 to value 0"]
        impl crate::Resettable for PORTSC1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "OTGSC (rw) register accessor: On-The-Go Status &amp; control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otgsc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`otgsc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otgsc`]
module"]
    pub type OTGSC = crate::Reg<otgsc::OTGSC_SPEC>;
    #[doc = "On-The-Go Status &amp; control Register"]
    pub mod otgsc {
        #[doc = "Register `OTGSC` reader"]
        pub type R = crate::R<OTGSC_SPEC>;
        #[doc = "Register `OTGSC` writer"]
        pub type W = crate::W<OTGSC_SPEC>;
        #[doc = "Field `VD` reader - VD VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor."]
        pub type VD_R = crate::BitReader;
        #[doc = "Field `VD` writer - VD VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor."]
        pub type VD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VC` reader - VC VBUS Charge - Read/Write. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP."]
        pub type VC_R = crate::BitReader;
        #[doc = "Field `VC` writer - VC VBUS Charge - Read/Write. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP."]
        pub type VC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IDPU` reader - IDPU ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on \\[default\\]. When this bit is 0, the ID input will not be sampled."]
        pub type IDPU_R = crate::BitReader;
        #[doc = "Field `IDPU` writer - IDPU ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on \\[default\\]. When this bit is 0, the ID input will not be sampled."]
        pub type IDPU_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ID` reader - ID USB ID - Read Only. 0 = A device, 1 = B device"]
        pub type ID_R = crate::BitReader;
        #[doc = "Field `AVV` reader - AVV A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold."]
        pub type AVV_R = crate::BitReader;
        #[doc = "Field `ASV` reader - ASV A Session Valid - Read Only. Indicates VBus is above the A session valid threshold."]
        pub type ASV_R = crate::BitReader;
        #[doc = "Field `IDIS` reader - IDIS USB ID Interrupt Status - Read/Write. This bit is set when a change on the ID input has been detected. Software must write a one to clear this bit."]
        pub type IDIS_R = crate::BitReader;
        #[doc = "Field `IDIS` writer - IDIS USB ID Interrupt Status - Read/Write. This bit is set when a change on the ID input has been detected. Software must write a one to clear this bit."]
        pub type IDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AVVIS` reader - AVVIS A VBus Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. Software must write a one to clear this bit."]
        pub type AVVIS_R = crate::BitReader;
        #[doc = "Field `AVVIS` writer - AVVIS A VBus Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. Software must write a one to clear this bit."]
        pub type AVVIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASVIS` reader - ASVIS A Session Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the A session valid threshold. Software must write a one to clear this bit."]
        pub type ASVIS_R = crate::BitReader;
        #[doc = "Field `ASVIS` writer - ASVIS A Session Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the A session valid threshold. Software must write a one to clear this bit."]
        pub type ASVIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IDIE` reader - IDIE USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt."]
        pub type IDIE_R = crate::BitReader;
        #[doc = "Field `IDIE` writer - IDIE USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt."]
        pub type IDIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AVVIE` reader - AVVIE A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt."]
        pub type AVVIE_R = crate::BitReader;
        #[doc = "Field `AVVIE` writer - AVVIE A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt."]
        pub type AVVIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ASVIE` reader - ASVIE A Session Valid Interrupt Enable - Read/Write."]
        pub type ASVIE_R = crate::BitReader;
        #[doc = "Field `ASVIE` writer - ASVIE A Session Valid Interrupt Enable - Read/Write."]
        pub type ASVIE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - VD VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor."]
            #[inline(always)]
            pub fn vd(&self) -> VD_R {
                VD_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - VC VBUS Charge - Read/Write. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP."]
            #[inline(always)]
            pub fn vc(&self) -> VC_R {
                VC_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 5 - IDPU ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on \\[default\\]. When this bit is 0, the ID input will not be sampled."]
            #[inline(always)]
            pub fn idpu(&self) -> IDPU_R {
                IDPU_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 8 - ID USB ID - Read Only. 0 = A device, 1 = B device"]
            #[inline(always)]
            pub fn id(&self) -> ID_R {
                ID_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - AVV A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold."]
            #[inline(always)]
            pub fn avv(&self) -> AVV_R {
                AVV_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - ASV A Session Valid - Read Only. Indicates VBus is above the A session valid threshold."]
            #[inline(always)]
            pub fn asv(&self) -> ASV_R {
                ASV_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 16 - IDIS USB ID Interrupt Status - Read/Write. This bit is set when a change on the ID input has been detected. Software must write a one to clear this bit."]
            #[inline(always)]
            pub fn idis(&self) -> IDIS_R {
                IDIS_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - AVVIS A VBus Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. Software must write a one to clear this bit."]
            #[inline(always)]
            pub fn avvis(&self) -> AVVIS_R {
                AVVIS_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 18 - ASVIS A Session Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the A session valid threshold. Software must write a one to clear this bit."]
            #[inline(always)]
            pub fn asvis(&self) -> ASVIS_R {
                ASVIS_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 24 - IDIE USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt."]
            #[inline(always)]
            pub fn idie(&self) -> IDIE_R {
                IDIE_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - AVVIE A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt."]
            #[inline(always)]
            pub fn avvie(&self) -> AVVIE_R {
                AVVIE_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - ASVIE A Session Valid Interrupt Enable - Read/Write."]
            #[inline(always)]
            pub fn asvie(&self) -> ASVIE_R {
                ASVIE_R::new(((self.bits >> 26) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - VD VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor."]
            #[inline(always)]
            #[must_use]
            pub fn vd(&mut self) -> VD_W<OTGSC_SPEC> {
                VD_W::new(self, 0)
            }
            #[doc = "Bit 1 - VC VBUS Charge - Read/Write. Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP."]
            #[inline(always)]
            #[must_use]
            pub fn vc(&mut self) -> VC_W<OTGSC_SPEC> {
                VC_W::new(self, 1)
            }
            #[doc = "Bit 5 - IDPU ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on \\[default\\]. When this bit is 0, the ID input will not be sampled."]
            #[inline(always)]
            #[must_use]
            pub fn idpu(&mut self) -> IDPU_W<OTGSC_SPEC> {
                IDPU_W::new(self, 5)
            }
            #[doc = "Bit 16 - IDIS USB ID Interrupt Status - Read/Write. This bit is set when a change on the ID input has been detected. Software must write a one to clear this bit."]
            #[inline(always)]
            #[must_use]
            pub fn idis(&mut self) -> IDIS_W<OTGSC_SPEC> {
                IDIS_W::new(self, 16)
            }
            #[doc = "Bit 17 - AVVIS A VBus Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. Software must write a one to clear this bit."]
            #[inline(always)]
            #[must_use]
            pub fn avvis(&mut self) -> AVVIS_W<OTGSC_SPEC> {
                AVVIS_W::new(self, 17)
            }
            #[doc = "Bit 18 - ASVIS A Session Valid Interrupt Status - Read/Write to Clear. This bit is set when VBus has either risen above or fallen below the A session valid threshold. Software must write a one to clear this bit."]
            #[inline(always)]
            #[must_use]
            pub fn asvis(&mut self) -> ASVIS_W<OTGSC_SPEC> {
                ASVIS_W::new(self, 18)
            }
            #[doc = "Bit 24 - IDIE USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn idie(&mut self) -> IDIE_W<OTGSC_SPEC> {
                IDIE_W::new(self, 24)
            }
            #[doc = "Bit 25 - AVVIE A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn avvie(&mut self) -> AVVIE_W<OTGSC_SPEC> {
                AVVIE_W::new(self, 25)
            }
            #[doc = "Bit 26 - ASVIE A Session Valid Interrupt Enable - Read/Write."]
            #[inline(always)]
            #[must_use]
            pub fn asvie(&mut self) -> ASVIE_W<OTGSC_SPEC> {
                ASVIE_W::new(self, 26)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "On-The-Go Status &amp; control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otgsc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`otgsc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct OTGSC_SPEC;
        impl crate::RegisterSpec for OTGSC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`otgsc::R`](R) reader structure"]
        impl crate::Readable for OTGSC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`otgsc::W`](W) writer structure"]
        impl crate::Writable for OTGSC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets OTGSC to value 0"]
        impl crate::Resettable for OTGSC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "USBMODE (rw) register accessor: USB Device Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbmode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbmode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbmode`]
module"]
    pub type USBMODE = crate::Reg<usbmode::USBMODE_SPEC>;
    #[doc = "USB Device Mode Register"]
    pub mod usbmode {
        #[doc = "Register `USBMODE` reader"]
        pub type R = crate::R<USBMODE_SPEC>;
        #[doc = "Register `USBMODE` writer"]
        pub type W = crate::W<USBMODE_SPEC>;
        #[doc = "Field `CM` reader - CM Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host &amp; device capability, the controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. For OTG controller core, reset value is '00b'. 00 - Idle \\[Default for combination host/device\\]
01 - Reserved 10 - Device Controller \\[Default for device only controller\\]
11 - Host Controller \\[Default for host only controller\\]"]
        pub type CM_R = crate::FieldReader;
        #[doc = "Field `CM` writer - CM Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host &amp; device capability, the controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. For OTG controller core, reset value is '00b'. 00 - Idle \\[Default for combination host/device\\]
01 - Reserved 10 - Device Controller \\[Default for device only controller\\]
11 - Host Controller \\[Default for host only controller\\]"]
        pub type CM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ES` reader - ES Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. Bit Meaning 0 - Little Endian \\[Default\\]
1 - Big Endian"]
        pub type ES_R = crate::BitReader;
        #[doc = "Field `ES` writer - ES Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. Bit Meaning 0 - Little Endian \\[Default\\]
1 - Big Endian"]
        pub type ES_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SLOM` reader - SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . 0 - Setup Lockouts On (default); 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD."]
        pub type SLOM_R = crate::BitReader;
        #[doc = "Field `SLOM` writer - SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . 0 - Setup Lockouts On (default); 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD."]
        pub type SLOM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SDIS` reader - SDIS Stream Disable Mode. (0 - Inactive \\[default\\]; 1 - Active) Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING \\[MPH Only\\]
to characterize the adjustments needed for the scheduler when using this feature. NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved."]
        pub type SDIS_R = crate::BitReader;
        #[doc = "Field `SDIS` writer - SDIS Stream Disable Mode. (0 - Inactive \\[default\\]; 1 - Active) Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING \\[MPH Only\\]
to characterize the adjustments needed for the scheduler when using this feature. NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved."]
        pub type SDIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1 - CM Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host &amp; device capability, the controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. For OTG controller core, reset value is '00b'. 00 - Idle \\[Default for combination host/device\\]
01 - Reserved 10 - Device Controller \\[Default for device only controller\\]
11 - Host Controller \\[Default for host only controller\\]"]
            #[inline(always)]
            pub fn cm(&self) -> CM_R {
                CM_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 2 - ES Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. Bit Meaning 0 - Little Endian \\[Default\\]
1 - Big Endian"]
            #[inline(always)]
            pub fn es(&self) -> ES_R {
                ES_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . 0 - Setup Lockouts On (default); 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD."]
            #[inline(always)]
            pub fn slom(&self) -> SLOM_R {
                SLOM_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - SDIS Stream Disable Mode. (0 - Inactive \\[default\\]; 1 - Active) Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING \\[MPH Only\\]
to characterize the adjustments needed for the scheduler when using this feature. NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved."]
            #[inline(always)]
            pub fn sdis(&self) -> SDIS_R {
                SDIS_R::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - CM Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only implementations. For those designs that contain both host &amp; device capability, the controller defaults to an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ device controllers, this register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. For OTG controller core, reset value is '00b'. 00 - Idle \\[Default for combination host/device\\]
01 - Reserved 10 - Device Controller \\[Default for device only controller\\]
11 - Host Controller \\[Default for host only controller\\]"]
            #[inline(always)]
            #[must_use]
            pub fn cm(&mut self) -> CM_W<USBMODE_SPEC> {
                CM_W::new(self, 0)
            }
            #[doc = "Bit 2 - ES Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected by the value of this bit because they are based upon the 32-bit word. Bit Meaning 0 - Little Endian \\[Default\\]
1 - Big Endian"]
            #[inline(always)]
            #[must_use]
            pub fn es(&mut self) -> ES_W<USBMODE_SPEC> {
                ES_W::new(self, 2)
            }
            #[doc = "Bit 3 - SLOM Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . 0 - Setup Lockouts On (default); 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD."]
            #[inline(always)]
            #[must_use]
            pub fn slom(&mut self) -> SLOM_W<USBMODE_SPEC> {
                SLOM_W::new(self, 3)
            }
            #[doc = "Bit 4 - SDIS Stream Disable Mode. (0 - Inactive \\[default\\]; 1 - Active) Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING \\[MPH Only\\]
to characterize the adjustments needed for the scheduler when using this feature. NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved."]
            #[inline(always)]
            #[must_use]
            pub fn sdis(&mut self) -> SDIS_W<USBMODE_SPEC> {
                SDIS_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "USB Device Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usbmode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usbmode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct USBMODE_SPEC;
        impl crate::RegisterSpec for USBMODE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`usbmode::R`](R) reader structure"]
        impl crate::Readable for USBMODE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`usbmode::W`](W) writer structure"]
        impl crate::Writable for USBMODE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets USBMODE to value 0"]
        impl crate::Resettable for USBMODE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTSETUPSTAT (rw) register accessor: Endpoint Setup Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptsetupstat::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptsetupstat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptsetupstat`]
module"]
    pub type ENDPTSETUPSTAT = crate::Reg<endptsetupstat::ENDPTSETUPSTAT_SPEC>;
    #[doc = "Endpoint Setup Status Register"]
    pub mod endptsetupstat {
        #[doc = "Register `ENDPTSETUPSTAT` reader"]
        pub type R = crate::R<ENDPTSETUPSTAT_SPEC>;
        #[doc = "Register `ENDPTSETUPSTAT` writer"]
        pub type W = crate::W<ENDPTSETUPSTAT_SPEC>;
        #[doc = "Field `ENDPTSETUPSTAT` reader - ENDPTSETUPSTAT Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode."]
        pub type ENDPTSETUPSTAT_R = crate::FieldReader;
        #[doc = "Field `ENDPTSETUPSTAT` writer - ENDPTSETUPSTAT Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode."]
        pub type ENDPTSETUPSTAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - ENDPTSETUPSTAT Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode."]
            #[inline(always)]
            pub fn endptsetupstat(&self) -> ENDPTSETUPSTAT_R {
                ENDPTSETUPSTAT_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - ENDPTSETUPSTAT Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. This register is only used in device mode."]
            #[inline(always)]
            #[must_use]
            pub fn endptsetupstat(&mut self) -> ENDPTSETUPSTAT_W<ENDPTSETUPSTAT_SPEC> {
                ENDPTSETUPSTAT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint Setup Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptsetupstat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptsetupstat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTSETUPSTAT_SPEC;
        impl crate::RegisterSpec for ENDPTSETUPSTAT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptsetupstat::R`](R) reader structure"]
        impl crate::Readable for ENDPTSETUPSTAT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptsetupstat::W`](W) writer structure"]
        impl crate::Writable for ENDPTSETUPSTAT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTSETUPSTAT to value 0"]
        impl crate::Resettable for ENDPTSETUPSTAT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTPRIME (rw) register accessor: Endpoint Prime Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptprime::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptprime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptprime`]
module"]
    pub type ENDPTPRIME = crate::Reg<endptprime::ENDPTPRIME_SPEC>;
    #[doc = "Endpoint Prime Register"]
    pub mod endptprime {
        #[doc = "Register `ENDPTPRIME` reader"]
        pub type R = crate::R<ENDPTPRIME_SPEC>;
        #[doc = "Register `ENDPTPRIME` writer"]
        pub type W = crate::W<ENDPTPRIME_SPEC>;
        #[doc = "Field `PERB` reader - PERB Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type PERB_R = crate::FieldReader;
        #[doc = "Field `PERB` writer - PERB Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type PERB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `PETB` reader - PETB Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type PETB_R = crate::FieldReader;
        #[doc = "Field `PETB` writer - PETB Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type PETB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - PERB Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn perb(&self) -> PERB_R {
                PERB_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - PETB Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn petb(&self) -> PETB_R {
                PETB_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - PERB Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PERB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            #[must_use]
            pub fn perb(&mut self) -> PERB_W<ENDPTPRIME_SPEC> {
                PERB_W::new(self, 0)
            }
            #[doc = "Bits 16:23 - PETB Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. Software should write a one to the corresponding bit when posting a new transfer descriptor to an endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD is retired, and the dQH is updated. PETB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            #[must_use]
            pub fn petb(&mut self) -> PETB_W<ENDPTPRIME_SPEC> {
                PETB_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint Prime Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptprime::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptprime::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTPRIME_SPEC;
        impl crate::RegisterSpec for ENDPTPRIME_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptprime::R`](R) reader structure"]
        impl crate::Readable for ENDPTPRIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptprime::W`](W) writer structure"]
        impl crate::Writable for ENDPTPRIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTPRIME to value 0"]
        impl crate::Resettable for ENDPTPRIME_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTFLUSH (rw) register accessor: Endpoint Flush Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptflush::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptflush::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptflush`]
module"]
    pub type ENDPTFLUSH = crate::Reg<endptflush::ENDPTFLUSH_SPEC>;
    #[doc = "Endpoint Flush Register"]
    pub mod endptflush {
        #[doc = "Register `ENDPTFLUSH` reader"]
        pub type R = crate::R<ENDPTFLUSH_SPEC>;
        #[doc = "Register `ENDPTFLUSH` writer"]
        pub type W = crate::W<ENDPTFLUSH_SPEC>;
        #[doc = "Field `FERB` reader - FERB Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FERB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type FERB_R = crate::FieldReader;
        #[doc = "Field `FERB` writer - FERB Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FERB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type FERB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `FETB` reader - FETB Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FETB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type FETB_R = crate::FieldReader;
        #[doc = "Field `FETB` writer - FETB Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FETB\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type FETB_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - FERB Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FERB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn ferb(&self) -> FERB_R {
                FERB_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - FETB Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FETB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn fetb(&self) -> FETB_R {
                FETB_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - FERB Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FERB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            #[must_use]
            pub fn ferb(&mut self) -> FERB_W<ENDPTFLUSH_SPEC> {
                FERB_W::new(self, 0)
            }
            #[doc = "Bits 16:23 - FETB Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. Hardware clears this register after the endpoint flush operation is successful. FETB\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            #[must_use]
            pub fn fetb(&mut self) -> FETB_W<ENDPTFLUSH_SPEC> {
                FETB_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint Flush Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptflush::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptflush::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTFLUSH_SPEC;
        impl crate::RegisterSpec for ENDPTFLUSH_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptflush::R`](R) reader structure"]
        impl crate::Readable for ENDPTFLUSH_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptflush::W`](W) writer structure"]
        impl crate::Writable for ENDPTFLUSH_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTFLUSH to value 0"]
        impl crate::Resettable for ENDPTFLUSH_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTSTAT (rw) register accessor: Endpoint Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptstat::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptstat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptstat`]
module"]
    pub type ENDPTSTAT = crate::Reg<endptstat::ENDPTSTAT_SPEC>;
    #[doc = "Endpoint Status Register"]
    pub mod endptstat {
        #[doc = "Register `ENDPTSTAT` reader"]
        pub type R = crate::R<ENDPTSTAT_SPEC>;
        #[doc = "Register `ENDPTSTAT` writer"]
        pub type W = crate::W<ENDPTSTAT_SPEC>;
        #[doc = "Field `ERBR` reader - ERBR Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ERBR\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type ERBR_R = crate::FieldReader;
        #[doc = "Field `ETBR` reader - ETBR Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type ETBR_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - ERBR Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ERBR\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn erbr(&self) -> ERBR_R {
                ERBR_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - ETBR Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. ETBR\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn etbr(&self) -> ETBR_R {
                ETBR_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptstat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptstat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTSTAT_SPEC;
        impl crate::RegisterSpec for ENDPTSTAT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptstat::R`](R) reader structure"]
        impl crate::Readable for ENDPTSTAT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptstat::W`](W) writer structure"]
        impl crate::Writable for ENDPTSTAT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTSTAT to value 0"]
        impl crate::Resettable for ENDPTSTAT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTCOMPLETE (rw) register accessor: Endpoint Complete Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptcomplete::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptcomplete::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptcomplete`]
module"]
    pub type ENDPTCOMPLETE = crate::Reg<endptcomplete::ENDPTCOMPLETE_SPEC>;
    #[doc = "Endpoint Complete Register"]
    pub mod endptcomplete {
        #[doc = "Register `ENDPTCOMPLETE` reader"]
        pub type R = crate::R<ENDPTCOMPLETE_SPEC>;
        #[doc = "Register `ENDPTCOMPLETE` writer"]
        pub type W = crate::W<ENDPTCOMPLETE_SPEC>;
        #[doc = "Field `ERCE` reader - ERCE Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ERCE\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type ERCE_R = crate::FieldReader;
        #[doc = "Field `ERCE` writer - ERCE Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ERCE\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type ERCE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `ETCE` reader - ETCE Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ETCE\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type ETCE_R = crate::FieldReader;
        #[doc = "Field `ETCE` writer - ETCE Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ETCE\\[N\\]
- Endpoint #N, N is in 0..7"]
        pub type ETCE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - ERCE Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ERCE\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn erce(&self) -> ERCE_R {
                ERCE_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - ETCE Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ETCE\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            pub fn etce(&self) -> ETCE_R {
                ETCE_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - ERCE Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ERCE\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            #[must_use]
            pub fn erce(&mut self) -> ERCE_W<ENDPTCOMPLETE_SPEC> {
                ERCE_W::new(self, 0)
            }
            #[doc = "Bits 16:23 - ETCE Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. ETCE\\[N\\]
- Endpoint #N, N is in 0..7"]
            #[inline(always)]
            #[must_use]
            pub fn etce(&mut self) -> ETCE_W<ENDPTCOMPLETE_SPEC> {
                ETCE_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Endpoint Complete Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptcomplete::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptcomplete::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTCOMPLETE_SPEC;
        impl crate::RegisterSpec for ENDPTCOMPLETE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptcomplete::R`](R) reader structure"]
        impl crate::Readable for ENDPTCOMPLETE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptcomplete::W`](W) writer structure"]
        impl crate::Writable for ENDPTCOMPLETE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTCOMPLETE to value 0"]
        impl crate::Resettable for ENDPTCOMPLETE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ENDPTCTRL (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@endptctrl`]
module"]
    pub type ENDPTCTRL = crate::Reg<endptctrl::ENDPTCTRL_SPEC>;
    #[doc = "no description available"]
    pub mod endptctrl {
        #[doc = "Register `ENDPTCTRL[%s]` reader"]
        pub type R = crate::R<ENDPTCTRL_SPEC>;
        #[doc = "Register `ENDPTCTRL[%s]` writer"]
        pub type W = crate::W<ENDPTCTRL_SPEC>;
        #[doc = "Field `RXS` reader - RXS RX Endpoint Stall - Read/Write 0 End Point OK. \\[Default\\]
1 End Point Stalled This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
        pub type RXS_R = crate::BitReader;
        #[doc = "Field `RXS` writer - RXS RX Endpoint Stall - Read/Write 0 End Point OK. \\[Default\\]
1 End Point Stalled This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
        pub type RXS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXT` reader - RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
        pub type RXT_R = crate::FieldReader;
        #[doc = "Field `RXT` writer - RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
        pub type RXT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `RXR` writer - RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device."]
        pub type RXR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RXE` reader - RXE RX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
        pub type RXE_R = crate::BitReader;
        #[doc = "Field `RXE` writer - RXE RX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
        pub type RXE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXS` reader - TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
        pub type TXS_R = crate::BitReader;
        #[doc = "Field `TXS` writer - TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
        pub type TXS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXT` reader - TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
        pub type TXT_R = crate::FieldReader;
        #[doc = "Field `TXT` writer - TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
        pub type TXT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `TXR` writer - TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device."]
        pub type TXR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TXE` reader - TXE TX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
        pub type TXE_R = crate::BitReader;
        #[doc = "Field `TXE` writer - TXE TX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
        pub type TXE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - RXS RX Endpoint Stall - Read/Write 0 End Point OK. \\[Default\\]
1 End Point Stalled This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
            #[inline(always)]
            pub fn rxs(&self) -> RXS_R {
                RXS_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 2:3 - RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
            #[inline(always)]
            pub fn rxt(&self) -> RXT_R {
                RXT_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bit 7 - RXE RX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
            #[inline(always)]
            pub fn rxe(&self) -> RXE_R {
                RXE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 16 - TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
            #[inline(always)]
            pub fn txs(&self) -> TXS_R {
                TXS_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bits 18:19 - TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
            #[inline(always)]
            pub fn txt(&self) -> TXT_R {
                TXT_R::new(((self.bits >> 18) & 3) as u8)
            }
            #[doc = "Bit 23 - TXE TX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
            #[inline(always)]
            pub fn txe(&self) -> TXE_R {
                TXE_R::new(((self.bits >> 23) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - RXS RX Endpoint Stall - Read/Write 0 End Point OK. \\[Default\\]
1 End Point Stalled This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
            #[inline(always)]
            #[must_use]
            pub fn rxs(&mut self) -> RXS_W<ENDPTCTRL_SPEC> {
                RXS_W::new(self, 0)
            }
            #[doc = "Bits 2:3 - RXT RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn rxt(&mut self) -> RXT_W<ENDPTCTRL_SPEC> {
                RXT_W::new(self, 2)
            }
            #[doc = "Bit 6 - RXR RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device."]
            #[inline(always)]
            #[must_use]
            pub fn rxr(&mut self) -> RXR_W<ENDPTCTRL_SPEC> {
                RXR_W::new(self, 6)
            }
            #[doc = "Bit 7 - RXE RX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
            #[inline(always)]
            #[must_use]
            pub fn rxe(&mut self) -> RXE_W<ENDPTCTRL_SPEC> {
                RXE_W::new(self, 7)
            }
            #[doc = "Bit 16 - TXS TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. NOTE: \\[CONTROL ENDPOINT TYPES ONLY\\]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit."]
            #[inline(always)]
            #[must_use]
            pub fn txs(&mut self) -> TXS_W<ENDPTCTRL_SPEC> {
                TXS_W::new(self, 16)
            }
            #[doc = "Bits 18:19 - TXT TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn txt(&mut self) -> TXT_W<ENDPTCTRL_SPEC> {
                TXT_W::new(self, 18)
            }
            #[doc = "Bit 22 - TXR TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device."]
            #[inline(always)]
            #[must_use]
            pub fn txr(&mut self) -> TXR_W<ENDPTCTRL_SPEC> {
                TXR_W::new(self, 22)
            }
            #[doc = "Bit 23 - TXE TX Endpoint Enable 0 Disabled \\[Default\\]
1 Enabled An Endpoint should be enabled only after it has been configured."]
            #[inline(always)]
            #[must_use]
            pub fn txe(&mut self) -> TXE_W<ENDPTCTRL_SPEC> {
                TXE_W::new(self, 23)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`endptctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`endptctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ENDPTCTRL_SPEC;
        impl crate::RegisterSpec for ENDPTCTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`endptctrl::R`](R) reader structure"]
        impl crate::Readable for ENDPTCTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`endptctrl::W`](W) writer structure"]
        impl crate::Writable for ENDPTCTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ENDPTCTRL[%s]
to value 0"]
        impl crate::Resettable for ENDPTCTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "OTG_CTRL0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otg_ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`otg_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@otg_ctrl0`]
module"]
    pub type OTG_CTRL0 = crate::Reg<otg_ctrl0::OTG_CTRL0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod otg_ctrl0 {
        #[doc = "Register `OTG_CTRL0` reader"]
        pub type R = crate::R<OTG_CTRL0_SPEC>;
        #[doc = "Register `OTG_CTRL0` writer"]
        pub type W = crate::W<OTG_CTRL0_SPEC>;
        #[doc = "Field `SER_MODE_SUSPEND_EN` reader - for naneng usbphy, only switch to serial mode when suspend"]
        pub type SER_MODE_SUSPEND_EN_R = crate::BitReader;
        #[doc = "Field `SER_MODE_SUSPEND_EN` writer - for naneng usbphy, only switch to serial mode when suspend"]
        pub type SER_MODE_SUSPEND_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_OVER_CUR_DIS` reader - No description avaiable"]
        pub type OTG_OVER_CUR_DIS_R = crate::BitReader;
        #[doc = "Field `OTG_OVER_CUR_DIS` writer - No description avaiable"]
        pub type OTG_OVER_CUR_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_OVER_CUR_POL` reader - No description avaiable"]
        pub type OTG_OVER_CUR_POL_R = crate::BitReader;
        #[doc = "Field `OTG_OVER_CUR_POL` writer - No description avaiable"]
        pub type OTG_OVER_CUR_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_POWER_MASK` reader - No description avaiable"]
        pub type OTG_POWER_MASK_R = crate::BitReader;
        #[doc = "Field `OTG_POWER_MASK` writer - No description avaiable"]
        pub type OTG_POWER_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_WAKEUP_INT_ENABLE` reader - No description avaiable"]
        pub type OTG_WAKEUP_INT_ENABLE_R = crate::BitReader;
        #[doc = "Field `OTG_WAKEUP_INT_ENABLE` writer - No description avaiable"]
        pub type OTG_WAKEUP_INT_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_UTMI_RESET_SW` reader - default 1 for naneng usbphy"]
        pub type OTG_UTMI_RESET_SW_R = crate::BitReader;
        #[doc = "Field `OTG_UTMI_RESET_SW` writer - default 1 for naneng usbphy"]
        pub type OTG_UTMI_RESET_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_UTMI_SUSPENDM_SW` reader - default 0 for naneng usbphy"]
        pub type OTG_UTMI_SUSPENDM_SW_R = crate::BitReader;
        #[doc = "Field `OTG_UTMI_SUSPENDM_SW` writer - default 0 for naneng usbphy"]
        pub type OTG_UTMI_SUSPENDM_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_VBUS_SOURCE_SEL` reader - No description avaiable"]
        pub type OTG_VBUS_SOURCE_SEL_R = crate::BitReader;
        #[doc = "Field `OTG_VBUS_SOURCE_SEL` writer - No description avaiable"]
        pub type OTG_VBUS_SOURCE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_ID_WAKEUP_EN` reader - No description avaiable"]
        pub type OTG_ID_WAKEUP_EN_R = crate::BitReader;
        #[doc = "Field `OTG_ID_WAKEUP_EN` writer - No description avaiable"]
        pub type OTG_ID_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_VBUS_WAKEUP_EN` reader - No description avaiable"]
        pub type OTG_VBUS_WAKEUP_EN_R = crate::BitReader;
        #[doc = "Field `OTG_VBUS_WAKEUP_EN` writer - No description avaiable"]
        pub type OTG_VBUS_WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AUTORESUME_EN` reader - No description avaiable"]
        pub type AUTORESUME_EN_R = crate::BitReader;
        #[doc = "Field `AUTORESUME_EN` writer - No description avaiable"]
        pub type AUTORESUME_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OTG_WKDPDMCHG_EN` reader - No description avaiable"]
        pub type OTG_WKDPDMCHG_EN_R = crate::BitReader;
        #[doc = "Field `OTG_WKDPDMCHG_EN` writer - No description avaiable"]
        pub type OTG_WKDPDMCHG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 4 - for naneng usbphy, only switch to serial mode when suspend"]
            #[inline(always)]
            pub fn ser_mode_suspend_en(&self) -> SER_MODE_SUSPEND_EN_R {
                SER_MODE_SUSPEND_EN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            pub fn otg_over_cur_dis(&self) -> OTG_OVER_CUR_DIS_R {
                OTG_OVER_CUR_DIS_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            pub fn otg_over_cur_pol(&self) -> OTG_OVER_CUR_POL_R {
                OTG_OVER_CUR_POL_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - No description avaiable"]
            #[inline(always)]
            pub fn otg_power_mask(&self) -> OTG_POWER_MASK_R {
                OTG_POWER_MASK_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - No description avaiable"]
            #[inline(always)]
            pub fn otg_wakeup_int_enable(&self) -> OTG_WAKEUP_INT_ENABLE_R {
                OTG_WAKEUP_INT_ENABLE_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - default 1 for naneng usbphy"]
            #[inline(always)]
            pub fn otg_utmi_reset_sw(&self) -> OTG_UTMI_RESET_SW_R {
                OTG_UTMI_RESET_SW_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bit 12 - default 0 for naneng usbphy"]
            #[inline(always)]
            pub fn otg_utmi_suspendm_sw(&self) -> OTG_UTMI_SUSPENDM_SW_R {
                OTG_UTMI_SUSPENDM_SW_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - No description avaiable"]
            #[inline(always)]
            pub fn otg_vbus_source_sel(&self) -> OTG_VBUS_SOURCE_SEL_R {
                OTG_VBUS_SOURCE_SEL_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 16 - No description avaiable"]
            #[inline(always)]
            pub fn otg_id_wakeup_en(&self) -> OTG_ID_WAKEUP_EN_R {
                OTG_ID_WAKEUP_EN_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - No description avaiable"]
            #[inline(always)]
            pub fn otg_vbus_wakeup_en(&self) -> OTG_VBUS_WAKEUP_EN_R {
                OTG_VBUS_WAKEUP_EN_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            pub fn autoresume_en(&self) -> AUTORESUME_EN_R {
                AUTORESUME_EN_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn otg_wkdpdmchg_en(&self) -> OTG_WKDPDMCHG_EN_R {
                OTG_WKDPDMCHG_EN_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 4 - for naneng usbphy, only switch to serial mode when suspend"]
            #[inline(always)]
            #[must_use]
            pub fn ser_mode_suspend_en(&mut self) -> SER_MODE_SUSPEND_EN_W<OTG_CTRL0_SPEC> {
                SER_MODE_SUSPEND_EN_W::new(self, 4)
            }
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_over_cur_dis(&mut self) -> OTG_OVER_CUR_DIS_W<OTG_CTRL0_SPEC> {
                OTG_OVER_CUR_DIS_W::new(self, 7)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_over_cur_pol(&mut self) -> OTG_OVER_CUR_POL_W<OTG_CTRL0_SPEC> {
                OTG_OVER_CUR_POL_W::new(self, 8)
            }
            #[doc = "Bit 9 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_power_mask(&mut self) -> OTG_POWER_MASK_W<OTG_CTRL0_SPEC> {
                OTG_POWER_MASK_W::new(self, 9)
            }
            #[doc = "Bit 10 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_wakeup_int_enable(&mut self) -> OTG_WAKEUP_INT_ENABLE_W<OTG_CTRL0_SPEC> {
                OTG_WAKEUP_INT_ENABLE_W::new(self, 10)
            }
            #[doc = "Bit 11 - default 1 for naneng usbphy"]
            #[inline(always)]
            #[must_use]
            pub fn otg_utmi_reset_sw(&mut self) -> OTG_UTMI_RESET_SW_W<OTG_CTRL0_SPEC> {
                OTG_UTMI_RESET_SW_W::new(self, 11)
            }
            #[doc = "Bit 12 - default 0 for naneng usbphy"]
            #[inline(always)]
            #[must_use]
            pub fn otg_utmi_suspendm_sw(&mut self) -> OTG_UTMI_SUSPENDM_SW_W<OTG_CTRL0_SPEC> {
                OTG_UTMI_SUSPENDM_SW_W::new(self, 12)
            }
            #[doc = "Bit 13 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_vbus_source_sel(&mut self) -> OTG_VBUS_SOURCE_SEL_W<OTG_CTRL0_SPEC> {
                OTG_VBUS_SOURCE_SEL_W::new(self, 13)
            }
            #[doc = "Bit 16 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_id_wakeup_en(&mut self) -> OTG_ID_WAKEUP_EN_W<OTG_CTRL0_SPEC> {
                OTG_ID_WAKEUP_EN_W::new(self, 16)
            }
            #[doc = "Bit 17 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_vbus_wakeup_en(&mut self) -> OTG_VBUS_WAKEUP_EN_W<OTG_CTRL0_SPEC> {
                OTG_VBUS_WAKEUP_EN_W::new(self, 17)
            }
            #[doc = "Bit 19 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn autoresume_en(&mut self) -> AUTORESUME_EN_W<OTG_CTRL0_SPEC> {
                AUTORESUME_EN_W::new(self, 19)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn otg_wkdpdmchg_en(&mut self) -> OTG_WKDPDMCHG_EN_W<OTG_CTRL0_SPEC> {
                OTG_WKDPDMCHG_EN_W::new(self, 25)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`otg_ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`otg_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct OTG_CTRL0_SPEC;
        impl crate::RegisterSpec for OTG_CTRL0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`otg_ctrl0::R`](R) reader structure"]
        impl crate::Readable for OTG_CTRL0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`otg_ctrl0::W`](W) writer structure"]
        impl crate::Writable for OTG_CTRL0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets OTG_CTRL0 to value 0"]
        impl crate::Resettable for OTG_CTRL0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PHY_CTRL0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_ctrl0`]
module"]
    pub type PHY_CTRL0 = crate::Reg<phy_ctrl0::PHY_CTRL0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod phy_ctrl0 {
        #[doc = "Register `PHY_CTRL0` reader"]
        pub type R = crate::R<PHY_CTRL0_SPEC>;
        #[doc = "Register `PHY_CTRL0` writer"]
        pub type W = crate::W<PHY_CTRL0_SPEC>;
        #[doc = "Field `VBUS_VALID_OVERRIDE_EN` reader - No description avaiable"]
        pub type VBUS_VALID_OVERRIDE_EN_R = crate::BitReader;
        #[doc = "Field `VBUS_VALID_OVERRIDE_EN` writer - No description avaiable"]
        pub type VBUS_VALID_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SESS_VALID_OVERRIDE_EN` reader - No description avaiable"]
        pub type SESS_VALID_OVERRIDE_EN_R = crate::BitReader;
        #[doc = "Field `SESS_VALID_OVERRIDE_EN` writer - No description avaiable"]
        pub type SESS_VALID_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ID_DIG_OVERRIDE_EN` reader - No description avaiable"]
        pub type ID_DIG_OVERRIDE_EN_R = crate::BitReader;
        #[doc = "Field `ID_DIG_OVERRIDE_EN` writer - No description avaiable"]
        pub type ID_DIG_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `VBUS_VALID_OVERRIDE` reader - No description avaiable"]
        pub type VBUS_VALID_OVERRIDE_R = crate::BitReader;
        #[doc = "Field `VBUS_VALID_OVERRIDE` writer - No description avaiable"]
        pub type VBUS_VALID_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SESS_VALID_OVERRIDE` reader - No description avaiable"]
        pub type SESS_VALID_OVERRIDE_R = crate::BitReader;
        #[doc = "Field `SESS_VALID_OVERRIDE` writer - No description avaiable"]
        pub type SESS_VALID_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ID_DIG_OVERRIDE` reader - No description avaiable"]
        pub type ID_DIG_OVERRIDE_R = crate::BitReader;
        #[doc = "Field `ID_DIG_OVERRIDE` writer - No description avaiable"]
        pub type ID_DIG_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GPIO_ID_SEL_N` reader - No description avaiable"]
        pub type GPIO_ID_SEL_N_R = crate::BitReader;
        #[doc = "Field `GPIO_ID_SEL_N` writer - No description avaiable"]
        pub type GPIO_ID_SEL_N_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            pub fn vbus_valid_override_en(&self) -> VBUS_VALID_OVERRIDE_EN_R {
                VBUS_VALID_OVERRIDE_EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn sess_valid_override_en(&self) -> SESS_VALID_OVERRIDE_EN_R {
                SESS_VALID_OVERRIDE_EN_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            pub fn id_dig_override_en(&self) -> ID_DIG_OVERRIDE_EN_R {
                ID_DIG_OVERRIDE_EN_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 12 - No description avaiable"]
            #[inline(always)]
            pub fn vbus_valid_override(&self) -> VBUS_VALID_OVERRIDE_R {
                VBUS_VALID_OVERRIDE_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - No description avaiable"]
            #[inline(always)]
            pub fn sess_valid_override(&self) -> SESS_VALID_OVERRIDE_R {
                SESS_VALID_OVERRIDE_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bit 14 - No description avaiable"]
            #[inline(always)]
            pub fn id_dig_override(&self) -> ID_DIG_OVERRIDE_R {
                ID_DIG_OVERRIDE_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            pub fn gpio_id_sel_n(&self) -> GPIO_ID_SEL_N_R {
                GPIO_ID_SEL_N_R::new(((self.bits >> 25) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn vbus_valid_override_en(&mut self) -> VBUS_VALID_OVERRIDE_EN_W<PHY_CTRL0_SPEC> {
                VBUS_VALID_OVERRIDE_EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn sess_valid_override_en(&mut self) -> SESS_VALID_OVERRIDE_EN_W<PHY_CTRL0_SPEC> {
                SESS_VALID_OVERRIDE_EN_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn id_dig_override_en(&mut self) -> ID_DIG_OVERRIDE_EN_W<PHY_CTRL0_SPEC> {
                ID_DIG_OVERRIDE_EN_W::new(self, 2)
            }
            #[doc = "Bit 12 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn vbus_valid_override(&mut self) -> VBUS_VALID_OVERRIDE_W<PHY_CTRL0_SPEC> {
                VBUS_VALID_OVERRIDE_W::new(self, 12)
            }
            #[doc = "Bit 13 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn sess_valid_override(&mut self) -> SESS_VALID_OVERRIDE_W<PHY_CTRL0_SPEC> {
                SESS_VALID_OVERRIDE_W::new(self, 13)
            }
            #[doc = "Bit 14 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn id_dig_override(&mut self) -> ID_DIG_OVERRIDE_W<PHY_CTRL0_SPEC> {
                ID_DIG_OVERRIDE_W::new(self, 14)
            }
            #[doc = "Bit 25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn gpio_id_sel_n(&mut self) -> GPIO_ID_SEL_N_W<PHY_CTRL0_SPEC> {
                GPIO_ID_SEL_N_W::new(self, 25)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHY_CTRL0_SPEC;
        impl crate::RegisterSpec for PHY_CTRL0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phy_ctrl0::R`](R) reader structure"]
        impl crate::Readable for PHY_CTRL0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phy_ctrl0::W`](W) writer structure"]
        impl crate::Writable for PHY_CTRL0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PHY_CTRL0 to value 0"]
        impl crate::Resettable for PHY_CTRL0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PHY_CTRL1 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_ctrl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_ctrl1`]
module"]
    pub type PHY_CTRL1 = crate::Reg<phy_ctrl1::PHY_CTRL1_SPEC>;
    #[doc = "No description avaiable"]
    pub mod phy_ctrl1 {
        #[doc = "Register `PHY_CTRL1` reader"]
        pub type R = crate::R<PHY_CTRL1_SPEC>;
        #[doc = "Register `PHY_CTRL1` writer"]
        pub type W = crate::W<PHY_CTRL1_SPEC>;
        #[doc = "Field `UTMI_OTG_SUSPENDM` reader - OTG suspend, not utmi_suspendm"]
        pub type UTMI_OTG_SUSPENDM_R = crate::BitReader;
        #[doc = "Field `UTMI_OTG_SUSPENDM` writer - OTG suspend, not utmi_suspendm"]
        pub type UTMI_OTG_SUSPENDM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UTMI_CFG_RST_N` reader - No description avaiable"]
        pub type UTMI_CFG_RST_N_R = crate::BitReader;
        #[doc = "Field `UTMI_CFG_RST_N` writer - No description avaiable"]
        pub type UTMI_CFG_RST_N_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 1 - OTG suspend, not utmi_suspendm"]
            #[inline(always)]
            pub fn utmi_otg_suspendm(&self) -> UTMI_OTG_SUSPENDM_R {
                UTMI_OTG_SUSPENDM_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            pub fn utmi_cfg_rst_n(&self) -> UTMI_CFG_RST_N_R {
                UTMI_CFG_RST_N_R::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 1 - OTG suspend, not utmi_suspendm"]
            #[inline(always)]
            #[must_use]
            pub fn utmi_otg_suspendm(&mut self) -> UTMI_OTG_SUSPENDM_W<PHY_CTRL1_SPEC> {
                UTMI_OTG_SUSPENDM_W::new(self, 1)
            }
            #[doc = "Bit 20 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn utmi_cfg_rst_n(&mut self) -> UTMI_CFG_RST_N_W<PHY_CTRL1_SPEC> {
                UTMI_CFG_RST_N_W::new(self, 20)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHY_CTRL1_SPEC;
        impl crate::RegisterSpec for PHY_CTRL1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phy_ctrl1::R`](R) reader structure"]
        impl crate::Readable for PHY_CTRL1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phy_ctrl1::W`](W) writer structure"]
        impl crate::Writable for PHY_CTRL1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PHY_CTRL1 to value 0"]
        impl crate::Resettable for PHY_CTRL1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TOP_STATUS (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`top_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@top_status`]
module"]
    pub type TOP_STATUS = crate::Reg<top_status::TOP_STATUS_SPEC>;
    #[doc = "No description avaiable"]
    pub mod top_status {
        #[doc = "Register `TOP_STATUS` reader"]
        pub type R = crate::R<TOP_STATUS_SPEC>;
        #[doc = "Register `TOP_STATUS` writer"]
        pub type W = crate::W<TOP_STATUS_SPEC>;
        #[doc = "Field `WAKEUP_INT_STATUS` reader - No description avaiable"]
        pub type WAKEUP_INT_STATUS_R = crate::BitReader;
        #[doc = "Field `WAKEUP_INT_STATUS` writer - No description avaiable"]
        pub type WAKEUP_INT_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 31 - No description avaiable"]
            #[inline(always)]
            pub fn wakeup_int_status(&self) -> WAKEUP_INT_STATUS_R {
                WAKEUP_INT_STATUS_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn wakeup_int_status(&mut self) -> WAKEUP_INT_STATUS_W<TOP_STATUS_SPEC> {
                WAKEUP_INT_STATUS_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`top_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`top_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TOP_STATUS_SPEC;
        impl crate::RegisterSpec for TOP_STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`top_status::R`](R) reader structure"]
        impl crate::Readable for TOP_STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`top_status::W`](W) writer structure"]
        impl crate::Writable for TOP_STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TOP_STATUS to value 0"]
        impl crate::Resettable for TOP_STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PHY_STATUS (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@phy_status`]
module"]
    pub type PHY_STATUS = crate::Reg<phy_status::PHY_STATUS_SPEC>;
    #[doc = "No description avaiable"]
    pub mod phy_status {
        #[doc = "Register `PHY_STATUS` reader"]
        pub type R = crate::R<PHY_STATUS_SPEC>;
        #[doc = "Register `PHY_STATUS` writer"]
        pub type W = crate::W<PHY_STATUS_SPEC>;
        #[doc = "Field `VBUS_VALID` reader - No description avaiable"]
        pub type VBUS_VALID_R = crate::BitReader;
        #[doc = "Field `VBUS_VALID` writer - No description avaiable"]
        pub type VBUS_VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `UTMI_SESS_VALID` reader - No description avaiable"]
        pub type UTMI_SESS_VALID_R = crate::BitReader;
        #[doc = "Field `UTMI_SESS_VALID` writer - No description avaiable"]
        pub type UTMI_SESS_VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ID_DIG` reader - No description avaiable"]
        pub type ID_DIG_R = crate::BitReader;
        #[doc = "Field `ID_DIG` writer - No description avaiable"]
        pub type ID_DIG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HOST_DISCONNECT` reader - No description avaiable"]
        pub type HOST_DISCONNECT_R = crate::BitReader;
        #[doc = "Field `HOST_DISCONNECT` writer - No description avaiable"]
        pub type HOST_DISCONNECT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LINE_STATE` reader - No description avaiable"]
        pub type LINE_STATE_R = crate::FieldReader;
        #[doc = "Field `LINE_STATE` writer - No description avaiable"]
        pub type LINE_STATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `UTMI_CLK_VALID` reader - No description avaiable"]
        pub type UTMI_CLK_VALID_R = crate::BitReader;
        #[doc = "Field `UTMI_CLK_VALID` writer - No description avaiable"]
        pub type UTMI_CLK_VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            pub fn vbus_valid(&self) -> VBUS_VALID_R {
                VBUS_VALID_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            pub fn utmi_sess_valid(&self) -> UTMI_SESS_VALID_R {
                UTMI_SESS_VALID_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 4 - No description avaiable"]
            #[inline(always)]
            pub fn id_dig(&self) -> ID_DIG_R {
                ID_DIG_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - No description avaiable"]
            #[inline(always)]
            pub fn host_disconnect(&self) -> HOST_DISCONNECT_R {
                HOST_DISCONNECT_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bits 6:7 - No description avaiable"]
            #[inline(always)]
            pub fn line_state(&self) -> LINE_STATE_R {
                LINE_STATE_R::new(((self.bits >> 6) & 3) as u8)
            }
            #[doc = "Bit 31 - No description avaiable"]
            #[inline(always)]
            pub fn utmi_clk_valid(&self) -> UTMI_CLK_VALID_R {
                UTMI_CLK_VALID_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn vbus_valid(&mut self) -> VBUS_VALID_W<PHY_STATUS_SPEC> {
                VBUS_VALID_W::new(self, 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn utmi_sess_valid(&mut self) -> UTMI_SESS_VALID_W<PHY_STATUS_SPEC> {
                UTMI_SESS_VALID_W::new(self, 2)
            }
            #[doc = "Bit 4 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn id_dig(&mut self) -> ID_DIG_W<PHY_STATUS_SPEC> {
                ID_DIG_W::new(self, 4)
            }
            #[doc = "Bit 5 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn host_disconnect(&mut self) -> HOST_DISCONNECT_W<PHY_STATUS_SPEC> {
                HOST_DISCONNECT_W::new(self, 5)
            }
            #[doc = "Bits 6:7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn line_state(&mut self) -> LINE_STATE_W<PHY_STATUS_SPEC> {
                LINE_STATE_W::new(self, 6)
            }
            #[doc = "Bit 31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn utmi_clk_valid(&mut self) -> UTMI_CLK_VALID_W<PHY_STATUS_SPEC> {
                UTMI_CLK_VALID_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`phy_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`phy_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PHY_STATUS_SPEC;
        impl crate::RegisterSpec for PHY_STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`phy_status::R`](R) reader structure"]
        impl crate::Readable for PHY_STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`phy_status::W`](W) writer structure"]
        impl crate::Writable for PHY_STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PHY_STATUS to value 0"]
        impl crate::Resettable for PHY_STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "SDP"]
pub struct SDP {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SDP {}
impl SDP {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const sdp::RegisterBlock = 0xf304_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const sdp::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SDP {
    type Target = sdp::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SDP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SDP").finish()
    }
}
#[doc = "SDP"]
pub mod sdp {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        sdpcr: SDPCR,
        modctrl: MODCTRL,
        pktcnt: PKTCNT,
        sta: STA,
        keyaddr: KEYADDR,
        keydat: KEYDAT,
        ciphiv: [CIPHIV; 4],
        haswrd: [HASWRD; 8],
        cmdptr: CMDPTR,
        npktptr: NPKTPTR,
        pktctl: PKTCTL,
        pktsrc: PKTSRC,
        pktdst: PKTDST,
        pktbuf: PKTBUF,
    }
    impl RegisterBlock {
        #[doc = "0x00 - SDP control register"]
        #[inline(always)]
        pub const fn sdpcr(&self) -> &SDPCR {
            &self.sdpcr
        }
        #[doc = "0x04 - Mod control register."]
        #[inline(always)]
        pub const fn modctrl(&self) -> &MODCTRL {
            &self.modctrl
        }
        #[doc = "0x08 - packet counter registers."]
        #[inline(always)]
        pub const fn pktcnt(&self) -> &PKTCNT {
            &self.pktcnt
        }
        #[doc = "0x0c - Status Registers"]
        #[inline(always)]
        pub const fn sta(&self) -> &STA {
            &self.sta
        }
        #[doc = "0x10 - Key Address"]
        #[inline(always)]
        pub const fn keyaddr(&self) -> &KEYADDR {
            &self.keyaddr
        }
        #[doc = "0x14 - Key Data"]
        #[inline(always)]
        pub const fn keydat(&self) -> &KEYDAT {
            &self.keydat
        }
        #[doc = "0x18..0x28 - no description available"]
        #[inline(always)]
        pub const fn ciphiv(&self, n: usize) -> &CIPHIV {
            &self.ciphiv[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x18..0x28 - no description available"]
        #[inline(always)]
        pub fn ciphiv_iter(&self) -> impl Iterator<Item = &CIPHIV> {
            self.ciphiv.iter()
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn ciphivciphiv0(&self) -> &CIPHIV {
            self.ciphiv(0)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn ciphivciphiv1(&self) -> &CIPHIV {
            self.ciphiv(1)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn ciphivciphiv2(&self) -> &CIPHIV {
            self.ciphiv(2)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn ciphivciphiv3(&self) -> &CIPHIV {
            self.ciphiv(3)
        }
        #[doc = "0x28..0x48 - no description available"]
        #[inline(always)]
        pub const fn haswrd(&self, n: usize) -> &HASWRD {
            &self.haswrd[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x28..0x48 - no description available"]
        #[inline(always)]
        pub fn haswrd_iter(&self) -> impl Iterator<Item = &HASWRD> {
            self.haswrd.iter()
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd0(&self) -> &HASWRD {
            self.haswrd(0)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd1(&self) -> &HASWRD {
            self.haswrd(1)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd2(&self) -> &HASWRD {
            self.haswrd(2)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd3(&self) -> &HASWRD {
            self.haswrd(3)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd4(&self) -> &HASWRD {
            self.haswrd(4)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd5(&self) -> &HASWRD {
            self.haswrd(5)
        }
        #[doc = "0x40 - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd6(&self) -> &HASWRD {
            self.haswrd(6)
        }
        #[doc = "0x44 - no description available"]
        #[inline(always)]
        pub const fn haswrdhaswrd7(&self) -> &HASWRD {
            self.haswrd(7)
        }
        #[doc = "0x48 - Command Pointer"]
        #[inline(always)]
        pub const fn cmdptr(&self) -> &CMDPTR {
            &self.cmdptr
        }
        #[doc = "0x4c - Next Packet Address Pointer"]
        #[inline(always)]
        pub const fn npktptr(&self) -> &NPKTPTR {
            &self.npktptr
        }
        #[doc = "0x50 - Packet Control Registers"]
        #[inline(always)]
        pub const fn pktctl(&self) -> &PKTCTL {
            &self.pktctl
        }
        #[doc = "0x54 - Packet Memory Source Address"]
        #[inline(always)]
        pub const fn pktsrc(&self) -> &PKTSRC {
            &self.pktsrc
        }
        #[doc = "0x58 - Packet Memory Destination Address"]
        #[inline(always)]
        pub const fn pktdst(&self) -> &PKTDST {
            &self.pktdst
        }
        #[doc = "0x5c - Packet buffer size."]
        #[inline(always)]
        pub const fn pktbuf(&self) -> &PKTBUF {
            &self.pktbuf
        }
    }
    #[doc = "SDPCR (rw) register accessor: SDP control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdpcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdpcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sdpcr`]
module"]
    pub type SDPCR = crate::Reg<sdpcr::SDPCR_SPEC>;
    #[doc = "SDP control register"]
    pub mod sdpcr {
        #[doc = "Register `SDPCR` reader"]
        pub type R = crate::R<SDPCR_SPEC>;
        #[doc = "Register `SDPCR` writer"]
        pub type W = crate::W<SDPCR_SPEC>;
        #[doc = "Field `INTEN` reader - Interrupt Enablement, controlled by SW. 1, SDP interrupt is enabled. 0, SDP interrupt is disabled."]
        pub type INTEN_R = crate::BitReader;
        #[doc = "Field `INTEN` writer - Interrupt Enablement, controlled by SW. 1, SDP interrupt is enabled. 0, SDP interrupt is disabled."]
        pub type INTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RDSCEN` reader - when set to \"1\", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) when set to \"0\", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR)"]
        pub type RDSCEN_R = crate::BitReader;
        #[doc = "Field `RDSCEN` writer - when set to \"1\", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) when set to \"0\", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR)"]
        pub type RDSCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TSTPKT0IRQ` reader - Test purpose for interrupt when Packet counter reachs \"0\", but CHAIN=1 in the current packet."]
        pub type TSTPKT0IRQ_R = crate::BitReader;
        #[doc = "Field `TSTPKT0IRQ` writer - Test purpose for interrupt when Packet counter reachs \"0\", but CHAIN=1 in the current packet."]
        pub type TSTPKT0IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DCRPDI` reader - Decryption Disable bit, Write to 1 to disable the decryption."]
        pub type DCRPDI_R = crate::BitReader;
        #[doc = "Field `DCRPDI` writer - Decryption Disable bit, Write to 1 to disable the decryption."]
        pub type DCRPDI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONFEN` reader - Constant Fill to memory, controlled by SW. 1, Constant fill is Enabled. 0, Constant fill is Disabled."]
        pub type CONFEN_R = crate::BitReader;
        #[doc = "Field `CONFEN` writer - Constant Fill to memory, controlled by SW. 1, Constant fill is Enabled. 0, Constant fill is Disabled."]
        pub type CONFEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MCPEN` reader - Memory Copy Enablement, controlled by SW. 1, Memory copy is Enabled. 0, Memory copy is Disabled."]
        pub type MCPEN_R = crate::BitReader;
        #[doc = "Field `MCPEN` writer - Memory Copy Enablement, controlled by SW. 1, Memory copy is Enabled. 0, Memory copy is Disabled."]
        pub type MCPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HASHEN` reader - HASH Enablement, controlled by SW. 1, HASH is Enabled. 0, HASH is Disabled."]
        pub type HASHEN_R = crate::BitReader;
        #[doc = "Field `HASHEN` writer - HASH Enablement, controlled by SW. 1, HASH is Enabled. 0, HASH is Disabled."]
        pub type HASHEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CIPHEN` reader - Cipher Enablement, controlled by SW. 1, Cipher is Enabled. 0, Cipher is Disabled."]
        pub type CIPHEN_R = crate::BitReader;
        #[doc = "Field `CIPHEN` writer - Cipher Enablement, controlled by SW. 1, Cipher is Enabled. 0, Cipher is Disabled."]
        pub type CIPHEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HASDIS` reader - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. 1, HASH is disabled in this chip. 0, HASH is enabled in this chip."]
        pub type HASDIS_R = crate::BitReader;
        #[doc = "Field `CIPDIS` reader - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. 1, Cipher is disabled in this chip. 0, Cipher is enabled in this chip."]
        pub type CIPDIS_R = crate::BitReader;
        #[doc = "Field `CLKGAT` reader - Clock Gate for the SDP main logic. Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block."]
        pub type CLKGAT_R = crate::BitReader;
        #[doc = "Field `CLKGAT` writer - Clock Gate for the SDP main logic. Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block."]
        pub type CLKGAT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SFTRST` reader - soft reset. Write 1 then 0, to reset the SDP block."]
        pub type SFTRST_R = crate::BitReader;
        #[doc = "Field `SFTRST` writer - soft reset. Write 1 then 0, to reset the SDP block."]
        pub type SFTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Interrupt Enablement, controlled by SW. 1, SDP interrupt is enabled. 0, SDP interrupt is disabled."]
            #[inline(always)]
            pub fn inten(&self) -> INTEN_R {
                INTEN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 8 - when set to \"1\", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) when set to \"0\", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR)"]
            #[inline(always)]
            pub fn rdscen(&self) -> RDSCEN_R {
                RDSCEN_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 17 - Test purpose for interrupt when Packet counter reachs \"0\", but CHAIN=1 in the current packet."]
            #[inline(always)]
            pub fn tstpkt0irq(&self) -> TSTPKT0IRQ_R {
                TSTPKT0IRQ_R::new(((self.bits >> 17) & 1) != 0)
            }
            #[doc = "Bit 19 - Decryption Disable bit, Write to 1 to disable the decryption."]
            #[inline(always)]
            pub fn dcrpdi(&self) -> DCRPDI_R {
                DCRPDI_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bit 20 - Constant Fill to memory, controlled by SW. 1, Constant fill is Enabled. 0, Constant fill is Disabled."]
            #[inline(always)]
            pub fn confen(&self) -> CONFEN_R {
                CONFEN_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 21 - Memory Copy Enablement, controlled by SW. 1, Memory copy is Enabled. 0, Memory copy is Disabled."]
            #[inline(always)]
            pub fn mcpen(&self) -> MCPEN_R {
                MCPEN_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - HASH Enablement, controlled by SW. 1, HASH is Enabled. 0, HASH is Disabled."]
            #[inline(always)]
            pub fn hashen(&self) -> HASHEN_R {
                HASHEN_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - Cipher Enablement, controlled by SW. 1, Cipher is Enabled. 0, Cipher is Disabled."]
            #[inline(always)]
            pub fn ciphen(&self) -> CIPHEN_R {
                CIPHEN_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 28 - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. 1, HASH is disabled in this chip. 0, HASH is enabled in this chip."]
            #[inline(always)]
            pub fn hasdis(&self) -> HASDIS_R {
                HASDIS_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. 1, Cipher is disabled in this chip. 0, Cipher is enabled in this chip."]
            #[inline(always)]
            pub fn cipdis(&self) -> CIPDIS_R {
                CIPDIS_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - Clock Gate for the SDP main logic. Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block."]
            #[inline(always)]
            pub fn clkgat(&self) -> CLKGAT_R {
                CLKGAT_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - soft reset. Write 1 then 0, to reset the SDP block."]
            #[inline(always)]
            pub fn sftrst(&self) -> SFTRST_R {
                SFTRST_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Interrupt Enablement, controlled by SW. 1, SDP interrupt is enabled. 0, SDP interrupt is disabled."]
            #[inline(always)]
            #[must_use]
            pub fn inten(&mut self) -> INTEN_W<SDPCR_SPEC> {
                INTEN_W::new(self, 0)
            }
            #[doc = "Bit 8 - when set to \"1\", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) when set to \"0\", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR)"]
            #[inline(always)]
            #[must_use]
            pub fn rdscen(&mut self) -> RDSCEN_W<SDPCR_SPEC> {
                RDSCEN_W::new(self, 8)
            }
            #[doc = "Bit 17 - Test purpose for interrupt when Packet counter reachs \"0\", but CHAIN=1 in the current packet."]
            #[inline(always)]
            #[must_use]
            pub fn tstpkt0irq(&mut self) -> TSTPKT0IRQ_W<SDPCR_SPEC> {
                TSTPKT0IRQ_W::new(self, 17)
            }
            #[doc = "Bit 19 - Decryption Disable bit, Write to 1 to disable the decryption."]
            #[inline(always)]
            #[must_use]
            pub fn dcrpdi(&mut self) -> DCRPDI_W<SDPCR_SPEC> {
                DCRPDI_W::new(self, 19)
            }
            #[doc = "Bit 20 - Constant Fill to memory, controlled by SW. 1, Constant fill is Enabled. 0, Constant fill is Disabled."]
            #[inline(always)]
            #[must_use]
            pub fn confen(&mut self) -> CONFEN_W<SDPCR_SPEC> {
                CONFEN_W::new(self, 20)
            }
            #[doc = "Bit 21 - Memory Copy Enablement, controlled by SW. 1, Memory copy is Enabled. 0, Memory copy is Disabled."]
            #[inline(always)]
            #[must_use]
            pub fn mcpen(&mut self) -> MCPEN_W<SDPCR_SPEC> {
                MCPEN_W::new(self, 21)
            }
            #[doc = "Bit 22 - HASH Enablement, controlled by SW. 1, HASH is Enabled. 0, HASH is Disabled."]
            #[inline(always)]
            #[must_use]
            pub fn hashen(&mut self) -> HASHEN_W<SDPCR_SPEC> {
                HASHEN_W::new(self, 22)
            }
            #[doc = "Bit 23 - Cipher Enablement, controlled by SW. 1, Cipher is Enabled. 0, Cipher is Disabled."]
            #[inline(always)]
            #[must_use]
            pub fn ciphen(&mut self) -> CIPHEN_W<SDPCR_SPEC> {
                CIPHEN_W::new(self, 23)
            }
            #[doc = "Bit 30 - Clock Gate for the SDP main logic. Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block."]
            #[inline(always)]
            #[must_use]
            pub fn clkgat(&mut self) -> CLKGAT_W<SDPCR_SPEC> {
                CLKGAT_W::new(self, 30)
            }
            #[doc = "Bit 31 - soft reset. Write 1 then 0, to reset the SDP block."]
            #[inline(always)]
            #[must_use]
            pub fn sftrst(&mut self) -> SFTRST_W<SDPCR_SPEC> {
                SFTRST_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "SDP control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sdpcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sdpcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SDPCR_SPEC;
        impl crate::RegisterSpec for SDPCR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sdpcr::R`](R) reader structure"]
        impl crate::Readable for SDPCR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sdpcr::W`](W) writer structure"]
        impl crate::Writable for SDPCR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SDPCR to value 0x3000_0000"]
        impl crate::Resettable for SDPCR_SPEC {
            const RESET_VALUE: u32 = 0x3000_0000;
        }
    }
    #[doc = "MODCTRL (rw) register accessor: Mod control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`modctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`modctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@modctrl`]
module"]
    pub type MODCTRL = crate::Reg<modctrl::MODCTRL_SPEC>;
    #[doc = "Mod control register."]
    pub mod modctrl {
        #[doc = "Register `MODCTRL` reader"]
        pub type R = crate::R<MODCTRL_SPEC>;
        #[doc = "Register `MODCTRL` writer"]
        pub type W = crate::W<MODCTRL_SPEC>;
        #[doc = "Field `KEYSWP` reader - Decide whether the SDP byteswaps the Key (big-endian data). When all bits are set, the data is assumed to be in the big-endian format"]
        pub type KEYSWP_R = crate::FieldReader;
        #[doc = "Field `KEYSWP` writer - Decide whether the SDP byteswaps the Key (big-endian data). When all bits are set, the data is assumed to be in the big-endian format"]
        pub type KEYSWP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `DOUTSWP` reader - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
        pub type DOUTSWP_R = crate::FieldReader;
        #[doc = "Field `DOUTSWP` writer - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
        pub type DOUTSWP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `DINSWP` reader - Decide whether the SDP byteswaps the input data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
        pub type DINSWP_R = crate::FieldReader;
        #[doc = "Field `DINSWP` writer - Decide whether the SDP byteswaps the input data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
        pub type DINSWP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `HASOUT` reader - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. 0 INPUT HASH 1 OUTPUT HASH"]
        pub type HASOUT_R = crate::BitReader;
        #[doc = "Field `HASOUT` writer - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. 0 INPUT HASH 1 OUTPUT HASH"]
        pub type HASOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HASCHK` reader - HASH Check Enable Bit. 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words."]
        pub type HASCHK_R = crate::BitReader;
        #[doc = "Field `HASCHK` writer - HASH Check Enable Bit. 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words."]
        pub type HASCHK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CRCEN` reader - CRC enable. 1x1, CRC is enabled. 1x0, CRC is disabled."]
        pub type CRCEN_R = crate::BitReader;
        #[doc = "Field `CRCEN` writer - CRC enable. 1x1, CRC is enabled. 1x0, CRC is disabled."]
        pub type CRCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HASALG` reader - HASH Algorithem selection. 0x0 SHA1 — 0x1 CRC32 — 0x2 SHA256 —"]
        pub type HASALG_R = crate::FieldReader;
        #[doc = "Field `HASALG` writer - HASH Algorithem selection. 0x0 SHA1 — 0x1 CRC32 — 0x2 SHA256 —"]
        pub type HASALG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `AESDIR` reader - AES direction 1x1, AES Decryption 1x0, AES Encryption."]
        pub type AESDIR_R = crate::BitReader;
        #[doc = "Field `AESDIR` writer - AES direction 1x1, AES Decryption 1x0, AES Encryption."]
        pub type AESDIR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AESKS` reader - AES Key Selection. These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. .... 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. 0x20: kman_sk0\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk0\\[255:0\\]
as AES key. 0x21: kman_sk0\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x22: kman_sk1\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk1\\[255:0\\]
as AES key. 0x23: kman_sk1\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x24: kman_sk2\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk2\\[255:0\\]
as AES key. 0x25: kman_sk2\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x26: kman_sk3\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk3\\[255:0\\]
as AES key. 0x27: kman_sk3\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x30: exip0_key\\[127:0\\]
from OTP for AES128; AES256 will use exip0_key\\[255:0\\]
as AES key. 0x31: exip0_key\\[255:128\\]
from OTP for AES128; not valid for AES256. 0x32: exip1_key\\[127:0\\]
from OTP for AES128; AES256 will use exip1_key\\[255:0\\]
as AES key. 0x33: exip1_key\\[255:128\\]
from OTP for AES128; not valid for AES256. Other values, reserved."]
        pub type AESKS_R = crate::FieldReader;
        #[doc = "Field `AESKS` writer - AES Key Selection. These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. .... 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. 0x20: kman_sk0\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk0\\[255:0\\]
as AES key. 0x21: kman_sk0\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x22: kman_sk1\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk1\\[255:0\\]
as AES key. 0x23: kman_sk1\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x24: kman_sk2\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk2\\[255:0\\]
as AES key. 0x25: kman_sk2\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x26: kman_sk3\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk3\\[255:0\\]
as AES key. 0x27: kman_sk3\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x30: exip0_key\\[127:0\\]
from OTP for AES128; AES256 will use exip0_key\\[255:0\\]
as AES key. 0x31: exip0_key\\[255:128\\]
from OTP for AES128; not valid for AES256. 0x32: exip1_key\\[127:0\\]
from OTP for AES128; AES256 will use exip1_key\\[255:0\\]
as AES key. 0x33: exip1_key\\[255:128\\]
from OTP for AES128; not valid for AES256. Other values, reserved."]
        pub type AESKS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
        #[doc = "Field `AESMOD` reader - AES mode selection. 0x0 = ECB; 0x1 = CBC; Others, reserved."]
        pub type AESMOD_R = crate::FieldReader;
        #[doc = "Field `AESMOD` writer - AES mode selection. 0x0 = ECB; 0x1 = CBC; Others, reserved."]
        pub type AESMOD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `AESALG` reader - AES algorithem selection. 0x0 = AES 128; 0x1 = AES 256; 0x8 = SM4； Others, reserved."]
        pub type AESALG_R = crate::FieldReader;
        #[doc = "Field `AESALG` writer - AES algorithem selection. 0x0 = AES 128; 0x1 = AES 256; 0x8 = SM4； Others, reserved."]
        pub type AESALG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:1 - Decide whether the SDP byteswaps the Key (big-endian data). When all bits are set, the data is assumed to be in the big-endian format"]
            #[inline(always)]
            pub fn keyswp(&self) -> KEYSWP_R {
                KEYSWP_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bits 2:3 - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
            #[inline(always)]
            pub fn doutswp(&self) -> DOUTSWP_R {
                DOUTSWP_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bits 4:5 - Decide whether the SDP byteswaps the input data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
            #[inline(always)]
            pub fn dinswp(&self) -> DINSWP_R {
                DINSWP_R::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bit 9 - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. 0 INPUT HASH 1 OUTPUT HASH"]
            #[inline(always)]
            pub fn hasout(&self) -> HASOUT_R {
                HASOUT_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bit 10 - HASH Check Enable Bit. 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words."]
            #[inline(always)]
            pub fn haschk(&self) -> HASCHK_R {
                HASCHK_R::new(((self.bits >> 10) & 1) != 0)
            }
            #[doc = "Bit 11 - CRC enable. 1x1, CRC is enabled. 1x0, CRC is disabled."]
            #[inline(always)]
            pub fn crcen(&self) -> CRCEN_R {
                CRCEN_R::new(((self.bits >> 11) & 1) != 0)
            }
            #[doc = "Bits 12:15 - HASH Algorithem selection. 0x0 SHA1 — 0x1 CRC32 — 0x2 SHA256 —"]
            #[inline(always)]
            pub fn hasalg(&self) -> HASALG_R {
                HASALG_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            #[doc = "Bit 16 - AES direction 1x1, AES Decryption 1x0, AES Encryption."]
            #[inline(always)]
            pub fn aesdir(&self) -> AESDIR_R {
                AESDIR_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bits 18:23 - AES Key Selection. These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. .... 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. 0x20: kman_sk0\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk0\\[255:0\\]
as AES key. 0x21: kman_sk0\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x22: kman_sk1\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk1\\[255:0\\]
as AES key. 0x23: kman_sk1\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x24: kman_sk2\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk2\\[255:0\\]
as AES key. 0x25: kman_sk2\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x26: kman_sk3\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk3\\[255:0\\]
as AES key. 0x27: kman_sk3\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x30: exip0_key\\[127:0\\]
from OTP for AES128; AES256 will use exip0_key\\[255:0\\]
as AES key. 0x31: exip0_key\\[255:128\\]
from OTP for AES128; not valid for AES256. 0x32: exip1_key\\[127:0\\]
from OTP for AES128; AES256 will use exip1_key\\[255:0\\]
as AES key. 0x33: exip1_key\\[255:128\\]
from OTP for AES128; not valid for AES256. Other values, reserved."]
            #[inline(always)]
            pub fn aesks(&self) -> AESKS_R {
                AESKS_R::new(((self.bits >> 18) & 0x3f) as u8)
            }
            #[doc = "Bits 24:27 - AES mode selection. 0x0 = ECB; 0x1 = CBC; Others, reserved."]
            #[inline(always)]
            pub fn aesmod(&self) -> AESMOD_R {
                AESMOD_R::new(((self.bits >> 24) & 0x0f) as u8)
            }
            #[doc = "Bits 28:31 - AES algorithem selection. 0x0 = AES 128; 0x1 = AES 256; 0x8 = SM4； Others, reserved."]
            #[inline(always)]
            pub fn aesalg(&self) -> AESALG_R {
                AESALG_R::new(((self.bits >> 28) & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - Decide whether the SDP byteswaps the Key (big-endian data). When all bits are set, the data is assumed to be in the big-endian format"]
            #[inline(always)]
            #[must_use]
            pub fn keyswp(&mut self) -> KEYSWP_W<MODCTRL_SPEC> {
                KEYSWP_W::new(self, 0)
            }
            #[doc = "Bits 2:3 - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
            #[inline(always)]
            #[must_use]
            pub fn doutswp(&mut self) -> DOUTSWP_W<MODCTRL_SPEC> {
                DOUTSWP_W::new(self, 2)
            }
            #[doc = "Bits 4:5 - Decide whether the SDP byteswaps the input data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format"]
            #[inline(always)]
            #[must_use]
            pub fn dinswp(&mut self) -> DINSWP_W<MODCTRL_SPEC> {
                DINSWP_W::new(self, 4)
            }
            #[doc = "Bit 9 - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. 0 INPUT HASH 1 OUTPUT HASH"]
            #[inline(always)]
            #[must_use]
            pub fn hasout(&mut self) -> HASOUT_W<MODCTRL_SPEC> {
                HASOUT_W::new(self, 9)
            }
            #[doc = "Bit 10 - HASH Check Enable Bit. 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words."]
            #[inline(always)]
            #[must_use]
            pub fn haschk(&mut self) -> HASCHK_W<MODCTRL_SPEC> {
                HASCHK_W::new(self, 10)
            }
            #[doc = "Bit 11 - CRC enable. 1x1, CRC is enabled. 1x0, CRC is disabled."]
            #[inline(always)]
            #[must_use]
            pub fn crcen(&mut self) -> CRCEN_W<MODCTRL_SPEC> {
                CRCEN_W::new(self, 11)
            }
            #[doc = "Bits 12:15 - HASH Algorithem selection. 0x0 SHA1 — 0x1 CRC32 — 0x2 SHA256 —"]
            #[inline(always)]
            #[must_use]
            pub fn hasalg(&mut self) -> HASALG_W<MODCTRL_SPEC> {
                HASALG_W::new(self, 12)
            }
            #[doc = "Bit 16 - AES direction 1x1, AES Decryption 1x0, AES Encryption."]
            #[inline(always)]
            #[must_use]
            pub fn aesdir(&mut self) -> AESDIR_W<MODCTRL_SPEC> {
                AESDIR_W::new(self, 16)
            }
            #[doc = "Bits 18:23 - AES Key Selection. These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. .... 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. 0x20: kman_sk0\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk0\\[255:0\\]
as AES key. 0x21: kman_sk0\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x22: kman_sk1\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk1\\[255:0\\]
as AES key. 0x23: kman_sk1\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x24: kman_sk2\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk2\\[255:0\\]
as AES key. 0x25: kman_sk2\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x26: kman_sk3\\[127:0\\]
from the key manager for AES128; AES256 will use kman_sk3\\[255:0\\]
as AES key. 0x27: kman_sk3\\[255:128\\]
from the key manager for AES128; not valid for AES256. 0x30: exip0_key\\[127:0\\]
from OTP for AES128; AES256 will use exip0_key\\[255:0\\]
as AES key. 0x31: exip0_key\\[255:128\\]
from OTP for AES128; not valid for AES256. 0x32: exip1_key\\[127:0\\]
from OTP for AES128; AES256 will use exip1_key\\[255:0\\]
as AES key. 0x33: exip1_key\\[255:128\\]
from OTP for AES128; not valid for AES256. Other values, reserved."]
            #[inline(always)]
            #[must_use]
            pub fn aesks(&mut self) -> AESKS_W<MODCTRL_SPEC> {
                AESKS_W::new(self, 18)
            }
            #[doc = "Bits 24:27 - AES mode selection. 0x0 = ECB; 0x1 = CBC; Others, reserved."]
            #[inline(always)]
            #[must_use]
            pub fn aesmod(&mut self) -> AESMOD_W<MODCTRL_SPEC> {
                AESMOD_W::new(self, 24)
            }
            #[doc = "Bits 28:31 - AES algorithem selection. 0x0 = AES 128; 0x1 = AES 256; 0x8 = SM4； Others, reserved."]
            #[inline(always)]
            #[must_use]
            pub fn aesalg(&mut self) -> AESALG_W<MODCTRL_SPEC> {
                AESALG_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Mod control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`modctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`modctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct MODCTRL_SPEC;
        impl crate::RegisterSpec for MODCTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`modctrl::R`](R) reader structure"]
        impl crate::Readable for MODCTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`modctrl::W`](W) writer structure"]
        impl crate::Writable for MODCTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets MODCTRL to value 0"]
        impl crate::Resettable for MODCTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PKTCNT (rw) register accessor: packet counter registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pktcnt`]
module"]
    pub type PKTCNT = crate::Reg<pktcnt::PKTCNT_SPEC>;
    #[doc = "packet counter registers."]
    pub mod pktcnt {
        #[doc = "Register `PKTCNT` reader"]
        pub type R = crate::R<PKTCNT_SPEC>;
        #[doc = "Register `PKTCNT` writer"]
        pub type W = crate::W<PKTCNT_SPEC>;
        #[doc = "Field `CNTINCR` reader - The value written to this field is added to the spacket count."]
        pub type CNTINCR_R = crate::FieldReader;
        #[doc = "Field `CNTINCR` writer - The value written to this field is added to the spacket count."]
        pub type CNTINCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `CNTVAL` reader - This read-only field shows the current (instantaneous) value of the packet counter"]
        pub type CNTVAL_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - The value written to this field is added to the spacket count."]
            #[inline(always)]
            pub fn cntincr(&self) -> CNTINCR_R {
                CNTINCR_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 16:23 - This read-only field shows the current (instantaneous) value of the packet counter"]
            #[inline(always)]
            pub fn cntval(&self) -> CNTVAL_R {
                CNTVAL_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - The value written to this field is added to the spacket count."]
            #[inline(always)]
            #[must_use]
            pub fn cntincr(&mut self) -> CNTINCR_W<PKTCNT_SPEC> {
                CNTINCR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "packet counter registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PKTCNT_SPEC;
        impl crate::RegisterSpec for PKTCNT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pktcnt::R`](R) reader structure"]
        impl crate::Readable for PKTCNT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pktcnt::W`](W) writer structure"]
        impl crate::Writable for PKTCNT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PKTCNT to value 0"]
        impl crate::Resettable for PKTCNT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "STA (rw) register accessor: Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sta`]
module"]
    pub type STA = crate::Reg<sta::STA_SPEC>;
    #[doc = "Status Registers"]
    pub mod sta {
        #[doc = "Register `STA` reader"]
        pub type R = crate::R<STA_SPEC>;
        #[doc = "Register `STA` writer"]
        pub type W = crate::W<STA_SPEC>;
        #[doc = "Field `ERRCHAIN` writer - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero."]
        pub type ERRCHAIN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERRHAS` writer - Hashing Check Error"]
        pub type ERRHAS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERRDST` writer - Destination Buffer Error"]
        pub type ERRDST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERRSRC` writer - Source Buffer Access Error"]
        pub type ERRSRC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERRPKT` writer - Packet head access error, or status update error."]
        pub type ERRPKT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ERRSET` writer - Working mode setup error."]
        pub type ERRSET_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PKTDON` writer - Packet processing done, will trigger this itnerrrupt when the \"PKTINT\" bit set in the packet control word."]
        pub type PKTDON_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PKTCNT0` writer - Packet Counter registers reachs to ZERO now."]
        pub type PKTCNT0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HASBSY` reader - Hashing Busy"]
        pub type HASBSY_R = crate::BitReader;
        #[doc = "Field `AESBSY` reader - AES Busy"]
        pub type AESBSY_R = crate::BitReader;
        #[doc = "Field `CHN1PKT0` writer - the chain buffer \"chain\" bit is \"1\", while packet counter is \"0\", now, waiting for new buffer data."]
        pub type CHN1PKT0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IRQ` writer - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero."]
        pub type IRQ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TAG` reader - packet tag."]
        pub type TAG_R = crate::FieldReader;
        impl R {
            #[doc = "Bit 18 - Hashing Busy"]
            #[inline(always)]
            pub fn hasbsy(&self) -> HASBSY_R {
                HASBSY_R::new(((self.bits >> 18) & 1) != 0)
            }
            #[doc = "Bit 19 - AES Busy"]
            #[inline(always)]
            pub fn aesbsy(&self) -> AESBSY_R {
                AESBSY_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bits 24:31 - packet tag."]
            #[inline(always)]
            pub fn tag(&self) -> TAG_R {
                TAG_R::new(((self.bits >> 24) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero."]
            #[inline(always)]
            #[must_use]
            pub fn errchain(&mut self) -> ERRCHAIN_W<STA_SPEC> {
                ERRCHAIN_W::new(self, 0)
            }
            #[doc = "Bit 1 - Hashing Check Error"]
            #[inline(always)]
            #[must_use]
            pub fn errhas(&mut self) -> ERRHAS_W<STA_SPEC> {
                ERRHAS_W::new(self, 1)
            }
            #[doc = "Bit 2 - Destination Buffer Error"]
            #[inline(always)]
            #[must_use]
            pub fn errdst(&mut self) -> ERRDST_W<STA_SPEC> {
                ERRDST_W::new(self, 2)
            }
            #[doc = "Bit 3 - Source Buffer Access Error"]
            #[inline(always)]
            #[must_use]
            pub fn errsrc(&mut self) -> ERRSRC_W<STA_SPEC> {
                ERRSRC_W::new(self, 3)
            }
            #[doc = "Bit 4 - Packet head access error, or status update error."]
            #[inline(always)]
            #[must_use]
            pub fn errpkt(&mut self) -> ERRPKT_W<STA_SPEC> {
                ERRPKT_W::new(self, 4)
            }
            #[doc = "Bit 5 - Working mode setup error."]
            #[inline(always)]
            #[must_use]
            pub fn errset(&mut self) -> ERRSET_W<STA_SPEC> {
                ERRSET_W::new(self, 5)
            }
            #[doc = "Bit 16 - Packet processing done, will trigger this itnerrrupt when the \"PKTINT\" bit set in the packet control word."]
            #[inline(always)]
            #[must_use]
            pub fn pktdon(&mut self) -> PKTDON_W<STA_SPEC> {
                PKTDON_W::new(self, 16)
            }
            #[doc = "Bit 17 - Packet Counter registers reachs to ZERO now."]
            #[inline(always)]
            #[must_use]
            pub fn pktcnt0(&mut self) -> PKTCNT0_W<STA_SPEC> {
                PKTCNT0_W::new(self, 17)
            }
            #[doc = "Bit 20 - the chain buffer \"chain\" bit is \"1\", while packet counter is \"0\", now, waiting for new buffer data."]
            #[inline(always)]
            #[must_use]
            pub fn chn1pkt0(&mut self) -> CHN1PKT0_W<STA_SPEC> {
                CHN1PKT0_W::new(self, 20)
            }
            #[doc = "Bit 23 - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero."]
            #[inline(always)]
            #[must_use]
            pub fn irq(&mut self) -> IRQ_W<STA_SPEC> {
                IRQ_W::new(self, 23)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STA_SPEC;
        impl crate::RegisterSpec for STA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sta::R`](R) reader structure"]
        impl crate::Readable for STA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sta::W`](W) writer structure"]
        impl crate::Writable for STA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets STA to value 0"]
        impl crate::Resettable for STA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "KEYADDR (rw) register accessor: Key Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`keyaddr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keyaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keyaddr`]
module"]
    pub type KEYADDR = crate::Reg<keyaddr::KEYADDR_SPEC>;
    #[doc = "Key Address"]
    pub mod keyaddr {
        #[doc = "Register `KEYADDR` reader"]
        pub type R = crate::R<KEYADDR_SPEC>;
        #[doc = "Register `KEYADDR` writer"]
        pub type W = crate::W<KEYADDR_SPEC>;
        #[doc = "Field `SUBWRD` reader - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field increments; To write a key, the software must first write the desired key index/subword to this register."]
        pub type SUBWRD_R = crate::FieldReader;
        #[doc = "Field `SUBWRD` writer - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field increments; To write a key, the software must first write the desired key index/subword to this register."]
        pub type SUBWRD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `INDEX` reader - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. Key index pointer. The valid indices are 0-\\[number_keys\\]. In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses."]
        pub type INDEX_R = crate::FieldReader;
        #[doc = "Field `INDEX` writer - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. Key index pointer. The valid indices are 0-\\[number_keys\\]. In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses."]
        pub type INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:1 - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field increments; To write a key, the software must first write the desired key index/subword to this register."]
            #[inline(always)]
            pub fn subwrd(&self) -> SUBWRD_R {
                SUBWRD_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bits 16:23 - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. Key index pointer. The valid indices are 0-\\[number_keys\\]. In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses."]
            #[inline(always)]
            pub fn index(&self) -> INDEX_R {
                INDEX_R::new(((self.bits >> 16) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field increments; To write a key, the software must first write the desired key index/subword to this register."]
            #[inline(always)]
            #[must_use]
            pub fn subwrd(&mut self) -> SUBWRD_W<KEYADDR_SPEC> {
                SUBWRD_W::new(self, 0)
            }
            #[doc = "Bits 16:23 - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. Key index pointer. The valid indices are 0-\\[number_keys\\]. In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses."]
            #[inline(always)]
            #[must_use]
            pub fn index(&mut self) -> INDEX_W<KEYADDR_SPEC> {
                INDEX_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Key Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`keyaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keyaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KEYADDR_SPEC;
        impl crate::RegisterSpec for KEYADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keyaddr::R`](R) reader structure"]
        impl crate::Readable for KEYADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`keyaddr::W`](W) writer structure"]
        impl crate::Writable for KEYADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets KEYADDR to value 0x40"]
        impl crate::Resettable for KEYADDR_SPEC {
            const RESET_VALUE: u32 = 0x40;
        }
    }
    #[doc = "KEYDAT (rw) register accessor: Key Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`keydat::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keydat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@keydat`]
module"]
    pub type KEYDAT = crate::Reg<keydat::KEYDAT_SPEC>;
    #[doc = "Key Data"]
    pub mod keydat {
        #[doc = "Register `KEYDAT` reader"]
        pub type R = crate::R<KEYDAT_SPEC>;
        #[doc = "Register `KEYDAT` writer"]
        pub type W = crate::W<KEYDAT_SPEC>;
        #[doc = "Field `KEYDAT` reader - This register provides the write access to the key/key subword specified by the key index register. Writing this location updates the selected subword for the key located at the index specified by the key index register. The write also triggers the SUBWORD field of the KEY register to increment to the next higher word in the key"]
        pub type KEYDAT_R = crate::FieldReader<u32>;
        #[doc = "Field `KEYDAT` writer - This register provides the write access to the key/key subword specified by the key index register. Writing this location updates the selected subword for the key located at the index specified by the key index register. The write also triggers the SUBWORD field of the KEY register to increment to the next higher word in the key"]
        pub type KEYDAT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - This register provides the write access to the key/key subword specified by the key index register. Writing this location updates the selected subword for the key located at the index specified by the key index register. The write also triggers the SUBWORD field of the KEY register to increment to the next higher word in the key"]
            #[inline(always)]
            pub fn keydat(&self) -> KEYDAT_R {
                KEYDAT_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - This register provides the write access to the key/key subword specified by the key index register. Writing this location updates the selected subword for the key located at the index specified by the key index register. The write also triggers the SUBWORD field of the KEY register to increment to the next higher word in the key"]
            #[inline(always)]
            #[must_use]
            pub fn keydat(&mut self) -> KEYDAT_W<KEYDAT_SPEC> {
                KEYDAT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Key Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`keydat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`keydat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct KEYDAT_SPEC;
        impl crate::RegisterSpec for KEYDAT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`keydat::R`](R) reader structure"]
        impl crate::Readable for KEYDAT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`keydat::W`](W) writer structure"]
        impl crate::Writable for KEYDAT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets KEYDAT to value 0x30"]
        impl crate::Resettable for KEYDAT_SPEC {
            const RESET_VALUE: u32 = 0x30;
        }
    }
    #[doc = "CIPHIV (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ciphiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ciphiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ciphiv`]
module"]
    pub type CIPHIV = crate::Reg<ciphiv::CIPHIV_SPEC>;
    #[doc = "no description available"]
    pub mod ciphiv {
        #[doc = "Register `CIPHIV[%s]` reader"]
        pub type R = crate::R<CIPHIV_SPEC>;
        #[doc = "Register `CIPHIV[%s]` writer"]
        pub type W = crate::W<CIPHIV_SPEC>;
        #[doc = "Field `CIPHIV` reader - cipher initialization vector."]
        pub type CIPHIV_R = crate::FieldReader<u32>;
        #[doc = "Field `CIPHIV` writer - cipher initialization vector."]
        pub type CIPHIV_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - cipher initialization vector."]
            #[inline(always)]
            pub fn ciphiv(&self) -> CIPHIV_R {
                CIPHIV_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - cipher initialization vector."]
            #[inline(always)]
            #[must_use]
            pub fn ciphiv(&mut self) -> CIPHIV_W<CIPHIV_SPEC> {
                CIPHIV_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ciphiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ciphiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CIPHIV_SPEC;
        impl crate::RegisterSpec for CIPHIV_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ciphiv::R`](R) reader structure"]
        impl crate::Readable for CIPHIV_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ciphiv::W`](W) writer structure"]
        impl crate::Writable for CIPHIV_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CIPHIV[%s]
to value 0"]
        impl crate::Resettable for CIPHIV_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "HASWRD (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haswrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haswrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@haswrd`]
module"]
    pub type HASWRD = crate::Reg<haswrd::HASWRD_SPEC>;
    #[doc = "no description available"]
    pub mod haswrd {
        #[doc = "Register `HASWRD[%s]` reader"]
        pub type R = crate::R<HASWRD_SPEC>;
        #[doc = "Register `HASWRD[%s]` writer"]
        pub type W = crate::W<HASWRD_SPEC>;
        #[doc = "Field `HASWRD` reader - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result\\[31:0\\]
here. If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result."]
        pub type HASWRD_R = crate::FieldReader<u32>;
        #[doc = "Field `HASWRD` writer - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result\\[31:0\\]
here. If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result."]
        pub type HASWRD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result\\[31:0\\]
here. If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result."]
            #[inline(always)]
            pub fn haswrd(&self) -> HASWRD_R {
                HASWRD_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result\\[31:0\\]
here. If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result."]
            #[inline(always)]
            #[must_use]
            pub fn haswrd(&mut self) -> HASWRD_W<HASWRD_SPEC> {
                HASWRD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`haswrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`haswrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct HASWRD_SPEC;
        impl crate::RegisterSpec for HASWRD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`haswrd::R`](R) reader structure"]
        impl crate::Readable for HASWRD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`haswrd::W`](W) writer structure"]
        impl crate::Writable for HASWRD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets HASWRD[%s]
to value 0x30"]
        impl crate::Resettable for HASWRD_SPEC {
            const RESET_VALUE: u32 = 0x30;
        }
    }
    #[doc = "CMDPTR (rw) register accessor: Command Pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdptr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdptr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdptr`]
module"]
    pub type CMDPTR = crate::Reg<cmdptr::CMDPTR_SPEC>;
    #[doc = "Command Pointer"]
    pub mod cmdptr {
        #[doc = "Register `CMDPTR` reader"]
        pub type R = crate::R<CMDPTR_SPEC>;
        #[doc = "Register `CMDPTR` writer"]
        pub type W = crate::W<CMDPTR_SPEC>;
        #[doc = "Field `CMDPTR` reader - current command addresses the register points to the multiword descriptor that is to be executed (or is currently being executed)"]
        pub type CMDPTR_R = crate::FieldReader<u32>;
        #[doc = "Field `CMDPTR` writer - current command addresses the register points to the multiword descriptor that is to be executed (or is currently being executed)"]
        pub type CMDPTR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - current command addresses the register points to the multiword descriptor that is to be executed (or is currently being executed)"]
            #[inline(always)]
            pub fn cmdptr(&self) -> CMDPTR_R {
                CMDPTR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - current command addresses the register points to the multiword descriptor that is to be executed (or is currently being executed)"]
            #[inline(always)]
            #[must_use]
            pub fn cmdptr(&mut self) -> CMDPTR_W<CMDPTR_SPEC> {
                CMDPTR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Command Pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdptr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdptr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMDPTR_SPEC;
        impl crate::RegisterSpec for CMDPTR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmdptr::R`](R) reader structure"]
        impl crate::Readable for CMDPTR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmdptr::W`](W) writer structure"]
        impl crate::Writable for CMDPTR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CMDPTR to value 0"]
        impl crate::Resettable for CMDPTR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "NPKTPTR (rw) register accessor: Next Packet Address Pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`npktptr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`npktptr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@npktptr`]
module"]
    pub type NPKTPTR = crate::Reg<npktptr::NPKTPTR_SPEC>;
    #[doc = "Next Packet Address Pointer"]
    pub mod npktptr {
        #[doc = "Register `NPKTPTR` reader"]
        pub type R = crate::R<NPKTPTR_SPEC>;
        #[doc = "Register `NPKTPTR` writer"]
        pub type W = crate::W<NPKTPTR_SPEC>;
        #[doc = "Field `NPKTPTR` reader - Next Packet Address Pointer"]
        pub type NPKTPTR_R = crate::FieldReader<u32>;
        #[doc = "Field `NPKTPTR` writer - Next Packet Address Pointer"]
        pub type NPKTPTR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Next Packet Address Pointer"]
            #[inline(always)]
            pub fn npktptr(&self) -> NPKTPTR_R {
                NPKTPTR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Next Packet Address Pointer"]
            #[inline(always)]
            #[must_use]
            pub fn npktptr(&mut self) -> NPKTPTR_W<NPKTPTR_SPEC> {
                NPKTPTR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Next Packet Address Pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`npktptr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`npktptr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct NPKTPTR_SPEC;
        impl crate::RegisterSpec for NPKTPTR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`npktptr::R`](R) reader structure"]
        impl crate::Readable for NPKTPTR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`npktptr::W`](W) writer structure"]
        impl crate::Writable for NPKTPTR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets NPKTPTR to value 0"]
        impl crate::Resettable for NPKTPTR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PKTCTL (rw) register accessor: Packet Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pktctl`]
module"]
    pub type PKTCTL = crate::Reg<pktctl::PKTCTL_SPEC>;
    #[doc = "Packet Control Registers"]
    pub mod pktctl {
        #[doc = "Register `PKTCTL` reader"]
        pub type R = crate::R<PKTCTL_SPEC>;
        #[doc = "Register `PKTCTL` writer"]
        pub type W = crate::W<PKTCTL_SPEC>;
        #[doc = "Field `PKTINT` reader - Reflects whether the channel must issue an interrupt upon the completion of the packet"]
        pub type PKTINT_R = crate::BitReader;
        #[doc = "Field `PKTINT` writer - Reflects whether the channel must issue an interrupt upon the completion of the packet"]
        pub type PKTINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DCRSEMA` reader - whether the channel's semaphore must be decremented at the end of the current operation. When the semaphore reaches a value of zero, no more operations are issued from the channel."]
        pub type DCRSEMA_R = crate::BitReader;
        #[doc = "Field `DCRSEMA` writer - whether the channel's semaphore must be decremented at the end of the current operation. When the semaphore reaches a value of zero, no more operations are issued from the channel."]
        pub type DCRSEMA_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CHAIN` reader - whether the next command pointer register must be loaded into the channel's current descriptor pointer."]
        pub type CHAIN_R = crate::BitReader;
        #[doc = "Field `CHAIN` writer - whether the next command pointer register must be loaded into the channel's current descriptor pointer."]
        pub type CHAIN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HASINI` reader - Hash Initialization packat"]
        pub type HASINI_R = crate::BitReader;
        #[doc = "Field `HASINI` writer - Hash Initialization packat"]
        pub type HASINI_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HASFNL` reader - Hash Termination packet"]
        pub type HASFNL_R = crate::BitReader;
        #[doc = "Field `HASFNL` writer - Hash Termination packet"]
        pub type HASFNL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CIPHIV` reader - Load Initial Vector for the AES in this packet."]
        pub type CIPHIV_R = crate::BitReader;
        #[doc = "Field `CIPHIV` writer - Load Initial Vector for the AES in this packet."]
        pub type CIPHIV_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PKTTAG` reader - packet tag"]
        pub type PKTTAG_R = crate::FieldReader;
        #[doc = "Field `PKTTAG` writer - packet tag"]
        pub type PKTTAG_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bit 1 - Reflects whether the channel must issue an interrupt upon the completion of the packet"]
            #[inline(always)]
            pub fn pktint(&self) -> PKTINT_R {
                PKTINT_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - whether the channel's semaphore must be decremented at the end of the current operation. When the semaphore reaches a value of zero, no more operations are issued from the channel."]
            #[inline(always)]
            pub fn dcrsema(&self) -> DCRSEMA_R {
                DCRSEMA_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - whether the next command pointer register must be loaded into the channel's current descriptor pointer."]
            #[inline(always)]
            pub fn chain(&self) -> CHAIN_R {
                CHAIN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Hash Initialization packat"]
            #[inline(always)]
            pub fn hasini(&self) -> HASINI_R {
                HASINI_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Hash Termination packet"]
            #[inline(always)]
            pub fn hasfnl(&self) -> HASFNL_R {
                HASFNL_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Load Initial Vector for the AES in this packet."]
            #[inline(always)]
            pub fn ciphiv(&self) -> CIPHIV_R {
                CIPHIV_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bits 24:31 - packet tag"]
            #[inline(always)]
            pub fn pkttag(&self) -> PKTTAG_R {
                PKTTAG_R::new(((self.bits >> 24) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bit 1 - Reflects whether the channel must issue an interrupt upon the completion of the packet"]
            #[inline(always)]
            #[must_use]
            pub fn pktint(&mut self) -> PKTINT_W<PKTCTL_SPEC> {
                PKTINT_W::new(self, 1)
            }
            #[doc = "Bit 2 - whether the channel's semaphore must be decremented at the end of the current operation. When the semaphore reaches a value of zero, no more operations are issued from the channel."]
            #[inline(always)]
            #[must_use]
            pub fn dcrsema(&mut self) -> DCRSEMA_W<PKTCTL_SPEC> {
                DCRSEMA_W::new(self, 2)
            }
            #[doc = "Bit 3 - whether the next command pointer register must be loaded into the channel's current descriptor pointer."]
            #[inline(always)]
            #[must_use]
            pub fn chain(&mut self) -> CHAIN_W<PKTCTL_SPEC> {
                CHAIN_W::new(self, 3)
            }
            #[doc = "Bit 4 - Hash Initialization packat"]
            #[inline(always)]
            #[must_use]
            pub fn hasini(&mut self) -> HASINI_W<PKTCTL_SPEC> {
                HASINI_W::new(self, 4)
            }
            #[doc = "Bit 5 - Hash Termination packet"]
            #[inline(always)]
            #[must_use]
            pub fn hasfnl(&mut self) -> HASFNL_W<PKTCTL_SPEC> {
                HASFNL_W::new(self, 5)
            }
            #[doc = "Bit 6 - Load Initial Vector for the AES in this packet."]
            #[inline(always)]
            #[must_use]
            pub fn ciphiv(&mut self) -> CIPHIV_W<PKTCTL_SPEC> {
                CIPHIV_W::new(self, 6)
            }
            #[doc = "Bits 24:31 - packet tag"]
            #[inline(always)]
            #[must_use]
            pub fn pkttag(&mut self) -> PKTTAG_W<PKTCTL_SPEC> {
                PKTTAG_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Packet Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PKTCTL_SPEC;
        impl crate::RegisterSpec for PKTCTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pktctl::R`](R) reader structure"]
        impl crate::Readable for PKTCTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pktctl::W`](W) writer structure"]
        impl crate::Writable for PKTCTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PKTCTL to value 0"]
        impl crate::Resettable for PKTCTL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PKTSRC (rw) register accessor: Packet Memory Source Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktsrc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktsrc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pktsrc`]
module"]
    pub type PKTSRC = crate::Reg<pktsrc::PKTSRC_SPEC>;
    #[doc = "Packet Memory Source Address"]
    pub mod pktsrc {
        #[doc = "Register `PKTSRC` reader"]
        pub type R = crate::R<PKTSRC_SPEC>;
        #[doc = "Register `PKTSRC` writer"]
        pub type W = crate::W<PKTSRC_SPEC>;
        #[doc = "Field `PKTSRC` reader - Packet Memory Source Address"]
        pub type PKTSRC_R = crate::FieldReader<u32>;
        #[doc = "Field `PKTSRC` writer - Packet Memory Source Address"]
        pub type PKTSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Packet Memory Source Address"]
            #[inline(always)]
            pub fn pktsrc(&self) -> PKTSRC_R {
                PKTSRC_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Packet Memory Source Address"]
            #[inline(always)]
            #[must_use]
            pub fn pktsrc(&mut self) -> PKTSRC_W<PKTSRC_SPEC> {
                PKTSRC_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Packet Memory Source Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktsrc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktsrc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PKTSRC_SPEC;
        impl crate::RegisterSpec for PKTSRC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pktsrc::R`](R) reader structure"]
        impl crate::Readable for PKTSRC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pktsrc::W`](W) writer structure"]
        impl crate::Writable for PKTSRC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PKTSRC to value 0"]
        impl crate::Resettable for PKTSRC_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PKTDST (rw) register accessor: Packet Memory Destination Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktdst::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktdst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pktdst`]
module"]
    pub type PKTDST = crate::Reg<pktdst::PKTDST_SPEC>;
    #[doc = "Packet Memory Destination Address"]
    pub mod pktdst {
        #[doc = "Register `PKTDST` reader"]
        pub type R = crate::R<PKTDST_SPEC>;
        #[doc = "Register `PKTDST` writer"]
        pub type W = crate::W<PKTDST_SPEC>;
        #[doc = "Field `PKTDST` reader - Packet Memory Destination Address"]
        pub type PKTDST_R = crate::FieldReader<u32>;
        #[doc = "Field `PKTDST` writer - Packet Memory Destination Address"]
        pub type PKTDST_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Packet Memory Destination Address"]
            #[inline(always)]
            pub fn pktdst(&self) -> PKTDST_R {
                PKTDST_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Packet Memory Destination Address"]
            #[inline(always)]
            #[must_use]
            pub fn pktdst(&mut self) -> PKTDST_W<PKTDST_SPEC> {
                PKTDST_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Packet Memory Destination Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktdst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktdst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PKTDST_SPEC;
        impl crate::RegisterSpec for PKTDST_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pktdst::R`](R) reader structure"]
        impl crate::Readable for PKTDST_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pktdst::W`](W) writer structure"]
        impl crate::Writable for PKTDST_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PKTDST to value 0"]
        impl crate::Resettable for PKTDST_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PKTBUF (rw) register accessor: Packet buffer size.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktbuf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktbuf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pktbuf`]
module"]
    pub type PKTBUF = crate::Reg<pktbuf::PKTBUF_SPEC>;
    #[doc = "Packet buffer size."]
    pub mod pktbuf {
        #[doc = "Register `PKTBUF` reader"]
        pub type R = crate::R<PKTBUF_SPEC>;
        #[doc = "Register `PKTBUF` writer"]
        pub type W = crate::W<PKTBUF_SPEC>;
        #[doc = "Field `PKTBUF` reader - No description avaiable"]
        pub type PKTBUF_R = crate::FieldReader<u32>;
        #[doc = "Field `PKTBUF` writer - No description avaiable"]
        pub type PKTBUF_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            pub fn pktbuf(&self) -> PKTBUF_R {
                PKTBUF_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn pktbuf(&mut self) -> PKTBUF_W<PKTBUF_SPEC> {
                PKTBUF_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Packet buffer size.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pktbuf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pktbuf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PKTBUF_SPEC;
        impl crate::RegisterSpec for PKTBUF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pktbuf::R`](R) reader structure"]
        impl crate::Readable for PKTBUF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pktbuf::W`](W) writer structure"]
        impl crate::Writable for PKTBUF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PKTBUF to value 0"]
        impl crate::Resettable for PKTBUF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "SEC"]
pub struct SEC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SEC {}
impl SEC {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const sec::RegisterBlock = 0xf304_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const sec::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SEC {
    type Target = sec::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SEC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SEC").finish()
    }
}
#[doc = "SEC"]
pub mod sec {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        secure_state: SECURE_STATE,
        secure_state_config: SECURE_STATE_CONFIG,
        violation_config: VIOLATION_CONFIG,
        escalate_config: ESCALATE_CONFIG,
        event: EVENT,
        lifecycle: LIFECYCLE,
    }
    impl RegisterBlock {
        #[doc = "0x00 - Secure state"]
        #[inline(always)]
        pub const fn secure_state(&self) -> &SECURE_STATE {
            &self.secure_state
        }
        #[doc = "0x04 - secure state configuration"]
        #[inline(always)]
        pub const fn secure_state_config(&self) -> &SECURE_STATE_CONFIG {
            &self.secure_state_config
        }
        #[doc = "0x08 - Security violation config"]
        #[inline(always)]
        pub const fn violation_config(&self) -> &VIOLATION_CONFIG {
            &self.violation_config
        }
        #[doc = "0x0c - Escalate behavior on security event"]
        #[inline(always)]
        pub const fn escalate_config(&self) -> &ESCALATE_CONFIG {
            &self.escalate_config
        }
        #[doc = "0x10 - Event and escalate status"]
        #[inline(always)]
        pub const fn event(&self) -> &EVENT {
            &self.event
        }
        #[doc = "0x14 - Lifecycle"]
        #[inline(always)]
        pub const fn lifecycle(&self) -> &LIFECYCLE {
            &self.lifecycle
        }
    }
    #[doc = "SECURE_STATE (rw) register accessor: Secure state\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`secure_state::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`secure_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secure_state`]
module"]
    pub type SECURE_STATE = crate::Reg<secure_state::SECURE_STATE_SPEC>;
    #[doc = "Secure state"]
    pub mod secure_state {
        #[doc = "Register `SECURE_STATE` reader"]
        pub type R = crate::R<SECURE_STATE_SPEC>;
        #[doc = "Register `SECURE_STATE` writer"]
        pub type W = crate::W<SECURE_STATE_SPEC>;
        #[doc = "Field `PMIC_INS` reader - PMIC secure state one hot indicator 0: secure state is not in inspect state 1: secure state is in inspect state"]
        pub type PMIC_INS_R = crate::BitReader;
        #[doc = "Field `PMIC_INS` writer - PMIC secure state one hot indicator 0: secure state is not in inspect state 1: secure state is in inspect state"]
        pub type PMIC_INS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PMIC_SEC` reader - PMIC secure state one hot indicator 0: secure state is not in secure state 1: secure state is in secure state"]
        pub type PMIC_SEC_R = crate::BitReader;
        #[doc = "Field `PMIC_SEC` writer - PMIC secure state one hot indicator 0: secure state is not in secure state 1: secure state is in secure state"]
        pub type PMIC_SEC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PMIC_NSC` reader - PMIC secure state one hot indicator 0: secure state is not in non-secure state 1: secure state is in non-secure state"]
        pub type PMIC_NSC_R = crate::BitReader;
        #[doc = "Field `PMIC_NSC` writer - PMIC secure state one hot indicator 0: secure state is not in non-secure state 1: secure state is in non-secure state"]
        pub type PMIC_NSC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PMIC_FAIL` reader - PMIC secure state one hot indicator 0: secure state is not in fail state 1: secure state is in fail state"]
        pub type PMIC_FAIL_R = crate::BitReader;
        #[doc = "Field `PMIC_FAIL` writer - PMIC secure state one hot indicator 0: secure state is not in fail state 1: secure state is in fail state"]
        pub type PMIC_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ALLOW_SEC` reader - Secure state allow 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter secure state"]
        pub type ALLOW_SEC_R = crate::BitReader;
        #[doc = "Field `ALLOW_NSC` reader - Non-secure state allow 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter non-secure state"]
        pub type ALLOW_NSC_R = crate::BitReader;
        impl R {
            #[doc = "Bit 4 - PMIC secure state one hot indicator 0: secure state is not in inspect state 1: secure state is in inspect state"]
            #[inline(always)]
            pub fn pmic_ins(&self) -> PMIC_INS_R {
                PMIC_INS_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - PMIC secure state one hot indicator 0: secure state is not in secure state 1: secure state is in secure state"]
            #[inline(always)]
            pub fn pmic_sec(&self) -> PMIC_SEC_R {
                PMIC_SEC_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - PMIC secure state one hot indicator 0: secure state is not in non-secure state 1: secure state is in non-secure state"]
            #[inline(always)]
            pub fn pmic_nsc(&self) -> PMIC_NSC_R {
                PMIC_NSC_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - PMIC secure state one hot indicator 0: secure state is not in fail state 1: secure state is in fail state"]
            #[inline(always)]
            pub fn pmic_fail(&self) -> PMIC_FAIL_R {
                PMIC_FAIL_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 16 - Secure state allow 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter secure state"]
            #[inline(always)]
            pub fn allow_sec(&self) -> ALLOW_SEC_R {
                ALLOW_SEC_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 17 - Non-secure state allow 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state 1: system is healthy to enter non-secure state"]
            #[inline(always)]
            pub fn allow_nsc(&self) -> ALLOW_NSC_R {
                ALLOW_NSC_R::new(((self.bits >> 17) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 4 - PMIC secure state one hot indicator 0: secure state is not in inspect state 1: secure state is in inspect state"]
            #[inline(always)]
            #[must_use]
            pub fn pmic_ins(&mut self) -> PMIC_INS_W<SECURE_STATE_SPEC> {
                PMIC_INS_W::new(self, 4)
            }
            #[doc = "Bit 5 - PMIC secure state one hot indicator 0: secure state is not in secure state 1: secure state is in secure state"]
            #[inline(always)]
            #[must_use]
            pub fn pmic_sec(&mut self) -> PMIC_SEC_W<SECURE_STATE_SPEC> {
                PMIC_SEC_W::new(self, 5)
            }
            #[doc = "Bit 6 - PMIC secure state one hot indicator 0: secure state is not in non-secure state 1: secure state is in non-secure state"]
            #[inline(always)]
            #[must_use]
            pub fn pmic_nsc(&mut self) -> PMIC_NSC_W<SECURE_STATE_SPEC> {
                PMIC_NSC_W::new(self, 6)
            }
            #[doc = "Bit 7 - PMIC secure state one hot indicator 0: secure state is not in fail state 1: secure state is in fail state"]
            #[inline(always)]
            #[must_use]
            pub fn pmic_fail(&mut self) -> PMIC_FAIL_W<SECURE_STATE_SPEC> {
                PMIC_FAIL_W::new(self, 7)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Secure state\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`secure_state::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`secure_state::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SECURE_STATE_SPEC;
        impl crate::RegisterSpec for SECURE_STATE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`secure_state::R`](R) reader structure"]
        impl crate::Readable for SECURE_STATE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`secure_state::W`](W) writer structure"]
        impl crate::Writable for SECURE_STATE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SECURE_STATE to value 0"]
        impl crate::Resettable for SECURE_STATE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SECURE_STATE_CONFIG (rw) register accessor: secure state configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`secure_state_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`secure_state_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@secure_state_config`]
module"]
    pub type SECURE_STATE_CONFIG = crate::Reg<secure_state_config::SECURE_STATE_CONFIG_SPEC>;
    #[doc = "secure state configuration"]
    pub mod secure_state_config {
        #[doc = "Register `SECURE_STATE_CONFIG` reader"]
        pub type R = crate::R<SECURE_STATE_CONFIG_SPEC>;
        #[doc = "Register `SECURE_STATE_CONFIG` writer"]
        pub type W = crate::W<SECURE_STATE_CONFIG_SPEC>;
        #[doc = "Field `ALLOW_RESTART` reader - allow secure state restart from fail state 0: restart is not allowed, only hardware reset can recover secure state 1: software is allowed to switch to inspect state from fail state"]
        pub type ALLOW_RESTART_R = crate::BitReader;
        #[doc = "Field `ALLOW_RESTART` writer - allow secure state restart from fail state 0: restart is not allowed, only hardware reset can recover secure state 1: software is allowed to switch to inspect state from fail state"]
        pub type ALLOW_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LOCK` reader - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 0: not locked, register can be modified 1: register locked, write access to the register is ignored"]
        pub type LOCK_R = crate::BitReader;
        #[doc = "Field `LOCK` writer - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 0: not locked, register can be modified 1: register locked, write access to the register is ignored"]
        pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - allow secure state restart from fail state 0: restart is not allowed, only hardware reset can recover secure state 1: software is allowed to switch to inspect state from fail state"]
            #[inline(always)]
            pub fn allow_restart(&self) -> ALLOW_RESTART_R {
                ALLOW_RESTART_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 3 - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 0: not locked, register can be modified 1: register locked, write access to the register is ignored"]
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(((self.bits >> 3) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - allow secure state restart from fail state 0: restart is not allowed, only hardware reset can recover secure state 1: software is allowed to switch to inspect state from fail state"]
            #[inline(always)]
            #[must_use]
            pub fn allow_restart(&mut self) -> ALLOW_RESTART_W<SECURE_STATE_CONFIG_SPEC> {
                ALLOW_RESTART_W::new(self, 0)
            }
            #[doc = "Bit 3 - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset 0: not locked, register can be modified 1: register locked, write access to the register is ignored"]
            #[inline(always)]
            #[must_use]
            pub fn lock(&mut self) -> LOCK_W<SECURE_STATE_CONFIG_SPEC> {
                LOCK_W::new(self, 3)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "secure state configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`secure_state_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`secure_state_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SECURE_STATE_CONFIG_SPEC;
        impl crate::RegisterSpec for SECURE_STATE_CONFIG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`secure_state_config::R`](R) reader structure"]
        impl crate::Readable for SECURE_STATE_CONFIG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`secure_state_config::W`](W) writer structure"]
        impl crate::Writable for SECURE_STATE_CONFIG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SECURE_STATE_CONFIG to value 0"]
        impl crate::Resettable for SECURE_STATE_CONFIG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "VIOLATION_CONFIG (rw) register accessor: Security violation config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`violation_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`violation_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@violation_config`]
module"]
    pub type VIOLATION_CONFIG = crate::Reg<violation_config::VIOLATION_CONFIG_SPEC>;
    #[doc = "Security violation config"]
    pub mod violation_config {
        #[doc = "Register `VIOLATION_CONFIG` reader"]
        pub type R = crate::R<VIOLATION_CONFIG_SPEC>;
        #[doc = "Register `VIOLATION_CONFIG` writer"]
        pub type W = crate::W<VIOLATION_CONFIG_SPEC>;
        #[doc = "Field `SEC_VIO_CFG` reader - configuration of secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
        pub type SEC_VIO_CFG_R = crate::FieldReader<u16>;
        #[doc = "Field `SEC_VIO_CFG` writer - configuration of secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
        pub type SEC_VIO_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
        #[doc = "Field `LOCK_SEC` reader - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_SEC_R = crate::BitReader;
        #[doc = "Field `LOCK_SEC` writer - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_SEC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NSC_VIO_CFG` reader - configuration of non-secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
        pub type NSC_VIO_CFG_R = crate::FieldReader<u16>;
        #[doc = "Field `NSC_VIO_CFG` writer - configuration of non-secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
        pub type NSC_VIO_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
        #[doc = "Field `LOCK_NSC` reader - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_NSC_R = crate::BitReader;
        #[doc = "Field `LOCK_NSC` writer - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_NSC_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:14 - configuration of secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
            #[inline(always)]
            pub fn sec_vio_cfg(&self) -> SEC_VIO_CFG_R {
                SEC_VIO_CFG_R::new((self.bits & 0x7fff) as u16)
            }
            #[doc = "Bit 15 - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            pub fn lock_sec(&self) -> LOCK_SEC_R {
                LOCK_SEC_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bits 16:30 - configuration of non-secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
            #[inline(always)]
            pub fn nsc_vio_cfg(&self) -> NSC_VIO_CFG_R {
                NSC_VIO_CFG_R::new(((self.bits >> 16) & 0x7fff) as u16)
            }
            #[doc = "Bit 31 - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            pub fn lock_nsc(&self) -> LOCK_NSC_R {
                LOCK_NSC_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:14 - configuration of secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
            #[inline(always)]
            #[must_use]
            pub fn sec_vio_cfg(&mut self) -> SEC_VIO_CFG_W<VIOLATION_CONFIG_SPEC> {
                SEC_VIO_CFG_W::new(self, 0)
            }
            #[doc = "Bit 15 - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            #[must_use]
            pub fn lock_sec(&mut self) -> LOCK_SEC_W<VIOLATION_CONFIG_SPEC> {
                LOCK_SEC_W::new(self, 15)
            }
            #[doc = "Bits 16:30 - configuration of non-secure state violations, each bit represents one security event 0: event is not a security violation 1: event is a security violation"]
            #[inline(always)]
            #[must_use]
            pub fn nsc_vio_cfg(&mut self) -> NSC_VIO_CFG_W<VIOLATION_CONFIG_SPEC> {
                NSC_VIO_CFG_W::new(self, 16)
            }
            #[doc = "Bit 31 - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            #[must_use]
            pub fn lock_nsc(&mut self) -> LOCK_NSC_W<VIOLATION_CONFIG_SPEC> {
                LOCK_NSC_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Security violation config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`violation_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`violation_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct VIOLATION_CONFIG_SPEC;
        impl crate::RegisterSpec for VIOLATION_CONFIG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`violation_config::R`](R) reader structure"]
        impl crate::Readable for VIOLATION_CONFIG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`violation_config::W`](W) writer structure"]
        impl crate::Writable for VIOLATION_CONFIG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets VIOLATION_CONFIG to value 0"]
        impl crate::Resettable for VIOLATION_CONFIG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ESCALATE_CONFIG (rw) register accessor: Escalate behavior on security event\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`escalate_config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`escalate_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@escalate_config`]
module"]
    pub type ESCALATE_CONFIG = crate::Reg<escalate_config::ESCALATE_CONFIG_SPEC>;
    #[doc = "Escalate behavior on security event"]
    pub mod escalate_config {
        #[doc = "Register `ESCALATE_CONFIG` reader"]
        pub type R = crate::R<ESCALATE_CONFIG_SPEC>;
        #[doc = "Register `ESCALATE_CONFIG` writer"]
        pub type W = crate::W<ESCALATE_CONFIG_SPEC>;
        #[doc = "Field `SEC_VIO_CFG` reader - configuration of secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
        pub type SEC_VIO_CFG_R = crate::FieldReader<u16>;
        #[doc = "Field `SEC_VIO_CFG` writer - configuration of secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
        pub type SEC_VIO_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
        #[doc = "Field `LOCK_SEC` reader - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_SEC_R = crate::BitReader;
        #[doc = "Field `LOCK_SEC` writer - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_SEC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `NSC_VIO_CFG` reader - configuration of non-secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
        pub type NSC_VIO_CFG_R = crate::FieldReader<u16>;
        #[doc = "Field `NSC_VIO_CFG` writer - configuration of non-secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
        pub type NSC_VIO_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
        #[doc = "Field `LOCK_NSC` reader - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_NSC_R = crate::BitReader;
        #[doc = "Field `LOCK_NSC` writer - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
        pub type LOCK_NSC_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:14 - configuration of secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
            #[inline(always)]
            pub fn sec_vio_cfg(&self) -> SEC_VIO_CFG_R {
                SEC_VIO_CFG_R::new((self.bits & 0x7fff) as u16)
            }
            #[doc = "Bit 15 - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            pub fn lock_sec(&self) -> LOCK_SEC_R {
                LOCK_SEC_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bits 16:30 - configuration of non-secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
            #[inline(always)]
            pub fn nsc_vio_cfg(&self) -> NSC_VIO_CFG_R {
                NSC_VIO_CFG_R::new(((self.bits >> 16) & 0x7fff) as u16)
            }
            #[doc = "Bit 31 - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            pub fn lock_nsc(&self) -> LOCK_NSC_R {
                LOCK_NSC_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:14 - configuration of secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
            #[inline(always)]
            #[must_use]
            pub fn sec_vio_cfg(&mut self) -> SEC_VIO_CFG_W<ESCALATE_CONFIG_SPEC> {
                SEC_VIO_CFG_W::new(self, 0)
            }
            #[doc = "Bit 15 - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            #[must_use]
            pub fn lock_sec(&mut self) -> LOCK_SEC_W<ESCALATE_CONFIG_SPEC> {
                LOCK_SEC_W::new(self, 15)
            }
            #[doc = "Bits 16:30 - configuration of non-secure state escalates, each bit represents one security event 0: event is not a security escalate 1: event is a security escalate"]
            #[inline(always)]
            #[must_use]
            pub fn nsc_vio_cfg(&mut self) -> NSC_VIO_CFG_W<ESCALATE_CONFIG_SPEC> {
                NSC_VIO_CFG_W::new(self, 16)
            }
            #[doc = "Bit 31 - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset 0: not locked, configuration can be modified 1: register locked, write access to the configuration is ignored"]
            #[inline(always)]
            #[must_use]
            pub fn lock_nsc(&mut self) -> LOCK_NSC_W<ESCALATE_CONFIG_SPEC> {
                LOCK_NSC_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Escalate behavior on security event\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`escalate_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`escalate_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ESCALATE_CONFIG_SPEC;
        impl crate::RegisterSpec for ESCALATE_CONFIG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`escalate_config::R`](R) reader structure"]
        impl crate::Readable for ESCALATE_CONFIG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`escalate_config::W`](W) writer structure"]
        impl crate::Writable for ESCALATE_CONFIG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ESCALATE_CONFIG to value 0"]
        impl crate::Resettable for ESCALATE_CONFIG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "EVENT (rw) register accessor: Event and escalate status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@event`]
module"]
    pub type EVENT = crate::Reg<event::EVENT_SPEC>;
    #[doc = "Event and escalate status"]
    pub mod event {
        #[doc = "Register `EVENT` reader"]
        pub type R = crate::R<EVENT_SPEC>;
        #[doc = "Register `EVENT` writer"]
        pub type W = crate::W<EVENT_SPEC>;
        #[doc = "Field `PMIC_ESC_SEC` reader - PMIC is escalting secure event"]
        pub type PMIC_ESC_SEC_R = crate::BitReader;
        #[doc = "Field `PMIC_ESC_NSC` reader - PMIC is escalating non-secure event"]
        pub type PMIC_ESC_NSC_R = crate::BitReader;
        #[doc = "Field `EVENT` reader - local event statue, each bit represents one security event"]
        pub type EVENT_R = crate::FieldReader<u16>;
        impl R {
            #[doc = "Bit 2 - PMIC is escalting secure event"]
            #[inline(always)]
            pub fn pmic_esc_sec(&self) -> PMIC_ESC_SEC_R {
                PMIC_ESC_SEC_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - PMIC is escalating non-secure event"]
            #[inline(always)]
            pub fn pmic_esc_nsc(&self) -> PMIC_ESC_NSC_R {
                PMIC_ESC_NSC_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 16:31 - local event statue, each bit represents one security event"]
            #[inline(always)]
            pub fn event(&self) -> EVENT_R {
                EVENT_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Event and escalate status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`event::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`event::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct EVENT_SPEC;
        impl crate::RegisterSpec for EVENT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`event::R`](R) reader structure"]
        impl crate::Readable for EVENT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`event::W`](W) writer structure"]
        impl crate::Writable for EVENT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets EVENT to value 0"]
        impl crate::Resettable for EVENT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "LIFECYCLE (rw) register accessor: Lifecycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lifecycle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lifecycle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lifecycle`]
module"]
    pub type LIFECYCLE = crate::Reg<lifecycle::LIFECYCLE_SPEC>;
    #[doc = "Lifecycle"]
    pub mod lifecycle {
        #[doc = "Register `LIFECYCLE` reader"]
        pub type R = crate::R<LIFECYCLE_SPEC>;
        #[doc = "Register `LIFECYCLE` writer"]
        pub type W = crate::W<LIFECYCLE_SPEC>;
        #[doc = "Field `LIFECYCLE` reader - lifecycle status, bit7: lifecycle_debate, bit6: lifecycle_scribe, bit5: lifecycle_no_ret, bit4: lifecycle_return, bit3: lifecycle_secure, bit2: lifecycle_nonsec, bit1: lifecycle_create, bit0: lifecycle_unknow"]
        pub type LIFECYCLE_R = crate::FieldReader;
        impl R {
            #[doc = "Bits 0:7 - lifecycle status, bit7: lifecycle_debate, bit6: lifecycle_scribe, bit5: lifecycle_no_ret, bit4: lifecycle_return, bit3: lifecycle_secure, bit2: lifecycle_nonsec, bit1: lifecycle_create, bit0: lifecycle_unknow"]
            #[inline(always)]
            pub fn lifecycle(&self) -> LIFECYCLE_R {
                LIFECYCLE_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Lifecycle\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lifecycle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lifecycle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LIFECYCLE_SPEC;
        impl crate::RegisterSpec for LIFECYCLE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`lifecycle::R`](R) reader structure"]
        impl crate::Readable for LIFECYCLE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`lifecycle::W`](W) writer structure"]
        impl crate::Writable for LIFECYCLE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LIFECYCLE to value 0"]
        impl crate::Resettable for LIFECYCLE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "MON"]
pub struct MON {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for MON {}
impl MON {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const mon::RegisterBlock = 0xf304_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const mon::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for MON {
    type Target = mon::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for MON {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("MON").finish()
    }
}
#[doc = "MON"]
pub mod mon {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        monitor: [MONITOR; 4],
        _reserved1: [u8; 0x20],
        irq_flag: IRQ_FLAG,
        irq_enable: IRQ_ENABLE,
    }
    impl RegisterBlock {
        #[doc = "0x00..0x20 - no description available"]
        #[inline(always)]
        pub const fn monitor(&self, n: usize) -> &MONITOR {
            &self.monitor[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x20 - no description available"]
        #[inline(always)]
        pub fn monitor_iter(&self) -> impl Iterator<Item = &MONITOR> {
            self.monitor.iter()
        }
        #[doc = "0x00..0x08 - no description available"]
        #[inline(always)]
        pub const fn monitorglitch0(&self) -> &MONITOR {
            self.monitor(0)
        }
        #[doc = "0x08..0x10 - no description available"]
        #[inline(always)]
        pub const fn monitorglitch1(&self) -> &MONITOR {
            self.monitor(1)
        }
        #[doc = "0x10..0x18 - no description available"]
        #[inline(always)]
        pub const fn monitorclock0(&self) -> &MONITOR {
            self.monitor(2)
        }
        #[doc = "0x18..0x20 - no description available"]
        #[inline(always)]
        pub const fn monitorclock1(&self) -> &MONITOR {
            self.monitor(3)
        }
        #[doc = "0x40 - No description avaiable"]
        #[inline(always)]
        pub const fn irq_flag(&self) -> &IRQ_FLAG {
            &self.irq_flag
        }
        #[doc = "0x44 - No description avaiable"]
        #[inline(always)]
        pub const fn irq_enable(&self) -> &IRQ_ENABLE {
            &self.irq_enable
        }
    }
    #[doc = "no description available"]
    pub use self::monitor::MONITOR;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod monitor {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct MONITOR {
            control: CONTROL,
            status: STATUS,
        }
        impl MONITOR {
            #[doc = "0x00 - Glitch and clock monitor control"]
            #[inline(always)]
            pub const fn control(&self) -> &CONTROL {
                &self.control
            }
            #[doc = "0x04 - Glitch and clock monitor status"]
            #[inline(always)]
            pub const fn status(&self) -> &STATUS {
                &self.status
            }
        }
        #[doc = "CONTROL (rw) register accessor: Glitch and clock monitor control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`]
module"]
        pub type CONTROL = crate::Reg<control::CONTROL_SPEC>;
        #[doc = "Glitch and clock monitor control"]
        pub mod control {
            #[doc = "Register `CONTROL` reader"]
            pub type R = crate::R<CONTROL_SPEC>;
            #[doc = "Register `CONTROL` writer"]
            pub type W = crate::W<CONTROL_SPEC>;
            #[doc = "Field `ENABLE` reader - enable glitch detector 0: detector disabled 1: detector enabled"]
            pub type ENABLE_R = crate::BitReader;
            #[doc = "Field `ENABLE` writer - enable glitch detector 0: detector disabled 1: detector enabled"]
            pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `ACTIVE` reader - select glitch works in active mode or passve mode. 0: passive mode, depends on power glitch destory DFF value 1: active mode, check glitch by DFF chain"]
            pub type ACTIVE_R = crate::BitReader;
            #[doc = "Field `ACTIVE` writer - select glitch works in active mode or passve mode. 0: passive mode, depends on power glitch destory DFF value 1: active mode, check glitch by DFF chain"]
            pub type ACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - enable glitch detector 0: detector disabled 1: detector enabled"]
                #[inline(always)]
                pub fn enable(&self) -> ENABLE_R {
                    ENABLE_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 4 - select glitch works in active mode or passve mode. 0: passive mode, depends on power glitch destory DFF value 1: active mode, check glitch by DFF chain"]
                #[inline(always)]
                pub fn active(&self) -> ACTIVE_R {
                    ACTIVE_R::new(((self.bits >> 4) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - enable glitch detector 0: detector disabled 1: detector enabled"]
                #[inline(always)]
                #[must_use]
                pub fn enable(&mut self) -> ENABLE_W<CONTROL_SPEC> {
                    ENABLE_W::new(self, 0)
                }
                #[doc = "Bit 4 - select glitch works in active mode or passve mode. 0: passive mode, depends on power glitch destory DFF value 1: active mode, check glitch by DFF chain"]
                #[inline(always)]
                #[must_use]
                pub fn active(&mut self) -> ACTIVE_W<CONTROL_SPEC> {
                    ACTIVE_W::new(self, 4)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Glitch and clock monitor control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CONTROL_SPEC;
            impl crate::RegisterSpec for CONTROL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`control::R`](R) reader structure"]
            impl crate::Readable for CONTROL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
            impl crate::Writable for CONTROL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CONTROL to value 0"]
            impl crate::Resettable for CONTROL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "STATUS (rw) register accessor: Glitch and clock monitor status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
        pub type STATUS = crate::Reg<status::STATUS_SPEC>;
        #[doc = "Glitch and clock monitor status"]
        pub mod status {
            #[doc = "Register `STATUS` reader"]
            pub type R = crate::R<STATUS_SPEC>;
            #[doc = "Register `STATUS` writer"]
            pub type W = crate::W<STATUS_SPEC>;
            #[doc = "Field `FLAG` reader - flag for glitch detected, write 1 to clear this flag 0: glitch not detected 1: glitch detected"]
            pub type FLAG_R = crate::BitReader;
            #[doc = "Field `FLAG` writer - flag for glitch detected, write 1 to clear this flag 0: glitch not detected 1: glitch detected"]
            pub type FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - flag for glitch detected, write 1 to clear this flag 0: glitch not detected 1: glitch detected"]
                #[inline(always)]
                pub fn flag(&self) -> FLAG_R {
                    FLAG_R::new((self.bits & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - flag for glitch detected, write 1 to clear this flag 0: glitch not detected 1: glitch detected"]
                #[inline(always)]
                #[must_use]
                pub fn flag(&mut self) -> FLAG_W<STATUS_SPEC> {
                    FLAG_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Glitch and clock monitor status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct STATUS_SPEC;
            impl crate::RegisterSpec for STATUS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`status::R`](R) reader structure"]
            impl crate::Readable for STATUS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
            impl crate::Writable for STATUS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets STATUS to value 0"]
            impl crate::Resettable for STATUS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "IRQ_FLAG (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_flag::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_flag::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_flag`]
module"]
    pub type IRQ_FLAG = crate::Reg<irq_flag::IRQ_FLAG_SPEC>;
    #[doc = "No description avaiable"]
    pub mod irq_flag {
        #[doc = "Register `IRQ_FLAG` reader"]
        pub type R = crate::R<IRQ_FLAG_SPEC>;
        #[doc = "Register `IRQ_FLAG` writer"]
        pub type W = crate::W<IRQ_FLAG_SPEC>;
        #[doc = "Field `FLAG` reader - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag 0: no monitor interrupt 1: monitor interrupt happened"]
        pub type FLAG_R = crate::FieldReader;
        #[doc = "Field `FLAG` writer - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag 0: no monitor interrupt 1: monitor interrupt happened"]
        pub type FLAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3 - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag 0: no monitor interrupt 1: monitor interrupt happened"]
            #[inline(always)]
            pub fn flag(&self) -> FLAG_R {
                FLAG_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag 0: no monitor interrupt 1: monitor interrupt happened"]
            #[inline(always)]
            #[must_use]
            pub fn flag(&mut self) -> FLAG_W<IRQ_FLAG_SPEC> {
                FLAG_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_flag::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_flag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IRQ_FLAG_SPEC;
        impl crate::RegisterSpec for IRQ_FLAG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`irq_flag::R`](R) reader structure"]
        impl crate::Readable for IRQ_FLAG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`irq_flag::W`](W) writer structure"]
        impl crate::Writable for IRQ_FLAG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IRQ_FLAG to value 0"]
        impl crate::Resettable for IRQ_FLAG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "IRQ_ENABLE (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enable`]
module"]
    pub type IRQ_ENABLE = crate::Reg<irq_enable::IRQ_ENABLE_SPEC>;
    #[doc = "No description avaiable"]
    pub mod irq_enable {
        #[doc = "Register `IRQ_ENABLE` reader"]
        pub type R = crate::R<IRQ_ENABLE_SPEC>;
        #[doc = "Register `IRQ_ENABLE` writer"]
        pub type W = crate::W<IRQ_ENABLE_SPEC>;
        #[doc = "Field `ENABLE` reader - interrupt enable, each bit represents for one monitor 0: monitor interrupt disabled 1: monitor interrupt enabled"]
        pub type ENABLE_R = crate::FieldReader;
        #[doc = "Field `ENABLE` writer - interrupt enable, each bit represents for one monitor 0: monitor interrupt disabled 1: monitor interrupt enabled"]
        pub type ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3 - interrupt enable, each bit represents for one monitor 0: monitor interrupt disabled 1: monitor interrupt enabled"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - interrupt enable, each bit represents for one monitor 0: monitor interrupt disabled 1: monitor interrupt enabled"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<IRQ_ENABLE_SPEC> {
                ENABLE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IRQ_ENABLE_SPEC;
        impl crate::RegisterSpec for IRQ_ENABLE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`irq_enable::R`](R) reader structure"]
        impl crate::Readable for IRQ_ENABLE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`irq_enable::W`](W) writer structure"]
        impl crate::Writable for IRQ_ENABLE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets IRQ_ENABLE to value 0"]
        impl crate::Resettable for IRQ_ENABLE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "RNG"]
pub struct RNG {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for RNG {}
impl RNG {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const rng::RegisterBlock = 0xf304_c000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const rng::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for RNG {
    type Target = rng::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for RNG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("RNG").finish()
    }
}
#[doc = "RNG"]
pub mod rng {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        cmd: CMD,
        ctrl: CTRL,
        sta: STA,
        err: ERR,
        fo2b: FO2B,
        _reserved5: [u8; 0x0c],
        r2sk: [R2SK; 8],
    }
    impl RegisterBlock {
        #[doc = "0x00 - Command Register"]
        #[inline(always)]
        pub const fn cmd(&self) -> &CMD {
            &self.cmd
        }
        #[doc = "0x04 - Control Register"]
        #[inline(always)]
        pub const fn ctrl(&self) -> &CTRL {
            &self.ctrl
        }
        #[doc = "0x08 - Status Register"]
        #[inline(always)]
        pub const fn sta(&self) -> &STA {
            &self.sta
        }
        #[doc = "0x0c - Error Registers"]
        #[inline(always)]
        pub const fn err(&self) -> &ERR {
            &self.err
        }
        #[doc = "0x10 - FIFO out to bus/cpu"]
        #[inline(always)]
        pub const fn fo2b(&self) -> &FO2B {
            &self.fo2b
        }
        #[doc = "0x20..0x40 - no description available"]
        #[inline(always)]
        pub const fn r2sk(&self, n: usize) -> &R2SK {
            &self.r2sk[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x20..0x40 - no description available"]
        #[inline(always)]
        pub fn r2sk_iter(&self) -> impl Iterator<Item = &R2SK> {
            self.r2sk.iter()
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s0(&self) -> &R2SK {
            self.r2sk(0)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s1(&self) -> &R2SK {
            self.r2sk(1)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s2(&self) -> &R2SK {
            self.r2sk(2)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s3(&self) -> &R2SK {
            self.r2sk(3)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s4(&self) -> &R2SK {
            self.r2sk(4)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s5(&self) -> &R2SK {
            self.r2sk(5)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s6(&self) -> &R2SK {
            self.r2sk(6)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn r2skfo2s7(&self) -> &R2SK {
            self.r2sk(7)
        }
    }
    #[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"]
    pub type CMD = crate::Reg<cmd::CMD_SPEC>;
    #[doc = "Command Register"]
    pub mod cmd {
        #[doc = "Register `CMD` reader"]
        pub type R = crate::R<CMD_SPEC>;
        #[doc = "Register `CMD` writer"]
        pub type W = crate::W<CMD_SPEC>;
        #[doc = "Field `SLFCHK` reader - Self Test, when both ST and GS triggered, ST first and GS next."]
        pub type SLFCHK_R = crate::BitReader;
        #[doc = "Field `SLFCHK` writer - Self Test, when both ST and GS triggered, ST first and GS next."]
        pub type SLFCHK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `GENSD` reader - Generate Seed, when both ST and GS triggered, ST first and GS next."]
        pub type GENSD_R = crate::BitReader;
        #[doc = "Field `GENSD` writer - Generate Seed, when both ST and GS triggered, ST first and GS next."]
        pub type GENSD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CLRINT` reader - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. 0 Do not clear the interrupt. 1 Clear the interrupt"]
        pub type CLRINT_R = crate::BitReader;
        #[doc = "Field `CLRINT` writer - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. 0 Do not clear the interrupt. 1 Clear the interrupt"]
        pub type CLRINT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CLRERR` reader - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. 0 Do not clear the errors and the interrupt. 1 Clear the errors and the interrupt."]
        pub type CLRERR_R = crate::BitReader;
        #[doc = "Field `CLRERR` writer - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. 0 Do not clear the errors and the interrupt. 1 Clear the errors and the interrupt."]
        pub type CLRERR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SFTRST` reader - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. 0 Do not perform a software reset. 1 Software reset"]
        pub type SFTRST_R = crate::BitReader;
        #[doc = "Field `SFTRST` writer - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. 0 Do not perform a software reset. 1 Software reset"]
        pub type SFTRST_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Self Test, when both ST and GS triggered, ST first and GS next."]
            #[inline(always)]
            pub fn slfchk(&self) -> SLFCHK_R {
                SLFCHK_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Generate Seed, when both ST and GS triggered, ST first and GS next."]
            #[inline(always)]
            pub fn gensd(&self) -> GENSD_R {
                GENSD_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 4 - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. 0 Do not clear the interrupt. 1 Clear the interrupt"]
            #[inline(always)]
            pub fn clrint(&self) -> CLRINT_R {
                CLRINT_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. 0 Do not clear the errors and the interrupt. 1 Clear the errors and the interrupt."]
            #[inline(always)]
            pub fn clrerr(&self) -> CLRERR_R {
                CLRERR_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. 0 Do not perform a software reset. 1 Software reset"]
            #[inline(always)]
            pub fn sftrst(&self) -> SFTRST_R {
                SFTRST_R::new(((self.bits >> 6) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Self Test, when both ST and GS triggered, ST first and GS next."]
            #[inline(always)]
            #[must_use]
            pub fn slfchk(&mut self) -> SLFCHK_W<CMD_SPEC> {
                SLFCHK_W::new(self, 0)
            }
            #[doc = "Bit 1 - Generate Seed, when both ST and GS triggered, ST first and GS next."]
            #[inline(always)]
            #[must_use]
            pub fn gensd(&mut self) -> GENSD_W<CMD_SPEC> {
                GENSD_W::new(self, 1)
            }
            #[doc = "Bit 4 - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. 0 Do not clear the interrupt. 1 Clear the interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn clrint(&mut self) -> CLRINT_W<CMD_SPEC> {
                CLRINT_W::new(self, 4)
            }
            #[doc = "Bit 5 - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. 0 Do not clear the errors and the interrupt. 1 Clear the errors and the interrupt."]
            #[inline(always)]
            #[must_use]
            pub fn clrerr(&mut self) -> CLRERR_W<CMD_SPEC> {
                CLRERR_W::new(self, 5)
            }
            #[doc = "Bit 6 - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. 0 Do not perform a software reset. 1 Software reset"]
            #[inline(always)]
            #[must_use]
            pub fn sftrst(&mut self) -> SFTRST_W<CMD_SPEC> {
                SFTRST_W::new(self, 6)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMD_SPEC;
        impl crate::RegisterSpec for CMD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
        impl crate::Readable for CMD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
        impl crate::Writable for CMD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CMD to value 0"]
        impl crate::Resettable for CMD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
    pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
    #[doc = "Control Register"]
    pub mod ctrl {
        #[doc = "Register `CTRL` reader"]
        pub type R = crate::R<CTRL_SPEC>;
        #[doc = "Register `CTRL` writer"]
        pub type W = crate::W<CTRL_SPEC>;
        #[doc = "Field `FUFMOD` reader - FIFO underflow response mode 00 Return all zeros and set the ESR\\[FUFE\\]. 01 Return all zeros and set the ESR\\[FUFE\\]. 10 Generate the bus transfer error 11 Generate the interrupt and return all zeros (overrides the CTRL\\[MASKERR\\])."]
        pub type FUFMOD_R = crate::FieldReader;
        #[doc = "Field `FUFMOD` writer - FIFO underflow response mode 00 Return all zeros and set the ESR\\[FUFE\\]. 01 Return all zeros and set the ESR\\[FUFE\\]. 10 Generate the bus transfer error 11 Generate the interrupt and return all zeros (overrides the CTRL\\[MASKERR\\])."]
        pub type FUFMOD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `AUTRSD` reader - Auto Reseed"]
        pub type AUTRSD_R = crate::BitReader;
        #[doc = "Field `AUTRSD` writer - Auto Reseed"]
        pub type AUTRSD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MIRQDN` reader - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: • Reading the STA and viewing the seed done and the self-test done bits (STA\\[SDN, STDN\\]). • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD\\[GS,ST\\]) being set, indicating that the operation is still taking place."]
        pub type MIRQDN_R = crate::BitReader;
        #[doc = "Field `MIRQDN` writer - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: • Reading the STA and viewing the seed done and the self-test done bits (STA\\[SDN, STDN\\]). • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD\\[GS,ST\\]) being set, indicating that the operation is still taking place."]
        pub type MIRQDN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MIRQERR` reader - Mask Interrupt Request for Error"]
        pub type MIRQERR_R = crate::BitReader;
        #[doc = "Field `MIRQERR` writer - Mask Interrupt Request for Error"]
        pub type MIRQERR_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:1 - FIFO underflow response mode 00 Return all zeros and set the ESR\\[FUFE\\]. 01 Return all zeros and set the ESR\\[FUFE\\]. 10 Generate the bus transfer error 11 Generate the interrupt and return all zeros (overrides the CTRL\\[MASKERR\\])."]
            #[inline(always)]
            pub fn fufmod(&self) -> FUFMOD_R {
                FUFMOD_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 4 - Auto Reseed"]
            #[inline(always)]
            pub fn autrsd(&self) -> AUTRSD_R {
                AUTRSD_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: • Reading the STA and viewing the seed done and the self-test done bits (STA\\[SDN, STDN\\]). • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD\\[GS,ST\\]) being set, indicating that the operation is still taking place."]
            #[inline(always)]
            pub fn mirqdn(&self) -> MIRQDN_R {
                MIRQDN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - Mask Interrupt Request for Error"]
            #[inline(always)]
            pub fn mirqerr(&self) -> MIRQERR_R {
                MIRQERR_R::new(((self.bits >> 6) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - FIFO underflow response mode 00 Return all zeros and set the ESR\\[FUFE\\]. 01 Return all zeros and set the ESR\\[FUFE\\]. 10 Generate the bus transfer error 11 Generate the interrupt and return all zeros (overrides the CTRL\\[MASKERR\\])."]
            #[inline(always)]
            #[must_use]
            pub fn fufmod(&mut self) -> FUFMOD_W<CTRL_SPEC> {
                FUFMOD_W::new(self, 0)
            }
            #[doc = "Bit 4 - Auto Reseed"]
            #[inline(always)]
            #[must_use]
            pub fn autrsd(&mut self) -> AUTRSD_W<CTRL_SPEC> {
                AUTRSD_W::new(self, 4)
            }
            #[doc = "Bit 5 - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: • Reading the STA and viewing the seed done and the self-test done bits (STA\\[SDN, STDN\\]). • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD\\[GS,ST\\]) being set, indicating that the operation is still taking place."]
            #[inline(always)]
            #[must_use]
            pub fn mirqdn(&mut self) -> MIRQDN_W<CTRL_SPEC> {
                MIRQDN_W::new(self, 5)
            }
            #[doc = "Bit 6 - Mask Interrupt Request for Error"]
            #[inline(always)]
            #[must_use]
            pub fn mirqerr(&mut self) -> MIRQERR_W<CTRL_SPEC> {
                MIRQERR_W::new(self, 6)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CTRL_SPEC;
        impl crate::RegisterSpec for CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
        impl crate::Readable for CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
        impl crate::Writable for CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CTRL to value 0"]
        impl crate::Resettable for CTRL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "STA (rw) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sta`]
module"]
    pub type STA = crate::Reg<sta::STA_SPEC>;
    #[doc = "Status Register"]
    pub mod sta {
        #[doc = "Register `STA` reader"]
        pub type R = crate::R<STA_SPEC>;
        #[doc = "Register `STA` writer"]
        pub type W = crate::W<STA_SPEC>;
        #[doc = "Field `BUSY` reader - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on."]
        pub type BUSY_R = crate::BitReader;
        #[doc = "Field `IDLE` reader - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again."]
        pub type IDLE_R = crate::BitReader;
        #[doc = "Field `RSDREQ` reader - Reseed needed Indicates that the RNG needs to be reseeded. This is done by setting the CMD\\[GS\\], or automatically if the CTRL\\[ARS\\]
is set."]
        pub type RSDREQ_R = crate::BitReader;
        #[doc = "Field `SCDN` reader - Self Check Done Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is initiated by setting the CMD\\[ST\\]. 0 Self test not completed 1 Completed a self test since the last reset."]
        pub type SCDN_R = crate::BitReader;
        #[doc = "Field `FSDDN` reader - 1st Seed done When \"1\", Indicates that the RNG generated the first seed."]
        pub type FSDDN_R = crate::BitReader;
        #[doc = "Field `NSDDN` reader - New seed done."]
        pub type NSDDN_R = crate::BitReader;
        #[doc = "Field `FRNNU` reader - Fifo Level, Indicates the number of random words currently in the output FIFO"]
        pub type FRNNU_R = crate::FieldReader;
        #[doc = "Field `FSIZE` reader - Fifo Size, it is 5 in this design."]
        pub type FSIZE_R = crate::FieldReader;
        #[doc = "Field `FUNCERR` reader - Error was detected, check ESR register for details"]
        pub type FUNCERR_R = crate::BitReader;
        #[doc = "Field `SCPF` reader - Self Check Pass Fail"]
        pub type SCPF_R = crate::FieldReader;
        impl R {
            #[doc = "Bit 1 - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on."]
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again."]
            #[inline(always)]
            pub fn idle(&self) -> IDLE_R {
                IDLE_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - Reseed needed Indicates that the RNG needs to be reseeded. This is done by setting the CMD\\[GS\\], or automatically if the CTRL\\[ARS\\]
is set."]
            #[inline(always)]
            pub fn rsdreq(&self) -> RSDREQ_R {
                RSDREQ_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - Self Check Done Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is initiated by setting the CMD\\[ST\\]. 0 Self test not completed 1 Completed a self test since the last reset."]
            #[inline(always)]
            pub fn scdn(&self) -> SCDN_R {
                SCDN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - 1st Seed done When \"1\", Indicates that the RNG generated the first seed."]
            #[inline(always)]
            pub fn fsddn(&self) -> FSDDN_R {
                FSDDN_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - New seed done."]
            #[inline(always)]
            pub fn nsddn(&self) -> NSDDN_R {
                NSDDN_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bits 8:11 - Fifo Level, Indicates the number of random words currently in the output FIFO"]
            #[inline(always)]
            pub fn frnnu(&self) -> FRNNU_R {
                FRNNU_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            #[doc = "Bits 12:15 - Fifo Size, it is 5 in this design."]
            #[inline(always)]
            pub fn fsize(&self) -> FSIZE_R {
                FSIZE_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            #[doc = "Bit 16 - Error was detected, check ESR register for details"]
            #[inline(always)]
            pub fn funcerr(&self) -> FUNCERR_R {
                FUNCERR_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bits 21:23 - Self Check Pass Fail"]
            #[inline(always)]
            pub fn scpf(&self) -> SCPF_R {
                SCPF_R::new(((self.bits >> 21) & 7) as u8)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STA_SPEC;
        impl crate::RegisterSpec for STA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sta::R`](R) reader structure"]
        impl crate::Readable for STA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sta::W`](W) writer structure"]
        impl crate::Writable for STA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets STA to value 0"]
        impl crate::Resettable for STA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ERR (rw) register accessor: Error Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err`]
module"]
    pub type ERR = crate::Reg<err::ERR_SPEC>;
    #[doc = "Error Registers"]
    pub mod err {
        #[doc = "Register `ERR` reader"]
        pub type R = crate::R<ERR_SPEC>;
        #[doc = "Register `ERR` writer"]
        pub type W = crate::W<ERR_SPEC>;
        #[doc = "Field `SCKERR` reader - Self-test error Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a hardware reset or by writing 1 to the CMD\\[CE\\]"]
        pub type SCKERR_R = crate::BitReader;
        #[doc = "Field `FUFE` reader - FIFO access error(underflow)"]
        pub type FUFE_R = crate::BitReader;
        impl R {
            #[doc = "Bit 3 - Self-test error Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a hardware reset or by writing 1 to the CMD\\[CE\\]"]
            #[inline(always)]
            pub fn sckerr(&self) -> SCKERR_R {
                SCKERR_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 5 - FIFO access error(underflow)"]
            #[inline(always)]
            pub fn fufe(&self) -> FUFE_R {
                FUFE_R::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Error Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ERR_SPEC;
        impl crate::RegisterSpec for ERR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`err::R`](R) reader structure"]
        impl crate::Readable for ERR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`err::W`](W) writer structure"]
        impl crate::Writable for ERR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ERR to value 0"]
        impl crate::Resettable for ERR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "FO2B (rw) register accessor: FIFO out to bus/cpu\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fo2b::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fo2b::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fo2b`]
module"]
    pub type FO2B = crate::Reg<fo2b::FO2B_SPEC>;
    #[doc = "FIFO out to bus/cpu"]
    pub mod fo2b {
        #[doc = "Register `FO2B` reader"]
        pub type R = crate::R<FO2B_SPEC>;
        #[doc = "Register `FO2B` writer"]
        pub type W = crate::W<FO2B_SPEC>;
        #[doc = "Field `FO2B` reader - SW read the FIFO output."]
        pub type FO2B_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - SW read the FIFO output."]
            #[inline(always)]
            pub fn fo2b(&self) -> FO2B_R {
                FO2B_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "FIFO out to bus/cpu\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fo2b::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fo2b::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FO2B_SPEC;
        impl crate::RegisterSpec for FO2B_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`fo2b::R`](R) reader structure"]
        impl crate::Readable for FO2B_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`fo2b::W`](W) writer structure"]
        impl crate::Writable for FO2B_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FO2B to value 0"]
        impl crate::Resettable for FO2B_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "R2SK (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2sk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2sk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@r2sk`]
module"]
    pub type R2SK = crate::Reg<r2sk::R2SK_SPEC>;
    #[doc = "no description available"]
    pub mod r2sk {
        #[doc = "Register `R2SK[%s]` reader"]
        pub type R = crate::R<R2SK_SPEC>;
        #[doc = "Register `R2SK[%s]` writer"]
        pub type W = crate::W<R2SK_SPEC>;
        #[doc = "Field `FO2S0` reader - FIFO out to KMAN, will be SDP engine key."]
        pub type FO2S0_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - FIFO out to KMAN, will be SDP engine key."]
            #[inline(always)]
            pub fn fo2s0(&self) -> FO2S0_R {
                FO2S0_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`r2sk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`r2sk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct R2SK_SPEC;
        impl crate::RegisterSpec for R2SK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`r2sk::R`](R) reader structure"]
        impl crate::Readable for R2SK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`r2sk::W`](W) writer structure"]
        impl crate::Writable for R2SK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets R2SK[%s]
to value 0"]
        impl crate::Resettable for R2SK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "OTP"]
pub struct OTP {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for OTP {}
impl OTP {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const otp::RegisterBlock = 0xf305_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const otp::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for OTP {
    type Target = otp::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for OTP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OTP").finish()
    }
}
#[doc = "OTP"]
pub mod otp {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        shadow: [SHADOW; 128],
        shadow_lock: [SHADOW_LOCK; 8],
        _reserved2: [u8; 0x01e0],
        fuse: [FUSE; 128],
        fuse_lock: [FUSE_LOCK; 8],
        _reserved4: [u8; 0x01e0],
        unlock: UNLOCK,
        data: DATA,
        addr: ADDR,
        cmd: CMD,
        _reserved8: [u8; 0x01f0],
        load_req: LOAD_REQ,
        load_comp: LOAD_COMP,
        _reserved10: [u8; 0x18],
        region: [REGION; 4],
        _reserved11: [u8; 0x01d0],
        int_flag: INT_FLAG,
        int_en: INT_EN,
    }
    impl RegisterBlock {
        #[doc = "0x00..0x200 - no description available"]
        #[inline(always)]
        pub const fn shadow(&self, n: usize) -> &SHADOW {
            &self.shadow[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x200 - no description available"]
        #[inline(always)]
        pub fn shadow_iter(&self) -> impl Iterator<Item = &SHADOW> {
            self.shadow.iter()
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow000(&self) -> &SHADOW {
            self.shadow(0)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow001(&self) -> &SHADOW {
            self.shadow(1)
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow002(&self) -> &SHADOW {
            self.shadow(2)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow003(&self) -> &SHADOW {
            self.shadow(3)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow004(&self) -> &SHADOW {
            self.shadow(4)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow005(&self) -> &SHADOW {
            self.shadow(5)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow006(&self) -> &SHADOW {
            self.shadow(6)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow007(&self) -> &SHADOW {
            self.shadow(7)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow008(&self) -> &SHADOW {
            self.shadow(8)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow009(&self) -> &SHADOW {
            self.shadow(9)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow010(&self) -> &SHADOW {
            self.shadow(10)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow011(&self) -> &SHADOW {
            self.shadow(11)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow012(&self) -> &SHADOW {
            self.shadow(12)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow013(&self) -> &SHADOW {
            self.shadow(13)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow014(&self) -> &SHADOW {
            self.shadow(14)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow015(&self) -> &SHADOW {
            self.shadow(15)
        }
        #[doc = "0x40 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow016(&self) -> &SHADOW {
            self.shadow(16)
        }
        #[doc = "0x44 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow017(&self) -> &SHADOW {
            self.shadow(17)
        }
        #[doc = "0x48 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow018(&self) -> &SHADOW {
            self.shadow(18)
        }
        #[doc = "0x4c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow019(&self) -> &SHADOW {
            self.shadow(19)
        }
        #[doc = "0x50 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow020(&self) -> &SHADOW {
            self.shadow(20)
        }
        #[doc = "0x54 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow021(&self) -> &SHADOW {
            self.shadow(21)
        }
        #[doc = "0x58 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow022(&self) -> &SHADOW {
            self.shadow(22)
        }
        #[doc = "0x5c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow023(&self) -> &SHADOW {
            self.shadow(23)
        }
        #[doc = "0x60 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow024(&self) -> &SHADOW {
            self.shadow(24)
        }
        #[doc = "0x64 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow025(&self) -> &SHADOW {
            self.shadow(25)
        }
        #[doc = "0x68 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow026(&self) -> &SHADOW {
            self.shadow(26)
        }
        #[doc = "0x6c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow027(&self) -> &SHADOW {
            self.shadow(27)
        }
        #[doc = "0x70 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow028(&self) -> &SHADOW {
            self.shadow(28)
        }
        #[doc = "0x74 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow029(&self) -> &SHADOW {
            self.shadow(29)
        }
        #[doc = "0x78 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow030(&self) -> &SHADOW {
            self.shadow(30)
        }
        #[doc = "0x7c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow031(&self) -> &SHADOW {
            self.shadow(31)
        }
        #[doc = "0x80 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow032(&self) -> &SHADOW {
            self.shadow(32)
        }
        #[doc = "0x84 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow033(&self) -> &SHADOW {
            self.shadow(33)
        }
        #[doc = "0x88 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow034(&self) -> &SHADOW {
            self.shadow(34)
        }
        #[doc = "0x8c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow035(&self) -> &SHADOW {
            self.shadow(35)
        }
        #[doc = "0x90 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow036(&self) -> &SHADOW {
            self.shadow(36)
        }
        #[doc = "0x94 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow037(&self) -> &SHADOW {
            self.shadow(37)
        }
        #[doc = "0x98 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow038(&self) -> &SHADOW {
            self.shadow(38)
        }
        #[doc = "0x9c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow039(&self) -> &SHADOW {
            self.shadow(39)
        }
        #[doc = "0xa0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow040(&self) -> &SHADOW {
            self.shadow(40)
        }
        #[doc = "0xa4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow041(&self) -> &SHADOW {
            self.shadow(41)
        }
        #[doc = "0xa8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow042(&self) -> &SHADOW {
            self.shadow(42)
        }
        #[doc = "0xac - no description available"]
        #[inline(always)]
        pub const fn shadowshadow043(&self) -> &SHADOW {
            self.shadow(43)
        }
        #[doc = "0xb0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow044(&self) -> &SHADOW {
            self.shadow(44)
        }
        #[doc = "0xb4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow045(&self) -> &SHADOW {
            self.shadow(45)
        }
        #[doc = "0xb8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow046(&self) -> &SHADOW {
            self.shadow(46)
        }
        #[doc = "0xbc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow047(&self) -> &SHADOW {
            self.shadow(47)
        }
        #[doc = "0xc0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow048(&self) -> &SHADOW {
            self.shadow(48)
        }
        #[doc = "0xc4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow049(&self) -> &SHADOW {
            self.shadow(49)
        }
        #[doc = "0xc8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow050(&self) -> &SHADOW {
            self.shadow(50)
        }
        #[doc = "0xcc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow051(&self) -> &SHADOW {
            self.shadow(51)
        }
        #[doc = "0xd0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow052(&self) -> &SHADOW {
            self.shadow(52)
        }
        #[doc = "0xd4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow053(&self) -> &SHADOW {
            self.shadow(53)
        }
        #[doc = "0xd8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow054(&self) -> &SHADOW {
            self.shadow(54)
        }
        #[doc = "0xdc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow055(&self) -> &SHADOW {
            self.shadow(55)
        }
        #[doc = "0xe0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow056(&self) -> &SHADOW {
            self.shadow(56)
        }
        #[doc = "0xe4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow057(&self) -> &SHADOW {
            self.shadow(57)
        }
        #[doc = "0xe8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow058(&self) -> &SHADOW {
            self.shadow(58)
        }
        #[doc = "0xec - no description available"]
        #[inline(always)]
        pub const fn shadowshadow059(&self) -> &SHADOW {
            self.shadow(59)
        }
        #[doc = "0xf0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow060(&self) -> &SHADOW {
            self.shadow(60)
        }
        #[doc = "0xf4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow061(&self) -> &SHADOW {
            self.shadow(61)
        }
        #[doc = "0xf8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow062(&self) -> &SHADOW {
            self.shadow(62)
        }
        #[doc = "0xfc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow063(&self) -> &SHADOW {
            self.shadow(63)
        }
        #[doc = "0x100 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow064(&self) -> &SHADOW {
            self.shadow(64)
        }
        #[doc = "0x104 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow065(&self) -> &SHADOW {
            self.shadow(65)
        }
        #[doc = "0x108 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow066(&self) -> &SHADOW {
            self.shadow(66)
        }
        #[doc = "0x10c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow067(&self) -> &SHADOW {
            self.shadow(67)
        }
        #[doc = "0x110 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow068(&self) -> &SHADOW {
            self.shadow(68)
        }
        #[doc = "0x114 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow069(&self) -> &SHADOW {
            self.shadow(69)
        }
        #[doc = "0x118 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow070(&self) -> &SHADOW {
            self.shadow(70)
        }
        #[doc = "0x11c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow071(&self) -> &SHADOW {
            self.shadow(71)
        }
        #[doc = "0x120 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow072(&self) -> &SHADOW {
            self.shadow(72)
        }
        #[doc = "0x124 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow073(&self) -> &SHADOW {
            self.shadow(73)
        }
        #[doc = "0x128 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow074(&self) -> &SHADOW {
            self.shadow(74)
        }
        #[doc = "0x12c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow075(&self) -> &SHADOW {
            self.shadow(75)
        }
        #[doc = "0x130 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow076(&self) -> &SHADOW {
            self.shadow(76)
        }
        #[doc = "0x134 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow077(&self) -> &SHADOW {
            self.shadow(77)
        }
        #[doc = "0x138 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow078(&self) -> &SHADOW {
            self.shadow(78)
        }
        #[doc = "0x13c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow079(&self) -> &SHADOW {
            self.shadow(79)
        }
        #[doc = "0x140 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow080(&self) -> &SHADOW {
            self.shadow(80)
        }
        #[doc = "0x144 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow081(&self) -> &SHADOW {
            self.shadow(81)
        }
        #[doc = "0x148 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow082(&self) -> &SHADOW {
            self.shadow(82)
        }
        #[doc = "0x14c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow083(&self) -> &SHADOW {
            self.shadow(83)
        }
        #[doc = "0x150 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow084(&self) -> &SHADOW {
            self.shadow(84)
        }
        #[doc = "0x154 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow085(&self) -> &SHADOW {
            self.shadow(85)
        }
        #[doc = "0x158 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow086(&self) -> &SHADOW {
            self.shadow(86)
        }
        #[doc = "0x15c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow087(&self) -> &SHADOW {
            self.shadow(87)
        }
        #[doc = "0x160 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow088(&self) -> &SHADOW {
            self.shadow(88)
        }
        #[doc = "0x164 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow089(&self) -> &SHADOW {
            self.shadow(89)
        }
        #[doc = "0x168 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow090(&self) -> &SHADOW {
            self.shadow(90)
        }
        #[doc = "0x16c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow091(&self) -> &SHADOW {
            self.shadow(91)
        }
        #[doc = "0x170 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow092(&self) -> &SHADOW {
            self.shadow(92)
        }
        #[doc = "0x174 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow093(&self) -> &SHADOW {
            self.shadow(93)
        }
        #[doc = "0x178 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow094(&self) -> &SHADOW {
            self.shadow(94)
        }
        #[doc = "0x17c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow095(&self) -> &SHADOW {
            self.shadow(95)
        }
        #[doc = "0x180 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow096(&self) -> &SHADOW {
            self.shadow(96)
        }
        #[doc = "0x184 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow097(&self) -> &SHADOW {
            self.shadow(97)
        }
        #[doc = "0x188 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow098(&self) -> &SHADOW {
            self.shadow(98)
        }
        #[doc = "0x18c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow099(&self) -> &SHADOW {
            self.shadow(99)
        }
        #[doc = "0x190 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow100(&self) -> &SHADOW {
            self.shadow(100)
        }
        #[doc = "0x194 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow101(&self) -> &SHADOW {
            self.shadow(101)
        }
        #[doc = "0x198 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow102(&self) -> &SHADOW {
            self.shadow(102)
        }
        #[doc = "0x19c - no description available"]
        #[inline(always)]
        pub const fn shadowshadow103(&self) -> &SHADOW {
            self.shadow(103)
        }
        #[doc = "0x1a0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow104(&self) -> &SHADOW {
            self.shadow(104)
        }
        #[doc = "0x1a4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow105(&self) -> &SHADOW {
            self.shadow(105)
        }
        #[doc = "0x1a8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow106(&self) -> &SHADOW {
            self.shadow(106)
        }
        #[doc = "0x1ac - no description available"]
        #[inline(always)]
        pub const fn shadowshadow107(&self) -> &SHADOW {
            self.shadow(107)
        }
        #[doc = "0x1b0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow108(&self) -> &SHADOW {
            self.shadow(108)
        }
        #[doc = "0x1b4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow109(&self) -> &SHADOW {
            self.shadow(109)
        }
        #[doc = "0x1b8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow110(&self) -> &SHADOW {
            self.shadow(110)
        }
        #[doc = "0x1bc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow111(&self) -> &SHADOW {
            self.shadow(111)
        }
        #[doc = "0x1c0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow112(&self) -> &SHADOW {
            self.shadow(112)
        }
        #[doc = "0x1c4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow113(&self) -> &SHADOW {
            self.shadow(113)
        }
        #[doc = "0x1c8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow114(&self) -> &SHADOW {
            self.shadow(114)
        }
        #[doc = "0x1cc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow115(&self) -> &SHADOW {
            self.shadow(115)
        }
        #[doc = "0x1d0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow116(&self) -> &SHADOW {
            self.shadow(116)
        }
        #[doc = "0x1d4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow117(&self) -> &SHADOW {
            self.shadow(117)
        }
        #[doc = "0x1d8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow118(&self) -> &SHADOW {
            self.shadow(118)
        }
        #[doc = "0x1dc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow119(&self) -> &SHADOW {
            self.shadow(119)
        }
        #[doc = "0x1e0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow120(&self) -> &SHADOW {
            self.shadow(120)
        }
        #[doc = "0x1e4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow121(&self) -> &SHADOW {
            self.shadow(121)
        }
        #[doc = "0x1e8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow122(&self) -> &SHADOW {
            self.shadow(122)
        }
        #[doc = "0x1ec - no description available"]
        #[inline(always)]
        pub const fn shadowshadow123(&self) -> &SHADOW {
            self.shadow(123)
        }
        #[doc = "0x1f0 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow124(&self) -> &SHADOW {
            self.shadow(124)
        }
        #[doc = "0x1f4 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow125(&self) -> &SHADOW {
            self.shadow(125)
        }
        #[doc = "0x1f8 - no description available"]
        #[inline(always)]
        pub const fn shadowshadow126(&self) -> &SHADOW {
            self.shadow(126)
        }
        #[doc = "0x1fc - no description available"]
        #[inline(always)]
        pub const fn shadowshadow127(&self) -> &SHADOW {
            self.shadow(127)
        }
        #[doc = "0x200..0x220 - no description available"]
        #[inline(always)]
        pub const fn shadow_lock(&self, n: usize) -> &SHADOW_LOCK {
            &self.shadow_lock[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x200..0x220 - no description available"]
        #[inline(always)]
        pub fn shadow_lock_iter(&self) -> impl Iterator<Item = &SHADOW_LOCK> {
            self.shadow_lock.iter()
        }
        #[doc = "0x200 - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock00(&self) -> &SHADOW_LOCK {
            self.shadow_lock(0)
        }
        #[doc = "0x204 - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock01(&self) -> &SHADOW_LOCK {
            self.shadow_lock(1)
        }
        #[doc = "0x208 - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock02(&self) -> &SHADOW_LOCK {
            self.shadow_lock(2)
        }
        #[doc = "0x20c - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock03(&self) -> &SHADOW_LOCK {
            self.shadow_lock(3)
        }
        #[doc = "0x210 - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock04(&self) -> &SHADOW_LOCK {
            self.shadow_lock(4)
        }
        #[doc = "0x214 - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock05(&self) -> &SHADOW_LOCK {
            self.shadow_lock(5)
        }
        #[doc = "0x218 - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock06(&self) -> &SHADOW_LOCK {
            self.shadow_lock(6)
        }
        #[doc = "0x21c - no description available"]
        #[inline(always)]
        pub const fn shadow_locklock07(&self) -> &SHADOW_LOCK {
            self.shadow_lock(7)
        }
        #[doc = "0x400..0x600 - no description available"]
        #[inline(always)]
        pub const fn fuse(&self, n: usize) -> &FUSE {
            &self.fuse[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x400..0x600 - no description available"]
        #[inline(always)]
        pub fn fuse_iter(&self) -> impl Iterator<Item = &FUSE> {
            self.fuse.iter()
        }
        #[doc = "0x400 - no description available"]
        #[inline(always)]
        pub const fn fusefuse000(&self) -> &FUSE {
            self.fuse(0)
        }
        #[doc = "0x404 - no description available"]
        #[inline(always)]
        pub const fn fusefuse001(&self) -> &FUSE {
            self.fuse(1)
        }
        #[doc = "0x408 - no description available"]
        #[inline(always)]
        pub const fn fusefuse002(&self) -> &FUSE {
            self.fuse(2)
        }
        #[doc = "0x40c - no description available"]
        #[inline(always)]
        pub const fn fusefuse003(&self) -> &FUSE {
            self.fuse(3)
        }
        #[doc = "0x410 - no description available"]
        #[inline(always)]
        pub const fn fusefuse004(&self) -> &FUSE {
            self.fuse(4)
        }
        #[doc = "0x414 - no description available"]
        #[inline(always)]
        pub const fn fusefuse005(&self) -> &FUSE {
            self.fuse(5)
        }
        #[doc = "0x418 - no description available"]
        #[inline(always)]
        pub const fn fusefuse006(&self) -> &FUSE {
            self.fuse(6)
        }
        #[doc = "0x41c - no description available"]
        #[inline(always)]
        pub const fn fusefuse007(&self) -> &FUSE {
            self.fuse(7)
        }
        #[doc = "0x420 - no description available"]
        #[inline(always)]
        pub const fn fusefuse008(&self) -> &FUSE {
            self.fuse(8)
        }
        #[doc = "0x424 - no description available"]
        #[inline(always)]
        pub const fn fusefuse009(&self) -> &FUSE {
            self.fuse(9)
        }
        #[doc = "0x428 - no description available"]
        #[inline(always)]
        pub const fn fusefuse010(&self) -> &FUSE {
            self.fuse(10)
        }
        #[doc = "0x42c - no description available"]
        #[inline(always)]
        pub const fn fusefuse011(&self) -> &FUSE {
            self.fuse(11)
        }
        #[doc = "0x430 - no description available"]
        #[inline(always)]
        pub const fn fusefuse012(&self) -> &FUSE {
            self.fuse(12)
        }
        #[doc = "0x434 - no description available"]
        #[inline(always)]
        pub const fn fusefuse013(&self) -> &FUSE {
            self.fuse(13)
        }
        #[doc = "0x438 - no description available"]
        #[inline(always)]
        pub const fn fusefuse014(&self) -> &FUSE {
            self.fuse(14)
        }
        #[doc = "0x43c - no description available"]
        #[inline(always)]
        pub const fn fusefuse015(&self) -> &FUSE {
            self.fuse(15)
        }
        #[doc = "0x440 - no description available"]
        #[inline(always)]
        pub const fn fusefuse016(&self) -> &FUSE {
            self.fuse(16)
        }
        #[doc = "0x444 - no description available"]
        #[inline(always)]
        pub const fn fusefuse017(&self) -> &FUSE {
            self.fuse(17)
        }
        #[doc = "0x448 - no description available"]
        #[inline(always)]
        pub const fn fusefuse018(&self) -> &FUSE {
            self.fuse(18)
        }
        #[doc = "0x44c - no description available"]
        #[inline(always)]
        pub const fn fusefuse019(&self) -> &FUSE {
            self.fuse(19)
        }
        #[doc = "0x450 - no description available"]
        #[inline(always)]
        pub const fn fusefuse020(&self) -> &FUSE {
            self.fuse(20)
        }
        #[doc = "0x454 - no description available"]
        #[inline(always)]
        pub const fn fusefuse021(&self) -> &FUSE {
            self.fuse(21)
        }
        #[doc = "0x458 - no description available"]
        #[inline(always)]
        pub const fn fusefuse022(&self) -> &FUSE {
            self.fuse(22)
        }
        #[doc = "0x45c - no description available"]
        #[inline(always)]
        pub const fn fusefuse023(&self) -> &FUSE {
            self.fuse(23)
        }
        #[doc = "0x460 - no description available"]
        #[inline(always)]
        pub const fn fusefuse024(&self) -> &FUSE {
            self.fuse(24)
        }
        #[doc = "0x464 - no description available"]
        #[inline(always)]
        pub const fn fusefuse025(&self) -> &FUSE {
            self.fuse(25)
        }
        #[doc = "0x468 - no description available"]
        #[inline(always)]
        pub const fn fusefuse026(&self) -> &FUSE {
            self.fuse(26)
        }
        #[doc = "0x46c - no description available"]
        #[inline(always)]
        pub const fn fusefuse027(&self) -> &FUSE {
            self.fuse(27)
        }
        #[doc = "0x470 - no description available"]
        #[inline(always)]
        pub const fn fusefuse028(&self) -> &FUSE {
            self.fuse(28)
        }
        #[doc = "0x474 - no description available"]
        #[inline(always)]
        pub const fn fusefuse029(&self) -> &FUSE {
            self.fuse(29)
        }
        #[doc = "0x478 - no description available"]
        #[inline(always)]
        pub const fn fusefuse030(&self) -> &FUSE {
            self.fuse(30)
        }
        #[doc = "0x47c - no description available"]
        #[inline(always)]
        pub const fn fusefuse031(&self) -> &FUSE {
            self.fuse(31)
        }
        #[doc = "0x480 - no description available"]
        #[inline(always)]
        pub const fn fusefuse032(&self) -> &FUSE {
            self.fuse(32)
        }
        #[doc = "0x484 - no description available"]
        #[inline(always)]
        pub const fn fusefuse033(&self) -> &FUSE {
            self.fuse(33)
        }
        #[doc = "0x488 - no description available"]
        #[inline(always)]
        pub const fn fusefuse034(&self) -> &FUSE {
            self.fuse(34)
        }
        #[doc = "0x48c - no description available"]
        #[inline(always)]
        pub const fn fusefuse035(&self) -> &FUSE {
            self.fuse(35)
        }
        #[doc = "0x490 - no description available"]
        #[inline(always)]
        pub const fn fusefuse036(&self) -> &FUSE {
            self.fuse(36)
        }
        #[doc = "0x494 - no description available"]
        #[inline(always)]
        pub const fn fusefuse037(&self) -> &FUSE {
            self.fuse(37)
        }
        #[doc = "0x498 - no description available"]
        #[inline(always)]
        pub const fn fusefuse038(&self) -> &FUSE {
            self.fuse(38)
        }
        #[doc = "0x49c - no description available"]
        #[inline(always)]
        pub const fn fusefuse039(&self) -> &FUSE {
            self.fuse(39)
        }
        #[doc = "0x4a0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse040(&self) -> &FUSE {
            self.fuse(40)
        }
        #[doc = "0x4a4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse041(&self) -> &FUSE {
            self.fuse(41)
        }
        #[doc = "0x4a8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse042(&self) -> &FUSE {
            self.fuse(42)
        }
        #[doc = "0x4ac - no description available"]
        #[inline(always)]
        pub const fn fusefuse043(&self) -> &FUSE {
            self.fuse(43)
        }
        #[doc = "0x4b0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse044(&self) -> &FUSE {
            self.fuse(44)
        }
        #[doc = "0x4b4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse045(&self) -> &FUSE {
            self.fuse(45)
        }
        #[doc = "0x4b8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse046(&self) -> &FUSE {
            self.fuse(46)
        }
        #[doc = "0x4bc - no description available"]
        #[inline(always)]
        pub const fn fusefuse047(&self) -> &FUSE {
            self.fuse(47)
        }
        #[doc = "0x4c0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse048(&self) -> &FUSE {
            self.fuse(48)
        }
        #[doc = "0x4c4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse049(&self) -> &FUSE {
            self.fuse(49)
        }
        #[doc = "0x4c8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse050(&self) -> &FUSE {
            self.fuse(50)
        }
        #[doc = "0x4cc - no description available"]
        #[inline(always)]
        pub const fn fusefuse051(&self) -> &FUSE {
            self.fuse(51)
        }
        #[doc = "0x4d0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse052(&self) -> &FUSE {
            self.fuse(52)
        }
        #[doc = "0x4d4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse053(&self) -> &FUSE {
            self.fuse(53)
        }
        #[doc = "0x4d8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse054(&self) -> &FUSE {
            self.fuse(54)
        }
        #[doc = "0x4dc - no description available"]
        #[inline(always)]
        pub const fn fusefuse055(&self) -> &FUSE {
            self.fuse(55)
        }
        #[doc = "0x4e0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse056(&self) -> &FUSE {
            self.fuse(56)
        }
        #[doc = "0x4e4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse057(&self) -> &FUSE {
            self.fuse(57)
        }
        #[doc = "0x4e8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse058(&self) -> &FUSE {
            self.fuse(58)
        }
        #[doc = "0x4ec - no description available"]
        #[inline(always)]
        pub const fn fusefuse059(&self) -> &FUSE {
            self.fuse(59)
        }
        #[doc = "0x4f0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse060(&self) -> &FUSE {
            self.fuse(60)
        }
        #[doc = "0x4f4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse061(&self) -> &FUSE {
            self.fuse(61)
        }
        #[doc = "0x4f8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse062(&self) -> &FUSE {
            self.fuse(62)
        }
        #[doc = "0x4fc - no description available"]
        #[inline(always)]
        pub const fn fusefuse063(&self) -> &FUSE {
            self.fuse(63)
        }
        #[doc = "0x500 - no description available"]
        #[inline(always)]
        pub const fn fusefuse064(&self) -> &FUSE {
            self.fuse(64)
        }
        #[doc = "0x504 - no description available"]
        #[inline(always)]
        pub const fn fusefuse065(&self) -> &FUSE {
            self.fuse(65)
        }
        #[doc = "0x508 - no description available"]
        #[inline(always)]
        pub const fn fusefuse066(&self) -> &FUSE {
            self.fuse(66)
        }
        #[doc = "0x50c - no description available"]
        #[inline(always)]
        pub const fn fusefuse067(&self) -> &FUSE {
            self.fuse(67)
        }
        #[doc = "0x510 - no description available"]
        #[inline(always)]
        pub const fn fusefuse068(&self) -> &FUSE {
            self.fuse(68)
        }
        #[doc = "0x514 - no description available"]
        #[inline(always)]
        pub const fn fusefuse069(&self) -> &FUSE {
            self.fuse(69)
        }
        #[doc = "0x518 - no description available"]
        #[inline(always)]
        pub const fn fusefuse070(&self) -> &FUSE {
            self.fuse(70)
        }
        #[doc = "0x51c - no description available"]
        #[inline(always)]
        pub const fn fusefuse071(&self) -> &FUSE {
            self.fuse(71)
        }
        #[doc = "0x520 - no description available"]
        #[inline(always)]
        pub const fn fusefuse072(&self) -> &FUSE {
            self.fuse(72)
        }
        #[doc = "0x524 - no description available"]
        #[inline(always)]
        pub const fn fusefuse073(&self) -> &FUSE {
            self.fuse(73)
        }
        #[doc = "0x528 - no description available"]
        #[inline(always)]
        pub const fn fusefuse074(&self) -> &FUSE {
            self.fuse(74)
        }
        #[doc = "0x52c - no description available"]
        #[inline(always)]
        pub const fn fusefuse075(&self) -> &FUSE {
            self.fuse(75)
        }
        #[doc = "0x530 - no description available"]
        #[inline(always)]
        pub const fn fusefuse076(&self) -> &FUSE {
            self.fuse(76)
        }
        #[doc = "0x534 - no description available"]
        #[inline(always)]
        pub const fn fusefuse077(&self) -> &FUSE {
            self.fuse(77)
        }
        #[doc = "0x538 - no description available"]
        #[inline(always)]
        pub const fn fusefuse078(&self) -> &FUSE {
            self.fuse(78)
        }
        #[doc = "0x53c - no description available"]
        #[inline(always)]
        pub const fn fusefuse079(&self) -> &FUSE {
            self.fuse(79)
        }
        #[doc = "0x540 - no description available"]
        #[inline(always)]
        pub const fn fusefuse080(&self) -> &FUSE {
            self.fuse(80)
        }
        #[doc = "0x544 - no description available"]
        #[inline(always)]
        pub const fn fusefuse081(&self) -> &FUSE {
            self.fuse(81)
        }
        #[doc = "0x548 - no description available"]
        #[inline(always)]
        pub const fn fusefuse082(&self) -> &FUSE {
            self.fuse(82)
        }
        #[doc = "0x54c - no description available"]
        #[inline(always)]
        pub const fn fusefuse083(&self) -> &FUSE {
            self.fuse(83)
        }
        #[doc = "0x550 - no description available"]
        #[inline(always)]
        pub const fn fusefuse084(&self) -> &FUSE {
            self.fuse(84)
        }
        #[doc = "0x554 - no description available"]
        #[inline(always)]
        pub const fn fusefuse085(&self) -> &FUSE {
            self.fuse(85)
        }
        #[doc = "0x558 - no description available"]
        #[inline(always)]
        pub const fn fusefuse086(&self) -> &FUSE {
            self.fuse(86)
        }
        #[doc = "0x55c - no description available"]
        #[inline(always)]
        pub const fn fusefuse087(&self) -> &FUSE {
            self.fuse(87)
        }
        #[doc = "0x560 - no description available"]
        #[inline(always)]
        pub const fn fusefuse088(&self) -> &FUSE {
            self.fuse(88)
        }
        #[doc = "0x564 - no description available"]
        #[inline(always)]
        pub const fn fusefuse089(&self) -> &FUSE {
            self.fuse(89)
        }
        #[doc = "0x568 - no description available"]
        #[inline(always)]
        pub const fn fusefuse090(&self) -> &FUSE {
            self.fuse(90)
        }
        #[doc = "0x56c - no description available"]
        #[inline(always)]
        pub const fn fusefuse091(&self) -> &FUSE {
            self.fuse(91)
        }
        #[doc = "0x570 - no description available"]
        #[inline(always)]
        pub const fn fusefuse092(&self) -> &FUSE {
            self.fuse(92)
        }
        #[doc = "0x574 - no description available"]
        #[inline(always)]
        pub const fn fusefuse093(&self) -> &FUSE {
            self.fuse(93)
        }
        #[doc = "0x578 - no description available"]
        #[inline(always)]
        pub const fn fusefuse094(&self) -> &FUSE {
            self.fuse(94)
        }
        #[doc = "0x57c - no description available"]
        #[inline(always)]
        pub const fn fusefuse095(&self) -> &FUSE {
            self.fuse(95)
        }
        #[doc = "0x580 - no description available"]
        #[inline(always)]
        pub const fn fusefuse096(&self) -> &FUSE {
            self.fuse(96)
        }
        #[doc = "0x584 - no description available"]
        #[inline(always)]
        pub const fn fusefuse097(&self) -> &FUSE {
            self.fuse(97)
        }
        #[doc = "0x588 - no description available"]
        #[inline(always)]
        pub const fn fusefuse098(&self) -> &FUSE {
            self.fuse(98)
        }
        #[doc = "0x58c - no description available"]
        #[inline(always)]
        pub const fn fusefuse099(&self) -> &FUSE {
            self.fuse(99)
        }
        #[doc = "0x590 - no description available"]
        #[inline(always)]
        pub const fn fusefuse100(&self) -> &FUSE {
            self.fuse(100)
        }
        #[doc = "0x594 - no description available"]
        #[inline(always)]
        pub const fn fusefuse101(&self) -> &FUSE {
            self.fuse(101)
        }
        #[doc = "0x598 - no description available"]
        #[inline(always)]
        pub const fn fusefuse102(&self) -> &FUSE {
            self.fuse(102)
        }
        #[doc = "0x59c - no description available"]
        #[inline(always)]
        pub const fn fusefuse103(&self) -> &FUSE {
            self.fuse(103)
        }
        #[doc = "0x5a0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse104(&self) -> &FUSE {
            self.fuse(104)
        }
        #[doc = "0x5a4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse105(&self) -> &FUSE {
            self.fuse(105)
        }
        #[doc = "0x5a8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse106(&self) -> &FUSE {
            self.fuse(106)
        }
        #[doc = "0x5ac - no description available"]
        #[inline(always)]
        pub const fn fusefuse107(&self) -> &FUSE {
            self.fuse(107)
        }
        #[doc = "0x5b0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse108(&self) -> &FUSE {
            self.fuse(108)
        }
        #[doc = "0x5b4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse109(&self) -> &FUSE {
            self.fuse(109)
        }
        #[doc = "0x5b8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse110(&self) -> &FUSE {
            self.fuse(110)
        }
        #[doc = "0x5bc - no description available"]
        #[inline(always)]
        pub const fn fusefuse111(&self) -> &FUSE {
            self.fuse(111)
        }
        #[doc = "0x5c0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse112(&self) -> &FUSE {
            self.fuse(112)
        }
        #[doc = "0x5c4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse113(&self) -> &FUSE {
            self.fuse(113)
        }
        #[doc = "0x5c8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse114(&self) -> &FUSE {
            self.fuse(114)
        }
        #[doc = "0x5cc - no description available"]
        #[inline(always)]
        pub const fn fusefuse115(&self) -> &FUSE {
            self.fuse(115)
        }
        #[doc = "0x5d0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse116(&self) -> &FUSE {
            self.fuse(116)
        }
        #[doc = "0x5d4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse117(&self) -> &FUSE {
            self.fuse(117)
        }
        #[doc = "0x5d8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse118(&self) -> &FUSE {
            self.fuse(118)
        }
        #[doc = "0x5dc - no description available"]
        #[inline(always)]
        pub const fn fusefuse119(&self) -> &FUSE {
            self.fuse(119)
        }
        #[doc = "0x5e0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse120(&self) -> &FUSE {
            self.fuse(120)
        }
        #[doc = "0x5e4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse121(&self) -> &FUSE {
            self.fuse(121)
        }
        #[doc = "0x5e8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse122(&self) -> &FUSE {
            self.fuse(122)
        }
        #[doc = "0x5ec - no description available"]
        #[inline(always)]
        pub const fn fusefuse123(&self) -> &FUSE {
            self.fuse(123)
        }
        #[doc = "0x5f0 - no description available"]
        #[inline(always)]
        pub const fn fusefuse124(&self) -> &FUSE {
            self.fuse(124)
        }
        #[doc = "0x5f4 - no description available"]
        #[inline(always)]
        pub const fn fusefuse125(&self) -> &FUSE {
            self.fuse(125)
        }
        #[doc = "0x5f8 - no description available"]
        #[inline(always)]
        pub const fn fusefuse126(&self) -> &FUSE {
            self.fuse(126)
        }
        #[doc = "0x5fc - no description available"]
        #[inline(always)]
        pub const fn fusefuse127(&self) -> &FUSE {
            self.fuse(127)
        }
        #[doc = "0x600..0x620 - no description available"]
        #[inline(always)]
        pub const fn fuse_lock(&self, n: usize) -> &FUSE_LOCK {
            &self.fuse_lock[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x600..0x620 - no description available"]
        #[inline(always)]
        pub fn fuse_lock_iter(&self) -> impl Iterator<Item = &FUSE_LOCK> {
            self.fuse_lock.iter()
        }
        #[doc = "0x600 - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock00(&self) -> &FUSE_LOCK {
            self.fuse_lock(0)
        }
        #[doc = "0x604 - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock01(&self) -> &FUSE_LOCK {
            self.fuse_lock(1)
        }
        #[doc = "0x608 - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock02(&self) -> &FUSE_LOCK {
            self.fuse_lock(2)
        }
        #[doc = "0x60c - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock03(&self) -> &FUSE_LOCK {
            self.fuse_lock(3)
        }
        #[doc = "0x610 - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock04(&self) -> &FUSE_LOCK {
            self.fuse_lock(4)
        }
        #[doc = "0x614 - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock05(&self) -> &FUSE_LOCK {
            self.fuse_lock(5)
        }
        #[doc = "0x618 - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock06(&self) -> &FUSE_LOCK {
            self.fuse_lock(6)
        }
        #[doc = "0x61c - no description available"]
        #[inline(always)]
        pub const fn fuse_locklock07(&self) -> &FUSE_LOCK {
            self.fuse_lock(7)
        }
        #[doc = "0x800 - UNLOCK"]
        #[inline(always)]
        pub const fn unlock(&self) -> &UNLOCK {
            &self.unlock
        }
        #[doc = "0x804 - DATA"]
        #[inline(always)]
        pub const fn data(&self) -> &DATA {
            &self.data
        }
        #[doc = "0x808 - ADDR"]
        #[inline(always)]
        pub const fn addr(&self) -> &ADDR {
            &self.addr
        }
        #[doc = "0x80c - CMD"]
        #[inline(always)]
        pub const fn cmd(&self) -> &CMD {
            &self.cmd
        }
        #[doc = "0xa00 - LOAD Request"]
        #[inline(always)]
        pub const fn load_req(&self) -> &LOAD_REQ {
            &self.load_req
        }
        #[doc = "0xa04 - LOAD complete"]
        #[inline(always)]
        pub const fn load_comp(&self) -> &LOAD_COMP {
            &self.load_comp
        }
        #[doc = "0xa20..0xa30 - no description available"]
        #[inline(always)]
        pub const fn region(&self, n: usize) -> &REGION {
            &self.region[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0xa20..0xa30 - no description available"]
        #[inline(always)]
        pub fn region_iter(&self) -> impl Iterator<Item = &REGION> {
            self.region.iter()
        }
        #[doc = "0xa20 - no description available"]
        #[inline(always)]
        pub const fn regionload_region0(&self) -> &REGION {
            self.region(0)
        }
        #[doc = "0xa24 - no description available"]
        #[inline(always)]
        pub const fn regionload_region1(&self) -> &REGION {
            self.region(1)
        }
        #[doc = "0xa28 - no description available"]
        #[inline(always)]
        pub const fn regionload_region2(&self) -> &REGION {
            self.region(2)
        }
        #[doc = "0xa2c - no description available"]
        #[inline(always)]
        pub const fn regionload_region3(&self) -> &REGION {
            self.region(3)
        }
        #[doc = "0xc00 - interrupt flag"]
        #[inline(always)]
        pub const fn int_flag(&self) -> &INT_FLAG {
            &self.int_flag
        }
        #[doc = "0xc04 - interrupt enable"]
        #[inline(always)]
        pub const fn int_en(&self) -> &INT_EN {
            &self.int_en
        }
    }
    #[doc = "SHADOW (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shadow::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shadow::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shadow`]
module"]
    pub type SHADOW = crate::Reg<shadow::SHADOW_SPEC>;
    #[doc = "no description available"]
    pub mod shadow {
        #[doc = "Register `SHADOW[%s]` reader"]
        pub type R = crate::R<SHADOW_SPEC>;
        #[doc = "Register `SHADOW[%s]` writer"]
        pub type W = crate::W<SHADOW_SPEC>;
        #[doc = "Field `SHADOW` reader - shadow register of fuse for pmic area for PMIC, index valid for 0-15, for SOC index valid for 16-128"]
        pub type SHADOW_R = crate::FieldReader<u32>;
        #[doc = "Field `SHADOW` writer - shadow register of fuse for pmic area for PMIC, index valid for 0-15, for SOC index valid for 16-128"]
        pub type SHADOW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - shadow register of fuse for pmic area for PMIC, index valid for 0-15, for SOC index valid for 16-128"]
            #[inline(always)]
            pub fn shadow(&self) -> SHADOW_R {
                SHADOW_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - shadow register of fuse for pmic area for PMIC, index valid for 0-15, for SOC index valid for 16-128"]
            #[inline(always)]
            #[must_use]
            pub fn shadow(&mut self) -> SHADOW_W<SHADOW_SPEC> {
                SHADOW_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shadow::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shadow::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SHADOW_SPEC;
        impl crate::RegisterSpec for SHADOW_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`shadow::R`](R) reader structure"]
        impl crate::Readable for SHADOW_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`shadow::W`](W) writer structure"]
        impl crate::Writable for SHADOW_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SHADOW[%s]
to value 0"]
        impl crate::Resettable for SHADOW_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SHADOW_LOCK (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shadow_lock::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shadow_lock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shadow_lock`]
module"]
    pub type SHADOW_LOCK = crate::Reg<shadow_lock::SHADOW_LOCK_SPEC>;
    #[doc = "no description available"]
    pub mod shadow_lock {
        #[doc = "Register `SHADOW_LOCK[%s]` reader"]
        pub type R = crate::R<SHADOW_LOCK_SPEC>;
        #[doc = "Register `SHADOW_LOCK[%s]` writer"]
        pub type W = crate::W<SHADOW_LOCK_SPEC>;
        #[doc = "Field `LOCK` reader - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
        pub type LOCK_R = crate::FieldReader<u32>;
        #[doc = "Field `LOCK` writer - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
        pub type LOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
            #[inline(always)]
            #[must_use]
            pub fn lock(&mut self) -> LOCK_W<SHADOW_LOCK_SPEC> {
                LOCK_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shadow_lock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shadow_lock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SHADOW_LOCK_SPEC;
        impl crate::RegisterSpec for SHADOW_LOCK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`shadow_lock::R`](R) reader structure"]
        impl crate::Readable for SHADOW_LOCK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`shadow_lock::W`](W) writer structure"]
        impl crate::Writable for SHADOW_LOCK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SHADOW_LOCK[%s]
to value 0"]
        impl crate::Resettable for SHADOW_LOCK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "FUSE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fuse::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fuse::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fuse`]
module"]
    pub type FUSE = crate::Reg<fuse::FUSE_SPEC>;
    #[doc = "no description available"]
    pub mod fuse {
        #[doc = "Register `FUSE[%s]` reader"]
        pub type R = crate::R<FUSE_SPEC>;
        #[doc = "Register `FUSE[%s]` writer"]
        pub type W = crate::W<FUSE_SPEC>;
        #[doc = "Field `FUSE` reader - fuse array, valid in PMIC part only read operation will read out value in fuse array write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready)"]
        pub type FUSE_R = crate::FieldReader<u32>;
        #[doc = "Field `FUSE` writer - fuse array, valid in PMIC part only read operation will read out value in fuse array write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready)"]
        pub type FUSE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - fuse array, valid in PMIC part only read operation will read out value in fuse array write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready)"]
            #[inline(always)]
            pub fn fuse(&self) -> FUSE_R {
                FUSE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - fuse array, valid in PMIC part only read operation will read out value in fuse array write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready)"]
            #[inline(always)]
            #[must_use]
            pub fn fuse(&mut self) -> FUSE_W<FUSE_SPEC> {
                FUSE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fuse::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fuse::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FUSE_SPEC;
        impl crate::RegisterSpec for FUSE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`fuse::R`](R) reader structure"]
        impl crate::Readable for FUSE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`fuse::W`](W) writer structure"]
        impl crate::Writable for FUSE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FUSE[%s]
to value 0"]
        impl crate::Resettable for FUSE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "FUSE_LOCK (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fuse_lock::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fuse_lock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fuse_lock`]
module"]
    pub type FUSE_LOCK = crate::Reg<fuse_lock::FUSE_LOCK_SPEC>;
    #[doc = "no description available"]
    pub mod fuse_lock {
        #[doc = "Register `FUSE_LOCK[%s]` reader"]
        pub type R = crate::R<FUSE_LOCK_SPEC>;
        #[doc = "Register `FUSE_LOCK[%s]` writer"]
        pub type W = crate::W<FUSE_LOCK_SPEC>;
        #[doc = "Field `LOCK` reader - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
        pub type LOCK_R = crate::FieldReader<u32>;
        #[doc = "Field `LOCK` writer - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
        pub type LOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
            #[inline(always)]
            pub fn lock(&self) -> LOCK_R {
                LOCK_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types 00: not locked 01: soft locked 10: not locked, and cannot lock in furture 11: double locked"]
            #[inline(always)]
            #[must_use]
            pub fn lock(&mut self) -> LOCK_W<FUSE_LOCK_SPEC> {
                LOCK_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fuse_lock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fuse_lock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct FUSE_LOCK_SPEC;
        impl crate::RegisterSpec for FUSE_LOCK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`fuse_lock::R`](R) reader structure"]
        impl crate::Readable for FUSE_LOCK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`fuse_lock::W`](W) writer structure"]
        impl crate::Writable for FUSE_LOCK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets FUSE_LOCK[%s]
to value 0"]
        impl crate::Resettable for FUSE_LOCK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "UNLOCK (rw) register accessor: UNLOCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unlock::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unlock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@unlock`]
module"]
    pub type UNLOCK = crate::Reg<unlock::UNLOCK_SPEC>;
    #[doc = "UNLOCK"]
    pub mod unlock {
        #[doc = "Register `UNLOCK` reader"]
        pub type R = crate::R<UNLOCK_SPEC>;
        #[doc = "Register `UNLOCK` writer"]
        pub type W = crate::W<UNLOCK_SPEC>;
        #[doc = "Field `UNLOCK` reader - unlock word for fuse array operation write \"OPEN\" to unlock fuse array, write any other value will lock write to fuse. Please make sure 24M crystal is running and 2.5V LDO working properly"]
        pub type UNLOCK_R = crate::FieldReader<u32>;
        #[doc = "Field `UNLOCK` writer - unlock word for fuse array operation write \"OPEN\" to unlock fuse array, write any other value will lock write to fuse. Please make sure 24M crystal is running and 2.5V LDO working properly"]
        pub type UNLOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - unlock word for fuse array operation write \"OPEN\" to unlock fuse array, write any other value will lock write to fuse. Please make sure 24M crystal is running and 2.5V LDO working properly"]
            #[inline(always)]
            pub fn unlock(&self) -> UNLOCK_R {
                UNLOCK_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - unlock word for fuse array operation write \"OPEN\" to unlock fuse array, write any other value will lock write to fuse. Please make sure 24M crystal is running and 2.5V LDO working properly"]
            #[inline(always)]
            #[must_use]
            pub fn unlock(&mut self) -> UNLOCK_W<UNLOCK_SPEC> {
                UNLOCK_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "UNLOCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`unlock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`unlock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct UNLOCK_SPEC;
        impl crate::RegisterSpec for UNLOCK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`unlock::R`](R) reader structure"]
        impl crate::Readable for UNLOCK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`unlock::W`](W) writer structure"]
        impl crate::Writable for UNLOCK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets UNLOCK to value 0"]
        impl crate::Resettable for UNLOCK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DATA (rw) register accessor: DATA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
    pub type DATA = crate::Reg<data::DATA_SPEC>;
    #[doc = "DATA"]
    pub mod data {
        #[doc = "Register `DATA` reader"]
        pub type R = crate::R<DATA_SPEC>;
        #[doc = "Register `DATA` writer"]
        pub type W = crate::W<DATA_SPEC>;
        #[doc = "Field `DATA` reader - data register for non-blocking access this register hold dat read from fuse array or data to by programmed to fuse array"]
        pub type DATA_R = crate::FieldReader<u32>;
        #[doc = "Field `DATA` writer - data register for non-blocking access this register hold dat read from fuse array or data to by programmed to fuse array"]
        pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - data register for non-blocking access this register hold dat read from fuse array or data to by programmed to fuse array"]
            #[inline(always)]
            pub fn data(&self) -> DATA_R {
                DATA_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - data register for non-blocking access this register hold dat read from fuse array or data to by programmed to fuse array"]
            #[inline(always)]
            #[must_use]
            pub fn data(&mut self) -> DATA_W<DATA_SPEC> {
                DATA_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DATA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DATA_SPEC;
        impl crate::RegisterSpec for DATA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`data::R`](R) reader structure"]
        impl crate::Readable for DATA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
        impl crate::Writable for DATA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DATA to value 0"]
        impl crate::Resettable for DATA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ADDR (rw) register accessor: ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
module"]
    pub type ADDR = crate::Reg<addr::ADDR_SPEC>;
    #[doc = "ADDR"]
    pub mod addr {
        #[doc = "Register `ADDR` reader"]
        pub type R = crate::R<ADDR_SPEC>;
        #[doc = "Register `ADDR` writer"]
        pub type W = crate::W<ADDR_SPEC>;
        #[doc = "Field `ADDR` reader - word address to be read or write"]
        pub type ADDR_R = crate::FieldReader;
        #[doc = "Field `ADDR` writer - word address to be read or write"]
        pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bits 0:6 - word address to be read or write"]
            #[inline(always)]
            pub fn addr(&self) -> ADDR_R {
                ADDR_R::new((self.bits & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - word address to be read or write"]
            #[inline(always)]
            #[must_use]
            pub fn addr(&mut self) -> ADDR_W<ADDR_SPEC> {
                ADDR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "ADDR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADDR_SPEC;
        impl crate::RegisterSpec for ADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`addr::R`](R) reader structure"]
        impl crate::Readable for ADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"]
        impl crate::Writable for ADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ADDR to value 0"]
        impl crate::Resettable for ADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CMD (rw) register accessor: CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"]
    pub type CMD = crate::Reg<cmd::CMD_SPEC>;
    #[doc = "CMD"]
    pub mod cmd {
        #[doc = "Register `CMD` reader"]
        pub type R = crate::R<CMD_SPEC>;
        #[doc = "Register `CMD` writer"]
        pub type W = crate::W<CMD_SPEC>;
        #[doc = "Field `CMD` reader - command to access fure array \"BLOW\" will update fuse word at ADDR to value hold in DATA \"READ\" will fetch fuse value in at ADDR to DATA register"]
        pub type CMD_R = crate::FieldReader<u32>;
        #[doc = "Field `CMD` writer - command to access fure array \"BLOW\" will update fuse word at ADDR to value hold in DATA \"READ\" will fetch fuse value in at ADDR to DATA register"]
        pub type CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - command to access fure array \"BLOW\" will update fuse word at ADDR to value hold in DATA \"READ\" will fetch fuse value in at ADDR to DATA register"]
            #[inline(always)]
            pub fn cmd(&self) -> CMD_R {
                CMD_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - command to access fure array \"BLOW\" will update fuse word at ADDR to value hold in DATA \"READ\" will fetch fuse value in at ADDR to DATA register"]
            #[inline(always)]
            #[must_use]
            pub fn cmd(&mut self) -> CMD_W<CMD_SPEC> {
                CMD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "CMD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CMD_SPEC;
        impl crate::RegisterSpec for CMD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
        impl crate::Readable for CMD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
        impl crate::Writable for CMD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CMD to value 0"]
        impl crate::Resettable for CMD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "LOAD_REQ (rw) register accessor: LOAD Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load_req::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load_req::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load_req`]
module"]
    pub type LOAD_REQ = crate::Reg<load_req::LOAD_REQ_SPEC>;
    #[doc = "LOAD Request"]
    pub mod load_req {
        #[doc = "Register `LOAD_REQ` reader"]
        pub type R = crate::R<LOAD_REQ_SPEC>;
        #[doc = "Register `LOAD_REQ` writer"]
        pub type W = crate::W<LOAD_REQ_SPEC>;
        #[doc = "Field `REQUEST` reader - reload request for 4 regions bit0: region0 bit1: region1 bit2: region2 bit3: region3"]
        pub type REQUEST_R = crate::FieldReader;
        #[doc = "Field `REQUEST` writer - reload request for 4 regions bit0: region0 bit1: region1 bit2: region2 bit3: region3"]
        pub type REQUEST_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3 - reload request for 4 regions bit0: region0 bit1: region1 bit2: region2 bit3: region3"]
            #[inline(always)]
            pub fn request(&self) -> REQUEST_R {
                REQUEST_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - reload request for 4 regions bit0: region0 bit1: region1 bit2: region2 bit3: region3"]
            #[inline(always)]
            #[must_use]
            pub fn request(&mut self) -> REQUEST_W<LOAD_REQ_SPEC> {
                REQUEST_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "LOAD Request\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load_req::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load_req::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LOAD_REQ_SPEC;
        impl crate::RegisterSpec for LOAD_REQ_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`load_req::R`](R) reader structure"]
        impl crate::Readable for LOAD_REQ_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`load_req::W`](W) writer structure"]
        impl crate::Writable for LOAD_REQ_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LOAD_REQ to value 0x07"]
        impl crate::Resettable for LOAD_REQ_SPEC {
            const RESET_VALUE: u32 = 0x07;
        }
    }
    #[doc = "LOAD_COMP (rw) register accessor: LOAD complete\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load_comp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load_comp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load_comp`]
module"]
    pub type LOAD_COMP = crate::Reg<load_comp::LOAD_COMP_SPEC>;
    #[doc = "LOAD complete"]
    pub mod load_comp {
        #[doc = "Register `LOAD_COMP` reader"]
        pub type R = crate::R<LOAD_COMP_SPEC>;
        #[doc = "Register `LOAD_COMP` writer"]
        pub type W = crate::W<LOAD_COMP_SPEC>;
        #[doc = "Field `COMPLETE` reader - reload complete sign for 4 regions bit0: region 0 bit1: region1 bit2: region2 bit3: region3"]
        pub type COMPLETE_R = crate::FieldReader;
        #[doc = "Field `COMPLETE` writer - reload complete sign for 4 regions bit0: region 0 bit1: region1 bit2: region2 bit3: region3"]
        pub type COMPLETE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        impl R {
            #[doc = "Bits 0:3 - reload complete sign for 4 regions bit0: region 0 bit1: region1 bit2: region2 bit3: region3"]
            #[inline(always)]
            pub fn complete(&self) -> COMPLETE_R {
                COMPLETE_R::new((self.bits & 0x0f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - reload complete sign for 4 regions bit0: region 0 bit1: region1 bit2: region2 bit3: region3"]
            #[inline(always)]
            #[must_use]
            pub fn complete(&mut self) -> COMPLETE_W<LOAD_COMP_SPEC> {
                COMPLETE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "LOAD complete\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load_comp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load_comp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LOAD_COMP_SPEC;
        impl crate::RegisterSpec for LOAD_COMP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`load_comp::R`](R) reader structure"]
        impl crate::Readable for LOAD_COMP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`load_comp::W`](W) writer structure"]
        impl crate::Writable for LOAD_COMP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LOAD_COMP to value 0x07"]
        impl crate::Resettable for LOAD_COMP_SPEC {
            const RESET_VALUE: u32 = 0x07;
        }
    }
    #[doc = "REGION (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`region::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`region::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@region`]
module"]
    pub type REGION = crate::Reg<region::REGION_SPEC>;
    #[doc = "no description available"]
    pub mod region {
        #[doc = "Register `REGION[%s]` reader"]
        pub type R = crate::R<REGION_SPEC>;
        #[doc = "Register `REGION[%s]` writer"]
        pub type W = crate::W<REGION_SPEC>;
        #[doc = "Field `START` reader - start address of load region, fuse word at start address will be reloaded region0: fixed at 0 region1: fixed at 8 region2: fixed at 16, region3: usrer configurable"]
        pub type START_R = crate::FieldReader;
        #[doc = "Field `START` writer - start address of load region, fuse word at start address will be reloaded region0: fixed at 0 region1: fixed at 8 region2: fixed at 16, region3: usrer configurable"]
        pub type START_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `STOP` reader - stop address of load region, fuse word at end address will NOT be reloaded region0: fixed at 8 region1: fixed at 16 region2: fixed at 0, region3: usrer configurable"]
        pub type STOP_R = crate::FieldReader;
        #[doc = "Field `STOP` writer - stop address of load region, fuse word at end address will NOT be reloaded region0: fixed at 8 region1: fixed at 16 region2: fixed at 0, region3: usrer configurable"]
        pub type STOP_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bits 0:6 - start address of load region, fuse word at start address will be reloaded region0: fixed at 0 region1: fixed at 8 region2: fixed at 16, region3: usrer configurable"]
            #[inline(always)]
            pub fn start(&self) -> START_R {
                START_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bits 8:14 - stop address of load region, fuse word at end address will NOT be reloaded region0: fixed at 8 region1: fixed at 16 region2: fixed at 0, region3: usrer configurable"]
            #[inline(always)]
            pub fn stop(&self) -> STOP_R {
                STOP_R::new(((self.bits >> 8) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - start address of load region, fuse word at start address will be reloaded region0: fixed at 0 region1: fixed at 8 region2: fixed at 16, region3: usrer configurable"]
            #[inline(always)]
            #[must_use]
            pub fn start(&mut self) -> START_W<REGION_SPEC> {
                START_W::new(self, 0)
            }
            #[doc = "Bits 8:14 - stop address of load region, fuse word at end address will NOT be reloaded region0: fixed at 8 region1: fixed at 16 region2: fixed at 0, region3: usrer configurable"]
            #[inline(always)]
            #[must_use]
            pub fn stop(&mut self) -> STOP_W<REGION_SPEC> {
                STOP_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`region::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`region::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct REGION_SPEC;
        impl crate::RegisterSpec for REGION_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`region::R`](R) reader structure"]
        impl crate::Readable for REGION_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`region::W`](W) writer structure"]
        impl crate::Writable for REGION_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets REGION[%s]
to value 0x0800"]
        impl crate::Resettable for REGION_SPEC {
            const RESET_VALUE: u32 = 0x0800;
        }
    }
    #[doc = "INT_FLAG (rw) register accessor: interrupt flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_flag::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_flag::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_flag`]
module"]
    pub type INT_FLAG = crate::Reg<int_flag::INT_FLAG_SPEC>;
    #[doc = "interrupt flag"]
    pub mod int_flag {
        #[doc = "Register `INT_FLAG` reader"]
        pub type R = crate::R<INT_FLAG_SPEC>;
        #[doc = "Register `INT_FLAG` writer"]
        pub type W = crate::W<INT_FLAG_SPEC>;
        #[doc = "Field `LOAD` reader - fuse load flag, write 1 to clear 0: fuse is not loaded or loading 1: fuse loaded"]
        pub type LOAD_R = crate::BitReader;
        #[doc = "Field `LOAD` writer - fuse load flag, write 1 to clear 0: fuse is not loaded or loading 1: fuse loaded"]
        pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `READ` reader - fuse read flag, write 1 to clear 0: fuse is not read or reading 1: fuse value is put in DATA register"]
        pub type READ_R = crate::BitReader;
        #[doc = "Field `READ` writer - fuse read flag, write 1 to clear 0: fuse is not read or reading 1: fuse value is put in DATA register"]
        pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WRITE` reader - fuse write flag, write 1 to clear 0: fuse is not written or writing 1: value in DATA register is programmed into fuse"]
        pub type WRITE_R = crate::BitReader;
        #[doc = "Field `WRITE` writer - fuse write flag, write 1 to clear 0: fuse is not written or writing 1: value in DATA register is programmed into fuse"]
        pub type WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - fuse load flag, write 1 to clear 0: fuse is not loaded or loading 1: fuse loaded"]
            #[inline(always)]
            pub fn load(&self) -> LOAD_R {
                LOAD_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - fuse read flag, write 1 to clear 0: fuse is not read or reading 1: fuse value is put in DATA register"]
            #[inline(always)]
            pub fn read(&self) -> READ_R {
                READ_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - fuse write flag, write 1 to clear 0: fuse is not written or writing 1: value in DATA register is programmed into fuse"]
            #[inline(always)]
            pub fn write(&self) -> WRITE_R {
                WRITE_R::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - fuse load flag, write 1 to clear 0: fuse is not loaded or loading 1: fuse loaded"]
            #[inline(always)]
            #[must_use]
            pub fn load(&mut self) -> LOAD_W<INT_FLAG_SPEC> {
                LOAD_W::new(self, 0)
            }
            #[doc = "Bit 1 - fuse read flag, write 1 to clear 0: fuse is not read or reading 1: fuse value is put in DATA register"]
            #[inline(always)]
            #[must_use]
            pub fn read(&mut self) -> READ_W<INT_FLAG_SPEC> {
                READ_W::new(self, 1)
            }
            #[doc = "Bit 2 - fuse write flag, write 1 to clear 0: fuse is not written or writing 1: value in DATA register is programmed into fuse"]
            #[inline(always)]
            #[must_use]
            pub fn write(&mut self) -> WRITE_W<INT_FLAG_SPEC> {
                WRITE_W::new(self, 2)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "interrupt flag\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_flag::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_flag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_FLAG_SPEC;
        impl crate::RegisterSpec for INT_FLAG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_flag::R`](R) reader structure"]
        impl crate::Readable for INT_FLAG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_flag::W`](W) writer structure"]
        impl crate::Writable for INT_FLAG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INT_FLAG to value 0"]
        impl crate::Resettable for INT_FLAG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "INT_EN (rw) register accessor: interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_en`]
module"]
    pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
    #[doc = "interrupt enable"]
    pub mod int_en {
        #[doc = "Register `INT_EN` reader"]
        pub type R = crate::R<INT_EN_SPEC>;
        #[doc = "Register `INT_EN` writer"]
        pub type W = crate::W<INT_EN_SPEC>;
        #[doc = "Field `LOAD` reader - fuse load interrupt enable 0: fuse load interrupt is not enable 1: fuse load interrupt is enable"]
        pub type LOAD_R = crate::BitReader;
        #[doc = "Field `LOAD` writer - fuse load interrupt enable 0: fuse load interrupt is not enable 1: fuse load interrupt is enable"]
        pub type LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `READ` reader - fuse read interrupt enable 0: fuse read interrupt is not enable 1: fuse read interrupt is enable"]
        pub type READ_R = crate::BitReader;
        #[doc = "Field `READ` writer - fuse read interrupt enable 0: fuse read interrupt is not enable 1: fuse read interrupt is enable"]
        pub type READ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `WRITE` reader - fuse write interrupt enable 0: fuse write interrupt is not enable 1: fuse write interrupt is enable"]
        pub type WRITE_R = crate::BitReader;
        #[doc = "Field `WRITE` writer - fuse write interrupt enable 0: fuse write interrupt is not enable 1: fuse write interrupt is enable"]
        pub type WRITE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - fuse load interrupt enable 0: fuse load interrupt is not enable 1: fuse load interrupt is enable"]
            #[inline(always)]
            pub fn load(&self) -> LOAD_R {
                LOAD_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - fuse read interrupt enable 0: fuse read interrupt is not enable 1: fuse read interrupt is enable"]
            #[inline(always)]
            pub fn read(&self) -> READ_R {
                READ_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - fuse write interrupt enable 0: fuse write interrupt is not enable 1: fuse write interrupt is enable"]
            #[inline(always)]
            pub fn write(&self) -> WRITE_R {
                WRITE_R::new(((self.bits >> 2) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - fuse load interrupt enable 0: fuse load interrupt is not enable 1: fuse load interrupt is enable"]
            #[inline(always)]
            #[must_use]
            pub fn load(&mut self) -> LOAD_W<INT_EN_SPEC> {
                LOAD_W::new(self, 0)
            }
            #[doc = "Bit 1 - fuse read interrupt enable 0: fuse read interrupt is not enable 1: fuse read interrupt is enable"]
            #[inline(always)]
            #[must_use]
            pub fn read(&mut self) -> READ_W<INT_EN_SPEC> {
                READ_W::new(self, 1)
            }
            #[doc = "Bit 2 - fuse write interrupt enable 0: fuse write interrupt is not enable 1: fuse write interrupt is enable"]
            #[inline(always)]
            #[must_use]
            pub fn write(&mut self) -> WRITE_W<INT_EN_SPEC> {
                WRITE_W::new(self, 2)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "interrupt enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_EN_SPEC;
        impl crate::RegisterSpec for INT_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_en::R`](R) reader structure"]
        impl crate::Readable for INT_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_en::W`](W) writer structure"]
        impl crate::Writable for INT_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets INT_EN to value 0"]
        impl crate::Resettable for INT_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "KEYM"]
pub struct KEYM {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for KEYM {}
impl KEYM {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const keym::RegisterBlock = 0xf305_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const keym::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for KEYM {
    type Target = keym::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for KEYM {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("KEYM").finish()
    }
}
#[doc = "KEYM"]
pub mod keym {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        softmkey: [SOFTMKEY; 8],
        softpkey: [SOFTPKEY; 8],
        sec_key_ctl: SEC_KEY_CTL,
        nsc_key_ctl: NSC_KEY_CTL,
        rng: RNG,
        read_control: READ_CONTROL,
    }
    impl RegisterBlock {
        #[doc = "0x00..0x20 - no description available"]
        #[inline(always)]
        pub const fn softmkey(&self, n: usize) -> &SOFTMKEY {
            &self.softmkey[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x20 - no description available"]
        #[inline(always)]
        pub fn softmkey_iter(&self) -> impl Iterator<Item = &SOFTMKEY> {
            self.softmkey.iter()
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk0(&self) -> &SOFTMKEY {
            self.softmkey(0)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk1(&self) -> &SOFTMKEY {
            self.softmkey(1)
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk2(&self) -> &SOFTMKEY {
            self.softmkey(2)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk3(&self) -> &SOFTMKEY {
            self.softmkey(3)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk4(&self) -> &SOFTMKEY {
            self.softmkey(4)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk5(&self) -> &SOFTMKEY {
            self.softmkey(5)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk6(&self) -> &SOFTMKEY {
            self.softmkey(6)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn softmkeysfk7(&self) -> &SOFTMKEY {
            self.softmkey(7)
        }
        #[doc = "0x20..0x40 - no description available"]
        #[inline(always)]
        pub const fn softpkey(&self, n: usize) -> &SOFTPKEY {
            &self.softpkey[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x20..0x40 - no description available"]
        #[inline(always)]
        pub fn softpkey_iter(&self) -> impl Iterator<Item = &SOFTPKEY> {
            self.softpkey.iter()
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk0(&self) -> &SOFTPKEY {
            self.softpkey(0)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk1(&self) -> &SOFTPKEY {
            self.softpkey(1)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk2(&self) -> &SOFTPKEY {
            self.softpkey(2)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk3(&self) -> &SOFTPKEY {
            self.softpkey(3)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk4(&self) -> &SOFTPKEY {
            self.softpkey(4)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk5(&self) -> &SOFTPKEY {
            self.softpkey(5)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk6(&self) -> &SOFTPKEY {
            self.softpkey(6)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn softpkeyspk7(&self) -> &SOFTPKEY {
            self.softpkey(7)
        }
        #[doc = "0x40 - secure key generation"]
        #[inline(always)]
        pub const fn sec_key_ctl(&self) -> &SEC_KEY_CTL {
            &self.sec_key_ctl
        }
        #[doc = "0x44 - non-secure key generation"]
        #[inline(always)]
        pub const fn nsc_key_ctl(&self) -> &NSC_KEY_CTL {
            &self.nsc_key_ctl
        }
        #[doc = "0x48 - Random number interface behavior"]
        #[inline(always)]
        pub const fn rng(&self) -> &RNG {
            &self.rng
        }
        #[doc = "0x4c - key read out control"]
        #[inline(always)]
        pub const fn read_control(&self) -> &READ_CONTROL {
            &self.read_control
        }
    }
    #[doc = "SOFTMKEY (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`softmkey::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`softmkey::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@softmkey`]
module"]
    pub type SOFTMKEY = crate::Reg<softmkey::SOFTMKEY_SPEC>;
    #[doc = "no description available"]
    pub mod softmkey {
        #[doc = "Register `SOFTMKEY[%s]` reader"]
        pub type R = crate::R<SOFTMKEY_SPEC>;
        #[doc = "Register `SOFTMKEY[%s]` writer"]
        pub type W = crate::W<SOFTMKEY_SPEC>;
        #[doc = "Field `KEY` reader - software symmetric key key will be scambled to 4 variants for software to use, and replicable on same chip. scramble keys are chip different, and not replicable on different chip must be write sequencely from 0 - 7, otherwise key value will be treated as all 0"]
        pub type KEY_R = crate::FieldReader<u32>;
        #[doc = "Field `KEY` writer - software symmetric key key will be scambled to 4 variants for software to use, and replicable on same chip. scramble keys are chip different, and not replicable on different chip must be write sequencely from 0 - 7, otherwise key value will be treated as all 0"]
        pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - software symmetric key key will be scambled to 4 variants for software to use, and replicable on same chip. scramble keys are chip different, and not replicable on different chip must be write sequencely from 0 - 7, otherwise key value will be treated as all 0"]
            #[inline(always)]
            pub fn key(&self) -> KEY_R {
                KEY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - software symmetric key key will be scambled to 4 variants for software to use, and replicable on same chip. scramble keys are chip different, and not replicable on different chip must be write sequencely from 0 - 7, otherwise key value will be treated as all 0"]
            #[inline(always)]
            #[must_use]
            pub fn key(&mut self) -> KEY_W<SOFTMKEY_SPEC> {
                KEY_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`softmkey::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`softmkey::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SOFTMKEY_SPEC;
        impl crate::RegisterSpec for SOFTMKEY_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`softmkey::R`](R) reader structure"]
        impl crate::Readable for SOFTMKEY_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`softmkey::W`](W) writer structure"]
        impl crate::Writable for SOFTMKEY_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SOFTMKEY[%s]
to value 0"]
        impl crate::Resettable for SOFTMKEY_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SOFTPKEY (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`softpkey::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`softpkey::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@softpkey`]
module"]
    pub type SOFTPKEY = crate::Reg<softpkey::SOFTPKEY_SPEC>;
    #[doc = "no description available"]
    pub mod softpkey {
        #[doc = "Register `SOFTPKEY[%s]` reader"]
        pub type R = crate::R<SOFTPKEY_SPEC>;
        #[doc = "Register `SOFTPKEY[%s]` writer"]
        pub type W = crate::W<SOFTPKEY_SPEC>;
        #[doc = "Field `KEY` reader - software asymmetric key key is derived from scrambles of fuse private key, software input key, SRK, and system security status. This key os read once, sencondary read will read out 0"]
        pub type KEY_R = crate::FieldReader<u32>;
        #[doc = "Field `KEY` writer - software asymmetric key key is derived from scrambles of fuse private key, software input key, SRK, and system security status. This key os read once, sencondary read will read out 0"]
        pub type KEY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - software asymmetric key key is derived from scrambles of fuse private key, software input key, SRK, and system security status. This key os read once, sencondary read will read out 0"]
            #[inline(always)]
            pub fn key(&self) -> KEY_R {
                KEY_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - software asymmetric key key is derived from scrambles of fuse private key, software input key, SRK, and system security status. This key os read once, sencondary read will read out 0"]
            #[inline(always)]
            #[must_use]
            pub fn key(&mut self) -> KEY_W<SOFTPKEY_SPEC> {
                KEY_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`softpkey::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`softpkey::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SOFTPKEY_SPEC;
        impl crate::RegisterSpec for SOFTPKEY_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`softpkey::R`](R) reader structure"]
        impl crate::Readable for SOFTPKEY_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`softpkey::W`](W) writer structure"]
        impl crate::Writable for SOFTPKEY_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SOFTPKEY[%s]
to value 0"]
        impl crate::Resettable for SOFTPKEY_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SEC_KEY_CTL (rw) register accessor: secure key generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sec_key_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sec_key_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_key_ctl`]
module"]
    pub type SEC_KEY_CTL = crate::Reg<sec_key_ctl::SEC_KEY_CTL_SPEC>;
    #[doc = "secure key generation"]
    pub mod sec_key_ctl {
        #[doc = "Register `SEC_KEY_CTL` reader"]
        pub type R = crate::R<SEC_KEY_CTL_SPEC>;
        #[doc = "Register `SEC_KEY_CTL` writer"]
        pub type W = crate::W<SEC_KEY_CTL_SPEC>;
        #[doc = "Field `KEY_SEL` reader - secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
        pub type KEY_SEL_R = crate::FieldReader;
        #[doc = "Field `KEY_SEL` writer - secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
        pub type KEY_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `FMK_SEL` reader - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use alnertave scramble of fuse symmetric key"]
        pub type FMK_SEL_R = crate::BitReader;
        #[doc = "Field `FMK_SEL` writer - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use alnertave scramble of fuse symmetric key"]
        pub type FMK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZMK_SEL` reader - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
        pub type ZMK_SEL_R = crate::BitReader;
        #[doc = "Field `ZMK_SEL` writer - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
        pub type ZMK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SMK_SEL` reader - software symmetric key selection 0: use origin value in software symmetric key 1: use scramble version of software symmetric key"]
        pub type SMK_SEL_R = crate::BitReader;
        #[doc = "Field `SMK_SEL` writer - software symmetric key selection 0: use origin value in software symmetric key 1: use scramble version of software symmetric key"]
        pub type SMK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SK_VAL` reader - session key valid 0: session key is all 0's and not usable 1: session key is valid"]
        pub type SK_VAL_R = crate::BitReader;
        #[doc = "Field `LOCK_SEC_CTL` reader - block secure state key setting being changed"]
        pub type LOCK_SEC_CTL_R = crate::BitReader;
        #[doc = "Field `LOCK_SEC_CTL` writer - block secure state key setting being changed"]
        pub type LOCK_SEC_CTL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:2 - secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
            #[inline(always)]
            pub fn key_sel(&self) -> KEY_SEL_R {
                KEY_SEL_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 4 - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use alnertave scramble of fuse symmetric key"]
            #[inline(always)]
            pub fn fmk_sel(&self) -> FMK_SEL_R {
                FMK_SEL_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 8 - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
            #[inline(always)]
            pub fn zmk_sel(&self) -> ZMK_SEL_R {
                ZMK_SEL_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 12 - software symmetric key selection 0: use origin value in software symmetric key 1: use scramble version of software symmetric key"]
            #[inline(always)]
            pub fn smk_sel(&self) -> SMK_SEL_R {
                SMK_SEL_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 16 - session key valid 0: session key is all 0's and not usable 1: session key is valid"]
            #[inline(always)]
            pub fn sk_val(&self) -> SK_VAL_R {
                SK_VAL_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 31 - block secure state key setting being changed"]
            #[inline(always)]
            pub fn lock_sec_ctl(&self) -> LOCK_SEC_CTL_R {
                LOCK_SEC_CTL_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
            #[inline(always)]
            #[must_use]
            pub fn key_sel(&mut self) -> KEY_SEL_W<SEC_KEY_CTL_SPEC> {
                KEY_SEL_W::new(self, 0)
            }
            #[doc = "Bit 4 - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use alnertave scramble of fuse symmetric key"]
            #[inline(always)]
            #[must_use]
            pub fn fmk_sel(&mut self) -> FMK_SEL_W<SEC_KEY_CTL_SPEC> {
                FMK_SEL_W::new(self, 4)
            }
            #[doc = "Bit 8 - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
            #[inline(always)]
            #[must_use]
            pub fn zmk_sel(&mut self) -> ZMK_SEL_W<SEC_KEY_CTL_SPEC> {
                ZMK_SEL_W::new(self, 8)
            }
            #[doc = "Bit 12 - software symmetric key selection 0: use origin value in software symmetric key 1: use scramble version of software symmetric key"]
            #[inline(always)]
            #[must_use]
            pub fn smk_sel(&mut self) -> SMK_SEL_W<SEC_KEY_CTL_SPEC> {
                SMK_SEL_W::new(self, 12)
            }
            #[doc = "Bit 31 - block secure state key setting being changed"]
            #[inline(always)]
            #[must_use]
            pub fn lock_sec_ctl(&mut self) -> LOCK_SEC_CTL_W<SEC_KEY_CTL_SPEC> {
                LOCK_SEC_CTL_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "secure key generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sec_key_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sec_key_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SEC_KEY_CTL_SPEC;
        impl crate::RegisterSpec for SEC_KEY_CTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sec_key_ctl::R`](R) reader structure"]
        impl crate::Readable for SEC_KEY_CTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sec_key_ctl::W`](W) writer structure"]
        impl crate::Writable for SEC_KEY_CTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SEC_KEY_CTL to value 0"]
        impl crate::Resettable for SEC_KEY_CTL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "NSC_KEY_CTL (rw) register accessor: non-secure key generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nsc_key_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nsc_key_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nsc_key_ctl`]
module"]
    pub type NSC_KEY_CTL = crate::Reg<nsc_key_ctl::NSC_KEY_CTL_SPEC>;
    #[doc = "non-secure key generation"]
    pub mod nsc_key_ctl {
        #[doc = "Register `NSC_KEY_CTL` reader"]
        pub type R = crate::R<NSC_KEY_CTL_SPEC>;
        #[doc = "Register `NSC_KEY_CTL` writer"]
        pub type W = crate::W<NSC_KEY_CTL_SPEC>;
        #[doc = "Field `KEY_SEL` reader - non-secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
        pub type KEY_SEL_R = crate::FieldReader;
        #[doc = "Field `KEY_SEL` writer - non-secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
        pub type KEY_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `FMK_SEL` reader - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use origin value in fuse symmetric key"]
        pub type FMK_SEL_R = crate::BitReader;
        #[doc = "Field `FMK_SEL` writer - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use origin value in fuse symmetric key"]
        pub type FMK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ZMK_SEL` reader - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
        pub type ZMK_SEL_R = crate::BitReader;
        #[doc = "Field `ZMK_SEL` writer - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
        pub type ZMK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SMK_SEL` reader - software symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
        pub type SMK_SEL_R = crate::BitReader;
        #[doc = "Field `SMK_SEL` writer - software symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
        pub type SMK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SK_VAL` reader - session key valid 0: session key is all 0's and not usable 1: session key is valid"]
        pub type SK_VAL_R = crate::BitReader;
        #[doc = "Field `LOCK_NSC_CTL` reader - block non-secure state key setting being changed"]
        pub type LOCK_NSC_CTL_R = crate::BitReader;
        #[doc = "Field `LOCK_NSC_CTL` writer - block non-secure state key setting being changed"]
        pub type LOCK_NSC_CTL_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:2 - non-secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
            #[inline(always)]
            pub fn key_sel(&self) -> KEY_SEL_R {
                KEY_SEL_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 4 - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use origin value in fuse symmetric key"]
            #[inline(always)]
            pub fn fmk_sel(&self) -> FMK_SEL_R {
                FMK_SEL_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 8 - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
            #[inline(always)]
            pub fn zmk_sel(&self) -> ZMK_SEL_R {
                ZMK_SEL_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 12 - software symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
            #[inline(always)]
            pub fn smk_sel(&self) -> SMK_SEL_R {
                SMK_SEL_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 16 - session key valid 0: session key is all 0's and not usable 1: session key is valid"]
            #[inline(always)]
            pub fn sk_val(&self) -> SK_VAL_R {
                SK_VAL_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 31 - block non-secure state key setting being changed"]
            #[inline(always)]
            pub fn lock_nsc_ctl(&self) -> LOCK_NSC_CTL_R {
                LOCK_NSC_CTL_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - non-secure symmtric key synthesize setting, key is a XOR of followings bit0: fuse mk, 0: not selected, 1:selected bit1: zmk from batt, 0: not selected, 1:selected bit2: software key 0: not selected, 1:selected"]
            #[inline(always)]
            #[must_use]
            pub fn key_sel(&mut self) -> KEY_SEL_W<NSC_KEY_CTL_SPEC> {
                KEY_SEL_W::new(self, 0)
            }
            #[doc = "Bit 4 - fuse symmetric key selection 0: use scramble version of fuse symmetric key 1: use origin value in fuse symmetric key"]
            #[inline(always)]
            #[must_use]
            pub fn fmk_sel(&mut self) -> FMK_SEL_W<NSC_KEY_CTL_SPEC> {
                FMK_SEL_W::new(self, 4)
            }
            #[doc = "Bit 8 - batt symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
            #[inline(always)]
            #[must_use]
            pub fn zmk_sel(&mut self) -> ZMK_SEL_W<NSC_KEY_CTL_SPEC> {
                ZMK_SEL_W::new(self, 8)
            }
            #[doc = "Bit 12 - software symmetric key selection 0: use scramble version of software symmetric key 1: use origin value in software symmetric key"]
            #[inline(always)]
            #[must_use]
            pub fn smk_sel(&mut self) -> SMK_SEL_W<NSC_KEY_CTL_SPEC> {
                SMK_SEL_W::new(self, 12)
            }
            #[doc = "Bit 31 - block non-secure state key setting being changed"]
            #[inline(always)]
            #[must_use]
            pub fn lock_nsc_ctl(&mut self) -> LOCK_NSC_CTL_W<NSC_KEY_CTL_SPEC> {
                LOCK_NSC_CTL_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "non-secure key generation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nsc_key_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nsc_key_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct NSC_KEY_CTL_SPEC;
        impl crate::RegisterSpec for NSC_KEY_CTL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`nsc_key_ctl::R`](R) reader structure"]
        impl crate::Readable for NSC_KEY_CTL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`nsc_key_ctl::W`](W) writer structure"]
        impl crate::Writable for NSC_KEY_CTL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets NSC_KEY_CTL to value 0"]
        impl crate::Resettable for NSC_KEY_CTL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RNG (rw) register accessor: Random number interface behavior\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rng`]
module"]
    pub type RNG = crate::Reg<rng::RNG_SPEC>;
    #[doc = "Random number interface behavior"]
    pub mod rng {
        #[doc = "Register `RNG` reader"]
        pub type R = crate::R<RNG_SPEC>;
        #[doc = "Register `RNG` writer"]
        pub type W = crate::W<RNG_SPEC>;
        #[doc = "Field `RNG_XOR` reader - control how SFK is accepted from random number generator 0: SFK value replaced by random number input 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG"]
        pub type RNG_XOR_R = crate::BitReader;
        #[doc = "Field `RNG_XOR` writer - control how SFK is accepted from random number generator 0: SFK value replaced by random number input 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG"]
        pub type RNG_XOR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BLOCK_RNG_XOR` reader - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset 0: RNG_XOR can be changed by software 1: RNG_XOR ignore software change from software"]
        pub type BLOCK_RNG_XOR_R = crate::BitReader;
        #[doc = "Field `BLOCK_RNG_XOR` writer - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset 0: RNG_XOR can be changed by software 1: RNG_XOR ignore software change from software"]
        pub type BLOCK_RNG_XOR_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - control how SFK is accepted from random number generator 0: SFK value replaced by random number input 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG"]
            #[inline(always)]
            pub fn rng_xor(&self) -> RNG_XOR_R {
                RNG_XOR_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 16 - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset 0: RNG_XOR can be changed by software 1: RNG_XOR ignore software change from software"]
            #[inline(always)]
            pub fn block_rng_xor(&self) -> BLOCK_RNG_XOR_R {
                BLOCK_RNG_XOR_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - control how SFK is accepted from random number generator 0: SFK value replaced by random number input 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG"]
            #[inline(always)]
            #[must_use]
            pub fn rng_xor(&mut self) -> RNG_XOR_W<RNG_SPEC> {
                RNG_XOR_W::new(self, 0)
            }
            #[doc = "Bit 16 - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset 0: RNG_XOR can be changed by software 1: RNG_XOR ignore software change from software"]
            #[inline(always)]
            #[must_use]
            pub fn block_rng_xor(&mut self) -> BLOCK_RNG_XOR_W<RNG_SPEC> {
                BLOCK_RNG_XOR_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Random number interface behavior\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rng::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rng::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RNG_SPEC;
        impl crate::RegisterSpec for RNG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rng::R`](R) reader structure"]
        impl crate::Readable for RNG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rng::W`](W) writer structure"]
        impl crate::Writable for RNG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RNG to value 0"]
        impl crate::Resettable for RNG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "READ_CONTROL (rw) register accessor: key read out control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read_control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`read_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@read_control`]
module"]
    pub type READ_CONTROL = crate::Reg<read_control::READ_CONTROL_SPEC>;
    #[doc = "key read out control"]
    pub mod read_control {
        #[doc = "Register `READ_CONTROL` reader"]
        pub type R = crate::R<READ_CONTROL_SPEC>;
        #[doc = "Register `READ_CONTROL` writer"]
        pub type W = crate::W<READ_CONTROL_SPEC>;
        #[doc = "Field `BLOCK_SMK_READ` reader - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
        pub type BLOCK_SMK_READ_R = crate::BitReader;
        #[doc = "Field `BLOCK_SMK_READ` writer - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
        pub type BLOCK_SMK_READ_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BLOCK_PK_READ` reader - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
        pub type BLOCK_PK_READ_R = crate::BitReader;
        #[doc = "Field `BLOCK_PK_READ` writer - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
        pub type BLOCK_PK_READ_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
            #[inline(always)]
            pub fn block_smk_read(&self) -> BLOCK_SMK_READ_R {
                BLOCK_SMK_READ_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 16 - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
            #[inline(always)]
            pub fn block_pk_read(&self) -> BLOCK_PK_READ_R {
                BLOCK_PK_READ_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
            #[inline(always)]
            #[must_use]
            pub fn block_smk_read(&mut self) -> BLOCK_SMK_READ_W<READ_CONTROL_SPEC> {
                BLOCK_SMK_READ_W::new(self, 0)
            }
            #[doc = "Bit 16 - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset 0: key can be read out 1: key cannot be read out"]
            #[inline(always)]
            #[must_use]
            pub fn block_pk_read(&mut self) -> BLOCK_PK_READ_W<READ_CONTROL_SPEC> {
                BLOCK_PK_READ_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "key read out control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`read_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`read_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct READ_CONTROL_SPEC;
        impl crate::RegisterSpec for READ_CONTROL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`read_control::R`](R) reader structure"]
        impl crate::Readable for READ_CONTROL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`read_control::W`](W) writer structure"]
        impl crate::Writable for READ_CONTROL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets READ_CONTROL to value 0"]
        impl crate::Resettable for READ_CONTROL_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "ADC0"]
pub struct ADC0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC0 {}
impl ADC0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const adc0::RegisterBlock = 0xf308_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const adc0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for ADC0 {
    type Target = adc0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for ADC0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC0").finish()
    }
}
#[doc = "ADC0"]
pub mod adc0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        config: [CONFIG; 12],
        trg_dma_addr: TRG_DMA_ADDR,
        trg_sw_sta: TRG_SW_STA,
        _reserved3: [u8; 0x03c8],
        bus_result: [BUS_RESULT; 16],
        _reserved4: [u8; 0xc0],
        buf_cfg0: BUF_CFG0,
        _reserved5: [u8; 0x02fc],
        seq_cfg0: SEQ_CFG0,
        seq_dma_addr: SEQ_DMA_ADDR,
        seq_wr_addr: SEQ_WR_ADDR,
        seq_dma_cfg: SEQ_DMA_CFG,
        seq_que: [SEQ_QUE; 16],
        seq_high_cfg: SEQ_HIGH_CFG,
        _reserved11: [u8; 0x03ac],
        prd_cfg_chn: (),
        _reserved12: [u8; 0x0400],
        sample_cfg: [SAMPLE_CFG; 16],
        _reserved13: [u8; 0xc4],
        conv_cfg1: CONV_CFG1,
        adc_cfg0: ADC_CFG0,
        _reserved15: [u8; 0x04],
        int_sts: INT_STS,
        int_en: INT_EN,
        _reserved17: [u8; 0xe8],
        ana_ctrl0: ANA_CTRL0,
        _reserved18: [u8; 0x0c],
        ana_status: ANA_STATUS,
        _reserved19: [u8; 0x01ec],
        adc16_params: [ADC16_PARAMS; 34],
        adc16_config0: ADC16_CONFIG0,
        _reserved21: [u8; 0x18],
        adc16_config1: ADC16_CONFIG1,
    }
    impl RegisterBlock {
        #[doc = "0x00..0x30 - no description available"]
        #[inline(always)]
        pub const fn config(&self, n: usize) -> &CONFIG {
            &self.config[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x30 - no description available"]
        #[inline(always)]
        pub fn config_iter(&self) -> impl Iterator<Item = &CONFIG> {
            self.config.iter()
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn configtrg0a(&self) -> &CONFIG {
            self.config(0)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn configtrg0b(&self) -> &CONFIG {
            self.config(1)
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn configtrg0c(&self) -> &CONFIG {
            self.config(2)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn configtrg1a(&self) -> &CONFIG {
            self.config(3)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn configtrg1b(&self) -> &CONFIG {
            self.config(4)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn configtrg1c(&self) -> &CONFIG {
            self.config(5)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn configtrg2a(&self) -> &CONFIG {
            self.config(6)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn configtrg2b(&self) -> &CONFIG {
            self.config(7)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn configtrg2c(&self) -> &CONFIG {
            self.config(8)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn configtrg3a(&self) -> &CONFIG {
            self.config(9)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn configtrg3b(&self) -> &CONFIG {
            self.config(10)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn configtrg3c(&self) -> &CONFIG {
            self.config(11)
        }
        #[doc = "0x30 - No description avaiable"]
        #[inline(always)]
        pub const fn trg_dma_addr(&self) -> &TRG_DMA_ADDR {
            &self.trg_dma_addr
        }
        #[doc = "0x34 - No description avaiable"]
        #[inline(always)]
        pub const fn trg_sw_sta(&self) -> &TRG_SW_STA {
            &self.trg_sw_sta
        }
        #[doc = "0x400..0x440 - no description available"]
        #[inline(always)]
        pub const fn bus_result(&self, n: usize) -> &BUS_RESULT {
            &self.bus_result[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x400..0x440 - no description available"]
        #[inline(always)]
        pub fn bus_result_iter(&self) -> impl Iterator<Item = &BUS_RESULT> {
            self.bus_result.iter()
        }
        #[doc = "0x400 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn0(&self) -> &BUS_RESULT {
            self.bus_result(0)
        }
        #[doc = "0x404 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn1(&self) -> &BUS_RESULT {
            self.bus_result(1)
        }
        #[doc = "0x408 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn2(&self) -> &BUS_RESULT {
            self.bus_result(2)
        }
        #[doc = "0x40c - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn3(&self) -> &BUS_RESULT {
            self.bus_result(3)
        }
        #[doc = "0x410 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn4(&self) -> &BUS_RESULT {
            self.bus_result(4)
        }
        #[doc = "0x414 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn5(&self) -> &BUS_RESULT {
            self.bus_result(5)
        }
        #[doc = "0x418 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn6(&self) -> &BUS_RESULT {
            self.bus_result(6)
        }
        #[doc = "0x41c - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn7(&self) -> &BUS_RESULT {
            self.bus_result(7)
        }
        #[doc = "0x420 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn8(&self) -> &BUS_RESULT {
            self.bus_result(8)
        }
        #[doc = "0x424 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn9(&self) -> &BUS_RESULT {
            self.bus_result(9)
        }
        #[doc = "0x428 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn10(&self) -> &BUS_RESULT {
            self.bus_result(10)
        }
        #[doc = "0x42c - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn11(&self) -> &BUS_RESULT {
            self.bus_result(11)
        }
        #[doc = "0x430 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn12(&self) -> &BUS_RESULT {
            self.bus_result(12)
        }
        #[doc = "0x434 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn13(&self) -> &BUS_RESULT {
            self.bus_result(13)
        }
        #[doc = "0x438 - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn14(&self) -> &BUS_RESULT {
            self.bus_result(14)
        }
        #[doc = "0x43c - no description available"]
        #[inline(always)]
        pub const fn bus_resultchn15(&self) -> &BUS_RESULT {
            self.bus_result(15)
        }
        #[doc = "0x500 - No description avaiable"]
        #[inline(always)]
        pub const fn buf_cfg0(&self) -> &BUF_CFG0 {
            &self.buf_cfg0
        }
        #[doc = "0x800 - No description avaiable"]
        #[inline(always)]
        pub const fn seq_cfg0(&self) -> &SEQ_CFG0 {
            &self.seq_cfg0
        }
        #[doc = "0x804 - No description avaiable"]
        #[inline(always)]
        pub const fn seq_dma_addr(&self) -> &SEQ_DMA_ADDR {
            &self.seq_dma_addr
        }
        #[doc = "0x808 - No description avaiable"]
        #[inline(always)]
        pub const fn seq_wr_addr(&self) -> &SEQ_WR_ADDR {
            &self.seq_wr_addr
        }
        #[doc = "0x80c - No description avaiable"]
        #[inline(always)]
        pub const fn seq_dma_cfg(&self) -> &SEQ_DMA_CFG {
            &self.seq_dma_cfg
        }
        #[doc = "0x810..0x850 - no description available"]
        #[inline(always)]
        pub const fn seq_que(&self, n: usize) -> &SEQ_QUE {
            &self.seq_que[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x810..0x850 - no description available"]
        #[inline(always)]
        pub fn seq_que_iter(&self) -> impl Iterator<Item = &SEQ_QUE> {
            self.seq_que.iter()
        }
        #[doc = "0x810 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg0(&self) -> &SEQ_QUE {
            self.seq_que(0)
        }
        #[doc = "0x814 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg1(&self) -> &SEQ_QUE {
            self.seq_que(1)
        }
        #[doc = "0x818 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg2(&self) -> &SEQ_QUE {
            self.seq_que(2)
        }
        #[doc = "0x81c - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg3(&self) -> &SEQ_QUE {
            self.seq_que(3)
        }
        #[doc = "0x820 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg4(&self) -> &SEQ_QUE {
            self.seq_que(4)
        }
        #[doc = "0x824 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg5(&self) -> &SEQ_QUE {
            self.seq_que(5)
        }
        #[doc = "0x828 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg6(&self) -> &SEQ_QUE {
            self.seq_que(6)
        }
        #[doc = "0x82c - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg7(&self) -> &SEQ_QUE {
            self.seq_que(7)
        }
        #[doc = "0x830 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg8(&self) -> &SEQ_QUE {
            self.seq_que(8)
        }
        #[doc = "0x834 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg9(&self) -> &SEQ_QUE {
            self.seq_que(9)
        }
        #[doc = "0x838 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg10(&self) -> &SEQ_QUE {
            self.seq_que(10)
        }
        #[doc = "0x83c - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg11(&self) -> &SEQ_QUE {
            self.seq_que(11)
        }
        #[doc = "0x840 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg12(&self) -> &SEQ_QUE {
            self.seq_que(12)
        }
        #[doc = "0x844 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg13(&self) -> &SEQ_QUE {
            self.seq_que(13)
        }
        #[doc = "0x848 - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg14(&self) -> &SEQ_QUE {
            self.seq_que(14)
        }
        #[doc = "0x84c - no description available"]
        #[inline(always)]
        pub const fn seq_quecfg15(&self) -> &SEQ_QUE {
            self.seq_que(15)
        }
        #[doc = "0x850 - No description avaiable"]
        #[inline(always)]
        pub const fn seq_high_cfg(&self) -> &SEQ_HIGH_CFG {
            &self.seq_high_cfg
        }
        #[doc = "0xc00..0xcc0 - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chn(&self, n: usize) -> &PRD_CFG_CHN {
            #[allow(clippy::no_effect)]
            [(); 16][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(3072)
                    .add(16 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0xc00..0xcc0 - no description available"]
        #[inline(always)]
        pub fn prd_cfg_chn_iter(&self) -> impl Iterator<Item = &PRD_CFG_CHN> {
            (0..16).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(3072)
                    .add(16 * n)
                    .cast()
            })
        }
        #[doc = "0xc00..0xc0c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn0(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(0)
        }
        #[doc = "0xc10..0xc1c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn1(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(1)
        }
        #[doc = "0xc20..0xc2c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn2(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(2)
        }
        #[doc = "0xc30..0xc3c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn3(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(3)
        }
        #[doc = "0xc40..0xc4c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn4(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(4)
        }
        #[doc = "0xc50..0xc5c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn5(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(5)
        }
        #[doc = "0xc60..0xc6c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn6(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(6)
        }
        #[doc = "0xc70..0xc7c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn7(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(7)
        }
        #[doc = "0xc80..0xc8c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn8(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(8)
        }
        #[doc = "0xc90..0xc9c - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn9(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(9)
        }
        #[doc = "0xca0..0xcac - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn10(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(10)
        }
        #[doc = "0xcb0..0xcbc - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn11(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(11)
        }
        #[doc = "0xcc0..0xccc - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn12(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(12)
        }
        #[doc = "0xcd0..0xcdc - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn13(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(13)
        }
        #[doc = "0xce0..0xcec - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn14(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(14)
        }
        #[doc = "0xcf0..0xcfc - no description available"]
        #[inline(always)]
        pub const fn prd_cfg_chnchn15(&self) -> &PRD_CFG_CHN {
            self.prd_cfg_chn(15)
        }
        #[doc = "0x1000..0x1040 - no description available"]
        #[inline(always)]
        pub const fn sample_cfg(&self, n: usize) -> &SAMPLE_CFG {
            &self.sample_cfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1000..0x1040 - no description available"]
        #[inline(always)]
        pub fn sample_cfg_iter(&self) -> impl Iterator<Item = &SAMPLE_CFG> {
            self.sample_cfg.iter()
        }
        #[doc = "0x1000 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn0(&self) -> &SAMPLE_CFG {
            self.sample_cfg(0)
        }
        #[doc = "0x1004 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn1(&self) -> &SAMPLE_CFG {
            self.sample_cfg(1)
        }
        #[doc = "0x1008 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn2(&self) -> &SAMPLE_CFG {
            self.sample_cfg(2)
        }
        #[doc = "0x100c - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn3(&self) -> &SAMPLE_CFG {
            self.sample_cfg(3)
        }
        #[doc = "0x1010 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn4(&self) -> &SAMPLE_CFG {
            self.sample_cfg(4)
        }
        #[doc = "0x1014 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn5(&self) -> &SAMPLE_CFG {
            self.sample_cfg(5)
        }
        #[doc = "0x1018 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn6(&self) -> &SAMPLE_CFG {
            self.sample_cfg(6)
        }
        #[doc = "0x101c - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn7(&self) -> &SAMPLE_CFG {
            self.sample_cfg(7)
        }
        #[doc = "0x1020 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn8(&self) -> &SAMPLE_CFG {
            self.sample_cfg(8)
        }
        #[doc = "0x1024 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn9(&self) -> &SAMPLE_CFG {
            self.sample_cfg(9)
        }
        #[doc = "0x1028 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn10(&self) -> &SAMPLE_CFG {
            self.sample_cfg(10)
        }
        #[doc = "0x102c - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn11(&self) -> &SAMPLE_CFG {
            self.sample_cfg(11)
        }
        #[doc = "0x1030 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn12(&self) -> &SAMPLE_CFG {
            self.sample_cfg(12)
        }
        #[doc = "0x1034 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn13(&self) -> &SAMPLE_CFG {
            self.sample_cfg(13)
        }
        #[doc = "0x1038 - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn14(&self) -> &SAMPLE_CFG {
            self.sample_cfg(14)
        }
        #[doc = "0x103c - no description available"]
        #[inline(always)]
        pub const fn sample_cfgchn15(&self) -> &SAMPLE_CFG {
            self.sample_cfg(15)
        }
        #[doc = "0x1104 - No description avaiable"]
        #[inline(always)]
        pub const fn conv_cfg1(&self) -> &CONV_CFG1 {
            &self.conv_cfg1
        }
        #[doc = "0x1108 - No description avaiable"]
        #[inline(always)]
        pub const fn adc_cfg0(&self) -> &ADC_CFG0 {
            &self.adc_cfg0
        }
        #[doc = "0x1110 - No description avaiable"]
        #[inline(always)]
        pub const fn int_sts(&self) -> &INT_STS {
            &self.int_sts
        }
        #[doc = "0x1114 - No description avaiable"]
        #[inline(always)]
        pub const fn int_en(&self) -> &INT_EN {
            &self.int_en
        }
        #[doc = "0x1200 - No description avaiable"]
        #[inline(always)]
        pub const fn ana_ctrl0(&self) -> &ANA_CTRL0 {
            &self.ana_ctrl0
        }
        #[doc = "0x1210 - No description avaiable"]
        #[inline(always)]
        pub const fn ana_status(&self) -> &ANA_STATUS {
            &self.ana_status
        }
        #[doc = "0x1400..0x1444 - no description available"]
        #[inline(always)]
        pub const fn adc16_params(&self, n: usize) -> &ADC16_PARAMS {
            &self.adc16_params[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1400..0x1444 - no description available"]
        #[inline(always)]
        pub fn adc16_params_iter(&self) -> impl Iterator<Item = &ADC16_PARAMS> {
            self.adc16_params.iter()
        }
        #[doc = "0x1400 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para00(&self) -> &ADC16_PARAMS {
            self.adc16_params(0)
        }
        #[doc = "0x1402 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para01(&self) -> &ADC16_PARAMS {
            self.adc16_params(1)
        }
        #[doc = "0x1404 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para02(&self) -> &ADC16_PARAMS {
            self.adc16_params(2)
        }
        #[doc = "0x1406 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para03(&self) -> &ADC16_PARAMS {
            self.adc16_params(3)
        }
        #[doc = "0x1408 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para04(&self) -> &ADC16_PARAMS {
            self.adc16_params(4)
        }
        #[doc = "0x140a - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para05(&self) -> &ADC16_PARAMS {
            self.adc16_params(5)
        }
        #[doc = "0x140c - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para06(&self) -> &ADC16_PARAMS {
            self.adc16_params(6)
        }
        #[doc = "0x140e - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para07(&self) -> &ADC16_PARAMS {
            self.adc16_params(7)
        }
        #[doc = "0x1410 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para08(&self) -> &ADC16_PARAMS {
            self.adc16_params(8)
        }
        #[doc = "0x1412 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para09(&self) -> &ADC16_PARAMS {
            self.adc16_params(9)
        }
        #[doc = "0x1414 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para10(&self) -> &ADC16_PARAMS {
            self.adc16_params(10)
        }
        #[doc = "0x1416 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para11(&self) -> &ADC16_PARAMS {
            self.adc16_params(11)
        }
        #[doc = "0x1418 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para12(&self) -> &ADC16_PARAMS {
            self.adc16_params(12)
        }
        #[doc = "0x141a - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para13(&self) -> &ADC16_PARAMS {
            self.adc16_params(13)
        }
        #[doc = "0x141c - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para14(&self) -> &ADC16_PARAMS {
            self.adc16_params(14)
        }
        #[doc = "0x141e - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para15(&self) -> &ADC16_PARAMS {
            self.adc16_params(15)
        }
        #[doc = "0x1420 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para16(&self) -> &ADC16_PARAMS {
            self.adc16_params(16)
        }
        #[doc = "0x1422 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para17(&self) -> &ADC16_PARAMS {
            self.adc16_params(17)
        }
        #[doc = "0x1424 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para18(&self) -> &ADC16_PARAMS {
            self.adc16_params(18)
        }
        #[doc = "0x1426 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para19(&self) -> &ADC16_PARAMS {
            self.adc16_params(19)
        }
        #[doc = "0x1428 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para20(&self) -> &ADC16_PARAMS {
            self.adc16_params(20)
        }
        #[doc = "0x142a - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para21(&self) -> &ADC16_PARAMS {
            self.adc16_params(21)
        }
        #[doc = "0x142c - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para22(&self) -> &ADC16_PARAMS {
            self.adc16_params(22)
        }
        #[doc = "0x142e - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para23(&self) -> &ADC16_PARAMS {
            self.adc16_params(23)
        }
        #[doc = "0x1430 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para24(&self) -> &ADC16_PARAMS {
            self.adc16_params(24)
        }
        #[doc = "0x1432 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para25(&self) -> &ADC16_PARAMS {
            self.adc16_params(25)
        }
        #[doc = "0x1434 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para26(&self) -> &ADC16_PARAMS {
            self.adc16_params(26)
        }
        #[doc = "0x1436 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para27(&self) -> &ADC16_PARAMS {
            self.adc16_params(27)
        }
        #[doc = "0x1438 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para28(&self) -> &ADC16_PARAMS {
            self.adc16_params(28)
        }
        #[doc = "0x143a - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para29(&self) -> &ADC16_PARAMS {
            self.adc16_params(29)
        }
        #[doc = "0x143c - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para30(&self) -> &ADC16_PARAMS {
            self.adc16_params(30)
        }
        #[doc = "0x143e - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para31(&self) -> &ADC16_PARAMS {
            self.adc16_params(31)
        }
        #[doc = "0x1440 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para32(&self) -> &ADC16_PARAMS {
            self.adc16_params(32)
        }
        #[doc = "0x1442 - no description available"]
        #[inline(always)]
        pub const fn adc16_paramsadc16_para33(&self) -> &ADC16_PARAMS {
            self.adc16_params(33)
        }
        #[doc = "0x1444 - No description avaiable"]
        #[inline(always)]
        pub const fn adc16_config0(&self) -> &ADC16_CONFIG0 {
            &self.adc16_config0
        }
        #[doc = "0x1460 - No description avaiable"]
        #[inline(always)]
        pub const fn adc16_config1(&self) -> &ADC16_CONFIG1 {
            &self.adc16_config1
        }
    }
    #[doc = "CONFIG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`]
module"]
    pub type CONFIG = crate::Reg<config::CONFIG_SPEC>;
    #[doc = "no description available"]
    pub mod config {
        #[doc = "Register `CONFIG[%s]` reader"]
        pub type R = crate::R<CONFIG_SPEC>;
        #[doc = "Register `CONFIG[%s]` writer"]
        pub type W = crate::W<CONFIG_SPEC>;
        #[doc = "Field `CHAN0` reader - channel number for 1st conversion"]
        pub type CHAN0_R = crate::FieldReader;
        #[doc = "Field `CHAN0` writer - channel number for 1st conversion"]
        pub type CHAN0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `INTEN0` reader - interupt enable for 1st conversion"]
        pub type INTEN0_R = crate::BitReader;
        #[doc = "Field `INTEN0` writer - interupt enable for 1st conversion"]
        pub type INTEN0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `QUEUE_EN` reader - preemption queue enable control"]
        pub type QUEUE_EN_R = crate::BitReader;
        #[doc = "Field `QUEUE_EN` writer - preemption queue enable control"]
        pub type QUEUE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CHAN1` reader - channel number for 2nd conversion"]
        pub type CHAN1_R = crate::FieldReader;
        #[doc = "Field `CHAN1` writer - channel number for 2nd conversion"]
        pub type CHAN1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `INTEN1` reader - interupt enable for 2nd conversion"]
        pub type INTEN1_R = crate::BitReader;
        #[doc = "Field `INTEN1` writer - interupt enable for 2nd conversion"]
        pub type INTEN1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CHAN2` reader - channel number for 3rd conversion"]
        pub type CHAN2_R = crate::FieldReader;
        #[doc = "Field `CHAN2` writer - channel number for 3rd conversion"]
        pub type CHAN2_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `INTEN2` reader - interupt enable for 3rd conversion"]
        pub type INTEN2_R = crate::BitReader;
        #[doc = "Field `INTEN2` writer - interupt enable for 3rd conversion"]
        pub type INTEN2_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CHAN3` reader - channel number for 4th conversion"]
        pub type CHAN3_R = crate::FieldReader;
        #[doc = "Field `CHAN3` writer - channel number for 4th conversion"]
        pub type CHAN3_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `INTEN3` reader - interupt enable for 4th conversion"]
        pub type INTEN3_R = crate::BitReader;
        #[doc = "Field `INTEN3` writer - interupt enable for 4th conversion"]
        pub type INTEN3_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_LEN` writer - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3"]
        pub type TRIG_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        impl R {
            #[doc = "Bits 0:4 - channel number for 1st conversion"]
            #[inline(always)]
            pub fn chan0(&self) -> CHAN0_R {
                CHAN0_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bit 5 - interupt enable for 1st conversion"]
            #[inline(always)]
            pub fn inten0(&self) -> INTEN0_R {
                INTEN0_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - preemption queue enable control"]
            #[inline(always)]
            pub fn queue_en(&self) -> QUEUE_EN_R {
                QUEUE_EN_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bits 8:12 - channel number for 2nd conversion"]
            #[inline(always)]
            pub fn chan1(&self) -> CHAN1_R {
                CHAN1_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bit 13 - interupt enable for 2nd conversion"]
            #[inline(always)]
            pub fn inten1(&self) -> INTEN1_R {
                INTEN1_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bits 16:20 - channel number for 3rd conversion"]
            #[inline(always)]
            pub fn chan2(&self) -> CHAN2_R {
                CHAN2_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bit 21 - interupt enable for 3rd conversion"]
            #[inline(always)]
            pub fn inten2(&self) -> INTEN2_R {
                INTEN2_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bits 24:28 - channel number for 4th conversion"]
            #[inline(always)]
            pub fn chan3(&self) -> CHAN3_R {
                CHAN3_R::new(((self.bits >> 24) & 0x1f) as u8)
            }
            #[doc = "Bit 29 - interupt enable for 4th conversion"]
            #[inline(always)]
            pub fn inten3(&self) -> INTEN3_R {
                INTEN3_R::new(((self.bits >> 29) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - channel number for 1st conversion"]
            #[inline(always)]
            #[must_use]
            pub fn chan0(&mut self) -> CHAN0_W<CONFIG_SPEC> {
                CHAN0_W::new(self, 0)
            }
            #[doc = "Bit 5 - interupt enable for 1st conversion"]
            #[inline(always)]
            #[must_use]
            pub fn inten0(&mut self) -> INTEN0_W<CONFIG_SPEC> {
                INTEN0_W::new(self, 5)
            }
            #[doc = "Bit 6 - preemption queue enable control"]
            #[inline(always)]
            #[must_use]
            pub fn queue_en(&mut self) -> QUEUE_EN_W<CONFIG_SPEC> {
                QUEUE_EN_W::new(self, 6)
            }
            #[doc = "Bits 8:12 - channel number for 2nd conversion"]
            #[inline(always)]
            #[must_use]
            pub fn chan1(&mut self) -> CHAN1_W<CONFIG_SPEC> {
                CHAN1_W::new(self, 8)
            }
            #[doc = "Bit 13 - interupt enable for 2nd conversion"]
            #[inline(always)]
            #[must_use]
            pub fn inten1(&mut self) -> INTEN1_W<CONFIG_SPEC> {
                INTEN1_W::new(self, 13)
            }
            #[doc = "Bits 16:20 - channel number for 3rd conversion"]
            #[inline(always)]
            #[must_use]
            pub fn chan2(&mut self) -> CHAN2_W<CONFIG_SPEC> {
                CHAN2_W::new(self, 16)
            }
            #[doc = "Bit 21 - interupt enable for 3rd conversion"]
            #[inline(always)]
            #[must_use]
            pub fn inten2(&mut self) -> INTEN2_W<CONFIG_SPEC> {
                INTEN2_W::new(self, 21)
            }
            #[doc = "Bits 24:28 - channel number for 4th conversion"]
            #[inline(always)]
            #[must_use]
            pub fn chan3(&mut self) -> CHAN3_W<CONFIG_SPEC> {
                CHAN3_W::new(self, 24)
            }
            #[doc = "Bit 29 - interupt enable for 4th conversion"]
            #[inline(always)]
            #[must_use]
            pub fn inten3(&mut self) -> INTEN3_W<CONFIG_SPEC> {
                INTEN3_W::new(self, 29)
            }
            #[doc = "Bits 30:31 - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3"]
            #[inline(always)]
            #[must_use]
            pub fn trig_len(&mut self) -> TRIG_LEN_W<CONFIG_SPEC> {
                TRIG_LEN_W::new(self, 30)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CONFIG_SPEC;
        impl crate::RegisterSpec for CONFIG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`config::R`](R) reader structure"]
        impl crate::Readable for CONFIG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"]
        impl crate::Writable for CONFIG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CONFIG[%s]
to value 0"]
        impl crate::Resettable for CONFIG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "trg_dma_addr (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_dma_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_dma_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trg_dma_addr`]
module"]
    pub type TRG_DMA_ADDR = crate::Reg<trg_dma_addr::TRG_DMA_ADDR_SPEC>;
    #[doc = "No description avaiable"]
    pub mod trg_dma_addr {
        #[doc = "Register `trg_dma_addr` reader"]
        pub type R = crate::R<TRG_DMA_ADDR_SPEC>;
        #[doc = "Register `trg_dma_addr` writer"]
        pub type W = crate::W<TRG_DMA_ADDR_SPEC>;
        #[doc = "Field `TRG_DMA_ADDR` reader - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion)"]
        pub type TRG_DMA_ADDR_R = crate::FieldReader<u32>;
        #[doc = "Field `TRG_DMA_ADDR` writer - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion)"]
        pub type TRG_DMA_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
        impl R {
            #[doc = "Bits 2:31 - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion)"]
            #[inline(always)]
            pub fn trg_dma_addr(&self) -> TRG_DMA_ADDR_R {
                TRG_DMA_ADDR_R::new((self.bits >> 2) & 0x3fff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 2:31 - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion)"]
            #[inline(always)]
            #[must_use]
            pub fn trg_dma_addr(&mut self) -> TRG_DMA_ADDR_W<TRG_DMA_ADDR_SPEC> {
                TRG_DMA_ADDR_W::new(self, 2)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_dma_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_dma_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRG_DMA_ADDR_SPEC;
        impl crate::RegisterSpec for TRG_DMA_ADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trg_dma_addr::R`](R) reader structure"]
        impl crate::Readable for TRG_DMA_ADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trg_dma_addr::W`](W) writer structure"]
        impl crate::Writable for TRG_DMA_ADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets trg_dma_addr to value 0"]
        impl crate::Resettable for TRG_DMA_ADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "trg_sw_sta (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_sw_sta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_sw_sta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trg_sw_sta`]
module"]
    pub type TRG_SW_STA = crate::Reg<trg_sw_sta::TRG_SW_STA_SPEC>;
    #[doc = "No description avaiable"]
    pub mod trg_sw_sta {
        #[doc = "Register `trg_sw_sta` reader"]
        pub type R = crate::R<TRG_SW_STA_SPEC>;
        #[doc = "Register `trg_sw_sta` writer"]
        pub type W = crate::W<TRG_SW_STA_SPEC>;
        #[doc = "Field `TRIG_SW_INDEX` reader - which trigger for the SW trigger 0 for trig0a, 1 for trig0b… 3 for trig1a, …11 for trig3c"]
        pub type TRIG_SW_INDEX_R = crate::FieldReader;
        #[doc = "Field `TRIG_SW_INDEX` writer - which trigger for the SW trigger 0 for trig0a, 1 for trig0b… 3 for trig1a, …11 for trig3c"]
        pub type TRIG_SW_INDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `TRG_SW_STA` reader - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it."]
        pub type TRG_SW_STA_R = crate::BitReader;
        #[doc = "Field `TRG_SW_STA` writer - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it."]
        pub type TRG_SW_STA_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:3 - which trigger for the SW trigger 0 for trig0a, 1 for trig0b… 3 for trig1a, …11 for trig3c"]
            #[inline(always)]
            pub fn trig_sw_index(&self) -> TRIG_SW_INDEX_R {
                TRIG_SW_INDEX_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bit 4 - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it."]
            #[inline(always)]
            pub fn trg_sw_sta(&self) -> TRG_SW_STA_R {
                TRG_SW_STA_R::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - which trigger for the SW trigger 0 for trig0a, 1 for trig0b… 3 for trig1a, …11 for trig3c"]
            #[inline(always)]
            #[must_use]
            pub fn trig_sw_index(&mut self) -> TRIG_SW_INDEX_W<TRG_SW_STA_SPEC> {
                TRIG_SW_INDEX_W::new(self, 0)
            }
            #[doc = "Bit 4 - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it."]
            #[inline(always)]
            #[must_use]
            pub fn trg_sw_sta(&mut self) -> TRG_SW_STA_W<TRG_SW_STA_SPEC> {
                TRG_SW_STA_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`trg_sw_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`trg_sw_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRG_SW_STA_SPEC;
        impl crate::RegisterSpec for TRG_SW_STA_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`trg_sw_sta::R`](R) reader structure"]
        impl crate::Readable for TRG_SW_STA_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`trg_sw_sta::W`](W) writer structure"]
        impl crate::Writable for TRG_SW_STA_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets trg_sw_sta to value 0"]
        impl crate::Resettable for TRG_SW_STA_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BUS_RESULT (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_result::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bus_result`]
module"]
    pub type BUS_RESULT = crate::Reg<bus_result::BUS_RESULT_SPEC>;
    #[doc = "no description available"]
    pub mod bus_result {
        #[doc = "Register `BUS_RESULT[%s]` reader"]
        pub type R = crate::R<BUS_RESULT_SPEC>;
        #[doc = "Register `BUS_RESULT[%s]` writer"]
        pub type W = crate::W<BUS_RESULT_SPEC>;
        #[doc = "Field `CHAN_RESULT` reader - read this register will trigger one adc conversion. If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long"]
        pub type CHAN_RESULT_R = crate::FieldReader<u16>;
        #[doc = "Field `VALID` reader - set after conversion finished if wait_dis is set, cleared after software read. The first time read with 0 will trigger one new conversion. If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. the result may not realtime if software read once and wait long time to read again"]
        pub type VALID_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:15 - read this register will trigger one adc conversion. If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long"]
            #[inline(always)]
            pub fn chan_result(&self) -> CHAN_RESULT_R {
                CHAN_RESULT_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bit 16 - set after conversion finished if wait_dis is set, cleared after software read. The first time read with 0 will trigger one new conversion. If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. the result may not realtime if software read once and wait long time to read again"]
            #[inline(always)]
            pub fn valid(&self) -> VALID_R {
                VALID_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_result::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_result::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BUS_RESULT_SPEC;
        impl crate::RegisterSpec for BUS_RESULT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bus_result::R`](R) reader structure"]
        impl crate::Readable for BUS_RESULT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bus_result::W`](W) writer structure"]
        impl crate::Writable for BUS_RESULT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BUS_RESULT[%s]
to value 0"]
        impl crate::Resettable for BUS_RESULT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "buf_cfg0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buf_cfg0`]
module"]
    pub type BUF_CFG0 = crate::Reg<buf_cfg0::BUF_CFG0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod buf_cfg0 {
        #[doc = "Register `buf_cfg0` reader"]
        pub type R = crate::R<BUF_CFG0_SPEC>;
        #[doc = "Register `buf_cfg0` writer"]
        pub type W = crate::W<BUF_CFG0_SPEC>;
        #[doc = "Field `WAIT_DIS` reader - set to disable read waiting, get result immediately but maybe not current conversion result."]
        pub type WAIT_DIS_R = crate::BitReader;
        #[doc = "Field `WAIT_DIS` writer - set to disable read waiting, get result immediately but maybe not current conversion result."]
        pub type WAIT_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BUS_MODE_EN` reader - bus mode enable"]
        pub type BUS_MODE_EN_R = crate::BitReader;
        #[doc = "Field `BUS_MODE_EN` writer - bus mode enable"]
        pub type BUS_MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - set to disable read waiting, get result immediately but maybe not current conversion result."]
            #[inline(always)]
            pub fn wait_dis(&self) -> WAIT_DIS_R {
                WAIT_DIS_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - bus mode enable"]
            #[inline(always)]
            pub fn bus_mode_en(&self) -> BUS_MODE_EN_R {
                BUS_MODE_EN_R::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - set to disable read waiting, get result immediately but maybe not current conversion result."]
            #[inline(always)]
            #[must_use]
            pub fn wait_dis(&mut self) -> WAIT_DIS_W<BUF_CFG0_SPEC> {
                WAIT_DIS_W::new(self, 0)
            }
            #[doc = "Bit 1 - bus mode enable"]
            #[inline(always)]
            #[must_use]
            pub fn bus_mode_en(&mut self) -> BUS_MODE_EN_W<BUF_CFG0_SPEC> {
                BUS_MODE_EN_W::new(self, 1)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BUF_CFG0_SPEC;
        impl crate::RegisterSpec for BUF_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`buf_cfg0::R`](R) reader structure"]
        impl crate::Readable for BUF_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`buf_cfg0::W`](W) writer structure"]
        impl crate::Writable for BUF_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets buf_cfg0 to value 0"]
        impl crate::Resettable for BUF_CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "seq_cfg0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@seq_cfg0`]
module"]
    pub type SEQ_CFG0 = crate::Reg<seq_cfg0::SEQ_CFG0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod seq_cfg0 {
        #[doc = "Register `seq_cfg0` reader"]
        pub type R = crate::R<SEQ_CFG0_SPEC>;
        #[doc = "Register `seq_cfg0` writer"]
        pub type W = crate::W<SEQ_CFG0_SPEC>;
        #[doc = "Field `HW_TRIG_EN` reader - set to enable external HW trigger, only trigger on posedge"]
        pub type HW_TRIG_EN_R = crate::BitReader;
        #[doc = "Field `HW_TRIG_EN` writer - set to enable external HW trigger, only trigger on posedge"]
        pub type HW_TRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SW_TRIG_EN` reader - set to enable SW trigger"]
        pub type SW_TRIG_EN_R = crate::BitReader;
        #[doc = "Field `SW_TRIG_EN` writer - set to enable SW trigger"]
        pub type SW_TRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SW_TRIG` writer - SW trigger, pulse signal, cleared by HW one cycle later"]
        pub type SW_TRIG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONT_EN` reader - if set, HW will continue process the queue till end(seq_len) after trigger once"]
        pub type CONT_EN_R = crate::BitReader;
        #[doc = "Field `CONT_EN` writer - if set, HW will continue process the queue till end(seq_len) after trigger once"]
        pub type CONT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESTART_EN` reader - if set together with cont_en, HW will continue process the whole queue after trigger once. If cont_en is 0, this bit is not used"]
        pub type RESTART_EN_R = crate::BitReader;
        #[doc = "Field `RESTART_EN` writer - if set together with cont_en, HW will continue process the whole queue after trigger once. If cont_en is 0, this bit is not used"]
        pub type RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_LEN` reader - sequence queue length, 0 for one, 0xF for 16"]
        pub type SEQ_LEN_R = crate::FieldReader;
        #[doc = "Field `SEQ_LEN` writer - sequence queue length, 0 for one, 0xF for 16"]
        pub type SEQ_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `CYCLE` reader - current dma write cycle bit"]
        pub type CYCLE_R = crate::BitReader;
        impl R {
            #[doc = "Bit 0 - set to enable external HW trigger, only trigger on posedge"]
            #[inline(always)]
            pub fn hw_trig_en(&self) -> HW_TRIG_EN_R {
                HW_TRIG_EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - set to enable SW trigger"]
            #[inline(always)]
            pub fn sw_trig_en(&self) -> SW_TRIG_EN_R {
                SW_TRIG_EN_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 3 - if set, HW will continue process the queue till end(seq_len) after trigger once"]
            #[inline(always)]
            pub fn cont_en(&self) -> CONT_EN_R {
                CONT_EN_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - if set together with cont_en, HW will continue process the whole queue after trigger once. If cont_en is 0, this bit is not used"]
            #[inline(always)]
            pub fn restart_en(&self) -> RESTART_EN_R {
                RESTART_EN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bits 8:11 - sequence queue length, 0 for one, 0xF for 16"]
            #[inline(always)]
            pub fn seq_len(&self) -> SEQ_LEN_R {
                SEQ_LEN_R::new(((self.bits >> 8) & 0x0f) as u8)
            }
            #[doc = "Bit 31 - current dma write cycle bit"]
            #[inline(always)]
            pub fn cycle(&self) -> CYCLE_R {
                CYCLE_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - set to enable external HW trigger, only trigger on posedge"]
            #[inline(always)]
            #[must_use]
            pub fn hw_trig_en(&mut self) -> HW_TRIG_EN_W<SEQ_CFG0_SPEC> {
                HW_TRIG_EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - set to enable SW trigger"]
            #[inline(always)]
            #[must_use]
            pub fn sw_trig_en(&mut self) -> SW_TRIG_EN_W<SEQ_CFG0_SPEC> {
                SW_TRIG_EN_W::new(self, 1)
            }
            #[doc = "Bit 2 - SW trigger, pulse signal, cleared by HW one cycle later"]
            #[inline(always)]
            #[must_use]
            pub fn sw_trig(&mut self) -> SW_TRIG_W<SEQ_CFG0_SPEC> {
                SW_TRIG_W::new(self, 2)
            }
            #[doc = "Bit 3 - if set, HW will continue process the queue till end(seq_len) after trigger once"]
            #[inline(always)]
            #[must_use]
            pub fn cont_en(&mut self) -> CONT_EN_W<SEQ_CFG0_SPEC> {
                CONT_EN_W::new(self, 3)
            }
            #[doc = "Bit 4 - if set together with cont_en, HW will continue process the whole queue after trigger once. If cont_en is 0, this bit is not used"]
            #[inline(always)]
            #[must_use]
            pub fn restart_en(&mut self) -> RESTART_EN_W<SEQ_CFG0_SPEC> {
                RESTART_EN_W::new(self, 4)
            }
            #[doc = "Bits 8:11 - sequence queue length, 0 for one, 0xF for 16"]
            #[inline(always)]
            #[must_use]
            pub fn seq_len(&mut self) -> SEQ_LEN_W<SEQ_CFG0_SPEC> {
                SEQ_LEN_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SEQ_CFG0_SPEC;
        impl crate::RegisterSpec for SEQ_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`seq_cfg0::R`](R) reader structure"]
        impl crate::Readable for SEQ_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`seq_cfg0::W`](W) writer structure"]
        impl crate::Writable for SEQ_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets seq_cfg0 to value 0"]
        impl crate::Resettable for SEQ_CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "seq_dma_addr (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_dma_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_dma_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@seq_dma_addr`]
module"]
    pub type SEQ_DMA_ADDR = crate::Reg<seq_dma_addr::SEQ_DMA_ADDR_SPEC>;
    #[doc = "No description avaiable"]
    pub mod seq_dma_addr {
        #[doc = "Register `seq_dma_addr` reader"]
        pub type R = crate::R<SEQ_DMA_ADDR_SPEC>;
        #[doc = "Register `seq_dma_addr` writer"]
        pub type W = crate::W<SEQ_DMA_ADDR_SPEC>;
        #[doc = "Field `TAR_ADDR` reader - dma target address, should be 4-byte aligned"]
        pub type TAR_ADDR_R = crate::FieldReader<u32>;
        #[doc = "Field `TAR_ADDR` writer - dma target address, should be 4-byte aligned"]
        pub type TAR_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
        impl R {
            #[doc = "Bits 2:31 - dma target address, should be 4-byte aligned"]
            #[inline(always)]
            pub fn tar_addr(&self) -> TAR_ADDR_R {
                TAR_ADDR_R::new((self.bits >> 2) & 0x3fff_ffff)
            }
        }
        impl W {
            #[doc = "Bits 2:31 - dma target address, should be 4-byte aligned"]
            #[inline(always)]
            #[must_use]
            pub fn tar_addr(&mut self) -> TAR_ADDR_W<SEQ_DMA_ADDR_SPEC> {
                TAR_ADDR_W::new(self, 2)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_dma_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_dma_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SEQ_DMA_ADDR_SPEC;
        impl crate::RegisterSpec for SEQ_DMA_ADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`seq_dma_addr::R`](R) reader structure"]
        impl crate::Readable for SEQ_DMA_ADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`seq_dma_addr::W`](W) writer structure"]
        impl crate::Writable for SEQ_DMA_ADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets seq_dma_addr to value 0"]
        impl crate::Resettable for SEQ_DMA_ADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "seq_wr_addr (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_wr_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_wr_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@seq_wr_addr`]
module"]
    pub type SEQ_WR_ADDR = crate::Reg<seq_wr_addr::SEQ_WR_ADDR_SPEC>;
    #[doc = "No description avaiable"]
    pub mod seq_wr_addr {
        #[doc = "Register `seq_wr_addr` reader"]
        pub type R = crate::R<SEQ_WR_ADDR_SPEC>;
        #[doc = "Register `seq_wr_addr` writer"]
        pub type W = crate::W<SEQ_WR_ADDR_SPEC>;
        #[doc = "Field `SEQ_WR_POINTER` reader - HW update this field after each dma write, it indicate the next dma write pointer. dma write address is (tar_addr+seq_wr_pointer)*4"]
        pub type SEQ_WR_POINTER_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:23 - HW update this field after each dma write, it indicate the next dma write pointer. dma write address is (tar_addr+seq_wr_pointer)*4"]
            #[inline(always)]
            pub fn seq_wr_pointer(&self) -> SEQ_WR_POINTER_R {
                SEQ_WR_POINTER_R::new(self.bits & 0x00ff_ffff)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_wr_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_wr_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SEQ_WR_ADDR_SPEC;
        impl crate::RegisterSpec for SEQ_WR_ADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`seq_wr_addr::R`](R) reader structure"]
        impl crate::Readable for SEQ_WR_ADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`seq_wr_addr::W`](W) writer structure"]
        impl crate::Writable for SEQ_WR_ADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets seq_wr_addr to value 0"]
        impl crate::Resettable for SEQ_WR_ADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "seq_dma_cfg (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_dma_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_dma_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@seq_dma_cfg`]
module"]
    pub type SEQ_DMA_CFG = crate::Reg<seq_dma_cfg::SEQ_DMA_CFG_SPEC>;
    #[doc = "No description avaiable"]
    pub mod seq_dma_cfg {
        #[doc = "Register `seq_dma_cfg` reader"]
        pub type R = crate::R<SEQ_DMA_CFG_SPEC>;
        #[doc = "Register `seq_dma_cfg` writer"]
        pub type W = crate::W<SEQ_DMA_CFG_SPEC>;
        #[doc = "Field `BUF_LEN` reader - dma buffer length, after write to (tar_addr\\[31:2\\]+buf_len)*4, the next dma address will be tar_addr\\[31:2\\]*4 0 for 4byte; 0xFFF for 16kbyte."]
        pub type BUF_LEN_R = crate::FieldReader<u16>;
        #[doc = "Field `BUF_LEN` writer - dma buffer length, after write to (tar_addr\\[31:2\\]+buf_len)*4, the next dma address will be tar_addr\\[31:2\\]*4 0 for 4byte; 0xFFF for 16kbyte."]
        pub type BUF_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `STOP_EN` reader - set to stop dma if reach the stop_pos"]
        pub type STOP_EN_R = crate::BitReader;
        #[doc = "Field `STOP_EN` writer - set to stop dma if reach the stop_pos"]
        pub type STOP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_RST` reader - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. SW should clear all cycle bit in buffer to 0 before clear dma_rst"]
        pub type DMA_RST_R = crate::BitReader;
        #[doc = "Field `DMA_RST` writer - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. SW should clear all cycle bit in buffer to 0 before clear dma_rst"]
        pub type DMA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STOP_POS` reader - if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet"]
        pub type STOP_POS_R = crate::FieldReader<u16>;
        #[doc = "Field `STOP_POS` writer - if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet"]
        pub type STOP_POS_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        impl R {
            #[doc = "Bits 0:11 - dma buffer length, after write to (tar_addr\\[31:2\\]+buf_len)*4, the next dma address will be tar_addr\\[31:2\\]*4 0 for 4byte; 0xFFF for 16kbyte."]
            #[inline(always)]
            pub fn buf_len(&self) -> BUF_LEN_R {
                BUF_LEN_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bit 12 - set to stop dma if reach the stop_pos"]
            #[inline(always)]
            pub fn stop_en(&self) -> STOP_EN_R {
                STOP_EN_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 13 - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. SW should clear all cycle bit in buffer to 0 before clear dma_rst"]
            #[inline(always)]
            pub fn dma_rst(&self) -> DMA_RST_R {
                DMA_RST_R::new(((self.bits >> 13) & 1) != 0)
            }
            #[doc = "Bits 16:27 - if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet"]
            #[inline(always)]
            pub fn stop_pos(&self) -> STOP_POS_R {
                STOP_POS_R::new(((self.bits >> 16) & 0x0fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - dma buffer length, after write to (tar_addr\\[31:2\\]+buf_len)*4, the next dma address will be tar_addr\\[31:2\\]*4 0 for 4byte; 0xFFF for 16kbyte."]
            #[inline(always)]
            #[must_use]
            pub fn buf_len(&mut self) -> BUF_LEN_W<SEQ_DMA_CFG_SPEC> {
                BUF_LEN_W::new(self, 0)
            }
            #[doc = "Bit 12 - set to stop dma if reach the stop_pos"]
            #[inline(always)]
            #[must_use]
            pub fn stop_en(&mut self) -> STOP_EN_W<SEQ_DMA_CFG_SPEC> {
                STOP_EN_W::new(self, 12)
            }
            #[doc = "Bit 13 - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. SW should clear all cycle bit in buffer to 0 before clear dma_rst"]
            #[inline(always)]
            #[must_use]
            pub fn dma_rst(&mut self) -> DMA_RST_W<SEQ_DMA_CFG_SPEC> {
                DMA_RST_W::new(self, 13)
            }
            #[doc = "Bits 16:27 - if stop_en is set, SW is responsible to udpate this field to the next read point, HW should not write data to this point since it's not read out by SW yet"]
            #[inline(always)]
            #[must_use]
            pub fn stop_pos(&mut self) -> STOP_POS_W<SEQ_DMA_CFG_SPEC> {
                STOP_POS_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_dma_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_dma_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SEQ_DMA_CFG_SPEC;
        impl crate::RegisterSpec for SEQ_DMA_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`seq_dma_cfg::R`](R) reader structure"]
        impl crate::Readable for SEQ_DMA_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`seq_dma_cfg::W`](W) writer structure"]
        impl crate::Writable for SEQ_DMA_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets seq_dma_cfg to value 0"]
        impl crate::Resettable for SEQ_DMA_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SEQ_QUE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_que::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_que::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@seq_que`]
module"]
    pub type SEQ_QUE = crate::Reg<seq_que::SEQ_QUE_SPEC>;
    #[doc = "no description available"]
    pub mod seq_que {
        #[doc = "Register `SEQ_QUE[%s]` reader"]
        pub type R = crate::R<SEQ_QUE_SPEC>;
        #[doc = "Register `SEQ_QUE[%s]` writer"]
        pub type W = crate::W<SEQ_QUE_SPEC>;
        #[doc = "Field `CHAN_NUM_4_0` reader - channel number for current conversion"]
        pub type CHAN_NUM_4_0_R = crate::FieldReader;
        #[doc = "Field `CHAN_NUM_4_0` writer - channel number for current conversion"]
        pub type CHAN_NUM_4_0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `SEQ_INT_EN` reader - interrupt enable for current conversion"]
        pub type SEQ_INT_EN_R = crate::BitReader;
        #[doc = "Field `SEQ_INT_EN` writer - interrupt enable for current conversion"]
        pub type SEQ_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:4 - channel number for current conversion"]
            #[inline(always)]
            pub fn chan_num_4_0(&self) -> CHAN_NUM_4_0_R {
                CHAN_NUM_4_0_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bit 5 - interrupt enable for current conversion"]
            #[inline(always)]
            pub fn seq_int_en(&self) -> SEQ_INT_EN_R {
                SEQ_INT_EN_R::new(((self.bits >> 5) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - channel number for current conversion"]
            #[inline(always)]
            #[must_use]
            pub fn chan_num_4_0(&mut self) -> CHAN_NUM_4_0_W<SEQ_QUE_SPEC> {
                CHAN_NUM_4_0_W::new(self, 0)
            }
            #[doc = "Bit 5 - interrupt enable for current conversion"]
            #[inline(always)]
            #[must_use]
            pub fn seq_int_en(&mut self) -> SEQ_INT_EN_W<SEQ_QUE_SPEC> {
                SEQ_INT_EN_W::new(self, 5)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_que::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_que::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SEQ_QUE_SPEC;
        impl crate::RegisterSpec for SEQ_QUE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`seq_que::R`](R) reader structure"]
        impl crate::Readable for SEQ_QUE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`seq_que::W`](W) writer structure"]
        impl crate::Writable for SEQ_QUE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SEQ_QUE[%s]
to value 0"]
        impl crate::Resettable for SEQ_QUE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "seq_high_cfg (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_high_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_high_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@seq_high_cfg`]
module"]
    pub type SEQ_HIGH_CFG = crate::Reg<seq_high_cfg::SEQ_HIGH_CFG_SPEC>;
    #[doc = "No description avaiable"]
    pub mod seq_high_cfg {
        #[doc = "Register `seq_high_cfg` reader"]
        pub type R = crate::R<SEQ_HIGH_CFG_SPEC>;
        #[doc = "Register `seq_high_cfg` writer"]
        pub type W = crate::W<SEQ_HIGH_CFG_SPEC>;
        #[doc = "Field `BUF_LEN_HIGH` reader - No description avaiable"]
        pub type BUF_LEN_HIGH_R = crate::FieldReader<u16>;
        #[doc = "Field `BUF_LEN_HIGH` writer - No description avaiable"]
        pub type BUF_LEN_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `STOP_POS_HIGH` reader - No description avaiable"]
        pub type STOP_POS_HIGH_R = crate::FieldReader<u16>;
        #[doc = "Field `STOP_POS_HIGH` writer - No description avaiable"]
        pub type STOP_POS_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        impl R {
            #[doc = "Bits 0:11 - No description avaiable"]
            #[inline(always)]
            pub fn buf_len_high(&self) -> BUF_LEN_HIGH_R {
                BUF_LEN_HIGH_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bits 12:23 - No description avaiable"]
            #[inline(always)]
            pub fn stop_pos_high(&self) -> STOP_POS_HIGH_R {
                STOP_POS_HIGH_R::new(((self.bits >> 12) & 0x0fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf_len_high(&mut self) -> BUF_LEN_HIGH_W<SEQ_HIGH_CFG_SPEC> {
                BUF_LEN_HIGH_W::new(self, 0)
            }
            #[doc = "Bits 12:23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn stop_pos_high(&mut self) -> STOP_POS_HIGH_W<SEQ_HIGH_CFG_SPEC> {
                STOP_POS_HIGH_W::new(self, 12)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`seq_high_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`seq_high_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SEQ_HIGH_CFG_SPEC;
        impl crate::RegisterSpec for SEQ_HIGH_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`seq_high_cfg::R`](R) reader structure"]
        impl crate::Readable for SEQ_HIGH_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`seq_high_cfg::W`](W) writer structure"]
        impl crate::Writable for SEQ_HIGH_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets seq_high_cfg to value 0"]
        impl crate::Resettable for SEQ_HIGH_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::prd_cfg_chn::PRD_CFG_CHN;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod prd_cfg_chn {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct PRD_CFG_CHN {
            prd_cfg: PRD_CFG,
            prd_thshd_cfg: PRD_THSHD_CFG,
            prd_result: PRD_RESULT,
        }
        impl PRD_CFG_CHN {
            #[doc = "0x00 - No description avaiable"]
            #[inline(always)]
            pub const fn prd_cfg(&self) -> &PRD_CFG {
                &self.prd_cfg
            }
            #[doc = "0x04 - No description avaiable"]
            #[inline(always)]
            pub const fn prd_thshd_cfg(&self) -> &PRD_THSHD_CFG {
                &self.prd_thshd_cfg
            }
            #[doc = "0x08 - No description avaiable"]
            #[inline(always)]
            pub const fn prd_result(&self) -> &PRD_RESULT {
                &self.prd_result
            }
        }
        #[doc = "prd_cfg (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prd_cfg`]
module"]
        pub type PRD_CFG = crate::Reg<prd_cfg::PRD_CFG_SPEC>;
        #[doc = "No description avaiable"]
        pub mod prd_cfg {
            #[doc = "Register `prd_cfg` reader"]
            pub type R = crate::R<PRD_CFG_SPEC>;
            #[doc = "Register `prd_cfg` writer"]
            pub type W = crate::W<PRD_CFG_SPEC>;
            #[doc = "Field `PRD` reader - conver period, with prescale. Set to 0 means disable current channel"]
            pub type PRD_R = crate::FieldReader;
            #[doc = "Field `PRD` writer - conver period, with prescale. Set to 0 means disable current channel"]
            pub type PRD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `PRESCALE` reader - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx"]
            pub type PRESCALE_R = crate::FieldReader;
            #[doc = "Field `PRESCALE` writer - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx"]
            pub type PRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            impl R {
                #[doc = "Bits 0:7 - conver period, with prescale. Set to 0 means disable current channel"]
                #[inline(always)]
                pub fn prd(&self) -> PRD_R {
                    PRD_R::new((self.bits & 0xff) as u8)
                }
                #[doc = "Bits 8:12 - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx"]
                #[inline(always)]
                pub fn prescale(&self) -> PRESCALE_R {
                    PRESCALE_R::new(((self.bits >> 8) & 0x1f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - conver period, with prescale. Set to 0 means disable current channel"]
                #[inline(always)]
                #[must_use]
                pub fn prd(&mut self) -> PRD_W<PRD_CFG_SPEC> {
                    PRD_W::new(self, 0)
                }
                #[doc = "Bits 8:12 - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx"]
                #[inline(always)]
                #[must_use]
                pub fn prescale(&mut self) -> PRESCALE_W<PRD_CFG_SPEC> {
                    PRESCALE_W::new(self, 8)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PRD_CFG_SPEC;
            impl crate::RegisterSpec for PRD_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`prd_cfg::R`](R) reader structure"]
            impl crate::Readable for PRD_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`prd_cfg::W`](W) writer structure"]
            impl crate::Writable for PRD_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets prd_cfg to value 0"]
            impl crate::Resettable for PRD_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "prd_thshd_cfg (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_thshd_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_thshd_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prd_thshd_cfg`]
module"]
        pub type PRD_THSHD_CFG = crate::Reg<prd_thshd_cfg::PRD_THSHD_CFG_SPEC>;
        #[doc = "No description avaiable"]
        pub mod prd_thshd_cfg {
            #[doc = "Register `prd_thshd_cfg` reader"]
            pub type R = crate::R<PRD_THSHD_CFG_SPEC>;
            #[doc = "Register `prd_thshd_cfg` writer"]
            pub type W = crate::W<PRD_THSHD_CFG_SPEC>;
            #[doc = "Field `THSHDL` reader - threshold low"]
            pub type THSHDL_R = crate::FieldReader<u16>;
            #[doc = "Field `THSHDL` writer - threshold low"]
            pub type THSHDL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            #[doc = "Field `THSHDH` reader - threshold high, assert interrupt(if enabled) if result exceed high or low."]
            pub type THSHDH_R = crate::FieldReader<u16>;
            #[doc = "Field `THSHDH` writer - threshold high, assert interrupt(if enabled) if result exceed high or low."]
            pub type THSHDH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - threshold low"]
                #[inline(always)]
                pub fn thshdl(&self) -> THSHDL_R {
                    THSHDL_R::new((self.bits & 0xffff) as u16)
                }
                #[doc = "Bits 16:31 - threshold high, assert interrupt(if enabled) if result exceed high or low."]
                #[inline(always)]
                pub fn thshdh(&self) -> THSHDH_R {
                    THSHDH_R::new(((self.bits >> 16) & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - threshold low"]
                #[inline(always)]
                #[must_use]
                pub fn thshdl(&mut self) -> THSHDL_W<PRD_THSHD_CFG_SPEC> {
                    THSHDL_W::new(self, 0)
                }
                #[doc = "Bits 16:31 - threshold high, assert interrupt(if enabled) if result exceed high or low."]
                #[inline(always)]
                #[must_use]
                pub fn thshdh(&mut self) -> THSHDH_W<PRD_THSHD_CFG_SPEC> {
                    THSHDH_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_thshd_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_thshd_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PRD_THSHD_CFG_SPEC;
            impl crate::RegisterSpec for PRD_THSHD_CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`prd_thshd_cfg::R`](R) reader structure"]
            impl crate::Readable for PRD_THSHD_CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`prd_thshd_cfg::W`](W) writer structure"]
            impl crate::Writable for PRD_THSHD_CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets prd_thshd_cfg to value 0"]
            impl crate::Resettable for PRD_THSHD_CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "prd_result (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_result::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_result::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prd_result`]
module"]
        pub type PRD_RESULT = crate::Reg<prd_result::PRD_RESULT_SPEC>;
        #[doc = "No description avaiable"]
        pub mod prd_result {
            #[doc = "Register `prd_result` reader"]
            pub type R = crate::R<PRD_RESULT_SPEC>;
            #[doc = "Register `prd_result` writer"]
            pub type W = crate::W<PRD_RESULT_SPEC>;
            #[doc = "Field `CHAN_RESULT` reader - adc convert result, update after each valid conversion. it may be updated period according to config, also may be updated due to other queue convert the same channel"]
            pub type CHAN_RESULT_R = crate::FieldReader<u16>;
            impl R {
                #[doc = "Bits 0:15 - adc convert result, update after each valid conversion. it may be updated period according to config, also may be updated due to other queue convert the same channel"]
                #[inline(always)]
                pub fn chan_result(&self) -> CHAN_RESULT_R {
                    CHAN_RESULT_R::new((self.bits & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prd_result::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prd_result::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PRD_RESULT_SPEC;
            impl crate::RegisterSpec for PRD_RESULT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`prd_result::R`](R) reader structure"]
            impl crate::Readable for PRD_RESULT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`prd_result::W`](W) writer structure"]
            impl crate::Writable for PRD_RESULT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets prd_result to value 0"]
            impl crate::Resettable for PRD_RESULT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "SAMPLE_CFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_cfg`]
module"]
    pub type SAMPLE_CFG = crate::Reg<sample_cfg::SAMPLE_CFG_SPEC>;
    #[doc = "no description available"]
    pub mod sample_cfg {
        #[doc = "Register `SAMPLE_CFG[%s]` reader"]
        pub type R = crate::R<SAMPLE_CFG_SPEC>;
        #[doc = "Register `SAMPLE_CFG[%s]` writer"]
        pub type W = crate::W<SAMPLE_CFG_SPEC>;
        #[doc = "Field `SAMPLE_CLOCK_NUMBER` reader - sample clock number, base on clock_period, default one period"]
        pub type SAMPLE_CLOCK_NUMBER_R = crate::FieldReader<u16>;
        #[doc = "Field `SAMPLE_CLOCK_NUMBER` writer - sample clock number, base on clock_period, default one period"]
        pub type SAMPLE_CLOCK_NUMBER_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `SAMPLE_CLOCK_NUMBER_SHIFT` reader - shift for sample clock number"]
        pub type SAMPLE_CLOCK_NUMBER_SHIFT_R = crate::FieldReader;
        #[doc = "Field `SAMPLE_CLOCK_NUMBER_SHIFT` writer - shift for sample clock number"]
        pub type SAMPLE_CLOCK_NUMBER_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bits 0:8 - sample clock number, base on clock_period, default one period"]
            #[inline(always)]
            pub fn sample_clock_number(&self) -> SAMPLE_CLOCK_NUMBER_R {
                SAMPLE_CLOCK_NUMBER_R::new((self.bits & 0x01ff) as u16)
            }
            #[doc = "Bits 9:11 - shift for sample clock number"]
            #[inline(always)]
            pub fn sample_clock_number_shift(&self) -> SAMPLE_CLOCK_NUMBER_SHIFT_R {
                SAMPLE_CLOCK_NUMBER_SHIFT_R::new(((self.bits >> 9) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:8 - sample clock number, base on clock_period, default one period"]
            #[inline(always)]
            #[must_use]
            pub fn sample_clock_number(&mut self) -> SAMPLE_CLOCK_NUMBER_W<SAMPLE_CFG_SPEC> {
                SAMPLE_CLOCK_NUMBER_W::new(self, 0)
            }
            #[doc = "Bits 9:11 - shift for sample clock number"]
            #[inline(always)]
            #[must_use]
            pub fn sample_clock_number_shift(
                &mut self,
            ) -> SAMPLE_CLOCK_NUMBER_SHIFT_W<SAMPLE_CFG_SPEC> {
                SAMPLE_CLOCK_NUMBER_SHIFT_W::new(self, 9)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SAMPLE_CFG_SPEC;
        impl crate::RegisterSpec for SAMPLE_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`sample_cfg::R`](R) reader structure"]
        impl crate::Readable for SAMPLE_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`sample_cfg::W`](W) writer structure"]
        impl crate::Writable for SAMPLE_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SAMPLE_CFG[%s]
to value 0"]
        impl crate::Resettable for SAMPLE_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "conv_cfg1 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conv_cfg1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conv_cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conv_cfg1`]
module"]
    pub type CONV_CFG1 = crate::Reg<conv_cfg1::CONV_CFG1_SPEC>;
    #[doc = "No description avaiable"]
    pub mod conv_cfg1 {
        #[doc = "Register `conv_cfg1` reader"]
        pub type R = crate::R<CONV_CFG1_SPEC>;
        #[doc = "Register `conv_cfg1` writer"]
        pub type W = crate::W<CONV_CFG1_SPEC>;
        #[doc = "Field `CLOCK_DIVIDER` reader - clock_period, N half clock cycle per half adc cycle 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3, ... 15 for 1:16 Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk"]
        pub type CLOCK_DIVIDER_R = crate::FieldReader;
        #[doc = "Field `CLOCK_DIVIDER` writer - clock_period, N half clock cycle per half adc cycle 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3, ... 15 for 1:16 Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk"]
        pub type CLOCK_DIVIDER_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `CONVERT_CLOCK_NUMBER` reader - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz)."]
        pub type CONVERT_CLOCK_NUMBER_R = crate::FieldReader;
        #[doc = "Field `CONVERT_CLOCK_NUMBER` writer - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz)."]
        pub type CONVERT_CLOCK_NUMBER_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 0:3 - clock_period, N half clock cycle per half adc cycle 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3, ... 15 for 1:16 Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk"]
            #[inline(always)]
            pub fn clock_divider(&self) -> CLOCK_DIVIDER_R {
                CLOCK_DIVIDER_R::new((self.bits & 0x0f) as u8)
            }
            #[doc = "Bits 4:8 - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz)."]
            #[inline(always)]
            pub fn convert_clock_number(&self) -> CONVERT_CLOCK_NUMBER_R {
                CONVERT_CLOCK_NUMBER_R::new(((self.bits >> 4) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:3 - clock_period, N half clock cycle per half adc cycle 0 for same adc_clk and bus_clk, 1 for 1:2, 2 for 1:3, ... 15 for 1:16 Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk"]
            #[inline(always)]
            #[must_use]
            pub fn clock_divider(&mut self) -> CLOCK_DIVIDER_W<CONV_CFG1_SPEC> {
                CLOCK_DIVIDER_W::new(self, 0)
            }
            #[doc = "Bits 4:8 - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); user can use small value to get faster convertion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC convertion(plus sample) need 25 cycles(50MHz)."]
            #[inline(always)]
            #[must_use]
            pub fn convert_clock_number(&mut self) -> CONVERT_CLOCK_NUMBER_W<CONV_CFG1_SPEC> {
                CONVERT_CLOCK_NUMBER_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conv_cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conv_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CONV_CFG1_SPEC;
        impl crate::RegisterSpec for CONV_CFG1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`conv_cfg1::R`](R) reader structure"]
        impl crate::Readable for CONV_CFG1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`conv_cfg1::W`](W) writer structure"]
        impl crate::Writable for CONV_CFG1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets conv_cfg1 to value 0"]
        impl crate::Resettable for CONV_CFG1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adc_cfg0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_cfg0`]
module"]
    pub type ADC_CFG0 = crate::Reg<adc_cfg0::ADC_CFG0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod adc_cfg0 {
        #[doc = "Register `adc_cfg0` reader"]
        pub type R = crate::R<ADC_CFG0_SPEC>;
        #[doc = "Register `adc_cfg0` writer"]
        pub type W = crate::W<ADC_CFG0_SPEC>;
        #[doc = "Field `PORT3_REALTIME` reader - set to enable trg queue stop other queues"]
        pub type PORT3_REALTIME_R = crate::BitReader;
        #[doc = "Field `PORT3_REALTIME` writer - set to enable trg queue stop other queues"]
        pub type PORT3_REALTIME_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CONVERT_DURATION` reader - for trigger queue, from trg_sample_req to trg_convert_req"]
        pub type CONVERT_DURATION_R = crate::FieldReader<u16>;
        #[doc = "Field `CONVERT_DURATION` writer - for trigger queue, from trg_sample_req to trg_convert_req"]
        pub type CONVERT_DURATION_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `ADC_AHB_EN` reader - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue;"]
        pub type ADC_AHB_EN_R = crate::BitReader;
        #[doc = "Field `ADC_AHB_EN` writer - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue;"]
        pub type ADC_AHB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEL_SYNC_AHB` reader - set to 1 will enable sync AHB bus, to get better bus performance. Adc_clk must to be set to same as bus clock at this mode"]
        pub type SEL_SYNC_AHB_R = crate::BitReader;
        #[doc = "Field `SEL_SYNC_AHB` writer - set to 1 will enable sync AHB bus, to get better bus performance. Adc_clk must to be set to same as bus clock at this mode"]
        pub type SEL_SYNC_AHB_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - set to enable trg queue stop other queues"]
            #[inline(always)]
            pub fn port3_realtime(&self) -> PORT3_REALTIME_R {
                PORT3_REALTIME_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 12:27 - for trigger queue, from trg_sample_req to trg_convert_req"]
            #[inline(always)]
            pub fn convert_duration(&self) -> CONVERT_DURATION_R {
                CONVERT_DURATION_R::new(((self.bits >> 12) & 0xffff) as u16)
            }
            #[doc = "Bit 29 - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue;"]
            #[inline(always)]
            pub fn adc_ahb_en(&self) -> ADC_AHB_EN_R {
                ADC_AHB_EN_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 31 - set to 1 will enable sync AHB bus, to get better bus performance. Adc_clk must to be set to same as bus clock at this mode"]
            #[inline(always)]
            pub fn sel_sync_ahb(&self) -> SEL_SYNC_AHB_R {
                SEL_SYNC_AHB_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - set to enable trg queue stop other queues"]
            #[inline(always)]
            #[must_use]
            pub fn port3_realtime(&mut self) -> PORT3_REALTIME_W<ADC_CFG0_SPEC> {
                PORT3_REALTIME_W::new(self, 0)
            }
            #[doc = "Bits 12:27 - for trigger queue, from trg_sample_req to trg_convert_req"]
            #[inline(always)]
            #[must_use]
            pub fn convert_duration(&mut self) -> CONVERT_DURATION_W<ADC_CFG0_SPEC> {
                CONVERT_DURATION_W::new(self, 12)
            }
            #[doc = "Bit 29 - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue;"]
            #[inline(always)]
            #[must_use]
            pub fn adc_ahb_en(&mut self) -> ADC_AHB_EN_W<ADC_CFG0_SPEC> {
                ADC_AHB_EN_W::new(self, 29)
            }
            #[doc = "Bit 31 - set to 1 will enable sync AHB bus, to get better bus performance. Adc_clk must to be set to same as bus clock at this mode"]
            #[inline(always)]
            #[must_use]
            pub fn sel_sync_ahb(&mut self) -> SEL_SYNC_AHB_W<ADC_CFG0_SPEC> {
                SEL_SYNC_AHB_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADC_CFG0_SPEC;
        impl crate::RegisterSpec for ADC_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adc_cfg0::R`](R) reader structure"]
        impl crate::Readable for ADC_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adc_cfg0::W`](W) writer structure"]
        impl crate::Writable for ADC_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adc_cfg0 to value 0"]
        impl crate::Resettable for ADC_CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "int_sts (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_sts`]
module"]
    pub type INT_STS = crate::Reg<int_sts::INT_STS_SPEC>;
    #[doc = "No description avaiable"]
    pub mod int_sts {
        #[doc = "Register `int_sts` reader"]
        pub type R = crate::R<INT_STS_SPEC>;
        #[doc = "Register `int_sts` writer"]
        pub type W = crate::W<INT_STS_SPEC>;
        #[doc = "Field `WDOG` reader - set if one chanel watch dog event triggered"]
        pub type WDOG_R = crate::FieldReader<u16>;
        #[doc = "Field `WDOG` writer - set if one chanel watch dog event triggered"]
        pub type WDOG_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `AHB_ERR` reader - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
        pub type AHB_ERR_R = crate::BitReader;
        #[doc = "Field `AHB_ERR` writer - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
        pub type AHB_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_FIFO_FULL` reader - DMA fifo full interrupt, user need to check clock frequency if it's set."]
        pub type DMA_FIFO_FULL_R = crate::BitReader;
        #[doc = "Field `DMA_FIFO_FULL` writer - DMA fifo full interrupt, user need to check clock frequency if it's set."]
        pub type DMA_FIFO_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_CVC` reader - one conversion complete in seq_queue if related seq_int_en is set"]
        pub type SEQ_CVC_R = crate::BitReader;
        #[doc = "Field `SEQ_CVC` writer - one conversion complete in seq_queue if related seq_int_en is set"]
        pub type SEQ_CVC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_CMPT` reader - the whole sequence complete interrupt"]
        pub type SEQ_CMPT_R = crate::BitReader;
        #[doc = "Field `SEQ_CMPT` writer - the whole sequence complete interrupt"]
        pub type SEQ_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_DMAABT` reader - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
        pub type SEQ_DMAABT_R = crate::BitReader;
        #[doc = "Field `SEQ_DMAABT` writer - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
        pub type SEQ_DMAABT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_HW_CFLCT` reader - No description avaiable"]
        pub type SEQ_HW_CFLCT_R = crate::BitReader;
        #[doc = "Field `SEQ_HW_CFLCT` writer - No description avaiable"]
        pub type SEQ_HW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_SW_CFLCT` reader - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
        pub type SEQ_SW_CFLCT_R = crate::BitReader;
        #[doc = "Field `SEQ_SW_CFLCT` writer - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
        pub type SEQ_SW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `READ_CFLCT` reader - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
        pub type READ_CFLCT_R = crate::BitReader;
        #[doc = "Field `READ_CFLCT` writer - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
        pub type READ_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_HW_CFLCT` reader - No description avaiable"]
        pub type TRIG_HW_CFLCT_R = crate::BitReader;
        #[doc = "Field `TRIG_HW_CFLCT` writer - No description avaiable"]
        pub type TRIG_HW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_SW_CFLCT` reader - No description avaiable"]
        pub type TRIG_SW_CFLCT_R = crate::BitReader;
        #[doc = "Field `TRIG_SW_CFLCT` writer - No description avaiable"]
        pub type TRIG_SW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_CMPT` reader - interrupt for one trigger conversion complete if enabled"]
        pub type TRIG_CMPT_R = crate::BitReader;
        #[doc = "Field `TRIG_CMPT` writer - interrupt for one trigger conversion complete if enabled"]
        pub type TRIG_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:13 - set if one chanel watch dog event triggered"]
            #[inline(always)]
            pub fn wdog(&self) -> WDOG_R {
                WDOG_R::new((self.bits & 0x3fff) as u16)
            }
            #[doc = "Bit 21 - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
            #[inline(always)]
            pub fn ahb_err(&self) -> AHB_ERR_R {
                AHB_ERR_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - DMA fifo full interrupt, user need to check clock frequency if it's set."]
            #[inline(always)]
            pub fn dma_fifo_full(&self) -> DMA_FIFO_FULL_R {
                DMA_FIFO_FULL_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - one conversion complete in seq_queue if related seq_int_en is set"]
            #[inline(always)]
            pub fn seq_cvc(&self) -> SEQ_CVC_R {
                SEQ_CVC_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - the whole sequence complete interrupt"]
            #[inline(always)]
            pub fn seq_cmpt(&self) -> SEQ_CMPT_R {
                SEQ_CMPT_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
            #[inline(always)]
            pub fn seq_dmaabt(&self) -> SEQ_DMAABT_R {
                SEQ_DMAABT_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn seq_hw_cflct(&self) -> SEQ_HW_CFLCT_R {
                SEQ_HW_CFLCT_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
            #[inline(always)]
            pub fn seq_sw_cflct(&self) -> SEQ_SW_CFLCT_R {
                SEQ_SW_CFLCT_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
            #[inline(always)]
            pub fn read_cflct(&self) -> READ_CFLCT_R {
                READ_CFLCT_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - No description avaiable"]
            #[inline(always)]
            pub fn trig_hw_cflct(&self) -> TRIG_HW_CFLCT_R {
                TRIG_HW_CFLCT_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - No description avaiable"]
            #[inline(always)]
            pub fn trig_sw_cflct(&self) -> TRIG_SW_CFLCT_R {
                TRIG_SW_CFLCT_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - interrupt for one trigger conversion complete if enabled"]
            #[inline(always)]
            pub fn trig_cmpt(&self) -> TRIG_CMPT_R {
                TRIG_CMPT_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:13 - set if one chanel watch dog event triggered"]
            #[inline(always)]
            #[must_use]
            pub fn wdog(&mut self) -> WDOG_W<INT_STS_SPEC> {
                WDOG_W::new(self, 0)
            }
            #[doc = "Bit 21 - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
            #[inline(always)]
            #[must_use]
            pub fn ahb_err(&mut self) -> AHB_ERR_W<INT_STS_SPEC> {
                AHB_ERR_W::new(self, 21)
            }
            #[doc = "Bit 22 - DMA fifo full interrupt, user need to check clock frequency if it's set."]
            #[inline(always)]
            #[must_use]
            pub fn dma_fifo_full(&mut self) -> DMA_FIFO_FULL_W<INT_STS_SPEC> {
                DMA_FIFO_FULL_W::new(self, 22)
            }
            #[doc = "Bit 23 - one conversion complete in seq_queue if related seq_int_en is set"]
            #[inline(always)]
            #[must_use]
            pub fn seq_cvc(&mut self) -> SEQ_CVC_W<INT_STS_SPEC> {
                SEQ_CVC_W::new(self, 23)
            }
            #[doc = "Bit 24 - the whole sequence complete interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn seq_cmpt(&mut self) -> SEQ_CMPT_W<INT_STS_SPEC> {
                SEQ_CMPT_W::new(self, 24)
            }
            #[doc = "Bit 25 - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
            #[inline(always)]
            #[must_use]
            pub fn seq_dmaabt(&mut self) -> SEQ_DMAABT_W<INT_STS_SPEC> {
                SEQ_DMAABT_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn seq_hw_cflct(&mut self) -> SEQ_HW_CFLCT_W<INT_STS_SPEC> {
                SEQ_HW_CFLCT_W::new(self, 26)
            }
            #[doc = "Bit 27 - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
            #[inline(always)]
            #[must_use]
            pub fn seq_sw_cflct(&mut self) -> SEQ_SW_CFLCT_W<INT_STS_SPEC> {
                SEQ_SW_CFLCT_W::new(self, 27)
            }
            #[doc = "Bit 28 - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
            #[inline(always)]
            #[must_use]
            pub fn read_cflct(&mut self) -> READ_CFLCT_W<INT_STS_SPEC> {
                READ_CFLCT_W::new(self, 28)
            }
            #[doc = "Bit 29 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn trig_hw_cflct(&mut self) -> TRIG_HW_CFLCT_W<INT_STS_SPEC> {
                TRIG_HW_CFLCT_W::new(self, 29)
            }
            #[doc = "Bit 30 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn trig_sw_cflct(&mut self) -> TRIG_SW_CFLCT_W<INT_STS_SPEC> {
                TRIG_SW_CFLCT_W::new(self, 30)
            }
            #[doc = "Bit 31 - interrupt for one trigger conversion complete if enabled"]
            #[inline(always)]
            #[must_use]
            pub fn trig_cmpt(&mut self) -> TRIG_CMPT_W<INT_STS_SPEC> {
                TRIG_CMPT_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_STS_SPEC;
        impl crate::RegisterSpec for INT_STS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_sts::R`](R) reader structure"]
        impl crate::Readable for INT_STS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_sts::W`](W) writer structure"]
        impl crate::Writable for INT_STS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets int_sts to value 0"]
        impl crate::Resettable for INT_STS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "int_en (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_en`]
module"]
    pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
    #[doc = "No description avaiable"]
    pub mod int_en {
        #[doc = "Register `int_en` reader"]
        pub type R = crate::R<INT_EN_SPEC>;
        #[doc = "Register `int_en` writer"]
        pub type W = crate::W<INT_EN_SPEC>;
        #[doc = "Field `WDOG` reader - set if one chanel watch dog event triggered"]
        pub type WDOG_R = crate::FieldReader<u16>;
        #[doc = "Field `WDOG` writer - set if one chanel watch dog event triggered"]
        pub type WDOG_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `AHB_ERR` reader - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
        pub type AHB_ERR_R = crate::BitReader;
        #[doc = "Field `AHB_ERR` writer - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
        pub type AHB_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_FIFO_FULL` reader - DMA fifo full interrupt, user need to check clock frequency if it's set."]
        pub type DMA_FIFO_FULL_R = crate::BitReader;
        #[doc = "Field `DMA_FIFO_FULL` writer - DMA fifo full interrupt, user need to check clock frequency if it's set."]
        pub type DMA_FIFO_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_CVC` reader - one conversion complete in seq_queue if related seq_int_en is set"]
        pub type SEQ_CVC_R = crate::BitReader;
        #[doc = "Field `SEQ_CVC` writer - one conversion complete in seq_queue if related seq_int_en is set"]
        pub type SEQ_CVC_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_CMPT` reader - the whole sequence complete interrupt"]
        pub type SEQ_CMPT_R = crate::BitReader;
        #[doc = "Field `SEQ_CMPT` writer - the whole sequence complete interrupt"]
        pub type SEQ_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_DMAABT` reader - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
        pub type SEQ_DMAABT_R = crate::BitReader;
        #[doc = "Field `SEQ_DMAABT` writer - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
        pub type SEQ_DMAABT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_HW_CFLCT` reader - No description avaiable"]
        pub type SEQ_HW_CFLCT_R = crate::BitReader;
        #[doc = "Field `SEQ_HW_CFLCT` writer - No description avaiable"]
        pub type SEQ_HW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEQ_SW_CFLCT` reader - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
        pub type SEQ_SW_CFLCT_R = crate::BitReader;
        #[doc = "Field `SEQ_SW_CFLCT` writer - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
        pub type SEQ_SW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `READ_CFLCT` reader - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
        pub type READ_CFLCT_R = crate::BitReader;
        #[doc = "Field `READ_CFLCT` writer - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
        pub type READ_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_HW_CFLCT` reader - No description avaiable"]
        pub type TRIG_HW_CFLCT_R = crate::BitReader;
        #[doc = "Field `TRIG_HW_CFLCT` writer - No description avaiable"]
        pub type TRIG_HW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_SW_CFLCT` reader - No description avaiable"]
        pub type TRIG_SW_CFLCT_R = crate::BitReader;
        #[doc = "Field `TRIG_SW_CFLCT` writer - No description avaiable"]
        pub type TRIG_SW_CFLCT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_CMPT` reader - interrupt for one trigger conversion complete if enabled"]
        pub type TRIG_CMPT_R = crate::BitReader;
        #[doc = "Field `TRIG_CMPT` writer - interrupt for one trigger conversion complete if enabled"]
        pub type TRIG_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:13 - set if one chanel watch dog event triggered"]
            #[inline(always)]
            pub fn wdog(&self) -> WDOG_R {
                WDOG_R::new((self.bits & 0x3fff) as u16)
            }
            #[doc = "Bit 21 - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
            #[inline(always)]
            pub fn ahb_err(&self) -> AHB_ERR_R {
                AHB_ERR_R::new(((self.bits >> 21) & 1) != 0)
            }
            #[doc = "Bit 22 - DMA fifo full interrupt, user need to check clock frequency if it's set."]
            #[inline(always)]
            pub fn dma_fifo_full(&self) -> DMA_FIFO_FULL_R {
                DMA_FIFO_FULL_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - one conversion complete in seq_queue if related seq_int_en is set"]
            #[inline(always)]
            pub fn seq_cvc(&self) -> SEQ_CVC_R {
                SEQ_CVC_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - the whole sequence complete interrupt"]
            #[inline(always)]
            pub fn seq_cmpt(&self) -> SEQ_CMPT_R {
                SEQ_CMPT_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
            #[inline(always)]
            pub fn seq_dmaabt(&self) -> SEQ_DMAABT_R {
                SEQ_DMAABT_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn seq_hw_cflct(&self) -> SEQ_HW_CFLCT_R {
                SEQ_HW_CFLCT_R::new(((self.bits >> 26) & 1) != 0)
            }
            #[doc = "Bit 27 - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
            #[inline(always)]
            pub fn seq_sw_cflct(&self) -> SEQ_SW_CFLCT_R {
                SEQ_SW_CFLCT_R::new(((self.bits >> 27) & 1) != 0)
            }
            #[doc = "Bit 28 - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
            #[inline(always)]
            pub fn read_cflct(&self) -> READ_CFLCT_R {
                READ_CFLCT_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - No description avaiable"]
            #[inline(always)]
            pub fn trig_hw_cflct(&self) -> TRIG_HW_CFLCT_R {
                TRIG_HW_CFLCT_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 30 - No description avaiable"]
            #[inline(always)]
            pub fn trig_sw_cflct(&self) -> TRIG_SW_CFLCT_R {
                TRIG_SW_CFLCT_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - interrupt for one trigger conversion complete if enabled"]
            #[inline(always)]
            pub fn trig_cmpt(&self) -> TRIG_CMPT_R {
                TRIG_CMPT_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:13 - set if one chanel watch dog event triggered"]
            #[inline(always)]
            #[must_use]
            pub fn wdog(&mut self) -> WDOG_W<INT_EN_SPEC> {
                WDOG_W::new(self, 0)
            }
            #[doc = "Bit 21 - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr"]
            #[inline(always)]
            #[must_use]
            pub fn ahb_err(&mut self) -> AHB_ERR_W<INT_EN_SPEC> {
                AHB_ERR_W::new(self, 21)
            }
            #[doc = "Bit 22 - DMA fifo full interrupt, user need to check clock frequency if it's set."]
            #[inline(always)]
            #[must_use]
            pub fn dma_fifo_full(&mut self) -> DMA_FIFO_FULL_W<INT_EN_SPEC> {
                DMA_FIFO_FULL_W::new(self, 22)
            }
            #[doc = "Bit 23 - one conversion complete in seq_queue if related seq_int_en is set"]
            #[inline(always)]
            #[must_use]
            pub fn seq_cvc(&mut self) -> SEQ_CVC_W<INT_EN_SPEC> {
                SEQ_CVC_W::new(self, 23)
            }
            #[doc = "Bit 24 - the whole sequence complete interrupt"]
            #[inline(always)]
            #[must_use]
            pub fn seq_cmpt(&mut self) -> SEQ_CMPT_W<INT_EN_SPEC> {
                SEQ_CMPT_W::new(self, 24)
            }
            #[doc = "Bit 25 - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set"]
            #[inline(always)]
            #[must_use]
            pub fn seq_dmaabt(&mut self) -> SEQ_DMAABT_W<INT_EN_SPEC> {
                SEQ_DMAABT_W::new(self, 25)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn seq_hw_cflct(&mut self) -> SEQ_HW_CFLCT_W<INT_EN_SPEC> {
                SEQ_HW_CFLCT_W::new(self, 26)
            }
            #[doc = "Bit 27 - sequence queue conflict interrup, set if HW or SW trigger received during conversion"]
            #[inline(always)]
            #[must_use]
            pub fn seq_sw_cflct(&mut self) -> SEQ_SW_CFLCT_W<INT_EN_SPEC> {
                SEQ_SW_CFLCT_W::new(self, 27)
            }
            #[doc = "Bit 28 - read conflict interrup, set if wait_dis is set, one conversion is in progress, SW read another channel"]
            #[inline(always)]
            #[must_use]
            pub fn read_cflct(&mut self) -> READ_CFLCT_W<INT_EN_SPEC> {
                READ_CFLCT_W::new(self, 28)
            }
            #[doc = "Bit 29 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn trig_hw_cflct(&mut self) -> TRIG_HW_CFLCT_W<INT_EN_SPEC> {
                TRIG_HW_CFLCT_W::new(self, 29)
            }
            #[doc = "Bit 30 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn trig_sw_cflct(&mut self) -> TRIG_SW_CFLCT_W<INT_EN_SPEC> {
                TRIG_SW_CFLCT_W::new(self, 30)
            }
            #[doc = "Bit 31 - interrupt for one trigger conversion complete if enabled"]
            #[inline(always)]
            #[must_use]
            pub fn trig_cmpt(&mut self) -> TRIG_CMPT_W<INT_EN_SPEC> {
                TRIG_CMPT_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct INT_EN_SPEC;
        impl crate::RegisterSpec for INT_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`int_en::R`](R) reader structure"]
        impl crate::Readable for INT_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`int_en::W`](W) writer structure"]
        impl crate::Writable for INT_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets int_en to value 0"]
        impl crate::Resettable for INT_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ana_ctrl0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_ctrl0`]
module"]
    pub type ANA_CTRL0 = crate::Reg<ana_ctrl0::ANA_CTRL0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod ana_ctrl0 {
        #[doc = "Register `ana_ctrl0` reader"]
        pub type R = crate::R<ANA_CTRL0_SPEC>;
        #[doc = "Register `ana_ctrl0` writer"]
        pub type W = crate::W<ANA_CTRL0_SPEC>;
        #[doc = "Field `STARTCAL` reader - set to start the offset calibration cycle (Active H). user need to clear it after setting it."]
        pub type STARTCAL_R = crate::BitReader;
        #[doc = "Field `STARTCAL` writer - set to start the offset calibration cycle (Active H). user need to clear it after setting it."]
        pub type STARTCAL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ADC_CLK_ON` reader - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. MUST set clock_period to 0 or 1 for adc16 reg access"]
        pub type ADC_CLK_ON_R = crate::BitReader;
        #[doc = "Field `ADC_CLK_ON` writer - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. MUST set clock_period to 0 or 1 for adc16 reg access"]
        pub type ADC_CLK_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `MOTO_EN` reader - \"set to enable moto_soc and moto_valid. Should use AHB clock for adc, this bit can be used avoid async output\""]
        pub type MOTO_EN_R = crate::BitReader;
        #[doc = "Field `MOTO_EN` writer - \"set to enable moto_soc and moto_valid. Should use AHB clock for adc, this bit can be used avoid async output\""]
        pub type MOTO_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 2 - set to start the offset calibration cycle (Active H). user need to clear it after setting it."]
            #[inline(always)]
            pub fn startcal(&self) -> STARTCAL_R {
                STARTCAL_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 12 - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. MUST set clock_period to 0 or 1 for adc16 reg access"]
            #[inline(always)]
            pub fn adc_clk_on(&self) -> ADC_CLK_ON_R {
                ADC_CLK_ON_R::new(((self.bits >> 12) & 1) != 0)
            }
            #[doc = "Bit 31 - \"set to enable moto_soc and moto_valid. Should use AHB clock for adc, this bit can be used avoid async output\""]
            #[inline(always)]
            pub fn moto_en(&self) -> MOTO_EN_R {
                MOTO_EN_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 2 - set to start the offset calibration cycle (Active H). user need to clear it after setting it."]
            #[inline(always)]
            #[must_use]
            pub fn startcal(&mut self) -> STARTCAL_W<ANA_CTRL0_SPEC> {
                STARTCAL_W::new(self, 2)
            }
            #[doc = "Bit 12 - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. MUST set clock_period to 0 or 1 for adc16 reg access"]
            #[inline(always)]
            #[must_use]
            pub fn adc_clk_on(&mut self) -> ADC_CLK_ON_W<ANA_CTRL0_SPEC> {
                ADC_CLK_ON_W::new(self, 12)
            }
            #[doc = "Bit 31 - \"set to enable moto_soc and moto_valid. Should use AHB clock for adc, this bit can be used avoid async output\""]
            #[inline(always)]
            #[must_use]
            pub fn moto_en(&mut self) -> MOTO_EN_W<ANA_CTRL0_SPEC> {
                MOTO_EN_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ANA_CTRL0_SPEC;
        impl crate::RegisterSpec for ANA_CTRL0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ana_ctrl0::R`](R) reader structure"]
        impl crate::Readable for ANA_CTRL0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ana_ctrl0::W`](W) writer structure"]
        impl crate::Writable for ANA_CTRL0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ana_ctrl0 to value 0"]
        impl crate::Resettable for ANA_CTRL0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ana_status (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_status`]
module"]
    pub type ANA_STATUS = crate::Reg<ana_status::ANA_STATUS_SPEC>;
    #[doc = "No description avaiable"]
    pub mod ana_status {
        #[doc = "Register `ana_status` reader"]
        pub type R = crate::R<ANA_STATUS_SPEC>;
        #[doc = "Register `ana_status` writer"]
        pub type W = crate::W<ANA_STATUS_SPEC>;
        #[doc = "Field `CALON` reader - Indicates if the ADC is in calibration mode (Active H)."]
        pub type CALON_R = crate::BitReader;
        #[doc = "Field `CALON` writer - Indicates if the ADC is in calibration mode (Active H)."]
        pub type CALON_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 7 - Indicates if the ADC is in calibration mode (Active H)."]
            #[inline(always)]
            pub fn calon(&self) -> CALON_R {
                CALON_R::new(((self.bits >> 7) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 7 - Indicates if the ADC is in calibration mode (Active H)."]
            #[inline(always)]
            #[must_use]
            pub fn calon(&mut self) -> CALON_W<ANA_STATUS_SPEC> {
                CALON_W::new(self, 7)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ANA_STATUS_SPEC;
        impl crate::RegisterSpec for ANA_STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ana_status::R`](R) reader structure"]
        impl crate::Readable for ANA_STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ana_status::W`](W) writer structure"]
        impl crate::Writable for ANA_STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ana_status to value 0"]
        impl crate::Resettable for ANA_STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ADC16_PARAMS (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc16_params::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc16_params::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc16_params`]
module"]
    pub type ADC16_PARAMS = crate::Reg<adc16_params::ADC16_PARAMS_SPEC>;
    #[doc = "no description available"]
    pub mod adc16_params {
        #[doc = "Register `ADC16_PARAMS[%s]` reader"]
        pub type R = crate::R<ADC16_PARAMS_SPEC>;
        #[doc = "Register `ADC16_PARAMS[%s]` writer"]
        pub type W = crate::W<ADC16_PARAMS_SPEC>;
        #[doc = "Field `PARAM_VAL` reader - No description avaiable"]
        pub type PARAM_VAL_R = crate::FieldReader<u16>;
        #[doc = "Field `PARAM_VAL` writer - No description avaiable"]
        pub type PARAM_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            pub fn param_val(&self) -> PARAM_VAL_R {
                PARAM_VAL_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn param_val(&mut self) -> PARAM_VAL_W<ADC16_PARAMS_SPEC> {
                PARAM_VAL_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc16_params::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc16_params::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADC16_PARAMS_SPEC;
        impl crate::RegisterSpec for ADC16_PARAMS_SPEC {
            type Ux = u16;
        }
        #[doc = "`read()` method returns [`adc16_params::R`](R) reader structure"]
        impl crate::Readable for ADC16_PARAMS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adc16_params::W`](W) writer structure"]
        impl crate::Writable for ADC16_PARAMS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
        }
        #[doc = "`reset()` method sets ADC16_PARAMS[%s]
to value 0"]
        impl crate::Resettable for ADC16_PARAMS_SPEC {
            const RESET_VALUE: u16 = 0;
        }
    }
    #[doc = "adc16_config0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc16_config0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc16_config0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc16_config0`]
module"]
    pub type ADC16_CONFIG0 = crate::Reg<adc16_config0::ADC16_CONFIG0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod adc16_config0 {
        #[doc = "Register `adc16_config0` reader"]
        pub type R = crate::R<ADC16_CONFIG0_SPEC>;
        #[doc = "Register `adc16_config0` writer"]
        pub type W = crate::W<ADC16_CONFIG0_SPEC>;
        #[doc = "Field `CONV_PARAM` reader - convertion parameter"]
        pub type CONV_PARAM_R = crate::FieldReader<u16>;
        #[doc = "Field `CONV_PARAM` writer - convertion parameter"]
        pub type CONV_PARAM_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
        #[doc = "Field `PREEMPT_EN` reader - set to enable preemption feature"]
        pub type PREEMPT_EN_R = crate::BitReader;
        #[doc = "Field `PREEMPT_EN` writer - set to enable preemption feature"]
        pub type PREEMPT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAL_AVG_CFG` reader - for average the calibration result. 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; 4- 16 loops; 5-32 loops; others reserved"]
        pub type CAL_AVG_CFG_R = crate::FieldReader;
        #[doc = "Field `CAL_AVG_CFG` writer - for average the calibration result. 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; 4- 16 loops; 5-32 loops; others reserved"]
        pub type CAL_AVG_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `BANDGAP_EN` reader - set to enable bandgap. user should set reg_en and bandgap_en before use adc16."]
        pub type BANDGAP_EN_R = crate::BitReader;
        #[doc = "Field `BANDGAP_EN` writer - set to enable bandgap. user should set reg_en and bandgap_en before use adc16."]
        pub type BANDGAP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `REG_EN` reader - set to enable regulator"]
        pub type REG_EN_R = crate::BitReader;
        #[doc = "Field `REG_EN` writer - set to enable regulator"]
        pub type REG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:13 - convertion parameter"]
            #[inline(always)]
            pub fn conv_param(&self) -> CONV_PARAM_R {
                CONV_PARAM_R::new((self.bits & 0x3fff) as u16)
            }
            #[doc = "Bit 14 - set to enable preemption feature"]
            #[inline(always)]
            pub fn preempt_en(&self) -> PREEMPT_EN_R {
                PREEMPT_EN_R::new(((self.bits >> 14) & 1) != 0)
            }
            #[doc = "Bits 20:22 - for average the calibration result. 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; 4- 16 loops; 5-32 loops; others reserved"]
            #[inline(always)]
            pub fn cal_avg_cfg(&self) -> CAL_AVG_CFG_R {
                CAL_AVG_CFG_R::new(((self.bits >> 20) & 7) as u8)
            }
            #[doc = "Bit 23 - set to enable bandgap. user should set reg_en and bandgap_en before use adc16."]
            #[inline(always)]
            pub fn bandgap_en(&self) -> BANDGAP_EN_R {
                BANDGAP_EN_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 24 - set to enable regulator"]
            #[inline(always)]
            pub fn reg_en(&self) -> REG_EN_R {
                REG_EN_R::new(((self.bits >> 24) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:13 - convertion parameter"]
            #[inline(always)]
            #[must_use]
            pub fn conv_param(&mut self) -> CONV_PARAM_W<ADC16_CONFIG0_SPEC> {
                CONV_PARAM_W::new(self, 0)
            }
            #[doc = "Bit 14 - set to enable preemption feature"]
            #[inline(always)]
            #[must_use]
            pub fn preempt_en(&mut self) -> PREEMPT_EN_W<ADC16_CONFIG0_SPEC> {
                PREEMPT_EN_W::new(self, 14)
            }
            #[doc = "Bits 20:22 - for average the calibration result. 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; 4- 16 loops; 5-32 loops; others reserved"]
            #[inline(always)]
            #[must_use]
            pub fn cal_avg_cfg(&mut self) -> CAL_AVG_CFG_W<ADC16_CONFIG0_SPEC> {
                CAL_AVG_CFG_W::new(self, 20)
            }
            #[doc = "Bit 23 - set to enable bandgap. user should set reg_en and bandgap_en before use adc16."]
            #[inline(always)]
            #[must_use]
            pub fn bandgap_en(&mut self) -> BANDGAP_EN_W<ADC16_CONFIG0_SPEC> {
                BANDGAP_EN_W::new(self, 23)
            }
            #[doc = "Bit 24 - set to enable regulator"]
            #[inline(always)]
            #[must_use]
            pub fn reg_en(&mut self) -> REG_EN_W<ADC16_CONFIG0_SPEC> {
                REG_EN_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc16_config0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc16_config0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADC16_CONFIG0_SPEC;
        impl crate::RegisterSpec for ADC16_CONFIG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adc16_config0::R`](R) reader structure"]
        impl crate::Readable for ADC16_CONFIG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adc16_config0::W`](W) writer structure"]
        impl crate::Writable for ADC16_CONFIG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adc16_config0 to value 0"]
        impl crate::Resettable for ADC16_CONFIG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "adc16_config1 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc16_config1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc16_config1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc16_config1`]
module"]
    pub type ADC16_CONFIG1 = crate::Reg<adc16_config1::ADC16_CONFIG1_SPEC>;
    #[doc = "No description avaiable"]
    pub mod adc16_config1 {
        #[doc = "Register `adc16_config1` reader"]
        pub type R = crate::R<ADC16_CONFIG1_SPEC>;
        #[doc = "Register `adc16_config1` writer"]
        pub type W = crate::W<ADC16_CONFIG1_SPEC>;
        #[doc = "Field `COV_END_CNT` reader - used for faster conversion, user can change it to get higher convert speed(but less accuracy). should set to (21-convert_clock_number+1)."]
        pub type COV_END_CNT_R = crate::FieldReader;
        #[doc = "Field `COV_END_CNT` writer - used for faster conversion, user can change it to get higher convert speed(but less accuracy). should set to (21-convert_clock_number+1)."]
        pub type COV_END_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        impl R {
            #[doc = "Bits 8:12 - used for faster conversion, user can change it to get higher convert speed(but less accuracy). should set to (21-convert_clock_number+1)."]
            #[inline(always)]
            pub fn cov_end_cnt(&self) -> COV_END_CNT_R {
                COV_END_CNT_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 8:12 - used for faster conversion, user can change it to get higher convert speed(but less accuracy). should set to (21-convert_clock_number+1)."]
            #[inline(always)]
            #[must_use]
            pub fn cov_end_cnt(&mut self) -> COV_END_CNT_W<ADC16_CONFIG1_SPEC> {
                COV_END_CNT_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc16_config1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc16_config1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADC16_CONFIG1_SPEC;
        impl crate::RegisterSpec for ADC16_CONFIG1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adc16_config1::R`](R) reader structure"]
        impl crate::Readable for ADC16_CONFIG1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adc16_config1::W`](W) writer structure"]
        impl crate::Writable for ADC16_CONFIG1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets adc16_config1 to value 0"]
        impl crate::Resettable for ADC16_CONFIG1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "ADC1"]
pub struct ADC1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for ADC1 {}
impl ADC1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const adc0::RegisterBlock = 0xf308_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const adc0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for ADC1 {
    type Target = adc0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for ADC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ADC1").finish()
    }
}
#[doc = "ADC1"]
pub use self::adc0 as adc1;
#[doc = "DAC0"]
pub struct DAC0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for DAC0 {}
impl DAC0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const dac0::RegisterBlock = 0xf309_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const dac0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for DAC0 {
    type Target = dac0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for DAC0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC0").finish()
    }
}
#[doc = "DAC0"]
pub mod dac0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        cfg0: CFG0,
        cfg1: CFG1,
        cfg2: CFG2,
        _reserved3: [u8; 0x04],
        step_cfg: [STEP_CFG; 4],
        buf_addr: [BUF_ADDR; 2],
        buf_length: BUF_LENGTH,
        _reserved6: [u8; 0x04],
        irq_sts: IRQ_STS,
        irq_en: IRQ_EN,
        dma_en: DMA_EN,
        _reserved9: [u8; 0x04],
        ana_cfg0: ANA_CFG0,
        cfg0_bak: CFG0_BAK,
        status0: STATUS0,
    }
    impl RegisterBlock {
        #[doc = "0x00 - No description avaiable"]
        #[inline(always)]
        pub const fn cfg0(&self) -> &CFG0 {
            &self.cfg0
        }
        #[doc = "0x04 - No description avaiable"]
        #[inline(always)]
        pub const fn cfg1(&self) -> &CFG1 {
            &self.cfg1
        }
        #[doc = "0x08 - No description avaiable"]
        #[inline(always)]
        pub const fn cfg2(&self) -> &CFG2 {
            &self.cfg2
        }
        #[doc = "0x10..0x20 - no description available"]
        #[inline(always)]
        pub const fn step_cfg(&self, n: usize) -> &STEP_CFG {
            &self.step_cfg[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x10..0x20 - no description available"]
        #[inline(always)]
        pub fn step_cfg_iter(&self) -> impl Iterator<Item = &STEP_CFG> {
            self.step_cfg.iter()
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn step_cfgstep0(&self) -> &STEP_CFG {
            self.step_cfg(0)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn step_cfgstep1(&self) -> &STEP_CFG {
            self.step_cfg(1)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn step_cfgstep2(&self) -> &STEP_CFG {
            self.step_cfg(2)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn step_cfgstep3(&self) -> &STEP_CFG {
            self.step_cfg(3)
        }
        #[doc = "0x20..0x28 - no description available"]
        #[inline(always)]
        pub const fn buf_addr(&self, n: usize) -> &BUF_ADDR {
            &self.buf_addr[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x20..0x28 - no description available"]
        #[inline(always)]
        pub fn buf_addr_iter(&self) -> impl Iterator<Item = &BUF_ADDR> {
            self.buf_addr.iter()
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn buf_addrbuf0(&self) -> &BUF_ADDR {
            self.buf_addr(0)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn buf_addrbuf1(&self) -> &BUF_ADDR {
            self.buf_addr(1)
        }
        #[doc = "0x28 - No description avaiable"]
        #[inline(always)]
        pub const fn buf_length(&self) -> &BUF_LENGTH {
            &self.buf_length
        }
        #[doc = "0x30 - No description avaiable"]
        #[inline(always)]
        pub const fn irq_sts(&self) -> &IRQ_STS {
            &self.irq_sts
        }
        #[doc = "0x34 - No description avaiable"]
        #[inline(always)]
        pub const fn irq_en(&self) -> &IRQ_EN {
            &self.irq_en
        }
        #[doc = "0x38 - No description avaiable"]
        #[inline(always)]
        pub const fn dma_en(&self) -> &DMA_EN {
            &self.dma_en
        }
        #[doc = "0x40 - No description avaiable"]
        #[inline(always)]
        pub const fn ana_cfg0(&self) -> &ANA_CFG0 {
            &self.ana_cfg0
        }
        #[doc = "0x44 - No description avaiable"]
        #[inline(always)]
        pub const fn cfg0_bak(&self) -> &CFG0_BAK {
            &self.cfg0_bak
        }
        #[doc = "0x48 - No description avaiable"]
        #[inline(always)]
        pub const fn status0(&self) -> &STATUS0 {
            &self.status0
        }
    }
    #[doc = "cfg0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg0`]
module"]
    pub type CFG0 = crate::Reg<cfg0::CFG0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod cfg0 {
        #[doc = "Register `cfg0` reader"]
        pub type R = crate::R<CFG0_SPEC>;
        #[doc = "Register `cfg0` writer"]
        pub type W = crate::W<CFG0_SPEC>;
        #[doc = "Field `HBURST_CFG` writer - DAC support following fixed burst only 000-SINGLE; 011-INCR4; 101: INCR8 others are reserved"]
        pub type HBURST_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `BUF_DATA_MODE` writer - data structure for buffer mode, 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 1: each 32-bit data contains 1 point, b11:0 for first"]
        pub type BUF_DATA_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DAC_MODE` writer - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; 11: trigger mode, DAC output from external trigger signals Note: Trigger mode is not supported in hpm63xx and hpm62xx families."]
        pub type DAC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `HW_TRIG_EN` writer - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode"]
        pub type HW_TRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_MODE` writer - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data."]
        pub type TRIG_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SYNC_MODE` writer - 1: sync dac clock and ahb clock. all HW trigger signals are pulse in sync mode, can get faster response; 0: async dac clock and ahb_clock all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock)"]
        pub type SYNC_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_AHB_EN` writer - set to enable internal DMA, it will read one burst if enough space in FIFO. Should only be used in buffer mode."]
        pub type DMA_AHB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SW_DAC_DATA` writer - dac data used in direct mode(dac_mode==2'b10)"]
        pub type SW_DAC_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        impl W {
            #[doc = "Bits 0:2 - DAC support following fixed burst only 000-SINGLE; 011-INCR4; 101: INCR8 others are reserved"]
            #[inline(always)]
            #[must_use]
            pub fn hburst_cfg(&mut self) -> HBURST_CFG_W<CFG0_SPEC> {
                HBURST_CFG_W::new(self, 0)
            }
            #[doc = "Bit 3 - data structure for buffer mode, 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 1: each 32-bit data contains 1 point, b11:0 for first"]
            #[inline(always)]
            #[must_use]
            pub fn buf_data_mode(&mut self) -> BUF_DATA_MODE_W<CFG0_SPEC> {
                BUF_DATA_MODE_W::new(self, 3)
            }
            #[doc = "Bits 4:5 - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; 11: trigger mode, DAC output from external trigger signals Note: Trigger mode is not supported in hpm63xx and hpm62xx families."]
            #[inline(always)]
            #[must_use]
            pub fn dac_mode(&mut self) -> DAC_MODE_W<CFG0_SPEC> {
                DAC_MODE_W::new(self, 4)
            }
            #[doc = "Bit 6 - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode"]
            #[inline(always)]
            #[must_use]
            pub fn hw_trig_en(&mut self) -> HW_TRIG_EN_W<CFG0_SPEC> {
                HW_TRIG_EN_W::new(self, 6)
            }
            #[doc = "Bit 7 - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data."]
            #[inline(always)]
            #[must_use]
            pub fn trig_mode(&mut self) -> TRIG_MODE_W<CFG0_SPEC> {
                TRIG_MODE_W::new(self, 7)
            }
            #[doc = "Bit 8 - 1: sync dac clock and ahb clock. all HW trigger signals are pulse in sync mode, can get faster response; 0: async dac clock and ahb_clock all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock)"]
            #[inline(always)]
            #[must_use]
            pub fn sync_mode(&mut self) -> SYNC_MODE_W<CFG0_SPEC> {
                SYNC_MODE_W::new(self, 8)
            }
            #[doc = "Bit 9 - set to enable internal DMA, it will read one burst if enough space in FIFO. Should only be used in buffer mode."]
            #[inline(always)]
            #[must_use]
            pub fn dma_ahb_en(&mut self) -> DMA_AHB_EN_W<CFG0_SPEC> {
                DMA_AHB_EN_W::new(self, 9)
            }
            #[doc = "Bits 16:27 - dac data used in direct mode(dac_mode==2'b10)"]
            #[inline(always)]
            #[must_use]
            pub fn sw_dac_data(&mut self) -> SW_DAC_DATA_W<CFG0_SPEC> {
                SW_DAC_DATA_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CFG0_SPEC;
        impl crate::RegisterSpec for CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg0::R`](R) reader structure"]
        impl crate::Readable for CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cfg0::W`](W) writer structure"]
        impl crate::Writable for CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cfg0 to value 0"]
        impl crate::Resettable for CFG0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "cfg1 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg1`]
module"]
    pub type CFG1 = crate::Reg<cfg1::CFG1_SPEC>;
    #[doc = "No description avaiable"]
    pub mod cfg1 {
        #[doc = "Register `cfg1` reader"]
        pub type R = crate::R<CFG1_SPEC>;
        #[doc = "Register `cfg1` writer"]
        pub type W = crate::W<CFG1_SPEC>;
        #[doc = "Field `DIV_CFG` reader - step mode and buffer mode: defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. Direct mode and trigger mode: defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. Note: For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families."]
        pub type DIV_CFG_R = crate::FieldReader<u16>;
        #[doc = "Field `DIV_CFG` writer - step mode and buffer mode: defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. Direct mode and trigger mode: defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. Note: For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families."]
        pub type DIV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `ANA_DIV_CFG` reader - clock divider config for ana_clk to dac analog; 00: div2 01: div4 10: div6 11: div8"]
        pub type ANA_DIV_CFG_R = crate::FieldReader;
        #[doc = "Field `ANA_DIV_CFG` writer - clock divider config for ana_clk to dac analog; 00: div2 01: div4 10: div6 11: div8"]
        pub type ANA_DIV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `ANA_CLK_EN` reader - set to enable analog clock(divided by ana_div_cfg) need to be set in direct mode and trigger mode"]
        pub type ANA_CLK_EN_R = crate::BitReader;
        #[doc = "Field `ANA_CLK_EN` writer - set to enable analog clock(divided by ana_div_cfg) need to be set in direct mode and trigger mode"]
        pub type ANA_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:15 - step mode and buffer mode: defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. Direct mode and trigger mode: defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. Note: For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families."]
            #[inline(always)]
            pub fn div_cfg(&self) -> DIV_CFG_R {
                DIV_CFG_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:17 - clock divider config for ana_clk to dac analog; 00: div2 01: div4 10: div6 11: div8"]
            #[inline(always)]
            pub fn ana_div_cfg(&self) -> ANA_DIV_CFG_R {
                ANA_DIV_CFG_R::new(((self.bits >> 16) & 3) as u8)
            }
            #[doc = "Bit 18 - set to enable analog clock(divided by ana_div_cfg) need to be set in direct mode and trigger mode"]
            #[inline(always)]
            pub fn ana_clk_en(&self) -> ANA_CLK_EN_R {
                ANA_CLK_EN_R::new(((self.bits >> 18) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - step mode and buffer mode: defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. Direct mode and trigger mode: defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. Note: For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families."]
            #[inline(always)]
            #[must_use]
            pub fn div_cfg(&mut self) -> DIV_CFG_W<CFG1_SPEC> {
                DIV_CFG_W::new(self, 0)
            }
            #[doc = "Bits 16:17 - clock divider config for ana_clk to dac analog; 00: div2 01: div4 10: div6 11: div8"]
            #[inline(always)]
            #[must_use]
            pub fn ana_div_cfg(&mut self) -> ANA_DIV_CFG_W<CFG1_SPEC> {
                ANA_DIV_CFG_W::new(self, 16)
            }
            #[doc = "Bit 18 - set to enable analog clock(divided by ana_div_cfg) need to be set in direct mode and trigger mode"]
            #[inline(always)]
            #[must_use]
            pub fn ana_clk_en(&mut self) -> ANA_CLK_EN_W<CFG1_SPEC> {
                ANA_CLK_EN_W::new(self, 18)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CFG1_SPEC;
        impl crate::RegisterSpec for CFG1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg1::R`](R) reader structure"]
        impl crate::Readable for CFG1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cfg1::W`](W) writer structure"]
        impl crate::Writable for CFG1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cfg1 to value 0x0001_0000"]
        impl crate::Resettable for CFG1_SPEC {
            const RESET_VALUE: u32 = 0x0001_0000;
        }
    }
    #[doc = "cfg2 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg2`]
module"]
    pub type CFG2 = crate::Reg<cfg2::CFG2_SPEC>;
    #[doc = "No description avaiable"]
    pub mod cfg2 {
        #[doc = "Register `cfg2` reader"]
        pub type R = crate::R<CFG2_SPEC>;
        #[doc = "Register `cfg2` writer"]
        pub type W = crate::W<CFG2_SPEC>;
        #[doc = "Field `STEP_SW_TRIG0` reader - software trigger0 for step mode, W1C in single mode. RW in continual mode"]
        pub type STEP_SW_TRIG0_R = crate::BitReader;
        #[doc = "Field `STEP_SW_TRIG0` writer - software trigger0 for step mode, W1C in single mode. RW in continual mode"]
        pub type STEP_SW_TRIG0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STEP_SW_TRIG1` reader - No description avaiable"]
        pub type STEP_SW_TRIG1_R = crate::BitReader;
        #[doc = "Field `STEP_SW_TRIG1` writer - No description avaiable"]
        pub type STEP_SW_TRIG1_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STEP_SW_TRIG2` reader - No description avaiable"]
        pub type STEP_SW_TRIG2_R = crate::BitReader;
        #[doc = "Field `STEP_SW_TRIG2` writer - No description avaiable"]
        pub type STEP_SW_TRIG2_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STEP_SW_TRIG3` reader - No description avaiable"]
        pub type STEP_SW_TRIG3_R = crate::BitReader;
        #[doc = "Field `STEP_SW_TRIG3` writer - No description avaiable"]
        pub type STEP_SW_TRIG3_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BUF_SW_TRIG` reader - software trigger for buffer mode, W1C in single mode. RW in continual mode"]
        pub type BUF_SW_TRIG_R = crate::BitReader;
        #[doc = "Field `BUF_SW_TRIG` writer - software trigger for buffer mode, W1C in single mode. RW in continual mode"]
        pub type BUF_SW_TRIG_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FIFO_CLR` writer - set to clear FIFO content(set both read/write pointer to 0)"]
        pub type FIFO_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_RST0` writer - set to reset dma read pointer to buf0_start_addr"]
        pub type DMA_RST0_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_RST1` writer - set to reset dma read pointer to buf1_start_addr; if set both dma_rst0&amp;dma_rst1, will set to buf0_start_addr user can set fifo_clr bit when use dma_rst*"]
        pub type DMA_RST1_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - software trigger0 for step mode, W1C in single mode. RW in continual mode"]
            #[inline(always)]
            pub fn step_sw_trig0(&self) -> STEP_SW_TRIG0_R {
                STEP_SW_TRIG0_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn step_sw_trig1(&self) -> STEP_SW_TRIG1_R {
                STEP_SW_TRIG1_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            pub fn step_sw_trig2(&self) -> STEP_SW_TRIG2_R {
                STEP_SW_TRIG2_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            pub fn step_sw_trig3(&self) -> STEP_SW_TRIG3_R {
                STEP_SW_TRIG3_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - software trigger for buffer mode, W1C in single mode. RW in continual mode"]
            #[inline(always)]
            pub fn buf_sw_trig(&self) -> BUF_SW_TRIG_R {
                BUF_SW_TRIG_R::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - software trigger0 for step mode, W1C in single mode. RW in continual mode"]
            #[inline(always)]
            #[must_use]
            pub fn step_sw_trig0(&mut self) -> STEP_SW_TRIG0_W<CFG2_SPEC> {
                STEP_SW_TRIG0_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn step_sw_trig1(&mut self) -> STEP_SW_TRIG1_W<CFG2_SPEC> {
                STEP_SW_TRIG1_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn step_sw_trig2(&mut self) -> STEP_SW_TRIG2_W<CFG2_SPEC> {
                STEP_SW_TRIG2_W::new(self, 2)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn step_sw_trig3(&mut self) -> STEP_SW_TRIG3_W<CFG2_SPEC> {
                STEP_SW_TRIG3_W::new(self, 3)
            }
            #[doc = "Bit 4 - software trigger for buffer mode, W1C in single mode. RW in continual mode"]
            #[inline(always)]
            #[must_use]
            pub fn buf_sw_trig(&mut self) -> BUF_SW_TRIG_W<CFG2_SPEC> {
                BUF_SW_TRIG_W::new(self, 4)
            }
            #[doc = "Bit 5 - set to clear FIFO content(set both read/write pointer to 0)"]
            #[inline(always)]
            #[must_use]
            pub fn fifo_clr(&mut self) -> FIFO_CLR_W<CFG2_SPEC> {
                FIFO_CLR_W::new(self, 5)
            }
            #[doc = "Bit 6 - set to reset dma read pointer to buf0_start_addr"]
            #[inline(always)]
            #[must_use]
            pub fn dma_rst0(&mut self) -> DMA_RST0_W<CFG2_SPEC> {
                DMA_RST0_W::new(self, 6)
            }
            #[doc = "Bit 7 - set to reset dma read pointer to buf1_start_addr; if set both dma_rst0&amp;dma_rst1, will set to buf0_start_addr user can set fifo_clr bit when use dma_rst*"]
            #[inline(always)]
            #[must_use]
            pub fn dma_rst1(&mut self) -> DMA_RST1_W<CFG2_SPEC> {
                DMA_RST1_W::new(self, 7)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CFG2_SPEC;
        impl crate::RegisterSpec for CFG2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg2::R`](R) reader structure"]
        impl crate::Readable for CFG2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cfg2::W`](W) writer structure"]
        impl crate::Writable for CFG2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cfg2 to value 0"]
        impl crate::Resettable for CFG2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "STEP_CFG (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`step_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`step_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@step_cfg`]
module"]
    pub type STEP_CFG = crate::Reg<step_cfg::STEP_CFG_SPEC>;
    #[doc = "no description available"]
    pub mod step_cfg {
        #[doc = "Register `STEP_CFG[%s]` reader"]
        pub type R = crate::R<STEP_CFG_SPEC>;
        #[doc = "Register `STEP_CFG[%s]` writer"]
        pub type W = crate::W<STEP_CFG_SPEC>;
        #[doc = "Field `START_POINT` reader - No description avaiable"]
        pub type START_POINT_R = crate::FieldReader<u16>;
        #[doc = "Field `START_POINT` writer - No description avaiable"]
        pub type START_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `STEP_NUM` reader - output data change step_num each DAC clock cycle. Ex: if step_num=3, output data sequence is 0,3,6,9 NOTE: user should make sure end_point can be reached if step_num is not 1 if step_num is 0, output data will always at start point"]
        pub type STEP_NUM_R = crate::FieldReader;
        #[doc = "Field `STEP_NUM` writer - output data change step_num each DAC clock cycle. Ex: if step_num=3, output data sequence is 0,3,6,9 NOTE: user should make sure end_point can be reached if step_num is not 1 if step_num is 0, output data will always at start point"]
        pub type STEP_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `END_POINT` reader - No description avaiable"]
        pub type END_POINT_R = crate::FieldReader<u16>;
        #[doc = "Field `END_POINT` writer - No description avaiable"]
        pub type END_POINT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `UP_DOWN` reader - 0 for up, 1 for down"]
        pub type UP_DOWN_R = crate::BitReader;
        #[doc = "Field `UP_DOWN` writer - 0 for up, 1 for down"]
        pub type UP_DOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `ROUND_MODE` reader - 0: stop at end point; 1: reload start point, step again"]
        pub type ROUND_MODE_R = crate::BitReader;
        #[doc = "Field `ROUND_MODE` writer - 0: stop at end point; 1: reload start point, step again"]
        pub type ROUND_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:11 - No description avaiable"]
            #[inline(always)]
            pub fn start_point(&self) -> START_POINT_R {
                START_POINT_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bits 12:15 - output data change step_num each DAC clock cycle. Ex: if step_num=3, output data sequence is 0,3,6,9 NOTE: user should make sure end_point can be reached if step_num is not 1 if step_num is 0, output data will always at start point"]
            #[inline(always)]
            pub fn step_num(&self) -> STEP_NUM_R {
                STEP_NUM_R::new(((self.bits >> 12) & 0x0f) as u8)
            }
            #[doc = "Bits 16:27 - No description avaiable"]
            #[inline(always)]
            pub fn end_point(&self) -> END_POINT_R {
                END_POINT_R::new(((self.bits >> 16) & 0x0fff) as u16)
            }
            #[doc = "Bit 28 - 0 for up, 1 for down"]
            #[inline(always)]
            pub fn up_down(&self) -> UP_DOWN_R {
                UP_DOWN_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - 0: stop at end point; 1: reload start point, step again"]
            #[inline(always)]
            pub fn round_mode(&self) -> ROUND_MODE_R {
                ROUND_MODE_R::new(((self.bits >> 29) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn start_point(&mut self) -> START_POINT_W<STEP_CFG_SPEC> {
                START_POINT_W::new(self, 0)
            }
            #[doc = "Bits 12:15 - output data change step_num each DAC clock cycle. Ex: if step_num=3, output data sequence is 0,3,6,9 NOTE: user should make sure end_point can be reached if step_num is not 1 if step_num is 0, output data will always at start point"]
            #[inline(always)]
            #[must_use]
            pub fn step_num(&mut self) -> STEP_NUM_W<STEP_CFG_SPEC> {
                STEP_NUM_W::new(self, 12)
            }
            #[doc = "Bits 16:27 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn end_point(&mut self) -> END_POINT_W<STEP_CFG_SPEC> {
                END_POINT_W::new(self, 16)
            }
            #[doc = "Bit 28 - 0 for up, 1 for down"]
            #[inline(always)]
            #[must_use]
            pub fn up_down(&mut self) -> UP_DOWN_W<STEP_CFG_SPEC> {
                UP_DOWN_W::new(self, 28)
            }
            #[doc = "Bit 29 - 0: stop at end point; 1: reload start point, step again"]
            #[inline(always)]
            #[must_use]
            pub fn round_mode(&mut self) -> ROUND_MODE_W<STEP_CFG_SPEC> {
                ROUND_MODE_W::new(self, 29)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`step_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`step_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STEP_CFG_SPEC;
        impl crate::RegisterSpec for STEP_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`step_cfg::R`](R) reader structure"]
        impl crate::Readable for STEP_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`step_cfg::W`](W) writer structure"]
        impl crate::Writable for STEP_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets STEP_CFG[%s]
to value 0"]
        impl crate::Resettable for STEP_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "BUF_ADDR (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buf_addr`]
module"]
    pub type BUF_ADDR = crate::Reg<buf_addr::BUF_ADDR_SPEC>;
    #[doc = "no description available"]
    pub mod buf_addr {
        #[doc = "Register `BUF_ADDR[%s]` reader"]
        pub type R = crate::R<BUF_ADDR_SPEC>;
        #[doc = "Register `BUF_ADDR[%s]` writer"]
        pub type W = crate::W<BUF_ADDR_SPEC>;
        #[doc = "Field `BUF_STOP` reader - set to stop read point at end of bufffer0"]
        pub type BUF_STOP_R = crate::BitReader;
        #[doc = "Field `BUF_STOP` writer - set to stop read point at end of bufffer0"]
        pub type BUF_STOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BUF_START_ADDR` reader - buffer start address, should be 4-byte aligned AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue."]
        pub type BUF_START_ADDR_R = crate::FieldReader<u32>;
        #[doc = "Field `BUF_START_ADDR` writer - buffer start address, should be 4-byte aligned AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue."]
        pub type BUF_START_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
        impl R {
            #[doc = "Bit 0 - set to stop read point at end of bufffer0"]
            #[inline(always)]
            pub fn buf_stop(&self) -> BUF_STOP_R {
                BUF_STOP_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bits 2:31 - buffer start address, should be 4-byte aligned AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue."]
            #[inline(always)]
            pub fn buf_start_addr(&self) -> BUF_START_ADDR_R {
                BUF_START_ADDR_R::new((self.bits >> 2) & 0x3fff_ffff)
            }
        }
        impl W {
            #[doc = "Bit 0 - set to stop read point at end of bufffer0"]
            #[inline(always)]
            #[must_use]
            pub fn buf_stop(&mut self) -> BUF_STOP_W<BUF_ADDR_SPEC> {
                BUF_STOP_W::new(self, 0)
            }
            #[doc = "Bits 2:31 - buffer start address, should be 4-byte aligned AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue."]
            #[inline(always)]
            #[must_use]
            pub fn buf_start_addr(&mut self) -> BUF_START_ADDR_W<BUF_ADDR_SPEC> {
                BUF_START_ADDR_W::new(self, 2)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BUF_ADDR_SPEC;
        impl crate::RegisterSpec for BUF_ADDR_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`buf_addr::R`](R) reader structure"]
        impl crate::Readable for BUF_ADDR_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`buf_addr::W`](W) writer structure"]
        impl crate::Writable for BUF_ADDR_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BUF_ADDR[%s]
to value 0"]
        impl crate::Resettable for BUF_ADDR_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "buf_length (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_length::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_length::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@buf_length`]
module"]
    pub type BUF_LENGTH = crate::Reg<buf_length::BUF_LENGTH_SPEC>;
    #[doc = "No description avaiable"]
    pub mod buf_length {
        #[doc = "Register `buf_length` reader"]
        pub type R = crate::R<BUF_LENGTH_SPEC>;
        #[doc = "Register `buf_length` writer"]
        pub type W = crate::W<BUF_LENGTH_SPEC>;
        #[doc = "Field `BUF0_LEN` reader - No description avaiable"]
        pub type BUF0_LEN_R = crate::FieldReader<u16>;
        #[doc = "Field `BUF0_LEN` writer - No description avaiable"]
        pub type BUF0_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `BUF1_LEN` reader - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer"]
        pub type BUF1_LEN_R = crate::FieldReader<u16>;
        #[doc = "Field `BUF1_LEN` writer - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer"]
        pub type BUF1_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            pub fn buf0_len(&self) -> BUF0_LEN_R {
                BUF0_LEN_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer"]
            #[inline(always)]
            pub fn buf1_len(&self) -> BUF1_LEN_R {
                BUF1_LEN_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf0_len(&mut self) -> BUF0_LEN_W<BUF_LENGTH_SPEC> {
                BUF0_LEN_W::new(self, 0)
            }
            #[doc = "Bits 16:31 - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer"]
            #[inline(always)]
            #[must_use]
            pub fn buf1_len(&mut self) -> BUF1_LEN_W<BUF_LENGTH_SPEC> {
                BUF1_LEN_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`buf_length::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`buf_length::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BUF_LENGTH_SPEC;
        impl crate::RegisterSpec for BUF_LENGTH_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`buf_length::R`](R) reader structure"]
        impl crate::Readable for BUF_LENGTH_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`buf_length::W`](W) writer structure"]
        impl crate::Writable for BUF_LENGTH_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets buf_length to value 0"]
        impl crate::Resettable for BUF_LENGTH_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "irq_sts (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sts`]
module"]
    pub type IRQ_STS = crate::Reg<irq_sts::IRQ_STS_SPEC>;
    #[doc = "No description avaiable"]
    pub mod irq_sts {
        #[doc = "Register `irq_sts` reader"]
        pub type R = crate::R<IRQ_STS_SPEC>;
        #[doc = "Register `irq_sts` writer"]
        pub type W = crate::W<IRQ_STS_SPEC>;
        #[doc = "Field `BUF0_CMPT` writer - No description avaiable"]
        pub type BUF0_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BUF1_CMPT` writer - No description avaiable"]
        pub type BUF1_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FIFO_EMPTY` writer - No description avaiable"]
        pub type FIFO_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AHB_ERROR` writer - set if hresp==2'b01(ERROR)"]
        pub type AHB_ERROR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STEP_CMPT` writer - No description avaiable"]
        pub type STEP_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf0_cmpt(&mut self) -> BUF0_CMPT_W<IRQ_STS_SPEC> {
                BUF0_CMPT_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf1_cmpt(&mut self) -> BUF1_CMPT_W<IRQ_STS_SPEC> {
                BUF1_CMPT_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn fifo_empty(&mut self) -> FIFO_EMPTY_W<IRQ_STS_SPEC> {
                FIFO_EMPTY_W::new(self, 2)
            }
            #[doc = "Bit 3 - set if hresp==2'b01(ERROR)"]
            #[inline(always)]
            #[must_use]
            pub fn ahb_error(&mut self) -> AHB_ERROR_W<IRQ_STS_SPEC> {
                AHB_ERROR_W::new(self, 3)
            }
            #[doc = "Bit 4 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn step_cmpt(&mut self) -> STEP_CMPT_W<IRQ_STS_SPEC> {
                STEP_CMPT_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IRQ_STS_SPEC;
        impl crate::RegisterSpec for IRQ_STS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`irq_sts::R`](R) reader structure"]
        impl crate::Readable for IRQ_STS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`irq_sts::W`](W) writer structure"]
        impl crate::Writable for IRQ_STS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets irq_sts to value 0"]
        impl crate::Resettable for IRQ_STS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "irq_en (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_en`]
module"]
    pub type IRQ_EN = crate::Reg<irq_en::IRQ_EN_SPEC>;
    #[doc = "No description avaiable"]
    pub mod irq_en {
        #[doc = "Register `irq_en` reader"]
        pub type R = crate::R<IRQ_EN_SPEC>;
        #[doc = "Register `irq_en` writer"]
        pub type W = crate::W<IRQ_EN_SPEC>;
        #[doc = "Field `BUF0_CMPT` reader - No description avaiable"]
        pub type BUF0_CMPT_R = crate::BitReader;
        #[doc = "Field `BUF0_CMPT` writer - No description avaiable"]
        pub type BUF0_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BUF1_CMPT` reader - No description avaiable"]
        pub type BUF1_CMPT_R = crate::BitReader;
        #[doc = "Field `BUF1_CMPT` writer - No description avaiable"]
        pub type BUF1_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `FIFO_EMPTY` reader - No description avaiable"]
        pub type FIFO_EMPTY_R = crate::BitReader;
        #[doc = "Field `FIFO_EMPTY` writer - No description avaiable"]
        pub type FIFO_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AHB_ERROR` reader - No description avaiable"]
        pub type AHB_ERROR_R = crate::BitReader;
        #[doc = "Field `AHB_ERROR` writer - No description avaiable"]
        pub type AHB_ERROR_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STEP_CMPT` reader - No description avaiable"]
        pub type STEP_CMPT_R = crate::BitReader;
        #[doc = "Field `STEP_CMPT` writer - No description avaiable"]
        pub type STEP_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            pub fn buf0_cmpt(&self) -> BUF0_CMPT_R {
                BUF0_CMPT_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn buf1_cmpt(&self) -> BUF1_CMPT_R {
                BUF1_CMPT_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            pub fn fifo_empty(&self) -> FIFO_EMPTY_R {
                FIFO_EMPTY_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            pub fn ahb_error(&self) -> AHB_ERROR_R {
                AHB_ERROR_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - No description avaiable"]
            #[inline(always)]
            pub fn step_cmpt(&self) -> STEP_CMPT_R {
                STEP_CMPT_R::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf0_cmpt(&mut self) -> BUF0_CMPT_W<IRQ_EN_SPEC> {
                BUF0_CMPT_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf1_cmpt(&mut self) -> BUF1_CMPT_W<IRQ_EN_SPEC> {
                BUF1_CMPT_W::new(self, 1)
            }
            #[doc = "Bit 2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn fifo_empty(&mut self) -> FIFO_EMPTY_W<IRQ_EN_SPEC> {
                FIFO_EMPTY_W::new(self, 2)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn ahb_error(&mut self) -> AHB_ERROR_W<IRQ_EN_SPEC> {
                AHB_ERROR_W::new(self, 3)
            }
            #[doc = "Bit 4 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn step_cmpt(&mut self) -> STEP_CMPT_W<IRQ_EN_SPEC> {
                STEP_CMPT_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct IRQ_EN_SPEC;
        impl crate::RegisterSpec for IRQ_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`irq_en::R`](R) reader structure"]
        impl crate::Readable for IRQ_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`irq_en::W`](W) writer structure"]
        impl crate::Writable for IRQ_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets irq_en to value 0"]
        impl crate::Resettable for IRQ_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "dma_en (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_en::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_en`]
module"]
    pub type DMA_EN = crate::Reg<dma_en::DMA_EN_SPEC>;
    #[doc = "No description avaiable"]
    pub mod dma_en {
        #[doc = "Register `dma_en` reader"]
        pub type R = crate::R<DMA_EN_SPEC>;
        #[doc = "Register `dma_en` writer"]
        pub type W = crate::W<DMA_EN_SPEC>;
        #[doc = "Field `BUF0_CMPT` reader - No description avaiable"]
        pub type BUF0_CMPT_R = crate::BitReader;
        #[doc = "Field `BUF0_CMPT` writer - No description avaiable"]
        pub type BUF0_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BUF1_CMPT` reader - No description avaiable"]
        pub type BUF1_CMPT_R = crate::BitReader;
        #[doc = "Field `BUF1_CMPT` writer - No description avaiable"]
        pub type BUF1_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `STEP_CMPT` reader - No description avaiable"]
        pub type STEP_CMPT_R = crate::BitReader;
        #[doc = "Field `STEP_CMPT` writer - No description avaiable"]
        pub type STEP_CMPT_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            pub fn buf0_cmpt(&self) -> BUF0_CMPT_R {
                BUF0_CMPT_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn buf1_cmpt(&self) -> BUF1_CMPT_R {
                BUF1_CMPT_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 4 - No description avaiable"]
            #[inline(always)]
            pub fn step_cmpt(&self) -> STEP_CMPT_R {
                STEP_CMPT_R::new(((self.bits >> 4) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf0_cmpt(&mut self) -> BUF0_CMPT_W<DMA_EN_SPEC> {
                BUF0_CMPT_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn buf1_cmpt(&mut self) -> BUF1_CMPT_W<DMA_EN_SPEC> {
                BUF1_CMPT_W::new(self, 1)
            }
            #[doc = "Bit 4 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn step_cmpt(&mut self) -> STEP_CMPT_W<DMA_EN_SPEC> {
                STEP_CMPT_W::new(self, 4)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DMA_EN_SPEC;
        impl crate::RegisterSpec for DMA_EN_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dma_en::R`](R) reader structure"]
        impl crate::Readable for DMA_EN_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dma_en::W`](W) writer structure"]
        impl crate::Writable for DMA_EN_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets dma_en to value 0"]
        impl crate::Resettable for DMA_EN_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ana_cfg0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ana_cfg0`]
module"]
    pub type ANA_CFG0 = crate::Reg<ana_cfg0::ANA_CFG0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod ana_cfg0 {
        #[doc = "Register `ana_cfg0` reader"]
        pub type R = crate::R<ANA_CFG0_SPEC>;
        #[doc = "Register `ana_cfg0` writer"]
        pub type W = crate::W<ANA_CFG0_SPEC>;
        #[doc = "Field `DAC12BIT_EN` reader - No description avaiable"]
        pub type DAC12BIT_EN_R = crate::BitReader;
        #[doc = "Field `DAC12BIT_EN` writer - No description avaiable"]
        pub type DAC12BIT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BYPASS_CALI_GM` reader - No description avaiable"]
        pub type BYPASS_CALI_GM_R = crate::BitReader;
        #[doc = "Field `BYPASS_CALI_GM` writer - No description avaiable"]
        pub type BYPASS_CALI_GM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CALI_DELTA_V_CFG` reader - No description avaiable"]
        pub type CALI_DELTA_V_CFG_R = crate::FieldReader;
        #[doc = "Field `CALI_DELTA_V_CFG` writer - No description avaiable"]
        pub type CALI_DELTA_V_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `DAC_CONFIG` reader - No description avaiable"]
        pub type DAC_CONFIG_R = crate::FieldReader;
        #[doc = "Field `DAC_CONFIG` writer - No description avaiable"]
        pub type DAC_CONFIG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DAC12BIT_LP_MODE` reader - No description avaiable"]
        pub type DAC12BIT_LP_MODE_R = crate::BitReader;
        #[doc = "Field `DAC12BIT_LP_MODE` writer - No description avaiable"]
        pub type DAC12BIT_LP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            pub fn dac12bit_en(&self) -> DAC12BIT_EN_R {
                DAC12BIT_EN_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            pub fn bypass_cali_gm(&self) -> BYPASS_CALI_GM_R {
                BYPASS_CALI_GM_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bits 2:3 - No description avaiable"]
            #[inline(always)]
            pub fn cali_delta_v_cfg(&self) -> CALI_DELTA_V_CFG_R {
                CALI_DELTA_V_CFG_R::new(((self.bits >> 2) & 3) as u8)
            }
            #[doc = "Bits 4:7 - No description avaiable"]
            #[inline(always)]
            pub fn dac_config(&self) -> DAC_CONFIG_R {
                DAC_CONFIG_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            pub fn dac12bit_lp_mode(&self) -> DAC12BIT_LP_MODE_R {
                DAC12BIT_LP_MODE_R::new(((self.bits >> 8) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dac12bit_en(&mut self) -> DAC12BIT_EN_W<ANA_CFG0_SPEC> {
                DAC12BIT_EN_W::new(self, 0)
            }
            #[doc = "Bit 1 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn bypass_cali_gm(&mut self) -> BYPASS_CALI_GM_W<ANA_CFG0_SPEC> {
                BYPASS_CALI_GM_W::new(self, 1)
            }
            #[doc = "Bits 2:3 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cali_delta_v_cfg(&mut self) -> CALI_DELTA_V_CFG_W<ANA_CFG0_SPEC> {
                CALI_DELTA_V_CFG_W::new(self, 2)
            }
            #[doc = "Bits 4:7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dac_config(&mut self) -> DAC_CONFIG_W<ANA_CFG0_SPEC> {
                DAC_CONFIG_W::new(self, 4)
            }
            #[doc = "Bit 8 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn dac12bit_lp_mode(&mut self) -> DAC12BIT_LP_MODE_W<ANA_CFG0_SPEC> {
                DAC12BIT_LP_MODE_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ana_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ana_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ANA_CFG0_SPEC;
        impl crate::RegisterSpec for ANA_CFG0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ana_cfg0::R`](R) reader structure"]
        impl crate::Readable for ANA_CFG0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ana_cfg0::W`](W) writer structure"]
        impl crate::Writable for ANA_CFG0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ana_cfg0 to value 0x30"]
        impl crate::Resettable for ANA_CFG0_SPEC {
            const RESET_VALUE: u32 = 0x30;
        }
    }
    #[doc = "cfg0_bak (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0_bak::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0_bak::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg0_bak`]
module"]
    pub type CFG0_BAK = crate::Reg<cfg0_bak::CFG0_BAK_SPEC>;
    #[doc = "No description avaiable"]
    pub mod cfg0_bak {
        #[doc = "Register `cfg0_bak` reader"]
        pub type R = crate::R<CFG0_BAK_SPEC>;
        #[doc = "Register `cfg0_bak` writer"]
        pub type W = crate::W<CFG0_BAK_SPEC>;
        #[doc = "Field `HBURST_CFG` reader - DAC support following fixed burst only 000-SINGLE; 011-INCR4; 101: INCR8 others are reserved"]
        pub type HBURST_CFG_R = crate::FieldReader;
        #[doc = "Field `HBURST_CFG` writer - DAC support following fixed burst only 000-SINGLE; 011-INCR4; 101: INCR8 others are reserved"]
        pub type HBURST_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `BUF_DATA_MODE` reader - data structure for buffer mode, 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 1: each 32-bit data contains 1 point, b11:0 for first"]
        pub type BUF_DATA_MODE_R = crate::BitReader;
        #[doc = "Field `BUF_DATA_MODE` writer - data structure for buffer mode, 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 1: each 32-bit data contains 1 point, b11:0 for first"]
        pub type BUF_DATA_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DAC_MODE` reader - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO;"]
        pub type DAC_MODE_R = crate::FieldReader;
        #[doc = "Field `DAC_MODE` writer - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO;"]
        pub type DAC_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `HW_TRIG_EN` reader - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode"]
        pub type HW_TRIG_EN_R = crate::BitReader;
        #[doc = "Field `HW_TRIG_EN` writer - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode"]
        pub type HW_TRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIG_MODE` reader - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data."]
        pub type TRIG_MODE_R = crate::BitReader;
        #[doc = "Field `TRIG_MODE` writer - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data."]
        pub type TRIG_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SYNC_MODE` reader - 1: sync dac clock and ahb clock. all HW trigger signals are pulse in sync mode, can get faster response; 0: async dac clock and ahb_clock all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock)"]
        pub type SYNC_MODE_R = crate::BitReader;
        #[doc = "Field `SYNC_MODE` writer - 1: sync dac clock and ahb clock. all HW trigger signals are pulse in sync mode, can get faster response; 0: async dac clock and ahb_clock all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock)"]
        pub type SYNC_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DMA_AHB_EN` reader - set to enable internal DMA, it will read one burst if enough space in FIFO. Should only be used in buffer mode."]
        pub type DMA_AHB_EN_R = crate::BitReader;
        #[doc = "Field `DMA_AHB_EN` writer - set to enable internal DMA, it will read one burst if enough space in FIFO. Should only be used in buffer mode."]
        pub type DMA_AHB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SW_DAC_DATA` reader - dac data used in direct mode(dac_mode==2'b10)"]
        pub type SW_DAC_DATA_R = crate::FieldReader<u16>;
        #[doc = "Field `SW_DAC_DATA` writer - dac data used in direct mode(dac_mode==2'b10)"]
        pub type SW_DAC_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        impl R {
            #[doc = "Bits 0:2 - DAC support following fixed burst only 000-SINGLE; 011-INCR4; 101: INCR8 others are reserved"]
            #[inline(always)]
            pub fn hburst_cfg(&self) -> HBURST_CFG_R {
                HBURST_CFG_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 3 - data structure for buffer mode, 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 1: each 32-bit data contains 1 point, b11:0 for first"]
            #[inline(always)]
            pub fn buf_data_mode(&self) -> BUF_DATA_MODE_R {
                BUF_DATA_MODE_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 4:5 - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO;"]
            #[inline(always)]
            pub fn dac_mode(&self) -> DAC_MODE_R {
                DAC_MODE_R::new(((self.bits >> 4) & 3) as u8)
            }
            #[doc = "Bit 6 - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode"]
            #[inline(always)]
            pub fn hw_trig_en(&self) -> HW_TRIG_EN_R {
                HW_TRIG_EN_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bit 7 - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data."]
            #[inline(always)]
            pub fn trig_mode(&self) -> TRIG_MODE_R {
                TRIG_MODE_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - 1: sync dac clock and ahb clock. all HW trigger signals are pulse in sync mode, can get faster response; 0: async dac clock and ahb_clock all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock)"]
            #[inline(always)]
            pub fn sync_mode(&self) -> SYNC_MODE_R {
                SYNC_MODE_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 9 - set to enable internal DMA, it will read one burst if enough space in FIFO. Should only be used in buffer mode."]
            #[inline(always)]
            pub fn dma_ahb_en(&self) -> DMA_AHB_EN_R {
                DMA_AHB_EN_R::new(((self.bits >> 9) & 1) != 0)
            }
            #[doc = "Bits 16:27 - dac data used in direct mode(dac_mode==2'b10)"]
            #[inline(always)]
            pub fn sw_dac_data(&self) -> SW_DAC_DATA_R {
                SW_DAC_DATA_R::new(((self.bits >> 16) & 0x0fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - DAC support following fixed burst only 000-SINGLE; 011-INCR4; 101: INCR8 others are reserved"]
            #[inline(always)]
            #[must_use]
            pub fn hburst_cfg(&mut self) -> HBURST_CFG_W<CFG0_BAK_SPEC> {
                HBURST_CFG_W::new(self, 0)
            }
            #[doc = "Bit 3 - data structure for buffer mode, 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. 1: each 32-bit data contains 1 point, b11:0 for first"]
            #[inline(always)]
            #[must_use]
            pub fn buf_data_mode(&mut self) -> BUF_DATA_MODE_W<CFG0_BAK_SPEC> {
                BUF_DATA_MODE_W::new(self, 3)
            }
            #[doc = "Bits 4:5 - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO;"]
            #[inline(always)]
            #[must_use]
            pub fn dac_mode(&mut self) -> DAC_MODE_W<CFG0_BAK_SPEC> {
                DAC_MODE_W::new(self, 4)
            }
            #[doc = "Bit 6 - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode"]
            #[inline(always)]
            #[must_use]
            pub fn hw_trig_en(&mut self) -> HW_TRIG_EN_W<CFG0_BAK_SPEC> {
                HW_TRIG_EN_W::new(self, 6)
            }
            #[doc = "Bit 7 - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data."]
            #[inline(always)]
            #[must_use]
            pub fn trig_mode(&mut self) -> TRIG_MODE_W<CFG0_BAK_SPEC> {
                TRIG_MODE_W::new(self, 7)
            }
            #[doc = "Bit 8 - 1: sync dac clock and ahb clock. all HW trigger signals are pulse in sync mode, can get faster response; 0: async dac clock and ahb_clock all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock)"]
            #[inline(always)]
            #[must_use]
            pub fn sync_mode(&mut self) -> SYNC_MODE_W<CFG0_BAK_SPEC> {
                SYNC_MODE_W::new(self, 8)
            }
            #[doc = "Bit 9 - set to enable internal DMA, it will read one burst if enough space in FIFO. Should only be used in buffer mode."]
            #[inline(always)]
            #[must_use]
            pub fn dma_ahb_en(&mut self) -> DMA_AHB_EN_W<CFG0_BAK_SPEC> {
                DMA_AHB_EN_W::new(self, 9)
            }
            #[doc = "Bits 16:27 - dac data used in direct mode(dac_mode==2'b10)"]
            #[inline(always)]
            #[must_use]
            pub fn sw_dac_data(&mut self) -> SW_DAC_DATA_W<CFG0_BAK_SPEC> {
                SW_DAC_DATA_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0_bak::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0_bak::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CFG0_BAK_SPEC;
        impl crate::RegisterSpec for CFG0_BAK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`cfg0_bak::R`](R) reader structure"]
        impl crate::Readable for CFG0_BAK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`cfg0_bak::W`](W) writer structure"]
        impl crate::Writable for CFG0_BAK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets cfg0_bak to value 0"]
        impl crate::Resettable for CFG0_BAK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "status0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status0`]
module"]
    pub type STATUS0 = crate::Reg<status0::STATUS0_SPEC>;
    #[doc = "No description avaiable"]
    pub mod status0 {
        #[doc = "Register `status0` reader"]
        pub type R = crate::R<STATUS0_SPEC>;
        #[doc = "Register `status0` writer"]
        pub type W = crate::W<STATUS0_SPEC>;
        #[doc = "Field `CUR_BUF_INDEX` reader - No description avaiable"]
        pub type CUR_BUF_INDEX_R = crate::BitReader;
        #[doc = "Field `CUR_BUF_INDEX` writer - No description avaiable"]
        pub type CUR_BUF_INDEX_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CUR_BUF_OFFSET` reader - No description avaiable"]
        pub type CUR_BUF_OFFSET_R = crate::FieldReader<u16>;
        #[doc = "Field `CUR_BUF_OFFSET` writer - No description avaiable"]
        pub type CUR_BUF_OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            pub fn cur_buf_index(&self) -> CUR_BUF_INDEX_R {
                CUR_BUF_INDEX_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bits 8:23 - No description avaiable"]
            #[inline(always)]
            pub fn cur_buf_offset(&self) -> CUR_BUF_OFFSET_R {
                CUR_BUF_OFFSET_R::new(((self.bits >> 8) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bit 7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cur_buf_index(&mut self) -> CUR_BUF_INDEX_W<STATUS0_SPEC> {
                CUR_BUF_INDEX_W::new(self, 7)
            }
            #[doc = "Bits 8:23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn cur_buf_offset(&mut self) -> CUR_BUF_OFFSET_W<STATUS0_SPEC> {
                CUR_BUF_OFFSET_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STATUS0_SPEC;
        impl crate::RegisterSpec for STATUS0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`status0::R`](R) reader structure"]
        impl crate::Readable for STATUS0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`status0::W`](W) writer structure"]
        impl crate::Writable for STATUS0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets status0 to value 0"]
        impl crate::Resettable for STATUS0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "DAC1"]
pub struct DAC1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for DAC1 {}
impl DAC1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const dac0::RegisterBlock = 0xf309_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const dac0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for DAC1 {
    type Target = dac0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for DAC1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("DAC1").finish()
    }
}
#[doc = "DAC1"]
pub use self::dac0 as dac1;
#[doc = "OPAMP0"]
pub struct OPAMP0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for OPAMP0 {}
impl OPAMP0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const opamp0::RegisterBlock = 0xf30a_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const opamp0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for OPAMP0 {
    type Target = opamp0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for OPAMP0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OPAMP0").finish()
    }
}
#[doc = "OPAMP0"]
pub mod opamp0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        ctrl0: CTRL0,
        status: STATUS,
        ctrl1: CTRL1,
        _reserved3: [u8; 0x04],
        cfg: (),
    }
    impl RegisterBlock {
        #[doc = "0x00 - control reg"]
        #[inline(always)]
        pub const fn ctrl0(&self) -> &CTRL0 {
            &self.ctrl0
        }
        #[doc = "0x04 - status reg"]
        #[inline(always)]
        pub const fn status(&self) -> &STATUS {
            &self.status
        }
        #[doc = "0x08 - control reg1"]
        #[inline(always)]
        pub const fn ctrl1(&self) -> &CTRL1 {
            &self.ctrl1
        }
        #[doc = "0x10..0x70 - no description available"]
        #[inline(always)]
        pub const fn cfg(&self, n: usize) -> &CFG {
            #[allow(clippy::no_effect)]
            [(); 8][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(16)
                    .add(16 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x10..0x70 - no description available"]
        #[inline(always)]
        pub fn cfg_iter(&self) -> impl Iterator<Item = &CFG> {
            (0..8).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(16)
                    .add(16 * n)
                    .cast()
            })
        }
        #[doc = "0x10..0x1c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset0(&self) -> &CFG {
            self.cfg(0)
        }
        #[doc = "0x20..0x2c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset1(&self) -> &CFG {
            self.cfg(1)
        }
        #[doc = "0x30..0x3c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset2(&self) -> &CFG {
            self.cfg(2)
        }
        #[doc = "0x40..0x4c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset3(&self) -> &CFG {
            self.cfg(3)
        }
        #[doc = "0x50..0x5c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset4(&self) -> &CFG {
            self.cfg(4)
        }
        #[doc = "0x60..0x6c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset5(&self) -> &CFG {
            self.cfg(5)
        }
        #[doc = "0x70..0x7c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset6(&self) -> &CFG {
            self.cfg(6)
        }
        #[doc = "0x80..0x8c - no description available"]
        #[inline(always)]
        pub const fn cfgpreset7(&self) -> &CFG {
            self.cfg(7)
        }
    }
    #[doc = "ctrl0 (rw) register accessor: control reg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
module"]
    pub type CTRL0 = crate::Reg<ctrl0::CTRL0_SPEC>;
    #[doc = "control reg"]
    pub mod ctrl0 {
        #[doc = "Register `ctrl0` reader"]
        pub type R = crate::R<CTRL0_SPEC>;
        #[doc = "Register `ctrl0` writer"]
        pub type W = crate::W<CTRL0_SPEC>;
        #[doc = "Field `VIP_SEL` reader - No description avaiable"]
        pub type VIP_SEL_R = crate::FieldReader;
        #[doc = "Field `VIP_SEL` writer - No description avaiable"]
        pub type VIP_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `VBYPASS` reader - No description avaiable"]
        pub type VBYPASS_R = crate::BitReader;
        #[doc = "Field `VBYPASS` writer - No description avaiable"]
        pub type VBYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CSEL` reader - No description avaiable"]
        pub type CSEL_R = crate::FieldReader;
        #[doc = "Field `CSEL` writer - No description avaiable"]
        pub type CSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `GPA_SEL` reader - No description avaiable"]
        pub type GPA_SEL_R = crate::FieldReader;
        #[doc = "Field `GPA_SEL` writer - No description avaiable"]
        pub type GPA_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `VIM_SEL` reader - No description avaiable"]
        pub type VIM_SEL_R = crate::FieldReader;
        #[doc = "Field `VIM_SEL` writer - No description avaiable"]
        pub type VIM_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `ISEL` reader - No description avaiable"]
        pub type ISEL_R = crate::FieldReader;
        #[doc = "Field `ISEL` writer - No description avaiable"]
        pub type ISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `VSWITCH_SEL` reader - No description avaiable"]
        pub type VSWITCH_SEL_R = crate::FieldReader;
        #[doc = "Field `VSWITCH_SEL` writer - No description avaiable"]
        pub type VSWITCH_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `OPAOUT_SEL` reader - No description avaiable"]
        pub type OPAOUT_SEL_R = crate::FieldReader;
        #[doc = "Field `OPAOUT_SEL` writer - No description avaiable"]
        pub type OPAOUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `EN_LV` reader - No description avaiable"]
        pub type EN_LV_R = crate::BitReader;
        #[doc = "Field `EN_LV` writer - No description avaiable"]
        pub type EN_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:2 - No description avaiable"]
            #[inline(always)]
            pub fn vip_sel(&self) -> VIP_SEL_R {
                VIP_SEL_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            pub fn vbypass(&self) -> VBYPASS_R {
                VBYPASS_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bits 4:7 - No description avaiable"]
            #[inline(always)]
            pub fn csel(&self) -> CSEL_R {
                CSEL_R::new(((self.bits >> 4) & 0x0f) as u8)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            pub fn gpa_sel(&self) -> GPA_SEL_R {
                GPA_SEL_R::new(((self.bits >> 8) & 0xff) as u8)
            }
            #[doc = "Bits 16:18 - No description avaiable"]
            #[inline(always)]
            pub fn vim_sel(&self) -> VIM_SEL_R {
                VIM_SEL_R::new(((self.bits >> 16) & 7) as u8)
            }
            #[doc = "Bits 19:20 - No description avaiable"]
            #[inline(always)]
            pub fn isel(&self) -> ISEL_R {
                ISEL_R::new(((self.bits >> 19) & 3) as u8)
            }
            #[doc = "Bits 21:23 - No description avaiable"]
            #[inline(always)]
            pub fn vswitch_sel(&self) -> VSWITCH_SEL_R {
                VSWITCH_SEL_R::new(((self.bits >> 21) & 7) as u8)
            }
            #[doc = "Bits 24:25 - No description avaiable"]
            #[inline(always)]
            pub fn opaout_sel(&self) -> OPAOUT_SEL_R {
                OPAOUT_SEL_R::new(((self.bits >> 24) & 3) as u8)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            pub fn en_lv(&self) -> EN_LV_R {
                EN_LV_R::new(((self.bits >> 26) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn vip_sel(&mut self) -> VIP_SEL_W<CTRL0_SPEC> {
                VIP_SEL_W::new(self, 0)
            }
            #[doc = "Bit 3 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn vbypass(&mut self) -> VBYPASS_W<CTRL0_SPEC> {
                VBYPASS_W::new(self, 3)
            }
            #[doc = "Bits 4:7 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn csel(&mut self) -> CSEL_W<CTRL0_SPEC> {
                CSEL_W::new(self, 4)
            }
            #[doc = "Bits 8:15 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn gpa_sel(&mut self) -> GPA_SEL_W<CTRL0_SPEC> {
                GPA_SEL_W::new(self, 8)
            }
            #[doc = "Bits 16:18 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn vim_sel(&mut self) -> VIM_SEL_W<CTRL0_SPEC> {
                VIM_SEL_W::new(self, 16)
            }
            #[doc = "Bits 19:20 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn isel(&mut self) -> ISEL_W<CTRL0_SPEC> {
                ISEL_W::new(self, 19)
            }
            #[doc = "Bits 21:23 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn vswitch_sel(&mut self) -> VSWITCH_SEL_W<CTRL0_SPEC> {
                VSWITCH_SEL_W::new(self, 21)
            }
            #[doc = "Bits 24:25 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn opaout_sel(&mut self) -> OPAOUT_SEL_W<CTRL0_SPEC> {
                OPAOUT_SEL_W::new(self, 24)
            }
            #[doc = "Bit 26 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn en_lv(&mut self) -> EN_LV_W<CTRL0_SPEC> {
                EN_LV_W::new(self, 26)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control reg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CTRL0_SPEC;
        impl crate::RegisterSpec for CTRL0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"]
        impl crate::Readable for CTRL0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
        impl crate::Writable for CTRL0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ctrl0 to value 0"]
        impl crate::Resettable for CTRL0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "status (rw) register accessor: status reg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
    pub type STATUS = crate::Reg<status::STATUS_SPEC>;
    #[doc = "status reg"]
    pub mod status {
        #[doc = "Register `status` reader"]
        pub type R = crate::R<STATUS_SPEC>;
        #[doc = "Register `status` writer"]
        pub type W = crate::W<STATUS_SPEC>;
        #[doc = "Field `CUR_PRESET` reader - current selected preset"]
        pub type CUR_PRESET_R = crate::FieldReader;
        #[doc = "Field `PRESET_ACT` reader - 1 for preset active; one of cur_preset is selected for OPAMP; 0 for no preset, OPAMP use cfg0 parameters"]
        pub type PRESET_ACT_R = crate::BitReader;
        #[doc = "Field `TRIG_CONFLICT` reader - if more than one hardware trigger is set, will put all trigger input here; write any value to clear"]
        pub type TRIG_CONFLICT_R = crate::FieldReader;
        #[doc = "Field `TRIG_CONFLICT` writer - if more than one hardware trigger is set, will put all trigger input here; write any value to clear"]
        pub type TRIG_CONFLICT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 16:18 - current selected preset"]
            #[inline(always)]
            pub fn cur_preset(&self) -> CUR_PRESET_R {
                CUR_PRESET_R::new(((self.bits >> 16) & 7) as u8)
            }
            #[doc = "Bit 19 - 1 for preset active; one of cur_preset is selected for OPAMP; 0 for no preset, OPAMP use cfg0 parameters"]
            #[inline(always)]
            pub fn preset_act(&self) -> PRESET_ACT_R {
                PRESET_ACT_R::new(((self.bits >> 19) & 1) != 0)
            }
            #[doc = "Bits 20:27 - if more than one hardware trigger is set, will put all trigger input here; write any value to clear"]
            #[inline(always)]
            pub fn trig_conflict(&self) -> TRIG_CONFLICT_R {
                TRIG_CONFLICT_R::new(((self.bits >> 20) & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 20:27 - if more than one hardware trigger is set, will put all trigger input here; write any value to clear"]
            #[inline(always)]
            #[must_use]
            pub fn trig_conflict(&mut self) -> TRIG_CONFLICT_W<STATUS_SPEC> {
                TRIG_CONFLICT_W::new(self, 20)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "status reg\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STATUS_SPEC;
        impl crate::RegisterSpec for STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`status::R`](R) reader structure"]
        impl crate::Readable for STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
        impl crate::Writable for STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets status to value 0"]
        impl crate::Resettable for STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ctrl1 (rw) register accessor: control reg1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
module"]
    pub type CTRL1 = crate::Reg<ctrl1::CTRL1_SPEC>;
    #[doc = "control reg1"]
    pub mod ctrl1 {
        #[doc = "Register `ctrl1` reader"]
        pub type R = crate::R<CTRL1_SPEC>;
        #[doc = "Register `ctrl1` writer"]
        pub type W = crate::W<CTRL1_SPEC>;
        #[doc = "Field `SW_SEL` reader - No description avaiable"]
        pub type SW_SEL_R = crate::FieldReader;
        #[doc = "Field `SW_SEL` writer - No description avaiable"]
        pub type SW_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `SW_PRESET` reader - set to use preset defined by sw_sel. NOTE: when set, the hardware trigger will not be used"]
        pub type SW_PRESET_R = crate::BitReader;
        #[doc = "Field `SW_PRESET` writer - set to use preset defined by sw_sel. NOTE: when set, the hardware trigger will not be used"]
        pub type SW_PRESET_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:2 - No description avaiable"]
            #[inline(always)]
            pub fn sw_sel(&self) -> SW_SEL_R {
                SW_SEL_R::new((self.bits & 7) as u8)
            }
            #[doc = "Bit 31 - set to use preset defined by sw_sel. NOTE: when set, the hardware trigger will not be used"]
            #[inline(always)]
            pub fn sw_preset(&self) -> SW_PRESET_R {
                SW_PRESET_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:2 - No description avaiable"]
            #[inline(always)]
            #[must_use]
            pub fn sw_sel(&mut self) -> SW_SEL_W<CTRL1_SPEC> {
                SW_SEL_W::new(self, 0)
            }
            #[doc = "Bit 31 - set to use preset defined by sw_sel. NOTE: when set, the hardware trigger will not be used"]
            #[inline(always)]
            #[must_use]
            pub fn sw_preset(&mut self) -> SW_PRESET_W<CTRL1_SPEC> {
                SW_PRESET_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control reg1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CTRL1_SPEC;
        impl crate::RegisterSpec for CTRL1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"]
        impl crate::Readable for CTRL1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
        impl crate::Writable for CTRL1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ctrl1 to value 0"]
        impl crate::Resettable for CTRL1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::cfg::CFG;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod cfg {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct CFG {
            cfg0: CFG0,
            cfg1: CFG1,
            cfg2: CFG2,
        }
        impl CFG {
            #[doc = "0x00 - No description avaiable"]
            #[inline(always)]
            pub const fn cfg0(&self) -> &CFG0 {
                &self.cfg0
            }
            #[doc = "0x04 - No description avaiable"]
            #[inline(always)]
            pub const fn cfg1(&self) -> &CFG1 {
                &self.cfg1
            }
            #[doc = "0x08 - No description avaiable"]
            #[inline(always)]
            pub const fn cfg2(&self) -> &CFG2 {
                &self.cfg2
            }
        }
        #[doc = "cfg0 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg0`]
module"]
        pub type CFG0 = crate::Reg<cfg0::CFG0_SPEC>;
        #[doc = "No description avaiable"]
        pub mod cfg0 {
            #[doc = "Register `cfg0` reader"]
            pub type R = crate::R<CFG0_SPEC>;
            #[doc = "Register `cfg0` writer"]
            pub type W = crate::W<CFG0_SPEC>;
            #[doc = "Field `VIP_SEL` reader - No description avaiable"]
            pub type VIP_SEL_R = crate::FieldReader;
            #[doc = "Field `VIP_SEL` writer - No description avaiable"]
            pub type VIP_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `VIM_SEL` reader - No description avaiable"]
            pub type VIM_SEL_R = crate::FieldReader;
            #[doc = "Field `VIM_SEL` writer - No description avaiable"]
            pub type VIM_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `VSWITCH_SEL` reader - No description avaiable"]
            pub type VSWITCH_SEL_R = crate::FieldReader;
            #[doc = "Field `VSWITCH_SEL` writer - No description avaiable"]
            pub type VSWITCH_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `CSEL` reader - No description avaiable"]
            pub type CSEL_R = crate::FieldReader;
            #[doc = "Field `CSEL` writer - No description avaiable"]
            pub type CSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            impl R {
                #[doc = "Bits 0:2 - No description avaiable"]
                #[inline(always)]
                pub fn vip_sel(&self) -> VIP_SEL_R {
                    VIP_SEL_R::new((self.bits & 7) as u8)
                }
                #[doc = "Bits 8:10 - No description avaiable"]
                #[inline(always)]
                pub fn vim_sel(&self) -> VIM_SEL_R {
                    VIM_SEL_R::new(((self.bits >> 8) & 7) as u8)
                }
                #[doc = "Bits 16:18 - No description avaiable"]
                #[inline(always)]
                pub fn vswitch_sel(&self) -> VSWITCH_SEL_R {
                    VSWITCH_SEL_R::new(((self.bits >> 16) & 7) as u8)
                }
                #[doc = "Bits 24:27 - No description avaiable"]
                #[inline(always)]
                pub fn csel(&self) -> CSEL_R {
                    CSEL_R::new(((self.bits >> 24) & 0x0f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:2 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn vip_sel(&mut self) -> VIP_SEL_W<CFG0_SPEC> {
                    VIP_SEL_W::new(self, 0)
                }
                #[doc = "Bits 8:10 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn vim_sel(&mut self) -> VIM_SEL_W<CFG0_SPEC> {
                    VIM_SEL_W::new(self, 8)
                }
                #[doc = "Bits 16:18 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn vswitch_sel(&mut self) -> VSWITCH_SEL_W<CFG0_SPEC> {
                    VSWITCH_SEL_W::new(self, 16)
                }
                #[doc = "Bits 24:27 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn csel(&mut self) -> CSEL_W<CFG0_SPEC> {
                    CSEL_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CFG0_SPEC;
            impl crate::RegisterSpec for CFG0_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cfg0::R`](R) reader structure"]
            impl crate::Readable for CFG0_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cfg0::W`](W) writer structure"]
            impl crate::Writable for CFG0_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets cfg0 to value 0"]
            impl crate::Resettable for CFG0_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "cfg1 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg1`]
module"]
        pub type CFG1 = crate::Reg<cfg1::CFG1_SPEC>;
        #[doc = "No description avaiable"]
        pub mod cfg1 {
            #[doc = "Register `cfg1` reader"]
            pub type R = crate::R<CFG1_SPEC>;
            #[doc = "Register `cfg1` writer"]
            pub type W = crate::W<CFG1_SPEC>;
            #[doc = "Field `PGA_SEL` reader - No description avaiable"]
            pub type PGA_SEL_R = crate::FieldReader;
            #[doc = "Field `PGA_SEL` writer - No description avaiable"]
            pub type PGA_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `ISEL` reader - No description avaiable"]
            pub type ISEL_R = crate::FieldReader;
            #[doc = "Field `ISEL` writer - No description avaiable"]
            pub type ISEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `OPAOUT_SEL` reader - No description avaiable"]
            pub type OPAOUT_SEL_R = crate::FieldReader;
            #[doc = "Field `OPAOUT_SEL` writer - No description avaiable"]
            pub type OPAOUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `VBYPASS_LV` reader - No description avaiable"]
            pub type VBYPASS_LV_R = crate::BitReader;
            #[doc = "Field `VBYPASS_LV` writer - No description avaiable"]
            pub type VBYPASS_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `EN_LV` reader - No description avaiable"]
            pub type EN_LV_R = crate::BitReader;
            #[doc = "Field `EN_LV` writer - No description avaiable"]
            pub type EN_LV_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `HW_TRIG_EN` reader - set to enable hardware trigger from moto system. NOTE: when sw_preset is enabled, this bit will not take effert"]
            pub type HW_TRIG_EN_R = crate::BitReader;
            #[doc = "Field `HW_TRIG_EN` writer - set to enable hardware trigger from moto system. NOTE: when sw_preset is enabled, this bit will not take effert"]
            pub type HW_TRIG_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:7 - No description avaiable"]
                #[inline(always)]
                pub fn pga_sel(&self) -> PGA_SEL_R {
                    PGA_SEL_R::new((self.bits & 0xff) as u8)
                }
                #[doc = "Bits 16:17 - No description avaiable"]
                #[inline(always)]
                pub fn isel(&self) -> ISEL_R {
                    ISEL_R::new(((self.bits >> 16) & 3) as u8)
                }
                #[doc = "Bits 24:25 - No description avaiable"]
                #[inline(always)]
                pub fn opaout_sel(&self) -> OPAOUT_SEL_R {
                    OPAOUT_SEL_R::new(((self.bits >> 24) & 3) as u8)
                }
                #[doc = "Bit 29 - No description avaiable"]
                #[inline(always)]
                pub fn vbypass_lv(&self) -> VBYPASS_LV_R {
                    VBYPASS_LV_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 30 - No description avaiable"]
                #[inline(always)]
                pub fn en_lv(&self) -> EN_LV_R {
                    EN_LV_R::new(((self.bits >> 30) & 1) != 0)
                }
                #[doc = "Bit 31 - set to enable hardware trigger from moto system. NOTE: when sw_preset is enabled, this bit will not take effert"]
                #[inline(always)]
                pub fn hw_trig_en(&self) -> HW_TRIG_EN_R {
                    HW_TRIG_EN_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn pga_sel(&mut self) -> PGA_SEL_W<CFG1_SPEC> {
                    PGA_SEL_W::new(self, 0)
                }
                #[doc = "Bits 16:17 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn isel(&mut self) -> ISEL_W<CFG1_SPEC> {
                    ISEL_W::new(self, 16)
                }
                #[doc = "Bits 24:25 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn opaout_sel(&mut self) -> OPAOUT_SEL_W<CFG1_SPEC> {
                    OPAOUT_SEL_W::new(self, 24)
                }
                #[doc = "Bit 29 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn vbypass_lv(&mut self) -> VBYPASS_LV_W<CFG1_SPEC> {
                    VBYPASS_LV_W::new(self, 29)
                }
                #[doc = "Bit 30 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn en_lv(&mut self) -> EN_LV_W<CFG1_SPEC> {
                    EN_LV_W::new(self, 30)
                }
                #[doc = "Bit 31 - set to enable hardware trigger from moto system. NOTE: when sw_preset is enabled, this bit will not take effert"]
                #[inline(always)]
                #[must_use]
                pub fn hw_trig_en(&mut self) -> HW_TRIG_EN_W<CFG1_SPEC> {
                    HW_TRIG_EN_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CFG1_SPEC;
            impl crate::RegisterSpec for CFG1_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cfg1::R`](R) reader structure"]
            impl crate::Readable for CFG1_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cfg1::W`](W) writer structure"]
            impl crate::Writable for CFG1_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets cfg1 to value 0"]
            impl crate::Resettable for CFG1_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "cfg2 (rw) register accessor: No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg2`]
module"]
        pub type CFG2 = crate::Reg<cfg2::CFG2_SPEC>;
        #[doc = "No description avaiable"]
        pub mod cfg2 {
            #[doc = "Register `cfg2` reader"]
            pub type R = crate::R<CFG2_SPEC>;
            #[doc = "Register `cfg2` writer"]
            pub type W = crate::W<CFG2_SPEC>;
            #[doc = "Field `CHANNEL` reader - No description avaiable"]
            pub type CHANNEL_R = crate::FieldReader;
            #[doc = "Field `CHANNEL` writer - No description avaiable"]
            pub type CHANNEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            impl R {
                #[doc = "Bits 24:26 - No description avaiable"]
                #[inline(always)]
                pub fn channel(&self) -> CHANNEL_R {
                    CHANNEL_R::new(((self.bits >> 24) & 7) as u8)
                }
            }
            impl W {
                #[doc = "Bits 24:26 - No description avaiable"]
                #[inline(always)]
                #[must_use]
                pub fn channel(&mut self) -> CHANNEL_W<CFG2_SPEC> {
                    CHANNEL_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "No description avaiable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CFG2_SPEC;
            impl crate::RegisterSpec for CFG2_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cfg2::R`](R) reader structure"]
            impl crate::Readable for CFG2_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cfg2::W`](W) writer structure"]
            impl crate::Writable for CFG2_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets cfg2 to value 0"]
            impl crate::Resettable for CFG2_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "OPAMP1"]
pub struct OPAMP1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for OPAMP1 {}
impl OPAMP1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const opamp0::RegisterBlock = 0xf30a_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const opamp0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for OPAMP1 {
    type Target = opamp0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for OPAMP1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("OPAMP1").finish()
    }
}
#[doc = "OPAMP1"]
pub use self::opamp0 as opamp1;
#[doc = "ACMP"]
pub struct ACMP {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for ACMP {}
impl ACMP {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const acmp::RegisterBlock = 0xf30b_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const acmp::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for ACMP {
    type Target = acmp::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for ACMP {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("ACMP").finish()
    }
}
#[doc = "ACMP"]
pub mod acmp {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        channel: (),
    }
    impl RegisterBlock {
        #[doc = "0x00..0x70 - no description available"]
        #[inline(always)]
        pub const fn channel(&self, n: usize) -> &CHANNEL {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe { &*(self as *const Self).cast::<u8>().add(0).add(32 * n).cast() }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x70 - no description available"]
        #[inline(always)]
        pub fn channel_iter(&self) -> impl Iterator<Item = &CHANNEL> {
            (0..4).map(move |n| unsafe {
                &*(self as *const Self).cast::<u8>().add(0).add(32 * n).cast()
            })
        }
        #[doc = "0x00..0x1c - no description available"]
        #[inline(always)]
        pub const fn channelchn0(&self) -> &CHANNEL {
            self.channel(0)
        }
        #[doc = "0x20..0x3c - no description available"]
        #[inline(always)]
        pub const fn channelchn1(&self) -> &CHANNEL {
            self.channel(1)
        }
        #[doc = "0x40..0x5c - no description available"]
        #[inline(always)]
        pub const fn channelchn2(&self) -> &CHANNEL {
            self.channel(2)
        }
        #[doc = "0x60..0x7c - no description available"]
        #[inline(always)]
        pub const fn channelchn3(&self) -> &CHANNEL {
            self.channel(3)
        }
    }
    #[doc = "no description available"]
    pub use self::channel::CHANNEL;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod channel {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct CHANNEL {
            cfg: CFG,
            daccfg: DACCFG,
            _reserved2: [u8; 0x08],
            sr: SR,
            irqen: IRQEN,
            dmaen: DMAEN,
        }
        impl CHANNEL {
            #[doc = "0x00 - Configure Register"]
            #[inline(always)]
            pub const fn cfg(&self) -> &CFG {
                &self.cfg
            }
            #[doc = "0x04 - DAC configure register"]
            #[inline(always)]
            pub const fn daccfg(&self) -> &DACCFG {
                &self.daccfg
            }
            #[doc = "0x10 - Status register"]
            #[inline(always)]
            pub const fn sr(&self) -> &SR {
                &self.sr
            }
            #[doc = "0x14 - Interrupt request enable register"]
            #[inline(always)]
            pub const fn irqen(&self) -> &IRQEN {
                &self.irqen
            }
            #[doc = "0x18 - DMA request enable register"]
            #[inline(always)]
            pub const fn dmaen(&self) -> &DMAEN {
                &self.dmaen
            }
        }
        #[doc = "cfg (rw) register accessor: Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub type CFG = crate::Reg<cfg::CFG_SPEC>;
        #[doc = "Configure Register"]
        pub mod cfg {
            #[doc = "Register `cfg` reader"]
            pub type R = crate::R<CFG_SPEC>;
            #[doc = "Register `cfg` writer"]
            pub type W = crate::W<CFG_SPEC>;
            #[doc = "Field `FLTLEN` reader - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle."]
            pub type FLTLEN_R = crate::FieldReader<u16>;
            #[doc = "Field `FLTLEN` writer - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle."]
            pub type FLTLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
            #[doc = "Field `SYNCEN` reader - This bit enable the comparator output synchronization. 0: ACMP output not synchronized with ACMP clock. 1: ACMP output synchronized with ACMP clock."]
            pub type SYNCEN_R = crate::BitReader;
            #[doc = "Field `SYNCEN` writer - This bit enable the comparator output synchronization. 0: ACMP output not synchronized with ACMP clock. 1: ACMP output synchronized with ACMP clock."]
            pub type SYNCEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FLTMODE` reader - This bitfield define the ACMP output digital filter mode: 000-bypass 100-change immediately; 101-change after filter; 110-stalbe low; 111-stable high"]
            pub type FLTMODE_R = crate::FieldReader;
            #[doc = "Field `FLTMODE` writer - This bitfield define the ACMP output digital filter mode: 000-bypass 100-change immediately; 101-change after filter; 110-stalbe low; 111-stable high"]
            pub type FLTMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `OPOL` reader - The output polarity control bit. 0: The ACMP output remain un-changed. 1: The ACMP output is inverted."]
            pub type OPOL_R = crate::BitReader;
            #[doc = "Field `OPOL` writer - The output polarity control bit. 0: The ACMP output remain un-changed. 1: The ACMP output is inverted."]
            pub type OPOL_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WINEN` reader - This bit enable the comparator window mode. 0: Window mode is disabled 1: Window mode is enabled"]
            pub type WINEN_R = crate::BitReader;
            #[doc = "Field `WINEN` writer - This bit enable the comparator window mode. 0: Window mode is disabled 1: Window mode is enabled"]
            pub type WINEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FLTBYPS` reader - This bit bypass the comparator output digital filter. 0: The ACMP output need pass digital filter 1: The ACMP output digital filter is bypassed."]
            pub type FLTBYPS_R = crate::BitReader;
            #[doc = "Field `FLTBYPS` writer - This bit bypass the comparator output digital filter. 0: The ACMP output need pass digital filter 1: The ACMP output digital filter is bypassed."]
            pub type FLTBYPS_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `CMPOEN` reader - This bit enable the comparator output on pad. 0: ACMP output disabled 1: ACMP output enabled"]
            pub type CMPOEN_R = crate::BitReader;
            #[doc = "Field `CMPOEN` writer - This bit enable the comparator output on pad. 0: ACMP output disabled 1: ACMP output enabled"]
            pub type CMPOEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PINSEL` reader - MIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
            pub type PINSEL_R = crate::FieldReader;
            #[doc = "Field `PINSEL` writer - MIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
            pub type PINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `MINSEL` reader - PIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
            pub type MINSEL_R = crate::FieldReader;
            #[doc = "Field `MINSEL` writer - PIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
            pub type MINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `CMPEN` reader - This bit enable the comparator. 0: ACMP disabled 1: ACMP enabled"]
            pub type CMPEN_R = crate::BitReader;
            #[doc = "Field `CMPEN` writer - This bit enable the comparator. 0: ACMP disabled 1: ACMP enabled"]
            pub type CMPEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `HPMODE` reader - This bit enable the comparator high performance mode. 0: HP mode disabled 1: HP mode enabled"]
            pub type HPMODE_R = crate::BitReader;
            #[doc = "Field `HPMODE` writer - This bit enable the comparator high performance mode. 0: HP mode disabled 1: HP mode enabled"]
            pub type HPMODE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DACEN` reader - This bit enable the comparator internal DAC 0: DAC disabled 1: DAC enabled"]
            pub type DACEN_R = crate::BitReader;
            #[doc = "Field `DACEN` writer - This bit enable the comparator internal DAC 0: DAC disabled 1: DAC enabled"]
            pub type DACEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `HYST` reader - This bitfield configure the comparator hysteresis. 00: Hysteresis level 0 01: Hysteresis level 1 10: Hysteresis level 2 11: Hysteresis level 3"]
            pub type HYST_R = crate::FieldReader;
            #[doc = "Field `HYST` writer - This bitfield configure the comparator hysteresis. 00: Hysteresis level 0 01: Hysteresis level 1 10: Hysteresis level 2 11: Hysteresis level 3"]
            pub type HYST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            impl R {
                #[doc = "Bits 0:11 - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle."]
                #[inline(always)]
                pub fn fltlen(&self) -> FLTLEN_R {
                    FLTLEN_R::new((self.bits & 0x0fff) as u16)
                }
                #[doc = "Bit 12 - This bit enable the comparator output synchronization. 0: ACMP output not synchronized with ACMP clock. 1: ACMP output synchronized with ACMP clock."]
                #[inline(always)]
                pub fn syncen(&self) -> SYNCEN_R {
                    SYNCEN_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bits 13:15 - This bitfield define the ACMP output digital filter mode: 000-bypass 100-change immediately; 101-change after filter; 110-stalbe low; 111-stable high"]
                #[inline(always)]
                pub fn fltmode(&self) -> FLTMODE_R {
                    FLTMODE_R::new(((self.bits >> 13) & 7) as u8)
                }
                #[doc = "Bit 16 - The output polarity control bit. 0: The ACMP output remain un-changed. 1: The ACMP output is inverted."]
                #[inline(always)]
                pub fn opol(&self) -> OPOL_R {
                    OPOL_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 17 - This bit enable the comparator window mode. 0: Window mode is disabled 1: Window mode is enabled"]
                #[inline(always)]
                pub fn winen(&self) -> WINEN_R {
                    WINEN_R::new(((self.bits >> 17) & 1) != 0)
                }
                #[doc = "Bit 18 - This bit bypass the comparator output digital filter. 0: The ACMP output need pass digital filter 1: The ACMP output digital filter is bypassed."]
                #[inline(always)]
                pub fn fltbyps(&self) -> FLTBYPS_R {
                    FLTBYPS_R::new(((self.bits >> 18) & 1) != 0)
                }
                #[doc = "Bit 19 - This bit enable the comparator output on pad. 0: ACMP output disabled 1: ACMP output enabled"]
                #[inline(always)]
                pub fn cmpoen(&self) -> CMPOEN_R {
                    CMPOEN_R::new(((self.bits >> 19) & 1) != 0)
                }
                #[doc = "Bits 20:22 - MIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
                #[inline(always)]
                pub fn pinsel(&self) -> PINSEL_R {
                    PINSEL_R::new(((self.bits >> 20) & 7) as u8)
                }
                #[doc = "Bits 24:26 - PIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
                #[inline(always)]
                pub fn minsel(&self) -> MINSEL_R {
                    MINSEL_R::new(((self.bits >> 24) & 7) as u8)
                }
                #[doc = "Bit 27 - This bit enable the comparator. 0: ACMP disabled 1: ACMP enabled"]
                #[inline(always)]
                pub fn cmpen(&self) -> CMPEN_R {
                    CMPEN_R::new(((self.bits >> 27) & 1) != 0)
                }
                #[doc = "Bit 28 - This bit enable the comparator high performance mode. 0: HP mode disabled 1: HP mode enabled"]
                #[inline(always)]
                pub fn hpmode(&self) -> HPMODE_R {
                    HPMODE_R::new(((self.bits >> 28) & 1) != 0)
                }
                #[doc = "Bit 29 - This bit enable the comparator internal DAC 0: DAC disabled 1: DAC enabled"]
                #[inline(always)]
                pub fn dacen(&self) -> DACEN_R {
                    DACEN_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bits 30:31 - This bitfield configure the comparator hysteresis. 00: Hysteresis level 0 01: Hysteresis level 1 10: Hysteresis level 2 11: Hysteresis level 3"]
                #[inline(always)]
                pub fn hyst(&self) -> HYST_R {
                    HYST_R::new(((self.bits >> 30) & 3) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:11 - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle."]
                #[inline(always)]
                #[must_use]
                pub fn fltlen(&mut self) -> FLTLEN_W<CFG_SPEC> {
                    FLTLEN_W::new(self, 0)
                }
                #[doc = "Bit 12 - This bit enable the comparator output synchronization. 0: ACMP output not synchronized with ACMP clock. 1: ACMP output synchronized with ACMP clock."]
                #[inline(always)]
                #[must_use]
                pub fn syncen(&mut self) -> SYNCEN_W<CFG_SPEC> {
                    SYNCEN_W::new(self, 12)
                }
                #[doc = "Bits 13:15 - This bitfield define the ACMP output digital filter mode: 000-bypass 100-change immediately; 101-change after filter; 110-stalbe low; 111-stable high"]
                #[inline(always)]
                #[must_use]
                pub fn fltmode(&mut self) -> FLTMODE_W<CFG_SPEC> {
                    FLTMODE_W::new(self, 13)
                }
                #[doc = "Bit 16 - The output polarity control bit. 0: The ACMP output remain un-changed. 1: The ACMP output is inverted."]
                #[inline(always)]
                #[must_use]
                pub fn opol(&mut self) -> OPOL_W<CFG_SPEC> {
                    OPOL_W::new(self, 16)
                }
                #[doc = "Bit 17 - This bit enable the comparator window mode. 0: Window mode is disabled 1: Window mode is enabled"]
                #[inline(always)]
                #[must_use]
                pub fn winen(&mut self) -> WINEN_W<CFG_SPEC> {
                    WINEN_W::new(self, 17)
                }
                #[doc = "Bit 18 - This bit bypass the comparator output digital filter. 0: The ACMP output need pass digital filter 1: The ACMP output digital filter is bypassed."]
                #[inline(always)]
                #[must_use]
                pub fn fltbyps(&mut self) -> FLTBYPS_W<CFG_SPEC> {
                    FLTBYPS_W::new(self, 18)
                }
                #[doc = "Bit 19 - This bit enable the comparator output on pad. 0: ACMP output disabled 1: ACMP output enabled"]
                #[inline(always)]
                #[must_use]
                pub fn cmpoen(&mut self) -> CMPOEN_W<CFG_SPEC> {
                    CMPOEN_W::new(self, 19)
                }
                #[doc = "Bits 20:22 - MIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
                #[inline(always)]
                #[must_use]
                pub fn pinsel(&mut self) -> PINSEL_W<CFG_SPEC> {
                    PINSEL_W::new(self, 20)
                }
                #[doc = "Bits 24:26 - PIN select, from pad_ai_acmp\\[7:1\\]
and dac_out"]
                #[inline(always)]
                #[must_use]
                pub fn minsel(&mut self) -> MINSEL_W<CFG_SPEC> {
                    MINSEL_W::new(self, 24)
                }
                #[doc = "Bit 27 - This bit enable the comparator. 0: ACMP disabled 1: ACMP enabled"]
                #[inline(always)]
                #[must_use]
                pub fn cmpen(&mut self) -> CMPEN_W<CFG_SPEC> {
                    CMPEN_W::new(self, 27)
                }
                #[doc = "Bit 28 - This bit enable the comparator high performance mode. 0: HP mode disabled 1: HP mode enabled"]
                #[inline(always)]
                #[must_use]
                pub fn hpmode(&mut self) -> HPMODE_W<CFG_SPEC> {
                    HPMODE_W::new(self, 28)
                }
                #[doc = "Bit 29 - This bit enable the comparator internal DAC 0: DAC disabled 1: DAC enabled"]
                #[inline(always)]
                #[must_use]
                pub fn dacen(&mut self) -> DACEN_W<CFG_SPEC> {
                    DACEN_W::new(self, 29)
                }
                #[doc = "Bits 30:31 - This bitfield configure the comparator hysteresis. 00: Hysteresis level 0 01: Hysteresis level 1 10: Hysteresis level 2 11: Hysteresis level 3"]
                #[inline(always)]
                #[must_use]
                pub fn hyst(&mut self) -> HYST_W<CFG_SPEC> {
                    HYST_W::new(self, 30)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CFG_SPEC;
            impl crate::RegisterSpec for CFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
            impl crate::Readable for CFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
            impl crate::Writable for CFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets cfg to value 0"]
            impl crate::Resettable for CFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "daccfg (rw) register accessor: DAC configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daccfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daccfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@daccfg`]
module"]
        pub type DACCFG = crate::Reg<daccfg::DACCFG_SPEC>;
        #[doc = "DAC configure register"]
        pub mod daccfg {
            #[doc = "Register `daccfg` reader"]
            pub type R = crate::R<DACCFG_SPEC>;
            #[doc = "Register `daccfg` writer"]
            pub type W = crate::W<DACCFG_SPEC>;
            #[doc = "Field `DACCFG` reader - 8bit DAC digital value"]
            pub type DACCFG_R = crate::FieldReader;
            #[doc = "Field `DACCFG` writer - 8bit DAC digital value"]
            pub type DACCFG_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bits 0:7 - 8bit DAC digital value"]
                #[inline(always)]
                pub fn daccfg(&self) -> DACCFG_R {
                    DACCFG_R::new((self.bits & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - 8bit DAC digital value"]
                #[inline(always)]
                #[must_use]
                pub fn daccfg(&mut self) -> DACCFG_W<DACCFG_SPEC> {
                    DACCFG_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "DAC configure register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`daccfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`daccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct DACCFG_SPEC;
            impl crate::RegisterSpec for DACCFG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`daccfg::R`](R) reader structure"]
            impl crate::Readable for DACCFG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`daccfg::W`](W) writer structure"]
            impl crate::Writable for DACCFG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets daccfg to value 0"]
            impl crate::Resettable for DACCFG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "sr (rw) register accessor: Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
module"]
        pub type SR = crate::Reg<sr::SR_SPEC>;
        #[doc = "Status register"]
        pub mod sr {
            #[doc = "Register `sr` reader"]
            pub type R = crate::R<SR_SPEC>;
            #[doc = "Register `sr` writer"]
            pub type W = crate::W<SR_SPEC>;
            #[doc = "Field `REDGF` reader - Output rising edge flag. Write 1 to clear this flag."]
            pub type REDGF_R = crate::BitReader;
            #[doc = "Field `REDGF` writer - Output rising edge flag. Write 1 to clear this flag."]
            pub type REDGF_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FEDGF` reader - Output falling edge flag. Write 1 to clear this flag."]
            pub type FEDGF_R = crate::BitReader;
            #[doc = "Field `FEDGF` writer - Output falling edge flag. Write 1 to clear this flag."]
            pub type FEDGF_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Output rising edge flag. Write 1 to clear this flag."]
                #[inline(always)]
                pub fn redgf(&self) -> REDGF_R {
                    REDGF_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - Output falling edge flag. Write 1 to clear this flag."]
                #[inline(always)]
                pub fn fedgf(&self) -> FEDGF_R {
                    FEDGF_R::new(((self.bits >> 1) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Output rising edge flag. Write 1 to clear this flag."]
                #[inline(always)]
                #[must_use]
                pub fn redgf(&mut self) -> REDGF_W<SR_SPEC> {
                    REDGF_W::new(self, 0)
                }
                #[doc = "Bit 1 - Output falling edge flag. Write 1 to clear this flag."]
                #[inline(always)]
                #[must_use]
                pub fn fedgf(&mut self) -> FEDGF_W<SR_SPEC> {
                    FEDGF_W::new(self, 1)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SR_SPEC;
            impl crate::RegisterSpec for SR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`sr::R`](R) reader structure"]
            impl crate::Readable for SR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
            impl crate::Writable for SR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets sr to value 0"]
            impl crate::Resettable for SR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "irqen (rw) register accessor: Interrupt request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irqen`]
module"]
        pub type IRQEN = crate::Reg<irqen::IRQEN_SPEC>;
        #[doc = "Interrupt request enable register"]
        pub mod irqen {
            #[doc = "Register `irqen` reader"]
            pub type R = crate::R<IRQEN_SPEC>;
            #[doc = "Register `irqen` writer"]
            pub type W = crate::W<IRQEN_SPEC>;
            #[doc = "Field `REDGEN` reader - Output rising edge flag interrupt enable bit."]
            pub type REDGEN_R = crate::BitReader;
            #[doc = "Field `REDGEN` writer - Output rising edge flag interrupt enable bit."]
            pub type REDGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FEDGEN` reader - Output falling edge flag interrupt enable bit."]
            pub type FEDGEN_R = crate::BitReader;
            #[doc = "Field `FEDGEN` writer - Output falling edge flag interrupt enable bit."]
            pub type FEDGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Output rising edge flag interrupt enable bit."]
                #[inline(always)]
                pub fn redgen(&self) -> REDGEN_R {
                    REDGEN_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - Output falling edge flag interrupt enable bit."]
                #[inline(always)]
                pub fn fedgen(&self) -> FEDGEN_R {
                    FEDGEN_R::new(((self.bits >> 1) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Output rising edge flag interrupt enable bit."]
                #[inline(always)]
                #[must_use]
                pub fn redgen(&mut self) -> REDGEN_W<IRQEN_SPEC> {
                    REDGEN_W::new(self, 0)
                }
                #[doc = "Bit 1 - Output falling edge flag interrupt enable bit."]
                #[inline(always)]
                #[must_use]
                pub fn fedgen(&mut self) -> FEDGEN_W<IRQEN_SPEC> {
                    FEDGEN_W::new(self, 1)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Interrupt request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irqen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irqen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct IRQEN_SPEC;
            impl crate::RegisterSpec for IRQEN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`irqen::R`](R) reader structure"]
            impl crate::Readable for IRQEN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`irqen::W`](W) writer structure"]
            impl crate::Writable for IRQEN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets irqen to value 0"]
            impl crate::Resettable for IRQEN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "dmaen (rw) register accessor: DMA request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaen`]
module"]
        pub type DMAEN = crate::Reg<dmaen::DMAEN_SPEC>;
        #[doc = "DMA request enable register"]
        pub mod dmaen {
            #[doc = "Register `dmaen` reader"]
            pub type R = crate::R<DMAEN_SPEC>;
            #[doc = "Register `dmaen` writer"]
            pub type W = crate::W<DMAEN_SPEC>;
            #[doc = "Field `REDGEN` reader - Output rising edge flag DMA request enable bit."]
            pub type REDGEN_R = crate::BitReader;
            #[doc = "Field `REDGEN` writer - Output rising edge flag DMA request enable bit."]
            pub type REDGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FEDGEN` reader - Output falling edge flag DMA request enable bit."]
            pub type FEDGEN_R = crate::BitReader;
            #[doc = "Field `FEDGEN` writer - Output falling edge flag DMA request enable bit."]
            pub type FEDGEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Output rising edge flag DMA request enable bit."]
                #[inline(always)]
                pub fn redgen(&self) -> REDGEN_R {
                    REDGEN_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 1 - Output falling edge flag DMA request enable bit."]
                #[inline(always)]
                pub fn fedgen(&self) -> FEDGEN_R {
                    FEDGEN_R::new(((self.bits >> 1) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Output rising edge flag DMA request enable bit."]
                #[inline(always)]
                #[must_use]
                pub fn redgen(&mut self) -> REDGEN_W<DMAEN_SPEC> {
                    REDGEN_W::new(self, 0)
                }
                #[doc = "Bit 1 - Output falling edge flag DMA request enable bit."]
                #[inline(always)]
                #[must_use]
                pub fn fedgen(&mut self) -> FEDGEN_W<DMAEN_SPEC> {
                    FEDGEN_W::new(self, 1)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "DMA request enable register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct DMAEN_SPEC;
            impl crate::RegisterSpec for DMAEN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`dmaen::R`](R) reader structure"]
            impl crate::Readable for DMAEN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`dmaen::W`](W) writer structure"]
            impl crate::Writable for DMAEN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets dmaen to value 0"]
            impl crate::Resettable for DMAEN_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "SYSCTL"]
pub struct SYSCTL {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for SYSCTL {}
impl SYSCTL {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const sysctl::RegisterBlock = 0xf400_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const sysctl::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for SYSCTL {
    type Target = sysctl::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for SYSCTL {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SYSCTL").finish()
    }
}
#[doc = "SYSCTL"]
pub mod sysctl {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        resource: [RESOURCE; 113],
        _reserved1: [u8; 0x063c],
        group0: [GROUP0; 2],
        _reserved2: [u8; 0xe0],
        affiliate: [AFFILIATE; 1],
        _reserved3: [u8; 0x10],
        retention: [RETENTION; 1],
        _reserved4: [u8; 0x06d0],
        power: [POWER; 1],
        _reserved5: [u8; 0x03ec],
        reset: [RESET; 2],
        _reserved6: [u8; 0x03e0],
        clock_cpu: [CLOCK_CPU; 1],
        clock: [CLOCK; 36],
        _reserved8: [u8; 0x036c],
        adcclk: [ADCCLK; 2],
        dacclk: [DACCLK; 2],
        _reserved10: [u8; 0x03f0],
        global00: GLOBAL00,
        _reserved11: [u8; 0x03fc],
        monitor: (),
        _reserved12: [u8; 0x0400],
        cpu: [CPU; 1],
    }
    impl RegisterBlock {
        #[doc = "0x00..0x1c4 - no description available"]
        #[inline(always)]
        pub const fn resource(&self, n: usize) -> &RESOURCE {
            &self.resource[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0x1c4 - no description available"]
        #[inline(always)]
        pub fn resource_iter(&self) -> impl Iterator<Item = &RESOURCE> {
            self.resource.iter()
        }
        #[doc = "0x00 - no description available"]
        #[inline(always)]
        pub const fn resourcecpu0(&self) -> &RESOURCE {
            self.resource(0)
        }
        #[doc = "0x04 - no description available"]
        #[inline(always)]
        pub const fn resourcecpx0(&self) -> &RESOURCE {
            self.resource(1)
        }
        #[doc = "0x08 - no description available"]
        #[inline(always)]
        pub const fn resourcepow_cpu0(&self) -> &RESOURCE {
            self.resource(2)
        }
        #[doc = "0x0c - no description available"]
        #[inline(always)]
        pub const fn resourcerst_soc(&self) -> &RESOURCE {
            self.resource(3)
        }
        #[doc = "0x10 - no description available"]
        #[inline(always)]
        pub const fn resourcerst_cpu0(&self) -> &RESOURCE {
            self.resource(4)
        }
        #[doc = "0x14 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_xtal(&self) -> &RESOURCE {
            self.resource(5)
        }
        #[doc = "0x18 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_pll0(&self) -> &RESOURCE {
            self.resource(6)
        }
        #[doc = "0x1c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_clk0_pll0(&self) -> &RESOURCE {
            self.resource(7)
        }
        #[doc = "0x20 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_clk1_pll0(&self) -> &RESOURCE {
            self.resource(8)
        }
        #[doc = "0x24 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_clk2_pll0(&self) -> &RESOURCE {
            self.resource(9)
        }
        #[doc = "0x28 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_pll1(&self) -> &RESOURCE {
            self.resource(10)
        }
        #[doc = "0x2c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_clk0_pll1(&self) -> &RESOURCE {
            self.resource(11)
        }
        #[doc = "0x30 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_clk1_pll1(&self) -> &RESOURCE {
            self.resource(12)
        }
        #[doc = "0x34 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_clk2_pll1(&self) -> &RESOURCE {
            self.resource(13)
        }
        #[doc = "0x38 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_clk3_pll1(&self) -> &RESOURCE {
            self.resource(14)
        }
        #[doc = "0x3c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_pll0_ref(&self) -> &RESOURCE {
            self.resource(15)
        }
        #[doc = "0x40 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_src_pll1_ref(&self) -> &RESOURCE {
            self.resource(16)
        }
        #[doc = "0x44 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_cpu0(&self) -> &RESOURCE {
            self.resource(17)
        }
        #[doc = "0x48 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_mct0(&self) -> &RESOURCE {
            self.resource(18)
        }
        #[doc = "0x4c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_can0(&self) -> &RESOURCE {
            self.resource(19)
        }
        #[doc = "0x50 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_can1(&self) -> &RESOURCE {
            self.resource(20)
        }
        #[doc = "0x54 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_can2(&self) -> &RESOURCE {
            self.resource(21)
        }
        #[doc = "0x58 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_can3(&self) -> &RESOURCE {
            self.resource(22)
        }
        #[doc = "0x5c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_lin0(&self) -> &RESOURCE {
            self.resource(23)
        }
        #[doc = "0x60 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_lin1(&self) -> &RESOURCE {
            self.resource(24)
        }
        #[doc = "0x64 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_lin2(&self) -> &RESOURCE {
            self.resource(25)
        }
        #[doc = "0x68 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_lin3(&self) -> &RESOURCE {
            self.resource(26)
        }
        #[doc = "0x6c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_tmr0(&self) -> &RESOURCE {
            self.resource(27)
        }
        #[doc = "0x70 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_tmr1(&self) -> &RESOURCE {
            self.resource(28)
        }
        #[doc = "0x74 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_tmr2(&self) -> &RESOURCE {
            self.resource(29)
        }
        #[doc = "0x78 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_tmr3(&self) -> &RESOURCE {
            self.resource(30)
        }
        #[doc = "0x7c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_i2c0(&self) -> &RESOURCE {
            self.resource(31)
        }
        #[doc = "0x80 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_i2c1(&self) -> &RESOURCE {
            self.resource(32)
        }
        #[doc = "0x84 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_i2c2(&self) -> &RESOURCE {
            self.resource(33)
        }
        #[doc = "0x88 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_i2c3(&self) -> &RESOURCE {
            self.resource(34)
        }
        #[doc = "0x8c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_spi0(&self) -> &RESOURCE {
            self.resource(35)
        }
        #[doc = "0x90 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_spi1(&self) -> &RESOURCE {
            self.resource(36)
        }
        #[doc = "0x94 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_spi2(&self) -> &RESOURCE {
            self.resource(37)
        }
        #[doc = "0x98 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_spi3(&self) -> &RESOURCE {
            self.resource(38)
        }
        #[doc = "0x9c - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt0(&self) -> &RESOURCE {
            self.resource(39)
        }
        #[doc = "0xa0 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt1(&self) -> &RESOURCE {
            self.resource(40)
        }
        #[doc = "0xa4 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt2(&self) -> &RESOURCE {
            self.resource(41)
        }
        #[doc = "0xa8 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt3(&self) -> &RESOURCE {
            self.resource(42)
        }
        #[doc = "0xac - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt4(&self) -> &RESOURCE {
            self.resource(43)
        }
        #[doc = "0xb0 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt5(&self) -> &RESOURCE {
            self.resource(44)
        }
        #[doc = "0xb4 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt6(&self) -> &RESOURCE {
            self.resource(45)
        }
        #[doc = "0xb8 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_urt7(&self) -> &RESOURCE {
            self.resource(46)
        }
        #[doc = "0xbc - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_xpi0(&self) -> &RESOURCE {
            self.resource(47)
        }
        #[doc = "0xc0 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_ana0(&self) -> &RESOURCE {
            self.resource(48)
        }
        #[doc = "0xc4 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_ana1(&self) -> &RESOURCE {
            self.resource(49)
        }
        #[doc = "0xc8 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_ana2(&self) -> &RESOURCE {
            self.resource(50)
        }
        #[doc = "0xcc - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_ana3(&self) -> &RESOURCE {
            self.resource(51)
        }
        #[doc = "0xd0 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_ref0(&self) -> &RESOURCE {
            self.resource(52)
        }
        #[doc = "0xd4 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_ref1(&self) -> &RESOURCE {
            self.resource(53)
        }
        #[doc = "0xd8 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_adc0(&self) -> &RESOURCE {
            self.resource(54)
        }
        #[doc = "0xdc - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_adc1(&self) -> &RESOURCE {
            self.resource(55)
        }
        #[doc = "0xe0 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_dac0(&self) -> &RESOURCE {
            self.resource(56)
        }
        #[doc = "0xe4 - no description available"]
        #[inline(always)]
        pub const fn resourceclk_top_dac1(&self) -> &RESOURCE {
            self.resource(57)
        }
        #[doc = "0xe8 - no description available"]
        #[inline(always)]
        pub const fn resourceahb0(&self) -> &RESOURCE {
            self.resource(58)
        }
        #[doc = "0xec - no description available"]
        #[inline(always)]
        pub const fn resourcelmm0(&self) -> &RESOURCE {
            self.resource(59)
        }
        #[doc = "0xf0 - no description available"]
        #[inline(always)]
        pub const fn resourcemct0(&self) -> &RESOURCE {
            self.resource(60)
        }
        #[doc = "0xf4 - no description available"]
        #[inline(always)]
        pub const fn resourcerom0(&self) -> &RESOURCE {
            self.resource(61)
        }
        #[doc = "0xf8 - no description available"]
        #[inline(always)]
        pub const fn resourcecan0(&self) -> &RESOURCE {
            self.resource(62)
        }
        #[doc = "0xfc - no description available"]
        #[inline(always)]
        pub const fn resourcecan1(&self) -> &RESOURCE {
            self.resource(63)
        }
        #[doc = "0x100 - no description available"]
        #[inline(always)]
        pub const fn resourcecan2(&self) -> &RESOURCE {
            self.resource(64)
        }
        #[doc = "0x104 - no description available"]
        #[inline(always)]
        pub const fn resourcecan3(&self) -> &RESOURCE {
            self.resource(65)
        }
        #[doc = "0x108 - no description available"]
        #[inline(always)]
        pub const fn resourceptpc(&self) -> &RESOURCE {
            self.resource(66)
        }
        #[doc = "0x10c - no description available"]
        #[inline(always)]
        pub const fn resourcelin0(&self) -> &RESOURCE {
            self.resource(67)
        }
        #[doc = "0x110 - no description available"]
        #[inline(always)]
        pub const fn resourcelin1(&self) -> &RESOURCE {
            self.resource(68)
        }
        #[doc = "0x114 - no description available"]
        #[inline(always)]
        pub const fn resourcelin2(&self) -> &RESOURCE {
            self.resource(69)
        }
        #[doc = "0x118 - no description available"]
        #[inline(always)]
        pub const fn resourcelin3(&self) -> &RESOURCE {
            self.resource(70)
        }
        #[doc = "0x11c - no description available"]
        #[inline(always)]
        pub const fn resourcetmr0(&self) -> &RESOURCE {
            self.resource(71)
        }
        #[doc = "0x120 - no description available"]
        #[inline(always)]
        pub const fn resourcetmr1(&self) -> &RESOURCE {
            self.resource(72)
        }
        #[doc = "0x124 - no description available"]
        #[inline(always)]
        pub const fn resourcetmr2(&self) -> &RESOURCE {
            self.resource(73)
        }
        #[doc = "0x128 - no description available"]
        #[inline(always)]
        pub const fn resourcetmr3(&self) -> &RESOURCE {
            self.resource(74)
        }
        #[doc = "0x12c - no description available"]
        #[inline(always)]
        pub const fn resourcei2c0(&self) -> &RESOURCE {
            self.resource(75)
        }
        #[doc = "0x130 - no description available"]
        #[inline(always)]
        pub const fn resourcei2c1(&self) -> &RESOURCE {
            self.resource(76)
        }
        #[doc = "0x134 - no description available"]
        #[inline(always)]
        pub const fn resourcei2c2(&self) -> &RESOURCE {
            self.resource(77)
        }
        #[doc = "0x138 - no description available"]
        #[inline(always)]
        pub const fn resourcei2c3(&self) -> &RESOURCE {
            self.resource(78)
        }
        #[doc = "0x13c - no description available"]
        #[inline(always)]
        pub const fn resourcespi0(&self) -> &RESOURCE {
            self.resource(79)
        }
        #[doc = "0x140 - no description available"]
        #[inline(always)]
        pub const fn resourcespi1(&self) -> &RESOURCE {
            self.resource(80)
        }
        #[doc = "0x144 - no description available"]
        #[inline(always)]
        pub const fn resourcespi2(&self) -> &RESOURCE {
            self.resource(81)
        }
        #[doc = "0x148 - no description available"]
        #[inline(always)]
        pub const fn resourcespi3(&self) -> &RESOURCE {
            self.resource(82)
        }
        #[doc = "0x14c - no description available"]
        #[inline(always)]
        pub const fn resourceurt0(&self) -> &RESOURCE {
            self.resource(83)
        }
        #[doc = "0x150 - no description available"]
        #[inline(always)]
        pub const fn resourceurt1(&self) -> &RESOURCE {
            self.resource(84)
        }
        #[doc = "0x154 - no description available"]
        #[inline(always)]
        pub const fn resourceurt2(&self) -> &RESOURCE {
            self.resource(85)
        }
        #[doc = "0x158 - no description available"]
        #[inline(always)]
        pub const fn resourceurt3(&self) -> &RESOURCE {
            self.resource(86)
        }
        #[doc = "0x15c - no description available"]
        #[inline(always)]
        pub const fn resourceurt4(&self) -> &RESOURCE {
            self.resource(87)
        }
        #[doc = "0x160 - no description available"]
        #[inline(always)]
        pub const fn resourceurt5(&self) -> &RESOURCE {
            self.resource(88)
        }
        #[doc = "0x164 - no description available"]
        #[inline(always)]
        pub const fn resourceurt6(&self) -> &RESOURCE {
            self.resource(89)
        }
        #[doc = "0x168 - no description available"]
        #[inline(always)]
        pub const fn resourceurt7(&self) -> &RESOURCE {
            self.resource(90)
        }
        #[doc = "0x16c - no description available"]
        #[inline(always)]
        pub const fn resourcewdg0(&self) -> &RESOURCE {
            self.resource(91)
        }
        #[doc = "0x170 - no description available"]
        #[inline(always)]
        pub const fn resourcewdg1(&self) -> &RESOURCE {
            self.resource(92)
        }
        #[doc = "0x174 - no description available"]
        #[inline(always)]
        pub const fn resourcembx0(&self) -> &RESOURCE {
            self.resource(93)
        }
        #[doc = "0x178 - no description available"]
        #[inline(always)]
        pub const fn resourcetsns(&self) -> &RESOURCE {
            self.resource(94)
        }
        #[doc = "0x17c - no description available"]
        #[inline(always)]
        pub const fn resourcecrc0(&self) -> &RESOURCE {
            self.resource(95)
        }
        #[doc = "0x180 - no description available"]
        #[inline(always)]
        pub const fn resourceadc0(&self) -> &RESOURCE {
            self.resource(96)
        }
        #[doc = "0x184 - no description available"]
        #[inline(always)]
        pub const fn resourceadc1(&self) -> &RESOURCE {
            self.resource(97)
        }
        #[doc = "0x188 - no description available"]
        #[inline(always)]
        pub const fn resourcedac0(&self) -> &RESOURCE {
            self.resource(98)
        }
        #[doc = "0x18c - no description available"]
        #[inline(always)]
        pub const fn resourcedac1(&self) -> &RESOURCE {
            self.resource(99)
        }
        #[doc = "0x190 - no description available"]
        #[inline(always)]
        pub const fn resourceacmp(&self) -> &RESOURCE {
            self.resource(100)
        }
        #[doc = "0x194 - no description available"]
        #[inline(always)]
        pub const fn resourceopa0(&self) -> &RESOURCE {
            self.resource(101)
        }
        #[doc = "0x198 - no description available"]
        #[inline(always)]
        pub const fn resourceopa1(&self) -> &RESOURCE {
            self.resource(102)
        }
        #[doc = "0x19c - no description available"]
        #[inline(always)]
        pub const fn resourcemot0(&self) -> &RESOURCE {
            self.resource(103)
        }
        #[doc = "0x1a0 - no description available"]
        #[inline(always)]
        pub const fn resourcerng0(&self) -> &RESOURCE {
            self.resource(104)
        }
        #[doc = "0x1a4 - no description available"]
        #[inline(always)]
        pub const fn resourcesdp0(&self) -> &RESOURCE {
            self.resource(105)
        }
        #[doc = "0x1a8 - no description available"]
        #[inline(always)]
        pub const fn resourcekman(&self) -> &RESOURCE {
            self.resource(106)
        }
        #[doc = "0x1ac - no description available"]
        #[inline(always)]
        pub const fn resourcegpio(&self) -> &RESOURCE {
            self.resource(107)
        }
        #[doc = "0x1b0 - no description available"]
        #[inline(always)]
        pub const fn resourcehdma(&self) -> &RESOURCE {
            self.resource(108)
        }
        #[doc = "0x1b4 - no description available"]
        #[inline(always)]
        pub const fn resourcexpi0(&self) -> &RESOURCE {
            self.resource(109)
        }
        #[doc = "0x1b8 - no description available"]
        #[inline(always)]
        pub const fn resourceusb0(&self) -> &RESOURCE {
            self.resource(110)
        }
        #[doc = "0x1bc - no description available"]
        #[inline(always)]
        pub const fn resourceref0(&self) -> &RESOURCE {
            self.resource(111)
        }
        #[doc = "0x1c0 - no description available"]
        #[inline(always)]
        pub const fn resourceref1(&self) -> &RESOURCE {
            self.resource(112)
        }
        #[doc = "0x800..0x820 - no description available"]
        #[inline(always)]
        pub const fn group0(&self, n: usize) -> &GROUP0 {
            &self.group0[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x800..0x820 - no description available"]
        #[inline(always)]
        pub fn group0_iter(&self) -> impl Iterator<Item = &GROUP0> {
            self.group0.iter()
        }
        #[doc = "0x800..0x810 - no description available"]
        #[inline(always)]
        pub const fn group0link0(&self) -> &GROUP0 {
            self.group0(0)
        }
        #[doc = "0x810..0x820 - no description available"]
        #[inline(always)]
        pub const fn group0link1(&self) -> &GROUP0 {
            self.group0(1)
        }
        #[doc = "0x900..0x910 - no description available"]
        #[inline(always)]
        pub const fn affiliate(&self, n: usize) -> &AFFILIATE {
            &self.affiliate[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x900..0x910 - no description available"]
        #[inline(always)]
        pub fn affiliate_iter(&self) -> impl Iterator<Item = &AFFILIATE> {
            self.affiliate.iter()
        }
        #[doc = "0x900..0x910 - no description available"]
        #[inline(always)]
        pub const fn affiliatecpu0(&self) -> &AFFILIATE {
            self.affiliate(0)
        }
        #[doc = "0x920..0x930 - no description available"]
        #[inline(always)]
        pub const fn retention(&self, n: usize) -> &RETENTION {
            &self.retention[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x920..0x930 - no description available"]
        #[inline(always)]
        pub fn retention_iter(&self) -> impl Iterator<Item = &RETENTION> {
            self.retention.iter()
        }
        #[doc = "0x920..0x930 - no description available"]
        #[inline(always)]
        pub const fn retentioncpu0(&self) -> &RETENTION {
            self.retention(0)
        }
        #[doc = "0x1000..0x1014 - no description available"]
        #[inline(always)]
        pub const fn power(&self, n: usize) -> &POWER {
            &self.power[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1000..0x1014 - no description available"]
        #[inline(always)]
        pub fn power_iter(&self) -> impl Iterator<Item = &POWER> {
            self.power.iter()
        }
        #[doc = "0x1000..0x1014 - no description available"]
        #[inline(always)]
        pub const fn powercpu0(&self) -> &POWER {
            self.power(0)
        }
        #[doc = "0x1400..0x1420 - no description available"]
        #[inline(always)]
        pub const fn reset(&self, n: usize) -> &RESET {
            &self.reset[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1400..0x1420 - no description available"]
        #[inline(always)]
        pub fn reset_iter(&self) -> impl Iterator<Item = &RESET> {
            self.reset.iter()
        }
        #[doc = "0x1400..0x1410 - no description available"]
        #[inline(always)]
        pub const fn resetsoc(&self) -> &RESET {
            self.reset(0)
        }
        #[doc = "0x1410..0x1420 - no description available"]
        #[inline(always)]
        pub const fn resetcpu0(&self) -> &RESET {
            self.reset(1)
        }
        #[doc = "0x1800 - no description available"]
        #[inline(always)]
        pub const fn clock_cpu(&self, n: usize) -> &CLOCK_CPU {
            &self.clock_cpu[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1800 - no description available"]
        #[inline(always)]
        pub fn clock_cpu_iter(&self) -> impl Iterator<Item = &CLOCK_CPU> {
            self.clock_cpu.iter()
        }
        #[doc = "0x1800 - no description available"]
        #[inline(always)]
        pub const fn clock_cpuclk_top_cpu0(&self) -> &CLOCK_CPU {
            self.clock_cpu(0)
        }
        #[doc = "0x1804..0x1894 - no description available"]
        #[inline(always)]
        pub const fn clock(&self, n: usize) -> &CLOCK {
            &self.clock[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1804..0x1894 - no description available"]
        #[inline(always)]
        pub fn clock_iter(&self) -> impl Iterator<Item = &CLOCK> {
            self.clock.iter()
        }
        #[doc = "0x1804 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_mct0(&self) -> &CLOCK {
            self.clock(0)
        }
        #[doc = "0x1808 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_can0(&self) -> &CLOCK {
            self.clock(1)
        }
        #[doc = "0x180c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_can1(&self) -> &CLOCK {
            self.clock(2)
        }
        #[doc = "0x1810 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_can2(&self) -> &CLOCK {
            self.clock(3)
        }
        #[doc = "0x1814 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_can3(&self) -> &CLOCK {
            self.clock(4)
        }
        #[doc = "0x1818 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_lin0(&self) -> &CLOCK {
            self.clock(5)
        }
        #[doc = "0x181c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_lin1(&self) -> &CLOCK {
            self.clock(6)
        }
        #[doc = "0x1820 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_lin2(&self) -> &CLOCK {
            self.clock(7)
        }
        #[doc = "0x1824 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_lin3(&self) -> &CLOCK {
            self.clock(8)
        }
        #[doc = "0x1828 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_tmr0(&self) -> &CLOCK {
            self.clock(9)
        }
        #[doc = "0x182c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_tmr1(&self) -> &CLOCK {
            self.clock(10)
        }
        #[doc = "0x1830 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_tmr2(&self) -> &CLOCK {
            self.clock(11)
        }
        #[doc = "0x1834 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_tmr3(&self) -> &CLOCK {
            self.clock(12)
        }
        #[doc = "0x1838 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_i2c0(&self) -> &CLOCK {
            self.clock(13)
        }
        #[doc = "0x183c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_i2c1(&self) -> &CLOCK {
            self.clock(14)
        }
        #[doc = "0x1840 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_i2c2(&self) -> &CLOCK {
            self.clock(15)
        }
        #[doc = "0x1844 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_i2c3(&self) -> &CLOCK {
            self.clock(16)
        }
        #[doc = "0x1848 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_spi0(&self) -> &CLOCK {
            self.clock(17)
        }
        #[doc = "0x184c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_spi1(&self) -> &CLOCK {
            self.clock(18)
        }
        #[doc = "0x1850 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_spi2(&self) -> &CLOCK {
            self.clock(19)
        }
        #[doc = "0x1854 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_spi3(&self) -> &CLOCK {
            self.clock(20)
        }
        #[doc = "0x1858 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt0(&self) -> &CLOCK {
            self.clock(21)
        }
        #[doc = "0x185c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt1(&self) -> &CLOCK {
            self.clock(22)
        }
        #[doc = "0x1860 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt2(&self) -> &CLOCK {
            self.clock(23)
        }
        #[doc = "0x1864 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt3(&self) -> &CLOCK {
            self.clock(24)
        }
        #[doc = "0x1868 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt4(&self) -> &CLOCK {
            self.clock(25)
        }
        #[doc = "0x186c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt5(&self) -> &CLOCK {
            self.clock(26)
        }
        #[doc = "0x1870 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt6(&self) -> &CLOCK {
            self.clock(27)
        }
        #[doc = "0x1874 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_urt7(&self) -> &CLOCK {
            self.clock(28)
        }
        #[doc = "0x1878 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_xpi0(&self) -> &CLOCK {
            self.clock(29)
        }
        #[doc = "0x187c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_ana0(&self) -> &CLOCK {
            self.clock(30)
        }
        #[doc = "0x1880 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_ana1(&self) -> &CLOCK {
            self.clock(31)
        }
        #[doc = "0x1884 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_ana2(&self) -> &CLOCK {
            self.clock(32)
        }
        #[doc = "0x1888 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_ana3(&self) -> &CLOCK {
            self.clock(33)
        }
        #[doc = "0x188c - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_ref0(&self) -> &CLOCK {
            self.clock(34)
        }
        #[doc = "0x1890 - no description available"]
        #[inline(always)]
        pub const fn clockclk_top_ref1(&self) -> &CLOCK {
            self.clock(35)
        }
        #[doc = "0x1c00..0x1c08 - no description available"]
        #[inline(always)]
        pub const fn adcclk(&self, n: usize) -> &ADCCLK {
            &self.adcclk[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1c00..0x1c08 - no description available"]
        #[inline(always)]
        pub fn adcclk_iter(&self) -> impl Iterator<Item = &ADCCLK> {
            self.adcclk.iter()
        }
        #[doc = "0x1c00 - no description available"]
        #[inline(always)]
        pub const fn adcclkclk_top_adc0(&self) -> &ADCCLK {
            self.adcclk(0)
        }
        #[doc = "0x1c04 - no description available"]
        #[inline(always)]
        pub const fn adcclkclk_top_adc1(&self) -> &ADCCLK {
            self.adcclk(1)
        }
        #[doc = "0x1c08..0x1c10 - no description available"]
        #[inline(always)]
        pub const fn dacclk(&self, n: usize) -> &DACCLK {
            &self.dacclk[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x1c08..0x1c10 - no description available"]
        #[inline(always)]
        pub fn dacclk_iter(&self) -> impl Iterator<Item = &DACCLK> {
            self.dacclk.iter()
        }
        #[doc = "0x1c08 - no description available"]
        #[inline(always)]
        pub const fn dacclkclk_top_dac0(&self) -> &DACCLK {
            self.dacclk(0)
        }
        #[doc = "0x1c0c - no description available"]
        #[inline(always)]
        pub const fn dacclkclk_top_dac1(&self) -> &DACCLK {
            self.dacclk(1)
        }
        #[doc = "0x2000 - Clock senario"]
        #[inline(always)]
        pub const fn global00(&self) -> &GLOBAL00 {
            &self.global00
        }
        #[doc = "0x2400..0x2440 - no description available"]
        #[inline(always)]
        pub const fn monitor(&self, n: usize) -> &MONITOR {
            #[allow(clippy::no_effect)]
            [(); 4][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(9216)
                    .add(32 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x2400..0x2440 - no description available"]
        #[inline(always)]
        pub fn monitor_iter(&self) -> impl Iterator<Item = &MONITOR> {
            (0..4).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(9216)
                    .add(32 * n)
                    .cast()
            })
        }
        #[doc = "0x2400..0x2410 - no description available"]
        #[inline(always)]
        pub const fn monitorslice0(&self) -> &MONITOR {
            self.monitor(0)
        }
        #[doc = "0x2420..0x2430 - no description available"]
        #[inline(always)]
        pub const fn monitorslice1(&self) -> &MONITOR {
            self.monitor(1)
        }
        #[doc = "0x2440..0x2450 - no description available"]
        #[inline(always)]
        pub const fn monitorslice2(&self) -> &MONITOR {
            self.monitor(2)
        }
        #[doc = "0x2460..0x2470 - no description available"]
        #[inline(always)]
        pub const fn monitorslice3(&self) -> &MONITOR {
            self.monitor(3)
        }
        #[doc = "0x2800..0x2890 - no description available"]
        #[inline(always)]
        pub const fn cpu(&self, n: usize) -> &CPU {
            &self.cpu[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x2800..0x2890 - no description available"]
        #[inline(always)]
        pub fn cpu_iter(&self) -> impl Iterator<Item = &CPU> {
            self.cpu.iter()
        }
        #[doc = "0x2800..0x2890 - no description available"]
        #[inline(always)]
        pub const fn cpucpu0(&self) -> &CPU {
            self.cpu(0)
        }
    }
    #[doc = "RESOURCE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resource::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resource::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resource`]
module"]
    pub type RESOURCE = crate::Reg<resource::RESOURCE_SPEC>;
    #[doc = "no description available"]
    pub mod resource {
        #[doc = "Register `RESOURCE[%s]` reader"]
        pub type R = crate::R<RESOURCE_SPEC>;
        #[doc = "Register `RESOURCE[%s]` writer"]
        pub type W = crate::W<RESOURCE_SPEC>;
        #[doc = "Field `MODE` reader - resource work mode 0:auto turn on and off as system required(recommended) 1:always on 2:always off 3:reserved"]
        pub type MODE_R = crate::FieldReader;
        #[doc = "Field `MODE` writer - resource work mode 0:auto turn on and off as system required(recommended) 1:always on 2:always off 3:reserved"]
        pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `LOC_BUSY` reader - local busy 0: no change is pending for current node 1: current node is changing status"]
        pub type LOC_BUSY_R = crate::BitReader;
        #[doc = "Field `GLB_BUSY` reader - global busy 0: no changes pending to any nodes 1: any of nodes is changing status"]
        pub type GLB_BUSY_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:1 - resource work mode 0:auto turn on and off as system required(recommended) 1:always on 2:always off 3:reserved"]
            #[inline(always)]
            pub fn mode(&self) -> MODE_R {
                MODE_R::new((self.bits & 3) as u8)
            }
            #[doc = "Bit 30 - local busy 0: no change is pending for current node 1: current node is changing status"]
            #[inline(always)]
            pub fn loc_busy(&self) -> LOC_BUSY_R {
                LOC_BUSY_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - global busy 0: no changes pending to any nodes 1: any of nodes is changing status"]
            #[inline(always)]
            pub fn glb_busy(&self) -> GLB_BUSY_R {
                GLB_BUSY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:1 - resource work mode 0:auto turn on and off as system required(recommended) 1:always on 2:always off 3:reserved"]
            #[inline(always)]
            #[must_use]
            pub fn mode(&mut self) -> MODE_W<RESOURCE_SPEC> {
                MODE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resource::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resource::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RESOURCE_SPEC;
        impl crate::RegisterSpec for RESOURCE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`resource::R`](R) reader structure"]
        impl crate::Readable for RESOURCE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`resource::W`](W) writer structure"]
        impl crate::Writable for RESOURCE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RESOURCE[%s]
to value 0"]
        impl crate::Resettable for RESOURCE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::group0::GROUP0;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod group0 {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct GROUP0 {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl GROUP0 {
            #[doc = "0x00 - Group setting"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - Group setting"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - Group setting"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - Group setting"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "Group setting"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `LINK` reader - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: peripheral is not needed 1: periphera is needed"]
            pub type LINK_R = crate::FieldReader<u32>;
            #[doc = "Field `LINK` writer - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: peripheral is not needed 1: periphera is needed"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: peripheral is not needed 1: periphera is needed"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: peripheral is not needed 1: periphera is needed"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<VALUE_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "Group setting"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `LINK` reader - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: add periphera into this group，periphera is needed"]
            pub type LINK_R = crate::FieldReader<u32>;
            #[doc = "Field `LINK` writer - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: add periphera into this group，periphera is needed"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: add periphera into this group，periphera is needed"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: add periphera into this group，periphera is needed"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<SET_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "Group setting"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `LINK` reader - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: delete periphera in this group，periphera is not needed"]
            pub type LINK_R = crate::FieldReader<u32>;
            #[doc = "Field `LINK` writer - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: delete periphera in this group，periphera is not needed"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: delete periphera in this group，periphera is not needed"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: delete periphera in this group，periphera is not needed"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<CLEAR_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "Group setting"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `LINK` reader - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: toggle the result that whether periphera is needed before"]
            pub type LINK_R = crate::FieldReader<u32>;
            #[doc = "Field `LINK` writer - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: toggle the result that whether periphera is needed before"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: toggle the result that whether periphera is needed before"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral 0: no effect 1: toggle the result that whether periphera is needed before"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<TOGGLE_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Group setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::affiliate::AFFILIATE;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod affiliate {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct AFFILIATE {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl AFFILIATE {
            #[doc = "0x00 - Affiliate of Group"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - Affiliate of Group"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - Affiliate of Group"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - Affiliate of Group"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "Affiliate of Group"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `LINK` reader - Affiliate groups of cpu0, each bit represents a group bit0: cpu0 depends on group0 bit1: cpu0 depends on group1 bit2: cpu0 depends on group2 bit3: cpu0 depends on group3"]
            pub type LINK_R = crate::FieldReader;
            #[doc = "Field `LINK` writer - Affiliate groups of cpu0, each bit represents a group bit0: cpu0 depends on group0 bit1: cpu0 depends on group1 bit2: cpu0 depends on group2 bit3: cpu0 depends on group3"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            impl R {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0, each bit represents a group bit0: cpu0 depends on group0 bit1: cpu0 depends on group1 bit2: cpu0 depends on group2 bit3: cpu0 depends on group3"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x0f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0, each bit represents a group bit0: cpu0 depends on group0 bit1: cpu0 depends on group1 bit2: cpu0 depends on group2 bit3: cpu0 depends on group3"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<VALUE_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "Affiliate of Group"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `LINK` reader - Affiliate groups of cpu0，each bit represents a group 0: no effect 1: the group is assigned to CPU0"]
            pub type LINK_R = crate::FieldReader;
            #[doc = "Field `LINK` writer - Affiliate groups of cpu0，each bit represents a group 0: no effect 1: the group is assigned to CPU0"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            impl R {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0，each bit represents a group 0: no effect 1: the group is assigned to CPU0"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x0f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0，each bit represents a group 0: no effect 1: the group is assigned to CPU0"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<SET_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "Affiliate of Group"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `LINK` reader - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: the group is not assigned to CPU0"]
            pub type LINK_R = crate::FieldReader;
            #[doc = "Field `LINK` writer - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: the group is not assigned to CPU0"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            impl R {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: the group is not assigned to CPU0"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x0f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: the group is not assigned to CPU0"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<CLEAR_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "Affiliate of Group"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `LINK` reader - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: toggle the result that whether the group is assigned to CPU0 before"]
            pub type LINK_R = crate::FieldReader;
            #[doc = "Field `LINK` writer - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: toggle the result that whether the group is assigned to CPU0 before"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
            impl R {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: toggle the result that whether the group is assigned to CPU0 before"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x0f) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:3 - Affiliate groups of cpu0, each bit represents a group 0: no effect 1: toggle the result that whether the group is assigned to CPU0 before"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<TOGGLE_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Affiliate of Group\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::retention::RETENTION;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod retention {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct RETENTION {
            value: VALUE,
            set: SET,
            clear: CLEAR,
            toggle: TOGGLE,
        }
        impl RETENTION {
            #[doc = "0x00 - Retention Contol"]
            #[inline(always)]
            pub const fn value(&self) -> &VALUE {
                &self.value
            }
            #[doc = "0x04 - Retention Contol"]
            #[inline(always)]
            pub const fn set(&self) -> &SET {
                &self.set
            }
            #[doc = "0x08 - Retention Contol"]
            #[inline(always)]
            pub const fn clear(&self) -> &CLEAR {
                &self.clear
            }
            #[doc = "0x0c - Retention Contol"]
            #[inline(always)]
            pub const fn toggle(&self) -> &TOGGLE {
                &self.toggle
            }
        }
        #[doc = "VALUE (rw) register accessor: Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@value`]
module"]
        pub type VALUE = crate::Reg<value::VALUE_SPEC>;
        #[doc = "Retention Contol"]
        pub mod value {
            #[doc = "Register `VALUE` reader"]
            pub type R = crate::R<VALUE_SPEC>;
            #[doc = "Register `VALUE` writer"]
            pub type W = crate::W<VALUE_SPEC>;
            #[doc = "Field `LINK` reader - retention setting while CPU0 enter stop mode, each bit represents a resource bit00: soc_mem is kept on while cpu0 stop bit01: soc_ctx is kept on while cpu0 stop bit02: cpu0_mem is kept on while cpu0 stop bit03: cpu0_ctx is kept on while cpu0 stop bit04: xtal_hold is kept on while cpu0 stop bit05: pll0_hold is kept on while cpu0 stop bit06: pll1_hold is kept on while cpu0 stop"]
            pub type LINK_R = crate::FieldReader<u16>;
            #[doc = "Field `LINK` writer - retention setting while CPU0 enter stop mode, each bit represents a resource bit00: soc_mem is kept on while cpu0 stop bit01: soc_ctx is kept on while cpu0 stop bit02: cpu0_mem is kept on while cpu0 stop bit03: cpu0_ctx is kept on while cpu0 stop bit04: xtal_hold is kept on while cpu0 stop bit05: pll0_hold is kept on while cpu0 stop bit06: pll1_hold is kept on while cpu0 stop"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
            impl R {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource bit00: soc_mem is kept on while cpu0 stop bit01: soc_ctx is kept on while cpu0 stop bit02: cpu0_mem is kept on while cpu0 stop bit03: cpu0_ctx is kept on while cpu0 stop bit04: xtal_hold is kept on while cpu0 stop bit05: pll0_hold is kept on while cpu0 stop bit06: pll1_hold is kept on while cpu0 stop"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x7fff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource bit00: soc_mem is kept on while cpu0 stop bit01: soc_ctx is kept on while cpu0 stop bit02: cpu0_mem is kept on while cpu0 stop bit03: cpu0_ctx is kept on while cpu0 stop bit04: xtal_hold is kept on while cpu0 stop bit05: pll0_hold is kept on while cpu0 stop bit06: pll1_hold is kept on while cpu0 stop"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<VALUE_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`value::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct VALUE_SPEC;
            impl crate::RegisterSpec for VALUE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`value::R`](R) reader structure"]
            impl crate::Readable for VALUE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`value::W`](W) writer structure"]
            impl crate::Writable for VALUE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets VALUE to value 0"]
            impl crate::Resettable for VALUE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SET (rw) register accessor: Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@set`]
module"]
        pub type SET = crate::Reg<set::SET_SPEC>;
        #[doc = "Retention Contol"]
        pub mod set {
            #[doc = "Register `SET` reader"]
            pub type R = crate::R<SET_SPEC>;
            #[doc = "Register `SET` writer"]
            pub type W = crate::W<SET_SPEC>;
            #[doc = "Field `LINK` reader - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: keep"]
            pub type LINK_R = crate::FieldReader<u16>;
            #[doc = "Field `LINK` writer - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: keep"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
            impl R {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: keep"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x7fff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: keep"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<SET_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SET_SPEC;
            impl crate::RegisterSpec for SET_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`set::R`](R) reader structure"]
            impl crate::Readable for SET_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`set::W`](W) writer structure"]
            impl crate::Writable for SET_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SET to value 0"]
            impl crate::Resettable for SET_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CLEAR (rw) register accessor: Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clear`]
module"]
        pub type CLEAR = crate::Reg<clear::CLEAR_SPEC>;
        #[doc = "Retention Contol"]
        pub mod clear {
            #[doc = "Register `CLEAR` reader"]
            pub type R = crate::R<CLEAR_SPEC>;
            #[doc = "Register `CLEAR` writer"]
            pub type W = crate::W<CLEAR_SPEC>;
            #[doc = "Field `LINK` reader - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: no keep"]
            pub type LINK_R = crate::FieldReader<u16>;
            #[doc = "Field `LINK` writer - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: no keep"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
            impl R {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: no keep"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x7fff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: no keep"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<CLEAR_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clear::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clear::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CLEAR_SPEC;
            impl crate::RegisterSpec for CLEAR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`clear::R`](R) reader structure"]
            impl crate::Readable for CLEAR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`clear::W`](W) writer structure"]
            impl crate::Writable for CLEAR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CLEAR to value 0"]
            impl crate::Resettable for CLEAR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "TOGGLE (rw) register accessor: Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@toggle`]
module"]
        pub type TOGGLE = crate::Reg<toggle::TOGGLE_SPEC>;
        #[doc = "Retention Contol"]
        pub mod toggle {
            #[doc = "Register `TOGGLE` reader"]
            pub type R = crate::R<TOGGLE_SPEC>;
            #[doc = "Register `TOGGLE` writer"]
            pub type W = crate::W<TOGGLE_SPEC>;
            #[doc = "Field `LINK` reader - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: toggle the result that whether the resource is kept on while CPU0 stop before"]
            pub type LINK_R = crate::FieldReader<u16>;
            #[doc = "Field `LINK` writer - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: toggle the result that whether the resource is kept on while CPU0 stop before"]
            pub type LINK_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
            impl R {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: toggle the result that whether the resource is kept on while CPU0 stop before"]
                #[inline(always)]
                pub fn link(&self) -> LINK_R {
                    LINK_R::new((self.bits & 0x7fff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:14 - retention setting while CPU0 enter stop mode, each bit represents a resource 0: no effect 1: toggle the result that whether the resource is kept on while CPU0 stop before"]
                #[inline(always)]
                #[must_use]
                pub fn link(&mut self) -> LINK_W<TOGGLE_SPEC> {
                    LINK_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Retention Contol\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`toggle::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`toggle::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct TOGGLE_SPEC;
            impl crate::RegisterSpec for TOGGLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`toggle::R`](R) reader structure"]
            impl crate::Readable for TOGGLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`toggle::W`](W) writer structure"]
            impl crate::Writable for TOGGLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets TOGGLE to value 0"]
            impl crate::Resettable for TOGGLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::power::POWER;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod power {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct POWER {
            status: STATUS,
            lf_wait: LF_WAIT,
            _reserved2: [u8; 0x04],
            off_wait: OFF_WAIT,
            ret_wait: RET_WAIT,
        }
        impl POWER {
            #[doc = "0x00 - Power Setting"]
            #[inline(always)]
            pub const fn status(&self) -> &STATUS {
                &self.status
            }
            #[doc = "0x04 - Power Setting"]
            #[inline(always)]
            pub const fn lf_wait(&self) -> &LF_WAIT {
                &self.lf_wait
            }
            #[doc = "0x0c - Power Setting"]
            #[inline(always)]
            pub const fn off_wait(&self) -> &OFF_WAIT {
                &self.off_wait
            }
            #[doc = "0x10 - Power Setting"]
            #[inline(always)]
            pub const fn ret_wait(&self) -> &RET_WAIT {
                &self.ret_wait
            }
        }
        #[doc = "status (rw) register accessor: Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
        pub type STATUS = crate::Reg<status::STATUS_SPEC>;
        #[doc = "Power Setting"]
        pub mod status {
            #[doc = "Register `status` reader"]
            pub type R = crate::R<STATUS_SPEC>;
            #[doc = "Register `status` writer"]
            pub type W = crate::W<STATUS_SPEC>;
            #[doc = "Field `LF_ACK` reader - low fanout power switch feedback 0: low fanout power switches are turned on 1: low fanout power switches are truned off"]
            pub type LF_ACK_R = crate::BitReader;
            #[doc = "Field `LF_DISABLE` reader - low fanout power switch disable 0: low fanout power switches are turned on 1: low fanout power switches are truned off"]
            pub type LF_DISABLE_R = crate::BitReader;
            #[doc = "Field `MEM_RET_P` reader - memory info retention control signal 0: memory not enterexitretention mode 1: memory enter retention mode"]
            pub type MEM_RET_P_R = crate::BitReader;
            #[doc = "Field `MEM_RET_N` reader - memory info retention control signal 0: memory enter retention mode 1: memory exit retention mode"]
            pub type MEM_RET_N_R = crate::BitReader;
            #[doc = "Field `FLAG_WAKE` reader - flag represents wakeup power cycle happened from last clear of this bit 0: power domain did not edurance wakeup power cycle since last clear of this bit 1: power domain enduranced wakeup power cycle since last clear of this bit"]
            pub type FLAG_WAKE_R = crate::BitReader;
            #[doc = "Field `FLAG_WAKE` writer - flag represents wakeup power cycle happened from last clear of this bit 0: power domain did not edurance wakeup power cycle since last clear of this bit 1: power domain enduranced wakeup power cycle since last clear of this bit"]
            pub type FLAG_WAKE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FLAG` reader - flag represents power cycle happened from last clear of this bit 0: power domain did not edurance power cycle since last clear of this bit 1: power domain enduranced power cycle since last clear of this bit"]
            pub type FLAG_R = crate::BitReader;
            #[doc = "Field `FLAG` writer - flag represents power cycle happened from last clear of this bit 0: power domain did not edurance power cycle since last clear of this bit 1: power domain enduranced power cycle since last clear of this bit"]
            pub type FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 8 - low fanout power switch feedback 0: low fanout power switches are turned on 1: low fanout power switches are truned off"]
                #[inline(always)]
                pub fn lf_ack(&self) -> LF_ACK_R {
                    LF_ACK_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 12 - low fanout power switch disable 0: low fanout power switches are turned on 1: low fanout power switches are truned off"]
                #[inline(always)]
                pub fn lf_disable(&self) -> LF_DISABLE_R {
                    LF_DISABLE_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bit 16 - memory info retention control signal 0: memory not enterexitretention mode 1: memory enter retention mode"]
                #[inline(always)]
                pub fn mem_ret_p(&self) -> MEM_RET_P_R {
                    MEM_RET_P_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 17 - memory info retention control signal 0: memory enter retention mode 1: memory exit retention mode"]
                #[inline(always)]
                pub fn mem_ret_n(&self) -> MEM_RET_N_R {
                    MEM_RET_N_R::new(((self.bits >> 17) & 1) != 0)
                }
                #[doc = "Bit 30 - flag represents wakeup power cycle happened from last clear of this bit 0: power domain did not edurance wakeup power cycle since last clear of this bit 1: power domain enduranced wakeup power cycle since last clear of this bit"]
                #[inline(always)]
                pub fn flag_wake(&self) -> FLAG_WAKE_R {
                    FLAG_WAKE_R::new(((self.bits >> 30) & 1) != 0)
                }
                #[doc = "Bit 31 - flag represents power cycle happened from last clear of this bit 0: power domain did not edurance power cycle since last clear of this bit 1: power domain enduranced power cycle since last clear of this bit"]
                #[inline(always)]
                pub fn flag(&self) -> FLAG_R {
                    FLAG_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 30 - flag represents wakeup power cycle happened from last clear of this bit 0: power domain did not edurance wakeup power cycle since last clear of this bit 1: power domain enduranced wakeup power cycle since last clear of this bit"]
                #[inline(always)]
                #[must_use]
                pub fn flag_wake(&mut self) -> FLAG_WAKE_W<STATUS_SPEC> {
                    FLAG_WAKE_W::new(self, 30)
                }
                #[doc = "Bit 31 - flag represents power cycle happened from last clear of this bit 0: power domain did not edurance power cycle since last clear of this bit 1: power domain enduranced power cycle since last clear of this bit"]
                #[inline(always)]
                #[must_use]
                pub fn flag(&mut self) -> FLAG_W<STATUS_SPEC> {
                    FLAG_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct STATUS_SPEC;
            impl crate::RegisterSpec for STATUS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`status::R`](R) reader structure"]
            impl crate::Readable for STATUS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
            impl crate::Writable for STATUS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets status to value 0x8000_0000"]
            impl crate::Resettable for STATUS_SPEC {
                const RESET_VALUE: u32 = 0x8000_0000;
            }
        }
        #[doc = "lf_wait (rw) register accessor: Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lf_wait::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lf_wait::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lf_wait`]
module"]
        pub type LF_WAIT = crate::Reg<lf_wait::LF_WAIT_SPEC>;
        #[doc = "Power Setting"]
        pub mod lf_wait {
            #[doc = "Register `lf_wait` reader"]
            pub type R = crate::R<LF_WAIT_SPEC>;
            #[doc = "Register `lf_wait` writer"]
            pub type W = crate::W<LF_WAIT_SPEC>;
            #[doc = "Field `WAIT` reader - wait time for low fan out power switch turn on, default value is 255 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
            pub type WAIT_R = crate::FieldReader<u32>;
            #[doc = "Field `WAIT` writer - wait time for low fan out power switch turn on, default value is 255 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
            pub type WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
            impl R {
                #[doc = "Bits 0:19 - wait time for low fan out power switch turn on, default value is 255 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
                #[inline(always)]
                pub fn wait(&self) -> WAIT_R {
                    WAIT_R::new(self.bits & 0x000f_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:19 - wait time for low fan out power switch turn on, default value is 255 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
                #[inline(always)]
                #[must_use]
                pub fn wait(&mut self) -> WAIT_W<LF_WAIT_SPEC> {
                    WAIT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lf_wait::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lf_wait::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LF_WAIT_SPEC;
            impl crate::RegisterSpec for LF_WAIT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`lf_wait::R`](R) reader structure"]
            impl crate::Readable for LF_WAIT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`lf_wait::W`](W) writer structure"]
            impl crate::Writable for LF_WAIT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets lf_wait to value 0xff"]
            impl crate::Resettable for LF_WAIT_SPEC {
                const RESET_VALUE: u32 = 0xff;
            }
        }
        #[doc = "off_wait (rw) register accessor: Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`off_wait::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`off_wait::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@off_wait`]
module"]
        pub type OFF_WAIT = crate::Reg<off_wait::OFF_WAIT_SPEC>;
        #[doc = "Power Setting"]
        pub mod off_wait {
            #[doc = "Register `off_wait` reader"]
            pub type R = crate::R<OFF_WAIT_SPEC>;
            #[doc = "Register `off_wait` writer"]
            pub type W = crate::W<OFF_WAIT_SPEC>;
            #[doc = "Field `WAIT` reader - wait time for power switch turn off, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
            pub type WAIT_R = crate::FieldReader<u32>;
            #[doc = "Field `WAIT` writer - wait time for power switch turn off, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
            pub type WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
            impl R {
                #[doc = "Bits 0:19 - wait time for power switch turn off, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
                #[inline(always)]
                pub fn wait(&self) -> WAIT_R {
                    WAIT_R::new(self.bits & 0x000f_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:19 - wait time for power switch turn off, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
                #[inline(always)]
                #[must_use]
                pub fn wait(&mut self) -> WAIT_W<OFF_WAIT_SPEC> {
                    WAIT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`off_wait::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`off_wait::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct OFF_WAIT_SPEC;
            impl crate::RegisterSpec for OFF_WAIT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`off_wait::R`](R) reader structure"]
            impl crate::Readable for OFF_WAIT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`off_wait::W`](W) writer structure"]
            impl crate::Writable for OFF_WAIT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets off_wait to value 0x0f"]
            impl crate::Resettable for OFF_WAIT_SPEC {
                const RESET_VALUE: u32 = 0x0f;
            }
        }
        #[doc = "ret_wait (rw) register accessor: Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ret_wait::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ret_wait::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ret_wait`]
module"]
        pub type RET_WAIT = crate::Reg<ret_wait::RET_WAIT_SPEC>;
        #[doc = "Power Setting"]
        pub mod ret_wait {
            #[doc = "Register `ret_wait` reader"]
            pub type R = crate::R<RET_WAIT_SPEC>;
            #[doc = "Register `ret_wait` writer"]
            pub type W = crate::W<RET_WAIT_SPEC>;
            #[doc = "Field `WAIT` reader - wait time for memory retention mode transition, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
            pub type WAIT_R = crate::FieldReader<u32>;
            #[doc = "Field `WAIT` writer - wait time for memory retention mode transition, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
            pub type WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
            impl R {
                #[doc = "Bits 0:19 - wait time for memory retention mode transition, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
                #[inline(always)]
                pub fn wait(&self) -> WAIT_R {
                    WAIT_R::new(self.bits & 0x000f_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:19 - wait time for memory retention mode transition, default value is 15 0: 0 clock cycle 1: 1 clock cycles . . . clock cycles count on 24MHz"]
                #[inline(always)]
                #[must_use]
                pub fn wait(&mut self) -> WAIT_W<RET_WAIT_SPEC> {
                    WAIT_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Power Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ret_wait::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ret_wait::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct RET_WAIT_SPEC;
            impl crate::RegisterSpec for RET_WAIT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ret_wait::R`](R) reader structure"]
            impl crate::Readable for RET_WAIT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ret_wait::W`](W) writer structure"]
            impl crate::Writable for RET_WAIT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ret_wait to value 0x0f"]
            impl crate::Resettable for RET_WAIT_SPEC {
                const RESET_VALUE: u32 = 0x0f;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::reset::RESET;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod reset {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct RESET {
            control: CONTROL,
            config: CONFIG,
            _reserved2: [u8; 0x04],
            counter: COUNTER,
        }
        impl RESET {
            #[doc = "0x00 - Reset Setting"]
            #[inline(always)]
            pub const fn control(&self) -> &CONTROL {
                &self.control
            }
            #[doc = "0x04 - Reset Setting"]
            #[inline(always)]
            pub const fn config(&self) -> &CONFIG {
                &self.config
            }
            #[doc = "0x0c - Reset Setting"]
            #[inline(always)]
            pub const fn counter(&self) -> &COUNTER {
                &self.counter
            }
        }
        #[doc = "control (rw) register accessor: Reset Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`]
module"]
        pub type CONTROL = crate::Reg<control::CONTROL_SPEC>;
        #[doc = "Reset Setting"]
        pub mod control {
            #[doc = "Register `control` reader"]
            pub type R = crate::R<CONTROL_SPEC>;
            #[doc = "Register `control` writer"]
            pub type W = crate::W<CONTROL_SPEC>;
            #[doc = "Field `RESET` reader - perform reset and release imediately 0: reset is released 1 reset is asserted and will release automaticly"]
            pub type RESET_R = crate::BitReader;
            #[doc = "Field `RESET` writer - perform reset and release imediately 0: reset is released 1 reset is asserted and will release automaticly"]
            pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `HOLD` reader - perform reset and hold in reset, until ths bit cleared by software 0: reset is released for function 1: reset is assert and hold"]
            pub type HOLD_R = crate::BitReader;
            #[doc = "Field `HOLD` writer - perform reset and hold in reset, until ths bit cleared by software 0: reset is released for function 1: reset is assert and hold"]
            pub type HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FLAG_WAKE` reader - flag represents wakeup reset happened from last clear of this bit 0: domain did not edurance wakeup reset cycle since last clear of this bit 1: domain enduranced wakeup reset cycle since last clear of this bit"]
            pub type FLAG_WAKE_R = crate::BitReader;
            #[doc = "Field `FLAG_WAKE` writer - flag represents wakeup reset happened from last clear of this bit 0: domain did not edurance wakeup reset cycle since last clear of this bit 1: domain enduranced wakeup reset cycle since last clear of this bit"]
            pub type FLAG_WAKE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `FLAG` reader - flag represents reset happened from last clear of this bit 0: domain did not edurance reset cycle since last clear of this bit 1: domain enduranced reset cycle since last clear of this bit"]
            pub type FLAG_R = crate::BitReader;
            #[doc = "Field `FLAG` writer - flag represents reset happened from last clear of this bit 0: domain did not edurance reset cycle since last clear of this bit 1: domain enduranced reset cycle since last clear of this bit"]
            pub type FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - perform reset and release imediately 0: reset is released 1 reset is asserted and will release automaticly"]
                #[inline(always)]
                pub fn reset(&self) -> RESET_R {
                    RESET_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 4 - perform reset and hold in reset, until ths bit cleared by software 0: reset is released for function 1: reset is assert and hold"]
                #[inline(always)]
                pub fn hold(&self) -> HOLD_R {
                    HOLD_R::new(((self.bits >> 4) & 1) != 0)
                }
                #[doc = "Bit 30 - flag represents wakeup reset happened from last clear of this bit 0: domain did not edurance wakeup reset cycle since last clear of this bit 1: domain enduranced wakeup reset cycle since last clear of this bit"]
                #[inline(always)]
                pub fn flag_wake(&self) -> FLAG_WAKE_R {
                    FLAG_WAKE_R::new(((self.bits >> 30) & 1) != 0)
                }
                #[doc = "Bit 31 - flag represents reset happened from last clear of this bit 0: domain did not edurance reset cycle since last clear of this bit 1: domain enduranced reset cycle since last clear of this bit"]
                #[inline(always)]
                pub fn flag(&self) -> FLAG_R {
                    FLAG_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - perform reset and release imediately 0: reset is released 1 reset is asserted and will release automaticly"]
                #[inline(always)]
                #[must_use]
                pub fn reset(&mut self) -> RESET_W<CONTROL_SPEC> {
                    RESET_W::new(self, 0)
                }
                #[doc = "Bit 4 - perform reset and hold in reset, until ths bit cleared by software 0: reset is released for function 1: reset is assert and hold"]
                #[inline(always)]
                #[must_use]
                pub fn hold(&mut self) -> HOLD_W<CONTROL_SPEC> {
                    HOLD_W::new(self, 4)
                }
                #[doc = "Bit 30 - flag represents wakeup reset happened from last clear of this bit 0: domain did not edurance wakeup reset cycle since last clear of this bit 1: domain enduranced wakeup reset cycle since last clear of this bit"]
                #[inline(always)]
                #[must_use]
                pub fn flag_wake(&mut self) -> FLAG_WAKE_W<CONTROL_SPEC> {
                    FLAG_WAKE_W::new(self, 30)
                }
                #[doc = "Bit 31 - flag represents reset happened from last clear of this bit 0: domain did not edurance reset cycle since last clear of this bit 1: domain enduranced reset cycle since last clear of this bit"]
                #[inline(always)]
                #[must_use]
                pub fn flag(&mut self) -> FLAG_W<CONTROL_SPEC> {
                    FLAG_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Reset Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CONTROL_SPEC;
            impl crate::RegisterSpec for CONTROL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`control::R`](R) reader structure"]
            impl crate::Readable for CONTROL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
            impl crate::Writable for CONTROL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets control to value 0x8000_0000"]
            impl crate::Resettable for CONTROL_SPEC {
                const RESET_VALUE: u32 = 0x8000_0000;
            }
        }
        #[doc = "config (rw) register accessor: Reset Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`]
module"]
        pub type CONFIG = crate::Reg<config::CONFIG_SPEC>;
        #[doc = "Reset Setting"]
        pub mod config {
            #[doc = "Register `config` reader"]
            pub type R = crate::R<CONFIG_SPEC>;
            #[doc = "Register `config` writer"]
            pub type W = crate::W<CONFIG_SPEC>;
            #[doc = "Field `POST_WAIT` reader - time guard band for reset release 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
            pub type POST_WAIT_R = crate::FieldReader;
            #[doc = "Field `POST_WAIT` writer - time guard band for reset release 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
            pub type POST_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `RSTCLK_NUM` reader - reset clock number(must be even number) 0: 0 cycle 1: 0 cycles 2: 2 cycles 3: 2 cycles . . . Note, clock cycle is base on 24M"]
            pub type RSTCLK_NUM_R = crate::FieldReader;
            #[doc = "Field `RSTCLK_NUM` writer - reset clock number(must be even number) 0: 0 cycle 1: 0 cycles 2: 2 cycles 3: 2 cycles . . . Note, clock cycle is base on 24M"]
            pub type RSTCLK_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `PRE_WAIT` reader - wait cycle numbers before assert reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
            pub type PRE_WAIT_R = crate::FieldReader;
            #[doc = "Field `PRE_WAIT` writer - wait cycle numbers before assert reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
            pub type PRE_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bits 0:7 - time guard band for reset release 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                pub fn post_wait(&self) -> POST_WAIT_R {
                    POST_WAIT_R::new((self.bits & 0xff) as u8)
                }
                #[doc = "Bits 8:15 - reset clock number(must be even number) 0: 0 cycle 1: 0 cycles 2: 2 cycles 3: 2 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                pub fn rstclk_num(&self) -> RSTCLK_NUM_R {
                    RSTCLK_NUM_R::new(((self.bits >> 8) & 0xff) as u8)
                }
                #[doc = "Bits 16:23 - wait cycle numbers before assert reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                pub fn pre_wait(&self) -> PRE_WAIT_R {
                    PRE_WAIT_R::new(((self.bits >> 16) & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - time guard band for reset release 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                #[must_use]
                pub fn post_wait(&mut self) -> POST_WAIT_W<CONFIG_SPEC> {
                    POST_WAIT_W::new(self, 0)
                }
                #[doc = "Bits 8:15 - reset clock number(must be even number) 0: 0 cycle 1: 0 cycles 2: 2 cycles 3: 2 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                #[must_use]
                pub fn rstclk_num(&mut self) -> RSTCLK_NUM_W<CONFIG_SPEC> {
                    RSTCLK_NUM_W::new(self, 8)
                }
                #[doc = "Bits 16:23 - wait cycle numbers before assert reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                #[must_use]
                pub fn pre_wait(&mut self) -> PRE_WAIT_W<CONFIG_SPEC> {
                    PRE_WAIT_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Reset Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CONFIG_SPEC;
            impl crate::RegisterSpec for CONFIG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`config::R`](R) reader structure"]
            impl crate::Readable for CONFIG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"]
            impl crate::Writable for CONFIG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets config to value 0x0040_2003"]
            impl crate::Resettable for CONFIG_SPEC {
                const RESET_VALUE: u32 = 0x0040_2003;
            }
        }
        #[doc = "counter (rw) register accessor: Reset Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`counter::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`counter::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@counter`]
module"]
        pub type COUNTER = crate::Reg<counter::COUNTER_SPEC>;
        #[doc = "Reset Setting"]
        pub mod counter {
            #[doc = "Register `counter` reader"]
            pub type R = crate::R<COUNTER_SPEC>;
            #[doc = "Register `counter` writer"]
            pub type W = crate::W<COUNTER_SPEC>;
            #[doc = "Field `COUNTER` reader - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
            pub type COUNTER_R = crate::FieldReader<u32>;
            #[doc = "Field `COUNTER` writer - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
            pub type COUNTER_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
            impl R {
                #[doc = "Bits 0:19 - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                pub fn counter(&self) -> COUNTER_R {
                    COUNTER_R::new(self.bits & 0x000f_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:19 - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset 0: wait 0 cycle 1: wait 1 cycles . . . Note, clock cycle is base on 24M"]
                #[inline(always)]
                #[must_use]
                pub fn counter(&mut self) -> COUNTER_W<COUNTER_SPEC> {
                    COUNTER_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Reset Setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`counter::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`counter::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct COUNTER_SPEC;
            impl crate::RegisterSpec for COUNTER_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`counter::R`](R) reader structure"]
            impl crate::Readable for COUNTER_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`counter::W`](W) writer structure"]
            impl crate::Writable for COUNTER_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets counter to value 0"]
            impl crate::Resettable for COUNTER_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "CLOCK_CPU (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_cpu::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_cpu::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_cpu`]
module"]
    pub type CLOCK_CPU = crate::Reg<clock_cpu::CLOCK_CPU_SPEC>;
    #[doc = "no description available"]
    pub mod clock_cpu {
        #[doc = "Register `CLOCK_CPU[%s]` reader"]
        pub type R = crate::R<CLOCK_CPU_SPEC>;
        #[doc = "Register `CLOCK_CPU[%s]` writer"]
        pub type W = crate::W<CLOCK_CPU_SPEC>;
        #[doc = "Field `DIV` reader - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
        pub type DIV_R = crate::FieldReader;
        #[doc = "Field `DIV` writer - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
        pub type DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `MUX` reader - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
        pub type MUX_R = crate::FieldReader;
        #[doc = "Field `MUX` writer - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
        pub type MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `SUB0_DIV` reader - ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …"]
        pub type SUB0_DIV_R = crate::FieldReader;
        #[doc = "Field `SUB0_DIV` writer - ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …"]
        pub type SUB0_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `PRESERVE` reader - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_R = crate::BitReader;
        #[doc = "Field `PRESERVE` writer - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LOC_BUSY` reader - local busy 0: a change is pending for current node 1: current node is changing status"]
        pub type LOC_BUSY_R = crate::BitReader;
        #[doc = "Field `GLB_BUSY` reader - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
        pub type GLB_BUSY_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:7 - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
            #[inline(always)]
            pub fn div(&self) -> DIV_R {
                DIV_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:10 - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
            #[inline(always)]
            pub fn mux(&self) -> MUX_R {
                MUX_R::new(((self.bits >> 8) & 7) as u8)
            }
            #[doc = "Bits 16:19 - ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …"]
            #[inline(always)]
            pub fn sub0_div(&self) -> SUB0_DIV_R {
                SUB0_DIV_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            pub fn preserve(&self) -> PRESERVE_R {
                PRESERVE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 30 - local busy 0: a change is pending for current node 1: current node is changing status"]
            #[inline(always)]
            pub fn loc_busy(&self) -> LOC_BUSY_R {
                LOC_BUSY_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
            #[inline(always)]
            pub fn glb_busy(&self) -> GLB_BUSY_R {
                GLB_BUSY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
            #[inline(always)]
            #[must_use]
            pub fn div(&mut self) -> DIV_W<CLOCK_CPU_SPEC> {
                DIV_W::new(self, 0)
            }
            #[doc = "Bits 8:10 - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
            #[inline(always)]
            #[must_use]
            pub fn mux(&mut self) -> MUX_W<CLOCK_CPU_SPEC> {
                MUX_W::new(self, 8)
            }
            #[doc = "Bits 16:19 - ahb bus divider, the bus clock is generated by cpu_clock/div 0: divider by 1 1: divider by 2 …"]
            #[inline(always)]
            #[must_use]
            pub fn sub0_div(&mut self) -> SUB0_DIV_W<CLOCK_CPU_SPEC> {
                SUB0_DIV_W::new(self, 16)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            #[must_use]
            pub fn preserve(&mut self) -> PRESERVE_W<CLOCK_CPU_SPEC> {
                PRESERVE_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock_cpu::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock_cpu::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CLOCK_CPU_SPEC;
        impl crate::RegisterSpec for CLOCK_CPU_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`clock_cpu::R`](R) reader structure"]
        impl crate::Readable for CLOCK_CPU_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`clock_cpu::W`](W) writer structure"]
        impl crate::Writable for CLOCK_CPU_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CLOCK_CPU[%s]
to value 0"]
        impl crate::Resettable for CLOCK_CPU_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "CLOCK (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock`]
module"]
    pub type CLOCK = crate::Reg<clock::CLOCK_SPEC>;
    #[doc = "no description available"]
    pub mod clock {
        #[doc = "Register `CLOCK[%s]` reader"]
        pub type R = crate::R<CLOCK_SPEC>;
        #[doc = "Register `CLOCK[%s]` writer"]
        pub type W = crate::W<CLOCK_SPEC>;
        #[doc = "Field `DIV` reader - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
        pub type DIV_R = crate::FieldReader;
        #[doc = "Field `DIV` writer - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
        pub type DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        #[doc = "Field `MUX` reader - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
        pub type MUX_R = crate::FieldReader;
        #[doc = "Field `MUX` writer - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
        pub type MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `PRESERVE` reader - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_R = crate::BitReader;
        #[doc = "Field `PRESERVE` writer - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LOC_BUSY` reader - local busy 0: a change is pending for current node 1: current node is changing status"]
        pub type LOC_BUSY_R = crate::BitReader;
        #[doc = "Field `GLB_BUSY` reader - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
        pub type GLB_BUSY_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:7 - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
            #[inline(always)]
            pub fn div(&self) -> DIV_R {
                DIV_R::new((self.bits & 0xff) as u8)
            }
            #[doc = "Bits 8:10 - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
            #[inline(always)]
            pub fn mux(&self) -> MUX_R {
                MUX_R::new(((self.bits >> 8) & 7) as u8)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            pub fn preserve(&self) -> PRESERVE_R {
                PRESERVE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 30 - local busy 0: a change is pending for current node 1: current node is changing status"]
            #[inline(always)]
            pub fn loc_busy(&self) -> LOC_BUSY_R {
                LOC_BUSY_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
            #[inline(always)]
            pub fn glb_busy(&self) -> GLB_BUSY_R {
                GLB_BUSY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - clock divider 0: divider by 1 1: divider by 2 2: divider by 3 . . . 255: divider by 256"]
            #[inline(always)]
            #[must_use]
            pub fn div(&mut self) -> DIV_W<CLOCK_SPEC> {
                DIV_W::new(self, 0)
            }
            #[doc = "Bits 8:10 - current mux in clock component 0:osc0_clk0 1:pll0_clk0 2:pll0_clk1 3:pll0_clk2 4:pll1_clk0 5:pll1_clk1 6:pll1_clk2 7:pll1_clk3"]
            #[inline(always)]
            #[must_use]
            pub fn mux(&mut self) -> MUX_W<CLOCK_SPEC> {
                MUX_W::new(self, 8)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            #[must_use]
            pub fn preserve(&mut self) -> PRESERVE_W<CLOCK_SPEC> {
                PRESERVE_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct CLOCK_SPEC;
        impl crate::RegisterSpec for CLOCK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`clock::R`](R) reader structure"]
        impl crate::Readable for CLOCK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`clock::W`](W) writer structure"]
        impl crate::Writable for CLOCK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets CLOCK[%s]
to value 0"]
        impl crate::Resettable for CLOCK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "ADCCLK (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcclk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcclk`]
module"]
    pub type ADCCLK = crate::Reg<adcclk::ADCCLK_SPEC>;
    #[doc = "no description available"]
    pub mod adcclk {
        #[doc = "Register `ADCCLK[%s]` reader"]
        pub type R = crate::R<ADCCLK_SPEC>;
        #[doc = "Register `ADCCLK[%s]` writer"]
        pub type W = crate::W<ADCCLK_SPEC>;
        #[doc = "Field `MUX` reader - current mux 0: ahb0 clock N 1: ana clock"]
        pub type MUX_R = crate::BitReader;
        #[doc = "Field `MUX` writer - current mux 0: ahb0 clock N 1: ana clock"]
        pub type MUX_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRESERVE` reader - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_R = crate::BitReader;
        #[doc = "Field `PRESERVE` writer - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LOC_BUSY` reader - local busy 0: a change is pending for current node 1: current node is changing status"]
        pub type LOC_BUSY_R = crate::BitReader;
        #[doc = "Field `GLB_BUSY` reader - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
        pub type GLB_BUSY_R = crate::BitReader;
        impl R {
            #[doc = "Bit 8 - current mux 0: ahb0 clock N 1: ana clock"]
            #[inline(always)]
            pub fn mux(&self) -> MUX_R {
                MUX_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            pub fn preserve(&self) -> PRESERVE_R {
                PRESERVE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 30 - local busy 0: a change is pending for current node 1: current node is changing status"]
            #[inline(always)]
            pub fn loc_busy(&self) -> LOC_BUSY_R {
                LOC_BUSY_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
            #[inline(always)]
            pub fn glb_busy(&self) -> GLB_BUSY_R {
                GLB_BUSY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 8 - current mux 0: ahb0 clock N 1: ana clock"]
            #[inline(always)]
            #[must_use]
            pub fn mux(&mut self) -> MUX_W<ADCCLK_SPEC> {
                MUX_W::new(self, 8)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            #[must_use]
            pub fn preserve(&mut self) -> PRESERVE_W<ADCCLK_SPEC> {
                PRESERVE_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcclk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct ADCCLK_SPEC;
        impl crate::RegisterSpec for ADCCLK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`adcclk::R`](R) reader structure"]
        impl crate::Readable for ADCCLK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`adcclk::W`](W) writer structure"]
        impl crate::Writable for ADCCLK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets ADCCLK[%s]
to value 0"]
        impl crate::Resettable for ADCCLK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DACCLK (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacclk::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacclk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dacclk`]
module"]
    pub type DACCLK = crate::Reg<dacclk::DACCLK_SPEC>;
    #[doc = "no description available"]
    pub mod dacclk {
        #[doc = "Register `DACCLK[%s]` reader"]
        pub type R = crate::R<DACCLK_SPEC>;
        #[doc = "Register `DACCLK[%s]` writer"]
        pub type W = crate::W<DACCLK_SPEC>;
        #[doc = "Field `MUX` reader - current mux 0: ahb0 clock N 1: ana clock"]
        pub type MUX_R = crate::BitReader;
        #[doc = "Field `MUX` writer - current mux 0: ahb0 clock N 1: ana clock"]
        pub type MUX_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `PRESERVE` reader - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_R = crate::BitReader;
        #[doc = "Field `PRESERVE` writer - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
        pub type PRESERVE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `LOC_BUSY` reader - local busy 0: a change is pending for current node 1: current node is changing status"]
        pub type LOC_BUSY_R = crate::BitReader;
        #[doc = "Field `GLB_BUSY` reader - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
        pub type GLB_BUSY_R = crate::BitReader;
        impl R {
            #[doc = "Bit 8 - current mux 0: ahb0 clock N 1: ana clock"]
            #[inline(always)]
            pub fn mux(&self) -> MUX_R {
                MUX_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            pub fn preserve(&self) -> PRESERVE_R {
                PRESERVE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 30 - local busy 0: a change is pending for current node 1: current node is changing status"]
            #[inline(always)]
            pub fn loc_busy(&self) -> LOC_BUSY_R {
                LOC_BUSY_R::new(((self.bits >> 30) & 1) != 0)
            }
            #[doc = "Bit 31 - global busy 0: no changes pending to any clock 1: any of nodes is changing status"]
            #[inline(always)]
            pub fn glb_busy(&self) -> GLB_BUSY_R {
                GLB_BUSY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 8 - current mux 0: ahb0 clock N 1: ana clock"]
            #[inline(always)]
            #[must_use]
            pub fn mux(&mut self) -> MUX_W<DACCLK_SPEC> {
                MUX_W::new(self, 8)
            }
            #[doc = "Bit 28 - preserve function against global select 0: select global clock setting 1: not select global clock setting"]
            #[inline(always)]
            #[must_use]
            pub fn preserve(&mut self) -> PRESERVE_W<DACCLK_SPEC> {
                PRESERVE_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacclk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacclk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DACCLK_SPEC;
        impl crate::RegisterSpec for DACCLK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dacclk::R`](R) reader structure"]
        impl crate::Readable for DACCLK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dacclk::W`](W) writer structure"]
        impl crate::Writable for DACCLK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DACCLK[%s]
to value 0"]
        impl crate::Resettable for DACCLK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "global00 (rw) register accessor: Clock senario\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`global00::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`global00::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@global00`]
module"]
    pub type GLOBAL00 = crate::Reg<global00::GLOBAL00_SPEC>;
    #[doc = "Clock senario"]
    pub mod global00 {
        #[doc = "Register `global00` reader"]
        pub type R = crate::R<GLOBAL00_SPEC>;
        #[doc = "Register `global00` writer"]
        pub type W = crate::W<GLOBAL00_SPEC>;
        #[doc = "Field `MUX` reader - global clock override request bit0: override to preset0 bit1: override to preset1 bit2: override to preset2 bit3: override to preset3 bit4: override to preset4 bit5: override to preset5 bit6: override to preset6 bit7: override to preset7"]
        pub type MUX_R = crate::FieldReader;
        #[doc = "Field `MUX` writer - global clock override request bit0: override to preset0 bit1: override to preset1 bit2: override to preset2 bit3: override to preset3 bit4: override to preset4 bit5: override to preset5 bit6: override to preset6 bit7: override to preset7"]
        pub type MUX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
        impl R {
            #[doc = "Bits 0:7 - global clock override request bit0: override to preset0 bit1: override to preset1 bit2: override to preset2 bit3: override to preset3 bit4: override to preset4 bit5: override to preset5 bit6: override to preset6 bit7: override to preset7"]
            #[inline(always)]
            pub fn mux(&self) -> MUX_R {
                MUX_R::new((self.bits & 0xff) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:7 - global clock override request bit0: override to preset0 bit1: override to preset1 bit2: override to preset2 bit3: override to preset3 bit4: override to preset4 bit5: override to preset5 bit6: override to preset6 bit7: override to preset7"]
            #[inline(always)]
            #[must_use]
            pub fn mux(&mut self) -> MUX_W<GLOBAL00_SPEC> {
                MUX_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Clock senario\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`global00::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`global00::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct GLOBAL00_SPEC;
        impl crate::RegisterSpec for GLOBAL00_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`global00::R`](R) reader structure"]
        impl crate::Readable for GLOBAL00_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`global00::W`](W) writer structure"]
        impl crate::Writable for GLOBAL00_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets global00 to value 0"]
        impl crate::Resettable for GLOBAL00_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "no description available"]
    pub use self::monitor::MONITOR;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod monitor {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct MONITOR {
            control: CONTROL,
            current: CURRENT,
            low_limit: LOW_LIMIT,
            high_limit: HIGH_LIMIT,
        }
        impl MONITOR {
            #[doc = "0x00 - Clock measure and monitor control"]
            #[inline(always)]
            pub const fn control(&self) -> &CONTROL {
                &self.control
            }
            #[doc = "0x04 - Clock measure result"]
            #[inline(always)]
            pub const fn current(&self) -> &CURRENT {
                &self.current
            }
            #[doc = "0x08 - Clock lower limit"]
            #[inline(always)]
            pub const fn low_limit(&self) -> &LOW_LIMIT {
                &self.low_limit
            }
            #[doc = "0x0c - Clock upper limit"]
            #[inline(always)]
            pub const fn high_limit(&self) -> &HIGH_LIMIT {
                &self.high_limit
            }
        }
        #[doc = "control (rw) register accessor: Clock measure and monitor control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control`]
module"]
        pub type CONTROL = crate::Reg<control::CONTROL_SPEC>;
        #[doc = "Clock measure and monitor control"]
        pub mod control {
            #[doc = "Register `control` reader"]
            pub type R = crate::R<CONTROL_SPEC>;
            #[doc = "Register `control` writer"]
            pub type W = crate::W<CONTROL_SPEC>;
            #[doc = "Field `SELECTION` reader - clock measurement selection"]
            pub type SELECTION_R = crate::FieldReader;
            #[doc = "Field `SELECTION` writer - clock measurement selection"]
            pub type SELECTION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `REFERENCE` reader - refrence clock selection, 0: 32k 1: 24M"]
            pub type REFERENCE_R = crate::BitReader;
            #[doc = "Field `REFERENCE` writer - refrence clock selection, 0: 32k 1: 24M"]
            pub type REFERENCE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `ACCURACY` reader - measurement accuracy, 0: resolution is 1kHz 1: resolution is 1Hz"]
            pub type ACCURACY_R = crate::BitReader;
            #[doc = "Field `ACCURACY` writer - measurement accuracy, 0: resolution is 1kHz 1: resolution is 1Hz"]
            pub type ACCURACY_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `MODE` reader - work mode, 0: register value will be compared to measurement 1: upper and lower value will be recordered in register"]
            pub type MODE_R = crate::BitReader;
            #[doc = "Field `MODE` writer - work mode, 0: register value will be compared to measurement 1: upper and lower value will be recordered in register"]
            pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `START` reader - start measurement"]
            pub type START_R = crate::BitReader;
            #[doc = "Field `START` writer - start measurement"]
            pub type START_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LOW` reader - clock frequency lower than lower limit"]
            pub type LOW_R = crate::BitReader;
            #[doc = "Field `LOW` writer - clock frequency lower than lower limit"]
            pub type LOW_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `HIGH` reader - clock frequency higher than upper limit"]
            pub type HIGH_R = crate::BitReader;
            #[doc = "Field `HIGH` writer - clock frequency higher than upper limit"]
            pub type HIGH_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DIV` reader - output divider"]
            pub type DIV_R = crate::FieldReader;
            #[doc = "Field `DIV` writer - output divider"]
            pub type DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            #[doc = "Field `OUTEN` reader - enable clock output"]
            pub type OUTEN_R = crate::BitReader;
            #[doc = "Field `OUTEN` writer - enable clock output"]
            pub type OUTEN_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `DIV_BUSY` reader - divider is applying new setting"]
            pub type DIV_BUSY_R = crate::BitReader;
            #[doc = "Field `VALID` reader - result is ready for read 0: not ready 1: result is ready"]
            pub type VALID_R = crate::BitReader;
            #[doc = "Field `VALID` writer - result is ready for read 0: not ready 1: result is ready"]
            pub type VALID_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:7 - clock measurement selection"]
                #[inline(always)]
                pub fn selection(&self) -> SELECTION_R {
                    SELECTION_R::new((self.bits & 0xff) as u8)
                }
                #[doc = "Bit 8 - refrence clock selection, 0: 32k 1: 24M"]
                #[inline(always)]
                pub fn reference(&self) -> REFERENCE_R {
                    REFERENCE_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - measurement accuracy, 0: resolution is 1kHz 1: resolution is 1Hz"]
                #[inline(always)]
                pub fn accuracy(&self) -> ACCURACY_R {
                    ACCURACY_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - work mode, 0: register value will be compared to measurement 1: upper and lower value will be recordered in register"]
                #[inline(always)]
                pub fn mode(&self) -> MODE_R {
                    MODE_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 12 - start measurement"]
                #[inline(always)]
                pub fn start(&self) -> START_R {
                    START_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bit 14 - clock frequency lower than lower limit"]
                #[inline(always)]
                pub fn low(&self) -> LOW_R {
                    LOW_R::new(((self.bits >> 14) & 1) != 0)
                }
                #[doc = "Bit 15 - clock frequency higher than upper limit"]
                #[inline(always)]
                pub fn high(&self) -> HIGH_R {
                    HIGH_R::new(((self.bits >> 15) & 1) != 0)
                }
                #[doc = "Bits 16:23 - output divider"]
                #[inline(always)]
                pub fn div(&self) -> DIV_R {
                    DIV_R::new(((self.bits >> 16) & 0xff) as u8)
                }
                #[doc = "Bit 24 - enable clock output"]
                #[inline(always)]
                pub fn outen(&self) -> OUTEN_R {
                    OUTEN_R::new(((self.bits >> 24) & 1) != 0)
                }
                #[doc = "Bit 27 - divider is applying new setting"]
                #[inline(always)]
                pub fn div_busy(&self) -> DIV_BUSY_R {
                    DIV_BUSY_R::new(((self.bits >> 27) & 1) != 0)
                }
                #[doc = "Bit 31 - result is ready for read 0: not ready 1: result is ready"]
                #[inline(always)]
                pub fn valid(&self) -> VALID_R {
                    VALID_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:7 - clock measurement selection"]
                #[inline(always)]
                #[must_use]
                pub fn selection(&mut self) -> SELECTION_W<CONTROL_SPEC> {
                    SELECTION_W::new(self, 0)
                }
                #[doc = "Bit 8 - refrence clock selection, 0: 32k 1: 24M"]
                #[inline(always)]
                #[must_use]
                pub fn reference(&mut self) -> REFERENCE_W<CONTROL_SPEC> {
                    REFERENCE_W::new(self, 8)
                }
                #[doc = "Bit 9 - measurement accuracy, 0: resolution is 1kHz 1: resolution is 1Hz"]
                #[inline(always)]
                #[must_use]
                pub fn accuracy(&mut self) -> ACCURACY_W<CONTROL_SPEC> {
                    ACCURACY_W::new(self, 9)
                }
                #[doc = "Bit 10 - work mode, 0: register value will be compared to measurement 1: upper and lower value will be recordered in register"]
                #[inline(always)]
                #[must_use]
                pub fn mode(&mut self) -> MODE_W<CONTROL_SPEC> {
                    MODE_W::new(self, 10)
                }
                #[doc = "Bit 12 - start measurement"]
                #[inline(always)]
                #[must_use]
                pub fn start(&mut self) -> START_W<CONTROL_SPEC> {
                    START_W::new(self, 12)
                }
                #[doc = "Bit 14 - clock frequency lower than lower limit"]
                #[inline(always)]
                #[must_use]
                pub fn low(&mut self) -> LOW_W<CONTROL_SPEC> {
                    LOW_W::new(self, 14)
                }
                #[doc = "Bit 15 - clock frequency higher than upper limit"]
                #[inline(always)]
                #[must_use]
                pub fn high(&mut self) -> HIGH_W<CONTROL_SPEC> {
                    HIGH_W::new(self, 15)
                }
                #[doc = "Bits 16:23 - output divider"]
                #[inline(always)]
                #[must_use]
                pub fn div(&mut self) -> DIV_W<CONTROL_SPEC> {
                    DIV_W::new(self, 16)
                }
                #[doc = "Bit 24 - enable clock output"]
                #[inline(always)]
                #[must_use]
                pub fn outen(&mut self) -> OUTEN_W<CONTROL_SPEC> {
                    OUTEN_W::new(self, 24)
                }
                #[doc = "Bit 31 - result is ready for read 0: not ready 1: result is ready"]
                #[inline(always)]
                #[must_use]
                pub fn valid(&mut self) -> VALID_W<CONTROL_SPEC> {
                    VALID_W::new(self, 31)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Clock measure and monitor control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CONTROL_SPEC;
            impl crate::RegisterSpec for CONTROL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`control::R`](R) reader structure"]
            impl crate::Readable for CONTROL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
            impl crate::Writable for CONTROL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets control to value 0"]
            impl crate::Resettable for CONTROL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "current (rw) register accessor: Clock measure result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@current`]
module"]
        pub type CURRENT = crate::Reg<current::CURRENT_SPEC>;
        #[doc = "Clock measure result"]
        pub mod current {
            #[doc = "Register `current` reader"]
            pub type R = crate::R<CURRENT_SPEC>;
            #[doc = "Register `current` writer"]
            pub type W = crate::W<CURRENT_SPEC>;
            #[doc = "Field `FREQUENCY` reader - self updating measure result"]
            pub type FREQUENCY_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - self updating measure result"]
                #[inline(always)]
                pub fn frequency(&self) -> FREQUENCY_R {
                    FREQUENCY_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Clock measure result\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`current::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`current::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CURRENT_SPEC;
            impl crate::RegisterSpec for CURRENT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`current::R`](R) reader structure"]
            impl crate::Readable for CURRENT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`current::W`](W) writer structure"]
            impl crate::Writable for CURRENT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets current to value 0"]
            impl crate::Resettable for CURRENT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "low_limit (rw) register accessor: Clock lower limit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`low_limit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`low_limit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@low_limit`]
module"]
        pub type LOW_LIMIT = crate::Reg<low_limit::LOW_LIMIT_SPEC>;
        #[doc = "Clock lower limit"]
        pub mod low_limit {
            #[doc = "Register `low_limit` reader"]
            pub type R = crate::R<LOW_LIMIT_SPEC>;
            #[doc = "Register `low_limit` writer"]
            pub type W = crate::W<LOW_LIMIT_SPEC>;
            #[doc = "Field `FREQUENCY` reader - lower frequency"]
            pub type FREQUENCY_R = crate::FieldReader<u32>;
            #[doc = "Field `FREQUENCY` writer - lower frequency"]
            pub type FREQUENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - lower frequency"]
                #[inline(always)]
                pub fn frequency(&self) -> FREQUENCY_R {
                    FREQUENCY_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - lower frequency"]
                #[inline(always)]
                #[must_use]
                pub fn frequency(&mut self) -> FREQUENCY_W<LOW_LIMIT_SPEC> {
                    FREQUENCY_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Clock lower limit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`low_limit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`low_limit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LOW_LIMIT_SPEC;
            impl crate::RegisterSpec for LOW_LIMIT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`low_limit::R`](R) reader structure"]
            impl crate::Readable for LOW_LIMIT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`low_limit::W`](W) writer structure"]
            impl crate::Writable for LOW_LIMIT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets low_limit to value 0xffff_ffff"]
            impl crate::Resettable for LOW_LIMIT_SPEC {
                const RESET_VALUE: u32 = 0xffff_ffff;
            }
        }
        #[doc = "high_limit (rw) register accessor: Clock upper limit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`high_limit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`high_limit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@high_limit`]
module"]
        pub type HIGH_LIMIT = crate::Reg<high_limit::HIGH_LIMIT_SPEC>;
        #[doc = "Clock upper limit"]
        pub mod high_limit {
            #[doc = "Register `high_limit` reader"]
            pub type R = crate::R<HIGH_LIMIT_SPEC>;
            #[doc = "Register `high_limit` writer"]
            pub type W = crate::W<HIGH_LIMIT_SPEC>;
            #[doc = "Field `FREQUENCY` reader - upper frequency"]
            pub type FREQUENCY_R = crate::FieldReader<u32>;
            #[doc = "Field `FREQUENCY` writer - upper frequency"]
            pub type FREQUENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - upper frequency"]
                #[inline(always)]
                pub fn frequency(&self) -> FREQUENCY_R {
                    FREQUENCY_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - upper frequency"]
                #[inline(always)]
                #[must_use]
                pub fn frequency(&mut self) -> FREQUENCY_W<HIGH_LIMIT_SPEC> {
                    FREQUENCY_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "Clock upper limit\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`high_limit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`high_limit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct HIGH_LIMIT_SPEC;
            impl crate::RegisterSpec for HIGH_LIMIT_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`high_limit::R`](R) reader structure"]
            impl crate::Readable for HIGH_LIMIT_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`high_limit::W`](W) writer structure"]
            impl crate::Writable for HIGH_LIMIT_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets high_limit to value 0"]
            impl crate::Resettable for HIGH_LIMIT_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
    #[doc = "no description available"]
    pub use self::cpu::CPU;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod cpu {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct CPU {
            lp: LP,
            lock: LOCK,
            gpr: [GPR; 14],
            wakeup_status: [WAKEUP_STATUS; 4],
            _reserved4: [u8; 0x30],
            wakeup_enable: [WAKEUP_ENABLE; 4],
        }
        impl CPU {
            #[doc = "0x00 - CPU0 LP control"]
            #[inline(always)]
            pub const fn lp(&self) -> &LP {
                &self.lp
            }
            #[doc = "0x04 - CPU0 Lock GPR"]
            #[inline(always)]
            pub const fn lock(&self) -> &LOCK {
                &self.lock
            }
            #[doc = "0x08..0x40 - no description available"]
            #[inline(always)]
            pub const fn gpr(&self, n: usize) -> &GPR {
                &self.gpr[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x08..0x40 - no description available"]
            #[inline(always)]
            pub fn gpr_iter(&self) -> impl Iterator<Item = &GPR> {
                self.gpr.iter()
            }
            #[doc = "0x08 - no description available"]
            #[inline(always)]
            pub const fn gprgpr0(&self) -> &GPR {
                self.gpr(0)
            }
            #[doc = "0x0c - no description available"]
            #[inline(always)]
            pub const fn gprgpr1(&self) -> &GPR {
                self.gpr(1)
            }
            #[doc = "0x10 - no description available"]
            #[inline(always)]
            pub const fn gprgpr2(&self) -> &GPR {
                self.gpr(2)
            }
            #[doc = "0x14 - no description available"]
            #[inline(always)]
            pub const fn gprgpr3(&self) -> &GPR {
                self.gpr(3)
            }
            #[doc = "0x18 - no description available"]
            #[inline(always)]
            pub const fn gprgpr4(&self) -> &GPR {
                self.gpr(4)
            }
            #[doc = "0x1c - no description available"]
            #[inline(always)]
            pub const fn gprgpr5(&self) -> &GPR {
                self.gpr(5)
            }
            #[doc = "0x20 - no description available"]
            #[inline(always)]
            pub const fn gprgpr6(&self) -> &GPR {
                self.gpr(6)
            }
            #[doc = "0x24 - no description available"]
            #[inline(always)]
            pub const fn gprgpr7(&self) -> &GPR {
                self.gpr(7)
            }
            #[doc = "0x28 - no description available"]
            #[inline(always)]
            pub const fn gprgpr8(&self) -> &GPR {
                self.gpr(8)
            }
            #[doc = "0x2c - no description available"]
            #[inline(always)]
            pub const fn gprgpr9(&self) -> &GPR {
                self.gpr(9)
            }
            #[doc = "0x30 - no description available"]
            #[inline(always)]
            pub const fn gprgpr10(&self) -> &GPR {
                self.gpr(10)
            }
            #[doc = "0x34 - no description available"]
            #[inline(always)]
            pub const fn gprgpr11(&self) -> &GPR {
                self.gpr(11)
            }
            #[doc = "0x38 - no description available"]
            #[inline(always)]
            pub const fn gprgpr12(&self) -> &GPR {
                self.gpr(12)
            }
            #[doc = "0x3c - no description available"]
            #[inline(always)]
            pub const fn gprgpr13(&self) -> &GPR {
                self.gpr(13)
            }
            #[doc = "0x40..0x50 - no description available"]
            #[inline(always)]
            pub const fn wakeup_status(&self, n: usize) -> &WAKEUP_STATUS {
                &self.wakeup_status[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x40..0x50 - no description available"]
            #[inline(always)]
            pub fn wakeup_status_iter(&self) -> impl Iterator<Item = &WAKEUP_STATUS> {
                self.wakeup_status.iter()
            }
            #[doc = "0x40 - no description available"]
            #[inline(always)]
            pub const fn wakeup_statusstatus0(&self) -> &WAKEUP_STATUS {
                self.wakeup_status(0)
            }
            #[doc = "0x44 - no description available"]
            #[inline(always)]
            pub const fn wakeup_statusstatus1(&self) -> &WAKEUP_STATUS {
                self.wakeup_status(1)
            }
            #[doc = "0x48 - no description available"]
            #[inline(always)]
            pub const fn wakeup_statusstatus2(&self) -> &WAKEUP_STATUS {
                self.wakeup_status(2)
            }
            #[doc = "0x4c - no description available"]
            #[inline(always)]
            pub const fn wakeup_statusstatus3(&self) -> &WAKEUP_STATUS {
                self.wakeup_status(3)
            }
            #[doc = "0x80..0x90 - no description available"]
            #[inline(always)]
            pub const fn wakeup_enable(&self, n: usize) -> &WAKEUP_ENABLE {
                &self.wakeup_enable[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x80..0x90 - no description available"]
            #[inline(always)]
            pub fn wakeup_enable_iter(&self) -> impl Iterator<Item = &WAKEUP_ENABLE> {
                self.wakeup_enable.iter()
            }
            #[doc = "0x80 - no description available"]
            #[inline(always)]
            pub const fn wakeup_enableenable0(&self) -> &WAKEUP_ENABLE {
                self.wakeup_enable(0)
            }
            #[doc = "0x84 - no description available"]
            #[inline(always)]
            pub const fn wakeup_enableenable1(&self) -> &WAKEUP_ENABLE {
                self.wakeup_enable(1)
            }
            #[doc = "0x88 - no description available"]
            #[inline(always)]
            pub const fn wakeup_enableenable2(&self) -> &WAKEUP_ENABLE {
                self.wakeup_enable(2)
            }
            #[doc = "0x8c - no description available"]
            #[inline(always)]
            pub const fn wakeup_enableenable3(&self) -> &WAKEUP_ENABLE {
                self.wakeup_enable(3)
            }
        }
        #[doc = "LP (rw) register accessor: CPU0 LP control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lp`]
module"]
        pub type LP = crate::Reg<lp::LP_SPEC>;
        #[doc = "CPU0 LP control"]
        pub mod lp {
            #[doc = "Register `LP` reader"]
            pub type R = crate::R<LP_SPEC>;
            #[doc = "Register `LP` writer"]
            pub type W = crate::W<LP_SPEC>;
            #[doc = "Field `MODE` reader - Low power mode, system behavior after WFI 00: CPU clock stop after WFI 01: System enter low power mode after WFI 10: Keep running after WFI 11: reserved"]
            pub type MODE_R = crate::FieldReader;
            #[doc = "Field `MODE` writer - Low power mode, system behavior after WFI 00: CPU clock stop after WFI 01: System enter low power mode after WFI 10: Keep running after WFI 11: reserved"]
            pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `RESET_FLAG` reader - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 0: CPU0 reset not happened 1: CPU0 reset happened"]
            pub type RESET_FLAG_R = crate::BitReader;
            #[doc = "Field `RESET_FLAG` writer - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 0: CPU0 reset not happened 1: CPU0 reset happened"]
            pub type RESET_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SLEEP_FLAG` reader - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 0: CPU0 sleep not happened 1: CPU0 sleep happened"]
            pub type SLEEP_FLAG_R = crate::BitReader;
            #[doc = "Field `SLEEP_FLAG` writer - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 0: CPU0 sleep not happened 1: CPU0 sleep happened"]
            pub type SLEEP_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WAKE_FLAG` reader - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 0: CPU0 wakeup not happened 1: CPU0 wake up happened"]
            pub type WAKE_FLAG_R = crate::BitReader;
            #[doc = "Field `WAKE_FLAG` writer - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 0: CPU0 wakeup not happened 1: CPU0 wake up happened"]
            pub type WAKE_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `EXEC` reader - CPU0 is executing 0: CPU0 is not executing 1: CPU0 is executing"]
            pub type EXEC_R = crate::BitReader;
            #[doc = "Field `WAKE` reader - CPU0 is waking up 0: CPU0 wake up not asserted 1: CPU0 wake up asserted"]
            pub type WAKE_R = crate::BitReader;
            #[doc = "Field `HALT` reader - halt request for CPU0, 0: CPU0 will start to execute after reset or receive wakeup request 1: CPU0 will not start after reset, or wakeup after WFI"]
            pub type HALT_R = crate::BitReader;
            #[doc = "Field `HALT` writer - halt request for CPU0, 0: CPU0 will start to execute after reset or receive wakeup request 1: CPU0 will not start after reset, or wakeup after WFI"]
            pub type HALT_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `WAKE_CNT` reader - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear"]
            pub type WAKE_CNT_R = crate::FieldReader;
            #[doc = "Field `WAKE_CNT` writer - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear"]
            pub type WAKE_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
            impl R {
                #[doc = "Bits 0:1 - Low power mode, system behavior after WFI 00: CPU clock stop after WFI 01: System enter low power mode after WFI 10: Keep running after WFI 11: reserved"]
                #[inline(always)]
                pub fn mode(&self) -> MODE_R {
                    MODE_R::new((self.bits & 3) as u8)
                }
                #[doc = "Bit 8 - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 0: CPU0 reset not happened 1: CPU0 reset happened"]
                #[inline(always)]
                pub fn reset_flag(&self) -> RESET_FLAG_R {
                    RESET_FLAG_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 9 - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 0: CPU0 sleep not happened 1: CPU0 sleep happened"]
                #[inline(always)]
                pub fn sleep_flag(&self) -> SLEEP_FLAG_R {
                    SLEEP_FLAG_R::new(((self.bits >> 9) & 1) != 0)
                }
                #[doc = "Bit 10 - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 0: CPU0 wakeup not happened 1: CPU0 wake up happened"]
                #[inline(always)]
                pub fn wake_flag(&self) -> WAKE_FLAG_R {
                    WAKE_FLAG_R::new(((self.bits >> 10) & 1) != 0)
                }
                #[doc = "Bit 12 - CPU0 is executing 0: CPU0 is not executing 1: CPU0 is executing"]
                #[inline(always)]
                pub fn exec(&self) -> EXEC_R {
                    EXEC_R::new(((self.bits >> 12) & 1) != 0)
                }
                #[doc = "Bit 13 - CPU0 is waking up 0: CPU0 wake up not asserted 1: CPU0 wake up asserted"]
                #[inline(always)]
                pub fn wake(&self) -> WAKE_R {
                    WAKE_R::new(((self.bits >> 13) & 1) != 0)
                }
                #[doc = "Bit 16 - halt request for CPU0, 0: CPU0 will start to execute after reset or receive wakeup request 1: CPU0 will not start after reset, or wakeup after WFI"]
                #[inline(always)]
                pub fn halt(&self) -> HALT_R {
                    HALT_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bits 24:31 - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear"]
                #[inline(always)]
                pub fn wake_cnt(&self) -> WAKE_CNT_R {
                    WAKE_CNT_R::new(((self.bits >> 24) & 0xff) as u8)
                }
            }
            impl W {
                #[doc = "Bits 0:1 - Low power mode, system behavior after WFI 00: CPU clock stop after WFI 01: System enter low power mode after WFI 10: Keep running after WFI 11: reserved"]
                #[inline(always)]
                #[must_use]
                pub fn mode(&mut self) -> MODE_W<LP_SPEC> {
                    MODE_W::new(self, 0)
                }
                #[doc = "Bit 8 - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit 0: CPU0 reset not happened 1: CPU0 reset happened"]
                #[inline(always)]
                #[must_use]
                pub fn reset_flag(&mut self) -> RESET_FLAG_W<LP_SPEC> {
                    RESET_FLAG_W::new(self, 8)
                }
                #[doc = "Bit 9 - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit 0: CPU0 sleep not happened 1: CPU0 sleep happened"]
                #[inline(always)]
                #[must_use]
                pub fn sleep_flag(&mut self) -> SLEEP_FLAG_W<LP_SPEC> {
                    SLEEP_FLAG_W::new(self, 9)
                }
                #[doc = "Bit 10 - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit 0: CPU0 wakeup not happened 1: CPU0 wake up happened"]
                #[inline(always)]
                #[must_use]
                pub fn wake_flag(&mut self) -> WAKE_FLAG_W<LP_SPEC> {
                    WAKE_FLAG_W::new(self, 10)
                }
                #[doc = "Bit 16 - halt request for CPU0, 0: CPU0 will start to execute after reset or receive wakeup request 1: CPU0 will not start after reset, or wakeup after WFI"]
                #[inline(always)]
                #[must_use]
                pub fn halt(&mut self) -> HALT_W<LP_SPEC> {
                    HALT_W::new(self, 16)
                }
                #[doc = "Bits 24:31 - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear"]
                #[inline(always)]
                #[must_use]
                pub fn wake_cnt(&mut self) -> WAKE_CNT_W<LP_SPEC> {
                    WAKE_CNT_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "CPU0 LP control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LP_SPEC;
            impl crate::RegisterSpec for LP_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`lp::R`](R) reader structure"]
            impl crate::Readable for LP_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`lp::W`](W) writer structure"]
            impl crate::Writable for LP_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets LP to value 0x1000"]
            impl crate::Resettable for LP_SPEC {
                const RESET_VALUE: u32 = 0x1000;
            }
        }
        #[doc = "LOCK (rw) register accessor: CPU0 Lock GPR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lock`]
module"]
        pub type LOCK = crate::Reg<lock::LOCK_SPEC>;
        #[doc = "CPU0 Lock GPR"]
        pub mod lock {
            #[doc = "Register `LOCK` reader"]
            pub type R = crate::R<LOCK_SPEC>;
            #[doc = "Register `LOCK` writer"]
            pub type W = crate::W<LOCK_SPEC>;
            #[doc = "Field `LOCK` reader - Lock bit for CPU_LOCK"]
            pub type LOCK_R = crate::BitReader;
            #[doc = "Field `LOCK` writer - Lock bit for CPU_LOCK"]
            pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `GPR` reader - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset"]
            pub type GPR_R = crate::FieldReader<u16>;
            #[doc = "Field `GPR` writer - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset"]
            pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
            impl R {
                #[doc = "Bit 1 - Lock bit for CPU_LOCK"]
                #[inline(always)]
                pub fn lock(&self) -> LOCK_R {
                    LOCK_R::new(((self.bits >> 1) & 1) != 0)
                }
                #[doc = "Bits 2:15 - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset"]
                #[inline(always)]
                pub fn gpr(&self) -> GPR_R {
                    GPR_R::new(((self.bits >> 2) & 0x3fff) as u16)
                }
            }
            impl W {
                #[doc = "Bit 1 - Lock bit for CPU_LOCK"]
                #[inline(always)]
                #[must_use]
                pub fn lock(&mut self) -> LOCK_W<LOCK_SPEC> {
                    LOCK_W::new(self, 1)
                }
                #[doc = "Bits 2:15 - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset"]
                #[inline(always)]
                #[must_use]
                pub fn gpr(&mut self) -> GPR_W<LOCK_SPEC> {
                    GPR_W::new(self, 2)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "CPU0 Lock GPR\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LOCK_SPEC;
            impl crate::RegisterSpec for LOCK_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`lock::R`](R) reader structure"]
            impl crate::Readable for LOCK_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`lock::W`](W) writer structure"]
            impl crate::Writable for LOCK_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets LOCK to value 0"]
            impl crate::Resettable for LOCK_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "GPR (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpr`]
module"]
        pub type GPR = crate::Reg<gpr::GPR_SPEC>;
        #[doc = "no description available"]
        pub mod gpr {
            #[doc = "Register `GPR[%s]` reader"]
            pub type R = crate::R<GPR_SPEC>;
            #[doc = "Register `GPR[%s]` writer"]
            pub type W = crate::W<GPR_SPEC>;
            #[doc = "Field `GPR` reader - register for software to handle resume, can save resume address or status"]
            pub type GPR_R = crate::FieldReader<u32>;
            #[doc = "Field `GPR` writer - register for software to handle resume, can save resume address or status"]
            pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - register for software to handle resume, can save resume address or status"]
                #[inline(always)]
                pub fn gpr(&self) -> GPR_R {
                    GPR_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - register for software to handle resume, can save resume address or status"]
                #[inline(always)]
                #[must_use]
                pub fn gpr(&mut self) -> GPR_W<GPR_SPEC> {
                    GPR_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct GPR_SPEC;
            impl crate::RegisterSpec for GPR_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`gpr::R`](R) reader structure"]
            impl crate::Readable for GPR_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`gpr::W`](W) writer structure"]
            impl crate::Writable for GPR_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets GPR[%s]
to value 0"]
            impl crate::Resettable for GPR_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "WAKEUP_STATUS (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_status`]
module"]
        pub type WAKEUP_STATUS = crate::Reg<wakeup_status::WAKEUP_STATUS_SPEC>;
        #[doc = "no description available"]
        pub mod wakeup_status {
            #[doc = "Register `WAKEUP_STATUS[%s]` reader"]
            pub type R = crate::R<WAKEUP_STATUS_SPEC>;
            #[doc = "Register `WAKEUP_STATUS[%s]` writer"]
            pub type W = crate::W<WAKEUP_STATUS_SPEC>;
            #[doc = "Field `STATUS` reader - IRQ values"]
            pub type STATUS_R = crate::FieldReader<u32>;
            impl R {
                #[doc = "Bits 0:31 - IRQ values"]
                #[inline(always)]
                pub fn status(&self) -> STATUS_R {
                    STATUS_R::new(self.bits)
                }
            }
            impl W {
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct WAKEUP_STATUS_SPEC;
            impl crate::RegisterSpec for WAKEUP_STATUS_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`wakeup_status::R`](R) reader structure"]
            impl crate::Readable for WAKEUP_STATUS_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`wakeup_status::W`](W) writer structure"]
            impl crate::Writable for WAKEUP_STATUS_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets WAKEUP_STATUS[%s]
to value 0"]
            impl crate::Resettable for WAKEUP_STATUS_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "WAKEUP_ENABLE (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_enable`]
module"]
        pub type WAKEUP_ENABLE = crate::Reg<wakeup_enable::WAKEUP_ENABLE_SPEC>;
        #[doc = "no description available"]
        pub mod wakeup_enable {
            #[doc = "Register `WAKEUP_ENABLE[%s]` reader"]
            pub type R = crate::R<WAKEUP_ENABLE_SPEC>;
            #[doc = "Register `WAKEUP_ENABLE[%s]` writer"]
            pub type W = crate::W<WAKEUP_ENABLE_SPEC>;
            #[doc = "Field `ENABLE` reader - IRQ wakeup enable"]
            pub type ENABLE_R = crate::FieldReader<u32>;
            #[doc = "Field `ENABLE` writer - IRQ wakeup enable"]
            pub type ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
            impl R {
                #[doc = "Bits 0:31 - IRQ wakeup enable"]
                #[inline(always)]
                pub fn enable(&self) -> ENABLE_R {
                    ENABLE_R::new(self.bits)
                }
            }
            impl W {
                #[doc = "Bits 0:31 - IRQ wakeup enable"]
                #[inline(always)]
                #[must_use]
                pub fn enable(&mut self) -> ENABLE_W<WAKEUP_ENABLE_SPEC> {
                    ENABLE_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct WAKEUP_ENABLE_SPEC;
            impl crate::RegisterSpec for WAKEUP_ENABLE_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`wakeup_enable::R`](R) reader structure"]
            impl crate::Readable for WAKEUP_ENABLE_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`wakeup_enable::W`](W) writer structure"]
            impl crate::Writable for WAKEUP_ENABLE_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets WAKEUP_ENABLE[%s]
to value 0"]
            impl crate::Resettable for WAKEUP_ENABLE_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "IOC"]
pub struct IOC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for IOC {}
impl IOC {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const ioc::RegisterBlock = 0xf404_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const ioc::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for IOC {
    type Target = ioc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for IOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("IOC").finish()
    }
}
#[doc = "IOC"]
pub mod ioc {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        pad: [PAD; 456],
    }
    impl RegisterBlock {
        #[doc = "0x00..0xe40 - no description available"]
        #[inline(always)]
        pub const fn pad(&self, n: usize) -> &PAD {
            &self.pad[n]
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x00..0xe40 - no description available"]
        #[inline(always)]
        pub fn pad_iter(&self) -> impl Iterator<Item = &PAD> {
            self.pad.iter()
        }
        #[doc = "0x00..0x08 - no description available"]
        #[inline(always)]
        pub const fn padpa00(&self) -> &PAD {
            self.pad(0)
        }
        #[doc = "0x08..0x10 - no description available"]
        #[inline(always)]
        pub const fn padpa01(&self) -> &PAD {
            self.pad(1)
        }
        #[doc = "0x10..0x18 - no description available"]
        #[inline(always)]
        pub const fn padpa02(&self) -> &PAD {
            self.pad(2)
        }
        #[doc = "0x18..0x20 - no description available"]
        #[inline(always)]
        pub const fn padpa03(&self) -> &PAD {
            self.pad(3)
        }
        #[doc = "0x20..0x28 - no description available"]
        #[inline(always)]
        pub const fn padpa04(&self) -> &PAD {
            self.pad(4)
        }
        #[doc = "0x28..0x30 - no description available"]
        #[inline(always)]
        pub const fn padpa05(&self) -> &PAD {
            self.pad(5)
        }
        #[doc = "0x30..0x38 - no description available"]
        #[inline(always)]
        pub const fn padpa06(&self) -> &PAD {
            self.pad(6)
        }
        #[doc = "0x38..0x40 - no description available"]
        #[inline(always)]
        pub const fn padpa07(&self) -> &PAD {
            self.pad(7)
        }
        #[doc = "0x40..0x48 - no description available"]
        #[inline(always)]
        pub const fn padpa08(&self) -> &PAD {
            self.pad(8)
        }
        #[doc = "0x48..0x50 - no description available"]
        #[inline(always)]
        pub const fn padpa09(&self) -> &PAD {
            self.pad(9)
        }
        #[doc = "0x50..0x58 - no description available"]
        #[inline(always)]
        pub const fn padpa10(&self) -> &PAD {
            self.pad(10)
        }
        #[doc = "0x58..0x60 - no description available"]
        #[inline(always)]
        pub const fn padpa11(&self) -> &PAD {
            self.pad(11)
        }
        #[doc = "0x60..0x68 - no description available"]
        #[inline(always)]
        pub const fn padpa12(&self) -> &PAD {
            self.pad(12)
        }
        #[doc = "0x68..0x70 - no description available"]
        #[inline(always)]
        pub const fn padpa13(&self) -> &PAD {
            self.pad(13)
        }
        #[doc = "0x70..0x78 - no description available"]
        #[inline(always)]
        pub const fn padpa14(&self) -> &PAD {
            self.pad(14)
        }
        #[doc = "0x78..0x80 - no description available"]
        #[inline(always)]
        pub const fn padpa15(&self) -> &PAD {
            self.pad(15)
        }
        #[doc = "0x80..0x88 - no description available"]
        #[inline(always)]
        pub const fn padpa16(&self) -> &PAD {
            self.pad(16)
        }
        #[doc = "0x88..0x90 - no description available"]
        #[inline(always)]
        pub const fn padpa17(&self) -> &PAD {
            self.pad(17)
        }
        #[doc = "0x90..0x98 - no description available"]
        #[inline(always)]
        pub const fn padpa18(&self) -> &PAD {
            self.pad(18)
        }
        #[doc = "0x98..0xa0 - no description available"]
        #[inline(always)]
        pub const fn padpa19(&self) -> &PAD {
            self.pad(19)
        }
        #[doc = "0xa0..0xa8 - no description available"]
        #[inline(always)]
        pub const fn padpa20(&self) -> &PAD {
            self.pad(20)
        }
        #[doc = "0xa8..0xb0 - no description available"]
        #[inline(always)]
        pub const fn padpa21(&self) -> &PAD {
            self.pad(21)
        }
        #[doc = "0xb0..0xb8 - no description available"]
        #[inline(always)]
        pub const fn padpa22(&self) -> &PAD {
            self.pad(22)
        }
        #[doc = "0xb8..0xc0 - no description available"]
        #[inline(always)]
        pub const fn padpa23(&self) -> &PAD {
            self.pad(23)
        }
        #[doc = "0xc0..0xc8 - no description available"]
        #[inline(always)]
        pub const fn padpa24(&self) -> &PAD {
            self.pad(24)
        }
        #[doc = "0xc8..0xd0 - no description available"]
        #[inline(always)]
        pub const fn padpa25(&self) -> &PAD {
            self.pad(25)
        }
        #[doc = "0xd0..0xd8 - no description available"]
        #[inline(always)]
        pub const fn padpa26(&self) -> &PAD {
            self.pad(26)
        }
        #[doc = "0xd8..0xe0 - no description available"]
        #[inline(always)]
        pub const fn padpa27(&self) -> &PAD {
            self.pad(27)
        }
        #[doc = "0xe0..0xe8 - no description available"]
        #[inline(always)]
        pub const fn padpa28(&self) -> &PAD {
            self.pad(28)
        }
        #[doc = "0xe8..0xf0 - no description available"]
        #[inline(always)]
        pub const fn padpa29(&self) -> &PAD {
            self.pad(29)
        }
        #[doc = "0xf0..0xf8 - no description available"]
        #[inline(always)]
        pub const fn padpa30(&self) -> &PAD {
            self.pad(30)
        }
        #[doc = "0xf8..0x100 - no description available"]
        #[inline(always)]
        pub const fn padpa31(&self) -> &PAD {
            self.pad(31)
        }
        #[doc = "0x100..0x108 - no description available"]
        #[inline(always)]
        pub const fn padpb00(&self) -> &PAD {
            self.pad(32)
        }
        #[doc = "0x108..0x110 - no description available"]
        #[inline(always)]
        pub const fn padpb01(&self) -> &PAD {
            self.pad(33)
        }
        #[doc = "0x110..0x118 - no description available"]
        #[inline(always)]
        pub const fn padpb02(&self) -> &PAD {
            self.pad(34)
        }
        #[doc = "0x118..0x120 - no description available"]
        #[inline(always)]
        pub const fn padpb03(&self) -> &PAD {
            self.pad(35)
        }
        #[doc = "0x120..0x128 - no description available"]
        #[inline(always)]
        pub const fn padpb04(&self) -> &PAD {
            self.pad(36)
        }
        #[doc = "0x128..0x130 - no description available"]
        #[inline(always)]
        pub const fn padpb05(&self) -> &PAD {
            self.pad(37)
        }
        #[doc = "0x130..0x138 - no description available"]
        #[inline(always)]
        pub const fn padpb06(&self) -> &PAD {
            self.pad(38)
        }
        #[doc = "0x138..0x140 - no description available"]
        #[inline(always)]
        pub const fn padpb07(&self) -> &PAD {
            self.pad(39)
        }
        #[doc = "0x140..0x148 - no description available"]
        #[inline(always)]
        pub const fn padpb08(&self) -> &PAD {
            self.pad(40)
        }
        #[doc = "0x148..0x150 - no description available"]
        #[inline(always)]
        pub const fn padpb09(&self) -> &PAD {
            self.pad(41)
        }
        #[doc = "0x150..0x158 - no description available"]
        #[inline(always)]
        pub const fn padpb10(&self) -> &PAD {
            self.pad(42)
        }
        #[doc = "0x158..0x160 - no description available"]
        #[inline(always)]
        pub const fn padpb11(&self) -> &PAD {
            self.pad(43)
        }
        #[doc = "0x160..0x168 - no description available"]
        #[inline(always)]
        pub const fn padpb12(&self) -> &PAD {
            self.pad(44)
        }
        #[doc = "0x168..0x170 - no description available"]
        #[inline(always)]
        pub const fn padpb13(&self) -> &PAD {
            self.pad(45)
        }
        #[doc = "0x170..0x178 - no description available"]
        #[inline(always)]
        pub const fn padpb14(&self) -> &PAD {
            self.pad(46)
        }
        #[doc = "0x178..0x180 - no description available"]
        #[inline(always)]
        pub const fn padpb15(&self) -> &PAD {
            self.pad(47)
        }
        #[doc = "0x180..0x188 - no description available"]
        #[inline(always)]
        pub const fn padrsv49(&self) -> &PAD {
            self.pad(48)
        }
        #[doc = "0x188..0x190 - no description available"]
        #[inline(always)]
        pub const fn padrsv50(&self) -> &PAD {
            self.pad(49)
        }
        #[doc = "0x190..0x198 - no description available"]
        #[inline(always)]
        pub const fn padrsv51(&self) -> &PAD {
            self.pad(50)
        }
        #[doc = "0x198..0x1a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv52(&self) -> &PAD {
            self.pad(51)
        }
        #[doc = "0x1a0..0x1a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv53(&self) -> &PAD {
            self.pad(52)
        }
        #[doc = "0x1a8..0x1b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv54(&self) -> &PAD {
            self.pad(53)
        }
        #[doc = "0x1b0..0x1b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv55(&self) -> &PAD {
            self.pad(54)
        }
        #[doc = "0x1b8..0x1c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv56(&self) -> &PAD {
            self.pad(55)
        }
        #[doc = "0x1c0..0x1c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv57(&self) -> &PAD {
            self.pad(56)
        }
        #[doc = "0x1c8..0x1d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv58(&self) -> &PAD {
            self.pad(57)
        }
        #[doc = "0x1d0..0x1d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv59(&self) -> &PAD {
            self.pad(58)
        }
        #[doc = "0x1d8..0x1e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv60(&self) -> &PAD {
            self.pad(59)
        }
        #[doc = "0x1e0..0x1e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv61(&self) -> &PAD {
            self.pad(60)
        }
        #[doc = "0x1e8..0x1f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv62(&self) -> &PAD {
            self.pad(61)
        }
        #[doc = "0x1f0..0x1f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv63(&self) -> &PAD {
            self.pad(62)
        }
        #[doc = "0x1f8..0x200 - no description available"]
        #[inline(always)]
        pub const fn padrsv64(&self) -> &PAD {
            self.pad(63)
        }
        #[doc = "0x200..0x208 - no description available"]
        #[inline(always)]
        pub const fn padrsv65(&self) -> &PAD {
            self.pad(64)
        }
        #[doc = "0x208..0x210 - no description available"]
        #[inline(always)]
        pub const fn padrsv66(&self) -> &PAD {
            self.pad(65)
        }
        #[doc = "0x210..0x218 - no description available"]
        #[inline(always)]
        pub const fn padrsv67(&self) -> &PAD {
            self.pad(66)
        }
        #[doc = "0x218..0x220 - no description available"]
        #[inline(always)]
        pub const fn padrsv68(&self) -> &PAD {
            self.pad(67)
        }
        #[doc = "0x220..0x228 - no description available"]
        #[inline(always)]
        pub const fn padrsv69(&self) -> &PAD {
            self.pad(68)
        }
        #[doc = "0x228..0x230 - no description available"]
        #[inline(always)]
        pub const fn padrsv70(&self) -> &PAD {
            self.pad(69)
        }
        #[doc = "0x230..0x238 - no description available"]
        #[inline(always)]
        pub const fn padrsv71(&self) -> &PAD {
            self.pad(70)
        }
        #[doc = "0x238..0x240 - no description available"]
        #[inline(always)]
        pub const fn padrsv72(&self) -> &PAD {
            self.pad(71)
        }
        #[doc = "0x240..0x248 - no description available"]
        #[inline(always)]
        pub const fn padrsv73(&self) -> &PAD {
            self.pad(72)
        }
        #[doc = "0x248..0x250 - no description available"]
        #[inline(always)]
        pub const fn padrsv74(&self) -> &PAD {
            self.pad(73)
        }
        #[doc = "0x250..0x258 - no description available"]
        #[inline(always)]
        pub const fn padrsv75(&self) -> &PAD {
            self.pad(74)
        }
        #[doc = "0x258..0x260 - no description available"]
        #[inline(always)]
        pub const fn padrsv76(&self) -> &PAD {
            self.pad(75)
        }
        #[doc = "0x260..0x268 - no description available"]
        #[inline(always)]
        pub const fn padrsv77(&self) -> &PAD {
            self.pad(76)
        }
        #[doc = "0x268..0x270 - no description available"]
        #[inline(always)]
        pub const fn padrsv78(&self) -> &PAD {
            self.pad(77)
        }
        #[doc = "0x270..0x278 - no description available"]
        #[inline(always)]
        pub const fn padrsv79(&self) -> &PAD {
            self.pad(78)
        }
        #[doc = "0x278..0x280 - no description available"]
        #[inline(always)]
        pub const fn padrsv80(&self) -> &PAD {
            self.pad(79)
        }
        #[doc = "0x280..0x288 - no description available"]
        #[inline(always)]
        pub const fn padrsv81(&self) -> &PAD {
            self.pad(80)
        }
        #[doc = "0x288..0x290 - no description available"]
        #[inline(always)]
        pub const fn padrsv82(&self) -> &PAD {
            self.pad(81)
        }
        #[doc = "0x290..0x298 - no description available"]
        #[inline(always)]
        pub const fn padrsv83(&self) -> &PAD {
            self.pad(82)
        }
        #[doc = "0x298..0x2a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv84(&self) -> &PAD {
            self.pad(83)
        }
        #[doc = "0x2a0..0x2a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv85(&self) -> &PAD {
            self.pad(84)
        }
        #[doc = "0x2a8..0x2b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv86(&self) -> &PAD {
            self.pad(85)
        }
        #[doc = "0x2b0..0x2b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv87(&self) -> &PAD {
            self.pad(86)
        }
        #[doc = "0x2b8..0x2c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv88(&self) -> &PAD {
            self.pad(87)
        }
        #[doc = "0x2c0..0x2c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv89(&self) -> &PAD {
            self.pad(88)
        }
        #[doc = "0x2c8..0x2d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv90(&self) -> &PAD {
            self.pad(89)
        }
        #[doc = "0x2d0..0x2d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv91(&self) -> &PAD {
            self.pad(90)
        }
        #[doc = "0x2d8..0x2e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv92(&self) -> &PAD {
            self.pad(91)
        }
        #[doc = "0x2e0..0x2e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv93(&self) -> &PAD {
            self.pad(92)
        }
        #[doc = "0x2e8..0x2f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv94(&self) -> &PAD {
            self.pad(93)
        }
        #[doc = "0x2f0..0x2f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv95(&self) -> &PAD {
            self.pad(94)
        }
        #[doc = "0x2f8..0x300 - no description available"]
        #[inline(always)]
        pub const fn padrsv96(&self) -> &PAD {
            self.pad(95)
        }
        #[doc = "0x300..0x308 - no description available"]
        #[inline(always)]
        pub const fn padrsv97(&self) -> &PAD {
            self.pad(96)
        }
        #[doc = "0x308..0x310 - no description available"]
        #[inline(always)]
        pub const fn padrsv98(&self) -> &PAD {
            self.pad(97)
        }
        #[doc = "0x310..0x318 - no description available"]
        #[inline(always)]
        pub const fn padrsv99(&self) -> &PAD {
            self.pad(98)
        }
        #[doc = "0x318..0x320 - no description available"]
        #[inline(always)]
        pub const fn padrsv100(&self) -> &PAD {
            self.pad(99)
        }
        #[doc = "0x320..0x328 - no description available"]
        #[inline(always)]
        pub const fn padrsv101(&self) -> &PAD {
            self.pad(100)
        }
        #[doc = "0x328..0x330 - no description available"]
        #[inline(always)]
        pub const fn padrsv102(&self) -> &PAD {
            self.pad(101)
        }
        #[doc = "0x330..0x338 - no description available"]
        #[inline(always)]
        pub const fn padrsv103(&self) -> &PAD {
            self.pad(102)
        }
        #[doc = "0x338..0x340 - no description available"]
        #[inline(always)]
        pub const fn padrsv104(&self) -> &PAD {
            self.pad(103)
        }
        #[doc = "0x340..0x348 - no description available"]
        #[inline(always)]
        pub const fn padrsv105(&self) -> &PAD {
            self.pad(104)
        }
        #[doc = "0x348..0x350 - no description available"]
        #[inline(always)]
        pub const fn padrsv106(&self) -> &PAD {
            self.pad(105)
        }
        #[doc = "0x350..0x358 - no description available"]
        #[inline(always)]
        pub const fn padrsv107(&self) -> &PAD {
            self.pad(106)
        }
        #[doc = "0x358..0x360 - no description available"]
        #[inline(always)]
        pub const fn padrsv108(&self) -> &PAD {
            self.pad(107)
        }
        #[doc = "0x360..0x368 - no description available"]
        #[inline(always)]
        pub const fn padrsv109(&self) -> &PAD {
            self.pad(108)
        }
        #[doc = "0x368..0x370 - no description available"]
        #[inline(always)]
        pub const fn padrsv110(&self) -> &PAD {
            self.pad(109)
        }
        #[doc = "0x370..0x378 - no description available"]
        #[inline(always)]
        pub const fn padrsv111(&self) -> &PAD {
            self.pad(110)
        }
        #[doc = "0x378..0x380 - no description available"]
        #[inline(always)]
        pub const fn padrsv112(&self) -> &PAD {
            self.pad(111)
        }
        #[doc = "0x380..0x388 - no description available"]
        #[inline(always)]
        pub const fn padrsv113(&self) -> &PAD {
            self.pad(112)
        }
        #[doc = "0x388..0x390 - no description available"]
        #[inline(always)]
        pub const fn padrsv114(&self) -> &PAD {
            self.pad(113)
        }
        #[doc = "0x390..0x398 - no description available"]
        #[inline(always)]
        pub const fn padrsv115(&self) -> &PAD {
            self.pad(114)
        }
        #[doc = "0x398..0x3a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv116(&self) -> &PAD {
            self.pad(115)
        }
        #[doc = "0x3a0..0x3a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv117(&self) -> &PAD {
            self.pad(116)
        }
        #[doc = "0x3a8..0x3b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv118(&self) -> &PAD {
            self.pad(117)
        }
        #[doc = "0x3b0..0x3b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv119(&self) -> &PAD {
            self.pad(118)
        }
        #[doc = "0x3b8..0x3c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv120(&self) -> &PAD {
            self.pad(119)
        }
        #[doc = "0x3c0..0x3c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv121(&self) -> &PAD {
            self.pad(120)
        }
        #[doc = "0x3c8..0x3d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv122(&self) -> &PAD {
            self.pad(121)
        }
        #[doc = "0x3d0..0x3d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv123(&self) -> &PAD {
            self.pad(122)
        }
        #[doc = "0x3d8..0x3e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv124(&self) -> &PAD {
            self.pad(123)
        }
        #[doc = "0x3e0..0x3e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv125(&self) -> &PAD {
            self.pad(124)
        }
        #[doc = "0x3e8..0x3f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv126(&self) -> &PAD {
            self.pad(125)
        }
        #[doc = "0x3f0..0x3f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv127(&self) -> &PAD {
            self.pad(126)
        }
        #[doc = "0x3f8..0x400 - no description available"]
        #[inline(always)]
        pub const fn padrsv128(&self) -> &PAD {
            self.pad(127)
        }
        #[doc = "0x400..0x408 - no description available"]
        #[inline(always)]
        pub const fn padrsv129(&self) -> &PAD {
            self.pad(128)
        }
        #[doc = "0x408..0x410 - no description available"]
        #[inline(always)]
        pub const fn padrsv130(&self) -> &PAD {
            self.pad(129)
        }
        #[doc = "0x410..0x418 - no description available"]
        #[inline(always)]
        pub const fn padrsv131(&self) -> &PAD {
            self.pad(130)
        }
        #[doc = "0x418..0x420 - no description available"]
        #[inline(always)]
        pub const fn padrsv132(&self) -> &PAD {
            self.pad(131)
        }
        #[doc = "0x420..0x428 - no description available"]
        #[inline(always)]
        pub const fn padrsv133(&self) -> &PAD {
            self.pad(132)
        }
        #[doc = "0x428..0x430 - no description available"]
        #[inline(always)]
        pub const fn padrsv134(&self) -> &PAD {
            self.pad(133)
        }
        #[doc = "0x430..0x438 - no description available"]
        #[inline(always)]
        pub const fn padrsv135(&self) -> &PAD {
            self.pad(134)
        }
        #[doc = "0x438..0x440 - no description available"]
        #[inline(always)]
        pub const fn padrsv136(&self) -> &PAD {
            self.pad(135)
        }
        #[doc = "0x440..0x448 - no description available"]
        #[inline(always)]
        pub const fn padrsv137(&self) -> &PAD {
            self.pad(136)
        }
        #[doc = "0x448..0x450 - no description available"]
        #[inline(always)]
        pub const fn padrsv138(&self) -> &PAD {
            self.pad(137)
        }
        #[doc = "0x450..0x458 - no description available"]
        #[inline(always)]
        pub const fn padrsv139(&self) -> &PAD {
            self.pad(138)
        }
        #[doc = "0x458..0x460 - no description available"]
        #[inline(always)]
        pub const fn padrsv140(&self) -> &PAD {
            self.pad(139)
        }
        #[doc = "0x460..0x468 - no description available"]
        #[inline(always)]
        pub const fn padrsv141(&self) -> &PAD {
            self.pad(140)
        }
        #[doc = "0x468..0x470 - no description available"]
        #[inline(always)]
        pub const fn padrsv142(&self) -> &PAD {
            self.pad(141)
        }
        #[doc = "0x470..0x478 - no description available"]
        #[inline(always)]
        pub const fn padrsv143(&self) -> &PAD {
            self.pad(142)
        }
        #[doc = "0x478..0x480 - no description available"]
        #[inline(always)]
        pub const fn padrsv144(&self) -> &PAD {
            self.pad(143)
        }
        #[doc = "0x480..0x488 - no description available"]
        #[inline(always)]
        pub const fn padrsv145(&self) -> &PAD {
            self.pad(144)
        }
        #[doc = "0x488..0x490 - no description available"]
        #[inline(always)]
        pub const fn padrsv146(&self) -> &PAD {
            self.pad(145)
        }
        #[doc = "0x490..0x498 - no description available"]
        #[inline(always)]
        pub const fn padrsv147(&self) -> &PAD {
            self.pad(146)
        }
        #[doc = "0x498..0x4a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv148(&self) -> &PAD {
            self.pad(147)
        }
        #[doc = "0x4a0..0x4a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv149(&self) -> &PAD {
            self.pad(148)
        }
        #[doc = "0x4a8..0x4b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv150(&self) -> &PAD {
            self.pad(149)
        }
        #[doc = "0x4b0..0x4b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv151(&self) -> &PAD {
            self.pad(150)
        }
        #[doc = "0x4b8..0x4c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv152(&self) -> &PAD {
            self.pad(151)
        }
        #[doc = "0x4c0..0x4c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv153(&self) -> &PAD {
            self.pad(152)
        }
        #[doc = "0x4c8..0x4d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv154(&self) -> &PAD {
            self.pad(153)
        }
        #[doc = "0x4d0..0x4d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv155(&self) -> &PAD {
            self.pad(154)
        }
        #[doc = "0x4d8..0x4e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv156(&self) -> &PAD {
            self.pad(155)
        }
        #[doc = "0x4e0..0x4e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv157(&self) -> &PAD {
            self.pad(156)
        }
        #[doc = "0x4e8..0x4f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv158(&self) -> &PAD {
            self.pad(157)
        }
        #[doc = "0x4f0..0x4f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv159(&self) -> &PAD {
            self.pad(158)
        }
        #[doc = "0x4f8..0x500 - no description available"]
        #[inline(always)]
        pub const fn padrsv160(&self) -> &PAD {
            self.pad(159)
        }
        #[doc = "0x500..0x508 - no description available"]
        #[inline(always)]
        pub const fn padrsv161(&self) -> &PAD {
            self.pad(160)
        }
        #[doc = "0x508..0x510 - no description available"]
        #[inline(always)]
        pub const fn padrsv162(&self) -> &PAD {
            self.pad(161)
        }
        #[doc = "0x510..0x518 - no description available"]
        #[inline(always)]
        pub const fn padrsv163(&self) -> &PAD {
            self.pad(162)
        }
        #[doc = "0x518..0x520 - no description available"]
        #[inline(always)]
        pub const fn padrsv164(&self) -> &PAD {
            self.pad(163)
        }
        #[doc = "0x520..0x528 - no description available"]
        #[inline(always)]
        pub const fn padrsv165(&self) -> &PAD {
            self.pad(164)
        }
        #[doc = "0x528..0x530 - no description available"]
        #[inline(always)]
        pub const fn padrsv166(&self) -> &PAD {
            self.pad(165)
        }
        #[doc = "0x530..0x538 - no description available"]
        #[inline(always)]
        pub const fn padrsv167(&self) -> &PAD {
            self.pad(166)
        }
        #[doc = "0x538..0x540 - no description available"]
        #[inline(always)]
        pub const fn padrsv168(&self) -> &PAD {
            self.pad(167)
        }
        #[doc = "0x540..0x548 - no description available"]
        #[inline(always)]
        pub const fn padrsv169(&self) -> &PAD {
            self.pad(168)
        }
        #[doc = "0x548..0x550 - no description available"]
        #[inline(always)]
        pub const fn padrsv170(&self) -> &PAD {
            self.pad(169)
        }
        #[doc = "0x550..0x558 - no description available"]
        #[inline(always)]
        pub const fn padrsv171(&self) -> &PAD {
            self.pad(170)
        }
        #[doc = "0x558..0x560 - no description available"]
        #[inline(always)]
        pub const fn padrsv172(&self) -> &PAD {
            self.pad(171)
        }
        #[doc = "0x560..0x568 - no description available"]
        #[inline(always)]
        pub const fn padrsv173(&self) -> &PAD {
            self.pad(172)
        }
        #[doc = "0x568..0x570 - no description available"]
        #[inline(always)]
        pub const fn padrsv174(&self) -> &PAD {
            self.pad(173)
        }
        #[doc = "0x570..0x578 - no description available"]
        #[inline(always)]
        pub const fn padrsv175(&self) -> &PAD {
            self.pad(174)
        }
        #[doc = "0x578..0x580 - no description available"]
        #[inline(always)]
        pub const fn padrsv176(&self) -> &PAD {
            self.pad(175)
        }
        #[doc = "0x580..0x588 - no description available"]
        #[inline(always)]
        pub const fn padrsv177(&self) -> &PAD {
            self.pad(176)
        }
        #[doc = "0x588..0x590 - no description available"]
        #[inline(always)]
        pub const fn padrsv178(&self) -> &PAD {
            self.pad(177)
        }
        #[doc = "0x590..0x598 - no description available"]
        #[inline(always)]
        pub const fn padrsv179(&self) -> &PAD {
            self.pad(178)
        }
        #[doc = "0x598..0x5a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv180(&self) -> &PAD {
            self.pad(179)
        }
        #[doc = "0x5a0..0x5a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv181(&self) -> &PAD {
            self.pad(180)
        }
        #[doc = "0x5a8..0x5b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv182(&self) -> &PAD {
            self.pad(181)
        }
        #[doc = "0x5b0..0x5b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv183(&self) -> &PAD {
            self.pad(182)
        }
        #[doc = "0x5b8..0x5c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv184(&self) -> &PAD {
            self.pad(183)
        }
        #[doc = "0x5c0..0x5c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv185(&self) -> &PAD {
            self.pad(184)
        }
        #[doc = "0x5c8..0x5d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv186(&self) -> &PAD {
            self.pad(185)
        }
        #[doc = "0x5d0..0x5d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv187(&self) -> &PAD {
            self.pad(186)
        }
        #[doc = "0x5d8..0x5e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv188(&self) -> &PAD {
            self.pad(187)
        }
        #[doc = "0x5e0..0x5e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv189(&self) -> &PAD {
            self.pad(188)
        }
        #[doc = "0x5e8..0x5f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv190(&self) -> &PAD {
            self.pad(189)
        }
        #[doc = "0x5f0..0x5f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv191(&self) -> &PAD {
            self.pad(190)
        }
        #[doc = "0x5f8..0x600 - no description available"]
        #[inline(always)]
        pub const fn padrsv192(&self) -> &PAD {
            self.pad(191)
        }
        #[doc = "0x600..0x608 - no description available"]
        #[inline(always)]
        pub const fn padrsv193(&self) -> &PAD {
            self.pad(192)
        }
        #[doc = "0x608..0x610 - no description available"]
        #[inline(always)]
        pub const fn padrsv194(&self) -> &PAD {
            self.pad(193)
        }
        #[doc = "0x610..0x618 - no description available"]
        #[inline(always)]
        pub const fn padrsv195(&self) -> &PAD {
            self.pad(194)
        }
        #[doc = "0x618..0x620 - no description available"]
        #[inline(always)]
        pub const fn padrsv196(&self) -> &PAD {
            self.pad(195)
        }
        #[doc = "0x620..0x628 - no description available"]
        #[inline(always)]
        pub const fn padrsv197(&self) -> &PAD {
            self.pad(196)
        }
        #[doc = "0x628..0x630 - no description available"]
        #[inline(always)]
        pub const fn padrsv198(&self) -> &PAD {
            self.pad(197)
        }
        #[doc = "0x630..0x638 - no description available"]
        #[inline(always)]
        pub const fn padrsv199(&self) -> &PAD {
            self.pad(198)
        }
        #[doc = "0x638..0x640 - no description available"]
        #[inline(always)]
        pub const fn padrsv200(&self) -> &PAD {
            self.pad(199)
        }
        #[doc = "0x640..0x648 - no description available"]
        #[inline(always)]
        pub const fn padrsv201(&self) -> &PAD {
            self.pad(200)
        }
        #[doc = "0x648..0x650 - no description available"]
        #[inline(always)]
        pub const fn padrsv202(&self) -> &PAD {
            self.pad(201)
        }
        #[doc = "0x650..0x658 - no description available"]
        #[inline(always)]
        pub const fn padrsv203(&self) -> &PAD {
            self.pad(202)
        }
        #[doc = "0x658..0x660 - no description available"]
        #[inline(always)]
        pub const fn padrsv204(&self) -> &PAD {
            self.pad(203)
        }
        #[doc = "0x660..0x668 - no description available"]
        #[inline(always)]
        pub const fn padrsv205(&self) -> &PAD {
            self.pad(204)
        }
        #[doc = "0x668..0x670 - no description available"]
        #[inline(always)]
        pub const fn padrsv206(&self) -> &PAD {
            self.pad(205)
        }
        #[doc = "0x670..0x678 - no description available"]
        #[inline(always)]
        pub const fn padrsv207(&self) -> &PAD {
            self.pad(206)
        }
        #[doc = "0x678..0x680 - no description available"]
        #[inline(always)]
        pub const fn padrsv208(&self) -> &PAD {
            self.pad(207)
        }
        #[doc = "0x680..0x688 - no description available"]
        #[inline(always)]
        pub const fn padrsv209(&self) -> &PAD {
            self.pad(208)
        }
        #[doc = "0x688..0x690 - no description available"]
        #[inline(always)]
        pub const fn padrsv210(&self) -> &PAD {
            self.pad(209)
        }
        #[doc = "0x690..0x698 - no description available"]
        #[inline(always)]
        pub const fn padrsv211(&self) -> &PAD {
            self.pad(210)
        }
        #[doc = "0x698..0x6a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv212(&self) -> &PAD {
            self.pad(211)
        }
        #[doc = "0x6a0..0x6a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv213(&self) -> &PAD {
            self.pad(212)
        }
        #[doc = "0x6a8..0x6b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv214(&self) -> &PAD {
            self.pad(213)
        }
        #[doc = "0x6b0..0x6b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv215(&self) -> &PAD {
            self.pad(214)
        }
        #[doc = "0x6b8..0x6c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv216(&self) -> &PAD {
            self.pad(215)
        }
        #[doc = "0x6c0..0x6c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv217(&self) -> &PAD {
            self.pad(216)
        }
        #[doc = "0x6c8..0x6d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv218(&self) -> &PAD {
            self.pad(217)
        }
        #[doc = "0x6d0..0x6d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv219(&self) -> &PAD {
            self.pad(218)
        }
        #[doc = "0x6d8..0x6e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv220(&self) -> &PAD {
            self.pad(219)
        }
        #[doc = "0x6e0..0x6e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv221(&self) -> &PAD {
            self.pad(220)
        }
        #[doc = "0x6e8..0x6f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv222(&self) -> &PAD {
            self.pad(221)
        }
        #[doc = "0x6f0..0x6f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv223(&self) -> &PAD {
            self.pad(222)
        }
        #[doc = "0x6f8..0x700 - no description available"]
        #[inline(always)]
        pub const fn padrsv224(&self) -> &PAD {
            self.pad(223)
        }
        #[doc = "0x700..0x708 - no description available"]
        #[inline(always)]
        pub const fn padrsv225(&self) -> &PAD {
            self.pad(224)
        }
        #[doc = "0x708..0x710 - no description available"]
        #[inline(always)]
        pub const fn padrsv226(&self) -> &PAD {
            self.pad(225)
        }
        #[doc = "0x710..0x718 - no description available"]
        #[inline(always)]
        pub const fn padrsv227(&self) -> &PAD {
            self.pad(226)
        }
        #[doc = "0x718..0x720 - no description available"]
        #[inline(always)]
        pub const fn padrsv228(&self) -> &PAD {
            self.pad(227)
        }
        #[doc = "0x720..0x728 - no description available"]
        #[inline(always)]
        pub const fn padrsv229(&self) -> &PAD {
            self.pad(228)
        }
        #[doc = "0x728..0x730 - no description available"]
        #[inline(always)]
        pub const fn padrsv230(&self) -> &PAD {
            self.pad(229)
        }
        #[doc = "0x730..0x738 - no description available"]
        #[inline(always)]
        pub const fn padrsv231(&self) -> &PAD {
            self.pad(230)
        }
        #[doc = "0x738..0x740 - no description available"]
        #[inline(always)]
        pub const fn padrsv232(&self) -> &PAD {
            self.pad(231)
        }
        #[doc = "0x740..0x748 - no description available"]
        #[inline(always)]
        pub const fn padrsv233(&self) -> &PAD {
            self.pad(232)
        }
        #[doc = "0x748..0x750 - no description available"]
        #[inline(always)]
        pub const fn padrsv234(&self) -> &PAD {
            self.pad(233)
        }
        #[doc = "0x750..0x758 - no description available"]
        #[inline(always)]
        pub const fn padrsv235(&self) -> &PAD {
            self.pad(234)
        }
        #[doc = "0x758..0x760 - no description available"]
        #[inline(always)]
        pub const fn padrsv236(&self) -> &PAD {
            self.pad(235)
        }
        #[doc = "0x760..0x768 - no description available"]
        #[inline(always)]
        pub const fn padrsv237(&self) -> &PAD {
            self.pad(236)
        }
        #[doc = "0x768..0x770 - no description available"]
        #[inline(always)]
        pub const fn padrsv238(&self) -> &PAD {
            self.pad(237)
        }
        #[doc = "0x770..0x778 - no description available"]
        #[inline(always)]
        pub const fn padrsv239(&self) -> &PAD {
            self.pad(238)
        }
        #[doc = "0x778..0x780 - no description available"]
        #[inline(always)]
        pub const fn padrsv240(&self) -> &PAD {
            self.pad(239)
        }
        #[doc = "0x780..0x788 - no description available"]
        #[inline(always)]
        pub const fn padrsv241(&self) -> &PAD {
            self.pad(240)
        }
        #[doc = "0x788..0x790 - no description available"]
        #[inline(always)]
        pub const fn padrsv242(&self) -> &PAD {
            self.pad(241)
        }
        #[doc = "0x790..0x798 - no description available"]
        #[inline(always)]
        pub const fn padrsv243(&self) -> &PAD {
            self.pad(242)
        }
        #[doc = "0x798..0x7a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv244(&self) -> &PAD {
            self.pad(243)
        }
        #[doc = "0x7a0..0x7a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv245(&self) -> &PAD {
            self.pad(244)
        }
        #[doc = "0x7a8..0x7b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv246(&self) -> &PAD {
            self.pad(245)
        }
        #[doc = "0x7b0..0x7b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv247(&self) -> &PAD {
            self.pad(246)
        }
        #[doc = "0x7b8..0x7c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv248(&self) -> &PAD {
            self.pad(247)
        }
        #[doc = "0x7c0..0x7c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv249(&self) -> &PAD {
            self.pad(248)
        }
        #[doc = "0x7c8..0x7d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv250(&self) -> &PAD {
            self.pad(249)
        }
        #[doc = "0x7d0..0x7d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv251(&self) -> &PAD {
            self.pad(250)
        }
        #[doc = "0x7d8..0x7e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv252(&self) -> &PAD {
            self.pad(251)
        }
        #[doc = "0x7e0..0x7e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv253(&self) -> &PAD {
            self.pad(252)
        }
        #[doc = "0x7e8..0x7f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv254(&self) -> &PAD {
            self.pad(253)
        }
        #[doc = "0x7f0..0x7f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv255(&self) -> &PAD {
            self.pad(254)
        }
        #[doc = "0x7f8..0x800 - no description available"]
        #[inline(always)]
        pub const fn padrsv256(&self) -> &PAD {
            self.pad(255)
        }
        #[doc = "0x800..0x808 - no description available"]
        #[inline(always)]
        pub const fn padrsv257(&self) -> &PAD {
            self.pad(256)
        }
        #[doc = "0x808..0x810 - no description available"]
        #[inline(always)]
        pub const fn padrsv258(&self) -> &PAD {
            self.pad(257)
        }
        #[doc = "0x810..0x818 - no description available"]
        #[inline(always)]
        pub const fn padrsv259(&self) -> &PAD {
            self.pad(258)
        }
        #[doc = "0x818..0x820 - no description available"]
        #[inline(always)]
        pub const fn padrsv260(&self) -> &PAD {
            self.pad(259)
        }
        #[doc = "0x820..0x828 - no description available"]
        #[inline(always)]
        pub const fn padrsv261(&self) -> &PAD {
            self.pad(260)
        }
        #[doc = "0x828..0x830 - no description available"]
        #[inline(always)]
        pub const fn padrsv262(&self) -> &PAD {
            self.pad(261)
        }
        #[doc = "0x830..0x838 - no description available"]
        #[inline(always)]
        pub const fn padrsv263(&self) -> &PAD {
            self.pad(262)
        }
        #[doc = "0x838..0x840 - no description available"]
        #[inline(always)]
        pub const fn padrsv264(&self) -> &PAD {
            self.pad(263)
        }
        #[doc = "0x840..0x848 - no description available"]
        #[inline(always)]
        pub const fn padrsv265(&self) -> &PAD {
            self.pad(264)
        }
        #[doc = "0x848..0x850 - no description available"]
        #[inline(always)]
        pub const fn padrsv266(&self) -> &PAD {
            self.pad(265)
        }
        #[doc = "0x850..0x858 - no description available"]
        #[inline(always)]
        pub const fn padrsv267(&self) -> &PAD {
            self.pad(266)
        }
        #[doc = "0x858..0x860 - no description available"]
        #[inline(always)]
        pub const fn padrsv268(&self) -> &PAD {
            self.pad(267)
        }
        #[doc = "0x860..0x868 - no description available"]
        #[inline(always)]
        pub const fn padrsv269(&self) -> &PAD {
            self.pad(268)
        }
        #[doc = "0x868..0x870 - no description available"]
        #[inline(always)]
        pub const fn padrsv270(&self) -> &PAD {
            self.pad(269)
        }
        #[doc = "0x870..0x878 - no description available"]
        #[inline(always)]
        pub const fn padrsv271(&self) -> &PAD {
            self.pad(270)
        }
        #[doc = "0x878..0x880 - no description available"]
        #[inline(always)]
        pub const fn padrsv272(&self) -> &PAD {
            self.pad(271)
        }
        #[doc = "0x880..0x888 - no description available"]
        #[inline(always)]
        pub const fn padrsv273(&self) -> &PAD {
            self.pad(272)
        }
        #[doc = "0x888..0x890 - no description available"]
        #[inline(always)]
        pub const fn padrsv274(&self) -> &PAD {
            self.pad(273)
        }
        #[doc = "0x890..0x898 - no description available"]
        #[inline(always)]
        pub const fn padrsv275(&self) -> &PAD {
            self.pad(274)
        }
        #[doc = "0x898..0x8a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv276(&self) -> &PAD {
            self.pad(275)
        }
        #[doc = "0x8a0..0x8a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv277(&self) -> &PAD {
            self.pad(276)
        }
        #[doc = "0x8a8..0x8b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv278(&self) -> &PAD {
            self.pad(277)
        }
        #[doc = "0x8b0..0x8b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv279(&self) -> &PAD {
            self.pad(278)
        }
        #[doc = "0x8b8..0x8c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv280(&self) -> &PAD {
            self.pad(279)
        }
        #[doc = "0x8c0..0x8c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv281(&self) -> &PAD {
            self.pad(280)
        }
        #[doc = "0x8c8..0x8d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv282(&self) -> &PAD {
            self.pad(281)
        }
        #[doc = "0x8d0..0x8d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv283(&self) -> &PAD {
            self.pad(282)
        }
        #[doc = "0x8d8..0x8e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv284(&self) -> &PAD {
            self.pad(283)
        }
        #[doc = "0x8e0..0x8e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv285(&self) -> &PAD {
            self.pad(284)
        }
        #[doc = "0x8e8..0x8f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv286(&self) -> &PAD {
            self.pad(285)
        }
        #[doc = "0x8f0..0x8f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv287(&self) -> &PAD {
            self.pad(286)
        }
        #[doc = "0x8f8..0x900 - no description available"]
        #[inline(always)]
        pub const fn padrsv288(&self) -> &PAD {
            self.pad(287)
        }
        #[doc = "0x900..0x908 - no description available"]
        #[inline(always)]
        pub const fn padrsv289(&self) -> &PAD {
            self.pad(288)
        }
        #[doc = "0x908..0x910 - no description available"]
        #[inline(always)]
        pub const fn padrsv290(&self) -> &PAD {
            self.pad(289)
        }
        #[doc = "0x910..0x918 - no description available"]
        #[inline(always)]
        pub const fn padrsv291(&self) -> &PAD {
            self.pad(290)
        }
        #[doc = "0x918..0x920 - no description available"]
        #[inline(always)]
        pub const fn padrsv292(&self) -> &PAD {
            self.pad(291)
        }
        #[doc = "0x920..0x928 - no description available"]
        #[inline(always)]
        pub const fn padrsv293(&self) -> &PAD {
            self.pad(292)
        }
        #[doc = "0x928..0x930 - no description available"]
        #[inline(always)]
        pub const fn padrsv294(&self) -> &PAD {
            self.pad(293)
        }
        #[doc = "0x930..0x938 - no description available"]
        #[inline(always)]
        pub const fn padrsv295(&self) -> &PAD {
            self.pad(294)
        }
        #[doc = "0x938..0x940 - no description available"]
        #[inline(always)]
        pub const fn padrsv296(&self) -> &PAD {
            self.pad(295)
        }
        #[doc = "0x940..0x948 - no description available"]
        #[inline(always)]
        pub const fn padrsv297(&self) -> &PAD {
            self.pad(296)
        }
        #[doc = "0x948..0x950 - no description available"]
        #[inline(always)]
        pub const fn padrsv298(&self) -> &PAD {
            self.pad(297)
        }
        #[doc = "0x950..0x958 - no description available"]
        #[inline(always)]
        pub const fn padrsv299(&self) -> &PAD {
            self.pad(298)
        }
        #[doc = "0x958..0x960 - no description available"]
        #[inline(always)]
        pub const fn padrsv300(&self) -> &PAD {
            self.pad(299)
        }
        #[doc = "0x960..0x968 - no description available"]
        #[inline(always)]
        pub const fn padrsv301(&self) -> &PAD {
            self.pad(300)
        }
        #[doc = "0x968..0x970 - no description available"]
        #[inline(always)]
        pub const fn padrsv302(&self) -> &PAD {
            self.pad(301)
        }
        #[doc = "0x970..0x978 - no description available"]
        #[inline(always)]
        pub const fn padrsv303(&self) -> &PAD {
            self.pad(302)
        }
        #[doc = "0x978..0x980 - no description available"]
        #[inline(always)]
        pub const fn padrsv304(&self) -> &PAD {
            self.pad(303)
        }
        #[doc = "0x980..0x988 - no description available"]
        #[inline(always)]
        pub const fn padrsv305(&self) -> &PAD {
            self.pad(304)
        }
        #[doc = "0x988..0x990 - no description available"]
        #[inline(always)]
        pub const fn padrsv306(&self) -> &PAD {
            self.pad(305)
        }
        #[doc = "0x990..0x998 - no description available"]
        #[inline(always)]
        pub const fn padrsv307(&self) -> &PAD {
            self.pad(306)
        }
        #[doc = "0x998..0x9a0 - no description available"]
        #[inline(always)]
        pub const fn padrsv308(&self) -> &PAD {
            self.pad(307)
        }
        #[doc = "0x9a0..0x9a8 - no description available"]
        #[inline(always)]
        pub const fn padrsv309(&self) -> &PAD {
            self.pad(308)
        }
        #[doc = "0x9a8..0x9b0 - no description available"]
        #[inline(always)]
        pub const fn padrsv310(&self) -> &PAD {
            self.pad(309)
        }
        #[doc = "0x9b0..0x9b8 - no description available"]
        #[inline(always)]
        pub const fn padrsv311(&self) -> &PAD {
            self.pad(310)
        }
        #[doc = "0x9b8..0x9c0 - no description available"]
        #[inline(always)]
        pub const fn padrsv312(&self) -> &PAD {
            self.pad(311)
        }
        #[doc = "0x9c0..0x9c8 - no description available"]
        #[inline(always)]
        pub const fn padrsv313(&self) -> &PAD {
            self.pad(312)
        }
        #[doc = "0x9c8..0x9d0 - no description available"]
        #[inline(always)]
        pub const fn padrsv314(&self) -> &PAD {
            self.pad(313)
        }
        #[doc = "0x9d0..0x9d8 - no description available"]
        #[inline(always)]
        pub const fn padrsv315(&self) -> &PAD {
            self.pad(314)
        }
        #[doc = "0x9d8..0x9e0 - no description available"]
        #[inline(always)]
        pub const fn padrsv316(&self) -> &PAD {
            self.pad(315)
        }
        #[doc = "0x9e0..0x9e8 - no description available"]
        #[inline(always)]
        pub const fn padrsv317(&self) -> &PAD {
            self.pad(316)
        }
        #[doc = "0x9e8..0x9f0 - no description available"]
        #[inline(always)]
        pub const fn padrsv318(&self) -> &PAD {
            self.pad(317)
        }
        #[doc = "0x9f0..0x9f8 - no description available"]
        #[inline(always)]
        pub const fn padrsv319(&self) -> &PAD {
            self.pad(318)
        }
        #[doc = "0x9f8..0xa00 - no description available"]
        #[inline(always)]
        pub const fn padrsv320(&self) -> &PAD {
            self.pad(319)
        }
        #[doc = "0xa00..0xa08 - no description available"]
        #[inline(always)]
        pub const fn padrsv321(&self) -> &PAD {
            self.pad(320)
        }
        #[doc = "0xa08..0xa10 - no description available"]
        #[inline(always)]
        pub const fn padrsv322(&self) -> &PAD {
            self.pad(321)
        }
        #[doc = "0xa10..0xa18 - no description available"]
        #[inline(always)]
        pub const fn padrsv323(&self) -> &PAD {
            self.pad(322)
        }
        #[doc = "0xa18..0xa20 - no description available"]
        #[inline(always)]
        pub const fn padrsv324(&self) -> &PAD {
            self.pad(323)
        }
        #[doc = "0xa20..0xa28 - no description available"]
        #[inline(always)]
        pub const fn padrsv325(&self) -> &PAD {
            self.pad(324)
        }
        #[doc = "0xa28..0xa30 - no description available"]
        #[inline(always)]
        pub const fn padrsv326(&self) -> &PAD {
            self.pad(325)
        }
        #[doc = "0xa30..0xa38 - no description available"]
        #[inline(always)]
        pub const fn padrsv327(&self) -> &PAD {
            self.pad(326)
        }
        #[doc = "0xa38..0xa40 - no description available"]
        #[inline(always)]
        pub const fn padrsv328(&self) -> &PAD {
            self.pad(327)
        }
        #[doc = "0xa40..0xa48 - no description available"]
        #[inline(always)]
        pub const fn padrsv329(&self) -> &PAD {
            self.pad(328)
        }
        #[doc = "0xa48..0xa50 - no description available"]
        #[inline(always)]
        pub const fn padrsv330(&self) -> &PAD {
            self.pad(329)
        }
        #[doc = "0xa50..0xa58 - no description available"]
        #[inline(always)]
        pub const fn padrsv331(&self) -> &PAD {
            self.pad(330)
        }
        #[doc = "0xa58..0xa60 - no description available"]
        #[inline(always)]
        pub const fn padrsv332(&self) -> &PAD {
            self.pad(331)
        }
        #[doc = "0xa60..0xa68 - no description available"]
        #[inline(always)]
        pub const fn padrsv333(&self) -> &PAD {
            self.pad(332)
        }
        #[doc = "0xa68..0xa70 - no description available"]
        #[inline(always)]
        pub const fn padrsv334(&self) -> &PAD {
            self.pad(333)
        }
        #[doc = "0xa70..0xa78 - no description available"]
        #[inline(always)]
        pub const fn padrsv335(&self) -> &PAD {
            self.pad(334)
        }
        #[doc = "0xa78..0xa80 - no description available"]
        #[inline(always)]
        pub const fn padrsv336(&self) -> &PAD {
            self.pad(335)
        }
        #[doc = "0xa80..0xa88 - no description available"]
        #[inline(always)]
        pub const fn padrsv337(&self) -> &PAD {
            self.pad(336)
        }
        #[doc = "0xa88..0xa90 - no description available"]
        #[inline(always)]
        pub const fn padrsv338(&self) -> &PAD {
            self.pad(337)
        }
        #[doc = "0xa90..0xa98 - no description available"]
        #[inline(always)]
        pub const fn padrsv339(&self) -> &PAD {
            self.pad(338)
        }
        #[doc = "0xa98..0xaa0 - no description available"]
        #[inline(always)]
        pub const fn padrsv340(&self) -> &PAD {
            self.pad(339)
        }
        #[doc = "0xaa0..0xaa8 - no description available"]
        #[inline(always)]
        pub const fn padrsv341(&self) -> &PAD {
            self.pad(340)
        }
        #[doc = "0xaa8..0xab0 - no description available"]
        #[inline(always)]
        pub const fn padrsv342(&self) -> &PAD {
            self.pad(341)
        }
        #[doc = "0xab0..0xab8 - no description available"]
        #[inline(always)]
        pub const fn padrsv343(&self) -> &PAD {
            self.pad(342)
        }
        #[doc = "0xab8..0xac0 - no description available"]
        #[inline(always)]
        pub const fn padrsv344(&self) -> &PAD {
            self.pad(343)
        }
        #[doc = "0xac0..0xac8 - no description available"]
        #[inline(always)]
        pub const fn padrsv345(&self) -> &PAD {
            self.pad(344)
        }
        #[doc = "0xac8..0xad0 - no description available"]
        #[inline(always)]
        pub const fn padrsv346(&self) -> &PAD {
            self.pad(345)
        }
        #[doc = "0xad0..0xad8 - no description available"]
        #[inline(always)]
        pub const fn padrsv347(&self) -> &PAD {
            self.pad(346)
        }
        #[doc = "0xad8..0xae0 - no description available"]
        #[inline(always)]
        pub const fn padrsv348(&self) -> &PAD {
            self.pad(347)
        }
        #[doc = "0xae0..0xae8 - no description available"]
        #[inline(always)]
        pub const fn padrsv349(&self) -> &PAD {
            self.pad(348)
        }
        #[doc = "0xae8..0xaf0 - no description available"]
        #[inline(always)]
        pub const fn padrsv350(&self) -> &PAD {
            self.pad(349)
        }
        #[doc = "0xaf0..0xaf8 - no description available"]
        #[inline(always)]
        pub const fn padrsv351(&self) -> &PAD {
            self.pad(350)
        }
        #[doc = "0xaf8..0xb00 - no description available"]
        #[inline(always)]
        pub const fn padrsv352(&self) -> &PAD {
            self.pad(351)
        }
        #[doc = "0xb00..0xb08 - no description available"]
        #[inline(always)]
        pub const fn padrsv353(&self) -> &PAD {
            self.pad(352)
        }
        #[doc = "0xb08..0xb10 - no description available"]
        #[inline(always)]
        pub const fn padrsv354(&self) -> &PAD {
            self.pad(353)
        }
        #[doc = "0xb10..0xb18 - no description available"]
        #[inline(always)]
        pub const fn padrsv355(&self) -> &PAD {
            self.pad(354)
        }
        #[doc = "0xb18..0xb20 - no description available"]
        #[inline(always)]
        pub const fn padrsv356(&self) -> &PAD {
            self.pad(355)
        }
        #[doc = "0xb20..0xb28 - no description available"]
        #[inline(always)]
        pub const fn padrsv357(&self) -> &PAD {
            self.pad(356)
        }
        #[doc = "0xb28..0xb30 - no description available"]
        #[inline(always)]
        pub const fn padrsv358(&self) -> &PAD {
            self.pad(357)
        }
        #[doc = "0xb30..0xb38 - no description available"]
        #[inline(always)]
        pub const fn padrsv359(&self) -> &PAD {
            self.pad(358)
        }
        #[doc = "0xb38..0xb40 - no description available"]
        #[inline(always)]
        pub const fn padrsv360(&self) -> &PAD {
            self.pad(359)
        }
        #[doc = "0xb40..0xb48 - no description available"]
        #[inline(always)]
        pub const fn padrsv361(&self) -> &PAD {
            self.pad(360)
        }
        #[doc = "0xb48..0xb50 - no description available"]
        #[inline(always)]
        pub const fn padrsv362(&self) -> &PAD {
            self.pad(361)
        }
        #[doc = "0xb50..0xb58 - no description available"]
        #[inline(always)]
        pub const fn padrsv363(&self) -> &PAD {
            self.pad(362)
        }
        #[doc = "0xb58..0xb60 - no description available"]
        #[inline(always)]
        pub const fn padrsv364(&self) -> &PAD {
            self.pad(363)
        }
        #[doc = "0xb60..0xb68 - no description available"]
        #[inline(always)]
        pub const fn padrsv365(&self) -> &PAD {
            self.pad(364)
        }
        #[doc = "0xb68..0xb70 - no description available"]
        #[inline(always)]
        pub const fn padrsv366(&self) -> &PAD {
            self.pad(365)
        }
        #[doc = "0xb70..0xb78 - no description available"]
        #[inline(always)]
        pub const fn padrsv367(&self) -> &PAD {
            self.pad(366)
        }
        #[doc = "0xb78..0xb80 - no description available"]
        #[inline(always)]
        pub const fn padrsv368(&self) -> &PAD {
            self.pad(367)
        }
        #[doc = "0xb80..0xb88 - no description available"]
        #[inline(always)]
        pub const fn padrsv369(&self) -> &PAD {
            self.pad(368)
        }
        #[doc = "0xb88..0xb90 - no description available"]
        #[inline(always)]
        pub const fn padrsv370(&self) -> &PAD {
            self.pad(369)
        }
        #[doc = "0xb90..0xb98 - no description available"]
        #[inline(always)]
        pub const fn padrsv371(&self) -> &PAD {
            self.pad(370)
        }
        #[doc = "0xb98..0xba0 - no description available"]
        #[inline(always)]
        pub const fn padrsv372(&self) -> &PAD {
            self.pad(371)
        }
        #[doc = "0xba0..0xba8 - no description available"]
        #[inline(always)]
        pub const fn padrsv373(&self) -> &PAD {
            self.pad(372)
        }
        #[doc = "0xba8..0xbb0 - no description available"]
        #[inline(always)]
        pub const fn padrsv374(&self) -> &PAD {
            self.pad(373)
        }
        #[doc = "0xbb0..0xbb8 - no description available"]
        #[inline(always)]
        pub const fn padrsv375(&self) -> &PAD {
            self.pad(374)
        }
        #[doc = "0xbb8..0xbc0 - no description available"]
        #[inline(always)]
        pub const fn padrsv376(&self) -> &PAD {
            self.pad(375)
        }
        #[doc = "0xbc0..0xbc8 - no description available"]
        #[inline(always)]
        pub const fn padrsv377(&self) -> &PAD {
            self.pad(376)
        }
        #[doc = "0xbc8..0xbd0 - no description available"]
        #[inline(always)]
        pub const fn padrsv378(&self) -> &PAD {
            self.pad(377)
        }
        #[doc = "0xbd0..0xbd8 - no description available"]
        #[inline(always)]
        pub const fn padrsv379(&self) -> &PAD {
            self.pad(378)
        }
        #[doc = "0xbd8..0xbe0 - no description available"]
        #[inline(always)]
        pub const fn padrsv380(&self) -> &PAD {
            self.pad(379)
        }
        #[doc = "0xbe0..0xbe8 - no description available"]
        #[inline(always)]
        pub const fn padrsv381(&self) -> &PAD {
            self.pad(380)
        }
        #[doc = "0xbe8..0xbf0 - no description available"]
        #[inline(always)]
        pub const fn padrsv382(&self) -> &PAD {
            self.pad(381)
        }
        #[doc = "0xbf0..0xbf8 - no description available"]
        #[inline(always)]
        pub const fn padrsv383(&self) -> &PAD {
            self.pad(382)
        }
        #[doc = "0xbf8..0xc00 - no description available"]
        #[inline(always)]
        pub const fn padrsv384(&self) -> &PAD {
            self.pad(383)
        }
        #[doc = "0xc00..0xc08 - no description available"]
        #[inline(always)]
        pub const fn padrsv385(&self) -> &PAD {
            self.pad(384)
        }
        #[doc = "0xc08..0xc10 - no description available"]
        #[inline(always)]
        pub const fn padrsv386(&self) -> &PAD {
            self.pad(385)
        }
        #[doc = "0xc10..0xc18 - no description available"]
        #[inline(always)]
        pub const fn padrsv387(&self) -> &PAD {
            self.pad(386)
        }
        #[doc = "0xc18..0xc20 - no description available"]
        #[inline(always)]
        pub const fn padrsv388(&self) -> &PAD {
            self.pad(387)
        }
        #[doc = "0xc20..0xc28 - no description available"]
        #[inline(always)]
        pub const fn padrsv389(&self) -> &PAD {
            self.pad(388)
        }
        #[doc = "0xc28..0xc30 - no description available"]
        #[inline(always)]
        pub const fn padrsv390(&self) -> &PAD {
            self.pad(389)
        }
        #[doc = "0xc30..0xc38 - no description available"]
        #[inline(always)]
        pub const fn padrsv391(&self) -> &PAD {
            self.pad(390)
        }
        #[doc = "0xc38..0xc40 - no description available"]
        #[inline(always)]
        pub const fn padrsv392(&self) -> &PAD {
            self.pad(391)
        }
        #[doc = "0xc40..0xc48 - no description available"]
        #[inline(always)]
        pub const fn padrsv393(&self) -> &PAD {
            self.pad(392)
        }
        #[doc = "0xc48..0xc50 - no description available"]
        #[inline(always)]
        pub const fn padrsv394(&self) -> &PAD {
            self.pad(393)
        }
        #[doc = "0xc50..0xc58 - no description available"]
        #[inline(always)]
        pub const fn padrsv395(&self) -> &PAD {
            self.pad(394)
        }
        #[doc = "0xc58..0xc60 - no description available"]
        #[inline(always)]
        pub const fn padrsv396(&self) -> &PAD {
            self.pad(395)
        }
        #[doc = "0xc60..0xc68 - no description available"]
        #[inline(always)]
        pub const fn padrsv397(&self) -> &PAD {
            self.pad(396)
        }
        #[doc = "0xc68..0xc70 - no description available"]
        #[inline(always)]
        pub const fn padrsv398(&self) -> &PAD {
            self.pad(397)
        }
        #[doc = "0xc70..0xc78 - no description available"]
        #[inline(always)]
        pub const fn padrsv399(&self) -> &PAD {
            self.pad(398)
        }
        #[doc = "0xc78..0xc80 - no description available"]
        #[inline(always)]
        pub const fn padrsv400(&self) -> &PAD {
            self.pad(399)
        }
        #[doc = "0xc80..0xc88 - no description available"]
        #[inline(always)]
        pub const fn padrsv401(&self) -> &PAD {
            self.pad(400)
        }
        #[doc = "0xc88..0xc90 - no description available"]
        #[inline(always)]
        pub const fn padrsv402(&self) -> &PAD {
            self.pad(401)
        }
        #[doc = "0xc90..0xc98 - no description available"]
        #[inline(always)]
        pub const fn padrsv403(&self) -> &PAD {
            self.pad(402)
        }
        #[doc = "0xc98..0xca0 - no description available"]
        #[inline(always)]
        pub const fn padrsv404(&self) -> &PAD {
            self.pad(403)
        }
        #[doc = "0xca0..0xca8 - no description available"]
        #[inline(always)]
        pub const fn padrsv405(&self) -> &PAD {
            self.pad(404)
        }
        #[doc = "0xca8..0xcb0 - no description available"]
        #[inline(always)]
        pub const fn padrsv406(&self) -> &PAD {
            self.pad(405)
        }
        #[doc = "0xcb0..0xcb8 - no description available"]
        #[inline(always)]
        pub const fn padrsv407(&self) -> &PAD {
            self.pad(406)
        }
        #[doc = "0xcb8..0xcc0 - no description available"]
        #[inline(always)]
        pub const fn padrsv408(&self) -> &PAD {
            self.pad(407)
        }
        #[doc = "0xcc0..0xcc8 - no description available"]
        #[inline(always)]
        pub const fn padrsv409(&self) -> &PAD {
            self.pad(408)
        }
        #[doc = "0xcc8..0xcd0 - no description available"]
        #[inline(always)]
        pub const fn padrsv410(&self) -> &PAD {
            self.pad(409)
        }
        #[doc = "0xcd0..0xcd8 - no description available"]
        #[inline(always)]
        pub const fn padrsv411(&self) -> &PAD {
            self.pad(410)
        }
        #[doc = "0xcd8..0xce0 - no description available"]
        #[inline(always)]
        pub const fn padrsv412(&self) -> &PAD {
            self.pad(411)
        }
        #[doc = "0xce0..0xce8 - no description available"]
        #[inline(always)]
        pub const fn padrsv413(&self) -> &PAD {
            self.pad(412)
        }
        #[doc = "0xce8..0xcf0 - no description available"]
        #[inline(always)]
        pub const fn padrsv414(&self) -> &PAD {
            self.pad(413)
        }
        #[doc = "0xcf0..0xcf8 - no description available"]
        #[inline(always)]
        pub const fn padrsv415(&self) -> &PAD {
            self.pad(414)
        }
        #[doc = "0xcf8..0xd00 - no description available"]
        #[inline(always)]
        pub const fn padrsv416(&self) -> &PAD {
            self.pad(415)
        }
        #[doc = "0xd00..0xd08 - no description available"]
        #[inline(always)]
        pub const fn padpx00(&self) -> &PAD {
            self.pad(416)
        }
        #[doc = "0xd08..0xd10 - no description available"]
        #[inline(always)]
        pub const fn padpx01(&self) -> &PAD {
            self.pad(417)
        }
        #[doc = "0xd10..0xd18 - no description available"]
        #[inline(always)]
        pub const fn padpx02(&self) -> &PAD {
            self.pad(418)
        }
        #[doc = "0xd18..0xd20 - no description available"]
        #[inline(always)]
        pub const fn padpx03(&self) -> &PAD {
            self.pad(419)
        }
        #[doc = "0xd20..0xd28 - no description available"]
        #[inline(always)]
        pub const fn padpx04(&self) -> &PAD {
            self.pad(420)
        }
        #[doc = "0xd28..0xd30 - no description available"]
        #[inline(always)]
        pub const fn padpx05(&self) -> &PAD {
            self.pad(421)
        }
        #[doc = "0xd30..0xd38 - no description available"]
        #[inline(always)]
        pub const fn padpx06(&self) -> &PAD {
            self.pad(422)
        }
        #[doc = "0xd38..0xd40 - no description available"]
        #[inline(always)]
        pub const fn padpx07(&self) -> &PAD {
            self.pad(423)
        }
        #[doc = "0xd40..0xd48 - no description available"]
        #[inline(always)]
        pub const fn padrsv425(&self) -> &PAD {
            self.pad(424)
        }
        #[doc = "0xd48..0xd50 - no description available"]
        #[inline(always)]
        pub const fn padrsv426(&self) -> &PAD {
            self.pad(425)
        }
        #[doc = "0xd50..0xd58 - no description available"]
        #[inline(always)]
        pub const fn padrsv427(&self) -> &PAD {
            self.pad(426)
        }
        #[doc = "0xd58..0xd60 - no description available"]
        #[inline(always)]
        pub const fn padrsv428(&self) -> &PAD {
            self.pad(427)
        }
        #[doc = "0xd60..0xd68 - no description available"]
        #[inline(always)]
        pub const fn padrsv429(&self) -> &PAD {
            self.pad(428)
        }
        #[doc = "0xd68..0xd70 - no description available"]
        #[inline(always)]
        pub const fn padrsv430(&self) -> &PAD {
            self.pad(429)
        }
        #[doc = "0xd70..0xd78 - no description available"]
        #[inline(always)]
        pub const fn padrsv431(&self) -> &PAD {
            self.pad(430)
        }
        #[doc = "0xd78..0xd80 - no description available"]
        #[inline(always)]
        pub const fn padrsv432(&self) -> &PAD {
            self.pad(431)
        }
        #[doc = "0xd80..0xd88 - no description available"]
        #[inline(always)]
        pub const fn padrsv433(&self) -> &PAD {
            self.pad(432)
        }
        #[doc = "0xd88..0xd90 - no description available"]
        #[inline(always)]
        pub const fn padrsv434(&self) -> &PAD {
            self.pad(433)
        }
        #[doc = "0xd90..0xd98 - no description available"]
        #[inline(always)]
        pub const fn padrsv435(&self) -> &PAD {
            self.pad(434)
        }
        #[doc = "0xd98..0xda0 - no description available"]
        #[inline(always)]
        pub const fn padrsv436(&self) -> &PAD {
            self.pad(435)
        }
        #[doc = "0xda0..0xda8 - no description available"]
        #[inline(always)]
        pub const fn padrsv437(&self) -> &PAD {
            self.pad(436)
        }
        #[doc = "0xda8..0xdb0 - no description available"]
        #[inline(always)]
        pub const fn padrsv438(&self) -> &PAD {
            self.pad(437)
        }
        #[doc = "0xdb0..0xdb8 - no description available"]
        #[inline(always)]
        pub const fn padrsv439(&self) -> &PAD {
            self.pad(438)
        }
        #[doc = "0xdb8..0xdc0 - no description available"]
        #[inline(always)]
        pub const fn padrsv440(&self) -> &PAD {
            self.pad(439)
        }
        #[doc = "0xdc0..0xdc8 - no description available"]
        #[inline(always)]
        pub const fn padrsv441(&self) -> &PAD {
            self.pad(440)
        }
        #[doc = "0xdc8..0xdd0 - no description available"]
        #[inline(always)]
        pub const fn padrsv442(&self) -> &PAD {
            self.pad(441)
        }
        #[doc = "0xdd0..0xdd8 - no description available"]
        #[inline(always)]
        pub const fn padrsv443(&self) -> &PAD {
            self.pad(442)
        }
        #[doc = "0xdd8..0xde0 - no description available"]
        #[inline(always)]
        pub const fn padrsv444(&self) -> &PAD {
            self.pad(443)
        }
        #[doc = "0xde0..0xde8 - no description available"]
        #[inline(always)]
        pub const fn padrsv445(&self) -> &PAD {
            self.pad(444)
        }
        #[doc = "0xde8..0xdf0 - no description available"]
        #[inline(always)]
        pub const fn padrsv446(&self) -> &PAD {
            self.pad(445)
        }
        #[doc = "0xdf0..0xdf8 - no description available"]
        #[inline(always)]
        pub const fn padrsv447(&self) -> &PAD {
            self.pad(446)
        }
        #[doc = "0xdf8..0xe00 - no description available"]
        #[inline(always)]
        pub const fn padrsv448(&self) -> &PAD {
            self.pad(447)
        }
        #[doc = "0xe00..0xe08 - no description available"]
        #[inline(always)]
        pub const fn padpy00(&self) -> &PAD {
            self.pad(448)
        }
        #[doc = "0xe08..0xe10 - no description available"]
        #[inline(always)]
        pub const fn padpy01(&self) -> &PAD {
            self.pad(449)
        }
        #[doc = "0xe10..0xe18 - no description available"]
        #[inline(always)]
        pub const fn padpy02(&self) -> &PAD {
            self.pad(450)
        }
        #[doc = "0xe18..0xe20 - no description available"]
        #[inline(always)]
        pub const fn padpy03(&self) -> &PAD {
            self.pad(451)
        }
        #[doc = "0xe20..0xe28 - no description available"]
        #[inline(always)]
        pub const fn padpy04(&self) -> &PAD {
            self.pad(452)
        }
        #[doc = "0xe28..0xe30 - no description available"]
        #[inline(always)]
        pub const fn padpy05(&self) -> &PAD {
            self.pad(453)
        }
        #[doc = "0xe30..0xe38 - no description available"]
        #[inline(always)]
        pub const fn padpy06(&self) -> &PAD {
            self.pad(454)
        }
        #[doc = "0xe38..0xe40 - no description available"]
        #[inline(always)]
        pub const fn padpy07(&self) -> &PAD {
            self.pad(455)
        }
    }
    #[doc = "no description available"]
    pub use self::pad::PAD;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod pad {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct PAD {
            func_ctl: FUNC_CTL,
            pad_ctl: PAD_CTL,
        }
        impl PAD {
            #[doc = "0x00 - ALT SELECT"]
            #[inline(always)]
            pub const fn func_ctl(&self) -> &FUNC_CTL {
                &self.func_ctl
            }
            #[doc = "0x04 - PAD SETTINGS"]
            #[inline(always)]
            pub const fn pad_ctl(&self) -> &PAD_CTL {
                &self.pad_ctl
            }
        }
        #[doc = "FUNC_CTL (rw) register accessor: ALT SELECT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@func_ctl`]
module"]
        pub type FUNC_CTL = crate::Reg<func_ctl::FUNC_CTL_SPEC>;
        #[doc = "ALT SELECT"]
        pub mod func_ctl {
            #[doc = "Register `FUNC_CTL` reader"]
            pub type R = crate::R<FUNC_CTL_SPEC>;
            #[doc = "Register `FUNC_CTL` writer"]
            pub type W = crate::W<FUNC_CTL_SPEC>;
            #[doc = "Field `ALT_SELECT` reader - alt select 0: ALT0 1: ALT1 ... 31:ALT31"]
            pub type ALT_SELECT_R = crate::FieldReader;
            #[doc = "Field `ALT_SELECT` writer - alt select 0: ALT0 1: ALT1 ... 31:ALT31"]
            pub type ALT_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
            #[doc = "Field `ANALOG` reader - select analog pin in pad 0: disable 1: enable"]
            pub type ANALOG_R = crate::BitReader;
            #[doc = "Field `ANALOG` writer - select analog pin in pad 0: disable 1: enable"]
            pub type ANALOG_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `LOOP_BACK` reader - force input on 0: disable 1: enable"]
            pub type LOOP_BACK_R = crate::BitReader;
            #[doc = "Field `LOOP_BACK` writer - force input on 0: disable 1: enable"]
            pub type LOOP_BACK_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:4 - alt select 0: ALT0 1: ALT1 ... 31:ALT31"]
                #[inline(always)]
                pub fn alt_select(&self) -> ALT_SELECT_R {
                    ALT_SELECT_R::new((self.bits & 0x1f) as u8)
                }
                #[doc = "Bit 8 - select analog pin in pad 0: disable 1: enable"]
                #[inline(always)]
                pub fn analog(&self) -> ANALOG_R {
                    ANALOG_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 16 - force input on 0: disable 1: enable"]
                #[inline(always)]
                pub fn loop_back(&self) -> LOOP_BACK_R {
                    LOOP_BACK_R::new(((self.bits >> 16) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:4 - alt select 0: ALT0 1: ALT1 ... 31:ALT31"]
                #[inline(always)]
                #[must_use]
                pub fn alt_select(&mut self) -> ALT_SELECT_W<FUNC_CTL_SPEC> {
                    ALT_SELECT_W::new(self, 0)
                }
                #[doc = "Bit 8 - select analog pin in pad 0: disable 1: enable"]
                #[inline(always)]
                #[must_use]
                pub fn analog(&mut self) -> ANALOG_W<FUNC_CTL_SPEC> {
                    ANALOG_W::new(self, 8)
                }
                #[doc = "Bit 16 - force input on 0: disable 1: enable"]
                #[inline(always)]
                #[must_use]
                pub fn loop_back(&mut self) -> LOOP_BACK_W<FUNC_CTL_SPEC> {
                    LOOP_BACK_W::new(self, 16)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "ALT SELECT\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`func_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`func_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct FUNC_CTL_SPEC;
            impl crate::RegisterSpec for FUNC_CTL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`func_ctl::R`](R) reader structure"]
            impl crate::Readable for FUNC_CTL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`func_ctl::W`](W) writer structure"]
            impl crate::Writable for FUNC_CTL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets FUNC_CTL to value 0"]
            impl crate::Resettable for FUNC_CTL_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "PAD_CTL (rw) register accessor: PAD SETTINGS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_ctl`]
module"]
        pub type PAD_CTL = crate::Reg<pad_ctl::PAD_CTL_SPEC>;
        #[doc = "PAD SETTINGS"]
        pub mod pad_ctl {
            #[doc = "Register `PAD_CTL` reader"]
            pub type R = crate::R<PAD_CTL_SPEC>;
            #[doc = "Register `PAD_CTL` writer"]
            pub type W = crate::W<PAD_CTL_SPEC>;
            #[doc = "Field `DS` reader - drive strength 1.8V Mode: 000: 260 Ohm 001: 260 Ohm 010: 130 Ohm 011: 88 Ohm 100: 65 Ohm 101: 52 Ohm 110: 43 Ohm 111: 37 Ohm 3.3V Mode: 000: 157 Ohm 001: 157 Ohm 010: 78 Ohm 011: 53 Ohm 100: 39 Ohm 101: 32 Ohm 110: 26 Ohm 111: 23 Ohm"]
            pub type DS_R = crate::FieldReader;
            #[doc = "Field `DS` writer - drive strength 1.8V Mode: 000: 260 Ohm 001: 260 Ohm 010: 130 Ohm 011: 88 Ohm 100: 65 Ohm 101: 52 Ohm 110: 43 Ohm 111: 37 Ohm 3.3V Mode: 000: 157 Ohm 001: 157 Ohm 010: 78 Ohm 011: 53 Ohm 100: 39 Ohm 101: 32 Ohm 110: 26 Ohm 111: 23 Ohm"]
            pub type DS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
            #[doc = "Field `SPD` reader - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise 00: Slow frequency slew rate(50Mhz) 01: Medium frequency slew rate(100 Mhz) 10: Fast frequency slew rate(150 Mhz) 11: Max frequency slew rate(200Mhz)"]
            pub type SPD_R = crate::FieldReader;
            #[doc = "Field `SPD` writer - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise 00: Slow frequency slew rate(50Mhz) 01: Medium frequency slew rate(100 Mhz) 10: Fast frequency slew rate(150 Mhz) 11: Max frequency slew rate(200Mhz)"]
            pub type SPD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `SR` reader - slew rate 0: Slow slew rate 1: Fast slew rate"]
            pub type SR_R = crate::BitReader;
            #[doc = "Field `SR` writer - slew rate 0: Slow slew rate 1: Fast slew rate"]
            pub type SR_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `OD` reader - open drain 0: open drain disable 1: open drain enable"]
            pub type OD_R = crate::BitReader;
            #[doc = "Field `OD` writer - open drain 0: open drain disable 1: open drain enable"]
            pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `KE` reader - keeper capability enable 0: keeper disable 1: keeper enable"]
            pub type KE_R = crate::BitReader;
            #[doc = "Field `KE` writer - keeper capability enable 0: keeper disable 1: keeper enable"]
            pub type KE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PE` reader - pull enable 0: pull disable 1: pull enable"]
            pub type PE_R = crate::BitReader;
            #[doc = "Field `PE` writer - pull enable 0: pull disable 1: pull enable"]
            pub type PE_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PS` reader - pull select 0: pull down 1: pull up"]
            pub type PS_R = crate::BitReader;
            #[doc = "Field `PS` writer - pull select 0: pull down 1: pull up"]
            pub type PS_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `PRS` reader - select pull up/down internal resistance strength: For pull down, only have 100 Kohm resistance For pull up: 00: 100 KOhm 01: 47 KOhm 10: 22 KOhm 11: 22 KOhm"]
            pub type PRS_R = crate::FieldReader;
            #[doc = "Field `PRS` writer - select pull up/down internal resistance strength: For pull down, only have 100 Kohm resistance For pull up: 00: 100 KOhm 01: 47 KOhm 10: 22 KOhm 11: 22 KOhm"]
            pub type PRS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
            #[doc = "Field `HYS` reader - schmitt trigger enable 0: disable 1: enable"]
            pub type HYS_R = crate::BitReader;
            #[doc = "Field `HYS` writer - schmitt trigger enable 0: disable 1: enable"]
            pub type HYS_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bits 0:2 - drive strength 1.8V Mode: 000: 260 Ohm 001: 260 Ohm 010: 130 Ohm 011: 88 Ohm 100: 65 Ohm 101: 52 Ohm 110: 43 Ohm 111: 37 Ohm 3.3V Mode: 000: 157 Ohm 001: 157 Ohm 010: 78 Ohm 011: 53 Ohm 100: 39 Ohm 101: 32 Ohm 110: 26 Ohm 111: 23 Ohm"]
                #[inline(always)]
                pub fn ds(&self) -> DS_R {
                    DS_R::new((self.bits & 7) as u8)
                }
                #[doc = "Bits 4:5 - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise 00: Slow frequency slew rate(50Mhz) 01: Medium frequency slew rate(100 Mhz) 10: Fast frequency slew rate(150 Mhz) 11: Max frequency slew rate(200Mhz)"]
                #[inline(always)]
                pub fn spd(&self) -> SPD_R {
                    SPD_R::new(((self.bits >> 4) & 3) as u8)
                }
                #[doc = "Bit 6 - slew rate 0: Slow slew rate 1: Fast slew rate"]
                #[inline(always)]
                pub fn sr(&self) -> SR_R {
                    SR_R::new(((self.bits >> 6) & 1) != 0)
                }
                #[doc = "Bit 8 - open drain 0: open drain disable 1: open drain enable"]
                #[inline(always)]
                pub fn od(&self) -> OD_R {
                    OD_R::new(((self.bits >> 8) & 1) != 0)
                }
                #[doc = "Bit 16 - keeper capability enable 0: keeper disable 1: keeper enable"]
                #[inline(always)]
                pub fn ke(&self) -> KE_R {
                    KE_R::new(((self.bits >> 16) & 1) != 0)
                }
                #[doc = "Bit 17 - pull enable 0: pull disable 1: pull enable"]
                #[inline(always)]
                pub fn pe(&self) -> PE_R {
                    PE_R::new(((self.bits >> 17) & 1) != 0)
                }
                #[doc = "Bit 18 - pull select 0: pull down 1: pull up"]
                #[inline(always)]
                pub fn ps(&self) -> PS_R {
                    PS_R::new(((self.bits >> 18) & 1) != 0)
                }
                #[doc = "Bits 20:21 - select pull up/down internal resistance strength: For pull down, only have 100 Kohm resistance For pull up: 00: 100 KOhm 01: 47 KOhm 10: 22 KOhm 11: 22 KOhm"]
                #[inline(always)]
                pub fn prs(&self) -> PRS_R {
                    PRS_R::new(((self.bits >> 20) & 3) as u8)
                }
                #[doc = "Bit 24 - schmitt trigger enable 0: disable 1: enable"]
                #[inline(always)]
                pub fn hys(&self) -> HYS_R {
                    HYS_R::new(((self.bits >> 24) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:2 - drive strength 1.8V Mode: 000: 260 Ohm 001: 260 Ohm 010: 130 Ohm 011: 88 Ohm 100: 65 Ohm 101: 52 Ohm 110: 43 Ohm 111: 37 Ohm 3.3V Mode: 000: 157 Ohm 001: 157 Ohm 010: 78 Ohm 011: 53 Ohm 100: 39 Ohm 101: 32 Ohm 110: 26 Ohm 111: 23 Ohm"]
                #[inline(always)]
                #[must_use]
                pub fn ds(&mut self) -> DS_W<PAD_CTL_SPEC> {
                    DS_W::new(self, 0)
                }
                #[doc = "Bits 4:5 - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise 00: Slow frequency slew rate(50Mhz) 01: Medium frequency slew rate(100 Mhz) 10: Fast frequency slew rate(150 Mhz) 11: Max frequency slew rate(200Mhz)"]
                #[inline(always)]
                #[must_use]
                pub fn spd(&mut self) -> SPD_W<PAD_CTL_SPEC> {
                    SPD_W::new(self, 4)
                }
                #[doc = "Bit 6 - slew rate 0: Slow slew rate 1: Fast slew rate"]
                #[inline(always)]
                #[must_use]
                pub fn sr(&mut self) -> SR_W<PAD_CTL_SPEC> {
                    SR_W::new(self, 6)
                }
                #[doc = "Bit 8 - open drain 0: open drain disable 1: open drain enable"]
                #[inline(always)]
                #[must_use]
                pub fn od(&mut self) -> OD_W<PAD_CTL_SPEC> {
                    OD_W::new(self, 8)
                }
                #[doc = "Bit 16 - keeper capability enable 0: keeper disable 1: keeper enable"]
                #[inline(always)]
                #[must_use]
                pub fn ke(&mut self) -> KE_W<PAD_CTL_SPEC> {
                    KE_W::new(self, 16)
                }
                #[doc = "Bit 17 - pull enable 0: pull disable 1: pull enable"]
                #[inline(always)]
                #[must_use]
                pub fn pe(&mut self) -> PE_W<PAD_CTL_SPEC> {
                    PE_W::new(self, 17)
                }
                #[doc = "Bit 18 - pull select 0: pull down 1: pull up"]
                #[inline(always)]
                #[must_use]
                pub fn ps(&mut self) -> PS_W<PAD_CTL_SPEC> {
                    PS_W::new(self, 18)
                }
                #[doc = "Bits 20:21 - select pull up/down internal resistance strength: For pull down, only have 100 Kohm resistance For pull up: 00: 100 KOhm 01: 47 KOhm 10: 22 KOhm 11: 22 KOhm"]
                #[inline(always)]
                #[must_use]
                pub fn prs(&mut self) -> PRS_W<PAD_CTL_SPEC> {
                    PRS_W::new(self, 20)
                }
                #[doc = "Bit 24 - schmitt trigger enable 0: disable 1: enable"]
                #[inline(always)]
                #[must_use]
                pub fn hys(&mut self) -> HYS_W<PAD_CTL_SPEC> {
                    HYS_W::new(self, 24)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PAD SETTINGS\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pad_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pad_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct PAD_CTL_SPEC;
            impl crate::RegisterSpec for PAD_CTL_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`pad_ctl::R`](R) reader structure"]
            impl crate::Readable for PAD_CTL_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`pad_ctl::W`](W) writer structure"]
            impl crate::Writable for PAD_CTL_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets PAD_CTL to value 0x0101_0056"]
            impl crate::Resettable for PAD_CTL_SPEC {
                const RESET_VALUE: u32 = 0x0101_0056;
            }
        }
    }
}
#[doc = "PIOC"]
pub struct PIOC {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PIOC {}
impl PIOC {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const ioc::RegisterBlock = 0xf411_8000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const ioc::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PIOC {
    type Target = ioc::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PIOC {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PIOC").finish()
    }
}
#[doc = "PIOC"]
pub use self::ioc as pioc;
#[doc = "PLLCTLV2"]
pub struct PLLCTLV2 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PLLCTLV2 {}
impl PLLCTLV2 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const pllctlv2::RegisterBlock = 0xf40c_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const pllctlv2::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PLLCTLV2 {
    type Target = pllctlv2::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PLLCTLV2 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PLLCTLV2").finish()
    }
}
#[doc = "PLLCTLV2"]
pub mod pllctlv2 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        xtal: XTAL,
        _reserved1: [u8; 0x7c],
        pll: (),
    }
    impl RegisterBlock {
        #[doc = "0x00 - OSC configuration"]
        #[inline(always)]
        pub const fn xtal(&self) -> &XTAL {
            &self.xtal
        }
        #[doc = "0x80..0x164 - no description available"]
        #[inline(always)]
        pub const fn pll(&self, n: usize) -> &PLL {
            #[allow(clippy::no_effect)]
            [(); 3][n];
            unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(128)
                    .add(128 * n)
                    .cast()
            }
        }
        #[doc = "Iterator for array of:"]
        #[doc = "0x80..0x164 - no description available"]
        #[inline(always)]
        pub fn pll_iter(&self) -> impl Iterator<Item = &PLL> {
            (0..3).map(move |n| unsafe {
                &*(self as *const Self)
                    .cast::<u8>()
                    .add(128)
                    .add(128 * n)
                    .cast()
            })
        }
        #[doc = "0x80..0xcc - no description available"]
        #[inline(always)]
        pub const fn pllpll0(&self) -> &PLL {
            self.pll(0)
        }
        #[doc = "0x100..0x14c - no description available"]
        #[inline(always)]
        pub const fn pllpll1(&self) -> &PLL {
            self.pll(1)
        }
        #[doc = "0x180..0x1cc - no description available"]
        #[inline(always)]
        pub const fn pllpll2(&self) -> &PLL {
            self.pll(2)
        }
    }
    #[doc = "XTAL (rw) register accessor: OSC configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xtal::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xtal::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@xtal`]
module"]
    pub type XTAL = crate::Reg<xtal::XTAL_SPEC>;
    #[doc = "OSC configuration"]
    pub mod xtal {
        #[doc = "Register `XTAL` reader"]
        pub type R = crate::R<XTAL_SPEC>;
        #[doc = "Register `XTAL` writer"]
        pub type W = crate::W<XTAL_SPEC>;
        #[doc = "Field `RAMP_TIME` reader - Rampup time of XTAL oscillator in cycles of RC24M clock 0: 0 cycle 1: 1 cycle 2: 2 cycle 1048575: 1048575 cycles"]
        pub type RAMP_TIME_R = crate::FieldReader<u32>;
        #[doc = "Field `RAMP_TIME` writer - Rampup time of XTAL oscillator in cycles of RC24M clock 0: 0 cycle 1: 1 cycle 2: 2 cycle 1048575: 1048575 cycles"]
        pub type RAMP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        #[doc = "Field `ENABLE` reader - Crystal oscillator enable status 0: Oscillator is off 1: Oscillator is on"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `RESPONSE` reader - Crystal oscillator status 0: Oscillator is not stable 1: Oscillator is stable for use"]
        pub type RESPONSE_R = crate::BitReader;
        #[doc = "Field `BUSY` reader - Busy flag 0: Oscillator is working or shutdown 1: Oscillator is changing status"]
        pub type BUSY_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:19 - Rampup time of XTAL oscillator in cycles of RC24M clock 0: 0 cycle 1: 1 cycle 2: 2 cycle 1048575: 1048575 cycles"]
            #[inline(always)]
            pub fn ramp_time(&self) -> RAMP_TIME_R {
                RAMP_TIME_R::new(self.bits & 0x000f_ffff)
            }
            #[doc = "Bit 28 - Crystal oscillator enable status 0: Oscillator is off 1: Oscillator is on"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(((self.bits >> 28) & 1) != 0)
            }
            #[doc = "Bit 29 - Crystal oscillator status 0: Oscillator is not stable 1: Oscillator is stable for use"]
            #[inline(always)]
            pub fn response(&self) -> RESPONSE_R {
                RESPONSE_R::new(((self.bits >> 29) & 1) != 0)
            }
            #[doc = "Bit 31 - Busy flag 0: Oscillator is working or shutdown 1: Oscillator is changing status"]
            #[inline(always)]
            pub fn busy(&self) -> BUSY_R {
                BUSY_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - Rampup time of XTAL oscillator in cycles of RC24M clock 0: 0 cycle 1: 1 cycle 2: 2 cycle 1048575: 1048575 cycles"]
            #[inline(always)]
            #[must_use]
            pub fn ramp_time(&mut self) -> RAMP_TIME_W<XTAL_SPEC> {
                RAMP_TIME_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "OSC configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`xtal::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`xtal::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct XTAL_SPEC;
        impl crate::RegisterSpec for XTAL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`xtal::R`](R) reader structure"]
        impl crate::Readable for XTAL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`xtal::W`](W) writer structure"]
        impl crate::Writable for XTAL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets XTAL to value 0x0001_ffff"]
        impl crate::Resettable for XTAL_SPEC {
            const RESET_VALUE: u32 = 0x0001_ffff;
        }
    }
    #[doc = "no description available"]
    pub use self::pll::PLL;
    #[doc = r"Cluster"]
    #[doc = "no description available"]
    pub mod pll {
        #[doc = r"Register block"]
        #[repr(C)]
        pub struct PLL {
            mfi: MFI,
            mfn: MFN,
            mfd: MFD,
            ss_step: SS_STEP,
            ss_stop: SS_STOP,
            config: CONFIG,
            locktime: LOCKTIME,
            steptime: STEPTIME,
            advanced: ADVANCED,
            _reserved9: [u8; 0x1c],
            div: [DIV; 3],
        }
        impl PLL {
            #[doc = "0x00 - PLL0 multiple register"]
            #[inline(always)]
            pub const fn mfi(&self) -> &MFI {
                &self.mfi
            }
            #[doc = "0x04 - PLL0 fraction numerator register"]
            #[inline(always)]
            pub const fn mfn(&self) -> &MFN {
                &self.mfn
            }
            #[doc = "0x08 - PLL0 fraction demoninator register"]
            #[inline(always)]
            pub const fn mfd(&self) -> &MFD {
                &self.mfd
            }
            #[doc = "0x0c - PLL0 spread spectrum step register"]
            #[inline(always)]
            pub const fn ss_step(&self) -> &SS_STEP {
                &self.ss_step
            }
            #[doc = "0x10 - PLL0 spread spectrum stop register"]
            #[inline(always)]
            pub const fn ss_stop(&self) -> &SS_STOP {
                &self.ss_stop
            }
            #[doc = "0x14 - PLL0 confguration register"]
            #[inline(always)]
            pub const fn config(&self) -> &CONFIG {
                &self.config
            }
            #[doc = "0x18 - PLL0 lock time register"]
            #[inline(always)]
            pub const fn locktime(&self) -> &LOCKTIME {
                &self.locktime
            }
            #[doc = "0x1c - PLL0 step time register"]
            #[inline(always)]
            pub const fn steptime(&self) -> &STEPTIME {
                &self.steptime
            }
            #[doc = "0x20 - PLL0 advance configuration register"]
            #[inline(always)]
            pub const fn advanced(&self) -> &ADVANCED {
                &self.advanced
            }
            #[doc = "0x40..0x4c - no description available"]
            #[inline(always)]
            pub const fn div(&self, n: usize) -> &DIV {
                &self.div[n]
            }
            #[doc = "Iterator for array of:"]
            #[doc = "0x40..0x4c - no description available"]
            #[inline(always)]
            pub fn div_iter(&self) -> impl Iterator<Item = &DIV> {
                self.div.iter()
            }
            #[doc = "0x40 - no description available"]
            #[inline(always)]
            pub const fn divdiv0(&self) -> &DIV {
                self.div(0)
            }
            #[doc = "0x44 - no description available"]
            #[inline(always)]
            pub const fn divdiv1(&self) -> &DIV {
                self.div(1)
            }
            #[doc = "0x48 - no description available"]
            #[inline(always)]
            pub const fn divdiv2(&self) -> &DIV {
                self.div(2)
            }
        }
        #[doc = "MFI (rw) register accessor: PLL0 multiple register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfi::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfi::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfi`]
module"]
        pub type MFI = crate::Reg<mfi::MFI_SPEC>;
        #[doc = "PLL0 multiple register"]
        pub mod mfi {
            #[doc = "Register `MFI` reader"]
            pub type R = crate::R<MFI_SPEC>;
            #[doc = "Register `MFI` writer"]
            pub type W = crate::W<MFI_SPEC>;
            #[doc = "Field `MFI` reader - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) 0-15: invalid 16: divide by 16 17: divide by17 . . . 42: divide by 42 43~:invalid"]
            pub type MFI_R = crate::FieldReader;
            #[doc = "Field `MFI` writer - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) 0-15: invalid 16: divide by 16 17: divide by17 . . . 42: divide by 42 43~:invalid"]
            pub type MFI_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
            #[doc = "Field `ENABLE` reader - PLL enable status 0: PLL is off 1: PLL is on"]
            pub type ENABLE_R = crate::BitReader;
            #[doc = "Field `RESPONSE` reader - PLL status 0: PLL is not stable 1: PLL is stable for use"]
            pub type RESPONSE_R = crate::BitReader;
            #[doc = "Field `BUSY` reader - Busy flag 0: PLL is stable or shutdown 1: PLL is changing status"]
            pub type BUSY_R = crate::BitReader;
            impl R {
                #[doc = "Bits 0:6 - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) 0-15: invalid 16: divide by 16 17: divide by17 . . . 42: divide by 42 43~:invalid"]
                #[inline(always)]
                pub fn mfi(&self) -> MFI_R {
                    MFI_R::new((self.bits & 0x7f) as u8)
                }
                #[doc = "Bit 28 - PLL enable status 0: PLL is off 1: PLL is on"]
                #[inline(always)]
                pub fn enable(&self) -> ENABLE_R {
                    ENABLE_R::new(((self.bits >> 28) & 1) != 0)
                }
                #[doc = "Bit 29 - PLL status 0: PLL is not stable 1: PLL is stable for use"]
                #[inline(always)]
                pub fn response(&self) -> RESPONSE_R {
                    RESPONSE_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 31 - Busy flag 0: PLL is stable or shutdown 1: PLL is changing status"]
                #[inline(always)]
                pub fn busy(&self) -> BUSY_R {
                    BUSY_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:6 - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) 0-15: invalid 16: divide by 16 17: divide by17 . . . 42: divide by 42 43~:invalid"]
                #[inline(always)]
                #[must_use]
                pub fn mfi(&mut self) -> MFI_W<MFI_SPEC> {
                    MFI_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 multiple register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfi::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfi::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MFI_SPEC;
            impl crate::RegisterSpec for MFI_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`mfi::R`](R) reader structure"]
            impl crate::Readable for MFI_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`mfi::W`](W) writer structure"]
            impl crate::Writable for MFI_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets MFI to value 0x10"]
            impl crate::Resettable for MFI_SPEC {
                const RESET_VALUE: u32 = 0x10;
            }
        }
        #[doc = "MFN (rw) register accessor: PLL0 fraction numerator register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfn::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfn::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfn`]
module"]
        pub type MFN = crate::Reg<mfn::MFN_SPEC>;
        #[doc = "PLL0 fraction numerator register"]
        pub mod mfn {
            #[doc = "Register `MFN` reader"]
            pub type R = crate::R<MFN_SPEC>;
            #[doc = "Register `MFN` writer"]
            pub type W = crate::W<MFN_SPEC>;
            #[doc = "Field `MFN` reader - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running."]
            pub type MFN_R = crate::FieldReader<u32>;
            #[doc = "Field `MFN` writer - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running."]
            pub type MFN_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
            impl R {
                #[doc = "Bits 0:29 - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running."]
                #[inline(always)]
                pub fn mfn(&self) -> MFN_R {
                    MFN_R::new(self.bits & 0x3fff_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:29 - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running."]
                #[inline(always)]
                #[must_use]
                pub fn mfn(&mut self) -> MFN_W<MFN_SPEC> {
                    MFN_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 fraction numerator register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfn::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfn::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MFN_SPEC;
            impl crate::RegisterSpec for MFN_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`mfn::R`](R) reader structure"]
            impl crate::Readable for MFN_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`mfn::W`](W) writer structure"]
            impl crate::Writable for MFN_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets MFN to value 0x0989_6800"]
            impl crate::Resettable for MFN_SPEC {
                const RESET_VALUE: u32 = 0x0989_6800;
            }
        }
        #[doc = "MFD (rw) register accessor: PLL0 fraction demoninator register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfd`]
module"]
        pub type MFD = crate::Reg<mfd::MFD_SPEC>;
        #[doc = "PLL0 fraction demoninator register"]
        pub mod mfd {
            #[doc = "Register `MFD` reader"]
            pub type R = crate::R<MFD_SPEC>;
            #[doc = "Register `MFD` writer"]
            pub type W = crate::W<MFD_SPEC>;
            #[doc = "Field `MFD` reader - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled."]
            pub type MFD_R = crate::FieldReader<u32>;
            #[doc = "Field `MFD` writer - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled."]
            pub type MFD_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
            impl R {
                #[doc = "Bits 0:29 - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled."]
                #[inline(always)]
                pub fn mfd(&self) -> MFD_R {
                    MFD_R::new(self.bits & 0x3fff_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:29 - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled."]
                #[inline(always)]
                #[must_use]
                pub fn mfd(&mut self) -> MFD_W<MFD_SPEC> {
                    MFD_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 fraction demoninator register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct MFD_SPEC;
            impl crate::RegisterSpec for MFD_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`mfd::R`](R) reader structure"]
            impl crate::Readable for MFD_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`mfd::W`](W) writer structure"]
            impl crate::Writable for MFD_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets MFD to value 0x0e4e_1c00"]
            impl crate::Resettable for MFD_SPEC {
                const RESET_VALUE: u32 = 0x0e4e_1c00;
            }
        }
        #[doc = "SS_STEP (rw) register accessor: PLL0 spread spectrum step register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_step::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_step::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_step`]
module"]
        pub type SS_STEP = crate::Reg<ss_step::SS_STEP_SPEC>;
        #[doc = "PLL0 spread spectrum step register"]
        pub mod ss_step {
            #[doc = "Register `SS_STEP` reader"]
            pub type R = crate::R<SS_STEP_SPEC>;
            #[doc = "Register `SS_STEP` writer"]
            pub type W = crate::W<SS_STEP_SPEC>;
            #[doc = "Field `STEP` reader - Step of spread spectrum modulator. This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
            pub type STEP_R = crate::FieldReader<u32>;
            #[doc = "Field `STEP` writer - Step of spread spectrum modulator. This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
            pub type STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
            impl R {
                #[doc = "Bits 0:29 - Step of spread spectrum modulator. This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
                #[inline(always)]
                pub fn step(&self) -> STEP_R {
                    STEP_R::new(self.bits & 0x3fff_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:29 - Step of spread spectrum modulator. This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
                #[inline(always)]
                #[must_use]
                pub fn step(&mut self) -> STEP_W<SS_STEP_SPEC> {
                    STEP_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 spread spectrum step register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_step::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_step::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SS_STEP_SPEC;
            impl crate::RegisterSpec for SS_STEP_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ss_step::R`](R) reader structure"]
            impl crate::Readable for SS_STEP_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ss_step::W`](W) writer structure"]
            impl crate::Writable for SS_STEP_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SS_STEP to value 0"]
            impl crate::Resettable for SS_STEP_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "SS_STOP (rw) register accessor: PLL0 spread spectrum stop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_stop::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_stop::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ss_stop`]
module"]
        pub type SS_STOP = crate::Reg<ss_stop::SS_STOP_SPEC>;
        #[doc = "PLL0 spread spectrum stop register"]
        pub mod ss_stop {
            #[doc = "Register `SS_STOP` reader"]
            pub type R = crate::R<SS_STOP_SPEC>;
            #[doc = "Register `SS_STOP` writer"]
            pub type W = crate::W<SS_STOP_SPEC>;
            #[doc = "Field `STOP` reader - Stop point of spread spectrum modulator This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
            pub type STOP_R = crate::FieldReader<u32>;
            #[doc = "Field `STOP` writer - Stop point of spread spectrum modulator This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
            pub type STOP_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
            impl R {
                #[doc = "Bits 0:29 - Stop point of spread spectrum modulator This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
                #[inline(always)]
                pub fn stop(&self) -> STOP_R {
                    STOP_R::new(self.bits & 0x3fff_ffff)
                }
            }
            impl W {
                #[doc = "Bits 0:29 - Stop point of spread spectrum modulator This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled."]
                #[inline(always)]
                #[must_use]
                pub fn stop(&mut self) -> STOP_W<SS_STOP_SPEC> {
                    STOP_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 spread spectrum stop register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ss_stop::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ss_stop::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct SS_STOP_SPEC;
            impl crate::RegisterSpec for SS_STOP_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`ss_stop::R`](R) reader structure"]
            impl crate::Readable for SS_STOP_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`ss_stop::W`](W) writer structure"]
            impl crate::Writable for SS_STOP_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets SS_STOP to value 0"]
            impl crate::Resettable for SS_STOP_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "CONFIG (rw) register accessor: PLL0 confguration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`]
module"]
        pub type CONFIG = crate::Reg<config::CONFIG_SPEC>;
        #[doc = "PLL0 confguration register"]
        pub mod config {
            #[doc = "Register `CONFIG` reader"]
            pub type R = crate::R<CONFIG_SPEC>;
            #[doc = "Register `CONFIG` writer"]
            pub type W = crate::W<CONFIG_SPEC>;
            #[doc = "Field `REFSEL` reader - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. 0: XTAL24M 1: IRC24M"]
            pub type REFSEL_R = crate::BitReader;
            #[doc = "Field `REFSEL` writer - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. 0: XTAL24M 1: IRC24M"]
            pub type REFSEL_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SPREAD` reader - Enable spread spectrum function. This field supports changing during PLL running."]
            pub type SPREAD_R = crate::BitReader;
            #[doc = "Field `SPREAD` writer - Enable spread spectrum function. This field supports changing during PLL running."]
            pub type SPREAD_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 0 - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. 0: XTAL24M 1: IRC24M"]
                #[inline(always)]
                pub fn refsel(&self) -> REFSEL_R {
                    REFSEL_R::new((self.bits & 1) != 0)
                }
                #[doc = "Bit 8 - Enable spread spectrum function. This field supports changing during PLL running."]
                #[inline(always)]
                pub fn spread(&self) -> SPREAD_R {
                    SPREAD_R::new(((self.bits >> 8) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 0 - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. 0: XTAL24M 1: IRC24M"]
                #[inline(always)]
                #[must_use]
                pub fn refsel(&mut self) -> REFSEL_W<CONFIG_SPEC> {
                    REFSEL_W::new(self, 0)
                }
                #[doc = "Bit 8 - Enable spread spectrum function. This field supports changing during PLL running."]
                #[inline(always)]
                #[must_use]
                pub fn spread(&mut self) -> SPREAD_W<CONFIG_SPEC> {
                    SPREAD_W::new(self, 8)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 confguration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct CONFIG_SPEC;
            impl crate::RegisterSpec for CONFIG_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`config::R`](R) reader structure"]
            impl crate::Readable for CONFIG_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"]
            impl crate::Writable for CONFIG_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets CONFIG to value 0"]
            impl crate::Resettable for CONFIG_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "LOCKTIME (rw) register accessor: PLL0 lock time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`locktime::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`locktime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@locktime`]
module"]
        pub type LOCKTIME = crate::Reg<locktime::LOCKTIME_SPEC>;
        #[doc = "PLL0 lock time register"]
        pub mod locktime {
            #[doc = "Register `LOCKTIME` reader"]
            pub type R = crate::R<LOCKTIME_SPEC>;
            #[doc = "Register `LOCKTIME` writer"]
            pub type W = crate::W<LOCKTIME_SPEC>;
            #[doc = "Field `LOCKTIME` reader - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting."]
            pub type LOCKTIME_R = crate::FieldReader<u16>;
            #[doc = "Field `LOCKTIME` writer - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting."]
            pub type LOCKTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting."]
                #[inline(always)]
                pub fn locktime(&self) -> LOCKTIME_R {
                    LOCKTIME_R::new((self.bits & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting."]
                #[inline(always)]
                #[must_use]
                pub fn locktime(&mut self) -> LOCKTIME_W<LOCKTIME_SPEC> {
                    LOCKTIME_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 lock time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`locktime::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`locktime::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct LOCKTIME_SPEC;
            impl crate::RegisterSpec for LOCKTIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`locktime::R`](R) reader structure"]
            impl crate::Readable for LOCKTIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`locktime::W`](W) writer structure"]
            impl crate::Writable for LOCKTIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets LOCKTIME to value 0x09c4"]
            impl crate::Resettable for LOCKTIME_SPEC {
                const RESET_VALUE: u32 = 0x09c4;
            }
        }
        #[doc = "STEPTIME (rw) register accessor: PLL0 step time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`steptime::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`steptime::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@steptime`]
module"]
        pub type STEPTIME = crate::Reg<steptime::STEPTIME_SPEC>;
        #[doc = "PLL0 step time register"]
        pub mod steptime {
            #[doc = "Register `STEPTIME` reader"]
            pub type R = crate::R<STEPTIME_SPEC>;
            #[doc = "Register `STEPTIME` writer"]
            pub type W = crate::W<STEPTIME_SPEC>;
            #[doc = "Field `STEPTIME` reader - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500."]
            pub type STEPTIME_R = crate::FieldReader<u16>;
            #[doc = "Field `STEPTIME` writer - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500."]
            pub type STEPTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
            impl R {
                #[doc = "Bits 0:15 - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500."]
                #[inline(always)]
                pub fn steptime(&self) -> STEPTIME_R {
                    STEPTIME_R::new((self.bits & 0xffff) as u16)
                }
            }
            impl W {
                #[doc = "Bits 0:15 - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500."]
                #[inline(always)]
                #[must_use]
                pub fn steptime(&mut self) -> STEPTIME_W<STEPTIME_SPEC> {
                    STEPTIME_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 step time register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`steptime::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`steptime::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct STEPTIME_SPEC;
            impl crate::RegisterSpec for STEPTIME_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`steptime::R`](R) reader structure"]
            impl crate::Readable for STEPTIME_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`steptime::W`](W) writer structure"]
            impl crate::Writable for STEPTIME_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets STEPTIME to value 0x09c4"]
            impl crate::Resettable for STEPTIME_SPEC {
                const RESET_VALUE: u32 = 0x09c4;
            }
        }
        #[doc = "ADVANCED (rw) register accessor: PLL0 advance configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`advanced::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`advanced::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@advanced`]
module"]
        pub type ADVANCED = crate::Reg<advanced::ADVANCED_SPEC>;
        #[doc = "PLL0 advance configuration register"]
        pub mod advanced {
            #[doc = "Register `ADVANCED` reader"]
            pub type R = crate::R<ADVANCED_SPEC>;
            #[doc = "Register `ADVANCED` writer"]
            pub type W = crate::W<ADVANCED_SPEC>;
            #[doc = "Field `DITHER` reader - Enable dither function"]
            pub type DITHER_R = crate::BitReader;
            #[doc = "Field `DITHER` writer - Enable dither function"]
            pub type DITHER_W<'a, REG> = crate::BitWriter<'a, REG>;
            #[doc = "Field `SLOW` reader - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. 0: fast lock enabled, lock time is 100us 1: fast lock disabled, lock time is 400us"]
            pub type SLOW_R = crate::BitReader;
            #[doc = "Field `SLOW` writer - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. 0: fast lock enabled, lock time is 100us 1: fast lock disabled, lock time is 400us"]
            pub type SLOW_W<'a, REG> = crate::BitWriter<'a, REG>;
            impl R {
                #[doc = "Bit 24 - Enable dither function"]
                #[inline(always)]
                pub fn dither(&self) -> DITHER_R {
                    DITHER_R::new(((self.bits >> 24) & 1) != 0)
                }
                #[doc = "Bit 28 - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. 0: fast lock enabled, lock time is 100us 1: fast lock disabled, lock time is 400us"]
                #[inline(always)]
                pub fn slow(&self) -> SLOW_R {
                    SLOW_R::new(((self.bits >> 28) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bit 24 - Enable dither function"]
                #[inline(always)]
                #[must_use]
                pub fn dither(&mut self) -> DITHER_W<ADVANCED_SPEC> {
                    DITHER_W::new(self, 24)
                }
                #[doc = "Bit 28 - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. 0: fast lock enabled, lock time is 100us 1: fast lock disabled, lock time is 400us"]
                #[inline(always)]
                #[must_use]
                pub fn slow(&mut self) -> SLOW_W<ADVANCED_SPEC> {
                    SLOW_W::new(self, 28)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "PLL0 advance configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`advanced::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`advanced::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct ADVANCED_SPEC;
            impl crate::RegisterSpec for ADVANCED_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`advanced::R`](R) reader structure"]
            impl crate::Readable for ADVANCED_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`advanced::W`](W) writer structure"]
            impl crate::Writable for ADVANCED_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets ADVANCED to value 0"]
            impl crate::Resettable for ADVANCED_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
        #[doc = "DIV (rw) register accessor: no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@div`]
module"]
        pub type DIV = crate::Reg<div::DIV_SPEC>;
        #[doc = "no description available"]
        pub mod div {
            #[doc = "Register `DIV[%s]` reader"]
            pub type R = crate::R<DIV_SPEC>;
            #[doc = "Register `DIV[%s]` writer"]
            pub type W = crate::W<DIV_SPEC>;
            #[doc = "Field `DIV` reader - Divider factor, divider factor is DIV/5 + 1 0: divide by 1 1: divide by 1.2 2: divide by 1.4 . . . 63: divide by 13.6"]
            pub type DIV_R = crate::FieldReader;
            #[doc = "Field `DIV` writer - Divider factor, divider factor is DIV/5 + 1 0: divide by 1 1: divide by 1.2 2: divide by 1.4 . . . 63: divide by 13.6"]
            pub type DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
            #[doc = "Field `ENABLE` reader - Divider enable status 0: Divider is off 1: Divider is on"]
            pub type ENABLE_R = crate::BitReader;
            #[doc = "Field `RESPONSE` reader - Divider response status 0: Divider is not stable 1: Divider is stable for use"]
            pub type RESPONSE_R = crate::BitReader;
            #[doc = "Field `BUSY` reader - Busy flag 0: divider is working 1: divider is changing status"]
            pub type BUSY_R = crate::BitReader;
            impl R {
                #[doc = "Bits 0:5 - Divider factor, divider factor is DIV/5 + 1 0: divide by 1 1: divide by 1.2 2: divide by 1.4 . . . 63: divide by 13.6"]
                #[inline(always)]
                pub fn div(&self) -> DIV_R {
                    DIV_R::new((self.bits & 0x3f) as u8)
                }
                #[doc = "Bit 28 - Divider enable status 0: Divider is off 1: Divider is on"]
                #[inline(always)]
                pub fn enable(&self) -> ENABLE_R {
                    ENABLE_R::new(((self.bits >> 28) & 1) != 0)
                }
                #[doc = "Bit 29 - Divider response status 0: Divider is not stable 1: Divider is stable for use"]
                #[inline(always)]
                pub fn response(&self) -> RESPONSE_R {
                    RESPONSE_R::new(((self.bits >> 29) & 1) != 0)
                }
                #[doc = "Bit 31 - Busy flag 0: divider is working 1: divider is changing status"]
                #[inline(always)]
                pub fn busy(&self) -> BUSY_R {
                    BUSY_R::new(((self.bits >> 31) & 1) != 0)
                }
            }
            impl W {
                #[doc = "Bits 0:5 - Divider factor, divider factor is DIV/5 + 1 0: divide by 1 1: divide by 1.2 2: divide by 1.4 . . . 63: divide by 13.6"]
                #[inline(always)]
                #[must_use]
                pub fn div(&mut self) -> DIV_W<DIV_SPEC> {
                    DIV_W::new(self, 0)
                }
                #[doc = r" Writes raw bits to the register."]
                #[doc = r""]
                #[doc = r" # Safety"]
                #[doc = r""]
                #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
                #[inline(always)]
                pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                    self.bits = bits;
                    self
                }
            }
            #[doc = "no description available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
            pub struct DIV_SPEC;
            impl crate::RegisterSpec for DIV_SPEC {
                type Ux = u32;
            }
            #[doc = "`read()` method returns [`div::R`](R) reader structure"]
            impl crate::Readable for DIV_SPEC {}
            #[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"]
            impl crate::Writable for DIV_SPEC {
                const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
                const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            }
            #[doc = "`reset()` method sets DIV[%s]
to value 0"]
            impl crate::Resettable for DIV_SPEC {
                const RESET_VALUE: u32 = 0;
            }
        }
    }
}
#[doc = "PPOR"]
pub struct PPOR {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PPOR {}
impl PPOR {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const ppor::RegisterBlock = 0xf410_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const ppor::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PPOR {
    type Target = ppor::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PPOR {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PPOR").finish()
    }
}
#[doc = "PPOR"]
pub mod ppor {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        reset_flag: RESET_FLAG,
        reset_status: RESET_STATUS,
        reset_hold: RESET_HOLD,
        reset_enable: RESET_ENABLE,
        reset_type: RESET_TYPE,
        _reserved5: [u8; 0x08],
        software_reset: SOFTWARE_RESET,
    }
    impl RegisterBlock {
        #[doc = "0x00 - flag indicate reset source"]
        #[inline(always)]
        pub const fn reset_flag(&self) -> &RESET_FLAG {
            &self.reset_flag
        }
        #[doc = "0x04 - reset source status"]
        #[inline(always)]
        pub const fn reset_status(&self) -> &RESET_STATUS {
            &self.reset_status
        }
        #[doc = "0x08 - reset hold attribute"]
        #[inline(always)]
        pub const fn reset_hold(&self) -> &RESET_HOLD {
            &self.reset_hold
        }
        #[doc = "0x0c - reset source enable"]
        #[inline(always)]
        pub const fn reset_enable(&self) -> &RESET_ENABLE {
            &self.reset_enable
        }
        #[doc = "0x10 - reset type triggered by reset"]
        #[inline(always)]
        pub const fn reset_type(&self) -> &RESET_TYPE {
            &self.reset_type
        }
        #[doc = "0x1c - Software reset counter"]
        #[inline(always)]
        pub const fn software_reset(&self) -> &SOFTWARE_RESET {
            &self.software_reset
        }
    }
    #[doc = "RESET_FLAG (rw) register accessor: flag indicate reset source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_flag::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_flag::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_flag`]
module"]
    pub type RESET_FLAG = crate::Reg<reset_flag::RESET_FLAG_SPEC>;
    #[doc = "flag indicate reset source"]
    pub mod reset_flag {
        #[doc = "Register `RESET_FLAG` reader"]
        pub type R = crate::R<RESET_FLAG_SPEC>;
        #[doc = "Register `RESET_FLAG` writer"]
        pub type W = crate::W<RESET_FLAG_SPEC>;
        #[doc = "Field `FLAG` writer - reset reason of last hard reset, write 1 to clear each bit 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type FLAG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - reset reason of last hard reset, write 1 to clear each bit 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            #[must_use]
            pub fn flag(&mut self) -> FLAG_W<RESET_FLAG_SPEC> {
                FLAG_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "flag indicate reset source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_flag::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_flag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RESET_FLAG_SPEC;
        impl crate::RegisterSpec for RESET_FLAG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`reset_flag::R`](R) reader structure"]
        impl crate::Readable for RESET_FLAG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`reset_flag::W`](W) writer structure"]
        impl crate::Writable for RESET_FLAG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RESET_FLAG to value 0"]
        impl crate::Resettable for RESET_FLAG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RESET_STATUS (rw) register accessor: reset source status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_status`]
module"]
    pub type RESET_STATUS = crate::Reg<reset_status::RESET_STATUS_SPEC>;
    #[doc = "reset source status"]
    pub mod reset_status {
        #[doc = "Register `RESET_STATUS` reader"]
        pub type R = crate::R<RESET_STATUS_SPEC>;
        #[doc = "Register `RESET_STATUS` writer"]
        pub type W = crate::W<RESET_STATUS_SPEC>;
        #[doc = "Field `STATUS` reader - current status of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type STATUS_R = crate::FieldReader<u32>;
        impl R {
            #[doc = "Bits 0:31 - current status of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            pub fn status(&self) -> STATUS_R {
                STATUS_R::new(self.bits)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "reset source status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RESET_STATUS_SPEC;
        impl crate::RegisterSpec for RESET_STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`reset_status::R`](R) reader structure"]
        impl crate::Readable for RESET_STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`reset_status::W`](W) writer structure"]
        impl crate::Writable for RESET_STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RESET_STATUS to value 0"]
        impl crate::Resettable for RESET_STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RESET_HOLD (rw) register accessor: reset hold attribute\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_hold::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_hold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_hold`]
module"]
    pub type RESET_HOLD = crate::Reg<reset_hold::RESET_HOLD_SPEC>;
    #[doc = "reset hold attribute"]
    pub mod reset_hold {
        #[doc = "Register `RESET_HOLD` reader"]
        pub type R = crate::R<RESET_HOLD_SPEC>;
        #[doc = "Register `RESET_HOLD` writer"]
        pub type W = crate::W<RESET_HOLD_SPEC>;
        #[doc = "Field `HOLD` reader - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type HOLD_R = crate::FieldReader<u32>;
        #[doc = "Field `HOLD` writer - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            pub fn hold(&self) -> HOLD_R {
                HOLD_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            #[must_use]
            pub fn hold(&mut self) -> HOLD_W<RESET_HOLD_SPEC> {
                HOLD_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "reset hold attribute\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_hold::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_hold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RESET_HOLD_SPEC;
        impl crate::RegisterSpec for RESET_HOLD_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`reset_hold::R`](R) reader structure"]
        impl crate::Readable for RESET_HOLD_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`reset_hold::W`](W) writer structure"]
        impl crate::Writable for RESET_HOLD_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RESET_HOLD to value 0"]
        impl crate::Resettable for RESET_HOLD_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "RESET_ENABLE (rw) register accessor: reset source enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_enable::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_enable`]
module"]
    pub type RESET_ENABLE = crate::Reg<reset_enable::RESET_ENABLE_SPEC>;
    #[doc = "reset source enable"]
    pub mod reset_enable {
        #[doc = "Register `RESET_ENABLE` reader"]
        pub type R = crate::R<RESET_ENABLE_SPEC>;
        #[doc = "Register `RESET_ENABLE` writer"]
        pub type W = crate::W<RESET_ENABLE_SPEC>;
        #[doc = "Field `ENABLE` reader - enable of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type ENABLE_R = crate::FieldReader<u32>;
        #[doc = "Field `ENABLE` writer - enable of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - enable of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - enable of reset sources 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<RESET_ENABLE_SPEC> {
                ENABLE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "reset source enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RESET_ENABLE_SPEC;
        impl crate::RegisterSpec for RESET_ENABLE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`reset_enable::R`](R) reader structure"]
        impl crate::Readable for RESET_ENABLE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`reset_enable::W`](W) writer structure"]
        impl crate::Writable for RESET_ENABLE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RESET_ENABLE to value 0xffff_ffff"]
        impl crate::Resettable for RESET_ENABLE_SPEC {
            const RESET_VALUE: u32 = 0xffff_ffff;
        }
    }
    #[doc = "RESET_TYPE (rw) register accessor: reset type triggered by reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_type::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_type::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reset_type`]
module"]
    pub type RESET_TYPE = crate::Reg<reset_type::RESET_TYPE_SPEC>;
    #[doc = "reset type triggered by reset"]
    pub mod reset_type {
        #[doc = "Register `RESET_TYPE` reader"]
        pub type R = crate::R<RESET_TYPE_SPEC>;
        #[doc = "Register `RESET_TYPE` writer"]
        pub type W = crate::W<RESET_TYPE_SPEC>;
        #[doc = "Field `TYPE` reader - reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type TYPE_R = crate::FieldReader<u32>;
        #[doc = "Field `TYPE` writer - reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
        pub type TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            pub fn type_(&self) -> TYPE_R {
                TYPE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem 0: brownout 1: temperature 4: debug reset 5: jtag soft reset 8: cpu0 lockup(not available) 9: cpu1 lockup(not available) 10: cpu0 request(not available) 11: cpu1 request(not available) 16: watch dog 0 17: watch dog 1 18: watch dog 2(not available) 19: watch dog 3(not available) 24: pmic watch dog 30: jtag ieee reset 31: software"]
            #[inline(always)]
            #[must_use]
            pub fn type_(&mut self) -> TYPE_W<RESET_TYPE_SPEC> {
                TYPE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "reset type triggered by reset\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`reset_type::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`reset_type::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RESET_TYPE_SPEC;
        impl crate::RegisterSpec for RESET_TYPE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`reset_type::R`](R) reader structure"]
        impl crate::Readable for RESET_TYPE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`reset_type::W`](W) writer structure"]
        impl crate::Writable for RESET_TYPE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RESET_TYPE to value 0"]
        impl crate::Resettable for RESET_TYPE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SOFTWARE_RESET (rw) register accessor: Software reset counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`software_reset::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`software_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@software_reset`]
module"]
    pub type SOFTWARE_RESET = crate::Reg<software_reset::SOFTWARE_RESET_SPEC>;
    #[doc = "Software reset counter"]
    pub mod software_reset {
        #[doc = "Register `SOFTWARE_RESET` reader"]
        pub type R = crate::R<SOFTWARE_RESET_SPEC>;
        #[doc = "Register `SOFTWARE_RESET` writer"]
        pub type W = crate::W<SOFTWARE_RESET_SPEC>;
        #[doc = "Field `COUNTER` reader - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset"]
        pub type COUNTER_R = crate::FieldReader<u32>;
        #[doc = "Field `COUNTER` writer - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset"]
        pub type COUNTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset"]
            #[inline(always)]
            pub fn counter(&self) -> COUNTER_R {
                COUNTER_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset"]
            #[inline(always)]
            #[must_use]
            pub fn counter(&mut self) -> COUNTER_W<SOFTWARE_RESET_SPEC> {
                COUNTER_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Software reset counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`software_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`software_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SOFTWARE_RESET_SPEC;
        impl crate::RegisterSpec for SOFTWARE_RESET_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`software_reset::R`](R) reader structure"]
        impl crate::Readable for SOFTWARE_RESET_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`software_reset::W`](W) writer structure"]
        impl crate::Writable for SOFTWARE_RESET_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SOFTWARE_RESET to value 0"]
        impl crate::Resettable for SOFTWARE_RESET_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "PCFG"]
pub struct PCFG {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PCFG {}
impl PCFG {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const pcfg::RegisterBlock = 0xf410_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const pcfg::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PCFG {
    type Target = pcfg::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PCFG {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PCFG").finish()
    }
}
#[doc = "PCFG"]
pub mod pcfg {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        bandgap: BANDGAP,
        ldo1p1: LDO1P1,
        ldo2p5: LDO2P5,
        _reserved3: [u8; 0x04],
        dcdc_mode: DCDC_MODE,
        dcdc_lpmode: DCDC_LPMODE,
        dcdc_prot: DCDC_PROT,
        dcdc_current: DCDC_CURRENT,
        dcdc_advmode: DCDC_ADVMODE,
        dcdc_advparam: DCDC_ADVPARAM,
        dcdc_misc: DCDC_MISC,
        dcdc_debug: DCDC_DEBUG,
        dcdc_start_time: DCDC_START_TIME,
        dcdc_resume_time: DCDC_RESUME_TIME,
        _reserved13: [u8; 0x08],
        power_trap: POWER_TRAP,
        wake_cause: WAKE_CAUSE,
        wake_mask: WAKE_MASK,
        scg_ctrl: SCG_CTRL,
        _reserved17: [u8; 0x10],
        rc24m: RC24M,
        rc24m_track: RC24M_TRACK,
        track_target: TRACK_TARGET,
        status: STATUS,
    }
    impl RegisterBlock {
        #[doc = "0x00 - BANGGAP control"]
        #[inline(always)]
        pub const fn bandgap(&self) -> &BANDGAP {
            &self.bandgap
        }
        #[doc = "0x04 - 1V LDO config"]
        #[inline(always)]
        pub const fn ldo1p1(&self) -> &LDO1P1 {
            &self.ldo1p1
        }
        #[doc = "0x08 - 2.5V LDO config"]
        #[inline(always)]
        pub const fn ldo2p5(&self) -> &LDO2P5 {
            &self.ldo2p5
        }
        #[doc = "0x10 - DCDC mode select"]
        #[inline(always)]
        pub const fn dcdc_mode(&self) -> &DCDC_MODE {
            &self.dcdc_mode
        }
        #[doc = "0x14 - DCDC low power mode"]
        #[inline(always)]
        pub const fn dcdc_lpmode(&self) -> &DCDC_LPMODE {
            &self.dcdc_lpmode
        }
        #[doc = "0x18 - DCDC protection"]
        #[inline(always)]
        pub const fn dcdc_prot(&self) -> &DCDC_PROT {
            &self.dcdc_prot
        }
        #[doc = "0x1c - DCDC current estimation"]
        #[inline(always)]
        pub const fn dcdc_current(&self) -> &DCDC_CURRENT {
            &self.dcdc_current
        }
        #[doc = "0x20 - DCDC advance setting"]
        #[inline(always)]
        pub const fn dcdc_advmode(&self) -> &DCDC_ADVMODE {
            &self.dcdc_advmode
        }
        #[doc = "0x24 - DCDC advance parameter"]
        #[inline(always)]
        pub const fn dcdc_advparam(&self) -> &DCDC_ADVPARAM {
            &self.dcdc_advparam
        }
        #[doc = "0x28 - DCDC misc parameter"]
        #[inline(always)]
        pub const fn dcdc_misc(&self) -> &DCDC_MISC {
            &self.dcdc_misc
        }
        #[doc = "0x2c - DCDC Debug"]
        #[inline(always)]
        pub const fn dcdc_debug(&self) -> &DCDC_DEBUG {
            &self.dcdc_debug
        }
        #[doc = "0x30 - DCDC ramp time"]
        #[inline(always)]
        pub const fn dcdc_start_time(&self) -> &DCDC_START_TIME {
            &self.dcdc_start_time
        }
        #[doc = "0x34 - DCDC resume time"]
        #[inline(always)]
        pub const fn dcdc_resume_time(&self) -> &DCDC_RESUME_TIME {
            &self.dcdc_resume_time
        }
        #[doc = "0x40 - SOC power trap"]
        #[inline(always)]
        pub const fn power_trap(&self) -> &POWER_TRAP {
            &self.power_trap
        }
        #[doc = "0x44 - Wake up source"]
        #[inline(always)]
        pub const fn wake_cause(&self) -> &WAKE_CAUSE {
            &self.wake_cause
        }
        #[doc = "0x48 - Wake up mask"]
        #[inline(always)]
        pub const fn wake_mask(&self) -> &WAKE_MASK {
            &self.wake_mask
        }
        #[doc = "0x4c - Clock gate control in PMIC"]
        #[inline(always)]
        pub const fn scg_ctrl(&self) -> &SCG_CTRL {
            &self.scg_ctrl
        }
        #[doc = "0x60 - RC 24M config"]
        #[inline(always)]
        pub const fn rc24m(&self) -> &RC24M {
            &self.rc24m
        }
        #[doc = "0x64 - RC 24M track mode"]
        #[inline(always)]
        pub const fn rc24m_track(&self) -> &RC24M_TRACK {
            &self.rc24m_track
        }
        #[doc = "0x68 - RC 24M track target"]
        #[inline(always)]
        pub const fn track_target(&self) -> &TRACK_TARGET {
            &self.track_target
        }
        #[doc = "0x6c - RC 24M track status"]
        #[inline(always)]
        pub const fn status(&self) -> &STATUS {
            &self.status
        }
    }
    #[doc = "BANDGAP (rw) register accessor: BANGGAP control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bandgap::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bandgap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bandgap`]
module"]
    pub type BANDGAP = crate::Reg<bandgap::BANDGAP_SPEC>;
    #[doc = "BANGGAP control"]
    pub mod bandgap {
        #[doc = "Register `BANDGAP` reader"]
        pub type R = crate::R<BANDGAP_SPEC>;
        #[doc = "Register `BANDGAP` writer"]
        pub type W = crate::W<BANDGAP_SPEC>;
        #[doc = "Field `VBG_P50_TRIM` reader - Banggap 1.0V output trim value"]
        pub type VBG_P50_TRIM_R = crate::FieldReader;
        #[doc = "Field `VBG_P50_TRIM` writer - Banggap 1.0V output trim value"]
        pub type VBG_P50_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `VBG_P65_TRIM` reader - Banggap 1.0V output trim value"]
        pub type VBG_P65_TRIM_R = crate::FieldReader;
        #[doc = "Field `VBG_P65_TRIM` writer - Banggap 1.0V output trim value"]
        pub type VBG_P65_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `VBG_1P0_TRIM` reader - Banggap 1.0V output trim value"]
        pub type VBG_1P0_TRIM_R = crate::FieldReader;
        #[doc = "Field `VBG_1P0_TRIM` writer - Banggap 1.0V output trim value"]
        pub type VBG_1P0_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `VBG_TRIMMED` reader - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: bandgap is not trimmed 1: bandgap is trimmed"]
        pub type VBG_TRIMMED_R = crate::BitReader;
        #[doc = "Field `VBG_TRIMMED` writer - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: bandgap is not trimmed 1: bandgap is trimmed"]
        pub type VBG_TRIMMED_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:4 - Banggap 1.0V output trim value"]
            #[inline(always)]
            pub fn vbg_p50_trim(&self) -> VBG_P50_TRIM_R {
                VBG_P50_TRIM_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bits 8:12 - Banggap 1.0V output trim value"]
            #[inline(always)]
            pub fn vbg_p65_trim(&self) -> VBG_P65_TRIM_R {
                VBG_P65_TRIM_R::new(((self.bits >> 8) & 0x1f) as u8)
            }
            #[doc = "Bits 16:20 - Banggap 1.0V output trim value"]
            #[inline(always)]
            pub fn vbg_1p0_trim(&self) -> VBG_1P0_TRIM_R {
                VBG_1P0_TRIM_R::new(((self.bits >> 16) & 0x1f) as u8)
            }
            #[doc = "Bit 31 - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: bandgap is not trimmed 1: bandgap is trimmed"]
            #[inline(always)]
            pub fn vbg_trimmed(&self) -> VBG_TRIMMED_R {
                VBG_TRIMMED_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - Banggap 1.0V output trim value"]
            #[inline(always)]
            #[must_use]
            pub fn vbg_p50_trim(&mut self) -> VBG_P50_TRIM_W<BANDGAP_SPEC> {
                VBG_P50_TRIM_W::new(self, 0)
            }
            #[doc = "Bits 8:12 - Banggap 1.0V output trim value"]
            #[inline(always)]
            #[must_use]
            pub fn vbg_p65_trim(&mut self) -> VBG_P65_TRIM_W<BANDGAP_SPEC> {
                VBG_P65_TRIM_W::new(self, 8)
            }
            #[doc = "Bits 16:20 - Banggap 1.0V output trim value"]
            #[inline(always)]
            #[must_use]
            pub fn vbg_1p0_trim(&mut self) -> VBG_1P0_TRIM_W<BANDGAP_SPEC> {
                VBG_1P0_TRIM_W::new(self, 16)
            }
            #[doc = "Bit 31 - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: bandgap is not trimmed 1: bandgap is trimmed"]
            #[inline(always)]
            #[must_use]
            pub fn vbg_trimmed(&mut self) -> VBG_TRIMMED_W<BANDGAP_SPEC> {
                VBG_TRIMMED_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "BANGGAP control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bandgap::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bandgap::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct BANDGAP_SPEC;
        impl crate::RegisterSpec for BANDGAP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`bandgap::R`](R) reader structure"]
        impl crate::Readable for BANDGAP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`bandgap::W`](W) writer structure"]
        impl crate::Writable for BANDGAP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets BANDGAP to value 0x0010_1010"]
        impl crate::Resettable for BANDGAP_SPEC {
            const RESET_VALUE: u32 = 0x0010_1010;
        }
    }
    #[doc = "LDO1P1 (rw) register accessor: 1V LDO config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ldo1p1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ldo1p1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ldo1p1`]
module"]
    pub type LDO1P1 = crate::Reg<ldo1p1::LDO1P1_SPEC>;
    #[doc = "1V LDO config"]
    pub mod ldo1p1 {
        #[doc = "Register `LDO1P1` reader"]
        pub type R = crate::R<LDO1P1_SPEC>;
        #[doc = "Register `LDO1P1` writer"]
        pub type W = crate::W<LDO1P1_SPEC>;
        #[doc = "Field `VOLT` reader - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. 700: 700mV 720: 720mV . . . 1320:1320mV"]
        pub type VOLT_R = crate::FieldReader<u16>;
        #[doc = "Field `VOLT` writer - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. 700: 700mV 720: 720mV . . . 1320:1320mV"]
        pub type VOLT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `ENABLE` reader - LDO enable 0: turn off LDO 1: turn on LDO"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `ENABLE` writer - LDO enable 0: turn off LDO 1: turn on LDO"]
        pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:11 - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. 700: 700mV 720: 720mV . . . 1320:1320mV"]
            #[inline(always)]
            pub fn volt(&self) -> VOLT_R {
                VOLT_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bit 16 - LDO enable 0: turn off LDO 1: turn on LDO"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. 700: 700mV 720: 720mV . . . 1320:1320mV"]
            #[inline(always)]
            #[must_use]
            pub fn volt(&mut self) -> VOLT_W<LDO1P1_SPEC> {
                VOLT_W::new(self, 0)
            }
            #[doc = "Bit 16 - LDO enable 0: turn off LDO 1: turn on LDO"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<LDO1P1_SPEC> {
                ENABLE_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "1V LDO config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ldo1p1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ldo1p1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LDO1P1_SPEC;
        impl crate::RegisterSpec for LDO1P1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ldo1p1::R`](R) reader structure"]
        impl crate::Readable for LDO1P1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ldo1p1::W`](W) writer structure"]
        impl crate::Writable for LDO1P1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LDO1P1 to value 0x0001_044c"]
        impl crate::Resettable for LDO1P1_SPEC {
            const RESET_VALUE: u32 = 0x0001_044c;
        }
    }
    #[doc = "LDO2P5 (rw) register accessor: 2.5V LDO config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ldo2p5::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ldo2p5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ldo2p5`]
module"]
    pub type LDO2P5 = crate::Reg<ldo2p5::LDO2P5_SPEC>;
    #[doc = "2.5V LDO config"]
    pub mod ldo2p5 {
        #[doc = "Register `LDO2P5` reader"]
        pub type R = crate::R<LDO2P5_SPEC>;
        #[doc = "Register `LDO2P5` writer"]
        pub type W = crate::W<LDO2P5_SPEC>;
        #[doc = "Field `VOLT` reader - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. 2125: 2125mV 2150: 2150mV . . . 2900:2900mV"]
        pub type VOLT_R = crate::FieldReader<u16>;
        #[doc = "Field `VOLT` writer - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. 2125: 2125mV 2150: 2150mV . . . 2900:2900mV"]
        pub type VOLT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `ENABLE` reader - LDO enable 0: turn off LDO 1: turn on LDO"]
        pub type ENABLE_R = crate::BitReader;
        #[doc = "Field `ENABLE` writer - LDO enable 0: turn off LDO 1: turn on LDO"]
        pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `READY` reader - Ready flag, will set 1ms after enabled or voltage change 0: LDO is not ready for use 1: LDO is ready"]
        pub type READY_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:11 - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. 2125: 2125mV 2150: 2150mV . . . 2900:2900mV"]
            #[inline(always)]
            pub fn volt(&self) -> VOLT_R {
                VOLT_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bit 16 - LDO enable 0: turn off LDO 1: turn on LDO"]
            #[inline(always)]
            pub fn enable(&self) -> ENABLE_R {
                ENABLE_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 28 - Ready flag, will set 1ms after enabled or voltage change 0: LDO is not ready for use 1: LDO is ready"]
            #[inline(always)]
            pub fn ready(&self) -> READY_R {
                READY_R::new(((self.bits >> 28) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. 2125: 2125mV 2150: 2150mV . . . 2900:2900mV"]
            #[inline(always)]
            #[must_use]
            pub fn volt(&mut self) -> VOLT_W<LDO2P5_SPEC> {
                VOLT_W::new(self, 0)
            }
            #[doc = "Bit 16 - LDO enable 0: turn off LDO 1: turn on LDO"]
            #[inline(always)]
            #[must_use]
            pub fn enable(&mut self) -> ENABLE_W<LDO2P5_SPEC> {
                ENABLE_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "2.5V LDO config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ldo2p5::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ldo2p5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct LDO2P5_SPEC;
        impl crate::RegisterSpec for LDO2P5_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`ldo2p5::R`](R) reader structure"]
        impl crate::Readable for LDO2P5_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`ldo2p5::W`](W) writer structure"]
        impl crate::Writable for LDO2P5_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets LDO2P5 to value 0x09c4"]
        impl crate::Resettable for LDO2P5_SPEC {
            const RESET_VALUE: u32 = 0x09c4;
        }
    }
    #[doc = "DCDC_MODE (rw) register accessor: DCDC mode select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_mode`]
module"]
    pub type DCDC_MODE = crate::Reg<dcdc_mode::DCDC_MODE_SPEC>;
    #[doc = "DCDC mode select"]
    pub mod dcdc_mode {
        #[doc = "Register `DCDC_MODE` reader"]
        pub type R = crate::R<DCDC_MODE_SPEC>;
        #[doc = "Register `DCDC_MODE` writer"]
        pub type W = crate::W<DCDC_MODE_SPEC>;
        #[doc = "Field `VOLT` reader - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
        pub type VOLT_R = crate::FieldReader<u16>;
        #[doc = "Field `VOLT` writer - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
        pub type VOLT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        #[doc = "Field `MODE` reader - DCDC work mode XX0: trun off 001: basic mode 011: generic mode 101: automatic mode 111: expert mode"]
        pub type MODE_R = crate::FieldReader;
        #[doc = "Field `MODE` writer - DCDC work mode XX0: trun off 001: basic mode 011: generic mode 101: automatic mode 111: expert mode"]
        pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `READY` reader - Ready flag 0: DCDC is applying new change 1: DCDC is ready"]
        pub type READY_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:11 - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
            #[inline(always)]
            pub fn volt(&self) -> VOLT_R {
                VOLT_R::new((self.bits & 0x0fff) as u16)
            }
            #[doc = "Bits 16:18 - DCDC work mode XX0: trun off 001: basic mode 011: generic mode 101: automatic mode 111: expert mode"]
            #[inline(always)]
            pub fn mode(&self) -> MODE_R {
                MODE_R::new(((self.bits >> 16) & 7) as u8)
            }
            #[doc = "Bit 28 - Ready flag 0: DCDC is applying new change 1: DCDC is ready"]
            #[inline(always)]
            pub fn ready(&self) -> READY_R {
                READY_R::new(((self.bits >> 28) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
            #[inline(always)]
            #[must_use]
            pub fn volt(&mut self) -> VOLT_W<DCDC_MODE_SPEC> {
                VOLT_W::new(self, 0)
            }
            #[doc = "Bits 16:18 - DCDC work mode XX0: trun off 001: basic mode 011: generic mode 101: automatic mode 111: expert mode"]
            #[inline(always)]
            #[must_use]
            pub fn mode(&mut self) -> MODE_W<DCDC_MODE_SPEC> {
                MODE_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC mode select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_MODE_SPEC;
        impl crate::RegisterSpec for DCDC_MODE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_mode::R`](R) reader structure"]
        impl crate::Readable for DCDC_MODE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_mode::W`](W) writer structure"]
        impl crate::Writable for DCDC_MODE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_MODE to value 0x0001_047e"]
        impl crate::Resettable for DCDC_MODE_SPEC {
            const RESET_VALUE: u32 = 0x0001_047e;
        }
    }
    #[doc = "DCDC_LPMODE (rw) register accessor: DCDC low power mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_lpmode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_lpmode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_lpmode`]
module"]
    pub type DCDC_LPMODE = crate::Reg<dcdc_lpmode::DCDC_LPMODE_SPEC>;
    #[doc = "DCDC low power mode"]
    pub mod dcdc_lpmode {
        #[doc = "Register `DCDC_LPMODE` reader"]
        pub type R = crate::R<DCDC_LPMODE_SPEC>;
        #[doc = "Register `DCDC_LPMODE` writer"]
        pub type W = crate::W<DCDC_LPMODE_SPEC>;
        #[doc = "Field `STBY_VOLT` reader - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
        pub type STBY_VOLT_R = crate::FieldReader<u16>;
        #[doc = "Field `STBY_VOLT` writer - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
        pub type STBY_VOLT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
        impl R {
            #[doc = "Bits 0:11 - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
            #[inline(always)]
            pub fn stby_volt(&self) -> STBY_VOLT_R {
                STBY_VOLT_R::new((self.bits & 0x0fff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:11 - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. 600: 600mV 625: 625mV . . . 1375:1375mV"]
            #[inline(always)]
            #[must_use]
            pub fn stby_volt(&mut self) -> STBY_VOLT_W<DCDC_LPMODE_SPEC> {
                STBY_VOLT_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC low power mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_lpmode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_lpmode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_LPMODE_SPEC;
        impl crate::RegisterSpec for DCDC_LPMODE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_lpmode::R`](R) reader structure"]
        impl crate::Readable for DCDC_LPMODE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_lpmode::W`](W) writer structure"]
        impl crate::Writable for DCDC_LPMODE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_LPMODE to value 0x0384"]
        impl crate::Resettable for DCDC_LPMODE_SPEC {
            const RESET_VALUE: u32 = 0x0384;
        }
    }
    #[doc = "DCDC_PROT (rw) register accessor: DCDC protection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_prot::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_prot::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_prot`]
module"]
    pub type DCDC_PROT = crate::Reg<dcdc_prot::DCDC_PROT_SPEC>;
    #[doc = "DCDC protection"]
    pub mod dcdc_prot {
        #[doc = "Register `DCDC_PROT` reader"]
        pub type R = crate::R<DCDC_PROT_SPEC>;
        #[doc = "Register `DCDC_PROT` writer"]
        pub type W = crate::W<DCDC_PROT_SPEC>;
        #[doc = "Field `SHORT_FLAG` reader - short circuit flag 0: current is within limit 1: short circuits detected"]
        pub type SHORT_FLAG_R = crate::BitReader;
        #[doc = "Field `SHORT_CURRENT` reader - short circuit current setting 0: 2.0A, 1: 1.3A"]
        pub type SHORT_CURRENT_R = crate::BitReader;
        #[doc = "Field `SHORT_CURRENT` writer - short circuit current setting 0: 2.0A, 1: 1.3A"]
        pub type SHORT_CURRENT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DISABLE_SHORT` reader - disable output short circuit protection 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected 1: short circuit protection disabled"]
        pub type DISABLE_SHORT_R = crate::BitReader;
        #[doc = "Field `DISABLE_SHORT` writer - disable output short circuit protection 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected 1: short circuit protection disabled"]
        pub type DISABLE_SHORT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OVERVOLT_FLAG` reader - output over voltage flag 0: output is normal 1: output is unexpected high"]
        pub type OVERVOLT_FLAG_R = crate::BitReader;
        #[doc = "Field `DISABLE_OVERVOLTAGE` reader - ouput over voltage protection 0: protection enabled, DCDC will shut down is output voltage is unexpected high 1: protection disabled, DCDC continue to adjust output voltage"]
        pub type DISABLE_OVERVOLTAGE_R = crate::BitReader;
        #[doc = "Field `DISABLE_OVERVOLTAGE` writer - ouput over voltage protection 0: protection enabled, DCDC will shut down is output voltage is unexpected high 1: protection disabled, DCDC continue to adjust output voltage"]
        pub type DISABLE_OVERVOLTAGE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `POWER_LOSS_FLAG` reader - power loss 0: input power is good 1: input power is too low"]
        pub type POWER_LOSS_FLAG_R = crate::BitReader;
        #[doc = "Field `OVERLOAD_LP` reader - over current in low power mode 0: current is below setting 1: overcurrent happened in low power mode"]
        pub type OVERLOAD_LP_R = crate::BitReader;
        #[doc = "Field `ILIMIT_LP` reader - over current setting for low power mode 0:250mA 1:200mA"]
        pub type ILIMIT_LP_R = crate::BitReader;
        #[doc = "Field `ILIMIT_LP` writer - over current setting for low power mode 0:250mA 1:200mA"]
        pub type ILIMIT_LP_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - short circuit flag 0: current is within limit 1: short circuits detected"]
            #[inline(always)]
            pub fn short_flag(&self) -> SHORT_FLAG_R {
                SHORT_FLAG_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4 - short circuit current setting 0: 2.0A, 1: 1.3A"]
            #[inline(always)]
            pub fn short_current(&self) -> SHORT_CURRENT_R {
                SHORT_CURRENT_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 7 - disable output short circuit protection 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected 1: short circuit protection disabled"]
            #[inline(always)]
            pub fn disable_short(&self) -> DISABLE_SHORT_R {
                DISABLE_SHORT_R::new(((self.bits >> 7) & 1) != 0)
            }
            #[doc = "Bit 8 - output over voltage flag 0: output is normal 1: output is unexpected high"]
            #[inline(always)]
            pub fn overvolt_flag(&self) -> OVERVOLT_FLAG_R {
                OVERVOLT_FLAG_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 15 - ouput over voltage protection 0: protection enabled, DCDC will shut down is output voltage is unexpected high 1: protection disabled, DCDC continue to adjust output voltage"]
            #[inline(always)]
            pub fn disable_overvoltage(&self) -> DISABLE_OVERVOLTAGE_R {
                DISABLE_OVERVOLTAGE_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - power loss 0: input power is good 1: input power is too low"]
            #[inline(always)]
            pub fn power_loss_flag(&self) -> POWER_LOSS_FLAG_R {
                POWER_LOSS_FLAG_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 24 - over current in low power mode 0: current is below setting 1: overcurrent happened in low power mode"]
            #[inline(always)]
            pub fn overload_lp(&self) -> OVERLOAD_LP_R {
                OVERLOAD_LP_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 28 - over current setting for low power mode 0:250mA 1:200mA"]
            #[inline(always)]
            pub fn ilimit_lp(&self) -> ILIMIT_LP_R {
                ILIMIT_LP_R::new(((self.bits >> 28) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 4 - short circuit current setting 0: 2.0A, 1: 1.3A"]
            #[inline(always)]
            #[must_use]
            pub fn short_current(&mut self) -> SHORT_CURRENT_W<DCDC_PROT_SPEC> {
                SHORT_CURRENT_W::new(self, 4)
            }
            #[doc = "Bit 7 - disable output short circuit protection 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected 1: short circuit protection disabled"]
            #[inline(always)]
            #[must_use]
            pub fn disable_short(&mut self) -> DISABLE_SHORT_W<DCDC_PROT_SPEC> {
                DISABLE_SHORT_W::new(self, 7)
            }
            #[doc = "Bit 15 - ouput over voltage protection 0: protection enabled, DCDC will shut down is output voltage is unexpected high 1: protection disabled, DCDC continue to adjust output voltage"]
            #[inline(always)]
            #[must_use]
            pub fn disable_overvoltage(&mut self) -> DISABLE_OVERVOLTAGE_W<DCDC_PROT_SPEC> {
                DISABLE_OVERVOLTAGE_W::new(self, 15)
            }
            #[doc = "Bit 28 - over current setting for low power mode 0:250mA 1:200mA"]
            #[inline(always)]
            #[must_use]
            pub fn ilimit_lp(&mut self) -> ILIMIT_LP_W<DCDC_PROT_SPEC> {
                ILIMIT_LP_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC protection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_prot::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_PROT_SPEC;
        impl crate::RegisterSpec for DCDC_PROT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_prot::R`](R) reader structure"]
        impl crate::Readable for DCDC_PROT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_prot::W`](W) writer structure"]
        impl crate::Writable for DCDC_PROT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_PROT to value 0x10"]
        impl crate::Resettable for DCDC_PROT_SPEC {
            const RESET_VALUE: u32 = 0x10;
        }
    }
    #[doc = "DCDC_CURRENT (rw) register accessor: DCDC current estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_current::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_current::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_current`]
module"]
    pub type DCDC_CURRENT = crate::Reg<dcdc_current::DCDC_CURRENT_SPEC>;
    #[doc = "DCDC current estimation"]
    pub mod dcdc_current {
        #[doc = "Register `DCDC_CURRENT` reader"]
        pub type R = crate::R<DCDC_CURRENT_SPEC>;
        #[doc = "Register `DCDC_CURRENT` writer"]
        pub type W = crate::W<DCDC_CURRENT_SPEC>;
        #[doc = "Field `LEVEL` reader - DCDC current level, current level is num * 50mA"]
        pub type LEVEL_R = crate::FieldReader;
        #[doc = "Field `VALID` reader - Current level valid 0: data is invalid 1: data is valid"]
        pub type VALID_R = crate::BitReader;
        #[doc = "Field `ESTI_EN` reader - enable current measure"]
        pub type ESTI_EN_R = crate::BitReader;
        #[doc = "Field `ESTI_EN` writer - enable current measure"]
        pub type ESTI_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:4 - DCDC current level, current level is num * 50mA"]
            #[inline(always)]
            pub fn level(&self) -> LEVEL_R {
                LEVEL_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bit 8 - Current level valid 0: data is invalid 1: data is valid"]
            #[inline(always)]
            pub fn valid(&self) -> VALID_R {
                VALID_R::new(((self.bits >> 8) & 1) != 0)
            }
            #[doc = "Bit 15 - enable current measure"]
            #[inline(always)]
            pub fn esti_en(&self) -> ESTI_EN_R {
                ESTI_EN_R::new(((self.bits >> 15) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 15 - enable current measure"]
            #[inline(always)]
            #[must_use]
            pub fn esti_en(&mut self) -> ESTI_EN_W<DCDC_CURRENT_SPEC> {
                ESTI_EN_W::new(self, 15)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC current estimation\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_current::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_current::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_CURRENT_SPEC;
        impl crate::RegisterSpec for DCDC_CURRENT_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_current::R`](R) reader structure"]
        impl crate::Readable for DCDC_CURRENT_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_current::W`](W) writer structure"]
        impl crate::Writable for DCDC_CURRENT_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_CURRENT to value 0"]
        impl crate::Resettable for DCDC_CURRENT_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DCDC_ADVMODE (rw) register accessor: DCDC advance setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_advmode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_advmode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_advmode`]
module"]
    pub type DCDC_ADVMODE = crate::Reg<dcdc_advmode::DCDC_ADVMODE_SPEC>;
    #[doc = "DCDC advance setting"]
    pub mod dcdc_advmode {
        #[doc = "Register `DCDC_ADVMODE` reader"]
        pub type R = crate::R<DCDC_ADVMODE_SPEC>;
        #[doc = "Register `DCDC_ADVMODE` writer"]
        pub type W = crate::W<DCDC_ADVMODE_SPEC>;
        #[doc = "Field `EN_DCM` reader - DCM mode 0: CCM mode 1: DCM mode"]
        pub type EN_DCM_R = crate::BitReader;
        #[doc = "Field `EN_DCM` writer - DCM mode 0: CCM mode 1: DCM mode"]
        pub type EN_DCM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_IDLE` reader - enable skip when voltage is higher than threshold 0: do not skip 1: skip if voltage is excess"]
        pub type EN_IDLE_R = crate::BitReader;
        #[doc = "Field `EN_IDLE` writer - enable skip when voltage is higher than threshold 0: do not skip 1: skip if voltage is excess"]
        pub type EN_IDLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_SKIP` reader - enable skip on narrow pulse 0: do not skip narrow pulse 1: skip narrow pulse"]
        pub type EN_SKIP_R = crate::BitReader;
        #[doc = "Field `EN_SKIP` writer - enable skip on narrow pulse 0: do not skip narrow pulse 1: skip narrow pulse"]
        pub type EN_SKIP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_DCM_EXIT` reader - avoid over voltage 0: stay in DCM mode when voltage excess 1: change to CCM mode when voltage excess"]
        pub type EN_DCM_EXIT_R = crate::BitReader;
        #[doc = "Field `EN_DCM_EXIT` writer - avoid over voltage 0: stay in DCM mode when voltage excess 1: change to CCM mode when voltage excess"]
        pub type EN_DCM_EXIT_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_AUTOLP` reader - enable auto enter low power mode 0: do not enter low power mode 1: enter low power mode if current is detected low"]
        pub type EN_AUTOLP_R = crate::BitReader;
        #[doc = "Field `EN_AUTOLP` writer - enable auto enter low power mode 0: do not enter low power mode 1: enter low power mode if current is detected low"]
        pub type EN_AUTOLP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_FF_LOOP` reader - enable feed forward loop 0: feed forward loop is disabled 1: feed forward loop is enabled"]
        pub type EN_FF_LOOP_R = crate::BitReader;
        #[doc = "Field `EN_FF_LOOP` writer - enable feed forward loop 0: feed forward loop is disabled 1: feed forward loop is enabled"]
        pub type EN_FF_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_FF_DET` reader - enable feed forward detect 0: feed forward detect is disabled 1: feed forward detect is enabled"]
        pub type EN_FF_DET_R = crate::BitReader;
        #[doc = "Field `EN_FF_DET` writer - enable feed forward detect 0: feed forward detect is disabled 1: feed forward detect is enabled"]
        pub type EN_FF_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DC_R` reader - Loop R number"]
        pub type DC_R_R = crate::FieldReader;
        #[doc = "Field `DC_R` writer - Loop R number"]
        pub type DC_R_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
        #[doc = "Field `DC_C` reader - Loop C number"]
        pub type DC_C_R = crate::FieldReader;
        #[doc = "Field `DC_C` writer - Loop C number"]
        pub type DC_C_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `EN_RCSCALE` reader - Enable RC scale"]
        pub type EN_RCSCALE_R = crate::FieldReader;
        #[doc = "Field `EN_RCSCALE` writer - Enable RC scale"]
        pub type EN_RCSCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        impl R {
            #[doc = "Bit 0 - DCM mode 0: CCM mode 1: DCM mode"]
            #[inline(always)]
            pub fn en_dcm(&self) -> EN_DCM_R {
                EN_DCM_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - enable skip when voltage is higher than threshold 0: do not skip 1: skip if voltage is excess"]
            #[inline(always)]
            pub fn en_idle(&self) -> EN_IDLE_R {
                EN_IDLE_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - enable skip on narrow pulse 0: do not skip narrow pulse 1: skip narrow pulse"]
            #[inline(always)]
            pub fn en_skip(&self) -> EN_SKIP_R {
                EN_SKIP_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 3 - avoid over voltage 0: stay in DCM mode when voltage excess 1: change to CCM mode when voltage excess"]
            #[inline(always)]
            pub fn en_dcm_exit(&self) -> EN_DCM_EXIT_R {
                EN_DCM_EXIT_R::new(((self.bits >> 3) & 1) != 0)
            }
            #[doc = "Bit 4 - enable auto enter low power mode 0: do not enter low power mode 1: enter low power mode if current is detected low"]
            #[inline(always)]
            pub fn en_autolp(&self) -> EN_AUTOLP_R {
                EN_AUTOLP_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 5 - enable feed forward loop 0: feed forward loop is disabled 1: feed forward loop is enabled"]
            #[inline(always)]
            pub fn en_ff_loop(&self) -> EN_FF_LOOP_R {
                EN_FF_LOOP_R::new(((self.bits >> 5) & 1) != 0)
            }
            #[doc = "Bit 6 - enable feed forward detect 0: feed forward detect is disabled 1: feed forward detect is enabled"]
            #[inline(always)]
            pub fn en_ff_det(&self) -> EN_FF_DET_R {
                EN_FF_DET_R::new(((self.bits >> 6) & 1) != 0)
            }
            #[doc = "Bits 16:19 - Loop R number"]
            #[inline(always)]
            pub fn dc_r(&self) -> DC_R_R {
                DC_R_R::new(((self.bits >> 16) & 0x0f) as u8)
            }
            #[doc = "Bits 20:21 - Loop C number"]
            #[inline(always)]
            pub fn dc_c(&self) -> DC_C_R {
                DC_C_R::new(((self.bits >> 20) & 3) as u8)
            }
            #[doc = "Bits 24:26 - Enable RC scale"]
            #[inline(always)]
            pub fn en_rcscale(&self) -> EN_RCSCALE_R {
                EN_RCSCALE_R::new(((self.bits >> 24) & 7) as u8)
            }
        }
        impl W {
            #[doc = "Bit 0 - DCM mode 0: CCM mode 1: DCM mode"]
            #[inline(always)]
            #[must_use]
            pub fn en_dcm(&mut self) -> EN_DCM_W<DCDC_ADVMODE_SPEC> {
                EN_DCM_W::new(self, 0)
            }
            #[doc = "Bit 1 - enable skip when voltage is higher than threshold 0: do not skip 1: skip if voltage is excess"]
            #[inline(always)]
            #[must_use]
            pub fn en_idle(&mut self) -> EN_IDLE_W<DCDC_ADVMODE_SPEC> {
                EN_IDLE_W::new(self, 1)
            }
            #[doc = "Bit 2 - enable skip on narrow pulse 0: do not skip narrow pulse 1: skip narrow pulse"]
            #[inline(always)]
            #[must_use]
            pub fn en_skip(&mut self) -> EN_SKIP_W<DCDC_ADVMODE_SPEC> {
                EN_SKIP_W::new(self, 2)
            }
            #[doc = "Bit 3 - avoid over voltage 0: stay in DCM mode when voltage excess 1: change to CCM mode when voltage excess"]
            #[inline(always)]
            #[must_use]
            pub fn en_dcm_exit(&mut self) -> EN_DCM_EXIT_W<DCDC_ADVMODE_SPEC> {
                EN_DCM_EXIT_W::new(self, 3)
            }
            #[doc = "Bit 4 - enable auto enter low power mode 0: do not enter low power mode 1: enter low power mode if current is detected low"]
            #[inline(always)]
            #[must_use]
            pub fn en_autolp(&mut self) -> EN_AUTOLP_W<DCDC_ADVMODE_SPEC> {
                EN_AUTOLP_W::new(self, 4)
            }
            #[doc = "Bit 5 - enable feed forward loop 0: feed forward loop is disabled 1: feed forward loop is enabled"]
            #[inline(always)]
            #[must_use]
            pub fn en_ff_loop(&mut self) -> EN_FF_LOOP_W<DCDC_ADVMODE_SPEC> {
                EN_FF_LOOP_W::new(self, 5)
            }
            #[doc = "Bit 6 - enable feed forward detect 0: feed forward detect is disabled 1: feed forward detect is enabled"]
            #[inline(always)]
            #[must_use]
            pub fn en_ff_det(&mut self) -> EN_FF_DET_W<DCDC_ADVMODE_SPEC> {
                EN_FF_DET_W::new(self, 6)
            }
            #[doc = "Bits 16:19 - Loop R number"]
            #[inline(always)]
            #[must_use]
            pub fn dc_r(&mut self) -> DC_R_W<DCDC_ADVMODE_SPEC> {
                DC_R_W::new(self, 16)
            }
            #[doc = "Bits 20:21 - Loop C number"]
            #[inline(always)]
            #[must_use]
            pub fn dc_c(&mut self) -> DC_C_W<DCDC_ADVMODE_SPEC> {
                DC_C_W::new(self, 20)
            }
            #[doc = "Bits 24:26 - Enable RC scale"]
            #[inline(always)]
            #[must_use]
            pub fn en_rcscale(&mut self) -> EN_RCSCALE_W<DCDC_ADVMODE_SPEC> {
                EN_RCSCALE_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC advance setting\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_advmode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_advmode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_ADVMODE_SPEC;
        impl crate::RegisterSpec for DCDC_ADVMODE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_advmode::R`](R) reader structure"]
        impl crate::Readable for DCDC_ADVMODE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_advmode::W`](W) writer structure"]
        impl crate::Writable for DCDC_ADVMODE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_ADVMODE to value 0x0312_0040"]
        impl crate::Resettable for DCDC_ADVMODE_SPEC {
            const RESET_VALUE: u32 = 0x0312_0040;
        }
    }
    #[doc = "DCDC_ADVPARAM (rw) register accessor: DCDC advance parameter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_advparam::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_advparam::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_advparam`]
module"]
    pub type DCDC_ADVPARAM = crate::Reg<dcdc_advparam::DCDC_ADVPARAM_SPEC>;
    #[doc = "DCDC advance parameter"]
    pub mod dcdc_advparam {
        #[doc = "Register `DCDC_ADVPARAM` reader"]
        pub type R = crate::R<DCDC_ADVPARAM_SPEC>;
        #[doc = "Register `DCDC_ADVPARAM` writer"]
        pub type W = crate::W<DCDC_ADVPARAM_SPEC>;
        #[doc = "Field `MAX_DUT` reader - maximum duty cycle"]
        pub type MAX_DUT_R = crate::FieldReader;
        #[doc = "Field `MAX_DUT` writer - maximum duty cycle"]
        pub type MAX_DUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        #[doc = "Field `MIN_DUT` reader - minimum duty cycle"]
        pub type MIN_DUT_R = crate::FieldReader;
        #[doc = "Field `MIN_DUT` writer - minimum duty cycle"]
        pub type MIN_DUT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
        impl R {
            #[doc = "Bits 0:6 - maximum duty cycle"]
            #[inline(always)]
            pub fn max_dut(&self) -> MAX_DUT_R {
                MAX_DUT_R::new((self.bits & 0x7f) as u8)
            }
            #[doc = "Bits 8:14 - minimum duty cycle"]
            #[inline(always)]
            pub fn min_dut(&self) -> MIN_DUT_R {
                MIN_DUT_R::new(((self.bits >> 8) & 0x7f) as u8)
            }
        }
        impl W {
            #[doc = "Bits 0:6 - maximum duty cycle"]
            #[inline(always)]
            #[must_use]
            pub fn max_dut(&mut self) -> MAX_DUT_W<DCDC_ADVPARAM_SPEC> {
                MAX_DUT_W::new(self, 0)
            }
            #[doc = "Bits 8:14 - minimum duty cycle"]
            #[inline(always)]
            #[must_use]
            pub fn min_dut(&mut self) -> MIN_DUT_W<DCDC_ADVPARAM_SPEC> {
                MIN_DUT_W::new(self, 8)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC advance parameter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_advparam::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_advparam::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_ADVPARAM_SPEC;
        impl crate::RegisterSpec for DCDC_ADVPARAM_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_advparam::R`](R) reader structure"]
        impl crate::Readable for DCDC_ADVPARAM_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_advparam::W`](W) writer structure"]
        impl crate::Writable for DCDC_ADVPARAM_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_ADVPARAM to value 0x6e1c"]
        impl crate::Resettable for DCDC_ADVPARAM_SPEC {
            const RESET_VALUE: u32 = 0x6e1c;
        }
    }
    #[doc = "DCDC_MISC (rw) register accessor: DCDC misc parameter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_misc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_misc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_misc`]
module"]
    pub type DCDC_MISC = crate::Reg<dcdc_misc::DCDC_MISC_SPEC>;
    #[doc = "DCDC misc parameter"]
    pub mod dcdc_misc {
        #[doc = "Register `DCDC_MISC` reader"]
        pub type R = crate::R<DCDC_MISC_SPEC>;
        #[doc = "Register `DCDC_MISC` writer"]
        pub type W = crate::W<DCDC_MISC_SPEC>;
        #[doc = "Field `EN_STEP` reader - enable stepping in voltage change 0: stepping disabled, 1: steping enabled"]
        pub type EN_STEP_R = crate::BitReader;
        #[doc = "Field `EN_STEP` writer - enable stepping in voltage change 0: stepping disabled, 1: steping enabled"]
        pub type EN_STEP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CLK_SEL` reader - clock selection 0: select DCDC internal oscillator 1: select RC24M oscillator"]
        pub type CLK_SEL_R = crate::BitReader;
        #[doc = "Field `CLK_SEL` writer - clock selection 0: select DCDC internal oscillator 1: select RC24M oscillator"]
        pub type CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `DELAY` reader - enable delay 0: delay disabled, 1: delay enabled"]
        pub type DELAY_R = crate::BitReader;
        #[doc = "Field `DELAY` writer - enable delay 0: delay disabled, 1: delay enabled"]
        pub type DELAY_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OL_HYST` reader - current hysteres range 0: 12.5mV 1: 25mV"]
        pub type OL_HYST_R = crate::BitReader;
        #[doc = "Field `OL_HYST` writer - current hysteres range 0: 12.5mV 1: 25mV"]
        pub type OL_HYST_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `OL_THRE` reader - overload for threshold for lod power mode"]
        pub type OL_THRE_R = crate::FieldReader;
        #[doc = "Field `OL_THRE` writer - overload for threshold for lod power mode"]
        pub type OL_THRE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
        #[doc = "Field `DC_FF` reader - Loop feed forward number"]
        pub type DC_FF_R = crate::FieldReader;
        #[doc = "Field `DC_FF` writer - Loop feed forward number"]
        pub type DC_FF_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `RC_SCALE` reader - Loop RC scale threshold"]
        pub type RC_SCALE_R = crate::BitReader;
        #[doc = "Field `RC_SCALE` writer - Loop RC scale threshold"]
        pub type RC_SCALE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HYST_THRS` reader - hysteres threshold"]
        pub type HYST_THRS_R = crate::BitReader;
        #[doc = "Field `HYST_THRS` writer - hysteres threshold"]
        pub type HYST_THRS_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `HYST_SIGN` reader - hysteres sign"]
        pub type HYST_SIGN_R = crate::BitReader;
        #[doc = "Field `HYST_SIGN` writer - hysteres sign"]
        pub type HYST_SIGN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `EN_HYST` reader - hysteres enable"]
        pub type EN_HYST_R = crate::BitReader;
        #[doc = "Field `EN_HYST` writer - hysteres enable"]
        pub type EN_HYST_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - enable stepping in voltage change 0: stepping disabled, 1: steping enabled"]
            #[inline(always)]
            pub fn en_step(&self) -> EN_STEP_R {
                EN_STEP_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - clock selection 0: select DCDC internal oscillator 1: select RC24M oscillator"]
            #[inline(always)]
            pub fn clk_sel(&self) -> CLK_SEL_R {
                CLK_SEL_R::new(((self.bits >> 1) & 1) != 0)
            }
            #[doc = "Bit 2 - enable delay 0: delay disabled, 1: delay enabled"]
            #[inline(always)]
            pub fn delay(&self) -> DELAY_R {
                DELAY_R::new(((self.bits >> 2) & 1) != 0)
            }
            #[doc = "Bit 4 - current hysteres range 0: 12.5mV 1: 25mV"]
            #[inline(always)]
            pub fn ol_hyst(&self) -> OL_HYST_R {
                OL_HYST_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bits 8:9 - overload for threshold for lod power mode"]
            #[inline(always)]
            pub fn ol_thre(&self) -> OL_THRE_R {
                OL_THRE_R::new(((self.bits >> 8) & 3) as u8)
            }
            #[doc = "Bits 16:18 - Loop feed forward number"]
            #[inline(always)]
            pub fn dc_ff(&self) -> DC_FF_R {
                DC_FF_R::new(((self.bits >> 16) & 7) as u8)
            }
            #[doc = "Bit 20 - Loop RC scale threshold"]
            #[inline(always)]
            pub fn rc_scale(&self) -> RC_SCALE_R {
                RC_SCALE_R::new(((self.bits >> 20) & 1) != 0)
            }
            #[doc = "Bit 24 - hysteres threshold"]
            #[inline(always)]
            pub fn hyst_thrs(&self) -> HYST_THRS_R {
                HYST_THRS_R::new(((self.bits >> 24) & 1) != 0)
            }
            #[doc = "Bit 25 - hysteres sign"]
            #[inline(always)]
            pub fn hyst_sign(&self) -> HYST_SIGN_R {
                HYST_SIGN_R::new(((self.bits >> 25) & 1) != 0)
            }
            #[doc = "Bit 28 - hysteres enable"]
            #[inline(always)]
            pub fn en_hyst(&self) -> EN_HYST_R {
                EN_HYST_R::new(((self.bits >> 28) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - enable stepping in voltage change 0: stepping disabled, 1: steping enabled"]
            #[inline(always)]
            #[must_use]
            pub fn en_step(&mut self) -> EN_STEP_W<DCDC_MISC_SPEC> {
                EN_STEP_W::new(self, 0)
            }
            #[doc = "Bit 1 - clock selection 0: select DCDC internal oscillator 1: select RC24M oscillator"]
            #[inline(always)]
            #[must_use]
            pub fn clk_sel(&mut self) -> CLK_SEL_W<DCDC_MISC_SPEC> {
                CLK_SEL_W::new(self, 1)
            }
            #[doc = "Bit 2 - enable delay 0: delay disabled, 1: delay enabled"]
            #[inline(always)]
            #[must_use]
            pub fn delay(&mut self) -> DELAY_W<DCDC_MISC_SPEC> {
                DELAY_W::new(self, 2)
            }
            #[doc = "Bit 4 - current hysteres range 0: 12.5mV 1: 25mV"]
            #[inline(always)]
            #[must_use]
            pub fn ol_hyst(&mut self) -> OL_HYST_W<DCDC_MISC_SPEC> {
                OL_HYST_W::new(self, 4)
            }
            #[doc = "Bits 8:9 - overload for threshold for lod power mode"]
            #[inline(always)]
            #[must_use]
            pub fn ol_thre(&mut self) -> OL_THRE_W<DCDC_MISC_SPEC> {
                OL_THRE_W::new(self, 8)
            }
            #[doc = "Bits 16:18 - Loop feed forward number"]
            #[inline(always)]
            #[must_use]
            pub fn dc_ff(&mut self) -> DC_FF_W<DCDC_MISC_SPEC> {
                DC_FF_W::new(self, 16)
            }
            #[doc = "Bit 20 - Loop RC scale threshold"]
            #[inline(always)]
            #[must_use]
            pub fn rc_scale(&mut self) -> RC_SCALE_W<DCDC_MISC_SPEC> {
                RC_SCALE_W::new(self, 20)
            }
            #[doc = "Bit 24 - hysteres threshold"]
            #[inline(always)]
            #[must_use]
            pub fn hyst_thrs(&mut self) -> HYST_THRS_W<DCDC_MISC_SPEC> {
                HYST_THRS_W::new(self, 24)
            }
            #[doc = "Bit 25 - hysteres sign"]
            #[inline(always)]
            #[must_use]
            pub fn hyst_sign(&mut self) -> HYST_SIGN_W<DCDC_MISC_SPEC> {
                HYST_SIGN_W::new(self, 25)
            }
            #[doc = "Bit 28 - hysteres enable"]
            #[inline(always)]
            #[must_use]
            pub fn en_hyst(&mut self) -> EN_HYST_W<DCDC_MISC_SPEC> {
                EN_HYST_W::new(self, 28)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC misc parameter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_misc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_misc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_MISC_SPEC;
        impl crate::RegisterSpec for DCDC_MISC_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_misc::R`](R) reader structure"]
        impl crate::Readable for DCDC_MISC_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_misc::W`](W) writer structure"]
        impl crate::Writable for DCDC_MISC_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_MISC to value 0x0007_0100"]
        impl crate::Resettable for DCDC_MISC_SPEC {
            const RESET_VALUE: u32 = 0x0007_0100;
        }
    }
    #[doc = "DCDC_DEBUG (rw) register accessor: DCDC Debug\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_debug::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_debug::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_debug`]
module"]
    pub type DCDC_DEBUG = crate::Reg<dcdc_debug::DCDC_DEBUG_SPEC>;
    #[doc = "DCDC Debug"]
    pub mod dcdc_debug {
        #[doc = "Register `DCDC_DEBUG` reader"]
        pub type R = crate::R<DCDC_DEBUG_SPEC>;
        #[doc = "Register `DCDC_DEBUG` writer"]
        pub type W = crate::W<DCDC_DEBUG_SPEC>;
        #[doc = "Field `UPDATE_TIME` reader - DCDC voltage change time in 24M clock cycles, default value is 1mS"]
        pub type UPDATE_TIME_R = crate::FieldReader<u32>;
        #[doc = "Field `UPDATE_TIME` writer - DCDC voltage change time in 24M clock cycles, default value is 1mS"]
        pub type UPDATE_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        impl R {
            #[doc = "Bits 0:19 - DCDC voltage change time in 24M clock cycles, default value is 1mS"]
            #[inline(always)]
            pub fn update_time(&self) -> UPDATE_TIME_R {
                UPDATE_TIME_R::new(self.bits & 0x000f_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - DCDC voltage change time in 24M clock cycles, default value is 1mS"]
            #[inline(always)]
            #[must_use]
            pub fn update_time(&mut self) -> UPDATE_TIME_W<DCDC_DEBUG_SPEC> {
                UPDATE_TIME_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC Debug\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_debug::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_debug::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_DEBUG_SPEC;
        impl crate::RegisterSpec for DCDC_DEBUG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_debug::R`](R) reader structure"]
        impl crate::Readable for DCDC_DEBUG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_debug::W`](W) writer structure"]
        impl crate::Writable for DCDC_DEBUG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_DEBUG to value 0x5dbf"]
        impl crate::Resettable for DCDC_DEBUG_SPEC {
            const RESET_VALUE: u32 = 0x5dbf;
        }
    }
    #[doc = "DCDC_START_TIME (rw) register accessor: DCDC ramp time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_start_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_start_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_start_time`]
module"]
    pub type DCDC_START_TIME = crate::Reg<dcdc_start_time::DCDC_START_TIME_SPEC>;
    #[doc = "DCDC ramp time"]
    pub mod dcdc_start_time {
        #[doc = "Register `DCDC_START_TIME` reader"]
        pub type R = crate::R<DCDC_START_TIME_SPEC>;
        #[doc = "Register `DCDC_START_TIME` writer"]
        pub type W = crate::W<DCDC_START_TIME_SPEC>;
        #[doc = "Field `START_TIME` reader - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS"]
        pub type START_TIME_R = crate::FieldReader<u32>;
        #[doc = "Field `START_TIME` writer - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS"]
        pub type START_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        impl R {
            #[doc = "Bits 0:19 - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS"]
            #[inline(always)]
            pub fn start_time(&self) -> START_TIME_R {
                START_TIME_R::new(self.bits & 0x000f_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS"]
            #[inline(always)]
            #[must_use]
            pub fn start_time(&mut self) -> START_TIME_W<DCDC_START_TIME_SPEC> {
                START_TIME_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC ramp time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_start_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_start_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_START_TIME_SPEC;
        impl crate::RegisterSpec for DCDC_START_TIME_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_start_time::R`](R) reader structure"]
        impl crate::Readable for DCDC_START_TIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_start_time::W`](W) writer structure"]
        impl crate::Writable for DCDC_START_TIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_START_TIME to value 0x0001_193f"]
        impl crate::Resettable for DCDC_START_TIME_SPEC {
            const RESET_VALUE: u32 = 0x0001_193f;
        }
    }
    #[doc = "DCDC_RESUME_TIME (rw) register accessor: DCDC resume time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_resume_time::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_resume_time::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dcdc_resume_time`]
module"]
    pub type DCDC_RESUME_TIME = crate::Reg<dcdc_resume_time::DCDC_RESUME_TIME_SPEC>;
    #[doc = "DCDC resume time"]
    pub mod dcdc_resume_time {
        #[doc = "Register `DCDC_RESUME_TIME` reader"]
        pub type R = crate::R<DCDC_RESUME_TIME_SPEC>;
        #[doc = "Register `DCDC_RESUME_TIME` writer"]
        pub type W = crate::W<DCDC_RESUME_TIME_SPEC>;
        #[doc = "Field `RESUME_TIME` reader - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS"]
        pub type RESUME_TIME_R = crate::FieldReader<u32>;
        #[doc = "Field `RESUME_TIME` writer - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS"]
        pub type RESUME_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
        impl R {
            #[doc = "Bits 0:19 - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS"]
            #[inline(always)]
            pub fn resume_time(&self) -> RESUME_TIME_R {
                RESUME_TIME_R::new(self.bits & 0x000f_ffff)
            }
        }
        impl W {
            #[doc = "Bits 0:19 - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS"]
            #[inline(always)]
            #[must_use]
            pub fn resume_time(&mut self) -> RESUME_TIME_W<DCDC_RESUME_TIME_SPEC> {
                RESUME_TIME_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "DCDC resume time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_resume_time::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_resume_time::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DCDC_RESUME_TIME_SPEC;
        impl crate::RegisterSpec for DCDC_RESUME_TIME_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dcdc_resume_time::R`](R) reader structure"]
        impl crate::Readable for DCDC_RESUME_TIME_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dcdc_resume_time::W`](W) writer structure"]
        impl crate::Writable for DCDC_RESUME_TIME_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DCDC_RESUME_TIME to value 0x8c9f"]
        impl crate::Resettable for DCDC_RESUME_TIME_SPEC {
            const RESET_VALUE: u32 = 0x8c9f;
        }
    }
    #[doc = "POWER_TRAP (rw) register accessor: SOC power trap\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_trap::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_trap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@power_trap`]
module"]
    pub type POWER_TRAP = crate::Reg<power_trap::POWER_TRAP_SPEC>;
    #[doc = "SOC power trap"]
    pub mod power_trap {
        #[doc = "Register `POWER_TRAP` reader"]
        pub type R = crate::R<POWER_TRAP_SPEC>;
        #[doc = "Register `POWER_TRAP` writer"]
        pub type W = crate::W<POWER_TRAP_SPEC>;
        #[doc = "Field `TRAP` reader - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered 0: trap not enabled, pmic side low power function disabled 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned."]
        pub type TRAP_R = crate::BitReader;
        #[doc = "Field `TRAP` writer - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered 0: trap not enabled, pmic side low power function disabled 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned."]
        pub type TRAP_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RETENTION` reader - DCDC enter standby mode, which will reduce voltage for memory content retention 0: Shutdown DCDC 1: reduce DCDC voltage"]
        pub type RETENTION_R = crate::BitReader;
        #[doc = "Field `RETENTION` writer - DCDC enter standby mode, which will reduce voltage for memory content retention 0: Shutdown DCDC 1: reduce DCDC voltage"]
        pub type RETENTION_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `TRIGGERED` reader - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. 0: low power trap is not triggered 1: low power trap triggered"]
        pub type TRIGGERED_R = crate::BitReader;
        #[doc = "Field `TRIGGERED` writer - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. 0: low power trap is not triggered 1: low power trap triggered"]
        pub type TRIGGERED_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered 0: trap not enabled, pmic side low power function disabled 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned."]
            #[inline(always)]
            pub fn trap(&self) -> TRAP_R {
                TRAP_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 16 - DCDC enter standby mode, which will reduce voltage for memory content retention 0: Shutdown DCDC 1: reduce DCDC voltage"]
            #[inline(always)]
            pub fn retention(&self) -> RETENTION_R {
                RETENTION_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 31 - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. 0: low power trap is not triggered 1: low power trap triggered"]
            #[inline(always)]
            pub fn triggered(&self) -> TRIGGERED_R {
                TRIGGERED_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered 0: trap not enabled, pmic side low power function disabled 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned."]
            #[inline(always)]
            #[must_use]
            pub fn trap(&mut self) -> TRAP_W<POWER_TRAP_SPEC> {
                TRAP_W::new(self, 0)
            }
            #[doc = "Bit 16 - DCDC enter standby mode, which will reduce voltage for memory content retention 0: Shutdown DCDC 1: reduce DCDC voltage"]
            #[inline(always)]
            #[must_use]
            pub fn retention(&mut self) -> RETENTION_W<POWER_TRAP_SPEC> {
                RETENTION_W::new(self, 16)
            }
            #[doc = "Bit 31 - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. 0: low power trap is not triggered 1: low power trap triggered"]
            #[inline(always)]
            #[must_use]
            pub fn triggered(&mut self) -> TRIGGERED_W<POWER_TRAP_SPEC> {
                TRIGGERED_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "SOC power trap\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`power_trap::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`power_trap::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct POWER_TRAP_SPEC;
        impl crate::RegisterSpec for POWER_TRAP_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`power_trap::R`](R) reader structure"]
        impl crate::Readable for POWER_TRAP_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`power_trap::W`](W) writer structure"]
        impl crate::Writable for POWER_TRAP_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets POWER_TRAP to value 0"]
        impl crate::Resettable for POWER_TRAP_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "WAKE_CAUSE (rw) register accessor: Wake up source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wake_cause::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_cause::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wake_cause`]
module"]
    pub type WAKE_CAUSE = crate::Reg<wake_cause::WAKE_CAUSE_SPEC>;
    #[doc = "Wake up source"]
    pub mod wake_cause {
        #[doc = "Register `WAKE_CAUSE` reader"]
        pub type R = crate::R<WAKE_CAUSE_SPEC>;
        #[doc = "Register `WAKE_CAUSE` writer"]
        pub type W = crate::W<WAKE_CAUSE_SPEC>;
        #[doc = "Field `CAUSE` reader - wake up cause, each bit represents one wake up source, write 1 to clear the register bit 0: wake up source is not active during last wakeup 1: wake up source is active furing last wakeup bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
        pub type CAUSE_R = crate::FieldReader<u32>;
        #[doc = "Field `CAUSE` writer - wake up cause, each bit represents one wake up source, write 1 to clear the register bit 0: wake up source is not active during last wakeup 1: wake up source is active furing last wakeup bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
        pub type CAUSE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - wake up cause, each bit represents one wake up source, write 1 to clear the register bit 0: wake up source is not active during last wakeup 1: wake up source is active furing last wakeup bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
            #[inline(always)]
            pub fn cause(&self) -> CAUSE_R {
                CAUSE_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - wake up cause, each bit represents one wake up source, write 1 to clear the register bit 0: wake up source is not active during last wakeup 1: wake up source is active furing last wakeup bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
            #[inline(always)]
            #[must_use]
            pub fn cause(&mut self) -> CAUSE_W<WAKE_CAUSE_SPEC> {
                CAUSE_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Wake up source\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wake_cause::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_cause::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WAKE_CAUSE_SPEC;
        impl crate::RegisterSpec for WAKE_CAUSE_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wake_cause::R`](R) reader structure"]
        impl crate::Readable for WAKE_CAUSE_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wake_cause::W`](W) writer structure"]
        impl crate::Writable for WAKE_CAUSE_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets WAKE_CAUSE to value 0"]
        impl crate::Resettable for WAKE_CAUSE_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "WAKE_MASK (rw) register accessor: Wake up mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wake_mask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wake_mask`]
module"]
    pub type WAKE_MASK = crate::Reg<wake_mask::WAKE_MASK_SPEC>;
    #[doc = "Wake up mask"]
    pub mod wake_mask {
        #[doc = "Register `WAKE_MASK` reader"]
        pub type R = crate::R<WAKE_MASK_SPEC>;
        #[doc = "Register `WAKE_MASK` writer"]
        pub type W = crate::W<WAKE_MASK_SPEC>;
        #[doc = "Field `MASK` reader - mask for wake up sources, each bit represents one wakeup source 0: allow source to wake up system 1: disallow source to wakeup system bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
        pub type MASK_R = crate::FieldReader<u32>;
        #[doc = "Field `MASK` writer - mask for wake up sources, each bit represents one wakeup source 0: allow source to wake up system 1: disallow source to wakeup system bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
        pub type MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - mask for wake up sources, each bit represents one wakeup source 0: allow source to wake up system 1: disallow source to wakeup system bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
            #[inline(always)]
            pub fn mask(&self) -> MASK_R {
                MASK_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - mask for wake up sources, each bit represents one wakeup source 0: allow source to wake up system 1: disallow source to wakeup system bit 0: pmic_enable bit 7: UART interrupt bit 8: TMR interrupt bit 9: WDG interrupt bit10: GPIO in PMIC interrupt bit31: pin wakeup"]
            #[inline(always)]
            #[must_use]
            pub fn mask(&mut self) -> MASK_W<WAKE_MASK_SPEC> {
                MASK_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Wake up mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wake_mask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wake_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct WAKE_MASK_SPEC;
        impl crate::RegisterSpec for WAKE_MASK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`wake_mask::R`](R) reader structure"]
        impl crate::Readable for WAKE_MASK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`wake_mask::W`](W) writer structure"]
        impl crate::Writable for WAKE_MASK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets WAKE_MASK to value 0"]
        impl crate::Resettable for WAKE_MASK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "SCG_CTRL (rw) register accessor: Clock gate control in PMIC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scg_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scg_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scg_ctrl`]
module"]
    pub type SCG_CTRL = crate::Reg<scg_ctrl::SCG_CTRL_SPEC>;
    #[doc = "Clock gate control in PMIC"]
    pub mod scg_ctrl {
        #[doc = "Register `SCG_CTRL` reader"]
        pub type R = crate::R<SCG_CTRL_SPEC>;
        #[doc = "Register `SCG_CTRL` writer"]
        pub type W = crate::W<SCG_CTRL_SPEC>;
        #[doc = "Field `SCG` reader - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral 00,01: reserved 10: clock is always off 11: clock is always on bit6-7:gpio bit8-9:ioc bit10-11: timer bit12-13:wdog bit14-15:uart"]
        pub type SCG_R = crate::FieldReader<u32>;
        #[doc = "Field `SCG` writer - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral 00,01: reserved 10: clock is always off 11: clock is always on bit6-7:gpio bit8-9:ioc bit10-11: timer bit12-13:wdog bit14-15:uart"]
        pub type SCG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral 00,01: reserved 10: clock is always off 11: clock is always on bit6-7:gpio bit8-9:ioc bit10-11: timer bit12-13:wdog bit14-15:uart"]
            #[inline(always)]
            pub fn scg(&self) -> SCG_R {
                SCG_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral 00,01: reserved 10: clock is always off 11: clock is always on bit6-7:gpio bit8-9:ioc bit10-11: timer bit12-13:wdog bit14-15:uart"]
            #[inline(always)]
            #[must_use]
            pub fn scg(&mut self) -> SCG_W<SCG_CTRL_SPEC> {
                SCG_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Clock gate control in PMIC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scg_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scg_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct SCG_CTRL_SPEC;
        impl crate::RegisterSpec for SCG_CTRL_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`scg_ctrl::R`](R) reader structure"]
        impl crate::Readable for SCG_CTRL_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`scg_ctrl::W`](W) writer structure"]
        impl crate::Writable for SCG_CTRL_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets SCG_CTRL to value 0xffff_ffff"]
        impl crate::Resettable for SCG_CTRL_SPEC {
            const RESET_VALUE: u32 = 0xffff_ffff;
        }
    }
    #[doc = "RC24M (rw) register accessor: RC 24M config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc24m::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc24m::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rc24m`]
module"]
    pub type RC24M = crate::Reg<rc24m::RC24M_SPEC>;
    #[doc = "RC 24M config"]
    pub mod rc24m {
        #[doc = "Register `RC24M` reader"]
        pub type R = crate::R<RC24M_SPEC>;
        #[doc = "Register `RC24M` writer"]
        pub type W = crate::W<RC24M_SPEC>;
        #[doc = "Field `TRIM_F` reader - Fine trim for RC24M, bigger value means faster"]
        pub type TRIM_F_R = crate::FieldReader;
        #[doc = "Field `TRIM_F` writer - Fine trim for RC24M, bigger value means faster"]
        pub type TRIM_F_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
        #[doc = "Field `TRIM_C` reader - Coarse trim for RC24M, bigger value means faster"]
        pub type TRIM_C_R = crate::FieldReader;
        #[doc = "Field `TRIM_C` writer - Coarse trim for RC24M, bigger value means faster"]
        pub type TRIM_C_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
        #[doc = "Field `RC_TRIMMED` reader - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: RC is not trimmed 1: RC is trimmed"]
        pub type RC_TRIMMED_R = crate::BitReader;
        #[doc = "Field `RC_TRIMMED` writer - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: RC is not trimmed 1: RC is trimmed"]
        pub type RC_TRIMMED_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:4 - Fine trim for RC24M, bigger value means faster"]
            #[inline(always)]
            pub fn trim_f(&self) -> TRIM_F_R {
                TRIM_F_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bits 8:10 - Coarse trim for RC24M, bigger value means faster"]
            #[inline(always)]
            pub fn trim_c(&self) -> TRIM_C_R {
                TRIM_C_R::new(((self.bits >> 8) & 7) as u8)
            }
            #[doc = "Bit 31 - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: RC is not trimmed 1: RC is trimmed"]
            #[inline(always)]
            pub fn rc_trimmed(&self) -> RC_TRIMMED_R {
                RC_TRIMMED_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:4 - Fine trim for RC24M, bigger value means faster"]
            #[inline(always)]
            #[must_use]
            pub fn trim_f(&mut self) -> TRIM_F_W<RC24M_SPEC> {
                TRIM_F_W::new(self, 0)
            }
            #[doc = "Bits 8:10 - Coarse trim for RC24M, bigger value means faster"]
            #[inline(always)]
            #[must_use]
            pub fn trim_c(&mut self) -> TRIM_C_W<RC24M_SPEC> {
                TRIM_C_W::new(self, 8)
            }
            #[doc = "Bit 31 - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: RC is not trimmed 1: RC is trimmed"]
            #[inline(always)]
            #[must_use]
            pub fn rc_trimmed(&mut self) -> RC_TRIMMED_W<RC24M_SPEC> {
                RC_TRIMMED_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "RC 24M config\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc24m::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc24m::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RC24M_SPEC;
        impl crate::RegisterSpec for RC24M_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rc24m::R`](R) reader structure"]
        impl crate::Readable for RC24M_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rc24m::W`](W) writer structure"]
        impl crate::Writable for RC24M_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RC24M to value 0x0310"]
        impl crate::Resettable for RC24M_SPEC {
            const RESET_VALUE: u32 = 0x0310;
        }
    }
    #[doc = "RC24M_TRACK (rw) register accessor: RC 24M track mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc24m_track::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc24m_track::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rc24m_track`]
module"]
    pub type RC24M_TRACK = crate::Reg<rc24m_track::RC24M_TRACK_SPEC>;
    #[doc = "RC 24M track mode"]
    pub mod rc24m_track {
        #[doc = "Register `RC24M_TRACK` reader"]
        pub type R = crate::R<RC24M_TRACK_SPEC>;
        #[doc = "Register `RC24M_TRACK` writer"]
        pub type W = crate::W<RC24M_TRACK_SPEC>;
        #[doc = "Field `TRACK` reader - track mode 0: RC24M free running 1: track RC24M to external XTAL"]
        pub type TRACK_R = crate::BitReader;
        #[doc = "Field `TRACK` writer - track mode 0: RC24M free running 1: track RC24M to external XTAL"]
        pub type TRACK_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RETURN` reader - Retrun default value when XTAL loss 0: remain last tracking value 1: switch to default value"]
        pub type RETURN_R = crate::BitReader;
        #[doc = "Field `RETURN` writer - Retrun default value when XTAL loss 0: remain last tracking value 1: switch to default value"]
        pub type RETURN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `SEL24M` reader - Select track reference 0: select 32K as reference 1: select 24M XTAL as reference"]
        pub type SEL24M_R = crate::BitReader;
        #[doc = "Field `SEL24M` writer - Select track reference 0: select 32K as reference 1: select 24M XTAL as reference"]
        pub type SEL24M_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - track mode 0: RC24M free running 1: track RC24M to external XTAL"]
            #[inline(always)]
            pub fn track(&self) -> TRACK_R {
                TRACK_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 4 - Retrun default value when XTAL loss 0: remain last tracking value 1: switch to default value"]
            #[inline(always)]
            pub fn return_(&self) -> RETURN_R {
                RETURN_R::new(((self.bits >> 4) & 1) != 0)
            }
            #[doc = "Bit 16 - Select track reference 0: select 32K as reference 1: select 24M XTAL as reference"]
            #[inline(always)]
            pub fn sel24m(&self) -> SEL24M_R {
                SEL24M_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - track mode 0: RC24M free running 1: track RC24M to external XTAL"]
            #[inline(always)]
            #[must_use]
            pub fn track(&mut self) -> TRACK_W<RC24M_TRACK_SPEC> {
                TRACK_W::new(self, 0)
            }
            #[doc = "Bit 4 - Retrun default value when XTAL loss 0: remain last tracking value 1: switch to default value"]
            #[inline(always)]
            #[must_use]
            pub fn return_(&mut self) -> RETURN_W<RC24M_TRACK_SPEC> {
                RETURN_W::new(self, 4)
            }
            #[doc = "Bit 16 - Select track reference 0: select 32K as reference 1: select 24M XTAL as reference"]
            #[inline(always)]
            #[must_use]
            pub fn sel24m(&mut self) -> SEL24M_W<RC24M_TRACK_SPEC> {
                SEL24M_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "RC 24M track mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rc24m_track::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rc24m_track::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct RC24M_TRACK_SPEC;
        impl crate::RegisterSpec for RC24M_TRACK_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`rc24m_track::R`](R) reader structure"]
        impl crate::Readable for RC24M_TRACK_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`rc24m_track::W`](W) writer structure"]
        impl crate::Writable for RC24M_TRACK_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets RC24M_TRACK to value 0"]
        impl crate::Resettable for RC24M_TRACK_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "TRACK_TARGET (rw) register accessor: RC 24M track target\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`track_target::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`track_target::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@track_target`]
module"]
    pub type TRACK_TARGET = crate::Reg<track_target::TRACK_TARGET_SPEC>;
    #[doc = "RC 24M track target"]
    pub mod track_target {
        #[doc = "Register `TRACK_TARGET` reader"]
        pub type R = crate::R<TRACK_TARGET_SPEC>;
        #[doc = "Register `TRACK_TARGET` writer"]
        pub type W = crate::W<TRACK_TARGET_SPEC>;
        #[doc = "Field `TARGET` reader - Target frequency multiplier of divided source"]
        pub type TARGET_R = crate::FieldReader<u16>;
        #[doc = "Field `TARGET` writer - Target frequency multiplier of divided source"]
        pub type TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        #[doc = "Field `PRE_DIV` reader - Divider for reference source"]
        pub type PRE_DIV_R = crate::FieldReader<u16>;
        #[doc = "Field `PRE_DIV` writer - Divider for reference source"]
        pub type PRE_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
        impl R {
            #[doc = "Bits 0:15 - Target frequency multiplier of divided source"]
            #[inline(always)]
            pub fn target(&self) -> TARGET_R {
                TARGET_R::new((self.bits & 0xffff) as u16)
            }
            #[doc = "Bits 16:31 - Divider for reference source"]
            #[inline(always)]
            pub fn pre_div(&self) -> PRE_DIV_R {
                PRE_DIV_R::new(((self.bits >> 16) & 0xffff) as u16)
            }
        }
        impl W {
            #[doc = "Bits 0:15 - Target frequency multiplier of divided source"]
            #[inline(always)]
            #[must_use]
            pub fn target(&mut self) -> TARGET_W<TRACK_TARGET_SPEC> {
                TARGET_W::new(self, 0)
            }
            #[doc = "Bits 16:31 - Divider for reference source"]
            #[inline(always)]
            #[must_use]
            pub fn pre_div(&mut self) -> PRE_DIV_W<TRACK_TARGET_SPEC> {
                PRE_DIV_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "RC 24M track target\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`track_target::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`track_target::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct TRACK_TARGET_SPEC;
        impl crate::RegisterSpec for TRACK_TARGET_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`track_target::R`](R) reader structure"]
        impl crate::Readable for TRACK_TARGET_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`track_target::W`](W) writer structure"]
        impl crate::Writable for TRACK_TARGET_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets TRACK_TARGET to value 0"]
        impl crate::Resettable for TRACK_TARGET_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "STATUS (rw) register accessor: RC 24M track status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
    pub type STATUS = crate::Reg<status::STATUS_SPEC>;
    #[doc = "RC 24M track status"]
    pub mod status {
        #[doc = "Register `STATUS` reader"]
        pub type R = crate::R<STATUS_SPEC>;
        #[doc = "Register `STATUS` writer"]
        pub type W = crate::W<STATUS_SPEC>;
        #[doc = "Field `TRIM_F` reader - default fine trim value"]
        pub type TRIM_F_R = crate::FieldReader;
        #[doc = "Field `TRIM_C` reader - default coarse trim value"]
        pub type TRIM_C_R = crate::FieldReader;
        #[doc = "Field `EN_TRIM` reader - default value takes effect 0: default value is invalid 1: default value is valid"]
        pub type EN_TRIM_R = crate::BitReader;
        #[doc = "Field `SEL24M` reader - track is using XTAL24M 0: track is not using XTAL24M 1: track is using XTAL24M"]
        pub type SEL24M_R = crate::BitReader;
        #[doc = "Field `SEL32K` reader - track is using XTAL32K 0: track is not using XTAL32K 1: track is using XTAL32K"]
        pub type SEL32K_R = crate::BitReader;
        impl R {
            #[doc = "Bits 0:4 - default fine trim value"]
            #[inline(always)]
            pub fn trim_f(&self) -> TRIM_F_R {
                TRIM_F_R::new((self.bits & 0x1f) as u8)
            }
            #[doc = "Bits 8:10 - default coarse trim value"]
            #[inline(always)]
            pub fn trim_c(&self) -> TRIM_C_R {
                TRIM_C_R::new(((self.bits >> 8) & 7) as u8)
            }
            #[doc = "Bit 15 - default value takes effect 0: default value is invalid 1: default value is valid"]
            #[inline(always)]
            pub fn en_trim(&self) -> EN_TRIM_R {
                EN_TRIM_R::new(((self.bits >> 15) & 1) != 0)
            }
            #[doc = "Bit 16 - track is using XTAL24M 0: track is not using XTAL24M 1: track is using XTAL24M"]
            #[inline(always)]
            pub fn sel24m(&self) -> SEL24M_R {
                SEL24M_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 20 - track is using XTAL32K 0: track is not using XTAL32K 1: track is using XTAL32K"]
            #[inline(always)]
            pub fn sel32k(&self) -> SEL32K_R {
                SEL32K_R::new(((self.bits >> 20) & 1) != 0)
            }
        }
        impl W {
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "RC 24M track status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct STATUS_SPEC;
        impl crate::RegisterSpec for STATUS_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`status::R`](R) reader structure"]
        impl crate::Readable for STATUS_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"]
        impl crate::Writable for STATUS_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets STATUS to value 0"]
        impl crate::Resettable for STATUS_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "PGPR0"]
pub struct PGPR0 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PGPR0 {}
impl PGPR0 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const pgpr0::RegisterBlock = 0xf411_0000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const pgpr0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PGPR0 {
    type Target = pgpr0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PGPR0 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PGPR0").finish()
    }
}
#[doc = "PGPR0"]
pub mod pgpr0 {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        pmic_gpr00: PMIC_GPR00,
        pmic_gpr01: PMIC_GPR01,
        pmic_gpr02: PMIC_GPR02,
        pmic_gpr03: PMIC_GPR03,
        pmic_gpr04: PMIC_GPR04,
        pmic_gpr05: PMIC_GPR05,
        pmic_gpr06: PMIC_GPR06,
        pmic_gpr07: PMIC_GPR07,
        pmic_gpr08: PMIC_GPR08,
        pmic_gpr09: PMIC_GPR09,
        pmic_gpr10: PMIC_GPR10,
        pmic_gpr11: PMIC_GPR11,
        pmic_gpr12: PMIC_GPR12,
        pmic_gpr13: PMIC_GPR13,
        pmic_gpr14: PMIC_GPR14,
        pmic_gpr15: PMIC_GPR15,
    }
    impl RegisterBlock {
        #[doc = "0x00 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr00(&self) -> &PMIC_GPR00 {
            &self.pmic_gpr00
        }
        #[doc = "0x04 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr01(&self) -> &PMIC_GPR01 {
            &self.pmic_gpr01
        }
        #[doc = "0x08 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr02(&self) -> &PMIC_GPR02 {
            &self.pmic_gpr02
        }
        #[doc = "0x0c - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr03(&self) -> &PMIC_GPR03 {
            &self.pmic_gpr03
        }
        #[doc = "0x10 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr04(&self) -> &PMIC_GPR04 {
            &self.pmic_gpr04
        }
        #[doc = "0x14 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr05(&self) -> &PMIC_GPR05 {
            &self.pmic_gpr05
        }
        #[doc = "0x18 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr06(&self) -> &PMIC_GPR06 {
            &self.pmic_gpr06
        }
        #[doc = "0x1c - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr07(&self) -> &PMIC_GPR07 {
            &self.pmic_gpr07
        }
        #[doc = "0x20 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr08(&self) -> &PMIC_GPR08 {
            &self.pmic_gpr08
        }
        #[doc = "0x24 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr09(&self) -> &PMIC_GPR09 {
            &self.pmic_gpr09
        }
        #[doc = "0x28 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr10(&self) -> &PMIC_GPR10 {
            &self.pmic_gpr10
        }
        #[doc = "0x2c - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr11(&self) -> &PMIC_GPR11 {
            &self.pmic_gpr11
        }
        #[doc = "0x30 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr12(&self) -> &PMIC_GPR12 {
            &self.pmic_gpr12
        }
        #[doc = "0x34 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr13(&self) -> &PMIC_GPR13 {
            &self.pmic_gpr13
        }
        #[doc = "0x38 - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr14(&self) -> &PMIC_GPR14 {
            &self.pmic_gpr14
        }
        #[doc = "0x3c - Generic control"]
        #[inline(always)]
        pub const fn pmic_gpr15(&self) -> &PMIC_GPR15 {
            &self.pmic_gpr15
        }
    }
    #[doc = "PMIC_GPR00 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr00::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr00::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr00`]
module"]
    pub type PMIC_GPR00 = crate::Reg<pmic_gpr00::PMIC_GPR00_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr00 {
        #[doc = "Register `PMIC_GPR00` reader"]
        pub type R = crate::R<PMIC_GPR00_SPEC>;
        #[doc = "Register `PMIC_GPR00` writer"]
        pub type W = crate::W<PMIC_GPR00_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR00_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr00::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr00::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR00_SPEC;
        impl crate::RegisterSpec for PMIC_GPR00_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr00::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR00_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr00::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR00_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR00 to value 0"]
        impl crate::Resettable for PMIC_GPR00_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR01 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr01`]
module"]
    pub type PMIC_GPR01 = crate::Reg<pmic_gpr01::PMIC_GPR01_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr01 {
        #[doc = "Register `PMIC_GPR01` reader"]
        pub type R = crate::R<PMIC_GPR01_SPEC>;
        #[doc = "Register `PMIC_GPR01` writer"]
        pub type W = crate::W<PMIC_GPR01_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR01_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR01_SPEC;
        impl crate::RegisterSpec for PMIC_GPR01_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr01::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR01_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr01::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR01_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR01 to value 0"]
        impl crate::Resettable for PMIC_GPR01_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR02 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr02::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr02::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr02`]
module"]
    pub type PMIC_GPR02 = crate::Reg<pmic_gpr02::PMIC_GPR02_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr02 {
        #[doc = "Register `PMIC_GPR02` reader"]
        pub type R = crate::R<PMIC_GPR02_SPEC>;
        #[doc = "Register `PMIC_GPR02` writer"]
        pub type W = crate::W<PMIC_GPR02_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR02_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr02::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr02::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR02_SPEC;
        impl crate::RegisterSpec for PMIC_GPR02_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr02::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR02_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr02::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR02_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR02 to value 0"]
        impl crate::Resettable for PMIC_GPR02_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR03 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr03::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr03::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr03`]
module"]
    pub type PMIC_GPR03 = crate::Reg<pmic_gpr03::PMIC_GPR03_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr03 {
        #[doc = "Register `PMIC_GPR03` reader"]
        pub type R = crate::R<PMIC_GPR03_SPEC>;
        #[doc = "Register `PMIC_GPR03` writer"]
        pub type W = crate::W<PMIC_GPR03_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR03_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr03::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr03::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR03_SPEC;
        impl crate::RegisterSpec for PMIC_GPR03_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr03::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR03_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr03::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR03_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR03 to value 0"]
        impl crate::Resettable for PMIC_GPR03_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR04 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr04::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr04::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr04`]
module"]
    pub type PMIC_GPR04 = crate::Reg<pmic_gpr04::PMIC_GPR04_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr04 {
        #[doc = "Register `PMIC_GPR04` reader"]
        pub type R = crate::R<PMIC_GPR04_SPEC>;
        #[doc = "Register `PMIC_GPR04` writer"]
        pub type W = crate::W<PMIC_GPR04_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR04_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr04::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr04::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR04_SPEC;
        impl crate::RegisterSpec for PMIC_GPR04_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr04::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR04_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr04::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR04_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR04 to value 0"]
        impl crate::Resettable for PMIC_GPR04_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR05 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr05::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr05::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr05`]
module"]
    pub type PMIC_GPR05 = crate::Reg<pmic_gpr05::PMIC_GPR05_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr05 {
        #[doc = "Register `PMIC_GPR05` reader"]
        pub type R = crate::R<PMIC_GPR05_SPEC>;
        #[doc = "Register `PMIC_GPR05` writer"]
        pub type W = crate::W<PMIC_GPR05_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR05_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr05::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr05::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR05_SPEC;
        impl crate::RegisterSpec for PMIC_GPR05_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr05::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR05_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr05::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR05_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR05 to value 0"]
        impl crate::Resettable for PMIC_GPR05_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR06 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr06::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr06::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr06`]
module"]
    pub type PMIC_GPR06 = crate::Reg<pmic_gpr06::PMIC_GPR06_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr06 {
        #[doc = "Register `PMIC_GPR06` reader"]
        pub type R = crate::R<PMIC_GPR06_SPEC>;
        #[doc = "Register `PMIC_GPR06` writer"]
        pub type W = crate::W<PMIC_GPR06_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR06_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr06::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr06::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR06_SPEC;
        impl crate::RegisterSpec for PMIC_GPR06_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr06::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR06_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr06::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR06_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR06 to value 0"]
        impl crate::Resettable for PMIC_GPR06_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR07 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr07::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr07::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr07`]
module"]
    pub type PMIC_GPR07 = crate::Reg<pmic_gpr07::PMIC_GPR07_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr07 {
        #[doc = "Register `PMIC_GPR07` reader"]
        pub type R = crate::R<PMIC_GPR07_SPEC>;
        #[doc = "Register `PMIC_GPR07` writer"]
        pub type W = crate::W<PMIC_GPR07_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR07_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr07::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr07::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR07_SPEC;
        impl crate::RegisterSpec for PMIC_GPR07_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr07::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR07_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr07::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR07_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR07 to value 0"]
        impl crate::Resettable for PMIC_GPR07_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR08 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr08::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr08::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr08`]
module"]
    pub type PMIC_GPR08 = crate::Reg<pmic_gpr08::PMIC_GPR08_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr08 {
        #[doc = "Register `PMIC_GPR08` reader"]
        pub type R = crate::R<PMIC_GPR08_SPEC>;
        #[doc = "Register `PMIC_GPR08` writer"]
        pub type W = crate::W<PMIC_GPR08_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR08_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr08::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr08::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR08_SPEC;
        impl crate::RegisterSpec for PMIC_GPR08_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr08::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR08_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr08::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR08_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR08 to value 0"]
        impl crate::Resettable for PMIC_GPR08_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR09 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr09::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr09::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr09`]
module"]
    pub type PMIC_GPR09 = crate::Reg<pmic_gpr09::PMIC_GPR09_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr09 {
        #[doc = "Register `PMIC_GPR09` reader"]
        pub type R = crate::R<PMIC_GPR09_SPEC>;
        #[doc = "Register `PMIC_GPR09` writer"]
        pub type W = crate::W<PMIC_GPR09_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR09_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr09::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr09::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR09_SPEC;
        impl crate::RegisterSpec for PMIC_GPR09_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr09::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR09_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr09::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR09_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR09 to value 0"]
        impl crate::Resettable for PMIC_GPR09_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR10 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr10::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr10`]
module"]
    pub type PMIC_GPR10 = crate::Reg<pmic_gpr10::PMIC_GPR10_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr10 {
        #[doc = "Register `PMIC_GPR10` reader"]
        pub type R = crate::R<PMIC_GPR10_SPEC>;
        #[doc = "Register `PMIC_GPR10` writer"]
        pub type W = crate::W<PMIC_GPR10_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR10_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr10::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR10_SPEC;
        impl crate::RegisterSpec for PMIC_GPR10_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr10::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR10_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr10::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR10_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR10 to value 0"]
        impl crate::Resettable for PMIC_GPR10_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR11 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr11::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr11`]
module"]
    pub type PMIC_GPR11 = crate::Reg<pmic_gpr11::PMIC_GPR11_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr11 {
        #[doc = "Register `PMIC_GPR11` reader"]
        pub type R = crate::R<PMIC_GPR11_SPEC>;
        #[doc = "Register `PMIC_GPR11` writer"]
        pub type W = crate::W<PMIC_GPR11_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR11_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr11::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR11_SPEC;
        impl crate::RegisterSpec for PMIC_GPR11_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr11::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR11_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr11::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR11_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR11 to value 0"]
        impl crate::Resettable for PMIC_GPR11_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR12 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr12::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr12`]
module"]
    pub type PMIC_GPR12 = crate::Reg<pmic_gpr12::PMIC_GPR12_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr12 {
        #[doc = "Register `PMIC_GPR12` reader"]
        pub type R = crate::R<PMIC_GPR12_SPEC>;
        #[doc = "Register `PMIC_GPR12` writer"]
        pub type W = crate::W<PMIC_GPR12_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR12_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr12::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR12_SPEC;
        impl crate::RegisterSpec for PMIC_GPR12_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr12::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR12_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr12::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR12_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR12 to value 0"]
        impl crate::Resettable for PMIC_GPR12_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR13 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr13::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr13`]
module"]
    pub type PMIC_GPR13 = crate::Reg<pmic_gpr13::PMIC_GPR13_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr13 {
        #[doc = "Register `PMIC_GPR13` reader"]
        pub type R = crate::R<PMIC_GPR13_SPEC>;
        #[doc = "Register `PMIC_GPR13` writer"]
        pub type W = crate::W<PMIC_GPR13_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR13_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr13::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR13_SPEC;
        impl crate::RegisterSpec for PMIC_GPR13_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr13::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR13_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr13::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR13_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR13 to value 0"]
        impl crate::Resettable for PMIC_GPR13_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR14 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr14::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr14`]
module"]
    pub type PMIC_GPR14 = crate::Reg<pmic_gpr14::PMIC_GPR14_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr14 {
        #[doc = "Register `PMIC_GPR14` reader"]
        pub type R = crate::R<PMIC_GPR14_SPEC>;
        #[doc = "Register `PMIC_GPR14` writer"]
        pub type W = crate::W<PMIC_GPR14_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR14_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr14::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR14_SPEC;
        impl crate::RegisterSpec for PMIC_GPR14_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr14::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR14_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr14::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR14_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR14 to value 0"]
        impl crate::Resettable for PMIC_GPR14_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "PMIC_GPR15 (rw) register accessor: Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr15::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr15::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmic_gpr15`]
module"]
    pub type PMIC_GPR15 = crate::Reg<pmic_gpr15::PMIC_GPR15_SPEC>;
    #[doc = "Generic control"]
    pub mod pmic_gpr15 {
        #[doc = "Register `PMIC_GPR15` reader"]
        pub type R = crate::R<PMIC_GPR15_SPEC>;
        #[doc = "Register `PMIC_GPR15` writer"]
        pub type W = crate::W<PMIC_GPR15_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<PMIC_GPR15_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmic_gpr15::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmic_gpr15::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct PMIC_GPR15_SPEC;
        impl crate::RegisterSpec for PMIC_GPR15_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`pmic_gpr15::R`](R) reader structure"]
        impl crate::Readable for PMIC_GPR15_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`pmic_gpr15::W`](W) writer structure"]
        impl crate::Writable for PMIC_GPR15_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets PMIC_GPR15 to value 0"]
        impl crate::Resettable for PMIC_GPR15_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[doc = "PGPR1"]
pub struct PGPR1 {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PGPR1 {}
impl PGPR1 {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const pgpr0::RegisterBlock = 0xf411_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const pgpr0::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PGPR1 {
    type Target = pgpr0::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PGPR1 {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PGPR1").finish()
    }
}
#[doc = "PGPR1"]
pub use self::pgpr0 as pgpr1;
#[doc = "PDGO"]
pub struct PDGO {
    _marker: PhantomData<*const ()>,
}
unsafe impl Send for PDGO {}
impl PDGO {
    #[doc = r"Pointer to the register block"]
    pub const PTR: *const pdgo::RegisterBlock = 0xf413_4000 as *const _;
    #[doc = r"Return the pointer to the register block"]
    #[inline(always)]
    pub const fn ptr() -> *const pdgo::RegisterBlock {
        Self::PTR
    }
    #[doc = r" Steal an instance of this peripheral"]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
    #[doc = r" that may race with any existing instances, for example by only"]
    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
    #[doc = r" original peripheral and using critical sections to coordinate"]
    #[doc = r" access between multiple new instances."]
    #[doc = r""]
    #[doc = r" Additionally, other software such as HALs may rely on only one"]
    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
    #[doc = r" no stolen instances are passed to such software."]
    pub unsafe fn steal() -> Self {
        Self {
            _marker: PhantomData,
        }
    }
}
impl Deref for PDGO {
    type Target = pdgo::RegisterBlock;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        unsafe { &*Self::PTR }
    }
}
impl core::fmt::Debug for PDGO {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("PDGO").finish()
    }
}
#[doc = "PDGO"]
pub mod pdgo {
    #[doc = r"Register block"]
    #[repr(C)]
    pub struct RegisterBlock {
        dgo_turnoff: DGO_TURNOFF,
        dgo_rc32k_cfg: DGO_RC32K_CFG,
        _reserved2: [u8; 0x05f8],
        dgo_gpr00: DGO_GPR00,
        dgo_gpr01: DGO_GPR01,
        dgo_gpr02: DGO_GPR02,
        dgo_gpr03: DGO_GPR03,
        _reserved6: [u8; 0xf0],
        dgo_ctr0: DGO_CTR0,
        dgo_ctr1: DGO_CTR1,
        dgo_ctr2: DGO_CTR2,
        dgo_ctr3: DGO_CTR3,
        dgo_ctr4: DGO_CTR4,
    }
    impl RegisterBlock {
        #[doc = "0x00 - trunoff control"]
        #[inline(always)]
        pub const fn dgo_turnoff(&self) -> &DGO_TURNOFF {
            &self.dgo_turnoff
        }
        #[doc = "0x04 - RC32K CLOCK"]
        #[inline(always)]
        pub const fn dgo_rc32k_cfg(&self) -> &DGO_RC32K_CFG {
            &self.dgo_rc32k_cfg
        }
        #[doc = "0x600 - Generic control 0"]
        #[inline(always)]
        pub const fn dgo_gpr00(&self) -> &DGO_GPR00 {
            &self.dgo_gpr00
        }
        #[doc = "0x604 - Generic control 1"]
        #[inline(always)]
        pub const fn dgo_gpr01(&self) -> &DGO_GPR01 {
            &self.dgo_gpr01
        }
        #[doc = "0x608 - Generic control 2"]
        #[inline(always)]
        pub const fn dgo_gpr02(&self) -> &DGO_GPR02 {
            &self.dgo_gpr02
        }
        #[doc = "0x60c - Generic control 3"]
        #[inline(always)]
        pub const fn dgo_gpr03(&self) -> &DGO_GPR03 {
            &self.dgo_gpr03
        }
        #[doc = "0x700 - control register 0"]
        #[inline(always)]
        pub const fn dgo_ctr0(&self) -> &DGO_CTR0 {
            &self.dgo_ctr0
        }
        #[doc = "0x704 - control register 1"]
        #[inline(always)]
        pub const fn dgo_ctr1(&self) -> &DGO_CTR1 {
            &self.dgo_ctr1
        }
        #[doc = "0x708 - control register 2"]
        #[inline(always)]
        pub const fn dgo_ctr2(&self) -> &DGO_CTR2 {
            &self.dgo_ctr2
        }
        #[doc = "0x70c - control register 3"]
        #[inline(always)]
        pub const fn dgo_ctr3(&self) -> &DGO_CTR3 {
            &self.dgo_ctr3
        }
        #[doc = "0x710 - control register 4"]
        #[inline(always)]
        pub const fn dgo_ctr4(&self) -> &DGO_CTR4 {
            &self.dgo_ctr4
        }
    }
    #[doc = "DGO_TURNOFF (rw) register accessor: trunoff control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_turnoff::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_turnoff::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_turnoff`]
module"]
    pub type DGO_TURNOFF = crate::Reg<dgo_turnoff::DGO_TURNOFF_SPEC>;
    #[doc = "trunoff control"]
    pub mod dgo_turnoff {
        #[doc = "Register `DGO_TURNOFF` reader"]
        pub type R = crate::R<DGO_TURNOFF_SPEC>;
        #[doc = "Register `DGO_TURNOFF` writer"]
        pub type W = crate::W<DGO_TURNOFF_SPEC>;
        #[doc = "Field `COUNTER` writer - trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1."]
        pub type COUNTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl W {
            #[doc = "Bits 0:31 - trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1."]
            #[inline(always)]
            #[must_use]
            pub fn counter(&mut self) -> COUNTER_W<DGO_TURNOFF_SPEC> {
                COUNTER_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "trunoff control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_turnoff::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_turnoff::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_TURNOFF_SPEC;
        impl crate::RegisterSpec for DGO_TURNOFF_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_turnoff::R`](R) reader structure"]
        impl crate::Readable for DGO_TURNOFF_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_turnoff::W`](W) writer structure"]
        impl crate::Writable for DGO_TURNOFF_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_TURNOFF to value 0"]
        impl crate::Resettable for DGO_TURNOFF_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_RC32K_CFG (rw) register accessor: RC32K CLOCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_rc32k_cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_rc32k_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_rc32k_cfg`]
module"]
    pub type DGO_RC32K_CFG = crate::Reg<dgo_rc32k_cfg::DGO_RC32K_CFG_SPEC>;
    #[doc = "RC32K CLOCK"]
    pub mod dgo_rc32k_cfg {
        #[doc = "Register `DGO_RC32K_CFG` reader"]
        pub type R = crate::R<DGO_RC32K_CFG_SPEC>;
        #[doc = "Register `DGO_RC32K_CFG` writer"]
        pub type W = crate::W<DGO_RC32K_CFG_SPEC>;
        #[doc = "Field `CAP_TRIM` reader - capacitor trim bits"]
        pub type CAP_TRIM_R = crate::FieldReader<u16>;
        #[doc = "Field `CAP_TRIM` writer - capacitor trim bits"]
        pub type CAP_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
        #[doc = "Field `CAPEX6_TRIM` reader - IRC32K bit 6"]
        pub type CAPEX6_TRIM_R = crate::BitReader;
        #[doc = "Field `CAPEX6_TRIM` writer - IRC32K bit 6"]
        pub type CAPEX6_TRIM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `CAPEX7_TRIM` reader - IRC32K bit 7"]
        pub type CAPEX7_TRIM_R = crate::BitReader;
        #[doc = "Field `CAPEX7_TRIM` writer - IRC32K bit 7"]
        pub type CAPEX7_TRIM_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `IRC_TRIMMED` reader - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: irc is not trimmed 1: irc is trimmed"]
        pub type IRC_TRIMMED_R = crate::BitReader;
        #[doc = "Field `IRC_TRIMMED` writer - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: irc is not trimmed 1: irc is trimmed"]
        pub type IRC_TRIMMED_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bits 0:8 - capacitor trim bits"]
            #[inline(always)]
            pub fn cap_trim(&self) -> CAP_TRIM_R {
                CAP_TRIM_R::new((self.bits & 0x01ff) as u16)
            }
            #[doc = "Bit 22 - IRC32K bit 6"]
            #[inline(always)]
            pub fn capex6_trim(&self) -> CAPEX6_TRIM_R {
                CAPEX6_TRIM_R::new(((self.bits >> 22) & 1) != 0)
            }
            #[doc = "Bit 23 - IRC32K bit 7"]
            #[inline(always)]
            pub fn capex7_trim(&self) -> CAPEX7_TRIM_R {
                CAPEX7_TRIM_R::new(((self.bits >> 23) & 1) != 0)
            }
            #[doc = "Bit 31 - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: irc is not trimmed 1: irc is trimmed"]
            #[inline(always)]
            pub fn irc_trimmed(&self) -> IRC_TRIMMED_R {
                IRC_TRIMMED_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bits 0:8 - capacitor trim bits"]
            #[inline(always)]
            #[must_use]
            pub fn cap_trim(&mut self) -> CAP_TRIM_W<DGO_RC32K_CFG_SPEC> {
                CAP_TRIM_W::new(self, 0)
            }
            #[doc = "Bit 22 - IRC32K bit 6"]
            #[inline(always)]
            #[must_use]
            pub fn capex6_trim(&mut self) -> CAPEX6_TRIM_W<DGO_RC32K_CFG_SPEC> {
                CAPEX6_TRIM_W::new(self, 22)
            }
            #[doc = "Bit 23 - IRC32K bit 7"]
            #[inline(always)]
            #[must_use]
            pub fn capex7_trim(&mut self) -> CAPEX7_TRIM_W<DGO_RC32K_CFG_SPEC> {
                CAPEX7_TRIM_W::new(self, 23)
            }
            #[doc = "Bit 31 - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value 0: irc is not trimmed 1: irc is trimmed"]
            #[inline(always)]
            #[must_use]
            pub fn irc_trimmed(&mut self) -> IRC_TRIMMED_W<DGO_RC32K_CFG_SPEC> {
                IRC_TRIMMED_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "RC32K CLOCK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_rc32k_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_rc32k_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_RC32K_CFG_SPEC;
        impl crate::RegisterSpec for DGO_RC32K_CFG_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_rc32k_cfg::R`](R) reader structure"]
        impl crate::Readable for DGO_RC32K_CFG_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_rc32k_cfg::W`](W) writer structure"]
        impl crate::Writable for DGO_RC32K_CFG_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_RC32K_CFG to value 0"]
        impl crate::Resettable for DGO_RC32K_CFG_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_GPR00 (rw) register accessor: Generic control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr00::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr00::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_gpr00`]
module"]
    pub type DGO_GPR00 = crate::Reg<dgo_gpr00::DGO_GPR00_SPEC>;
    #[doc = "Generic control 0"]
    pub mod dgo_gpr00 {
        #[doc = "Register `DGO_GPR00` reader"]
        pub type R = crate::R<DGO_GPR00_SPEC>;
        #[doc = "Register `DGO_GPR00` writer"]
        pub type W = crate::W<DGO_GPR00_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<DGO_GPR00_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr00::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr00::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_GPR00_SPEC;
        impl crate::RegisterSpec for DGO_GPR00_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_gpr00::R`](R) reader structure"]
        impl crate::Readable for DGO_GPR00_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_gpr00::W`](W) writer structure"]
        impl crate::Writable for DGO_GPR00_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_GPR00 to value 0"]
        impl crate::Resettable for DGO_GPR00_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_GPR01 (rw) register accessor: Generic control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_gpr01`]
module"]
    pub type DGO_GPR01 = crate::Reg<dgo_gpr01::DGO_GPR01_SPEC>;
    #[doc = "Generic control 1"]
    pub mod dgo_gpr01 {
        #[doc = "Register `DGO_GPR01` reader"]
        pub type R = crate::R<DGO_GPR01_SPEC>;
        #[doc = "Register `DGO_GPR01` writer"]
        pub type W = crate::W<DGO_GPR01_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<DGO_GPR01_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_GPR01_SPEC;
        impl crate::RegisterSpec for DGO_GPR01_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_gpr01::R`](R) reader structure"]
        impl crate::Readable for DGO_GPR01_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_gpr01::W`](W) writer structure"]
        impl crate::Writable for DGO_GPR01_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_GPR01 to value 0"]
        impl crate::Resettable for DGO_GPR01_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_GPR02 (rw) register accessor: Generic control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr02::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr02::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_gpr02`]
module"]
    pub type DGO_GPR02 = crate::Reg<dgo_gpr02::DGO_GPR02_SPEC>;
    #[doc = "Generic control 2"]
    pub mod dgo_gpr02 {
        #[doc = "Register `DGO_GPR02` reader"]
        pub type R = crate::R<DGO_GPR02_SPEC>;
        #[doc = "Register `DGO_GPR02` writer"]
        pub type W = crate::W<DGO_GPR02_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<DGO_GPR02_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr02::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr02::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_GPR02_SPEC;
        impl crate::RegisterSpec for DGO_GPR02_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_gpr02::R`](R) reader structure"]
        impl crate::Readable for DGO_GPR02_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_gpr02::W`](W) writer structure"]
        impl crate::Writable for DGO_GPR02_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_GPR02 to value 0"]
        impl crate::Resettable for DGO_GPR02_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_GPR03 (rw) register accessor: Generic control 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr03::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr03::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_gpr03`]
module"]
    pub type DGO_GPR03 = crate::Reg<dgo_gpr03::DGO_GPR03_SPEC>;
    #[doc = "Generic control 3"]
    pub mod dgo_gpr03 {
        #[doc = "Register `DGO_GPR03` reader"]
        pub type R = crate::R<DGO_GPR03_SPEC>;
        #[doc = "Register `DGO_GPR03` writer"]
        pub type W = crate::W<DGO_GPR03_SPEC>;
        #[doc = "Field `GPR` reader - Generic control"]
        pub type GPR_R = crate::FieldReader<u32>;
        #[doc = "Field `GPR` writer - Generic control"]
        pub type GPR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            pub fn gpr(&self) -> GPR_R {
                GPR_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - Generic control"]
            #[inline(always)]
            #[must_use]
            pub fn gpr(&mut self) -> GPR_W<DGO_GPR03_SPEC> {
                GPR_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "Generic control 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_gpr03::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_gpr03::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_GPR03_SPEC;
        impl crate::RegisterSpec for DGO_GPR03_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_gpr03::R`](R) reader structure"]
        impl crate::Readable for DGO_GPR03_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_gpr03::W`](W) writer structure"]
        impl crate::Writable for DGO_GPR03_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_GPR03 to value 0"]
        impl crate::Resettable for DGO_GPR03_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_CTR0 (rw) register accessor: control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_ctr0`]
module"]
    pub type DGO_CTR0 = crate::Reg<dgo_ctr0::DGO_CTR0_SPEC>;
    #[doc = "control register 0"]
    pub mod dgo_ctr0 {
        #[doc = "Register `DGO_CTR0` reader"]
        pub type R = crate::R<DGO_CTR0_SPEC>;
        #[doc = "Register `DGO_CTR0` writer"]
        pub type W = crate::W<DGO_CTR0_SPEC>;
        #[doc = "Field `RETENTION` reader - dgo register status retenion"]
        pub type RETENTION_R = crate::BitReader;
        #[doc = "Field `RETENTION` writer - dgo register status retenion"]
        pub type RETENTION_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 16 - dgo register status retenion"]
            #[inline(always)]
            pub fn retention(&self) -> RETENTION_R {
                RETENTION_R::new(((self.bits >> 16) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 16 - dgo register status retenion"]
            #[inline(always)]
            #[must_use]
            pub fn retention(&mut self) -> RETENTION_W<DGO_CTR0_SPEC> {
                RETENTION_W::new(self, 16)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_CTR0_SPEC;
        impl crate::RegisterSpec for DGO_CTR0_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_ctr0::R`](R) reader structure"]
        impl crate::Readable for DGO_CTR0_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_ctr0::W`](W) writer structure"]
        impl crate::Writable for DGO_CTR0_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_CTR0 to value 0"]
        impl crate::Resettable for DGO_CTR0_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_CTR1 (rw) register accessor: control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_ctr1`]
module"]
    pub type DGO_CTR1 = crate::Reg<dgo_ctr1::DGO_CTR1_SPEC>;
    #[doc = "control register 1"]
    pub mod dgo_ctr1 {
        #[doc = "Register `DGO_CTR1` reader"]
        pub type R = crate::R<DGO_CTR1_SPEC>;
        #[doc = "Register `DGO_CTR1` writer"]
        pub type W = crate::W<DGO_CTR1_SPEC>;
        #[doc = "Field `PIN_WAKEUP_STATUS` reader - wakeup pin status"]
        pub type PIN_WAKEUP_STATUS_R = crate::BitReader;
        #[doc = "Field `WAKEUP_EN` reader - permit wakeup pin or software wakeup"]
        pub type WAKEUP_EN_R = crate::BitReader;
        #[doc = "Field `WAKEUP_EN` writer - permit wakeup pin or software wakeup"]
        pub type WAKEUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `AOTO_SYS_WAKEUP` reader - software wakeup： 0 : wakeup once； 1：auto wakeup Continuously"]
        pub type AOTO_SYS_WAKEUP_R = crate::BitReader;
        #[doc = "Field `AOTO_SYS_WAKEUP` writer - software wakeup： 0 : wakeup once； 1：auto wakeup Continuously"]
        pub type AOTO_SYS_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - wakeup pin status"]
            #[inline(always)]
            pub fn pin_wakeup_status(&self) -> PIN_WAKEUP_STATUS_R {
                PIN_WAKEUP_STATUS_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 16 - permit wakeup pin or software wakeup"]
            #[inline(always)]
            pub fn wakeup_en(&self) -> WAKEUP_EN_R {
                WAKEUP_EN_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 31 - software wakeup： 0 : wakeup once； 1：auto wakeup Continuously"]
            #[inline(always)]
            pub fn aoto_sys_wakeup(&self) -> AOTO_SYS_WAKEUP_R {
                AOTO_SYS_WAKEUP_R::new(((self.bits >> 31) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 16 - permit wakeup pin or software wakeup"]
            #[inline(always)]
            #[must_use]
            pub fn wakeup_en(&mut self) -> WAKEUP_EN_W<DGO_CTR1_SPEC> {
                WAKEUP_EN_W::new(self, 16)
            }
            #[doc = "Bit 31 - software wakeup： 0 : wakeup once； 1：auto wakeup Continuously"]
            #[inline(always)]
            #[must_use]
            pub fn aoto_sys_wakeup(&mut self) -> AOTO_SYS_WAKEUP_W<DGO_CTR1_SPEC> {
                AOTO_SYS_WAKEUP_W::new(self, 31)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_CTR1_SPEC;
        impl crate::RegisterSpec for DGO_CTR1_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_ctr1::R`](R) reader structure"]
        impl crate::Readable for DGO_CTR1_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_ctr1::W`](W) writer structure"]
        impl crate::Writable for DGO_CTR1_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_CTR1 to value 0"]
        impl crate::Resettable for DGO_CTR1_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_CTR2 (rw) register accessor: control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_ctr2`]
module"]
    pub type DGO_CTR2 = crate::Reg<dgo_ctr2::DGO_CTR2_SPEC>;
    #[doc = "control register 2"]
    pub mod dgo_ctr2 {
        #[doc = "Register `DGO_CTR2` reader"]
        pub type R = crate::R<DGO_CTR2_SPEC>;
        #[doc = "Register `DGO_CTR2` writer"]
        pub type W = crate::W<DGO_CTR2_SPEC>;
        #[doc = "Field `WAKEUP_PULLDN_DISABLE` reader - wakeup pin pull down disable"]
        pub type WAKEUP_PULLDN_DISABLE_R = crate::BitReader;
        #[doc = "Field `WAKEUP_PULLDN_DISABLE` writer - wakeup pin pull down disable"]
        pub type WAKEUP_PULLDN_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `RESETN_PULLUP_DISABLE` reader - resetn pin pull up disable"]
        pub type RESETN_PULLUP_DISABLE_R = crate::BitReader;
        #[doc = "Field `RESETN_PULLUP_DISABLE` writer - resetn pin pull up disable"]
        pub type RESETN_PULLUP_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 16 - wakeup pin pull down disable"]
            #[inline(always)]
            pub fn wakeup_pulldn_disable(&self) -> WAKEUP_PULLDN_DISABLE_R {
                WAKEUP_PULLDN_DISABLE_R::new(((self.bits >> 16) & 1) != 0)
            }
            #[doc = "Bit 24 - resetn pin pull up disable"]
            #[inline(always)]
            pub fn resetn_pullup_disable(&self) -> RESETN_PULLUP_DISABLE_R {
                RESETN_PULLUP_DISABLE_R::new(((self.bits >> 24) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 16 - wakeup pin pull down disable"]
            #[inline(always)]
            #[must_use]
            pub fn wakeup_pulldn_disable(&mut self) -> WAKEUP_PULLDN_DISABLE_W<DGO_CTR2_SPEC> {
                WAKEUP_PULLDN_DISABLE_W::new(self, 16)
            }
            #[doc = "Bit 24 - resetn pin pull up disable"]
            #[inline(always)]
            #[must_use]
            pub fn resetn_pullup_disable(&mut self) -> RESETN_PULLUP_DISABLE_W<DGO_CTR2_SPEC> {
                RESETN_PULLUP_DISABLE_W::new(self, 24)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_CTR2_SPEC;
        impl crate::RegisterSpec for DGO_CTR2_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_ctr2::R`](R) reader structure"]
        impl crate::Readable for DGO_CTR2_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_ctr2::W`](W) writer structure"]
        impl crate::Writable for DGO_CTR2_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_CTR2 to value 0"]
        impl crate::Resettable for DGO_CTR2_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_CTR3 (rw) register accessor: control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_ctr3`]
module"]
    pub type DGO_CTR3 = crate::Reg<dgo_ctr3::DGO_CTR3_SPEC>;
    #[doc = "control register 3"]
    pub mod dgo_ctr3 {
        #[doc = "Register `DGO_CTR3` reader"]
        pub type R = crate::R<DGO_CTR3_SPEC>;
        #[doc = "Register `DGO_CTR3` writer"]
        pub type W = crate::W<DGO_CTR3_SPEC>;
        #[doc = "Field `WAKEUP_COUNTER` reader - software wakeup counter"]
        pub type WAKEUP_COUNTER_R = crate::FieldReader<u32>;
        #[doc = "Field `WAKEUP_COUNTER` writer - software wakeup counter"]
        pub type WAKEUP_COUNTER_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
        impl R {
            #[doc = "Bits 0:31 - software wakeup counter"]
            #[inline(always)]
            pub fn wakeup_counter(&self) -> WAKEUP_COUNTER_R {
                WAKEUP_COUNTER_R::new(self.bits)
            }
        }
        impl W {
            #[doc = "Bits 0:31 - software wakeup counter"]
            #[inline(always)]
            #[must_use]
            pub fn wakeup_counter(&mut self) -> WAKEUP_COUNTER_W<DGO_CTR3_SPEC> {
                WAKEUP_COUNTER_W::new(self, 0)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_CTR3_SPEC;
        impl crate::RegisterSpec for DGO_CTR3_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_ctr3::R`](R) reader structure"]
        impl crate::Readable for DGO_CTR3_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_ctr3::W`](W) writer structure"]
        impl crate::Writable for DGO_CTR3_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_CTR3 to value 0"]
        impl crate::Resettable for DGO_CTR3_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
    #[doc = "DGO_CTR4 (rw) register accessor: control register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr4::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dgo_ctr4`]
module"]
    pub type DGO_CTR4 = crate::Reg<dgo_ctr4::DGO_CTR4_SPEC>;
    #[doc = "control register 4"]
    pub mod dgo_ctr4 {
        #[doc = "Register `DGO_CTR4` reader"]
        pub type R = crate::R<DGO_CTR4_SPEC>;
        #[doc = "Register `DGO_CTR4` writer"]
        pub type W = crate::W<DGO_CTR4_SPEC>;
        #[doc = "Field `BANDGAP_LP_MODE` reader - Banggap work in low power mode, banggap function limited 0: banggap works in normal mode 1: banggap works in low power mode"]
        pub type BANDGAP_LP_MODE_R = crate::BitReader;
        #[doc = "Field `BANDGAP_LP_MODE` writer - Banggap work in low power mode, banggap function limited 0: banggap works in normal mode 1: banggap works in low power mode"]
        pub type BANDGAP_LP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
        #[doc = "Field `BANDGAP_LESS_POWER` reader - Banggap work in power save mode, banggap function normally 0: banggap works in high performance mode 1: banggap works in power saving mode"]
        pub type BANDGAP_LESS_POWER_R = crate::BitReader;
        #[doc = "Field `BANDGAP_LESS_POWER` writer - Banggap work in power save mode, banggap function normally 0: banggap works in high performance mode 1: banggap works in power saving mode"]
        pub type BANDGAP_LESS_POWER_W<'a, REG> = crate::BitWriter<'a, REG>;
        impl R {
            #[doc = "Bit 0 - Banggap work in low power mode, banggap function limited 0: banggap works in normal mode 1: banggap works in low power mode"]
            #[inline(always)]
            pub fn bandgap_lp_mode(&self) -> BANDGAP_LP_MODE_R {
                BANDGAP_LP_MODE_R::new((self.bits & 1) != 0)
            }
            #[doc = "Bit 1 - Banggap work in power save mode, banggap function normally 0: banggap works in high performance mode 1: banggap works in power saving mode"]
            #[inline(always)]
            pub fn bandgap_less_power(&self) -> BANDGAP_LESS_POWER_R {
                BANDGAP_LESS_POWER_R::new(((self.bits >> 1) & 1) != 0)
            }
        }
        impl W {
            #[doc = "Bit 0 - Banggap work in low power mode, banggap function limited 0: banggap works in normal mode 1: banggap works in low power mode"]
            #[inline(always)]
            #[must_use]
            pub fn bandgap_lp_mode(&mut self) -> BANDGAP_LP_MODE_W<DGO_CTR4_SPEC> {
                BANDGAP_LP_MODE_W::new(self, 0)
            }
            #[doc = "Bit 1 - Banggap work in power save mode, banggap function normally 0: banggap works in high performance mode 1: banggap works in power saving mode"]
            #[inline(always)]
            #[must_use]
            pub fn bandgap_less_power(&mut self) -> BANDGAP_LESS_POWER_W<DGO_CTR4_SPEC> {
                BANDGAP_LESS_POWER_W::new(self, 1)
            }
            #[doc = r" Writes raw bits to the register."]
            #[doc = r""]
            #[doc = r" # Safety"]
            #[doc = r""]
            #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
            #[inline(always)]
            pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
                self.bits = bits;
                self
            }
        }
        #[doc = "control register 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dgo_ctr4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dgo_ctr4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
        pub struct DGO_CTR4_SPEC;
        impl crate::RegisterSpec for DGO_CTR4_SPEC {
            type Ux = u32;
        }
        #[doc = "`read()` method returns [`dgo_ctr4::R`](R) reader structure"]
        impl crate::Readable for DGO_CTR4_SPEC {}
        #[doc = "`write(|w| ..)` method takes [`dgo_ctr4::W`](W) writer structure"]
        impl crate::Writable for DGO_CTR4_SPEC {
            const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
            const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
        }
        #[doc = "`reset()` method sets DGO_CTR4 to value 0"]
        impl crate::Resettable for DGO_CTR4_SPEC {
            const RESET_VALUE: u32 = 0;
        }
    }
}
#[no_mangle]
static mut DEVICE_PERIPHERALS: bool = false;
#[doc = r" All the peripherals."]
#[allow(non_snake_case)]
pub struct Peripherals {
    #[doc = "FGPIO"]
    pub FGPIO: FGPIO,
    #[doc = "GPIO0"]
    pub GPIO0: GPIO0,
    #[doc = "PGPIO"]
    pub PGPIO: PGPIO,
    #[doc = "PLIC"]
    pub PLIC: PLIC,
    #[doc = "MCHTMR"]
    pub MCHTMR: MCHTMR,
    #[doc = "PLICSW"]
    pub PLICSW: PLICSW,
    #[doc = "GPTMR0"]
    pub GPTMR0: GPTMR0,
    #[doc = "GPTMR1"]
    pub GPTMR1: GPTMR1,
    #[doc = "GPTMR2"]
    pub GPTMR2: GPTMR2,
    #[doc = "GPTMR3"]
    pub GPTMR3: GPTMR3,
    #[doc = "PTMR"]
    pub PTMR: PTMR,
    #[doc = "LIN0"]
    pub LIN0: LIN0,
    #[doc = "LIN1"]
    pub LIN1: LIN1,
    #[doc = "LIN2"]
    pub LIN2: LIN2,
    #[doc = "LIN3"]
    pub LIN3: LIN3,
    #[doc = "UART0"]
    pub UART0: UART0,
    #[doc = "UART1"]
    pub UART1: UART1,
    #[doc = "UART2"]
    pub UART2: UART2,
    #[doc = "UART3"]
    pub UART3: UART3,
    #[doc = "UART4"]
    pub UART4: UART4,
    #[doc = "UART5"]
    pub UART5: UART5,
    #[doc = "UART6"]
    pub UART6: UART6,
    #[doc = "UART7"]
    pub UART7: UART7,
    #[doc = "PUART"]
    pub PUART: PUART,
    #[doc = "I2C0"]
    pub I2C0: I2C0,
    #[doc = "I2C1"]
    pub I2C1: I2C1,
    #[doc = "I2C2"]
    pub I2C2: I2C2,
    #[doc = "I2C3"]
    pub I2C3: I2C3,
    #[doc = "SPI0"]
    pub SPI0: SPI0,
    #[doc = "SPI1"]
    pub SPI1: SPI1,
    #[doc = "SPI2"]
    pub SPI2: SPI2,
    #[doc = "SPI3"]
    pub SPI3: SPI3,
    #[doc = "CRC"]
    pub CRC: CRC,
    #[doc = "TSNS"]
    pub TSNS: TSNS,
    #[doc = "MBX0A"]
    pub MBX0A: MBX0A,
    #[doc = "MBX0B"]
    pub MBX0B: MBX0B,
    #[doc = "WDG0"]
    pub WDG0: WDG0,
    #[doc = "WDG1"]
    pub WDG1: WDG1,
    #[doc = "PWDG"]
    pub PWDG: PWDG,
    #[doc = "DMAMUX"]
    pub DMAMUX: DMAMUX,
    #[doc = "HDMA"]
    pub HDMA: HDMA,
    #[doc = "GPIOM"]
    pub GPIOM: GPIOM,
    #[doc = "MCAN0"]
    pub MCAN0: MCAN0,
    #[doc = "MCAN1"]
    pub MCAN1: MCAN1,
    #[doc = "MCAN2"]
    pub MCAN2: MCAN2,
    #[doc = "MCAN3"]
    pub MCAN3: MCAN3,
    #[doc = "PTPC"]
    pub PTPC: PTPC,
    #[doc = "QEI0"]
    pub QEI0: QEI0,
    #[doc = "QEI1"]
    pub QEI1: QEI1,
    #[doc = "QEO0"]
    pub QEO0: QEO0,
    #[doc = "QEO1"]
    pub QEO1: QEO1,
    #[doc = "MMC0"]
    pub MMC0: MMC0,
    #[doc = "MMC1"]
    pub MMC1: MMC1,
    #[doc = "PWM0"]
    pub PWM0: PWM0,
    #[doc = "PWM1"]
    pub PWM1: PWM1,
    #[doc = "RDC"]
    pub RDC: RDC,
    #[doc = "PLB"]
    pub PLB: PLB,
    #[doc = "SYNT"]
    pub SYNT: SYNT,
    #[doc = "SEI"]
    pub SEI: SEI,
    #[doc = "TRGM0"]
    pub TRGM0: TRGM0,
    #[doc = "USB0"]
    pub USB0: USB0,
    #[doc = "SDP"]
    pub SDP: SDP,
    #[doc = "SEC"]
    pub SEC: SEC,
    #[doc = "MON"]
    pub MON: MON,
    #[doc = "RNG"]
    pub RNG: RNG,
    #[doc = "OTP"]
    pub OTP: OTP,
    #[doc = "KEYM"]
    pub KEYM: KEYM,
    #[doc = "ADC0"]
    pub ADC0: ADC0,
    #[doc = "ADC1"]
    pub ADC1: ADC1,
    #[doc = "DAC0"]
    pub DAC0: DAC0,
    #[doc = "DAC1"]
    pub DAC1: DAC1,
    #[doc = "OPAMP0"]
    pub OPAMP0: OPAMP0,
    #[doc = "OPAMP1"]
    pub OPAMP1: OPAMP1,
    #[doc = "ACMP"]
    pub ACMP: ACMP,
    #[doc = "SYSCTL"]
    pub SYSCTL: SYSCTL,
    #[doc = "IOC"]
    pub IOC: IOC,
    #[doc = "PIOC"]
    pub PIOC: PIOC,
    #[doc = "PLLCTLV2"]
    pub PLLCTLV2: PLLCTLV2,
    #[doc = "PPOR"]
    pub PPOR: PPOR,
    #[doc = "PCFG"]
    pub PCFG: PCFG,
    #[doc = "PGPR0"]
    pub PGPR0: PGPR0,
    #[doc = "PGPR1"]
    pub PGPR1: PGPR1,
    #[doc = "PDGO"]
    pub PDGO: PDGO,
}
impl Peripherals {
    #[doc = r" Returns all the peripherals *once*."]
    #[cfg(feature = "critical-section")]
    #[inline]
    pub fn take() -> Option<Self> {
        critical_section::with(|_| {
            if unsafe { DEVICE_PERIPHERALS } {
                return None;
            }
            Some(unsafe { Peripherals::steal() })
        })
    }
    #[doc = r" Unchecked version of `Peripherals::take`."]
    #[doc = r""]
    #[doc = r" # Safety"]
    #[doc = r""]
    #[doc = r" Each of the returned peripherals must be used at most once."]
    #[inline]
    pub unsafe fn steal() -> Self {
        DEVICE_PERIPHERALS = true;
        Peripherals {
            FGPIO: FGPIO {
                _marker: PhantomData,
            },
            GPIO0: GPIO0 {
                _marker: PhantomData,
            },
            PGPIO: PGPIO {
                _marker: PhantomData,
            },
            PLIC: PLIC {
                _marker: PhantomData,
            },
            MCHTMR: MCHTMR {
                _marker: PhantomData,
            },
            PLICSW: PLICSW {
                _marker: PhantomData,
            },
            GPTMR0: GPTMR0 {
                _marker: PhantomData,
            },
            GPTMR1: GPTMR1 {
                _marker: PhantomData,
            },
            GPTMR2: GPTMR2 {
                _marker: PhantomData,
            },
            GPTMR3: GPTMR3 {
                _marker: PhantomData,
            },
            PTMR: PTMR {
                _marker: PhantomData,
            },
            LIN0: LIN0 {
                _marker: PhantomData,
            },
            LIN1: LIN1 {
                _marker: PhantomData,
            },
            LIN2: LIN2 {
                _marker: PhantomData,
            },
            LIN3: LIN3 {
                _marker: PhantomData,
            },
            UART0: UART0 {
                _marker: PhantomData,
            },
            UART1: UART1 {
                _marker: PhantomData,
            },
            UART2: UART2 {
                _marker: PhantomData,
            },
            UART3: UART3 {
                _marker: PhantomData,
            },
            UART4: UART4 {
                _marker: PhantomData,
            },
            UART5: UART5 {
                _marker: PhantomData,
            },
            UART6: UART6 {
                _marker: PhantomData,
            },
            UART7: UART7 {
                _marker: PhantomData,
            },
            PUART: PUART {
                _marker: PhantomData,
            },
            I2C0: I2C0 {
                _marker: PhantomData,
            },
            I2C1: I2C1 {
                _marker: PhantomData,
            },
            I2C2: I2C2 {
                _marker: PhantomData,
            },
            I2C3: I2C3 {
                _marker: PhantomData,
            },
            SPI0: SPI0 {
                _marker: PhantomData,
            },
            SPI1: SPI1 {
                _marker: PhantomData,
            },
            SPI2: SPI2 {
                _marker: PhantomData,
            },
            SPI3: SPI3 {
                _marker: PhantomData,
            },
            CRC: CRC {
                _marker: PhantomData,
            },
            TSNS: TSNS {
                _marker: PhantomData,
            },
            MBX0A: MBX0A {
                _marker: PhantomData,
            },
            MBX0B: MBX0B {
                _marker: PhantomData,
            },
            WDG0: WDG0 {
                _marker: PhantomData,
            },
            WDG1: WDG1 {
                _marker: PhantomData,
            },
            PWDG: PWDG {
                _marker: PhantomData,
            },
            DMAMUX: DMAMUX {
                _marker: PhantomData,
            },
            HDMA: HDMA {
                _marker: PhantomData,
            },
            GPIOM: GPIOM {
                _marker: PhantomData,
            },
            MCAN0: MCAN0 {
                _marker: PhantomData,
            },
            MCAN1: MCAN1 {
                _marker: PhantomData,
            },
            MCAN2: MCAN2 {
                _marker: PhantomData,
            },
            MCAN3: MCAN3 {
                _marker: PhantomData,
            },
            PTPC: PTPC {
                _marker: PhantomData,
            },
            QEI0: QEI0 {
                _marker: PhantomData,
            },
            QEI1: QEI1 {
                _marker: PhantomData,
            },
            QEO0: QEO0 {
                _marker: PhantomData,
            },
            QEO1: QEO1 {
                _marker: PhantomData,
            },
            MMC0: MMC0 {
                _marker: PhantomData,
            },
            MMC1: MMC1 {
                _marker: PhantomData,
            },
            PWM0: PWM0 {
                _marker: PhantomData,
            },
            PWM1: PWM1 {
                _marker: PhantomData,
            },
            RDC: RDC {
                _marker: PhantomData,
            },
            PLB: PLB {
                _marker: PhantomData,
            },
            SYNT: SYNT {
                _marker: PhantomData,
            },
            SEI: SEI {
                _marker: PhantomData,
            },
            TRGM0: TRGM0 {
                _marker: PhantomData,
            },
            USB0: USB0 {
                _marker: PhantomData,
            },
            SDP: SDP {
                _marker: PhantomData,
            },
            SEC: SEC {
                _marker: PhantomData,
            },
            MON: MON {
                _marker: PhantomData,
            },
            RNG: RNG {
                _marker: PhantomData,
            },
            OTP: OTP {
                _marker: PhantomData,
            },
            KEYM: KEYM {
                _marker: PhantomData,
            },
            ADC0: ADC0 {
                _marker: PhantomData,
            },
            ADC1: ADC1 {
                _marker: PhantomData,
            },
            DAC0: DAC0 {
                _marker: PhantomData,
            },
            DAC1: DAC1 {
                _marker: PhantomData,
            },
            OPAMP0: OPAMP0 {
                _marker: PhantomData,
            },
            OPAMP1: OPAMP1 {
                _marker: PhantomData,
            },
            ACMP: ACMP {
                _marker: PhantomData,
            },
            SYSCTL: SYSCTL {
                _marker: PhantomData,
            },
            IOC: IOC {
                _marker: PhantomData,
            },
            PIOC: PIOC {
                _marker: PhantomData,
            },
            PLLCTLV2: PLLCTLV2 {
                _marker: PhantomData,
            },
            PPOR: PPOR {
                _marker: PhantomData,
            },
            PCFG: PCFG {
                _marker: PhantomData,
            },
            PGPR0: PGPR0 {
                _marker: PhantomData,
            },
            PGPR1: PGPR1 {
                _marker: PhantomData,
            },
            PDGO: PDGO {
                _marker: PhantomData,
            },
        }
    }
}