# This is a config file for the Sail generated from ARM-ASL

pc = "_PC"

ifetch = "Read_ifetch"

read_exclusives = ["Read_exclusive", "Read_exclusive_acquire"]
write_exclusives = ["Write_exclusive", "Write_exclusive_release"]

# The assembler is used for assembling the code in litmus tests. We
# assume it takes arguments like GNU as.
assembler = "aarch64-linux-gnu-as -march=armv8.1-a"
objdump = "aarch64-linux-gnu-objdump"
linker = "aarch64-linux-gnu-ld"

[mmu]
page_table_base = "0x300000"

# This section contains the base address for loading the code for each
# thread in a litmus test, and the stride which is the distance
# between each thread in bytes. The overall range for thread memory is
# the half-open range [base,top)"
[threads]
base = "0x400000"
top = "0x500000"
stride = "0x1000"

# If we want to give symbolic addresses concrete values, then we start
# with a base address and increment by stride for each new symbolic
# address.
[symbolic_addrs]
base = "0x600000"
stride = "0x10"

[registers]
ignore = [
  "SEE",
  "__unconditional",
  "__trickbox_enabled",
  "__v81_implemented",
  "__v82_implemented",
  "__v83_implemented",
  "__v84_implemented",
  "__v85_implemented"
]

[registers.defaults]
"VBAR_EL1" = "0x0000000000000000"
"VBAR_EL2" = "0x0000000000000000"
# Bit 1 being set causes us to abort on unaligned accesses
# Bit 26 being set allows cache-maintenance ops in EL0
"SCTLR_EL1" = "0x0000000004000002"
# Causes CNTCV to be incremented every cycle if bit 0 is 1
"CNTCR" = "0x00000001"
# SSAdvance?
"MDSCR_EL1" = "0x00000000"
"InGuardedPage" = false
"__currentInstrLength" = 4
"_PendingPhysicalSE" = false
"__CNTControlBase" = "0x0000000000000"
"HCR_EL2" = "0x0000000000000000"
"TCR_EL1" = "0x0000000000000000"
"TCR_EL2" = "0x0000000000000000"
"TCR_EL3" = "0x00000000"
"TLBHits" = 0
"TLBMisses" = 0
"CFG_RMR_AA64" = "0b1"
"CFG_RVBAR" = "0x0000000010300000"
"CFG_ID_AA64PFR0_EL1_MPAM" = "0x1"
"CFG_ID_AA64PFR0_EL1_EL3" = "0x2"
"CFG_ID_AA64PFR0_EL1_EL2" = "0x2"
"CFG_ID_AA64PFR0_EL1_EL1" = "0x2"
"CFG_ID_AA64PFR0_EL1_EL0" = "0x2"
# Need to investigate BTI extension. Guard pages cause problems with
# memory accesses.
"__v81_implemented" = true
"__v82_implemented" = false
"__v83_implemented" = false
"__v84_implemented" = false
"__v85_implemented" = false
"__unpred_tsize_aborts" = true
# Trickbox has various features for debugging spec and running tests
"__trickbox_enabled" = false
"__tlb_enabled" = false
"__syncAbortOnTTWNonCache" = true
"__syncAbortOnTTWCache" = true
"__syncAbortOnSoWrite" = true
"__syncAbortOnSoRead" = true
"__syncAbortOnReadNormNonCache" = true
"__syncAbortOnReadNormCache" = true
"__syncAbortOnPrefetch" = true
"__syncAbortOnDeviceRead" = true
"__support_52bit_pa" = true
"__mte_implemented" = false
"__mpam_has_hcr" = true
"__vmid16_implemented" = true
"__pan_implemented" = true
"__fp16_implemented" = true
"__dot_product_implemented" = true
"__crc32_implemented" = true
"__aa32_hpd_implemented" = true
"__crypto_aes_implemented" = 2
"__crypto_sha256_implemented" = true
"__crypto_sha1_implemented" = true
"__syncAbortOnWriteNormNonCache" = false
"__syncAbortOnWriteNormCache" = false
"__syncAbortOnDeviceWrite" = false
"__mpam_implemented" = false
"__crypto_sm4_implemented" = false
"__crypto_sm3_implemented" = false
"__crypto_sha512_implemented" = false
"__crypto_sha3_implemented" = false

# A map from register names that may appear in litmus files to Sail
# register names
[registers.renames]
"X0" = "R0"
"X1" = "R1"
"X2" = "R2"
"X3" = "R3"
"X4" = "R4"
"X5" = "R5"
"X6" = "R6"
"X7" = "R7"
"X8" = "R8"
"X9" = "R9"
"X10" = "R10"
"X11" = "R11"
"X12" = "R12"
"X13" = "R13"
"X14" = "R14"
"X15" = "R15"
"X16" = "R16"
"X17" = "R17"
"X18" = "R18"
"X19" = "R19"
"X20" = "R20"
"X21" = "R21"
"X22" = "R22"
"X23" = "R23"
"X24" = "R24"
"X25" = "R25"
"X26" = "R26"
"X27" = "R27"
"X28" = "R28"
"X29" = "R29"
"X30" = "R30"
"W0" = "R0"
"W1" = "R1"
"W2" = "R2"
"W3" = "R3"
"W4" = "R4"
"W5" = "R5"
"W6" = "R6"
"W7" = "R7"
"W8" = "R8"
"W9" = "R9"
"W10" = "R10"
"W11" = "R11"
"W12" = "R12"
"W13" = "R13"
"W14" = "R14"
"W15" = "R15"
"W16" = "R16"
"W17" = "R17"
"W18" = "R18"
"W19" = "R19"
"W20" = "R20"
"W21" = "R21"
"W22" = "R22"
"W23" = "R23"
"W24" = "R24"
"W25" = "R25"
"W26" = "R26"
"W27" = "R27"
"W28" = "R28"
"W29" = "R29"
"W30" = "R30"

[reads]
Read_acquire = "A"
Read_exclusive_acquire = "A"

[writes]
Write_release = "L"
Write_exclusive_release = "L"

[cache_ops]
Cache_op_D_CVAU = "DC"
Cache_op_I_IVAU = "IC"
Cache_op_I_IALLU = "IC"

# A mapping from Sail barrier_kinds for the spec to the names in cat
# memory models.
[barriers]
Barrier_DMB_SY = "DMB.SY"
Barrier_DMB_ST = "DMB.ST"
Barrier_DMB_LD = "DMB.LD"
Barrier_DMB_ISH = "DMB.ISH"
Barrier_DMB_ISHST = "DMB.ISHST"
Barrier_DMB_ISHLD = "DMB.ISHLD"
Barrier_DMB_NSH = "DMB.NSH"
Barrier_DMB_NSHST = "DMB.NSHST"
Barrier_DMB_NSHLD = "DMB.NSHLD"
Barrier_DMB_OSH = "DMB.OSH"
Barrier_DMB_OSHST = "DMB.OSHST"
Barrier_DMB_OSHLD = "DMB.OSHLD"
Barrier_DSB_SY = "DSB.SY"
Barrier_DSB_ST = "DSB.ST"
Barrier_DSB_LD = "DSB.LD"
Barrier_DSB_ISH = "DSB.ISH"
Barrier_DSB_ISHST = "DSB.ISHST"
Barrier_DSB_ISHLD = "DSB.ISHLD"
Barrier_DSB_NSH = "DSB.NSH"
Barrier_DSB_NSHST = "DSB.NSHST"
Barrier_DSB_NSHLD = "DSB.NSHLD"
Barrier_DSB_OSH = "DSB.OSH"
Barrier_DSB_OSHST = "DSB.OSHST"
Barrier_DSB_OSHLD = "DSB.OSHLD"
Barrier_ISB = "ISB"