IWRL6432 1.0 IWRL6432 Radar CM4 1.0 other true true 3 false 8 32 32 read-write 0x00000000 0xFFFFFFFF GPADC_CTRL 0x50F7FC00 0 92 registers GPADC_CTRL REG0 0x0 32 gpadc modes and enable NU3 [31:17] TI reserved 15 17 GPADC_DEBUG_MODE_ENABLE [16:16] 1:GPADC raw samples will be collected in the Output RAM in IFM mode 1 16 NU2 [15:12] TI reserved 4 12 GPADC2ADCBUF_PATH_EN [11:9] TI reserved 3 9 GPADC_FSM_CLK_ENABLE [8:8] Enable the clock to gpadc fsm 1 8 NU1 [7:2] TI reserved 6 2 DCBIST_MODE [1:0] 0:Disable,1:IFM Mode enable ,2:CTM mode enable 2 0 0 REG1 0x4 32 gpadc start trigger for Inter frame mode NU4 [31:25] TI reserved 7 25 GPADC_START_BYP_VAL 1 24 NU3 [23:17] TI reserved 7 17 GPADC_FSM_BYPASS [16:16] 1:Bypass gpadc control .When bypassed start = gpadc_start_byp_val config_val = config_value_ifm param_val = param_val_ifm 1 16 NU2 [15:9] TI reserved 7 9 GPADC_INIT [8:8] Resets the FSM and clears the data RAM 1 8 NU1 [7:1] TI reserved 7 1 GPADC_TRIGGER [0:0] Generates a single cycle pulse to trigger the IFM mode 1 0 0 REG2 0x8 32 gpadc config for IFM CONFIG_VALUE_IFM [31:0] Configuration value to be passed to analog in IFM mode 32 0 0 REG3 0xC 32 gpadc param, skip samples and collect samples for IFM NU 9 23 SKIP_SAMPLES_IFM [22:16] number of GPADC clocks to skip after trigger . Number of samples to skip = skip_samples_ifm[3:0]x(2skip_samples_ifm[6:4]) 7 16 COLLECT_SAMPLES_IFM [15:8] number of GPADC readings to collect 8 8 PARAM_VAL_IFM [7:0] Param value to be passed to analog in IFM mode(after one hot encoding) 8 0 0 REG4 0x10 32 Base address for Chirp profile 0 in instruction packet RAM PKT_RAM_BASE_ADDR_CP3 [31:24] TI reserved 8 24 PKT_RAM_BASE_ADDR_CP2 [23:16] TI reserved 8 16 PKT_RAM_BASE_ADDR_CP1 [15:8] (End-Address + 1) of instruction-ram in CTM mode 8 8 PKT_RAM_BASE_ADDR_CP0 [7:0] Start Address of instruction-ram in CTM mode 8 0 0 REG5 0x14 32 Base address for Chirp profile 1 in instruction packet RAM PKT_RAM_BASE_ADDR_CP7 [31:24] TI reserved 8 24 PKT_RAM_BASE_ADDR_CP6 [23:16] TI reserved 8 16 PKT_RAM_BASE_ADDR_CP5 [15:8] TI reserved 8 8 PKT_RAM_BASE_ADDR_CP4 [7:0] TI reserved 8 0 0 REG6 0x18 32 Base address for Chirp profile 2 in instruction packet RAM PKT_RAM_BASE_ADDR_CP11 [31:24] TI reserved 8 24 PKT_RAM_BASE_ADDR_CP10 [23:16] TI reserved 8 16 PKT_RAM_BASE_ADDR_CP9 [15:8] TI reserved 8 8 PKT_RAM_BASE_ADDR_CP8 [7:0] TI reserved 8 0 0 REG7 0x1C 32 Base address for Chirp profile 3 in instruction packet RAM PKT_RAM_BASE_ADDR_CP15 [31:24] TI reserved 8 24 PKT_RAM_BASE_ADDR_CP14 [23:16] TI reserved 8 16 PKT_RAM_BASE_ADDR_CP13 [15:8] TI reserved 8 8 PKT_RAM_BASE_ADDR_CP12 [7:0] TI reserved 8 0 0 REG8 0x20 32 REG8 NU 23 9 GPADC_CLK_ENABLE [8:8] TI reserved 1 8 GPADC_CLK_DIV [7:0] TI reserved 8 0 0 REG9 0x24 32 REG9 PARAM_NOT_USED_TX_ENA1_OFF [31:0] TI reserved 32 0 0 REG10 0x28 32 REG10 PARAM_NOT_USED_TX_ENA2_OFF [31:0] TI reserved 32 0 0 REG11 0x2C 32 REG11 PARAM_NOT_USED_TX_ENA3_OFF [31:0] TI reserved 32 0 0 REG12 0x30 32 REG12 DRAM_REPAIRED_BIT [31:24] TI reserved 8 24 DRAM_ECC_ERR_ADDR [23:16] TI reserved 8 16 NU2 [15:9] TI reserved 7 9 DRAM_ECC_ERR_CLR [8:8] TI reserved 1 8 NU1 [7:1] TI reserved 7 1 DRAM_ECC_ENABLE 1 0 0 REG13 0x34 32 REG13 SPARE_WR2 [31:0] TI reserved 32 0 0 REG14 0x38 32 Sum of GP ADC readings NU [31:20] TI reserved 12 20 SUM_IFM [19:0] Sum of GP ADC readings 20 0 0 REG15 0x3C 32 Min and Max of GP ADC readings NU2 [31:26] TI reserved 6 26 MAX_GPADC [25:16] Max of GPADC readings 10 16 NU1 [15:10] TI reserved 6 10 MIN_GPADC [9:0] Min of GPADC readings 10 0 0 REG16 0x40 32 REG16 NU [31:1] TI reserved 31 1 GPADC_MEM_INIT_DONE_STAT [0:0] Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress 1 0 0 REG17 0x44 32 REG17 NU [31:1] TI reserved 31 1 GPADC_IFM_DONE_STATUS [0:0] Test completion status in IFM mode.Used for FW polling 1 0 0 REG18 0x48 32 REG18 NU [31:1] TI reserved 31 1 GPADC_IFM_DONE_CLR [0:0] Clear "ifm_done_status" 1 0 0 REG19 0x4C 32 REG19 NU [31:16] TI reserved 16 16 GPADC_SAMPLES_FRAME [15:0] Total number of GPADC samples collected in a frame 16 0 0 REG20 0x50 32 REG20 SPARE_RD1 [31:0] TI reserved 32 0 0 REG21 0x54 32 REG21 SPARE_RD2 [31:0] TI reserved 32 0 0 REG22 0x58 32 REG22 SPARE_WR1 [31:0] TI reserved 32 0 0 APP_LIN 0x53000000 0 148 registers APP_LIN SCIGCR0 0x0 32 The SCIGCR0 register defines the module reset. Reserved1 [31:16] Reserved 16 16 Reserved [15:1] Reserved 15 1 RESET [0:0] This bit resets the SCI/LIN module. This bit is effective in LIN or SCI-compatible mode.. This bit affects the reset state of the SCI/LIN module. Writable Only in privilege mode 1 0 0 SCIGCR1 0x4 32 The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI. Reserved2 [31:26] Reserved 6 26 TXENA [25:25] Transmit enable. This bit is effective in LIN and SCI modes. Data is transferred from SCITD or the TDy (with y=0, 1,...7) buffers in LIN mode to the SCITXSHF shift out register only when the TXENA bit is set. Note: Data written to SCITD or the transmit multi-buffer before TXENA is set is not transmitted. If TXENA is cleared while transmission is ongoing, the data previously written to SCITD is sent (including the checksum byte in LIN mode). 1 25 RXENA [24:24] Receive enable. This bit is effective in LIN or SCI-compatible mode. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD or the receive multibuffers. Note: Clearing RXENA stops received characters from being transferred into the receive buffer or multi-buffers, prevents the RX status flags (see Table 7) from being updated by receive data, and inhibits both receive and error interrupts. However, the shift register continues to assemble data regardless of the state of RXENA. Note: If RXENA is cleared before the time the reception of a frame is complete, the data from the frame is not transferred into the receive buffer. Note: If RXENA is set before the time the reception of a frame is complete, the data from the frame is transferred into the receive buffer. If RXENA is set while SCIRXSHF is in the process of assembling a frame, the status flags are not guaranteed to be accurate for that frame. To ensure that the status flags correctly reflect what was detected on the bus during a particular frame, RXENA should be set before the detection of that frame 1 24 Reserved1 [23:18] Reserved 6 18 CONT [17:17] Continue on suspend. This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI/LIN operates when the program is suspended. This bit affects the LIN counters. When this bit is set, the counters are not stopped during debug. When this bit is cleared, the counters are stopped during debug. 1 17 LOOPBACK [16:16] Loopback bit. This bit is effective in LIN or SCI-compatible mode. The self-checking option for the SCI/LIN can be selected with this bit. If the LINTX and LINRX pins are configured with SCI/LIN functionality, then the LINTX pin is internally connected to the LINRX pin. Externally, during loop back operation, the LINTX pin outputs a high value and the LINRX pin is in a high-impedance state. If this bit value is changed while the SCI/LIN is transmitting or receiving data, errors may result. 1 16 Reserved [15:14] Reserved 2 14 STOPEXTFRAME [13:13] Stop extended frame communication. This bit is effective in LIN mode only. This bit can be written only during extended frame communication. When the extended frame communication is stopped, this bit is cleared automatically. 1 13 HGENCTRL [12:12] HGEN control bit. This bit is effective in LIN mode only. This bit controls the type of mask filtering comparison. 1 12 CTYPE [11:11] Checksum type. This bit is effective in LIN mode only. This bit controls the type of checksum to be used: classic or enhanced. 1 11 MBUFMODE [10:10] Multibuffer mode. This bit is effective in LIN or SCI-compatible mode. This bit controls receive/transmit buffer usage, that is, whether the RX/TX multibuffers are used or a single register, RD0/TD0, is used. 1 10 ADAPT [9:9] Adapt mode enable. This mode is effective in LIN mode only. This bit has an effect during the detection of the Sync Field. There are two LIN protocol bit rate modes that could be enabled with this bit according to the Node capability file definition: automatic or select. Software and network configuration will decide which of the previous two modes. When this bit is cleared, the LIN 2.0 protocol fixed bit rate should be used. If the ADAPT bit is set, a LIN slave node detecting the baudrate will compare it to the prescalers in BRSR register and update it if they are different. The BRSR register will be updated with the new value. If this bit is not set there will be no adjustment to the BRSR register. This field is writable in LIN mode only. 1 9 SLEEP [8:8] SCI sleep. SCI compatibility mode only. In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode. The receiver still operates when the SLEEP bit is set; however, RXRDY is updated and SCIRD is loaded with new data only when an address frame is detected. The remaining receiver status flags are updated and an error interrupt is requested if the corresponding interrupt enable bit is set, regardless of the value of the SLEEP bit. In this way, if an error is detected on the receive data line while the SCI is asleep, software can promptly deal with the error condition. The SLEEP bit is not automatically cleared when an address byte is detected. This field is writable in SCI mode only. 1 8 SWnRST [7:7] Software reset (active low). This bit is effective in LIN or SCI-compatible mode. The SCI/LIN should only be configured while SWnRST = 0. Only the following configuration bits can be changed in runtime (i.e., while SWnRESET = 1): - STOP EXT Frame (SCIGCR1[13]) - CC bit (SCIGCR2[17]) - SC bit (SCIGCR2[16]) 1 7 LINMODE [6:6] LIN mode This bit controls the mode of operation of the module. Writable Only in privilege mode 1 6 CLK_MASTER [5:5] SCI internal clock enable or LIN Master/Slave configuration. In the SCI mode, this bit enables the clock to the SCI module. In LIN mode, this bit determines whether a LIN node is a slave or master. 1 5 STOP [4:4] SCI number of stop bits. This bit is effective in SCI-compatible mode only. Note: The receiver checks for only one stop bit. However in idle-line mode, the receiver waits until the end of the second stop bit (if STOP = 1) to begin checking for an idle period. This field is writable in SCI mode only. 1 4 PARITY [3:3] SCI parity odd/even selection. This bit is effective in SCI-compatible mode only. If the PARITY ENA bit (SCIGCR1.2) is set, PARITY designates odd or even parity. The parity bit is calculated based on the data bits in each frame and the address bit (in address-bit mode). The start and stop fields in the frame are not included in the parity calculation. This field is writable in SCI mode only. 1 3 PARITYENA [2:2] Parity enable. Enables or disables the parity function. 1 2 TIMINGMODE [1:1] SCI timing mode bit. This bit is effective in SCI-compatible mode only. It must be set to 1 when the SCI mode is used. This bit configures the SCI for asynchronous operation. 1 1 COMMMODE [0:0] SCI/LIN communication mode bit. In compatibility mode, it selects the SCI communication mode. In LIN mode it selects length control option for ID-field bits ID4 and ID5. 1 0 0 SCIGCR2 0x8 32 The SCIGCR2 register is used to send or compare a checksum byte during extended frames, to generate a wakeup and for low-power mode control of the LIN module. Reserved2 [31:18] Reserved 14 18 CC [17:17] Compare Checksum. This mode is effective in LIN mode only. This bit is used by the receiver for extended frames to trigger a checksum compare. The user will initiate this transaction by writing a one to this bit. In non multibuffer mode, once the CC bit is set, the checksum will be compared on the byte that is currently being received, expected to be the checkbyte. During Multi-buffer mode, following are the scenarios associated with the CC bit : - If CC bit is set during the reception of the data, then the byte that is received after the reception of the programmed no. of data bytes indicated by SCIFORMAT[18:16], is treated as a checksum byte. - If CC bit is set during the IDLE period (i.e. during inter-frame space), then the next immediate byte will be treated as a checksum byte. A CE will immediatly be flagged if there is a checksum error. This bit is automatically cleared once the checksum is successfully compared. 1 17 SC [16:16] Send Checksum This mode is effective in LIN mode only. This bit is used by the transmitter with extended frames to send a checkbyte. In non multibuffer mode the checkbyte will be sent after the current byte transmission. In multibuffer mode the checkbyte will be sent after the last byte count, indicated by the SCIFORMAT[18:16]). This field is writable in LIN mode only. 1 16 Reserved1 [15:9] Reserved 7 9 GENWU [8:8] Generate wakeup signal. This bit controls the generation of a wakeup signal, by transmitting the TDO buffer value. This bit is cleared on reception of a valid sync break. 1 8 Reserved [7:1] Reserved 7 1 POWERDOWN [0:0] Power down. This bit is effective in LIN or SCI-compatible mode. When the powerdown bit is set, the SCI/LIN module attempts to enter local low-power mode. If the POWERDOWN bit is set while the receiver is actively receiving data and the wakeup interrupt is disabled, then the SCI/LIN will delay low-power mode from being entered until completion of reception. In LIN mode the user may set the POWERDOWN bit on Sleep Command reception or on idle bus detection (more than 4 seconds, i.e. 80,000 cycles at 20kHz) 1 0 0 SCISETINT 0xC 32 The SCISETINT register is used to enable the various interrupts available in the LIN module. SETBEINT [31:31] Set bit error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a bit error. This field is writable in LIN mode only. 1 31 SETPBEINT [30:30] Set physical bus error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a physical bus error occurs. This field is writable in LIN mode only. 1 30 SETCEINT [29:29] Set checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is a checksum error. This field is writable in LIN mode only. 1 29 SETISFEINT [28:28] Set inconsistent-sync-field-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when there is an inconsistent sync field error. This field is writable in LIN mode only. 1 28 SETNREINT [27:27] Set no-response-error interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN module to generate an interrupt when a no-response error occurs. This field is writable in LIN mode only. 1 27 SETFEINT [26:26] Set framing-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a framing error occurs. 1 26 SETOEINT [25:25] Set overrun-error interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when an overrun error occurs. 1 25 SETPEINT [24:24] Set parity interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN module to generate an interrupt when a parity error occurs. 1 24 Reserved4 [23:19] Reserved 5 19 SET_RX_DMA_ALL [18:18] Set receiver DMA for Address & Data frames. This bit is effective in LIN or SCI-compatible mode. To enable RX DMA request for address and data frames this bit must be set. If it is cleared, RX interrupt request is generated for address frames and DMA requests are generated for data frames. 1 18 SET_RX_DMA [17:17] Set receiver DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the receiver this bit must be set. If it is cleared, interrupt requests are generated depending on SETRXINT. 1 17 SET_TX_DMA [16:16] Set transmit DMA. This bit is effective in LIN or SCI-compatible mode. To enable DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SETTXINT. 1 16 Reserved3 [15:14] Reserved 2 14 SETIDINT [13:13] Set Identification interrupt. This bit is effective in LIN mode only. This bit is set to enable interrupt once a valid matching identifier is received. 1 13 Reserved2 [12:10] Reserved 3 10 SETRXINT [9:9] Set Receiver interrupt. Setting this bit enables the SCI/LIN to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. 1 9 SETTXINT [8:8] Set Transmitter interrupt. Setting this bit enables the SCI/LIN to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. 1 8 SETTOA3WUSINT [7:7] Set Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after 3 wakeup signals have been sent. This field is writable in LIN mode only. 1 7 SETTOAWUSINT [6:6] Set Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when there is a timeout after one wakeup signal has been sent. This field is writable in LIN mode only. 1 6 Reserved1 [5:5] Reserved 1 5 SETTIMEOUTINT [4:4] Set timeout interrupt. This bit is effective in LIN mode only. Setting this bit enables the SCI/LIN to generate an interrupt when no LIN bus activity (bus idle) occurs for at least 4 seconds. This field is writable in LIN mode only. 1 4 Reserved [3:2] Reserved 2 2 SETWAKEUPINT [1:1] Set wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit enables the SCI/LIN to generate a wake-up interrupt and thereby exit low-power mode. The wake-up interrupt is asserted on falling edge of the wake-up pulse. If enabled, the wake-up interrupt is asserted when local low-power mode is requested while the receiver is busy or if a low level is detected on the SCIRX pin during low-power mode. Wake-up interrupt is not asserted upon a wakeup pulse if the module is not in power down mode. 1 1 SETBRKDTINT [0:0] Set break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit enables the SCI/LIN to generate an interrupt if a break condition is detected on the LINRX pin. This field is writable in SCI mode only. 1 0 0 SCICLEARINT 0x10 32 The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register. CLRBEINT [31:31] Clear Bit Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only. 1 31 CLRPBEINT [30:30] Clear Physical Bus Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only. 1 30 CLRCEINT [29:29] Clear checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only. 1 29 CLRISFEINT [28:28] Clear Inconsistent-Sync-Field-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only. 1 28 CLRNREINT [27:27] Clear No-Reponse-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only. 1 27 CLRFEINT [26:26] Clear Framing-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt. 1 26 CLROEINT [25:25] Clear Overrun-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt. 1 25 CLRPEINT [24:24] Clear Parity Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt. 1 24 Reserved5 [23:19] Reserved 5 19 Reserved4 [18:18] Reserved 1 18 CLRRXDMA [17:17] Clear receiver DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request. 1 17 CLRTXDMA [16:16] Clear transmit DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request. 1 16 Reserved3 [15:14] Reserved 2 14 CLRIDINT [13:13] Clear Identifier interrupt. This bit is effective in LIN mode only. Setting this bit disables the ID interrupt. 1 13 Reserved2 [12:10] Reserved 3 10 CLRRXINT [9:9] Clear Receiver interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt. 1 9 CLRTXINT [8:8] Clear Transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt. 1 8 CLRTOA3WUSINT [7:7] Clear Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only. 1 7 CLRTOAWUSINT [6:6] Clear Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only. 1 6 Reserved1 [5:5] Reserved 1 5 CLRTIMEOUTINT [4:4] Clear Timeout interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout (LIN bus idle) interrupt. This field is writable in LIN mode only. 1 4 Reserved [3:2] Reserved 2 2 CLRWAKEUPINT [1:1] Clear Wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt. 1 1 CLRBRKDTINT [0:0] Clear Break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only. 1 0 0 SCISETINTLVL 0x14 32 The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line. SETBEINTLVL [31:31] Set Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 31 SETPBEINTLVL [30:30] Set Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 30 SETCEINTLVL [29:29] Set Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 29 SETISFEINTLVL [28:28] Set Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 28 SETNREINTLVL [27:27] Set No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 27 SETFEINTLVL [26:26] Set Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line. 1 26 SETOEINTLVL [25:25] Set Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line. 1 25 SETPEINTLVL [24:24] Set Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line. 1 24 Reserved6 [23:19] Reserved 5 19 Reserved5 [18:18] Reserved 1 18 Reserved4 [17:16] Reserved 2 16 Reserved3 [15:14] Reserved 2 14 SETIDINTLVL [13:13] Set ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only. 1 13 Reserved2 [12:10] Reserved 3 10 SETRXINTOVO [9:9] Set Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line. 1 9 SETTXINTLVL [8:8] Set Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line. 1 8 SETTOA3WUSINTLVL [7:7] Set Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only. 1 7 SETTOAWUSINTLVL [6:6] Set Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only. 1 6 Reserved1 [5:5] Reserved 1 5 SETTIMEOUTINTLVL [4:4] Set Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only. 1 4 Reserved [3:2] Reserved 2 2 SETWAKEUPINTLVL [1:1] Set Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line. 1 1 SETBRKDTINTLVL [0:0] Set Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only. 1 0 0 SCICLEARINTLVL 0x18 32 The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line. CLRBEINTLVL [31:31] Clear Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 31 CLRPBEINTLVL [30:30] Clear Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 30 CLRCEINTLVL [29:29] Clear Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 29 CLRISFEINTLVL [28:28] Clear Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 28 CLRNREINTLVL [27:27] Clear No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 27 CLRFEINTLVL [26:26] Clear Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line. 1 26 CLROEINTLVL [25:25] Clear Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line. 1 25 CLRPEINTLVL [24:24] Clear Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line. 1 24 Reserved6 [23:19] Reserved 5 19 Reserved5 [18:18] Reserved 1 18 Reserved4 [17:16] Reserved 2 16 Reserved3 [15:14] Reserved 2 14 CLRIDINTLVL [13:13] Clear ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only. 1 13 Reserved2 [12:10] Reserved 3 10 CLRRXINTLVL [9:9] Clear Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line. 1 9 CLRTXINTLVL [8:8] Clear Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line. 1 8 CLRTOA3WUSINTLVL [7:7] Clear Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only. 1 7 CLRTOAWUSINTLVL [6:6] Clear Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only. 1 6 Reserved1 [5:5] Reserved 1 5 CLRTIMEOUTINTLVL [4:4] Clear Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only. 1 4 Reserved [3:2] Reserved 2 2 CLRWAKEUPINTLVL [1:1] Clear Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line. 1 1 CLRBRKDTINTLVL [0:0] Clear Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only. 1 0 0 SCIFLR 0x1C 32 The SCIFLR register indicates the current status of the various interrupt sources of the LIN module. BE [31:31] Bit Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a bit error. This is detected by the bit monitor in the internal bit monitor. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 31 PBE [30:30] Physical Bus Error Flag. This bit is effective in LIN mode only. This bit is set when there has been a physical bus error. This is detected by the bit monitor in TED. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break Note: thie PBE will ony be flagged if no sync break can be generated. (because of a bus shortage to VBAT) or if no sync break delimeter can be generated (because of a bus shortage to GND). This field is writable in LIN mode only. 1 30 CE [29:29] Checksum Error Flag. This bit is effective in LIN mode only. This bit is set when there is checksum error detected by a receiving node. The type of checksum to be used depends on the SCIGCR1.CTYPE bit. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 29 ISFE [28:28] Inconsistent Sync Field Error Flag. This bit is effective in LIN mode only. This bit is set when there has been an inconsistent Sync Field error detected by the synchronizer during header reception. See the "Header Reception and Adaptive Baudrate" section for more information. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 28 NRE [27:27] No-Response Error Flag. This bit is effective in LIN mode only. This bit is set when there is no response to a master’s header completed within TFRAME_MAX. This timeout period is applied for message frames of unknown length (identifiers 0 to 61). This error is detected by the synchronizer of the module. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new sync break This field is writable in LIN mode only. 1 27 FE [26:26] Framing error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when an expected stop bit is not found. In SCI compatible mode, only the first stop bit is checked. The missing stop bit indicates that synchronization with the start bit has been lost and that the character is incorrectly framed. Detection of a framing error causes the SCI to generate an error interrupt if the RXERR INT ENA bit is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit - Reception of a new character (SCI-compatible mode), or frame (LIN mode) In multibuffer mode the frame is defined in the SCIFORMAT register. 1 26 OE [25:25] Overrun error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD or the RDy buffers. Detection of an overrun error causes the LIN to generate an error interrupt if the SET OE INT bit is one. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit 1 25 PE [24:24] Parity error flag. This bit is effective in LIN or SCI-compatible mode. This bit is set when a parity error is detected in the received data. In SCI address-bit mode, the parity is calculated on the data and address bit fields of the received frame. In idle-line mode, only the data is used to calculate parity. An error is generated when a character is received with a mismatch between the number of 1s and its parity bit. For more information on parity checking, see the "SCI Global Control Register (SCIGCR1)" description. If the parity function is disabled (that is, SCIGCR1.2 = 0), the PE flag is disabled and read as 0. Detection of a parity error causes the LIN to generate an error interrupt if the SET PE INT bit = 1. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reception of a new charcter (SCI-compatible mode) or frame (LIN mode) - Writing a 1 to this bit 1 24 Reserved2 [23:16] reserved 8 16 Reserved1 [15:15] reserved 1 15 IDRXFLAG [14:14] Identifier On Receive Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with an RX match and no ID-parity error. See the "Message Filtering and Validation" section for more details. When this flag is set it indicates that a new valid identifier has been received on an RX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only. 1 14 IDTXFLAG [13:13] Identifier On Transmit Flag. This bit is effective in LIN mode only. This flag is set once an identifier is received with a TX match and no ID-parity error. See the "Message Filtering and Validation" section for more details. When this flag is set it indicates that a new valid identifier has been received on a TX match. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - RESET bit (SCIGCR0.0) - Setting SWnRESET - System reset - Reading the LINID register - Writing a 1 to this bit This field is writable in LIN mode only. 1 13 RXWAKE [12:12] Receiver wakeup detect flag. This bit is effective in SCI-compatible mode only. The SCI sets this bit to indicate that the data currently in SCIRD is an address. This bit is cleared by: - RESET bit - Setting the SWnRESET bit (SCIGCR1.7) - System reset - Receipt of a data frame This bit is writable in SCI mode only. 1 12 TXEMPTY [11:11] Transmitter Empty flag. The value of this flag indicates the contents of the transmitter’s buffer register(s) (SCITD/TDy) and shift register (SCITXSHF). In multibuffer mode, this flag indicates the value of the TDx registers and shift register (SCITXSHF). In non multibuffer mode, this flag indicates the value of LINTD0 (byte) and shift register (SCITXSHF). This bit is set by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET bit (SCIGCR1.7) - System reset. Note: This bit does not cause an interrupt request. 1 11 TXWAKE [10:10] SCI transmitter wakeup method select. This bit is effective in SCI-compatible mode only. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format. This bit is set to 1 or 0 by software before a byte is written to SCITD and is cleared by the SCI when data is transferred from SCITD to SCITXSHF or by a system reset. TXWAKE is not cleared by the SWnRESET bit (SCIGCR1.7). 1 10 RXRDY [9:9] Receiver ready flag. In SCI compatibility mode, the receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU. In LIN mode, RXRDY is set once a valid frame is received in multibuffer mode, a valid frame being a message frame received with no errors. In non multibuffer mode RXRDY is set for each received byte and will be set for the last byte of the frame if there are no errors. The SCI/LIN generates a receive interrupt when RXRDY flag bit is set if the interrupt-enable bit is set (SCISETINT.9). RXRDY is cleared by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET - System reset - Writing a 1 to this bit - Reading SCIRD in while in SCI compatibility mode - Reading last data byte RDy of the response in LIN mode Note: The RXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register. 1 9 TXRDY [8:8] Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer(s) register (SCITD in compatibility mode and LINTD0, LINTD1 in MBUF mode) is/are ready to get another character from a CPU write. In SCI compatibility mode, writing data to SCITD automatically clears this bit. In LIN mode, this bit is cleared once byte 0 (TD0) is written to LINTD0. This bit is set after the data of the TX buffer are shifted into the SCITXSHF register. This event can trigger a transmit DMA event if the DMA enable bit is set. This bit is set to 1 by: - RESET bit (SCIGCR0.0) - Setting the SWnRESET (SCIGCR1.7) - System reset Note: The TXRDY flag cannot be cleared by reading the corresponding interrupt offset in the SCIINTVECT0/1 register. Note: The transmit interrupt request can be eliminated until the next series of data is written into the transmit buffers LINTD0 and LINTD1, by disaLINg the corresponding interrupt via the SCICLEARINT register or by disaLINg the transmitter via the TXENA bit (SCIGCR1.25=0). 1 8 TOA3WUS [7:7] Timeout After 3 Wakeup Signals flag. This bit is effective in LIN mode only. This flag is set if there is no Sync Break received after 3 wakeup signals and a period of 1.5 seconds have passed. Such expiration time is used before issuing another round of wakeup signals. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only. 1 7 TOAWUS [6:6] Timeout After Wakeup Signal flag. This bit is effective in LIN mode only. This bit is set if there is no Sync Break received after a wakeup signal has been sent. A minimum of 150 ms expiration time is used before issuing another wakeup signal. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only. 1 6 Reserved [5:5] reserved 1 5 TIMEOUT [4:4] LIN Bus IDLE timeout flag. This bit is effective in LIN mode only. This bit is set if there is no LIN bus activity for at least 4 seconds. LIN bus activity being a transition from recessive to dominant. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit This field is writable in LIN mode only. 1 4 BUSY [3:3] Bus BUSY flag. This bit is effective in LIN mode and SCI-compatible mode. This bit indicates whether the receiver is in the process of receiving a frame. As soon as the receiver detects the beginning of a start bit, the BUSY bit is set to 1. When the reception of a frame is complete, the BUSY bit is cleared. If SET WAKEUP INT is set and power down is requested while this bit is set, the SCI/LIN automatically prevents low-power mode from being entered and generates wakeup interrupt. The BUSY bit is controlled directly by the SCI receiver but can be cleared by: - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset. 1 3 IDLE [2:2] SCI receiver in idle state. This bit is effective in SCI-compatible mode only. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. The receiver does not receive any data while the bit is set. The bus must be idle for 11 bit periods to clear this bit. The SCI enters this state: - After a system reset - Setting the SWnRESET bit (SCIGCR1.7) - After coming out of power down This bit is writable in SCI mode only. 1 2 WAKEUP [1:1] Wake-up flag. This bit is effective in LIN mode only. This bit is set by the SCI/LIN when receiver or transmitter activity has taken the module out of power-down mode. An interrupt is generated if the SET WAKEUP INT bit (SCISETINT.1) is set. This bit is cleared by: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - Writing a 1 to this bit. This field is writable in LIN mode only. 1 1 BRKDT [0:0] SCI break-detect flag. This bit is effective in SCI-compatible mode only. This bit is set when the SCI detects a break condition on the LINRX pin. A break condition occurs when the LINRX pin remains continuously low for at least 10 bits after a missing first stop bit, that is, after a framing error. Detection of a break condition causes the SCI to generate an error interrupt if the BRKDT INT ENA bit is set. The BRKDT bit is cleared by the following: - Reading the corresponding interrupt offset in the SCIINTVECT0/1 register. - Setting the SWnRESET bit (SCIGCR1.7) - RESET bit (SCIGCR0.0) - System reset - By writing a 1 to this bit. This bit is writable in SCI mode only. 1 0 0 SCIINTVECT0 0x20 32 The SCIINTVECT0 register indicates the offset for the INT0 interrupt line. Reserved1 [31:16] Reserved 16 16 Reserved [15:5] Reserved 11 5 INTVECT0 [4:0] Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register). 5 0 0 SCIINTVECT1 0x24 32 The SCIINTVECT1 register indicates the offset for the INT1 interrupt line. Reserved1 [31:16] Reserved 16 16 Reserved [15:5] Reserved 11 5 INTVECT1 [4:0] Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. A read to this register updates its value to the next highest priority pending interrupt in SCIFLR and clears the flag corresponding to the offset that was read. Note: The flags for the receive (SCIFLR.9) and the transmit (SCIFLR.8) interrupts cannot be cleared by reading the corresponding offset vector in this register (see detailed description in SCIFLR register). 5 0 0 SCIFORMAT 0x28 32 The SCIFORMAT register is used to set up the character and frame lengths. Reserved1 [31:19] Reserved 13 19 LENGTH [18:16] Frame length control bits. In LIN mode, these bits indicate the number of bytes in the response field from 1 to 8 bytes. In buffered SCI mode, these bits indicate the number of characters. When these bits are used to indicate LIN response length (SCIGCR1[0] = 1), then when there is an ID RX match, this value should be updated with the expected length of the response. In buffered SCI mode, these bits indicate the number of characters with SCIFORMAT[2:0] bits per character. i.e. these bits indicate the transmitter/receiver format for the number of characters: 1 to 8. There can be up to eight characters with eight bits each. 3 16 Reserved [15:3] Reserved 13 3 CHAR [2:0] Character length control bits. These bits are effective in SCI compatible mode only. These bits set the SCI character length from 1 to 8 bits. Note: In compatibility mode or buffered SCI mode, when data of fewer than eight bits in length is received, it is left justified in SCIRD/RDy and padded with trailing zeros. Data read from the SCIRD should be shifted by software to make the received data right justified. Note: Data written to the SCITD should be right justified but does not need to be padded with leading zeros. These bits are witable in SCI mode only. 3 0 0 BRSR 0x2C 32 The BRSR register is used to configure the baud rate of the LIN module. Reserved [31:31] Reserved 1 31 U [30:28] Superfractional Divider Selection. (U) These bits are an additional fractional part for the baudrate specification. These bits allow a super fine tuning of the fractional baudrate with 7 more intermediate values for each of the M fractional divider values. See the Superfractional Divider section for more details. 3 28 M [27:24] SCI/LIN 4-bit Fractional Divider Selection. (M) These bits are effective in LIN or SCI asynchronous mode. These bits are used to select a baud rate for the SCI/LIN module, and they are a fractional part for the baud rate specification. The M divider allows fine-tuning of the baud rate over the P prescaler with 15 additional intermediate values for each of the P integer values. 4 24 SCI_LIN_PSH [23:16] PRESCALER P (High Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection. 8 16 SCI_LIN_PSL [15:0] PRESCALER P (Low Bits). SCI/LIN 24-bit Integer Prescaler Selection. These bits are used to select a baudrate for the SCI/LIN module. These bits are effective in LIN mode and SCI compatible mode. The SCI/LIN has an internally generated serial clock determined by the LIN module input clock and the prescalers P and M in this register. The SCI/LIN uses the 24-bit integer prescaler P value to select 1 of over 16,700,000 available baud rates. The additional 4-bit fractional prescaler M refines the baudate selection. 16 0 0 SCIED 0x30 32 The SCIED register is a duplicate copy of SCIRD register that has no affect on the RXRDY flag for use with an emulator. Reserved [31:8] Reserved 24 8 ED [7:0] Receiver Emulation Data. This bit is effective in SCI-compatible mode only. Reading SCIED(7–0) does not clear the RXRDY flag. This register should be used only by an emulator that must continually read the data buffer without affecting the RXRDY flag. 8 0 0 SCIRD 0x34 32 The SCIRD register is where received data is stored and can be read from. Reserved [31:8] Reserved 24 8 RD [7:0] Received Data. This bit is effective in SCI-compatible mode only. When a frame has been completely received, the data in the frame is transferred from the receiver shift register SCIRXSHF to this register. As this transfer occurs, the RXRDY flag is set and a receive interrupt is generated if RX INT ENA (SCISETINT0.9) is set. When the data is read from SCIRD, the RXRDY flag is automatically cleared. When the SCI receives data that is fewer than eight bits in length, it loads the data into this register in a left justified format padded with trailing zeros. Therefore, your software should perform a logical shift on the data by the correct number of positions to make it right justified. 8 0 0 SCITD 0x38 32 The SCITD register is where data to be transmitted is written to by application software. Reserved [31:8] Reserved 24 8 TD [7:0] Transmit data This bit is effective in SCI-compatible mode only. Data to be transmitted is written to this register. The transfer of data from this register to the transmit shift register SCITXSHF sets the TXRDY flag (SCIFLR.23), which indicates that SCITD is ready to be loaded with another byte of data. Note: If TX INT ENA (SCISETINT.8) is set, this data transfer also causes an interrupt. Note: Data written to the SCIRD register that is fewer than eight bits long must be right justified, but it does not need to be padded with leading zeros. 8 0 0 SCIPIO0 0x3C 32 The SCIPIO0 register is used to enable the LINTX and LINRX pins. Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXFUNC [2:2] Transmit pin function. This bit is effective in LIN or SCI mode. This bit defines the function of LINTX pin. 1 2 RXFUNC [1:1] Receive pin function. This bit is effective in LIN or SCI mode. This bit defines the function of the LINRX pin. 1 1 CLKFUNC [0:0] Reserved 1 0 0 SCIPIO1 0x40 32 SCIPIO1 Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXDIR [2:2] Transmit pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINTX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin 1 2 RXDIR [1:1] Receive pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on the LINRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). 0: general purpose input pin. 1: general-purpose output pin 1 1 CLKDIR [0:0] Reserved 1 0 0 SCIPIO2 0x44 32 The SCIPIO2 register indicates the current status of the LINTX and LINRX pins. Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXIN [2:2] Transmit data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINTX pin. 1 2 RXIN [1:1] Receive data in. This bit is effective in LIN or SCI-compatible mode. This bit contains the current value on the LINRX pin. 1 1 CLKIN [0:0] Reserved 1 0 0 SCIPIO3 0x48 32 SCIPIO3 Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXOUT [2:2] Transmit pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINTX. 1 2 RXOUT [1:1] Receive pin out. This bit is effective in LIN or SCI mode. This pin specifies the logic to be output on pin LINRX. 1 1 CLKOUT [0:0] Reserved 1 0 0 SCIPIO4 0x4C 32 SCIPIO4 Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXSET [2:2] Transmit pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINTX. 1 2 RXSET [1:1] Receive pin set. This bit is effective in LIN or SCI mode. This bit sets the logic to be output on pin LINRX. 1 1 CLKSET [0:0] Reserved 1 0 0 SCIPIO5 0x50 32 SCIPIO5 Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXCLR [2:2] Transmit pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINTX. 1 2 RXCLR [1:1] Receive pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin LINRX. 1 1 CLKCLR [0:0] Reserved 1 0 0 SCIPIO6 0x54 32 SCIPIO6 Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXPDR [2:2] Transmit pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINTX. 1 2 RXPDR [1:1] Receive pin open drain enable. This bit is effective in LIN or SCI mode. This bit enables open-drain capability in the output pin LINRX. 1 1 CLKDR [0:0] Reserved 1 0 0 SCIPIO7 0x58 32 SCIPIO7 Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXPD [2:2] Transmit pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINTX. 1 2 RXPD [1:1] Receive pin pull control disable. This bit is effective in LIN or SCI mode. This bit disables pull control capability on the input pin LINRX. 1 1 CLKPD [0:0] Reserved 1 0 0 SCIPIO8 0x5C 32 SCIPIO8 Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXPSL [2:2] TX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINTX. 1 2 RXPSL [1:1] RX pin pull select. This bit is effective in LIN or SCI mode. This bit selects pull type in the input pin LINRX. 1 1 CLKPSL [0:0] Reserved 1 0 0 LINCOMP 0x60 32 The LINCOMPARE register is used to configure the sync delimeter and sync break extension. Reserved2 [31:16] Reserved 16 16 Reserved1 [15:10] Reserved 6 10 SDEL [9:8] 2-bit Sync Delimiter compare. These bits are effective in LIN mode only. These bits are used to configure the number of Tbit for the sync delimiter in the sync field. The time delay calculation for the synchronization delimiter is: TSDEL = (SDEL + 1)Tbit These bits are writable in LIN mode only. 2 8 Reserved [7:3] Reserved 5 3 SBREAK [2:0] 3-bit Sync Break extend. LIN mode only. These bits are used to configure the number of Tbits for the sync break to extend the minimum 13 Tbit in the Sync Field to a maximum of 20 Tbit. The time delay calculation for the sync break is: TSYNBRK = 13Tbit + SBREAK x Tbit These bits are writable in LIN mode only. 3 0 0 LINRD0 0x64 32 The LINRD0 register contains the lower 4 bytes of the received LIN frame data. RD0 [31:24] 8-bit Receive Buffer 0 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. A read of this byte clears the RXDY byte. Note: RD<x-1> is equivalent to Data byte <x> of the LIN frame. 8 24 RD1 [23:16] 8-bit Receive Buffer 1. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. 8 16 RD2 [15:8] 8-bit Receive Buffer 2. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. 8 8 RD3 [7:0] 8-bit Receive Buffer 3. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. 8 0 0 LINRD1 0x68 32 The LINRD1 regsiter contains the upper 4 bytes of the received LIN frame data. RD4 [31:24] 8-bit Receive Buffer 4 Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. 8 24 RD5 [23:16] 8-bit Receive Buffer 5. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. 8 16 RD6 [15:8] 8-bit Receive Buffer 6. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. 8 8 RD7 [7:0] 8-bit Receive Buffer 7. Each response data-byte that is received in the SCIRXSHFT register is transferred to the corresponding RDy register according to the number of bytes received. 8 0 0 LINMASK 0x6C 32 The LINMASK register is used to configure the masks used for filtering incoming ID messages for receive and transmit frames. Reserved1 [31:24] Reserved 8 24 RXIDMASK [23:16] Receive ID mask. This field is effective in LIN mode only.This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID witht the RX ID mask will set the ID RX flag and trigger and ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that that bit is filtered and therefore not used in the compare. When HGENCTRL is set to 1, this field must be set to 0xFF. 8 16 Reserved [15:8] Reserved 8 8 TXIDMASK [7:0] Transmit ID mask. This field is effective in LIN mode only. This 8-bit mask is used for filtering an incoming ID message and compare it to the ID-byte. A compare match of the received ID with the TX ID Mask will set the ID TX flag and trigger an ID interrupt if enabled. A 0 bit in the mask indicates that bit is compared to the ID-byte. A 1 bit in the mask indicates that bit is filtered and therefore not used for the compare. When HGENCTRL is set to 1, this field must be set to 0xFF. 8 0 0 LINID 0x70 32 The LINID register contains the identification fields for LIN communication. NOTE: For software compatibility with future LIN modules, the HGEN CTRL bit must be set to 1, the RX ID MASK field must be set to FFh, and the TX ID MASK field must be set to FFh. Reserved [31:24] Reserved 8 24 RECEIVEDID [23:16] Received ID. This bit is effective in LIN mode only. This byte contains the current message identifier. During header reception the received ID is copied from the SCIRXSHF register to this byte if there is no ID-parity error and there has been an RX/TX match. Note: If a framing error (FE) is detected during ID reception, the received ID will also not be copied to the LINID register. 8 16 IDSLAVETASKBYTE [15:8] ID Slave Task byte. This field is effective in LIN mode only. This byte contains the identifier to which the received ID of an incoming header will be compared in order to decide whether a RX response, a TX response, or no action needs to be done by the LIN node. These bits are writable in LIN mode only. 8 8 IDBYTE [7:0] ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. On a master node, a write to this register by the CPU initiates a header transmission. For a slave task, this byte is used for message filtering when HGENCTRL (SCIGCR1.12) is '0'. These bits are writable in LIN mode only. 8 0 0 LINTD0 0x74 32 The LINTD0 register contains the lower 4 bytes of the data to be transmitted. NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame. TD0 [31:24] 8-bit Transmit Buffer 0. Byte 0 to be transmitted is written into this register and then copied to SCITXSHF for transmission. Once byte 0 is written in TDO buffer, transmission will be initiated. 8 24 TD1 [23:16] 8-bit Transmit Buffer 3. Byte 1 to be transmitted is written into this register and then copied to SCITXSHF for transmission. 8 16 TD2 [15:8] 8-bit Transmit Buffer 2. Byte 2 to be transmitted is written into this register and then copied to SCITXSHF for transmission. 8 8 TD3 [7:0] 8-bit Transmit Buffer 3. Byte 3 to be transmitted is written into this register and then copied to SCITXSHF for transmission. 8 0 0 LINTD1 0x78 32 The LINTD1 register contains the upper 4 bytes of the data to be transmitted. NOTE: TD<x-1> is equivalent to Data byte <x> of the LIN frame. TD4 [31:24] 8-bit Transmit Buffer 4. Byte4 to be transmitted is written into this register and then copied to SCITXSHF for transmission. 8 24 TD5 [23:16] 8-bit Transmit Buffer 5. Byte 5 to be transmitted is written into this register and then copied to SCITXSHF for transmission. 8 16 TD6 [15:8] 8-bit Transmit Buffer 6. Byte 6 to be transmitted is written into this register and then copied to SCITXSHF for transmission. 8 8 TD7 [7:0] 8-bit Transmit Buffer 7. Byte 7 to be transmitted is written into this register and then copied to SCITXSHF for transmission. 8 0 0 MBRSR 0x7C 32 The MBRSR register is used to configure the expected maximum baud rate of the LIN network. Reserved [31:13] Reserved 19 13 MBR [12:0] Maximum Baud Rate Prescaler. This field is effective in LIN mode only. This 13-bit prescaler is used during the synchronization phase (see the "Header Reception and Adaptive Baudrate" section) of a slave module if the ADAPT bit is set. In this way, a SCI/LIN slave using an automatic or select bit rate modes detects any LIN bus legal rate automatically. The MBR value should be programmed to allow a maximum baud rate that is not more than 10% above the expected operating baud rate in the LIN network. Otherwise a s 0x00 data byte could mistakenly be detected as sync break. The default value is for a 70MHz LINCLK (0xDAC). This MBR prescaler is used by the wake-up and idle time counters for a constant expiration time relative to a 20kHz rate. 13 0 0 SCIPIO9 0x80 32 Couldn't find this register in spec. But it's mentioned in RTL. Reserved1 [31:16] Reserved 16 16 Reserved [15:3] Reserved 13 3 TXSL [2:2] SCITX PIN value 1 2 RXSL [1:1] SCIRX PIN value 1 1 CLKSL [0:0] Reserved 1 0 0 Reserved 0x84 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved1 0x88 32 Reserved1 Reserved [31:0] Reserved 32 0 0 Reserved2 0x8C 32 Reserved2 Reserved [31:0] Reserved 32 0 0 IODFTCTRL 0x90 32 The IODFTCTRL register is used to emulate various error and test conditions. BERRENA [31:31] Bit Errror Enable bit. This bit is effective in LIN mode only. This bit is used to create a Bit error. When this bit is set, the bit received is ORed with 1 and passed to the Bit monitor circuitry. 1 31 PBERRENA [30:30] Physical Bus Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a Physical Bus Error. When this bit is set, the bit received during Sync Break field transmission is ORed with 1 and passed to the Bit monitor circuitry 1 30 CERRENA [29:29] Checksum Error Enable bit. This bit is effective in LIN mode only. This bit is used to create a checksum error. When this bit is set, the polarity of the CTYPE (checksum type) in the receive checksum calculator is changed so that a checksum error is generated. 1 29 ISFERRENA [28:28] Inconsistent Sync Field Error Enable bit. This bit is effective in LIN mode only. This bit is used to create an ISF error. When this bit is set, the bit widths in the sync field are varied so that the ISF check fails and the error flag is set. 1 28 Reserved3 [27:27] Reserved 1 27 FERRENA [26:26] This bit is used to create a Frame Error. This bit is effective in SCI-compatible mode only. When this bit is set, the stop bit received is ANDed with ’0’ and passed to the stop bit check circuitry. 1 26 PERRENA [25:25] Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create a Parity Error. When this bit is set, in compatible mode, the parity bit received is toggled so that a parity error occurs. 1 25 BRKDTERRENA [24:24] Compatible Mode only This bit is effective in SCI-compatible mode only. This bit is used to create BRKDT error (SCI mode only). When this bit is set, the stop bit of the frame is ANDed with ’0’ and passed to the RSM so that a frame error occurs. Then the RX Pin is forced to continuous low for 10 Tbits so that a BRKDT error occurs. 1 24 Reserved2 [23:21] Reserved 3 21 PINSAMPLEMASK [20:19] Pin sample mask. These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples correctly with the majority detection circuitry. Note: During IODFT mode testing for the pin sample mask, the prescalar P must be programmed to be greater than 2. 2 19 TXSHIFT [18:16] Transmit shift. These bits define the delay by which the value on LINTX is delayed so that the value on LINRX is asynchronous. (Not applicable to Start Bit) 3 16 Reserved1 [15:12] Reserved 4 12 IODFTENA [11:8] IO DFT Enable Key This field is used to enable the IODFT mode of the SCI/LIN module for testing. Writable Only in privilege mode 4 8 Reserved [7:2] Reserved 6 2 LPBENA [1:1] Module loopback enable. In analog loopback mode the complete communication path through the I/Os can be tested, whereas in digital loopback mode the I/O buffers are excluded from this path. Writable Only in privilege mode 1 1 RXPENA [0:0] Module Analog loopback through receive pin enable. This bit defines whether the I/O buffers for the transmit or the receive pin are included in the communication path in analog loopback mode only. Writable Only in privilege mode 1 0 0 APP_UART_0 0x53F7F000 0 148 registers APP_UART SCIGCR0 0x0 32 The SCIGCR0 register defines the module reset RESERVED [31:1] Reserved 31 1 RESET [0:0] GIO reset 1 0 0 SCIGCR1 0x4 32 The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI RESERVED4 [31:26] Reserved 6 26 TXENA [25:25] Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set 1 25 RXENA [24:24] Allows the receiver to transfer data from the shift buffer to the receive buffer 1 24 RESERVED3 [23:18] Reserved 6 18 CONT [17:17] This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended 1 17 LOOP_BACK [16:16] Enable bit for loopback mode 1 16 RESERVED2 [15:10] Reserved 6 10 POWERDOWN [9:9] When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode 1 9 SLEEP [8:8] In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode 1 8 SW_nRESET [7:7] Software reset (active low) 1 7 RESERVED1 [6:6] Reserved 1 6 CLOCK [5:5] SCI internal clock enable 1 5 STOP [4:4] SCI number of stop bits 1 4 PARITY [3:3] SCI parity odd/even selection 1 3 PARITY_ENA [2:2] SCI parity enable 1 2 TIMING_MODE [1:1] SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing) 1 1 COMM_MODE [0:0] SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode) 1 0 0 RESERVED1 0x8 32 Reserved RESERVED [31:0] Reserved 32 0 0 SCISETINT 0xC 32 SCI Set Interrupt Register RESERVED4 [31:27] Reserved 5 27 SET_FE_INT [26:26] Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 26 SET_OE_INT [25:25] Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 25 SET_PE_INT [24:24] Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 24 RESERVED3 [23:19] Reserved 5 19 SET_RX_DMA_ALL [18:18] Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames 1 18 SET_RX_DMA [17:17] To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 17 SET_TX_DMA [16:16] To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 16 RESERVED2 [15:10] Reserved 6 10 SET_RX_INT [9:9] Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 9 SET_TX_INT [8:8] Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 8 RESERVED1 [7:2] Reserved 6 2 SET_WAKEUP_INT [1:1] Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 1 SET_BRKDT_INT [0:0] Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 0 0 SCICLEARINT 0x10 32 SCI Clear Interrupt Register RESERVED4 [31:27] Reserved 5 27 CLR_FE_INT [26:26] Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 26 CLR_OE_INT [25:25] Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 25 CLR_PE_INT [24:24] Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 24 RESERVED3 [23:19] Reserved 5 19 CLR_RX_DMA_ALL [18:18] User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames 1 18 CLR_RX_DMA [17:17] Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 17 CLR_TX_DMA [16:16] Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 16 RESERVED2 [15:10] Reserved 6 10 CLR_RX_INT [9:9] Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 9 CLR_TX_INT [8:8] Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 8 RESERVED1 [7:2] Reserved 6 2 CLR_WAKEUP_INT [1:1] Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 1 CLR_BRKDT_INT [0:0] Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 0 0 SCISETINTLVL 0x14 32 SCI Set Interrupt Level Register RESERVED5 [31:27] Reserved 5 27 SET_FE_INT_LVL [26:26] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 26 SET_OE_INT_LVL [25:25] Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 25 SET_PE_INT_LVL [24:24] Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 24 RESERVED4 [23:19] Reserved 5 19 SET_RX_DMA_ALL_INT_LVL [18:18] User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 18 RESERVED3 [17:16] Reserved 2 16 SET_INC_BR_INT_LVL [15:15] Reserved 1 15 RESERVED2 [14:10] Reserved 5 10 SET_RX_INT_LVL [9:9] Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 9 SET_TX_INT_LVL [8:8] Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 8 RESERVED1 [7:2] Reserved 6 2 SET_WAKEUP_INT_LVL [1:1] Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 1 SET_BRKDT_INT_LVL [0:0] Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 0 0 SCICLEARINTLVL 0x18 32 SCI Clear Interrupt Level Register RESERVED5 [31:27] Reserved 5 27 CLR_FE_INT_LVL [26:26] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 26 CLR_OE_INT_LVL [25:25] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 25 CLR_PE_INT_LVL [24:24] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 24 RESERVED4 [23:19] Reserved 5 19 CLR_RX_DMA_ALL_INT_LVL [18:18] Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0. 1 18 RESERVED3 [17:16] Reserved 2 16 CLR_INC_BR_INT_LVL 1 15 RESERVED2 [14:10] Reserved 5 10 CLR_RX_INT_LVL [9:9] Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 9 CLR_TX_INT_LVL [8:8] Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 8 RESERVED1 [7:2] Reserved 6 2 CLR_WAKEUP_INT_LVL [1:1] Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 1 CLR_BRKDT_INT_LVL [0:0] Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 0 0 SCIFLR 0x1C 32 SCI Flags Register RESERVED3 [31:27] Reserved 5 27 FE [26:26] SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0 1 26 OE [25:25] SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD 1 25 PE [24:24] SCI parity error flag. This bit is set when a parity error is detected in the received data 1 24 RESERVED2 [23:13] Reserved 11 13 RXWAKE [12:12] Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address 1 12 TX_EMPTY [11:11] Transmitter empty flag. The value of this flag indicates the contents of the transmitter’s buffer register (SCITD) and shift register (SCITXSHF) 1 11 TXWAKE [10:10] SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format 1 10 RXRDY [9:9] SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA. 1 9 TXRDY [8:8] Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character. 1 8 RESERVED1 [7:4] Reserved 4 4 Bus_busy_flag [3:3] This bit indicates whether the receiver is in the process of receiving a frame. 1 3 IDLE [2:2] SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. 1 2 WAKEUP [1:1] Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode. 1 1 BRKDT [0:0] SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin. 1 0 0 SCIINTVECT0 0x20 32 SCI Interrupt Offset Vector 0 Register RESERVED [31:4] Reserved 28 4 INTVECT0 [3:0] Interrupt vector offset for INT0 4 0 0 SCIINTVECT1 0x24 32 SCI Interrupt Offset Vector 1 Register RESERVED [31:4] Reserved 28 4 INTVECT1 [3:0] Interrupt vector offset for INT1 4 0 0 SCICHAR 0x28 32 SCI Character Control Register RESERVED [31:3] Reserved 29 3 CHAR [2:0] Sets the SCI data length from 1 to 8 bits 3 0 0 SCIBAUD 0x2C 32 SCI Baud Rate Selection Register RESERVED [31:24] Reserved 8 24 BAUD [23:0] SCI 24-bit baud selection 24 0 0 SCIED 0x30 32 Receiver Emulation Data Buffer RESERVED [31:8] Reserved 24 8 ED [7:0] Receiver Emulation Data Buffer 8 0 0 SCIRD 0x34 32 Receiver Data Buffer RESERVED [31:8] Reserved 24 8 RD [7:0] Contains received data. 8 0 0 SCITD 0x38 32 Transmit Data Buffer Register RESERVED [31:8] Reserved 24 8 TD [7:0] Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register. 8 0 0 SCIPIO0 0x3C 32 SCI Pin I/O Control Register 0 RESERVED [31:3] Reserved 29 3 TX_FUNC [2:2] Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin. 1 2 RX_FUNC [1:1] Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin 1 1 CLK_FUNC [0:0] Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin. 1 0 0 SCIPIO1 0x40 32 SCI Pin I/O Control Register 1 RESERVED [31:3] Reserved 29 3 TX_DIR [2:2] Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin 1 2 RX_DIR [1:1] Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin 1 1 CLK_DIR [0:0] Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin 1 0 0 SCIPIO2 0x44 32 SCI Pin I/O Control Register 2 RESERVED [31:3] Reserved 29 3 TX_DATA_IN [2:2] Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high. 1 2 RX_DATA_IN [1:1] Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high. 1 1 CLK_DATA_IN [0:0] Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high. 1 0 0 SCIPIO3 0x48 32 SCI Pin I/O Control Register 3 RESERVED [31:3] Reserved 29 3 TX_DATA_OUT [2:2] Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high). 1 2 RX_DATA_OUT [1:1] Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high). 1 1 CLK_DATA_OUT [0:0] Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high). 1 0 0 SCIPIO4 0x4C 32 SCI Pin I/O Control Register 4 RESERVED [31:3] Reserved 29 3 TX_DATA_SET [2:2] Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.) 1 2 RX_DATA_SET [1:1] Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.) 1 1 CLK_DATA_SET [0:0] Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.) 1 0 0 SCIPIO5 0x50 32 SCI Pin I/O Control Register 5 RESERVED [31:3] Reserved 29 3 TX_DATA_CLR [2:2] Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.) 1 2 RX_DATA_CLR [1:1] Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.) 1 1 CLK_DATA_CLR [0:0] Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.) 1 0 0 SCIPIO6 0x54 32 SCI Pin I/O Control Register 6 RESERVED [31:3] Reserved 29 3 TX_PDR [2:2] TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1 1 2 RX_PDR [1:1] RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1 1 1 CLK_PDR [0:0] CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1 1 0 0 SCIPIO7 0x58 32 SCI Pin I/O Control Register 7 RESERVED [31:3] Reserved 29 3 TX_PD [2:2] TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled. 1 2 RX_PD [1:1] RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled. 1 1 CLK_PD [0:0] CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled. 1 0 0 SCIPIO8 0x5C 32 SCI Pin I/O Control Register 8 RESERVED [31:3] Reserved 29 3 TX_PSL [2:2] TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin. 1 2 RX_PSL [1:1] RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin. 1 1 CLK_PSL [0:0] CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin. 1 0 0 RESERVED2 0x60 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED3 0x64 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED4 0x68 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED5 0x6C 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED6 0x70 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED7 0x74 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED8 0x78 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED9 0x7C 32 Reserved RESERVED [31:0] Reserved 32 0 0 SCIPIO9 0x80 32 SCI Pin I/O Control Register 9 RESERVED [31:3] Reserved 29 3 TX_SL [2:2] This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin. 1 2 RX_SL [1:1] This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin 1 1 CLK_SL [0:0] This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin 1 0 0 SCIIODCTRL 0x90 32 SCI IO DFT Control RESERVED4 [31:27] Reserved 5 27 FEN [26:26] Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ’0’ and passed to the stop bit check circuitry. 0 = No effect. 1 26 PEN [25:25] Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect 1 25 BRKDT_ENA [24:24] Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ‘0’ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect. 1 24 RESERVED3 [23:21] Reserved 3 21 PIN_SAMPLE_MASK [20:19] PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK. 2 19 TX_SHIFT [18:16] These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay. 3 16 RESERVED2 [15:12] Reserved 4 12 IODFTENA [11:8] These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay. 4 8 RESERVED1 [7:2] Reserved 6 2 LBP_ENA [1:1] Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled. 1 1 RXP_ENA [0:0] Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin. 1 0 0 APP_SPI_0 0x53F7F400 0 420 registers APP_SPI HL_REV 0x0 32 IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility SCHEME [31:30] Used to distinguish between old scheme and current - (RO ) 2 30 RSVD [29:28] Reserved These bits are initialized to zero and writes to them are ignored - (RO ) 2 28 FUNC [27:16] Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned - (RO ) 12 16 R_RTL [15:11] RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or Y changes Design team has an internal 'Z' [customer invisible] number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO ) 5 11 X_MAJOR [10:8] Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X does NOT change due to: [1] Bug fixes [2] Change in feature parameters - (RO ) 3 8 CUSTOM [7:6] Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers - (RO ) 2 6 Y_MINOR [5:0] Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available [2] When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: [1] Bug fixes [2] Typos or clarifications [3] major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: [1] Typos/clarifications [2] Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release [say for silicon PG11] that occurs due to bug fix should document the corresponding spec number [XYS] in its release notes - (RO ) 6 0 0 HL_HWINFO 0x4 32 Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. RSVD [31:7] Reserved These bits are initialized to zero and writes to them are ignored - (RO ) 25 7 RETMODE [6:6] This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO ) 1 6 FFNBYTE [5:1] FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO ) 5 1 USEFIFO [0:0] Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO ) 1 0 0 HL_SYSCONFIG 0x10 32 Clock management configuration RSVD [31:4] Reserved - (RO ) 28 4 IDLEMODE [3:2] Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW ) 2 2 FREEEMU [1:1] Sensitivity to emulation [debug] suspend input signal - (RW ) 1 1 SOFTRESET [0:0] Software reset [Optional] - (RW ) 1 0 0 REVISION 0x100 32 This register contains the hard coded RTL revision number. RESERVED_13 [31:8] Reads returns 0 - (RO ) 24 8 REV [7:0] IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO 8 0 0 SYSCONFIG 0x110 32 This register allows controlling various parameters of the OCP interface. RESERVED_14 [31:10] Reads returns 0 - (RO ) 22 10 CLOCKACTIVITY [9:8] Clocks activity during wake up mode period - (RW ) 2 8 RESERVED_15 [7:5] Reads returns 0 - (RO ) 3 5 SIDLEMODE [4:3] Power management - (RW ) 2 3 ENAWAKEUP [2:2] WakeUp feature control - (RW ) 1 2 SOFTRESET [1:1] Software reset During reads it always returns 0 - (RW ) 1 1 AUTOIDLE [0:0] Internal OCP Clock gating strategy - (RW ) 1 0 0 SYSSTATUS 0x114 32 This register provides status information about the module excluding the interrupt status information RESERVED_16 [31:1] Reserved for module specific status information Read returns 0 - (RO ) 31 1 RESETDONE [0:0] Internal Reset Monitoring - (RO ) 1 0 0 IRQSTATUS 0x118 32 The interrupt status regroups all the status of the module internal events that can generate an interrupt RESERVED_8 [31:18] Reads returns 0 - (RO ) 14 18 EOW [17:17] End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] - (RW ) 1 17 WKS [16:16] Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - (RW ) 1 16 RESERVED_7 [15:15] Reads returns 0 - (RO ) 1 15 RX3_FULL [14:14] Receiver register is full or almost full Only when Channel 3 is enabled - (RW ) 1 14 TX3_UNDERFLOW [13:13] Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW ) 1 13 TX3_EMPTY [12:12] Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW ) 1 12 RESERVED_9 [11:11] Reads returns 0 - (RO ) 1 11 RX2_FULL [10:10] Receiver register full or almost full Channel 2 - (RW ) 1 10 TX2_UNDERFLOW [9:9] Transmitter register underflow Channel 2 - (RW ) 1 9 TX2_EMPTY [8:8] Transmitter register empty or almost empty Channel 2 - (RW ) 1 8 RESERVED_10 [7:7] Reads returns 0 - (RO ) 1 7 RX1_FULL [6:6] Receiver register full or almost full Channel 1 - (RW ) 1 6 TX1_UNDERFLOW [5:5] Transmitter register underflow Channel 1 - (RW ) 1 5 TX1_EMPTY [4:4] Transmitter register empty or almost empty Channel 1 - (RW ) 1 4 RX0_OVERFLOW [3:3] Receiver register overflow [slave mode only] Channel 0 - (RW ) 1 3 RX0_FULL [2:2] Receiver register full or almost full Channel 0 - (RW ) 1 2 TX0_UNDERFLOW [1:1] Transmitter register underflow Channel 0 - (RW ) 1 1 TX0_EMPTY [0:0] Transmitter register empty or almost empty Channel 0 - (RW ) 1 0 0 IRQENABLE 0x11C 32 This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis. RESERVED_5 [31:18] Reads return 0 - (RO ) 14 18 EOW_ENABLE [17:17] End of Word count Interrupt Enable - (RW ) 1 17 WKE [16:16] Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - (RW ) 1 16 RESERVED_4 [15:15] Reads returns 0 - (RO ) 1 15 RX3_FULL_ENABLE [14:14] Receiver register Full Interrupt Enable Ch 3 - (RW ) 1 14 TX3_UNDERFLOW_ENABLE [13:13] Transmitter register Underflow Interrupt Enable Ch 3 - (RW ) 1 13 TX3_EMPTY_ENABLE [12:12] Transmitter register Empty Interrupt Enable Ch3 - (RW ) 1 12 RESERVED_6 [11:11] Reads return 0 - (RO ) 1 11 RX2_FULL_ENABLE [10:10] Receiver register Full Interrupt Enable Ch 2 - (RW ) 1 10 TX2_UNDERFLOW_ENABLE [9:9] Transmitter register Underflow Interrupt Enable Ch 2 - (RW ) 1 9 TX2_EMPTY_ENABLE [8:8] Transmitter register Empty Interrupt Enable Ch 2 - (RW ) 1 8 RESERVED_3 [7:7] Reads return 0 - (RO ) 1 7 RX1_FULL_ENABLE [6:6] Receiver register Full Interrupt Enable Ch 1 - (RW ) 1 6 TX1_UNDERFLOW_ENABLE [5:5] Transmitter register Underflow Interrupt Enable Ch 1 - (RW ) 1 5 TX1_EMPTY_ENABLE [4:4] Transmitter register Empty Interrupt Enable Ch 1 - (RW ) 1 4 RX0_OVERFLOW_ENABLE [3:3] Receiver register Overflow Interrupt Enable Ch 0 - (RW ) 1 3 RX0_FULL_ENABLE [2:2] Receiver register Full Interrupt Enable Ch 0 - (RW ) 1 2 TX0_UNDERFLOW_ENABLE [1:1] Transmitter register Underflow Interrupt Enable Ch 0 - (RW ) 1 1 TX0_EMPTY_ENABLE [0:0] Transmitter register Empty Interrupt Enable Ch 0 - (RW ) 1 0 0 WAKEUPENABLE 0x120 32 The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis. RESERVED_18 [31:1] Reads returns 0 - (RO ) 31 1 WKEN [0:0] WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - (RW ) 1 0 0 SYST 0x124 32 This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode. RESERVED_17 [31:12] Reads returns 0 - (RO ) 20 12 SSB [11:11] Set status bit - (RW ) 1 11 SPIENDIR [10:10] Set the direction of the SPIEN[3:0] lines and SPICLK line - (RW ) 1 10 SPIDATDIR1 [9:9] Set the direction of the SPIDAT[1] - (RW ) 1 9 SPIDATDIR0 [8:8] Set the direction of the SPIDAT[0] - (RW ) 1 8 WAKD [7:7] SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit - (RW ) 1 7 SPICLK [6:6] SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI line is driven high or low according to the value written into this register - (RW ) 1 6 SPIDAT_1 [5:5] SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit returns the value on the SPIDAT[1] line [high or low] and a write into this bit has no effect - (RW ) 1 5 SPIDAT_0 [4:4] SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit returns the value on the SPIDAT[0] line [high or low] and a write into this bit has no effect - (RW ) 1 4 SPIEN_3 [3:3] SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[3] line [high or low] and a write into this bit has no effect - (RW ) 1 3 SPIEN_2 [2:2] SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[2] line [high or low] and a write into this bit has no effect - (RW ) 1 2 SPIEN_1 [1:1] SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[1] line [high or low] and a write into this bit has no effect - (RW ) 1 1 SPIEN_0 [0:0] SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[0] line [high or low] and a write into this bit has no effect - (RW ) 1 0 0 MODULCTRL 0x128 32 This register is dedicated to the configuration of the serial port interface. RESERVED_11 [31:9] Reads returns 0 - (RO ) 23 9 FDAA [8:8] FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX[i] and MCSPI_RX[i] registers - (RW ) 1 8 MOA [7:7] Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 - (RW ) 1 7 INITDLY [6:4] Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW ) 3 4 SYSTEM_TEST [3:3] Enables the system test mode - (RW ) 1 3 MS [2:2] Master/ Slave - (RW ) 1 2 PIN34 [1:1] Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW ) 1 1 SINGLE [0:0] Single channel / Multi Channel [master mode only] - (RW ) 1 0 0 CH0CONF 0x12C 32 This register is dedicated to the configuration of the channel 0 RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS0 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 SPIENSLV [22:21] Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH0STAT 0x130 32 This register provides status information about transmitter and receiver registers of channel 0 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH0CTRL 0x134 32 This register is dedicated to enable the channel 0 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX0 0x138 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 0 Data to transmit - (RW ) 32 0 0 RX0 0x13C 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 0 Received Data - (RO ) 32 0 0 CH1CONF 0x140 32 This register is dedicated to the configuration of the channel. RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS1 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 RESERVED_1 [22:21] read returns 0 - (RO ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH1STAT 0x144 32 This register provides status information about transmitter and receiver registers of channel 1 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH1CTRL 0x148 32 This register is dedicated to enable the channel 1 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX1 0x14C 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 1 Data to transmit - (RW ) 32 0 0 RX1 0x150 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 1 Received Data - (RO ) 32 0 0 CH2CONF 0x154 32 This register is dedicated to the configuration of the channel 2 RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS2 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 RESERVED_1 [22:21] read returns 0 - (RO ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH2STAT 0x158 32 This register provides status information about transmitter and receiver registers of channel 2 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH2CTRL 0x15C 32 This register is dedicated to enable the channel 2 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX2 0x160 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 2 Data to transmit - (RW ) 32 0 0 RX2 0x164 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 2 Received Data - (RO ) 32 0 0 CH3CONF 0x168 32 This register is dedicated to the configuration of the channel 3 RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS3 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 RESERVED_1 [22:21] read returns 0 - (RO ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH3STAT 0x16C 32 This register provides status information about transmitter and receiver registers of channel 3 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH3CTRL 0x170 32 This register is dedicated to enable the channel 3 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX3 0x174 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 3 Data to transmit - (RW ) 32 0 0 RX3 0x178 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 3 Received Data - (RO ) 32 0 0 XFERLEVEL 0x17C 32 This register provides transfer levels needed while using FIFO buffer during transfer. WCNT [31:16] Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW ) 16 16 AFL [15:8] Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL[AFL] must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW ) 8 8 AEL [7:0] Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL[AEL] must be set with n-1 - (RW ) 8 0 0 DAFTX 0x180 32 This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled. DAFTDATA [31:0] FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to "1" and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW ) 32 0 0 DAFRX 0x1A0 32 This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled. DAFRDATA [31:0] FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to "1" and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO ) 32 0 0 APP_CANCFG 0x53F7F800 0 768 registers APP_CANCFG SS_PID 0x0 32 SS_PID SCHEME [31:30] PID register scheme 2 30 BU [29:28] Business Unit: 10 = Processors 2 28 MODULE_ID [27:16] Module ID 12 16 RTL [15:11] RTL revision. Will vary depending on release. 5 11 MAJOR [10:8] Major revision 3 8 CUSTOM [7:6] Custom 2 6 MINOR [5:0] Minor revision 6 0 0 SS_CTRL 0x4 32 SS_CTRL NU0 [31:7] Reserved 25 7 EXT_TS_CNTR_EN [6:6] External TimeStamp Counter Enable 1 6 AUTOWAKEUP [5:5] Automatic Wakeup Enable 1 5 WAKEUPREGEN [4:4] Wakeup Request Enable 1 4 DBGSUSP_FREE [3:3] 0-Honor Debug Suspend, 1-Disregard debug suspend 1 3 NU [2:0] Reserved 3 0 0 SS_STAT 0x8 32 SS_STAT NU1 [31:3] Reserved 29 3 EN_FDOE [2:2] Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe 1 2 MMI_DONE [1:1] 0:Memory Initialization is in progress, 1:Memory Intialization Done 1 1 NU [0:0] Reserved 1 0 0 SS_ICS 0xC 32 SS_ICS NU2 [31:1] Reserved 31 1 ICS [0:0] This bit contains the External TimeStamp Counter Overflow Interrupt status. Write '1' to clear bits. (ICS - Interrupt Clear Shadow Register) 1 0 0 SS_IRS 0x10 32 SS_IRS NU3 [31:1] Reserved 31 1 IRS [0:0] External TimeStamp Counter Overflow Interrupt status. Read raw interrupt status. (IRS - Interrupt Raw Status Register) 1 0 0 SS_IECS 0x14 32 SS_IECS NU4 [31:1] Reserved 31 1 IECS [0:0] External TimeStamp Counter Overflow Interrupt. Write '1' to clear bits. (IECS - Interrupt Enable Clear Shadow Register) 1 0 0 SS_IE 0x18 32 SS_IE NU5 [31:1] Reserved 31 1 IE [0:0] External TimeStamp Counter Overflow Interrupt. Write '1' to set interrupt enable. Read returns interrupt enable. (IE - Interrupt Enable Register) 1 0 0 SS_IES 0x1C 32 SS_IES NU6 [31:1] Reserved 31 1 IES [0:0] External TimeStamp Counter Overflow Interrupt. Read Enabled Interrupts. (IES - Interrupt Enable Status) 1 0 0 SS_EOI 0x20 32 SS_EOI NU7 [31:8] Reserved 24 8 EOI [7:0] Write with bit position of targeted interrupt. (E.g. Ext TS is bit 0). Upon write, level interrupt will clear and if unserviced interrupt counter > 1 will issue another pulse interrupt. Field values: ext_ts_eoi(0): EOI value for External TS interrupt mcan_0_eoi(1): EOI value for mcan[0] interrupt mcan_1_eoi(2): EOI value for mcan[1] interrupt (EOI - End Of Interrupt) 8 0 0 SS_EXT_TS_PS 0x24 32 SS_EXT_TS_PS NU8 [31:24] Reserved 8 24 PRESCALE [23:0] External Timestamp Prescaler reload value. External Timestamp count rate is host clock rate divided by this value with one exception: a value of 0 has the same effect as 1 . 24 0 0 SS_EXT_TS_USIC 0x28 32 SS_EXT_TS_USIC NU9 [31:5] Reserved 27 5 EXT_TS_INTR_CNTR [4:0] Number of unserviced rollover interrupts. If >1 an EOI write will issue another pulse interrupt (EXT_TS_USIC - External TImeStamp Unserviced Interrupts Counter) 5 0 0 CREL 0x200 32 CREL REL [31:28] Core Release 4 28 STEP [27:24] Step of Core Release 4 24 SUBSTEP [23:20] Sub-Step of Core Release 4 20 YEAR [19:16] Time Stamp Year 4 16 MON [15:8] Time Stamp Month 8 8 DAY [7:0] Time Stamp Day 8 0 0 ENDN 0x204 32 ENDN ETV [31:0] Endianess test value 32 0 0 CUST 0x208 32 CUST CUST [31:0] Custom 32 0 0 DBTP 0x20C 32 DBTP NU13 [31:24] Reserved 8 24 TDC [23:23] Transmitter Delay Compensation 1 23 NU12 [22:21] Reserved 2 21 DBRP [20:16] Data Baud Rate Prescaler 5 16 NU11 [15:13] Reserved 3 13 DTSEG1 [12:8] Data time segment before smaple point 5 8 DTSEG2 [7:4] Data time segment after sample point 4 4 DSJW [3:0] Data resynchronization Jump Width 4 0 0 TEST 0x210 32 TEST NU15 [31:8] Reserved 24 8 RX [7:7] Receive Pin 1 7 TX [6:5] Control of Transmit Pin 2 5 LBCK [4:4] Loop Back Mode 1 4 NU14 [3:0] Reserved 4 0 0 RWD 0x214 32 RWD NU16 [31:16] Reserved 16 16 WDV [15:8] Watchdog Value 8 8 WDC [7:0] Watchdog Counter Value 8 0 0 CCCR 0x218 32 CCCR NU18 [31:15] Reserved 17 15 TXP [14:14] Transmit Pause 1 14 EFBI [13:13] Edge Filtering durign Bus Integration 1 13 PXHD [12:12] Protocol Exception Handling Disable 1 12 NU17 [11:10] Reserved 2 10 BRSE [9:9] Bit Rate Switch Enable 1 9 FDOE [8:8] FD Operation Enable 1 8 TEST [7:7] Test Mode enable 1 7 DAR [6:6] Disable Automatic Regransmission 1 6 MON [5:5] Bus Monitoring Mode 1 5 CSR [4:4] Clock Stop Request 1 4 CSA [3:3] Clock Stop Acknowledge 1 3 ASM [2:2] Restriced Operation Mode 1 2 CCE [1:1] Configuration Change Enable 1 1 INIT [0:0] Initialization 1 0 0 NBTP 0x21C 32 NBTP NSJW [31:25] Nominal Resynchronization Jump Width 7 25 NBRP [24:16] Nominal Baud Rate Prescaler 9 16 NTSEG1 [15:8] Nominal Time segment before sample point 8 8 NU19 [7:7] Reserved 1 7 NTSEG2 [6:0] Nominal Time segment after sample point 7 0 0 TSCC 0x220 32 TSCC NU21 [31:20] Reserved 12 20 TCP [19:16] Timestamp Counter Prescaler 4 16 NU20 [15:2] Reserved 14 2 TSS [1:0] Timestamp Select 2 0 0 TSCV 0x224 32 TSCV NU22 [31:16] Reserved 16 16 TSC [15:0] Timestamp Counter 16 0 0 TOCC 0x228 32 TOCC TOP [31:16] Timeout Period 16 16 NU23 [15:3] Reserved 13 3 TOS [2:1] Timeout Select 2 1 ETOC [0:0] Enable Timeout Counter 1 0 0 TOCV 0x22C 32 TOCV NU24 [31:16] Reserved 16 16 TOC [15:0] Timeout Counter 16 0 0 RES00 0x230 32 RES00 RES00 [31:0] Reserved 32 0 0 RES01 0x234 32 RES01 RES01 [31:0] Reserved 32 0 0 RES02 0x238 32 RES02 RES02 [31:0] Reserved 32 0 0 RES03 0x23C 32 RES03 RES03 [31:0] Reserved 32 0 0 ECR 0x240 32 ECR NU25 [31:24] Reserved 8 24 CEL [23:16] CAN Error Logging 8 16 RP [15:15] Recieve Error Passive 1 15 REC [14:8] Recieve Error Counter 7 8 TEC [7:0] Transmit Error Counter 8 0 0 PSR 0x244 32 PSR NU27 [31:23] Reserved 9 23 TDCV [22:16] Transmitter Delay Compensation Value 7 16 NU26 [15:15] Reserved 1 15 PXE [14:14] Protocol Exception Event 1 14 RFDF [13:13] Recieved a CAN FD Message 1 13 RBRS [12:12] BRS flag of last recieved CAN FD Message 1 12 RESI [11:11] ESI flag of last recieved CAN FD Message 1 11 DLEC [10:8] Data Phase Last Error Code 3 8 BO [7:7] Bus_Off status 1 7 EW [6:6] Warning Status 1 6 EP [5:5] Error Passive 1 5 ACT [4:3] Activity 2 3 LEC [2:0] Last Error Code 3 0 0 TDCR 0x248 32 TDCR NU29 [31:15] Reserved 17 15 TDCO [14:8] Transmitter Delay Compensation Offset 7 8 NU28 [7:7] Reserved 1 7 TDCF [6:0] Transmitter Delay Compensation Filter Window Length 7 0 0 RES04 0x24C 32 RES04 RES04 [31:0] Reserved 32 0 0 IR 0x250 32 IR NU30 [31:30] Reserved 2 30 ARA [29:29] Access to Reserved Address 1 29 PED [28:28] Protocol Error in data Phase 1 28 PEA [27:27] Protocol Error in Arbitration Phase 1 27 WDI [26:26] Watchdog Interrupt 1 26 BO [25:25] Bus_Off Status 1 25 EW [24:24] Warning Status 1 24 EP [23:23] Error Passive 1 23 ELO [22:22] Error Logging Overflow 1 22 BEU [21:21] Bit Error Uncorrected 1 21 BEC [20:20] Bit Error Corrected 1 20 DRX [19:19] Message stored to Dedicated Rx Buffer 1 19 TOO [18:18] Timeout Occurred 1 18 MRAF [17:17] Message RAM Access Failure 1 17 TSW [16:16] Timestamp Wraparound 1 16 TEFL [15:15] Tx Event FIFO Element Lost 1 15 TEFF [14:14] Tx Event FIFO Full 1 14 TEFW [13:13] Tx Event FIFO Watermark Reached 1 13 TEFN [12:12] Tx Event FIFO New Entry 1 12 TFE [11:11] Tx FIFO Empty 1 11 TCF [10:10] Transmission Cancellation Finished 1 10 TC [9:9] Transmission Complete 1 9 HPM [8:8] High Priority Message 1 8 RF1L [7:7] Rx FIFO 1 Message Lost 1 7 RF1F [6:6] Rx FIFO 1 Full 1 6 RF1W [5:5] Rx FIFO 1 Watermark Reached 1 5 RF1N [4:4] Rx FIFO 1 New Message 1 4 RF0L [3:3] Rx FIFO 0 Message Lost 1 3 RF0F [2:2] Rx FIFO 0 Full 1 2 RF0W [1:1] Rx FIFO 0 Watermark Reached 1 1 RF0N [0:0] Rx FIFO 0 New Message 1 0 0 IE 0x254 32 IE NU31 [31:30] Reserved 2 30 ARAE [29:29] Accees to Reserve Address Interrupt Enable 1 29 PEDE [28:28] Protocol Error in Data Phase Interrupt Enable 1 28 PEAE [27:27] Protocol Error in Arbitration Phase Interrupt Enable 1 27 WDIE [26:26] Watchdog Interrupt Enable 1 26 BOE [25:25] Bus_Off Status Interrupt Enable 1 25 EWE [24:24] Warning Status Interrupt Enable 1 24 EPE [23:23] Error Passive Interrupt Enable 1 23 ELOE [22:22] Error Logging Overflow Interrupt Enable 1 22 BEUE [21:21] Bit Error Uncorrected Interrupt Enable 1 21 BECE [20:20] Bit Error Corrected Interrupt Enable 1 20 DRX [19:19] Message stored to Dedicated Rx Buffer Interrupt Enable 1 19 TOOE [18:18] Timeout Occurred Interrupt Enable 1 18 MRAFE [17:17] Message RAM Access Failure Interrupt Enable 1 17 TSWE [16:16] Timestamp Wraparound Interrupt Enable 1 16 TEFLE [15:15] Tx Event FIFO Event Lost Interrupt Enable 1 15 TEFFE [14:14] Tx Event FIFO Full Interrupt Enable 1 14 TEFWE [13:13] Tx Event FIFO Watermark Reached Interrupt enable 1 13 TEFNE [12:12] Tx Event FIFO New Entry Interrupt Enable 1 12 TFEE [11:11] Tx FIFO Empty Interrupt Enable 1 11 TCFE [10:10] Transmission Cancellation Finishied Interrupt Enable 1 10 TCE [9:9] Transmission Completed Interrupt Enable 1 9 HPME [8:8] High Priority message Interrupt Enable 1 8 RF1LE [7:7] rx FIFO 1 Message Lost Interrupt Enable 1 7 RF1FE [6:6] Rx FIFO 1 Full Interrupt Enable 1 6 RF1WE [5:5] Rx FIFO 1 Watermark Reached Interrupt Enable 1 5 RF1NE [4:4] Rx FIFO 1 New Message Interrupt Enable 1 4 RF0LE [3:3] Rx FIFO 0 Message Lost Interrupt Enable 1 3 RF0FE [2:2] Rx FIFO 0 Full Interrupt Enable 1 2 RF0WE [1:1] Rx FIFO 0 Watermark Reached Interrupt Enable 1 1 RF0NE [0:0] Rx FIFO 0 New Message Interrupt Enable 1 0 0 ILS 0x258 32 ILS NU32 [31:30] Reserved 2 30 ARAL [29:29] Accees to Reserve Address Interrupt Line 1 29 PEDL [28:28] Protocol Error in Data Phase Interrupt Line 1 28 PEAL [27:27] Protocol Error in Arbitration Phase Interrupt Line 1 27 WDIL [26:26] Watchdog Interrupt Line 1 26 BOL [25:25] Bus_Off Status Interrupt Line 1 25 EWL [24:24] Warning Status Interrupt Line 1 24 EPL [23:23] Error Passive Interrupt Line 1 23 ELOL [22:22] Error Logging Overflow Interrupt Line 1 22 BEUL [21:21] Bit Error Uncorrected Interrupt Line 1 21 BECL [20:20] Bit Error Corrected Interrupt Line 1 20 DRXL [19:19] Message stored to Dedicated Rx Buffer Interrupt Line 1 19 TOOL [18:18] Timeout Occurred Interrupt Line 1 18 MRAFL [17:17] Message RAM Access Failure Interrupt Line 1 17 TSWL [16:16] Timestamp Wraparound Interrupt Line 1 16 TEFLL [15:15] Tx Event FIFO Event Lost Interrupt Line 1 15 TEFFL [14:14] Tx Event FIFO Full Interrupt Line 1 14 TEFWL [13:13] Tx Event FIFO Watermark Reached Interrupt Line 1 13 TEFNL [12:12] Tx Event FIFO New Entry Interrupt Line 1 12 TFEL [11:11] Tx FIFO Empty Interrupt Line 1 11 TCFL [10:10] Transmission Cancellation Finishied Interrupt Line 1 10 TCL [9:9] Transmission Completed Interrupt Line 1 9 HPML [8:8] High Priority message Interrupt Line 1 8 RF1LL [7:7] rx FIFO 1 Message Lost Interrupt Line 1 7 RF1FL [6:6] Rx FIFO 1 Full Interrupt Line 1 6 RF1WL [5:5] Rx FIFO 1 Watermark Reached Interrupt Line 1 5 RF1NL [4:4] Rx FIFO 1 New Message Interrupt Line 1 4 RF0LL [3:3] Rx FIFO 0 Message Lost Interrupt Line 1 3 RF0FL [2:2] Rx FIFO 0 Full Interrupt Line 1 2 RF0WL [1:1] Rx FIFO 0 Watermark Reached Interrupt Line 1 1 RF0NL [0:0] Rx FIFO 0 New Message Interrupt Line 1 0 0 ILE 0x25C 32 ILE NU33 [31:2] Reserved 30 2 EINT1 [1:1] Enable Interrupt Line 1 1 1 EINT0 [0:0] Enable Interrupt Line 0 1 0 0 RES05 0x260 32 RES05 RES05 [31:0] Reserved 32 0 0 RES06 0x264 32 RES06 RES06 [31:0] Reserved 32 0 0 RES07 0x268 32 RES07 RES07 [31:0] Reserved 32 0 0 RES08 0x26C 32 RES08 RES08 [31:0] Reserved 32 0 0 RES09 0x270 32 RES09 RES09 [31:0] Reserved 32 0 0 RES10 0x274 32 RES10 RES10 [31:0] Reserved 32 0 0 RES11 0x278 32 RES11 RES11 [31:0] Reserved 32 0 0 RES12 0x27C 32 RES12 RES12 [31:0] Reserved 32 0 0 GFC 0x280 32 GFC NU34 [31:6] Reserved 26 6 ANFS [5:4] Accept Non-matching Frames Standard 2 4 ANFE [3:2] Accept Non-matching Frames Extended 2 2 RRFS [1:1] reject Remote Frames Standard 1 1 RRFE [0:0] reject Remote Frames Extended 1 0 0 SIDFC 0x284 32 SIDFC NU36 [31:24] Reserved 8 24 LSS_S [23:16] List Size Standard 8 16 FLSSA_S [15:2] Filter List Standard Start Address 14 2 NU35 [1:0] Reserved 2 0 0 XIDFC 0x288 32 XIDFC NU38 [31:23] Reserved 9 23 LSS_X [22:16] List Size Standard 7 16 FLSSA_X [15:2] Filter List Standard Start Address 14 2 NU37 [1:0] Reserved 2 0 0 RES13 0x28C 32 RES13 RES13 [31:0] Reserved 32 0 0 XIDAM 0x290 32 XIDAM NU39 [31:29] Reserved 3 29 EIDM [28:0] Extended ID Mask 29 0 0 HPMS 0x294 32 HPMS NU40 [31:16] Reserved 16 16 FLST [15:15] Filter List 1 15 FIDX [14:8] Filter Index 7 8 MSI [7:6] Message Storeage Indicator 2 6 BIDX [5:0] Buffer Index 6 0 0 NDAT1 0x298 32 NDAT1 ND0_31 [31:0] New Data 0-31 32 0 0 NDAT2 0x29C 32 NDAT2 ND32_63 [31:0] New Data 32-63 32 0 0 RXF0C 0x2A0 32 RXF0C F0OM [31:31] Rx FIFO 0 Operation Mode 1 31 F0WM [30:24] Rx FIFO 0 Watermark 7 24 NU42_1 [23:23] Reserved 1 23 F0S [22:16] Rx FIFO 0 Size 7 16 NU42 [15:15] Reserved 1 15 F0SA [14:2] Rx FIFO 0 Start Address 13 2 NU41 [1:0] Reserved 2 0 0 RXF0S 0x2A4 32 RXF0S NU46 [31:26] Reserved 6 26 RF0L [25:25] Rx FIFO 0 Message Lost 1 25 F0F [24:24] Rx FIFO 0 Full 1 24 NU45 [23:22] Reserved 2 22 F0PI [21:16] Rx FIFO 0 Put Index 6 16 NU44 [15:14] Reserved 2 14 F0GI [13:8] Rx FIFO 0 Get Index 6 8 NU43 [7:7] Reserved 1 7 F0FL [6:0] Rx FIFO 0 Fill Level 7 0 0 RXF0A 0x2A8 32 RXF0A NU47 [31:6] Reserved 26 6 F0AI [5:0] Rx FIFO 0 Acknowledge Index 6 0 0 RXBC 0x2AC 32 RXBC NU49 [31:16] Reserved 16 16 RBSA [15:2] Rx Buffer Start Address 14 2 NU48 [1:0] Reserved 2 0 0 RXF1C 0x2B0 32 RXF1C F1OM [31:31] Rx FIFO 0 Operation Mode 1 31 F1WM [30:24] Rx FIFO 0 Watermark 7 24 NU50_1 [23:23] Reserved 1 23 F1S [22:16] Rx FIFO 0 Size 7 16 NU50 [15:15] Reserved 1 15 F1SA [14:2] Rx FIFO 0 Start Address 13 2 NU499 [1:0] Reserved 2 0 0 RXF1S 0x2B4 32 RXF1S NU54 [31:26] Reserved 6 26 RF1L [25:25] Rx FIFO 0 Message Lost 1 25 F1F [24:24] Rx FIFO 0 Full 1 24 NU53 [23:22] Reserved 2 22 F1PI [21:16] Rx FIFO 0 Put Index 6 16 NU52 [15:14] Reserved 2 14 F1GI [13:8] Rx FIFO 0 Get Index 6 8 NU51 [7:7] Reserved 1 7 F1FL [6:0] Rx FIFO 0 Fill Level 7 0 0 RXF1A 0x2B8 32 RXF1A NU55 [31:6] Reserved 26 6 F1AI [5:0] Rx FIFO 0 Acknowledge Index 6 0 0 RXESC 0x2BC 32 RXESC NU58 [31:11] Reserved 21 11 RBDS [10:8] Rx Buffer data Field Size 3 8 NU57 [7:7] Reserved 1 7 F1DS [6:4] Rx FIFO 1 Data Field Size 3 4 NU56 [3:3] Reserved 1 3 F0DS [2:0] Rx FIFO 0 Data Field Size 3 0 0 TXBC 0x2C0 32 TXBC NU61 [31:31] Reserved 1 31 TFQM [30:30] Tx FIFO/Queue Mode 1 30 TFQS [29:24] Transmit FIFO/Queue Size 6 24 NU60 [23:22] Reserved 2 22 NDTB [21:16] Number of Dedicated Transmit Buffers 6 16 TBSA [15:2] Tx Buffers Start Address 14 2 NU59 [1:0] Reserved 2 0 0 TXFQS 0x2C4 32 TXFQS NU64 [31:22] Reserved 10 22 TFQF [21:21] Tx FIFO/Queue Full 1 21 TFQPI [20:16] Tx FIFO/Queue Put Index 5 16 NU63 [15:13] Reserved 3 13 TFGI [12:8] Tx Queue Get Index 5 8 NU62 [7:6] Reserved 2 6 TFFL [5:0] Tx FIFO Free Level 6 0 0 TXESC 0x2C8 32 TXESC NU65 [31:3] Reserved 29 3 TBDS [2:0] Tx Buffer Data Field Size 3 0 0 TXBRP 0x2CC 32 TXBRP TRP [31:0] Transmission Request Pending 32 0 0 TXBAR 0x2D0 32 TXBAR AR [31:0] Add request 32 0 0 TXBCR 0x2D4 32 TXBCR CR [31:0] Cancellation Request 32 0 0 TXBTO 0x2D8 32 TXBTO TO [31:0] Transmission Occurred 32 0 0 TXBCF 0x2DC 32 TXBCF CF [31:0] Cancellation Finished 32 0 0 TXBTIE 0x2E0 32 TXBTIE TIE [31:0] Transmission Interrupt Enable 32 0 0 TXBCIE 0x2E4 32 TXBCIE CFIE [31:0] Cancellation Finished Interrupt Enable 32 0 0 RES14 0x2E8 32 RES14 RES14 [31:0] Reserved 32 0 0 RES15 0x2EC 32 RES15 RES15 [31:0] Reserved 32 0 0 TXEFC 0x2F0 32 TXEFC NU68 [31:30] Reserved 2 30 EFWM [29:24] Event FIFO Watermark 6 24 NU67 [23:22] Reserved 2 22 EFS [21:16] Event FIFO Size 6 16 EFSA [15:2] Event FIFO Start Address 14 2 NU66 [1:0] Reserved 2 0 0 TXEFS 0x2F4 32 TXEFS NU72 [31:26] Reserved 6 26 TEFL [25:25] Tx Event FIFO Element Lost 1 25 EFF [24:24] Event FIFO Full 1 24 NU71 [23:21] Reserved 3 21 EFPI [20:16] Event FIFO Put Index 5 16 NU70 [15:13] Reserved 3 13 EFGI [12:8] Event FIFO Get Index 5 8 NU69 [7:6] Reserved 2 6 EFFL [5:0] Event FIFO FIll Level 6 0 0 TXEFA 0x2F8 32 TXEFA NU73 [31:5] Reserved 27 5 EFAI [4:0] Event FIFO Acknowledge Index 5 0 0 RES16 0x2FC 32 RES16 RES16 [31:0] Reserved 32 0 0 APP_CANECC 0x53F7FC00 0 784 registers APP_CANECC REV 0x0 32 Aggregator Revision Register SCHEME [31:30] Scheme 2 30 BU [29:28] bu 2 28 MODULE_ID [27:16] Module ID 12 16 REVRTL [15:11] RTL version 5 11 REVMAJ [10:8] Major version 3 8 CUSTOM [7:6] Custom version 2 6 REVMIN [5:0] Minor version 6 0 0 VECTOR 0x8 32 ECC Vector Register NU1 [31:25] Reserved 7 25 RD_SVBUS_DONE [24:24] Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. 1 24 RD_SVBUS_ADDR [23:16] Read address 8 16 RD_SVBUS [15:15] Write 1 to trigger a read on the serial VBUS. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. 1 15 NU0 [14:11] Reserved 4 11 ECC_VEC [10:0] Value written to select the corresponding ECC RAM for control or status 11 0 0 STAT 0xC 32 Misc Status NU2 [31:11] Reserved 21 11 NUM_RAMS [10:0] Indicates the number of RAMS serviced by the ECC aggregator 11 0 0 CTRL 0x14 32 CTRL NU3 [31:9] TI Internal : Reserved 23 9 CHECK TIMEOUT [8:8] TI Internal : Check timeout 1 8 CHECK PARITY [7:7] TI Internal : Check Parity 1 7 ERROR_ONCE [6:6] TI Internal : Force Error only once 1 6 FORCE_N_ROW [5:5] TI Internal : Force Error on any RAM read 1 5 FORCE_DED [4:4] TI Internal : Force Double Bit Error 1 4 FORCE_SEC [3:3] TI Internal : Force Single Bit Error 1 3 EN_RMW [2:2] TI Internal : Enable rmw 1 2 ECC_CHK [1:1] TI Internal : Enable ECC check 1 1 ECC_EN [0:0] TI Internal : Enable ECC 1 0 0 ERR_CTRL1 0x18 32 ERR_CTRL1 ECC_ROW [31:0] TI Internal : Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set 32 0 0 ERR_CTRL2 0x1C 32 ERR_CTRL2 ECC_BIT2 [31:16] TI Internal : Data bit that needs to be flipped if double bit error needs to be forced 16 16 ECC_BIT1 [15:0] TI Internal : Data bit that needs to be flipped when force_sec is set 16 0 0 ERR_STAT1 0x20 32 ERR_STAT1 ECC_BIT1_STS [31:16] TI Internal : Data bit that corresponds to the single-bit error 16 16 CLR_ECC_CTRL_REG [15:15] TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing. 1 15 CLR_ECC_PAR [14:13] TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing. 2 13 CLR_ECC_OTHER [12:12] TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing. 1 12 CLR_ECC_DED [11:10] TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing. 2 10 CLR_ECC_SEC [9:8] TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing. 2 8 ECC_CTRL_REG [7:7] TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing. 1 7 ECC_PAR [6:5] TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing. 2 5 ECC_OTHER [4:4] TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing. 1 4 ECC_DED [3:2] TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing. 2 2 ECC_SEC [1:0] TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing. 2 0 0 ERR_STAT2 0x24 32 ERR_STAT2 ECC_ROW [31:0] TI Internal : Row address where the single or double-bit error has occurred 32 0 0 ERR_STAT3 0x28 32 ERR_STAT3 NU6 [31:10] TI Internal : Reserved 22 10 CLR_TIMEOUT_PEND [9:9] TI Internal : Clear timeout pending 1 9 NU5 [8:2] TI Internal : Reserved 7 2 TIMEOUT_PEND [1:1] TI Internal : Timeout pending 1 1 NU4 [0:0] TI Internal : Reserved 1 0 0 SEC_EOI_REG 0x3C 32 EOI Register NU7 [31:1] Reserved 31 1 SEC_EOI_WR [0:0] EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0. 1 0 0 SEC_STATUS_REG0 0x40 32 Interrupt Status Register 0 NU8 [31:2] Reserved 30 2 CTRL_EDC_VBUSS_PEND [1:1] Interrupt Pending Status for ctrl_edc_vbuss_pend. 1 1 SEC_PEND [0:0] Interrupt Pending Status for msgmem_pend. 1 0 0 SEC_ENABLE_SET_REG0 0x80 32 Interrupt Enable Set Register 0 NU9 [31:2] Reserved 30 2 CTRL_EDC_VBUSS_ENABLE_SET [1:1] Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. 1 1 SEC_EN_SET [0:0] Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. 1 0 0 SEC_ENABLE_CLR_REG0 0xC0 32 Interrupt Enable Clear Register 0 NU10 [31:2] Reserved 30 2 CTRL_EDC_VBUSS_ENABLE_CLR [1:1] Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0. 1 1 SEC_EN_CLR [0:0] Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0. 1 0 0 DED_EOI_REG 0x13C 32 EOI Register NU11 [31:1] Reserved 31 1 DED_EOI_WR [0:0] EOI Register. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. This bit is self clearing, reading this bit will return 0. 1 0 0 DED_STATUS_REG0 0x140 32 Interrupt Status Register 0 NU12 [31:2] Reserved 30 2 CTRL_EDC_VBUSS_PEND [1:1] Interrupt Pending Status for ctrl_edc_vbuss_pend. 1 1 DED_PEND [0:0] Interrupt Pending Status for msgmem_pend. 1 0 0 DED_ENABLE_SET_REG0 0x180 32 Interrupt Enable Set Register 0 NU13 [31:2] Reserved 30 2 CTRL_EDC_VBUSS_ENABLE_SET [1:1] Interrupt Enable Set Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. 1 1 DED_EN_SET [0:0] Interrupt Enable Set Register for msgmem_pend. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. 1 0 0 DED_ENABLE_CLR_REG0 0x1C0 32 Interrupt Enable Clear Register 0 NU14 [31:2] Reserved 30 2 CTRL_EDC_VBUSS_ENABLE_CLR [1:1] Interrupt Enable Clear Register for ctrl_edc_vbuss_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0. 1 1 DED_EN_CLR [0:0] Interrupt Enable Clear Register for msgmem_pend. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0. 1 0 0 AGGR_ENABLE_SET 0x200 32 AGGR interrupt enable set Register NU15 [31:2] Reserved 30 2 TIMEOUT [1:1] Interrupt Enable Set Register for svbus timeout errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. 1 1 PARITY [0:0] Interrupt Enable Set Register for parity errors. Writing 1 to any bit will set the corresponding bit. Reads do not alter the value of the field. 1 0 0 AGGR_ENABLE_CLR 0x204 32 AGGR interrupt enable clear Register NU16 [31:2] Reserved 30 2 TIMEOUT [1:1] Interrupt Enable Clear for svbus timeout errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0. 1 1 PARITY [0:0] Interrupt Enable Clear for parity errors. Writing 1 to any bit will clear the corresponding bits. Reads do not alter the value of the field. Reading this bit will return 0. 1 0 0 AGGR_STATUS_SET 0x208 32 AGGR interrupt status set Register NU17 [31:4] Reserved 28 4 TIMEOUT [3:2] Interrupt status set for svbus timeout errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field. 2 2 PARITY [1:0] Interrupt status set for parity errors. A write to increment field. Writing a value to this field increment the field value by the value written. Reads do not alter the value of the field. 2 0 0 AGGR_STATUS_CLR 0x20C 32 AGGR interrupt status clear Register NU18 [31:4] Reserved 28 4 TIMEOUT [3:2] Interrupt status clear for svbus timeout errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field. 2 2 PARITY [1:0] Interrupt status clear for parity errors. A write to decrement field. Writing a value to this field decrements the field value by the value written. Reads do not alter the value of the field. 2 0 0 TPTC_A0 0x54000000 0 860 registers Register test environment PID 0x0 32 Peripheral ID Register [31:30] PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1. 2 30 [27:16] Function indicates a software compatible module family. 12 16 [15:11] RTL Version 5 11 [10:8] Major Revision 3 8 [7:6] Custom revision field: Not used on this version of EDMA. 2 6 [5:0] Minor Revision 6 0 0 TCCFG 0x4 32 TC Configuration Register [9:8] Dst Register FIFO Depth Parameterization 2 8 [5:4] Bus Width Parameterization 2 4 [2:0] Fifo Size Parameterization 3 0 0 TCSTAT 0x100 32 TC Status Register [13:12] Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3 2 12 [8:8] Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy. 1 8 [6:4] Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter. 3 4 [2:2] Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands. 1 2 [1:1] Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request. 1 1 [0:0] Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set. 1 0 0 INTSTAT 0x104 32 Interrupt Status Register [1:1] TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit. 1 1 [0:0] Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit. 1 0 0 INTEN 0x108 32 Interrupt Enable Register [1:1] TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation 1 1 [0:0] Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation 1 0 0 INTCLR 0x10C 32 Interrupt Clear Register [1:1] TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit 1 1 [0:0] Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit 1 0 0 INTCMD 0x110 32 Interrupt Command Register [1:1] Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 ERRSTAT 0x120 32 Error Status Register [3:3] MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded. 1 3 [2:2] TR Error:#br#TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded. 1 2 [0:0] Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]. 1 0 0 ERREN 0x124 32 Error Enable Register [3:3] Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation. 1 3 [2:2] Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation. 1 2 [0:0] Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation. 1 0 0 ERRCLR 0x128 32 Error Clear Register [3:3] Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register. 1 3 [2:2] Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register. 1 2 [0:0] Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register. 1 0 0 ERRDET 0x12C 32 Error Details Register [17:17] Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 17 [16:16] Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 16 [13:8] Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error. 6 8 [3:0] Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec. 4 0 0 ERRCMD 0x130 32 Error Command Register [1:1] Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 RDRATE 0x140 32 Read Rate Register [2:0] Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC. 3 0 0 POPT 0x200 32 Prog Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 PSRC 0x204 32 Prog Set Src Address [31:0] Source address for Program Register Set 32 0 0 PCNT 0x208 32 Prog Set Count [31:16] B-Dimension count. Number of arrays to be transferred where each array is ACNT in length. 16 16 [15:0] A-Dimension count. Number of bytes to be transferred in first dimension. 16 0 0 PDST 0x20C 32 Prog Set Dst Address [31:0] Destination address for Program Register Set 32 0 0 PBIDX 0x210 32 Prog Set B-Dim Idx [31:16] Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 PMPPRXY 0x214 32 Prog Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SAOPT 0x240 32 Src Actv Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 SASRC 0x244 32 Src Actv Set Src Address [31:0] Source address for Source Active Register Set 32 0 0 SACNT 0x248 32 Src Actv Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred in first dimension. 23 0 0 SADST 0x24C 32 Src Actv Set Dst Address [31:0] Destination address for Source Active Register Set 32 0 0 SABIDX 0x250 32 Src Actv Set B-Dim Idx [31:16] Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 SAMPPRXY 0x254 32 Src Actv Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SACNTRLD 0x258 32 Src Actv Set Cnt Reload [15:0] A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 SASRCBREF 0x25C 32 Src Actv Set Src Addr B-Reference [31:0] Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 SADSTBREF 0x260 32 Src Actv Set Dst Addr B-Reference [31:0] Dst address reference is not applicable for Src Active Register Set. Reads return 0x0. 32 0 0 SABCNT 0x264 32 Src Actv Set B-Count [15:0] B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete. 16 0 0 DFCNTRLD 0x280 32 Dst FIFO Set Cnt Reload [15:0] A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 DFSRCBREF 0x284 32 Dst FIFO Set Src Addr B-Reference [31:0] Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 DFOPT0 0x300 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC0 0x304 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT0 0x308 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST0 0x30C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX0 0x310 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY0 0x314 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT0 0x318 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 DFOPT1 0x340 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC1 0x344 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT1 0x348 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST1 0x34C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX1 0x350 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY1 0x354 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT1 0x358 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 TPTC_A1 0x54010000 0 860 registers Register test environment PID 0x0 32 Peripheral ID Register [31:30] PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1. 2 30 [27:16] Function indicates a software compatible module family. 12 16 [15:11] RTL Version 5 11 [10:8] Major Revision 3 8 [7:6] Custom revision field: Not used on this version of EDMA. 2 6 [5:0] Minor Revision 6 0 0 TCCFG 0x4 32 TC Configuration Register [9:8] Dst Register FIFO Depth Parameterization 2 8 [5:4] Bus Width Parameterization 2 4 [2:0] Fifo Size Parameterization 3 0 0 TCSTAT 0x100 32 TC Status Register [13:12] Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3 2 12 [8:8] Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy. 1 8 [6:4] Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter. 3 4 [2:2] Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands. 1 2 [1:1] Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request. 1 1 [0:0] Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set. 1 0 0 INTSTAT 0x104 32 Interrupt Status Register [1:1] TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit. 1 1 [0:0] Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit. 1 0 0 INTEN 0x108 32 Interrupt Enable Register [1:1] TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation 1 1 [0:0] Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation 1 0 0 INTCLR 0x10C 32 Interrupt Clear Register [1:1] TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit 1 1 [0:0] Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit 1 0 0 INTCMD 0x110 32 Interrupt Command Register [1:1] Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 ERRSTAT 0x120 32 Error Status Register [3:3] MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded. 1 3 [2:2] TR Error:#br#TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded. 1 2 [0:0] Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]. 1 0 0 ERREN 0x124 32 Error Enable Register [3:3] Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation. 1 3 [2:2] Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation. 1 2 [0:0] Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation. 1 0 0 ERRCLR 0x128 32 Error Clear Register [3:3] Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register. 1 3 [2:2] Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register. 1 2 [0:0] Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register. 1 0 0 ERRDET 0x12C 32 Error Details Register [17:17] Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 17 [16:16] Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 16 [13:8] Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error. 6 8 [3:0] Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec. 4 0 0 ERRCMD 0x130 32 Error Command Register [1:1] Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 RDRATE 0x140 32 Read Rate Register [2:0] Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC. 3 0 0 POPT 0x200 32 Prog Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 PSRC 0x204 32 Prog Set Src Address [31:0] Source address for Program Register Set 32 0 0 PCNT 0x208 32 Prog Set Count [31:16] B-Dimension count. Number of arrays to be transferred where each array is ACNT in length. 16 16 [15:0] A-Dimension count. Number of bytes to be transferred in first dimension. 16 0 0 PDST 0x20C 32 Prog Set Dst Address [31:0] Destination address for Program Register Set 32 0 0 PBIDX 0x210 32 Prog Set B-Dim Idx [31:16] Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 PMPPRXY 0x214 32 Prog Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SAOPT 0x240 32 Src Actv Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 SASRC 0x244 32 Src Actv Set Src Address [31:0] Source address for Source Active Register Set 32 0 0 SACNT 0x248 32 Src Actv Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred in first dimension. 23 0 0 SADST 0x24C 32 Src Actv Set Dst Address [31:0] Destination address for Source Active Register Set 32 0 0 SABIDX 0x250 32 Src Actv Set B-Dim Idx [31:16] Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 SAMPPRXY 0x254 32 Src Actv Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SACNTRLD 0x258 32 Src Actv Set Cnt Reload [15:0] A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 SASRCBREF 0x25C 32 Src Actv Set Src Addr B-Reference [31:0] Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 SADSTBREF 0x260 32 Src Actv Set Dst Addr B-Reference [31:0] Dst address reference is not applicable for Src Active Register Set. Reads return 0x0. 32 0 0 SABCNT 0x264 32 Src Actv Set B-Count [15:0] B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete. 16 0 0 DFCNTRLD 0x280 32 Dst FIFO Set Cnt Reload [15:0] A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 DFSRCBREF 0x284 32 Dst FIFO Set Src Addr B-Reference [31:0] Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 DFOPT0 0x300 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC0 0x304 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT0 0x308 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST0 0x30C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX0 0x310 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY0 0x314 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT0 0x318 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 DFOPT1 0x340 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC1 0x344 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT1 0x348 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST1 0x34C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX1 0x350 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY1 0x354 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT1 0x358 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 APP_CRC 0x54020000 0 328 registers APP_CRC CRC_CTRL0 0x0 32 Contains sw reset control bit to reset PSA NU12 [31:31] Reserved 1 31 NU11 [30:30] Reserved 1 30 NU10 [29:29] Reserved 1 29 NU9 [28:27] Reserved 2 27 NU8 [26:25] Reserved 2 25 NU7 [24:24] Reserved 1 24 NU6 [23:23] Reserved 1 23 NU5 [22:22] Reserved 1 22 NU4 [21:21] Reserved 1 21 NU3 [20:19] Reserved 2 19 NU2 [18:17] Reserved 2 17 NU1 [16:16] Reserved 1 16 CH2_CRC_SEL2 [15:15] Refer "CH2_DW_SEL" field description 1 15 CH2_BYTE_SWAP [14:14] BYTE SWAP Enable across Data Size 0 – Byte Swap Disabled 1 – Byte Swap enabled. 1 14 CH2_BIT_SWAP [13:13] msb/lsb SWAPPING 0 – msb (most significant bit First) 1 – lsb (least significant bit First) 1 13 CH2_CRC_SEL [12:11] CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL[1:0]} 000 – CRC-64 001 - CRC-16 010 – CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4 2 11 CH2_DW_SEL [10:9] CRC Data Size select. 000 – Not Supported 001 - 16 bit Data Size 010 – 32 Bit Data Size 2 9 CH2_PSA_SWREST [8:8] Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ‘0’. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset 1 8 CH1_CRC_SEL2 [7:7] Refer "CH1_DW_SEL" field description 1 7 CH1_BYTE_SWAP [6:6] BYTE SWAP Enable across Data Size 0 – Byte Swap Disabled 1 – Byte Swap enabled. 1 6 CH1_BIT_SWAP [5:5] msb/lsb SWAPPING 0 – msb (most significant bit First) 1 – lsb (least significant bit First) 1 5 CH1_CRC_SEL [4:3] CRC type select. {CH1_CRC_SEL2,CH1_CRC_SEL[1:0]} 000 – CRC-64 001 - CRC-16 010 – CRC-32 100 - VDA CAN, SAE-J1850 CRC-8 101 - H2F, Autosar 4.0 110 - CASTAGNOLI, iSCSI 111 / 011 - E2E Profile 4 2 3 CH1_DW_SEL [2:1] CRC Data Size select. 000 – Not Supported 001 - 16 bit Data Size 010 – 32 Bit Data Size 2 1 CH1_PSA_SWREST [0:0] Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a ‘0’. 0 = PSA Signature Register not reset 1 = PSA Signature Register reset 1 0 0 CRC_CTRL1 0x8 32 Contains power down control bit Reserved1 [31:1] Reserved 31 1 PWDN [0:0] Power Down. When set, MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode 1 = MCRC is in power down mode 1 0 0 CRC_CTRL2 0x10 32 Contains channel mode, data trace enable control bits Reserved5 [31:26] Reserved 6 26 NU14 [25:24] Reserved 2 24 Reserved4 [23:18] Reserved 6 18 NU13 [17:16] Reserved 2 16 Reserved3 [15:10] Reserved 6 10 CH2_MODE [9:8] Channel 2 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode 2 8 Reserved2 [7:5] Reserved 3 5 CH1_TRACEEN [4:4] Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. The channel snoops on the CPU VBUSM, ITCM, DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When suspend is on, the PSA Signature Register does not compress any read data on these buses. 0 = Data Trace disable 1 = Data Trace enable 1 4 Reserved1 [3:2] Reserved 2 2 CH1_MODE [1:0] Channel 1 Mode: 0 0 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register 0 1 = AUTO mode 1 0 = reserved 1 1 = Full-CPU mode 2 0 0 CRC_INTS 0x18 32 Write one to a bit to enable a interrupt Reserved5 [31:29] Reserved 3 29 NU22 [28:28] Reserved 1 28 NU21 [27:27] Reserved 1 27 NU20 [26:26] Reserved 1 26 NU19 [25:25] Reserved 1 25 Reserved4 [24:21] Reserved 4 21 NU18 [20:20] Reserved 1 20 NU17 [19:19] Reserved 1 19 NU16 [18:18] Reserved 1 18 NU15 [17:17] Reserved 1 17 Reserved3 [16:13] Reserved 4 13 CH2_TIMEOUTENS [12:12] Channel 2 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable 1 12 CH2_UNDERENS [11:11] Channel 2 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable 1 11 CH2_OVERENS [10:10] Channel 2 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable 1 10 CH2_CRCFAILENS [9:9] Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable 1 9 Reserved2 [8:5] Reserved 4 5 CH1_TIMEOUTENS [4:4] Channel 1 Timeout Interrupt Enable Bit. Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable 1 4 CH1_UNDERENS [3:3] Channel 1 Underrun Interrupt Enable Bit. Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable 1 3 CH1_OVERENS [2:2] Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable 1 2 CH1_CRCFAILENS [1:1] Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable 1 1 Reserved1 [0:0] Reserved 1 0 0 CRC_INTR 0x20 32 Write one to a bit to disable a interrupt Reserved5 [31:29] Reserved 3 29 NU30 [28:28] Reserved 1 28 NU29 [27:27] Reserved 1 27 NU28 [26:26] Reserved 1 26 NU27 [25:25] Reserved 1 25 Reserved4 [24:21] Reserved 4 21 NU26 [20:20] Reserved 1 20 NU25 [19:19] Reserved 1 19 NU24 [18:18] Reserved 1 18 NU23 [17:17] Reserved 1 17 Reserved3 [16:13] Reserved 4 13 CH2_TIMEOUTENR [12:12] Channel 2 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable 1 12 CH2_UNDERENR [11:11] Channel 2 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable 1 11 CH2_OVERENR [10:10] Channel 2 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable 1 10 CH2_CRCFAILENR [9:9] Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable 1 9 Reserved2 [8:5] Reserved 4 5 CH1_TIMEOUTENR [4:4] Channel 1 Timeout Interrupt Disable Bit. Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt disable 1 4 CH1_UNDERENR [3:3] Channel 1 Underrun Interrupt Disable Bit. Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/dis- able). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt disable 1 3 CH1_OVERENR [2:2] Channel 1 Overrun Interrupt Disable Bit. Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt disable 1 2 CH1_CRCFAILENR [1:1] Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt disable 1 1 Reserved1 [0:0] Reserved 1 0 0 CRC_STATUS_REG 0x28 32 Contains interrupt flags for different types of interrupt Reserved5 [31:29] Reserved 3 29 NU38 [28:28] Reserved 1 28 NU37 [27:27] Reserved 1 27 NU36 [26:26] Reserved 1 26 NU35 [25:25] Reserved 1 25 Reserved4 [24:21] Reserved 4 21 NU34 [20:20] Reserved 1 20 NU33 [19:19] Reserved 1 19 NU32 [18:18] Reserved 1 18 NU31 [17:17] Reserved 1 17 Reserved3 [16:13] Reserved 4 13 CH2_TIMEOUT [12:12] Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active 1 12 CH2_UNDER [11:11] Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active 1 11 CH2_OVER [10:10] Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active 1 10 CH2_CRCFAIL [9:9] Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active 1 9 Reserved2 [8:5] Reserved 4 5 CH1_TIMEOUT [4:4] Channel 1 CRC Timeout Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active 1 4 CH1_UNDER [3:3] Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active 1 3 CH1_OVER [2:2] Channel 1 CRC Overrun Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active 1 2 CH1_CRCFAIL [1:1] Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a ’1’ to it only. Writing ’0’ has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active 1 1 Reserved1 [0:0] Reserved 1 0 0 CRC_INT_OFFSET_REG 0x30 32 Contains the interrupt offset vector address Reserved1 [31:8] Reserved 24 8 OFSTREG [7:0] CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register auto- matically clear the respective interrupt flag. Please reference Table 1–3. for details. 8 0 0 CRC_BUSY 0x38 32 Contains the busy flag for each channel Reserved4 [31:25] Reserved 7 25 NU40 [24:24] Reserved 1 24 Reserved3 [23:17] Reserved 7 17 NU39 [16:16] Reserved 1 16 Reserved2 [15:9] Reserved 7 9 Ch2_BUSY [8:8] Ch2_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed. 1 8 Reserved1 [7:1] Reserved 7 1 CH1_BUSY [0:0] CH1_BUSY. During AUTO mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed. 1 0 0 CRC_PCOUNT_REG1 0x40 32 Channel 1 preload register for the pattern count Reserved1 [31:20] Reserved 12 20 CRC_PAT_COUNT1 [19:0] Channel 1 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed. 20 0 0 CRC_SCOUNT_REG1 0x44 32 Channel 1 preload register for the sector count Reserved1 [31:16] Reserved 16 16 CRC_SEC_COUNT1 [15:0] Channel 1 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory. 16 0 0 CRC_CURSEC_REG1 0x48 32 Channel 1 current sector register contains the sector number which causes CRC failure Reserved1 [31:16] Reserved 16 16 CRC_CURSEC1 [15:0] Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number. 16 0 0 CRC_WDTOPLD1 0x4C 32 Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer Reserved1 [31:24] Reserved 8 24 CRC_WDTOPLD1 [23:0] Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns. 24 0 0 CRC_BCTOPLD1 0x50 32 Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time Reserved1 [31:24] Reserved 8 24 CRC_BCTOPLD1 [23:0] Channel 1 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated. 24 0 0 PSA_SIGREGL1 0x60 32 Channel 1 PSA signature low register PSASIG1_31_0 [31:0] Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register. 32 0 0 PSA_SIGREGH1 0x64 32 Channel 1 PSA signature high register PSA_SIG1_63_32 [31:0] Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register. 32 0 0 CRC_REGL1 0x68 32 Channel 1 CRC value low register CRC1_31_0 [31:0] Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] regis- ter. 32 0 0 CRC_REGH1 0x6C 32 Channel 1 CRC value high register CRC1_63_32 [31:0] Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] regis- ter. 32 0 0 PSA_SECSIGREGL1 0x70 32 Channel 1 PSA sector signature low regis-ter PSASECSIG1_31_0 [31:0] Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register. 32 0 0 PSA_SECSIGREGH1 0x74 32 Channel 1 PSA sector signature high regis-ter PSASECSIG1_63_32 [31:0] Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register. 32 0 0 RAW_DATAREGL1 0x78 32 Channel 1 un-compressed raw data low register RAW_DATA1_31_0 [31:0] Channel 1 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data. 32 0 0 RAW_DATAREGH1 0x7C 32 Channel 1 un-compressed raw data high register RAW_DATA1_63_32 [31:0] Channel 1 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data. 32 0 0 CRC_PCOUNT_REG2 0x80 32 Channel 2 preload register for the pattern count Reserved1 [31:20] Reserved 12 20 CRC_PAT_COUNT2 [19:0] Channel 2 Pattern Counter Preload Register. This register con- tains the number of data patterns in one sector to be compressed before a CRC is performed. 20 0 0 CRC_SCOUNT_REG2 0x84 32 Channel 2 preload register for the sector count Reserved1 [31:16] Reserved 16 16 CRC_SEC_COUNT2 [15:0] Channel 2 Sector Counter Preload Register. This register con- tains the number of sectors in one block of memory. 16 0 0 CRC_CURSEC_REG2 0x88 32 Channel 2 current sector register contains the sector number which causes CRC fail-ure Reserved1 [31:16] Reserved 16 16 CRC_CURSEC2 [15:0] Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erro- neous sector number. 16 0 0 CRC_WDTOPLD2 0x8C 32 Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer Reserved1 [31:24] Reserved 8 24 CRC_WDTOPLD2 [23:0] Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns. 24 0 0 CRC_BCTOPLD2 0x90 32 Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time Reserved1 [31:24] Reserved 8 24 CRC_BCTOPLD2 [23:0] Channel 2 Block Complete Timeout Counter Preload Regis- ter. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated. 24 0 0 PSA_SIGREGL2 0xA0 32 Channel 2 PSA signature low register PSASIG2_31_0 [31:0] Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register. 32 0 0 PSA_SIGREGH2 0xA4 32 Channel 2 PSA signature high register PSA_SIG2_63_32 [31:0] Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register. 32 0 0 CRC_REGL2 0xA8 32 Channel 2 CRC value low register CRC2_31_0 [31:0] Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] regis- ter. 32 0 0 CRC_REGH2 0xAC 32 Channel 2 CRC value high register CRC2_63_32 [31:0] Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] regis- ter. 32 0 0 PSA_SECSIGREGL2 0xB0 32 Channel 2 PSA sector signature low regis-ter PSASECSIG2_31_0 [31:0] Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register. 32 0 0 PSA_SECSIGREGH2 0xB4 32 Channel 2 PSA sector signature high regis-ter PSASECSIG2_63_32 [31:0] Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register. 32 0 0 RAW_DATAREGL2 0xB8 32 Channel 2 un-compressed raw data low register RAW_DATA2_31_0 [31:0] Channel 2 Raw Data Low Register. This register contains bit 31:0 of the un-compressed raw data. 32 0 0 RAW_DATAREGH2 0xBC 32 Channel 2 un-compressed raw data high Register RAW_DATA2_63_32 [31:0] Channel 2 Raw Data High Register. This register contains bit 63:32 of the un-compressed raw data. 32 0 0 CRC_PCOUNT_REG3 0xC0 32 Channel 3 preload register for the pattern count Reserved1 [31:20] Reserved 12 20 NU41 [19:0] Reserved 20 0 0 CRC_SCOUNT_REG3 0xC4 32 Channel 3 preload register for the sector count Reserved1 [31:16] Reserved 16 16 NU42 [15:0] Reserved 16 0 0 CRC_CURSEC_REG3 0xC8 32 Channel 3 current sector register contains the sector number which causes CRC fail-ure Reserved1 [31:16] Reserved 16 16 NU43 [15:0] Reserved 16 0 0 CRC_WDTOPLD3 0xCC 32 Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer Reserved1 [31:24] Reserved 8 24 NU44 [23:0] Reserved 24 0 0 CRC_BCTOPLD3 0xD0 32 Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time Reserved1 [31:24] Reserved 8 24 NU45 [23:0] Reserved 24 0 0 PSA_SIGREGL3 0xE0 32 Channel 3 PSA signature low register NU46 [31:0] Reserved 32 0 0 PSA_SIGREGH3 0xE4 32 Channel 3 PSA signature high register NU47 [31:0] Reserved 32 0 0 CRC_REGL3 0xE8 32 Channel 3 CRC value low register NU48 [31:0] Reserved 32 0 0 CRC_REGH3 0xEC 32 Channel 3 CRC value high register NU49 [31:0] Reserved 32 0 0 PSA_SECSIGREGL3 0xF0 32 Channel 3 PSA sector signature low regis-ter NU50 [31:0] Reserved 32 0 0 PSA_SECSIGREGH3 0xF4 32 Channel 3 PSA sector signature high regis-ter NU51 [31:0] Reserved 32 0 0 RAW_DATAREGL3 0xF8 32 Channel 3 un-compressed raw data low register NU52 [31:0] Reserved 32 0 0 RAW_DATAREGH3 0xFC 32 Channel 3 un-compressed raw data high Register NU53 [31:0] Reserved 32 0 0 CRC_PCOUNT_REG4 0x100 32 Channel 4 preload register for the pattern count Reserved1 [31:20] Reserved 12 20 NU54 [19:0] Reserved 20 0 0 CRC_SCOUNT_REG4 0x104 32 Channel 4 preload register for the sector count Reserved1 [31:16] Reserved 16 16 NU55 [15:0] Reserved 16 0 0 CRC_CURSEC_REG4 0x108 32 Channel 4 current sector register contains the sector number which causes CRC fail-ure Reserved1 [31:16] Reserved 16 16 NU56 [15:0] Reserved 16 0 0 CRC_WDTOPLD4 0x10C 32 Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer Reserved1 [31:24] Reserved 8 24 NU57 [23:0] Reserved 24 0 0 CRC_BCTOPLD4 0x110 32 Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time Reserved1 [31:24] Reserved 8 24 NU58 [23:0] Reserved 24 0 0 PSA_SIGREGL4 0x120 32 Channel 4 PSA signature low register NU59 [31:0] Reserved 32 0 0 PSA_SIGREGH4 0x124 32 Channel 4 PSA signature high register NU60 [31:0] Reserved 32 0 0 CRC_REGL4 0x128 32 Channel 4 CRC value low register NU61 [31:0] Reserved 32 0 0 CRC_REGH4 0x12C 32 Channel 4 CRC value high register NU62 [31:0] Reserved 32 0 0 PSA_SECSIGREGL4 0x130 32 Channel 4 PSA sector signature low regis-ter NU63 [31:0] Reserved 32 0 0 PSA_SECSIGREGH4 0x134 32 Channel 4 PSA sector signature high regis-ter NU64 [31:0] Reserved 32 0 0 RAW_DATAREGL4 0x138 32 Channel 4 un-compressed raw data low register NU65 [31:0] Reserved 32 0 0 RAW_DATAREGH4 0x13C 32 Channel 4 un-compressed raw data high Register NU66 [31:0] Reserved 32 0 0 MCRC_BUS_SEL 0x140 32 Disables either or all tracing of data buses NU67 [31:3] Reserved 29 3 MEn [2:2] MEn. Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled 1 2 DTCMEn [1:1] DTCMEn. Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled 1 1 ITCMEn [0:0] ITCMEn. Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled 1 0 0 MCRC_RESERVED 0x144 32 0x144 to 0x1FF is reserved area. NU68 [31:0] 0x144 to 0x1FF is reserved area. 32 0 0 HWA_CFG 0x55010000 0 984 registers HWA_CFG HWACCREG1 0x0 32 HWACCREG1 NU2 19 13 ACCDYNCLKEN_LEVEL2 [12:12] Level 2 dynamic clock-gating control :- Setting this register bit to 1 will lead to further power saving by disabling clock during FSM wait state. 1 12 ACCDYNCLKEN [11:11] Dynamic Clock-gating Control:Setting this register bit to 1 enables the capability to clock gate the Radar Accelerator core IPs (FFT and CFAR-CA datapath,CFAR-OS datapath, memory compression datapath) based on the ParamSet being executed. 1 11 FFT1DEN [10:10] ADC buffer sharing mode This register is relevant where the Radar Hardware Accelerator is included in a single device along with the mmWave RF front-end. In such a case, during active chirp transmission and inline 1st dimension FFT processing, the ACCEL_MEM0 and ACCEL_MEM1 memories of the accelerator are shared as ping-pong ADC buffers. This register bit needs to be set during this time, so that while the Digital Front End writes ADC samples to the ping buffer, the accelerator automatically accesses (only) the pong buffer, and vice versa. At the end of the active transmission portion of a frame, this bit can be cleared, so that the accelerator has access to all the four local memories independently. 1 10 NU1 1 9 ACCRESET [8:6] Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator. The assertion of these register bits by the main processor will bring the Accelerator Engine to a known reset state. This is mostly applicable for resetting the accelerator in case of unexpected behavior. The sequence to be followed in case software reset is to write 111b to this register and then a 000b 3 6 ACCCLKEN [5:3] Clock-gating Control: This register bit controls the enable/disable for the clock of the Radar Accelerator. This register bit can be set to 0 to clock-gate the accelerator when not using the accelerator. Before enabling the accelerator or before configuring the registers of accelerator, this register bit should be set to 111b first, so that the clock is available. 3 3 ACCENABLE [2:0] Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state. 3 0 0 HWACCREG2 0x4 32 HWACCREG2 NU 16 16 DMA2ACCTRIG [15:0] DMA trigger register: This register is relevant whenever DMA triggered mode is used (i.e., TRIGMODE = 011b). Whenever a DMA channel has finished copying input samples into the local memory of the accelerator and wants to trigger the accelerator, the procedure to follow is to use a second linked DMA channel to write a 16-bit one-hot signature into this register to trigger the accelerator. In DMA triggered mode, the State Machine keeps monitoring this 16-bit register and waits as long as a specific bit (see DMA2ACC_CHANNEL_TRIGSRC) in this register is zero. The second linked DMA channel writes a one-hot signature that sets the specific bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set. 16 0 0 HWACCREG3 0x8 32 HWACCREG3 CM42DMATRIG [31:16] Override accelerator Trigger to DMA.Can be used for triggering the first and second DMA transfer thorugh processor 16 16 NU 15 1 CM42ACCTRIG [0:0] Software trigger bit: This register bit is relevant whenever software triggered mode is used (i.e., TRIGMODE = 001b). The main processor software can set this register bit, so that the State Machine gets triggered and starts the accelerator operations for that parameter-set. 1 0 0 HWACCREG4 0xC 32 HWACCREG4 SPARE [31:0] Spare register 32 0 0 HWACCREG5 0x10 32 HWACCREG5 BPMPATTERNMSB [31:0] BPM pattern MSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled 32 0 0 HWACCREG6 0x14 32 HWACCREG6 BPMPATTERNLSB [31:0] BPM pattern LSB: Specifies the BPM pattern to be used to multiply the input samples if BPM removal is enabled 32 0 0 HWACCREG7 0x18 32 HWACCREG7 NU3 7 25 STG1LUTSELWR [24:24] Select Window RAM or Internal RAM: The Internal RAM for Vector Multiplication mode is mapped to the same address space as the Window RAM. Hence, this register bit is required to specify which of these two needs to be selected, when loading the co-efficients via DMA or M4. 0 - Window RAM is selected 1 - Internal RAM for Vector Multiplication mode is selected. Keep this register bit as 0 always, except during the period when Internal RAM needs to be loaded. 1 24 NU2 7 17 DITHERTWIDEN [16:16] Twiddle factor dithering enable: This register-bit is used to enable/disable dithering of twiddle factors in the FFT. 1 16 NU1 6 10 BPMRATE [9:0] BPM rate: Specifies the number of input samples corresponding to each BPM bit. Minimum valid value for this register is 1. 10 0 0 HWACCREG8 0x1C 32 HWACCREG8 NU2 3 29 FFTSUMDIV [28:24] Right-shifting for Sum Statistic: This register specifies how many LSBs to drop to convert the sum statistics to 24-bit value going to the Output Formatter 5 24 NU1 24 0 0 HWACCREG11 0x20 32 HWACCREG11 LFSRLOAD [31:31] To load the LFSR seed, a pulse signal needs to be provided, by writing a 1 to the LFSR_LOAD register-bit. Self clearing 1 31 NU 2 29 LFSRSEED [28:0] LFSR seed value (random pattern) for twiddle factor dithering, 29 0 0 HWACCREG12 0x24 32 HWACCREG12 NU2 7 25 ACC_TRIGGER_IN_CLR [24:24] Clear trigger status read-only register: This register-bit when set clears the trigger status register ACC_TRIG_IN_STAT described above 1 24 NU1 5 19 ACC_TRIGGER_IN_STAT [18:0] Debug register for trigger status: This is a read-only status register, which indicates the trigger status of the accelerator, i.e., whether a specific DMA trigger or a Ping-pong trigger or a SW trigger was ever received (refer TRIGMODE in HW_ACC_PARAM register set). The MSB 16 bits of this register indicate whether a trigger was received via DMA trigger method. The next two bits (i.e., bit indices 2 and 1) indicate the status of DFE ping-pong switch-based trigger and SW trigger respectively. The LSB bit is always 1 and can be ignored {DMA2ACCTRIG[15:0],adc_buffer_done,CM42ACCTRIG,1} 19 0 0 HWACCREG13 0x28 32 HWACCREG13 NU 14 18 CFAR_THRESH [17:0] CFAR Threshold scale factor: This value is used to either multiply or add to the surrounding noise average to determine the threshold used for detection of the present cell under test. If logarithmic CFAR mode is disabled (i.e., in magnitude or magnitude-squared mode), then the register value is multiplied with the surrounding noise average to determine the threshold, else it is added to the surrounding noise average. In the former case, this 18-bit register is interpreted as a 14.4 value. In the latter case (i.e., logarithmic mode), the 18-bit register is interpreted as a 7.11 value. 18 0 0 HWACCREG14 0x2C 32 HWACCREG14 PARAMDONESTAT [31:0] Parameter-set done status: This read-only status register can be used by the main processor to see which parameter-sets are complete that led to the interrupt to the main processor. The individual bits in this 32-bit status register indicate which of the 32 parameter-sets have completed. 32 0 0 HWACCREG15 0x30 32 HWACCREG15 PARAMDONECLR [31:0] Status bits in PARAMDONESTAT are not automatically cleared, but they can be individually cleared by writing to 32-bit register PARAMDONECLR. 32 0 0 CFAR_DET_THR 0x34 32 CFAR_DET_THR NU 8 24 CFAR_DET_THR [23:0] This register is used to specify the threshold used for the detection of the present cell under test during CFAR-CA mode when number of samples for left side and right side noise averaging is 0. 24 0 0 MAX1VALUE 0x38 32 MAX1VALUE NU 8 24 MAX1VALUE [23:0] Max value: These registers contain the max value on a per-iteration basis. These registers are meaningful only when Magnitude or Log-Magnitude is enabled. Only the max values for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set). 24 0 0 MAX1INDEX 0x3C 32 MAX1INDEX NU 20 12 MAX1INDEX [11:0] Max index: These registers contain the max index on a per-iteration basis, corresponding to each max value in the MAXn_VALUE registers. 12 0 0 ISUM1LSB 0x40 32 ISUM1LSB ISUM1LSB [31:0] Sum statistics: These registers contain the sum of the I outputs and Q outputs on a per-iteration basis. Only the statistics for up to four iterations are recorded in these registers. For larger number of iterations, use Statistics output mode (FFT_OUT_MODE in HW_ACC_PARAM register set). 32 0 0 ISUM1MSB 0x44 32 ISUM1MSB NU 28 4 ISUM1MSB [3:0] Refer ISUM1LSB 4 0 0 QSUM1LSB 0x48 32 QSUM1LSB QSUM1LSB [31:0] Refer ISUM1LSB 32 0 0 QSUM1MSB 0x4C 32 QSUM1MSB NU 28 4 QSUM1MSB [3:0] Refer ISUM1LSB 4 0 0 MAX2VALUE 0x50 32 MAX2VALUE NU 8 24 MAX2VALUE [23:0] Refer MAX1VALUE 24 0 0 MAX2INDEX 0x54 32 MAX2INDEX NU 20 12 MAX2INDEX [11:0] Refer MAX1INDEX 12 0 0 ISUM2LSB 0x58 32 ISUM2LSB ISUM2LSB [31:0] Refer ISUM1LSB 32 0 0 ISUM2MSB 0x5C 32 ISUM2MSB NU 28 4 ISUM2MSB [3:0] Refer ISUM1LSB 4 0 0 QSUM2LSB 0x60 32 QSUM2LSB QSUM2LSB [31:0] Refer ISUM1LSB 32 0 0 QSUM2MSB 0x64 32 QSUM2MSB NU 28 4 QSUM2MSB [3:0] Refer ISUM1LSB 4 0 0 MAX3VALUE 0x68 32 MAX3VALUE NU 8 24 MAX3VALUE [23:0] Refer MAX1VALUE 24 0 0 MAX3INDEX 0x6C 32 MAX3INDEX NU 20 12 MAX3INDEX [11:0] Refer MAX1INDEX 12 0 0 ISUM3LSB 0x70 32 ISUM3LSB ISUM3LSB [31:0] Refer ISUM1LSB 32 0 0 ISUM3MSB 0x74 32 ISUM3MSB NU 28 4 ISUM3MSB [3:0] Refer ISUM1LSB 4 0 0 QSUM3LSB 0x78 32 QSUM3LSB QSUM3LSB [31:0] Refer ISUM1LSB 32 0 0 QSUM3MSB 0x7C 32 QSUM3MSB NU 28 4 QSUM3MSB [3:0] Refer ISUM1LSB 4 0 0 MAX4VALUE 0x80 32 MAX4VALUE NU 8 24 MAX4VALUE [23:0] Refer MAX1INDEX 24 0 0 MAX4INDEX 0x84 32 MAX4INDEX NU 20 12 MAX4INDEX [11:0] Refer MAX1VALUE 12 0 0 ISUM4LSB 0x88 32 ISUM4LSB ISUM4LSB [31:0] Refer ISUM1LSB 32 0 0 ISUM4MSB 0x8C 32 ISUM4MSB NU 28 4 ISUM4MSB [3:0] Refer ISUM1LSB 4 0 0 QSUM4LSB 0x90 32 QSUM4LSB QSUM4LSB [31:0] Refer ISUM1LSB 32 0 0 QSUM4MSB 0x94 32 QSUM4MSB NU 28 4 QSUM4MSB [3:0] Refer ISUM1LSB 4 0 0 CFARTEST 0x98 32 CFARTEST NU 8 24 CFARTEST [23:0] Reserved.TI internal 24 0 0 RDSTATUS 0x9C 32 RDSTATUS NU 15 17 LOOPCNT [16:5] Running value of the loop count when the HWA is executing from PARAM RAM . For Debug only 12 5 PARAMADDR [4:0] Index of the current parameter set being executed from PARAM RAM . For Debug only 5 0 0 SIGDMACH1DONE 0xA0 32 SIGDMACH1DONE SIGDMACH1DONE [31:0] Signature for DMA channel 1 completion (tied to 0x0001 in HW). Linked DMA can copy from one of these SIG_DMACHx_DONE registers into DMA2ACC_TRIG register to set the appropriate register bit to signal the completion of DMA and trigger the accelerator 32 0 0 SIGDMACH2DONE 0xA4 32 SIGDMACH2DONE SIGDMACH2DONE [31:0] Signature for DMA channel 2 completion (tied to 0x0002 in HW) 32 0 0 SIGDMACH3DONE 0xA8 32 SIGDMACH3DONE SIGDMACH3DONE [31:0] Signature for DMA channel 3 completion (tied to 0x0004 in HW) 32 0 0 SIGDMACH4DONE 0xAC 32 SIGDMACH4DONE SIGDMACH4DONE [31:0] Signature for DMA channel 4 completion (tied to 0x0008 in HW) 32 0 0 SIGDMACH5DONE 0xB0 32 SIGDMACH5DONE SIGDMACH5DONE [31:0] Signature for DMA channel 5 completion (tied to 0x0010 in HW) 32 0 0 SIGDMACH6DONE 0xB4 32 SIGDMACH6DONE SIGDMACH6DONE [31:0] Signature for DMA channel 6 completion (tied to 0x0020 in HW) 32 0 0 SIGDMACH7DONE 0xB8 32 SIGDMACH7DONE SIGDMACH7DONE [31:0] Signature for DMA channel 7 completion (tied to 0x0040 in HW) 32 0 0 SIGDMACH8DONE 0xBC 32 SIGDMACH8DONE SIGDMACH8DONE [31:0] Signature for DMA channel 8 completion (tied to 0x0080 in HW) 32 0 0 SIGDMACH9DONE 0xC0 32 SIGDMACH9DONE SIGDMACH9DONE [31:0] Signature for DMA channel 9 completion (tied to 0x0100 in HW) 32 0 0 SIGDMACH10DONE 0xC4 32 SIGDMACH10DONE SIGDMACH10DONE [31:0] Signature for DMA channel 10 completion (tied to 0x0200 in HW) 32 0 0 SIGDMACH11DONE 0xC8 32 SIGDMACH11DONE SIGDMACH11DONE [31:0] Signature for DMA channel 11 completion (tied to 0x0040 in HW) 32 0 0 SIGDMACH12DONE 0xCC 32 SIGDMACH12DONE SIGDMACH12DONE [31:0] Signature for DMA channel 12 completion (tied to 0x0080 in HW) 32 0 0 SIGDMACH13DONE 0xD0 32 SIGDMACH13DONE SIGDMACH13DONE [31:0] Signature for DMA channel 13 completion (tied to 0x1000 in HW) 32 0 0 SIGDMACH14DONE 0xD4 32 SIGDMACH14DONE SIGDMACH14DONE [31:0] Signature for DMA channel 14 completion (tied to 0x2000 in HW) 32 0 0 SIGDMACH15DONE 0xD8 32 SIGDMACH15DONE SIGDMACH15DONE [31:0] Signature for DMA channel 15 completion (tied to 0x4000 in HW) 32 0 0 SIGDMACH16DONE 0xDC 32 SIGDMACH16DONE SIGDMACH16DONE [31:0] Signature for DMA channel 16 completion (tied to 0x8000 in HW) 32 0 0 MEMACCESSERR 0xE0 32 MEMACCESSERR NU3 12 20 STATERRCODE [19:16] Reserved.TI internal 4 16 NU2 4 12 ERRCODEMASK [11:8] Reserved.TI internal 4 8 NU1 4 4 ERRCODECLR [3:0] Reserved.TI internal 4 0 0 FFTCLIP 0xE4 32 FFTCLIP NU2 15 17 CLRFFTCLIPSTAT [16:16] FFTCLIPSTAT can be cleared by setting single-bit register CLRFFTCLIPSTAT, so that the saturation status indication gets cleared back to 0 and any subsequent saturation events can be freshly monitored. 1 16 NU1 6 10 FFTCLIPSTAT [9:0] FFT Clip Status (read-only): This is a read-only status register, which indicates any saturation/clipping events that have happened in the FFT butterfly stages. Note that each of the 10 butterfly stages in the FFT can be programmed to either saturate the MSB or round the LSB. Whenever saturation of MSB is used in any stage, there is a possibility that that stage can saturate/clip samples. In that case, this saturation event is indicated in the corresponding bit in this status registert. If multiple FFTs are performed, this status register includes any saturation events happening in any of them. 10 0 0 FFTPEAKCNT 0xE8 32 FFTPEAKCNT NU 20 12 FFTPEAKCNT [11:0] CFAR Detected Peak Count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory, when CFAR Engine is configured in Detected Peaks List mode. 12 0 0 HWACCREG1RD 0xEC 32 HWACCREG1RD HWACCREG1RD [31:0] Reserved.TI internal 32 0 0 HWACCREG2RD 0xF0 32 HWACCREG2RD HWACCREG2RD [31:0] Reserved.TI internal 32 0 0 HWACCREG3RD 0xF4 32 HWACCREG3RD HWACCREG3RD [31:0] Reserved.TI internal 32 0 0 CMP_EGE_K0123 0xF8 32 CMP_EGE_K0123 NU4 [31:29] Reserved.TI internal 3 29 CMP_EGE_K3 [28:24] EGE K-param for the 4th accumulator 5 24 NU3 [23:21] Reserved.TI internal 3 21 CMP_EGE_K2 [20:16] EGE K-param for the 3rd accumulator 5 16 NU2 [15:13] Reserved.TI internal 3 13 CMP_EGE_K1 [12:8] EGE K-param for the 2nd accumulator 5 8 NU1 [7:5] Reserved.TI internal 3 5 CMP_EGE_K0 [4:0] EGE K-param for the 1st accumulator 5 0 0 CMP_EGE_K4567 0xFC 32 CMP_EGE_K4567 NU4 [31:29] Reserved.TI internal 3 29 CMP_EGE_K7 [28:24] EGE K-param for the 8th accumulator 5 24 NU3 [23:21] Reserved.TI internal 3 21 CMP_EGE_K6 [20:16] EGE K-param for the 7th accumulator 5 16 NU2 [15:13] Reserved.TI internal 3 13 CMP_EGE_K5 [12:8] EGE K-param for the 6th accumulator 5 8 NU1 [7:5] Reserved.TI internal 3 5 CMP_EGE_K4 [4:0] EGE K-param for the 5th accumulator 5 0 0 HWA_SAFETY_ENABLE 0x100 32 HWA_SAFETY_ENABLE NU2 14 18 FSM_LOCKSTEP_SELFTEST_EN [17:17] 1: Enable Selftest for Accelerator FSM 1 17 FSM_LOCKSTEP_EN [16:16] 1: Enable Lockstep for Accelerator FSM 1 16 OPONG_PARITY_EN [15:15] 1: Enable PARITY for ACCEL_MEM3 1 15 OPING_PARITY_EN [14:14] 1: Enable PARITY for ACCEL_MEM2 1 14 IPONG_PARITY_EN [13:13] 1: Enable PARITY for ACCEL_MEM1 1 13 IPING_PARITY_EN [12:12] 1: Enable PARITY for ACCEL_MEM0 1 12 NU1 10 2 PARAM_ECC_EN [1:1] Not used. 1 1 WIN_RAM_PARITY_EN [0:0] 1: Enable PARITY for Window RAM 1 0 0 MEMINIT 0x104 32 MEMINIT NU 24 8 MC_ODD_INIT [7:7] 1: Start initialising MEM_COMPRESSION_ODD_RAM with all '0's 1 7 MC_EVEN_INIT [6:6] 1: Start initialising MEM_COMPRESSION_EVEN_RAM with all '0's 1 6 OPONG_INIT [5:5] 1: Start initialising ACCEL_MEM3 with all '0's 1 5 OPING_INIT [4:4] 1: Start initialising ACCEL_MEM2 with all '0's 1 4 IPONG_INIT [3:3] 1: Start initialising ACCEL_MEM1 with all '0's 1 3 IPING_INIT [2:2] 1: Start initialising ACCEL_MEM0 with all '0's 1 2 PARAM_INIT [1:1] 1: Start initialising Parameter set RAM with all '0's 1 1 WIN_RAM_INIT [0:0] 1: Start initialising Window RAM with all '0's 1 0 0 MEMINITDONE 0x108 32 MEMINITDONE NU 24 8 MC_ODD_INITDONE [7:7] 1: Init done status for MEM_COMPRESSION_ODD_RAM 1 7 MC_EVEN_INITDONE [6:6] 1: Init done status for MEM_COMPRESSION_EVEN_RAM 1 6 OPONG_INITDONE [5:5] 1: Init done status for ACCEL_MEM3 1 5 OPING_INITDONE [4:4] 1: Init done status for ACCEL_MEM2 1 4 IPONG_INITDONE [3:3] 1: Init done status for ACCEL_MEM1 1 3 IPING_INITDONE [2:2] 1: Init done status for ACCEL_MEM0 1 2 PARAM_INITDONE [1:1] 1: Init done status for Parameter set RAM 1 1 WIN_RAM_INITDONE [0:0] 1: Init done status for Window RAM 1 0 0 HWA_SAFETY_WIN_RAM_ERR_LOC 0x10C 32 HWA_SAFETY_WIN_RAM_ERR_LOC NU 16 16 HWA_SAFETY_WIN_RAM_ERR_ADDR [15:0] [Debug] Address of parity error location within Window RAM 16 0 0 HWA_SAFETY_PARAM_RAM_ERR_LOC 0x110 32 HWA_SAFETY_PARAM_RAM_ERR_LOC SPARE [31:0] Reserved.TI internal 32 0 0 HWA_SAFETY_IPING_ERR_LOC 0x114 32 HWA_SAFETY_IPING_ERR_LOC NU 16 16 HWA_SAFETY_IPING_ERR_ADDR [15:0] [Debug ]Address of parity error location within ACCEL_MEM0 (rows 0-1023) 16 0 0 HWA_SAFETY_IPONG_ERR_LOC 0x118 32 HWA_SAFETY_IPONG_ERR_LOC NU 16 16 HWA_SAFETY_IPONG_ERR_ADDR [15:0] [Debug ]Address of parity error location within ACCEL_MEM1 (rows 0-1023) 16 0 0 HWA_SAFETY_OPING_ERR_LOC 0x11C 32 HWA_SAFETY_OPING_ERR_LOC NU 16 16 HWA_SAFETY_OPING_ERR_ADDR [15:0] [Debug ]Address of parity error location within ACCEL_MEM2 (rows 0-1023) 16 0 0 HWA_SAFETY_OPONG_ERR_LOC 0x120 32 HWA_SAFETY_OPONG_ERR_LOC NU 16 16 HWA_SAFETY_OPONG_ERR_ADDR [15:0] [Debug ]Address of parity error location within ACCEL_MEM3 (rows 0-1023) 16 0 0 FFTINTMEMWRDATA 0x124 32 FFTINTMEMWRDATA FFTINTMEMWRDATA [31:0] Reserved.TI internal 32 0 0 FFTINTMEMRDDATA 0x128 32 FFTINTMEMRDDATA FFTINTMEMRDDATA [31:0] Reserved.TI internal 32 0 0 HWACCREG16 0x12C 32 HWACCREG16 NU1 10 22 PARAMSTOP [21:17] These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START. 5 17 PARAMSTART [16:12] These registers are used to control the start and stop index of the parameter-set through which the state machine loops through. The state machine starts at the parameter-set specified by PARAM_START and loads each parameter-set one after another and runs the accelerator as per that configuration. When the state machine reaches the parameter-set specified by PARAM_STOP, it loops back to the start index as specified by PARAM_START. 5 12 NLOOPS [11:0] Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them. The maximum number of times the loop can be made is run is 4094. A value of zero programmed in this register means that the looping mechanism is disabled. 12 0 0 DCEST1I_SW 0x130 32 DCEST1I_SW NU1 8 24 DCEST1I_SW [23:0] This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 0. 24 0 0 DCEST2I_SW 0x134 32 DCEST2I_SW NU1 8 24 DCEST2I_SW [23:0] This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 1. 24 0 0 DCEST3I_SW 0x138 32 DCEST3I_SW NU1 8 24 DCEST3I_SW [23:0] This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 2. 24 0 0 DCEST4I_SW 0x13C 32 DCEST4I_SW NU1 8 24 DCEST4I_SW [23:0] This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 3. 24 0 0 DCEST5I_SW 0x140 32 DCEST5I_SW NU1 8 24 DCEST5I_SW [23:0] This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 4. 24 0 0 DCEST6I_SW 0x144 32 DCEST6I_SW NU1 8 24 DCEST6I_SW [23:0] This register holds the software programmed dc value I to be subtracted from incoming sample for bcnt = 5. 24 0 0 DCEST1I 0x148 32 DCEST1I NU1 8 24 DCEST1I [23:0] This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =0 . 24 0 0 DCEST2I 0x14C 32 DCEST2I NU1 8 24 DCEST2I [23:0] This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =1 . 24 0 0 DCEST3I 0x150 32 DCEST3I NU1 8 24 DCEST3I [23:0] This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =2 . 24 0 0 DCEST4I 0x154 32 DCEST4I NU1 8 24 DCEST4I [23:0] This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =3. 24 0 0 DCEST5I 0x158 32 DCEST5I NU1 8 24 DCEST5I [23:0] This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =4 . 24 0 0 DCEST6I 0x15C 32 DCEST6I NU1 8 24 DCEST6I [23:0] This register holds the estimated dc value I to be subtracted from incoming sample for bcnt =5 . 24 0 0 DC_ACC1I_LSB 0x160 32 DC_ACC1I_LSB DC_ACC1I_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=0 32 0 0 DC_ACC1I_MSB 0x164 32 DC_ACC1I_MSB NU1 28 4 DC_ACC1I_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=0 4 0 0 DC_ACC2I_LSB 0x168 32 DC_ACC2I_LSB DC_ACC2I_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=1 32 0 0 DC_ACC2I_MSB 0x16C 32 DC_ACC2I_MSB NU1 28 4 DC_ACC2I_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=1 4 0 0 DC_ACC3I_LSB 0x170 32 DC_ACC3I_LSB DC_ACC3I_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=2 32 0 0 DC_ACC3I_MSB 0x174 32 DC_ACC3I_MSB NU1 28 4 DC_ACC3I_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=2 4 0 0 DC_ACC4I_LSB 0x178 32 DC_ACC4I_LSB DC_ACC4I_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=3 32 0 0 DC_ACC4I_MSB 0x17C 32 DC_ACC4I_MSB NU1 28 4 DC_ACC4I_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=3 4 0 0 DC_ACC5I_LSB 0x180 32 DC_ACC5I_LSB DC_ACC5I_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=4 32 0 0 DC_ACC5I_MSB 0x184 32 DC_ACC5I_MSB NU1 28 4 DC_ACC5I_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=4 4 0 0 DC_ACC6I_LSB 0x188 32 DC_ACC6I_LSB DC_ACC6I_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator I channel for bcnt=5 32 0 0 DC_ACC6I_MSB 0x18C 32 DC_ACC6I_MSB NU1 28 4 DC_ACC6I_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator I channel for bcnt=5 4 0 0 DCEST1Q_SW 0x190 32 DCEST1Q_SW NU1 8 24 DCEST1Q_SW [23:0] This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 0. 24 0 0 DCEST2Q_SW 0x194 32 DCEST2Q_SW NU1 8 24 DCEST2Q_SW [23:0] This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 1. 24 0 0 DCEST3Q_SW 0x198 32 DCEST3Q_SW NU1 8 24 DCEST3Q_SW [23:0] This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 2. 24 0 0 DCEST4Q_SW 0x19C 32 DCEST4Q_SW NU1 8 24 DCEST4Q_SW [23:0] This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 3. 24 0 0 DCEST5Q_SW 0x1A0 32 DCEST5Q_SW NU1 8 24 DCEST5Q_SW [23:0] This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 4. 24 0 0 DCEST6Q_SW 0x1A4 32 DCEST6Q_SW NU1 8 24 DCEST6Q_SW [23:0] This register holds the software programmed dc value Q to be subtracted from incoming sample for bcnt = 5. 24 0 0 DCEST1Q 0x1A8 32 DCEST1Q NU1 8 24 DCEST1Q [23:0] This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =0 . 24 0 0 DCEST2Q 0x1AC 32 DCEST2Q NU1 8 24 DCEST2Q [23:0] This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =1 . 24 0 0 DCEST3Q 0x1B0 32 DCEST3Q NU1 8 24 DCEST3Q [23:0] This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =2 . 24 0 0 DCEST4Q 0x1B4 32 DCEST4Q NU1 8 24 DCEST4Q [23:0] This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =3. 24 0 0 DCEST5Q 0x1B8 32 DCEST5Q NU1 8 24 DCEST5Q [23:0] This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =4 . 24 0 0 DCEST6Q 0x1BC 32 DCEST6Q NU1 8 24 DCEST6Q [23:0] This register holds the estimated dc value Q to be subtracted from incoming sample for bcnt =5 . 24 0 0 DC_ACC1Q_LSB 0x1C0 32 DC_ACC1Q_LSB DC_ACC1Q_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=0 32 0 0 DC_ACC1Q_MSB 0x1C4 32 DC_ACC1Q_MSB NU1 28 4 DC_ACC1Q_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=0 4 0 0 DC_ACC2Q_LSB 0x1C8 32 DC_ACC2Q_LSB DC_ACC2Q_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=1 32 0 0 DC_ACC2Q_MSB 0x1CC 32 DC_ACC2Q_MSB NU1 28 4 DC_ACC2Q_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=1 4 0 0 DC_ACC3Q_LSB 0x1D0 32 DC_ACC3Q_LSB DC_ACC3Q_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=2 32 0 0 DC_ACC3Q_MSB 0x1D4 32 DC_ACC3Q_MSB NU1 28 4 DC_ACC3Q_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=2 4 0 0 DC_ACC4Q_LSB 0x1D8 32 DC_ACC4Q_LSB DC_ACC4Q_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=3 32 0 0 DC_ACC4Q_MSB 0x1DC 32 DC_ACC4Q_MSB NU1 28 4 DC_ACC4Q_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=3 4 0 0 DC_ACC5Q_LSB 0x1E0 32 DC_ACC5Q_LSB DC_ACC5Q_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=4 32 0 0 DC_ACC5Q_MSB 0x1E4 32 DC_ACC5Q_MSB NU1 28 4 DC_ACC5Q_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=4 4 0 0 DC_ACC6Q_LSB 0x1E8 32 DC_ACC6Q_LSB DC_ACC6Q_LSB [31:0] This register provides the LSB 32 bits value of DC accumulator Q channel for bcnt=5 32 0 0 DC_ACC6Q_MSB 0x1EC 32 DC_ACC6Q_MSB NU1 28 4 DC_ACC6Q_MSB [3:0] This register provides the MSB 4 bits value of DC accumulator Q channel for bcnt=5 4 0 0 DCACC1_CLIP 0x1F0 32 DCACC1_CLIP NU1 31 1 DCACC1_CLIP [0:0] This register contains the clip status of both I/Q of DC accumulators for bcnt =0 1 0 0 DCACC2_CLIP 0x1F4 32 DCACC2_CLIP NU1 31 1 DCACC2_CLIP [0:0] This register contains the clip status of both I/Q of DC accumulators for bcnt =1 1 0 0 DCACC3_CLIP 0x1F8 32 DCACC3_CLIP NU1 31 1 DCACC3_CLIP [0:0] This register contains the clip status of both I/Q of DC accumulators for bcnt =2 1 0 0 DCACC4_CLIP 0x1FC 32 DCACC4_CLIP NU1 31 1 DCACC4_CLIP [0:0] This register contains the clip status of both I/Q of DC accumulators for bcnt =3 1 0 0 DCACC5_CLIP 0x200 32 DCACC5_CLIP NU1 31 1 DCACC5_CLIP [0:0] This register contains the clip status of both I/Q of DC accumulators for bcnt =4 1 0 0 DCACC6_CLIP 0x204 32 DCACC6_CLIP NU1 31 1 DCACC6_CLIP [0:0] This register contains the clip status of both I/Q of DC accumulators for bcnt =5 1 0 0 DCEST1_CLIP 0x208 32 DCEST1_CLIP NU1 31 1 DCEST1_CLIP [0:0] This register contains the clip status of both I/Q DC estimates for bcnt =0 1 0 0 DCEST2_CLIP 0x20C 32 DCEST2_CLIP NU1 31 1 DCEST2_CLIP [0:0] This register contains the clip status of both I/Q DC estimates for bcnt =1 1 0 0 DCEST3_CLIP 0x210 32 DCEST3_CLIP NU1 31 1 DCEST3_CLIP [0:0] This register contains the clip status of both I/Q DC estimates for bcnt =2 1 0 0 DCEST4_CLIP 0x214 32 DCEST4_CLIP NU1 31 1 DCEST4_CLIP [0:0] This register contains the clip status of both I/Q DC estimates for bcnt =3 1 0 0 DCEST5_CLIP 0x218 32 DCEST5_CLIP NU1 31 1 DCEST5_CLIP [0:0] This register contains the clip status of both I/Q DC estimates for bcnt =4 1 0 0 DCEST6_CLIP 0x21C 32 DCEST6_CLIP NU1 31 1 DCEST6_CLIP [0:0] This register contains the clip status of both I/Q DC estimates for bcnt =5 1 0 0 DCSUB1_CLIP 0x220 32 DCSUB1_CLIP NU1 31 1 DCSUB1_CLIP [0:0] Indicates the DC subtraction clip status for bcnt =0 1 0 0 DCSUB2_CLIP 0x224 32 DCSUB2_CLIP NU1 31 1 DCSUB2_CLIP [0:0] Indicates the DC subtraction clip status for bcnt =1 1 0 0 DCSUB3_CLIP 0x228 32 DCSUB3_CLIP NU1 31 1 DCSUB3_CLIP [0:0] Indicates the DC subtraction clip status for bcnt =2 1 0 0 DCSUB4_CLIP 0x22C 32 DCSUB4_CLIP NU1 31 1 DCSUB4_CLIP [0:0] Indicates the DC subtraction clip status for bcnt =3 1 0 0 DCSUB5_CLIP 0x230 32 DCSUB5_CLIP NU1 31 1 DCSUB5_CLIP [0:0] Indicates the DC subtraction clip status for bcnt =4 1 0 0 DCSUB6_CLIP 0x234 32 DCSUB6_CLIP NU1 31 1 DCSUB6_CLIP [0:0] Indicates the DC subtraction clip status for bcnt =5 1 0 0 DCEST_SHIFT 0x238 32 DCEST_SHIFT NU1 28 4 DCEST_SHIFT [3:0] Programmable shift applied to all 6 accumulator outputs. Cannot be bypassed. Scaled accumulator output is shifted by 2^( 2+DCEST_SHIFT). For DCEST_SHIFT = 15 also gives 2^(24) and not 25 (saturate at 24) 4 0 0 DCEST_SCALE 0x23C 32 DCEST_SCALE NU1 23 9 DCEST_SCALE [8:0] 9-bit scale applied to all 6 accumulators. Multiplies the accumulator output by DCEST_SCALE/256.This is followed by right shift and truncation.Default value is 256 giving a scale of 1.0. Setting it to 128, gives a scale of 0.5 9 0 0 INTF_MAG_SCALE 0x240 32 INTF_MAG_SCALE NU1 24 8 INTF_MAG_SCALE [7:0] Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block.Default 8= scale of 1.0 8 0 0 INTF_MAG_SHIFT 0x244 32 INTF_MAG_SHIFT NU1 28 4 INTF_MAG_SHIFT [3:0] Right shift applied after scaling – 2^(4+INTERFSUM_MAG_SHIFT). Can t be more than 2^(17). 4 0 0 INTF_MAGDIFF_SCALE 0x248 32 INTF_MAGDIFF_SCALE NU1 24 8 INTF_MAGDIFF_SCALE [7:0] Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block.Default 8= scale of 1.0 8 0 0 INTF_MAGDIFF_SHIFT 0x24C 32 INTF_MAGDIFF_SHIFT NU1 28 4 INTF_MAGDIFF_SHIFT [3:0] Right shift applied after scaling – 2^(4+INTERFSUM_MAGDIFF_SHIFT). Can t be more than 2^(17). 4 0 0 INTF_FRAME_ZEROCOUNT 0x250 32 INTF_FRAME_ZEROCOUNT NU1 12 20 INTF_FRAME_ZEROCOUNT [19:0] Number of samples that exceeded the threshold in a frame 20 0 0 INTF_CHIRP_ZEROCOUNT 0x254 32 INTF_CHIRP_ZEROCOUNT NU1 20 12 INTF_CHIRP_ZEROCOUNT [11:0] Number of samples that exceeded the threshold in a chirp 12 0 0 INTF_MAGTHRESH1_SW 0x258 32 INTF_MAGTHRESH1_SW NU1 8 24 INTF_MAGTHRESH1_SW [23:0] This register provides software programmed interference magnitude threshold value for bcnt =0 24 0 0 INTF_MAGTHRESH2_SW 0x25C 32 INTF_MAGTHRESH2_SW NU1 8 24 INTF_MAGTHRESH2_SW [23:0] This register provides software programmed interference magnitude threshold value for bcnt =1 24 0 0 INTF_MAGTHRESH3_SW 0x260 32 INTF_MAGTHRESH3_SW NU1 8 24 INTF_MAGTHRESH3_SW [23:0] This register provides software programmed interference magnitude threshold value for bcnt =2 24 0 0 INTF_MAGTHRESH4_SW 0x264 32 INTF_MAGTHRESH4_SW NU1 8 24 INTF_MAGTHRESH4_SW [23:0] This register provides software programmed interference magnitude threshold value for bcnt =3 24 0 0 INTF_MAGTHRESH5_SW 0x268 32 INTF_MAGTHRESH5_SW NU1 8 24 INTF_MAGTHRESH5_SW [23:0] This register provides software programmed interference magnitude threshold value for bcnt =4 24 0 0 INTF_MAGTHRESH6_SW 0x26C 32 INTF_MAGTHRESH6_SW NU1 8 24 INTF_MAGTHRESH6_SW [23:0] This register provides software programmed interference magnitude threshold value for bcnt =5 24 0 0 INTF_MAGDIFFTHRESH1_SW 0x270 32 INTF_MAGDIFFTHRESH1_SW NU1 8 24 INTF_MAGDIFFTHRESH1_SW [23:0] This register provides software programmed interference magnitude difference threshold value for bcnt =0 24 0 0 INTF_MAGDIFFTHRESH2_SW 0x274 32 INTF_MAGDIFFTHRESH2_SW NU1 8 24 INTF_MAGDIFFTHRESH2_SW [23:0] This register provides software programmed interference magnitude difference threshold value for bcnt =1 24 0 0 INTF_MAGDIFFTHRESH3_SW 0x278 32 INTF_MAGDIFFTHRESH3_SW NU1 8 24 INTF_MAGDIFFTHRESH3_SW [23:0] This register provides software programmed interference magnitude difference threshold value for bcnt =2 24 0 0 INTF_MAGDIFFTHRESH4_SW 0x27C 32 INTF_MAGDIFFTHRESH4_SW NU1 8 24 INTF_MAGDIFFTHRESH4_SW [23:0] This register provides software programmed interference magnitude difference threshold value for bcnt =3 24 0 0 INTF_MAGDIFFTHRESH5_SW 0x280 32 INTF_MAGDIFFTHRESH5_SW NU1 8 24 INTF_MAGDIFFTHRESH5_SW [23:0] This register provides software programmed interference magnitude difference threshold value for bcnt =4 24 0 0 INTF_MAGDIFFTHRESH6_SW 0x284 32 INTF_MAGDIFFTHRESH6_SW NU1 8 24 INTF_MAGDIFFTHRESH6_SW [23:0] This register provides software programmed interference magnitude difference threshold value for bcnt =5 24 0 0 INTF_MAGACC1_LSB 0x288 32 INTF_MAGACC1_LSB INTF_MAGACC1_LSB [31:0] This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 0 32 0 0 INTF_MAGACC1_MSB 0x28C 32 INTF_MAGACC1_MSB NU1 28 4 INTF_MAGACC1_MSB [3:0] This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 0 4 0 0 INTF_MAGACC2_LSB 0x290 32 INTF_MAGACC2_LSB INTF_MAGACC2_LSB [31:0] This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 1 32 0 0 INTF_MAGACC2_MSB 0x294 32 INTF_MAGACC2_MSB NU1 28 4 INTF_MAGACC2_MSB [3:0] This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 1 4 0 0 INTF_MAGACC3_LSB 0x298 32 INTF_MAGACC3_LSB INTF_MAGACC3_LSB [31:0] This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 2 32 0 0 INTF_MAGACC3_MSB 0x29C 32 INTF_MAGACC3_MSB NU1 28 4 INTF_MAGACC3_MSB [3:0] This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 2 4 0 0 INTF_MAGACC4_LSB 0x2A0 32 INTF_MAGACC4_LSB INTF_MAGACC4_LSB [31:0] This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 3 32 0 0 INTF_MAGACC4_MSB 0x2A4 32 INTF_MAGACC4_MSB NU1 28 4 INTF_MAGACC4_MSB [3:0] This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 3 4 0 0 INTF_MAGACC5_LSB 0x2A8 32 INTF_MAGACC5_LSB INTF_MAGACC5_LSB [31:0] This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 4 32 0 0 INTF_MAGACC5_MSB 0x2AC 32 INTF_MAGACC5_MSB NU1 28 4 INTF_MAGACC5_MSB [3:0] This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 4 4 0 0 INTF_MAGACC6_LSB 0x2B0 32 INTF_MAGACC6_LSB INTF_MAGACC6_LSB [31:0] This register contains the accumulator value of the interference magnitude (LSB 32 bits) for bcnt = 5 32 0 0 INTF_MAGACC6_MSB 0x2B4 32 INTF_MAGACC6_MSB NU1 28 4 INTF_MAGACC6_MSB [3:0] This register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 5 4 0 0 INTF_MAGDIFFACC1_LSB 0x2B8 32 INTF_MAGDIFFACC1_LSB INTF_MAGDIFFACC1_LSB [31:0] This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 0 32 0 0 INTF_MAGDIFFACC1_MSB 0x2BC 32 INTF_MAGDIFFACC1_MSB NU1 28 4 INTF_MAGDIFFACC1_MSB [3:0] This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0 4 0 0 INTF_MAGDIFFACC2_LSB 0x2C0 32 INTF_MAGDIFFACC2_LSB INTF_MAGDIFFACC2_LSB [31:0] This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 1 32 0 0 INTF_MAGDIFFACC2_MSB 0x2C4 32 INTF_MAGDIFFACC2_MSB NU1 28 4 INTF_MAGDIFFACC2_MSB [3:0] This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1 4 0 0 INTF_MAGDIFFACC3_LSB 0x2C8 32 INTF_MAGDIFFACC3_LSB INTF_MAGDIFFACC3_LSB [31:0] This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 2 32 0 0 INTF_MAGDIFFACC3_MSB 0x2CC 32 INTF_MAGDIFFACC3_MSB NU1 28 4 INTF_MAGDIFFACC3_MSB [3:0] This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2 4 0 0 INTF_MAGDIFFACC4_LSB 0x2D0 32 INTF_MAGDIFFACC4_LSB INTF_MAGDIFFACC4_LSB [31:0] This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 3 32 0 0 INTF_MAGDIFFACC4_MSB 0x2D4 32 INTF_MAGDIFFACC4_MSB NU1 28 4 INTF_MAGDIFFACC4_MSB [3:0] This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3 4 0 0 INTF_MAGDIFFACC5_LSB 0x2D8 32 INTF_MAGDIFFACC5_LSB INTF_MAGDIFFACC5_LSB [31:0] This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 4 32 0 0 INTF_MAGDIFFACC5_MSB 0x2DC 32 INTF_MAGDIFFACC5_MSB NU1 28 4 INTF_MAGDIFFACC5_MSB [3:0] This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4 4 0 0 INTF_MAGDIFFACC6_LSB 0x2E0 32 INTF_MAGDIFFACC6_LSB INTF_MAGDIFFACC6_LSB [31:0] This register contains the accumulator value of the interference magnitude difference (LSB 32 bits) for bcnt = 5 32 0 0 INTF_MAGDIFFACC6_MSB 0x2E4 32 INTF_MAGDIFFACC6_MSB NU1 28 4 INTF_MAGDIFFACC6_MSB [3:0] This register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5 4 0 0 INTF_MAGACC1_CLIP 0x2E8 32 INTF_MAGACC1_CLIP NU1 31 1 INTF_MAGACC1_CLIP [0:0] Interference magnitude accumulator clip status 1 0 0 INTF_MAGACC2_CLIP 0x2EC 32 INTF_MAGACC2_CLIP NU1 31 1 INTF_MAGACC2_CLIP [0:0] Interference magnitude accumulator clip status 1 0 0 INTF_MAGACC3_CLIP 0x2F0 32 INTF_MAGACC3_CLIP NU1 31 1 INTF_MAGACC3_CLIP [0:0] Interference magnitude accumulator clip status 1 0 0 INTF_MAGACC4_CLIP 0x2F4 32 INTF_MAGACC4_CLIP NU1 31 1 INTF_MAGACC4_CLIP [0:0] Interference magnitude accumulator clip status 1 0 0 INTF_MAGACC5_CLIP 0x2F8 32 INTF_MAGACC5_CLIP NU1 31 1 INTF_MAGACC5_CLIP [0:0] Interference magnitude accumulator clip status 1 0 0 INTF_MAGACC6_CLIP 0x2FC 32 INTF_MAGACC6_CLIP NU1 31 1 INTF_MAGACC6_CLIP [0:0] Interference magnitude accumulator clip status 1 0 0 INTF_MAGDIFFACC1_CLIP 0x300 32 INTF_MAGDIFFACC1_CLIP NU1 31 1 INTF_MAGDIFFACC1_CLIP [0:0] Interference magnitude difference accumulator clip status 1 0 0 INTF_MAGDIFFACC2_CLIP 0x304 32 INTF_MAGDIFFACC2_CLIP NU1 31 1 INTF_MAGDIFFACC2_CLIP [0:0] Interference magnitude difference accumulator clip status 1 0 0 INTF_MAGDIFFACC3_CLIP 0x308 32 INTF_MAGDIFFACC3_CLIP NU1 31 1 INTF_MAGDIFFACC3_CLIP [0:0] Interference magnitude difference accumulator clip status 1 0 0 INTF_MAGDIFFACC4_CLIP 0x30C 32 INTF_MAGDIFFACC4_CLIP NU1 31 1 INTF_MAGDIFFACC4_CLIP [0:0] Interference magnitude difference accumulator clip status 1 0 0 INTF_MAGDIFFACC5_CLIP 0x310 32 INTF_MAGDIFFACC5_CLIP NU1 31 1 INTF_MAGDIFFACC5_CLIP [0:0] Interference magnitude difference accumulator clip status 1 0 0 INTF_MAGDIFFACC6_CLIP 0x314 32 INTF_MAGDIFFACC6_CLIP NU1 31 1 INTF_MAGDIFFACC6_CLIP [0:0] Interference magnitude difference accumulator clip status 1 0 0 INTF_MAGTHRESH1 0x318 32 INTF_MAGTHRESH1 NU1 8 24 INTF_MAGTHRESH1 [23:0] Indicates interference magnitude threshold by interference statistics for bcnt =0 24 0 0 INTF_MAGTHRESH2 0x31C 32 INTF_MAGTHRESH2 NU1 8 24 INTF_MAGTHRESH2 [23:0] Indicates interference magnitude threshold by interference statistics for bcnt =1 24 0 0 INTF_MAGTHRESH3 0x320 32 INTF_MAGTHRESH3 NU1 8 24 INTF_MAGTHRESH3 [23:0] Indicates interference magnitude threshold by interference statistics for bcnt =2 24 0 0 INTF_MAGTHRESH4 0x324 32 INTF_MAGTHRESH4 NU1 8 24 INTF_MAGTHRESH4 [23:0] Indicates interference magnitude threshold by interference statistics for bcnt =3 24 0 0 INTF_MAGTHRESH5 0x328 32 INTF_MAGTHRESH5 NU1 8 24 INTF_MAGTHRESH5 [23:0] Indicates interference magnitude threshold by interference statistics for bcnt =4 24 0 0 INTF_MAGTHRESH6 0x32C 32 INTF_MAGTHRESH6 NU1 8 24 INTF_MAGTHRESH6 [23:0] Indicates interference magnitude threshold by interference statistics for bcnt =5 24 0 0 INTF_MAGDIFFTHRESH1 0x330 32 INTF_MAGDIFFTHRESH1 NU1 8 24 INTF_MAGDIFFTHRESH1 [23:0] Indicates interference magnitude difference threshold by interference statistics for bcnt =0 24 0 0 INTF_MAGDIFFTHRESH2 0x334 32 INTF_MAGDIFFTHRESH2 NU1 8 24 INTF_MAGDIFFTHRESH2 [23:0] Indicates interference magnitude difference threshold by interference statistics for bcnt =1 24 0 0 INTF_MAGDIFFTHRESH3 0x338 32 INTF_MAGDIFFTHRESH3 NU1 8 24 INTF_MAGDIFFTHRESH3 [23:0] Indicates interference magnitude difference threshold by interference statistics for bcnt =2 24 0 0 INTF_MAGDIFFTHRESH4 0x33C 32 INTF_MAGDIFFTHRESH4 NU1 8 24 INTF_MAGDIFFTHRESH4 [23:0] Indicates interference magnitude difference threshold by interference statistics for bcnt =3 24 0 0 INTF_MAGDIFFTHRESH5 0x340 32 INTF_MAGDIFFTHRESH5 NU1 8 24 INTF_MAGDIFFTHRESH5 [23:0] Indicates interference magnitude difference threshold by interference statistics for bcnt =4 24 0 0 INTF_MAGDIFFTHRESH6 0x344 32 INTF_MAGDIFFTHRESH6 NU1 8 24 INTF_MAGDIFFTHRESH6 [23:0] Indicates interference magnitude difference threshold by interference statistics for bcnt =5 24 0 0 INTF_SUMMAGTHRESH 0x348 32 INTF_SUMMAGTHRESH NU1 8 24 INTF_SUMMAGTHRESH [23:0] Indicates the sum of mag values ; only Configured BCNT mag values are added 24 0 0 INTF_SUMMAGDIFFTHRESH 0x34C 32 INTF_SUMMAGDIFFTHRESH NU1 8 24 INTF_SUMMAGDIFFTHRESH [23:0] Indicates the sum of magdiff values ; only Configured BCNT magdiff values are added 24 0 0 INTF_SUMMAGTHRESH_CLIP 0x350 32 INTF_SUMMAGTHRESH_CLIP NU1 31 1 INTF_SUMMAGTHRESH_CLIP [0:0] Indicates the clip status of sum of magnitude threshold values 1 0 0 INTF_SUMMAGDIFFTHRESH_CLIP 0x354 32 INTF_SUMMAGDIFFTHRESH_CLIP NU1 31 1 INTF_SUMMAGDIFFTHRESH_CLIP [0:0] Indicates the clip status of sum of magnitude difference threshold values 1 0 0 CMULTSCALE1I 0x358 32 CMULTSCALE1I NU 11 21 CMULTSCALE1I [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE2I 0x35C 32 CMULTSCALE2I NU1 11 21 CMULTSCALE2I [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE3I 0x360 32 CMULTSCALE3I NU1 11 21 CMULTSCALE3I [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE4I 0x364 32 CMULTSCALE4I NU1 11 21 CMULTSCALE4I [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE5I 0x368 32 CMULTSCALE5I NU1 11 21 CMULTSCALE5I [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE6I 0x36C 32 CMULTSCALE6I NU1 11 21 CMULTSCALE6I [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE1Q 0x370 32 CMULTSCALE1Q NU 11 21 CMULTSCALE1Q [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE2Q 0x374 32 CMULTSCALE2Q NU1 11 21 CMULTSCALE2Q [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE3Q 0x378 32 CMULTSCALE3Q NU1 11 21 CMULTSCALE3Q [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE4Q 0x37C 32 CMULTSCALE4Q NU1 11 21 CMULTSCALE4Q [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE5Q 0x380 32 CMULTSCALE5Q NU1 11 21 CMULTSCALE5Q [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CMULTSCALE6Q 0x384 32 CMULTSCALE6Q NU1 11 21 CMULTSCALE6Q [20:0] In CMULT_MODE : 101 , the input samples are multiplied by a different complex scalar CMULTSCALE1I, CMULTSCALE1Q to CMULTSCALE6I, CMULTSCALE6Q per-iteration based on REG_BCNT. Else, a constant complex scalar CMULTSCALE1I and CMULTSCALEQI is applied to all sample across all iterations. 21 0 0 CLR_MISC_CLIP 0x388 32 CLR_MISC_CLIP NU1 31 1 CLR_MISC_CLIP [0:0] This clears the following clip register :- dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status Intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status intf_stats_thresh_magdiff_clip_status ip_formatter_clip_status op_formatter_clip_status intf_stats_sum_mag_val_clip_status intf_stats_sum_magdiff_val_clip_status Its a self clearing bit 1 0 0 FFTINTMEMADDR 0x38C 32 FFTINTMEMADDR NU3 [31:25] Reserved.TI internal 7 25 FFT_INT_MEM_RD [24:24] Reserved.TI internal 1 24 NU2 [23:17] Reserved.TI internal 7 17 FFT_INT_MEM_EN [16:16] Reserved.TI internal 1 16 NU1 [15:12] Reserved.TI internal 4 12 FFT_INT_MEM_SEL [11:9] Reserved.TI internal 3 9 FFT_INT_MEM_ADDR [8:0] Reserved.TI internal 9 0 0 INTF_STATS_RESET_SW 0x390 32 INTF_STATS_RESET_SW NU1 31 1 INTF_STATS_RESET_SW [0:0] SW reset for Interference statistics module. Its a self clearing bit. 1 0 0 DCEST_RESET_SW 0x394 32 DCEST_RESET_SW NU1 31 1 DCEST_RESET_SW [0:0] Reset for all 6 DC estimation accumulators.Its a self clearing bit. 1 0 0 IP_OP_FORMATTER_CLIP_STATUS 0x398 32 IP_OP_FORMATTER_CLIP_STATUS NU2 15 17 OP_FORMATTER_CLIP_STATUS [16:16] Indicates output formatter clip status 1 16 NU1 15 1 IP_FORMATTER_CLIP_STATUS [0:0] Indicates input formatter clip status 1 0 0 INTF_MAGTHRESH1_CLIP 0x39C 32 INTF_MAGTHRESH1_CLIP NU1 31 1 INTF_MAGTHRESH1_CLIP [0:0] Interference magnitude threshold clip status 1 0 0 INTF_MAGTHRESH2_CLIP 0x3A0 32 INTF_MAGTHRESH2_CLIP NU1 31 1 INTF_MAGTHRESH2_CLIP [0:0] Interference magnitude threshold clip status 1 0 0 INTF_MAGTHRESH3_CLIP 0x3A4 32 INTF_MAGTHRESH3_CLIP NU1 31 1 INTF_MAGTHRESH3_CLIP [0:0] Interference magnitude threshold clip status 1 0 0 INTF_MAGTHRESH4_CLIP 0x3A8 32 INTF_MAGTHRESH4_CLIP NU1 31 1 INTF_MAGTHRESH4_CLIP [0:0] Interference magnitude threshold clip status 1 0 0 INTF_MAGTHRESH5_CLIP 0x3AC 32 INTF_MAGTHRESH5_CLIP NU1 31 1 INTF_MAGTHRESH5_CLIP [0:0] Interference magnitude threshold clip status 1 0 0 INTF_MAGTHRESH6_CLIP 0x3B0 32 INTF_MAGTHRESH6_CLIP NU1 31 1 INTF_MAGTHRESH6_CLIP [0:0] Interference magnitude threshold clip status 1 0 0 INTF_MAGDIFFTHRESH1_CLIP 0x3B4 32 INTF_MAGDIFFTHRESH1_CLIP NU1 31 1 INTF_MAGDIFFTHRESH1_CLIP [0:0] Interference magnitude difference threshold clip status 1 0 0 INTF_MAGDIFFTHRESH2_CLIP 0x3B8 32 INTF_MAGDIFFTHRESH2_CLIP NU1 31 1 INTF_MAGDIFFTHRESH2_CLIP [0:0] Interference magnitude difference threshold clip status 1 0 0 INTF_MAGDIFFTHRESH3_CLIP 0x3BC 32 INTF_MAGDIFFTHRESH3_CLIP NU1 31 1 INTF_MAGDIFFTHRESH3_CLIP [0:0] Interference magnitude difference threshold clip status 1 0 0 INTF_MAGDIFFTHRESH4_CLIP 0x3C0 32 INTF_MAGDIFFTHRESH4_CLIP NU1 31 1 INTF_MAGDIFFTHRESH4_CLIP [0:0] Interference magnitude difference threshold clip status 1 0 0 INTF_MAGDIFFTHRESH5_CLIP 0x3C4 32 INTF_MAGDIFFTHRESH5_CLIP NU1 31 1 INTF_MAGDIFFTHRESH5_CLIP [0:0] Interference magnitude difference threshold clip status 1 0 0 INTF_MAGDIFFTHRESH6_CLIP 0x3C8 32 INTF_MAGDIFFTHRESH6_CLIP NU1 31 1 INTF_MAGDIFFTHRESH6_CLIP [0:0] Interference magnitude difference threshold clip status 1 0 0 HWA_SAFETY_ERR_MASK 0x3CC 32 HWA_SAFETY_ERR_MASK NU1 22 10 HWA_SAFETY_ACCESS_ERR_MASK_OPONG_RAM [9:9] When 1'b1 : ACCEL_MEM3 access error is masked.1'b0 : ACCEL_MEM3 access error is not masked 1 9 HWA_SAFETY_ACCESS_ERR_MASK_OPING_RAM [8:8] When 1'b1 : ACCEL_MEM2 access error is masked.1'b0 : ACCEL_MEM2 access error is not masked 1 8 HWA_SAFETY_ACCESS_ERR_MASK_IPONG_RAM [7:7] When 1'b1 : ACCEL_MEM1 access error is masked.1'b0 : ACCEL_MEM1 access error is not masked 1 7 HWA_SAFETY_ACCESS_ERR_MASK_IPING_RAM [6:6] When 1'b1 : ACCEL_MEM0 access error is masked.1'b0 : ACCEL_MEM0 access error is not masked 1 6 HWA_SAFETY_PARITY_ERR_MASK_OPONG_RAM [5:5] When 1'b1 : ACCEL_MEM3 parity error is masked.1'b0 : ACCEL_MEM03 parity error is not masked 1 5 HWA_SAFETY_PARITY_ERR_MASK_OPING_RAM [4:4] When 1'b1 : ACCEL_MEM2 parity error is masked.1'b0 : ACCEL_MEM2 parity error is not masked 1 4 HWA_SAFETY_PARITY_ERR_MASK_IPONG_RAM [3:3] When 1'b1 : ACCEL_MEM1 parity error is masked.1'b0 : ACCEL_MEM1 parity error is not masked 1 3 HWA_SAFETY_PARITY_ERR_MASK_IPING_RAM [2:2] When 1'b1 : ACCEL_MEM0 parity error is masked.1'b0 : ACCEL_MEM0 parity error is not masked 1 2 HWA_SAFETY_PARITY_ERR_MASK_WINDOW_RAM [1:1] When 1'b1 : Window RAM parity error is masked.1'b0 : Window RAM parity error is not masked 1 1 HWA_SAFETY_ERR_MASK_FSM_LOCKSTEP [0:0] When 1'b1 : FSM lockstep error is masked.1'b0 : FSM lockstep error is not masked 1 0 0 HWA_SAFETY_ERR_STATUS 0x3D0 32 HWA_SAFETY_ERR_STATUS NU1 22 10 HWA_SAFETY_ACCESS_ERR_STATUS_OPONG_RAM [9:9] Indicates the ACCEL_MEM3 access error (Masked status) 1 9 HWA_SAFETY_ACCESS_ERR_STATUS_OPING_RAM [8:8] Indicates the ACCEL_MEM2 access error (Masked status) 1 8 HWA_SAFETY_ACCESS_ERR_STATUS_IPONG_RAM [7:7] Indicates the ACCEL_MEM1 access error (Masked status) 1 7 HWA_SAFETY_ACCESS_ERR_STATUS_IPING_RAM [6:6] Indicates the ACCEL_MEM0 access error (Masked status) 1 6 HWA_SAFETY_PARITY_ERR_STATUS_OPONG_RAM [5:5] Indicates the ACCEL_MEM3 parity error (Masked status) 1 5 HWA_SAFETY_PARITY_ERR_STATUS_OPING_RAM [4:4] Indicates the ACCEL_MEM2 parity error (Masked status) 1 4 HWA_SAFETY_PARITY_ERR_STATUS_IPONG_RAM [3:3] Indicates the ACCEL_MEM1 parity error (Masked status) 1 3 HWA_SAFETY_PARITY_ERR_STATUS_IPING_RAM [2:2] Indicates the ACCEL_MEM0 parity error (Masked status) 1 2 HWA_SAFETY_PARITY_ERR_STATUS_WINDOW_RAM [1:1] Indicates the Window RAM parity error (Masked status) 1 1 HWA_SAFETY_ERR_STATUS_FSM_LOCKSTEP [0:0] Indicates the FSM lockstep error (Masked status) 1 0 0 HWA_SAFETY_ERR_STATUS_RAW 0x3D4 32 HWA_SAFETY_ERR_STATUS_RAW NU1 22 10 HWA_SAFETY_ACCESS_ERR_STATUS_RAW_OPONG_RAM [9:9] Indicates the ACCEL_MEM3 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 9 1 9 HWA_SAFETY_ACCESS_ERR_STATUS_RAW_OPING_RAM [8:8] Indicates the ACCEL_MEM2 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 8 1 8 HWA_SAFETY_ACCESS_ERR_STATUS_RAW_IPONG_RAM [7:7] Indicates the ACCEL_MEM1 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 7 1 7 HWA_SAFETY_ACCESS_ERR_STATUS_RAW_IPING_RAM [6:6] Indicates the ACCEL_MEM0 access error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 6 1 6 HWA_SAFETY_PARITY_ERR_STATUS_RAW_OPONG_RAM [5:5] Indicates the ACCEL_MEM3 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 5 1 5 HWA_SAFETY_PARITY_ERR_STATUS_RAW_OPING_RAM [4:4] Indicates the ACCEL_MEM2 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 4 1 4 HWA_SAFETY_PARITY_ERR_STATUS_RAW_IPONG_RAM [3:3] Indicates the ACCEL_MEM1 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 3 1 3 HWA_SAFETY_PARITY_ERR_STATUS_RAW_IPING_RAM [2:2] Indicates the ACCEL_MEM0 parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 2 1 2 HWA_SAFETY_PARITY_ERR_STATUS_RAW_WINDOW_RAM [1:1] Indicates the Window RAM parity error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 1 1 1 HWA_SAFETY_ERR_STATUS_RAW_FSM_LOCKSTEP [0:0] Indicates the FSM lockstep error (raw status).Set irrespective of HWA_SAFETY_ERR_MASK bit 0 1 0 0 TPTC_B0 0x55020000 0 860 registers Register test environment PID 0x0 32 Peripheral ID Register [31:30] PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1. 2 30 [27:16] Function indicates a software compatible module family. 12 16 [15:11] RTL Version 5 11 [10:8] Major Revision 3 8 [7:6] Custom revision field: Not used on this version of EDMA. 2 6 [5:0] Minor Revision 6 0 0 TCCFG 0x4 32 TC Configuration Register [9:8] Dst Register FIFO Depth Parameterization 2 8 [5:4] Bus Width Parameterization 2 4 [2:0] Fifo Size Parameterization 3 0 0 TCSTAT 0x100 32 TC Status Register [13:12] Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3 2 12 [8:8] Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy. 1 8 [6:4] Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter. 3 4 [2:2] Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands. 1 2 [1:1] Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request. 1 1 [0:0] Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set. 1 0 0 INTSTAT 0x104 32 Interrupt Status Register [1:1] TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit. 1 1 [0:0] Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit. 1 0 0 INTEN 0x108 32 Interrupt Enable Register [1:1] TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation 1 1 [0:0] Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation 1 0 0 INTCLR 0x10C 32 Interrupt Clear Register [1:1] TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit 1 1 [0:0] Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit 1 0 0 INTCMD 0x110 32 Interrupt Command Register [1:1] Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 ERRSTAT 0x120 32 Error Status Register [3:3] MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded. 1 3 [2:2] TR Error:#br#TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded. 1 2 [0:0] Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]. 1 0 0 ERREN 0x124 32 Error Enable Register [3:3] Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation. 1 3 [2:2] Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation. 1 2 [0:0] Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation. 1 0 0 ERRCLR 0x128 32 Error Clear Register [3:3] Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register. 1 3 [2:2] Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register. 1 2 [0:0] Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register. 1 0 0 ERRDET 0x12C 32 Error Details Register [17:17] Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 17 [16:16] Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 16 [13:8] Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error. 6 8 [3:0] Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec. 4 0 0 ERRCMD 0x130 32 Error Command Register [1:1] Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 RDRATE 0x140 32 Read Rate Register [2:0] Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC. 3 0 0 POPT 0x200 32 Prog Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 PSRC 0x204 32 Prog Set Src Address [31:0] Source address for Program Register Set 32 0 0 PCNT 0x208 32 Prog Set Count [31:16] B-Dimension count. Number of arrays to be transferred where each array is ACNT in length. 16 16 [15:0] A-Dimension count. Number of bytes to be transferred in first dimension. 16 0 0 PDST 0x20C 32 Prog Set Dst Address [31:0] Destination address for Program Register Set 32 0 0 PBIDX 0x210 32 Prog Set B-Dim Idx [31:16] Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 PMPPRXY 0x214 32 Prog Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SAOPT 0x240 32 Src Actv Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 SASRC 0x244 32 Src Actv Set Src Address [31:0] Source address for Source Active Register Set 32 0 0 SACNT 0x248 32 Src Actv Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred in first dimension. 23 0 0 SADST 0x24C 32 Src Actv Set Dst Address [31:0] Destination address for Source Active Register Set 32 0 0 SABIDX 0x250 32 Src Actv Set B-Dim Idx [31:16] Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 SAMPPRXY 0x254 32 Src Actv Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SACNTRLD 0x258 32 Src Actv Set Cnt Reload [15:0] A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 SASRCBREF 0x25C 32 Src Actv Set Src Addr B-Reference [31:0] Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 SADSTBREF 0x260 32 Src Actv Set Dst Addr B-Reference [31:0] Dst address reference is not applicable for Src Active Register Set. Reads return 0x0. 32 0 0 SABCNT 0x264 32 Src Actv Set B-Count [15:0] B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete. 16 0 0 DFCNTRLD 0x280 32 Dst FIFO Set Cnt Reload [15:0] A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 DFSRCBREF 0x284 32 Dst FIFO Set Src Addr B-Reference [31:0] Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 DFOPT0 0x300 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC0 0x304 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT0 0x308 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST0 0x30C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX0 0x310 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY0 0x314 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT0 0x318 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 DFOPT1 0x340 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC1 0x344 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT1 0x348 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST1 0x34C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX1 0x350 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY1 0x354 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT1 0x358 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 TPTC_B0 0x55040000 0 860 registers Register test environment PID 0x0 32 Peripheral ID Register [31:30] PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1. 2 30 [27:16] Function indicates a software compatible module family. 12 16 [15:11] RTL Version 5 11 [10:8] Major Revision 3 8 [7:6] Custom revision field: Not used on this version of EDMA. 2 6 [5:0] Minor Revision 6 0 0 TCCFG 0x4 32 TC Configuration Register [9:8] Dst Register FIFO Depth Parameterization 2 8 [5:4] Bus Width Parameterization 2 4 [2:0] Fifo Size Parameterization 3 0 0 TCSTAT 0x100 32 TC Status Register [13:12] Dst FIFO Start Pointer#br#Represents the offset to the head entry of Dst Register FIFO in units of entries. Legal values = 0x0 to 0x3 2 12 [8:8] Channel Active#br#Channel Active is a logical-OR of each of the BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR.#br#ACTV = 0 : Channel is idle.#br#ACTV = 1 : Channel is busy. 1 8 [6:4] Destination Active State#br#Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant.#br#Legal values are constrained by the DSTREGDEPTH parameter. 3 4 [2:2] Write Status Active#br#WSACTV = 0 : Write status is not pending. Write status has been received for all previously issued write commands.#br#WSACTV = 1 : Write Status is pending. Write status has not been received for all previously issued write commands. 1 2 [1:1] Source Active State#br#SRCACTV = 0 : Source Active set is idle. Any TR written to Prog Set will immediately transition to Source Active set as long as the Dst FIFO Set is not full [DSTFULL == 1].#br#SRCACTV = 1 : Source Active set is busy either performing read transfers or waiting to perform read transfers for current Transfer Request. 1 1 [0:0] Program Register Set Busy#br#PROGBUSY = 0 : Prog set idle and is available for programming.#br#PROGBUSY = 1 : Prog set busy. User should poll for PROGBUSY equal to '0' prior to re-programming the Program Register set. 1 0 0 INTSTAT 0x104 32 Interrupt Status Register [1:1] TR Done Event Status:#br#TRDONE = 0 : Condition not detected.#br#TRDONE = 1 : Set when TC has completed a Transfer Request. TRDONE should be set when the write status is returned for the final write of a TR. Cleared when user writes '1' to INTCLR.TRDONE register bit. 1 1 [0:0] Program Set Empty Event Status:#br#PROGEMPTY = 0 : Condition not detected.#br#PROGEMPTY = 1 : Set when Program Register set transitions to empty state. Cleared when user writes '1' to INTCLR.PROGEMPTY register bit. 1 0 0 INTEN 0x108 32 Interrupt Enable Register [1:1] TR Done Event Enable:#br#INTEN.TRDONE = 0 : TRDONE Event is disabled.#br#INTEN.TRDONE = 1 : TRDONE Event is enabled and contributes to interrupt generation 1 1 [0:0] Program Set Empty Event Enable:#br#INTEN.PROGEMPTY = 0 : PROGEMPTY Event is disabled.#br#INTEN.PROGEMPTY = 1 : PROGEMPTY Event is enabled and contributes to interrupt generation 1 0 0 INTCLR 0x10C 32 Interrupt Clear Register [1:1] TR Done Event Clear:#br#INTCLR.TRDONE = 0 : Writes of '0' have no effect.#br#INTCLR.TRDONE = 1 : Write of '1' clears INTSTAT.TRDONE bit 1 1 [0:0] Program Set Empty Event Clear:#br#INTCLR.PROGEMPTY = 0 : Writes of '0' have no effect.#br#INTCLR.PROGEMPTY = 1 : Write of '1' clears INTSTAT.PROGEMPTY bit 1 0 0 INTCMD 0x110 32 Interrupt Command Register [1:1] Set TPTC interrupt:#br#Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC interrupt#br#Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 ERRSTAT 0x120 32 Error Status Register [3:3] MMR Address Error:#br#MMRAERR = 0 : Condition not detected.#br#MMRAERR = 1 : User attempted to read or write to invalid address configuration memory map. [Is only be set for non-emulation accesses]. No additional error information is recorded. 1 3 [2:2] TR Error:#br#TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0. No additional error information is recorded. 1 2 [0:0] Bus Error Event:#br#BUSERR = 0: Condition not detected.#br#BUSERR = 1: TC has detected an error code on the write response bus or read response bus. Error information is stored in Error Details Register [ERRDET]. 1 0 0 ERREN 0x124 32 Error Enable Register [3:3] Interrupt enable for ERRSTAT.MMRAERR:#br#ERREN.MMRAERR = 0 : BUSERR is disabled.#br#ERREN.MMRAERR = 1 : MMRAERR is enabled and contributes to the TPTC error interrupt generation. 1 3 [2:2] Interrupt enable for ERRSTAT.TRERR:#br#ERREN.TRERR = 0 : BUSERR is disabled.#br#ERREN.TRERR = 1 : TRERR is enabled and contributes to the TPTC error interrupt generation. 1 2 [0:0] Interrupt enable for ERRSTAT.BUSERR:#br#ERREN.BUSERR = 0 : BUSERR is disabled.#br#ERREN.BUSERR = 1 : BUSERR is enabled and contributes to the TPTC error interrupt generation. 1 0 0 ERRCLR 0x128 32 Error Clear Register [3:3] Interrupt clear for ERRSTAT.MMRAERR:#br#ERRCLR.MMRAERR = 0 : Writes of '0' have no effect.#br#ERRCLR.MMRAERR = 1 : Write of '1' clears ERRSTAT.MMRAERR bit. Write of '1' to ERRCLR.MMRAERR does not clear the ERRDET register. 1 3 [2:2] Interrupt clear for ERRSTAT.TRERR:#br#ERRCLR.TRERR = 0 : Writes of '0' have no effect.#br#ERRCLR.TRERR = 1 : Write of '1' clears ERRSTAT.TRERR bit. Write of '1' to ERRCLR.TRERR does not clear the ERRDET register. 1 2 [0:0] Interrupt clear for ERRSTAT.BUSERR:#br#ERRCLR.BUSERR = 0 : Writes of '0' have no effect.#br#ERRCLR.BUSERR = 1 : Write of '1' clears ERRSTAT.BUSERR bit. Write of '1' to ERRCLR.BUSERR clears the ERRDET register. 1 0 0 ERRDET 0x12C 32 Error Details Register [17:17] Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 17 [16:16] Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error. 1 16 [13:8] Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error. 6 8 [3:0] Transaction Status:#br#Stores the non-zero status/error code that was detected on the read status or write status bus.#br#MS-bit effectively serves as the read vs. write error code.#br#If read status and write status are returned on the same cycle then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority.#br#Encoding of errors matches the CBA spec. 4 0 0 ERRCMD 0x130 32 Error Command Register [1:1] Set TPTC error interrupt:#br#Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally.#br#Writes of '0' have no affect. 1 1 [0:0] Evaluate state of TPTC error interrupt#br#Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'.#br#Writes of '0' have no affect. 1 0 0 RDRATE 0x140 32 Read Rate Register [2:0] Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC. 3 0 0 POPT 0x200 32 Prog Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 PSRC 0x204 32 Prog Set Src Address [31:0] Source address for Program Register Set 32 0 0 PCNT 0x208 32 Prog Set Count [31:16] B-Dimension count. Number of arrays to be transferred where each array is ACNT in length. 16 16 [15:0] A-Dimension count. Number of bytes to be transferred in first dimension. 16 0 0 PDST 0x20C 32 Prog Set Dst Address [31:0] Destination address for Program Register Set 32 0 0 PBIDX 0x210 32 Prog Set B-Dim Idx [31:16] Dest B-Idx for Program Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Program Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 PMPPRXY 0x214 32 Prog Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SAOPT 0x240 32 Src Actv Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 SASRC 0x244 32 Src Actv Set Src Address [31:0] Source address for Source Active Register Set 32 0 0 SACNT 0x248 32 Src Actv Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred in first dimension. 23 0 0 SADST 0x24C 32 Src Actv Set Dst Address [31:0] Destination address for Source Active Register Set 32 0 0 SABIDX 0x250 32 Src Actv Set B-Dim Idx [31:16] Dest B-Idx for Source Active Register Set:#br#B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]. DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Source B-Idx for Source Active Register Set:#br#B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]. SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 SAMPPRXY 0x254 32 Src Actv Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 SACNTRLD 0x258 32 Src Actv Set Cnt Reload [15:0] A-Cnt Reload value for Source Active Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 SASRCBREF 0x25C 32 Src Actv Set Src Addr B-Reference [31:0] Source address reference for Source Active Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 SADSTBREF 0x260 32 Src Actv Set Dst Addr B-Reference [31:0] Dst address reference is not applicable for Src Active Register Set. Reads return 0x0. 32 0 0 SABCNT 0x264 32 Src Actv Set B-Count [15:0] B-Dimension count:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Count Remaining for Src Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete. 16 0 0 DFCNTRLD 0x280 32 Dst FIFO Set Cnt Reload [15:0] A-Cnt Reload value for Destination FIFO Register set. Value copied from PCNT.ACNT: Represents the originally programmed value of ACNT.#br#The Reload value is used to reinitialize ACNT after each array is serviced [i.e. ACNT decrements to 0]. by the Src offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT bytes] 16 0 0 DFSRCBREF 0x284 32 Dst FIFO Set Src Addr B-Reference [31:0] Source address reference for Destination FIFO Register Set:#br#Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value. 32 0 0 DFOPT0 0x300 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC0 0x304 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT0 0x308 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST0 0x30C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX0 0x310 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY0 0x314 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT0 0x318 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 DFOPT1 0x340 32 Dst FIFO Set Options [29:28] Debug ID#br#Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus.#br#Used at system level for trace/profiling of user selected transfers in systems that include this feature. 2 28 [22:22] Transfer complete chaining enable:#br#0: Transfer complete chaining is disabled.#br#1: Transfer complete chaining is enabled. 1 22 [20:20] Transfer complete interrupt enable:#br#0: Transfer complete interrupt is disabled.#br#1: Transfer complete interrupt is enabled. 1 20 [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module. 6 12 [10:8] FIFO width control: Applies if either SAM or DAM is set to FIFO mode. 3 8 [6:4] Transfer Priority:#br#0: Priority 0 - Highest priority#br#1: Priority 1 ...#br#7: Priority 7 - Lowest priority 3 4 [1:1] Destination Address Mode within an array:#br#0: INCR Dst addressing within an array increments.#br#1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 [0:0] Source Address Mode within an array:#br#0: INCR Src addressing within an array increments.#br#1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 DFSRC1 0x344 32 Dst FIFO Set Src Address [31:0] Source address is not applicable for Dst FIFO Register Set: Reads return 0x0. 32 0 0 DFACNT1 0x348 32 Dst FIFO Set A-Count [22:0] A-Dimension count. Number of bytes to be transferred infirst dimension. 23 0 0 DFDST1 0x34C 32 Dst FIFO Set Dst Address [31:0] Destination address for Dst FIFO Register Set:#br#Initial value is copied from PDST.DADDR.#br#TC updates value according to destination addressing mode [OPT.SAM] and/or dest index value [BIDX.DBIDX] after each write command is issued.#br#When a TR is complete the final value should be the address of the last write command issued. 32 0 0 DFBIDX1 0x350 32 Dst FIFO Set B-Dim Idx [31:16] Dest B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements].#br#DBIDX is always used regardless of whether DAM is Increment or FIFO mode. 16 16 [15:0] Src B-Idx for Dest FIFO Register Set.#br#Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].#br#SBIDX is always used regardless of whether SAM is Increment or FIFO mode. 16 0 0 DFMPPRXY1 0x354 32 Dst FIFO Set Mem Protect Proxy [9:9] Secure Level: Deprecated, always read as 0. 1 9 [8:8] Privilege Level:#br#PRIV = 0 : User level privilege#br#PRIV = 1 : Supervisor level privilege#br#PMPPRXY.PRIV is always updated with the value from the configuration bus privilege field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIV value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the PRIV of the external host that sets up the DMA transaction. 1 8 [3:0] Privilege ID:#br#PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register].#br#The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values.The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform memory protection checks based on the privid of the external host that sets up the DMA transaction. 4 0 0 DFBCNT1 0x358 32 Dst FIFO Set B-Count [15:0] B-Count Remaining for Dst Register Set:#br#Number of arrays to be transferred where each array is ACNT in length.#br#Represents the amount of data remaining to be written.#br#Initial value is copied from PCNT.#br#TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete. 16 0 0 TPCC_B 0x55080000 0 16416 registers TPCC PID 0x0 32 Peripheral ID Register SCHEME [31:30] PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1. 2 30 RES1 [29:28] RESERVE FIELD 2 28 FUNC [27:16] Function indicates a software compatible module family. 12 16 RTL [15:11] RTL Version 5 11 MAJOR [10:8] Major Revision 3 8 CUSTOM [7:6] Custom revision field: Not used on this version of EDMA. 2 6 MINOR [5:0] Minor Revision 6 0 0 CCCFG 0x4 32 CC Configuration Register RES2 [31:26] RESERVE FIELD 6 26 MPEXIST [25:25] Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included. 1 25 CHMAPEXIST [24:24] Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included. 1 24 RES3 [23:22] RESERVE FIELD 2 22 NUMREGN [21:20] Number of MP and Shadow regions 2 20 RES4 [19:19] RESERVE FIELD 1 19 NUMTC [18:16] Number of Queues/Number of TCs 3 16 RES5 [15:15] RESERVE FIELD 1 15 NUMPAENTRY [14:12] Number of PaRAM entries 3 12 RES6 [11:11] RESERVE FIELD 1 11 NUMINTCH [10:8] Number of Interrupt Channels 3 8 RES7 [7:7] RESERVE FIELD 1 7 NUMQDMACH [6:4] Number of QDMA Channels 3 4 RES8 [3:3] RESERVE FIELD 1 3 NUMDMACH [2:0] Number of DMA Channels 3 0 0 QCHMAPN 0x200 32 QDMA Channel N Mapping Register RES10 [31:14] RESERVE FIELD 18 14 PAENTRY [13:5] PaRAM Entry number for QDMA Channel N. 9 5 TRWORD [4:2] TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized. 3 2 0 DMAQNUMN 0x240 32 DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel. RES11 [31:31] RESERVE FIELD 1 31 E7 [30:28] DMA Queue Number for event #7 3 28 RES12 [27:27] RESERVE FIELD 1 27 E6 [26:24] DMA Queue Number for event #6 3 24 RES13 [23:23] RESERVE FIELD 1 23 E5 [22:20] DMA Queue Number for event #5 3 20 RES14 [19:19] RESERVE FIELD 1 19 E4 [18:16] DMA Queue Number for event #4 3 16 RES15 [15:15] RESERVE FIELD 1 15 E3 [14:12] DMA Queue Number for event #3 3 12 RES16 [11:11] RESERVE FIELD 1 11 E2 [10:8] DMA Queue Number for event #2 3 8 RES17 [7:7] RESERVE FIELD 1 7 E1 [6:4] DMA Queue Number for event #1 3 4 RES18 [3:3] RESERVE FIELD 1 3 E0 [2:0] DMA Queue Number for event #0 3 0 0 QDMAQNUM 0x260 32 QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel. RES19 [31:31] RESERVE FIELD 1 31 E7 [30:28] QDMA Queue Number for event #7 3 28 RES20 [27:27] RESERVE FIELD 1 27 E6 [26:24] QDMA Queue Number for event #6 3 24 RES21 [23:23] RESERVE FIELD 1 23 E5 [22:20] QDMA Queue Number for event #5 3 20 RES22 [19:19] RESERVE FIELD 1 19 E4 [18:16] QDMA Queue Number for event #4 3 16 RES23 [15:15] RESERVE FIELD 1 15 E3 [14:12] QDMA Queue Number for event #3 3 12 RES24 [11:11] RESERVE FIELD 1 11 E2 [10:8] QDMA Queue Number for event #2 3 8 RES25 [7:7] RESERVE FIELD 1 7 E1 [6:4] QDMA Queue Number for event #1 3 4 RES26 [3:3] RESERVE FIELD 1 3 E0 [2:0] QDMA Queue Number for event #0 3 0 0 QUETCMAP 0x280 32 Queue to TC Mapping RES27 [31:7] RESERVE FIELD 25 7 TCNUMQ1 [6:4] TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to. 3 4 RES28 [3:3] RESERVE FIELD 1 3 TCNUMQ0 [2:0] TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to. 3 0 0 QUEPRI 0x284 32 Queue Priority RES29 [31:7] RESERVE FIELD 25 7 PRIQ1 [6:4] Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands. 3 4 RES30 [3:3] RESERVE FIELD 1 3 PRIQ0 [2:0] Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands. 3 0 0 EMR 0x300 32 Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt. E31 [31:31] Event Missed #31 1 31 E30 [30:30] Event Missed #30 1 30 E29 [29:29] Event Missed #29 1 29 E28 [28:28] Event Missed #28 1 28 E27 [27:27] Event Missed #27 1 27 E26 [26:26] Event Missed #26 1 26 E25 [25:25] Event Missed #25 1 25 E24 [24:24] Event Missed #24 1 24 E23 [23:23] Event Missed #23 1 23 E22 [22:22] Event Missed #22 1 22 E21 [21:21] Event Missed #21 1 21 E20 [20:20] Event Missed #20 1 20 E19 [19:19] Event Missed #19 1 19 E18 [18:18] Event Missed #18 1 18 E17 [17:17] Event Missed #17 1 17 E16 [16:16] Event Missed #16 1 16 E15 [15:15] Event Missed #15 1 15 E14 [14:14] Event Missed #14 1 14 E13 [13:13] Event Missed #13 1 13 E12 [12:12] Event Missed #12 1 12 E11 [11:11] Event Missed #11 1 11 E10 [10:10] Event Missed #10 1 10 E9 [9:9] Event Missed #9 1 9 E8 [8:8] Event Missed #8 1 8 E7 [7:7] Event Missed #7 1 7 E6 [6:6] Event Missed #6 1 6 E5 [5:5] Event Missed #5 1 5 E4 [4:4] Event Missed #4 1 4 E3 [3:3] Event Missed #3 1 3 E2 [2:2] Event Missed #2 1 2 E1 [1:1] Event Missed #1 1 1 E0 [0:0] Event Missed #0 1 0 0 EMRH 0x304 32 Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt. E63 [31:31] Event Missed #63 1 31 E62 [30:30] Event Missed #62 1 30 E61 [29:29] Event Missed #61 1 29 E60 [28:28] Event Missed #60 1 28 E59 [27:27] Event Missed #59 1 27 E58 [26:26] Event Missed #58 1 26 E57 [25:25] Event Missed #57 1 25 E56 [24:24] Event Missed #56 1 24 E55 [23:23] Event Missed #55 1 23 E54 [22:22] Event Missed #54 1 22 E53 [21:21] Event Missed #53 1 21 E52 [20:20] Event Missed #52 1 20 E51 [19:19] Event Missed #51 1 19 E50 [18:18] Event Missed #50 1 18 E49 [17:17] Event Missed #49 1 17 E48 [16:16] Event Missed #48 1 16 E47 [15:15] Event Missed #47 1 15 E46 [14:14] Event Missed #46 1 14 E45 [13:13] Event Missed #45 1 13 E44 [12:12] Event Missed #44 1 12 E43 [11:11] Event Missed #43 1 11 E42 [10:10] Event Missed #42 1 10 E41 [9:9] Event Missed #41 1 9 E40 [8:8] Event Missed #40 1 8 E39 [7:7] Event Missed #39 1 7 E38 [6:6] Event Missed #38 1 6 E37 [5:5] Event Missed #37 1 5 E36 [4:4] Event Missed #36 1 4 E35 [3:3] Event Missed #35 1 3 E34 [2:2] Event Missed #34 1 2 E33 [1:1] Event Missed #33 1 1 E32 [0:0] Event Missed #32 1 0 0 EMCR 0x308 32 Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC. E31 [31:31] Event Missed Clear #31 1 31 E30 [30:30] Event Missed Clear #30 1 30 E29 [29:29] Event Missed Clear #29 1 29 E28 [28:28] Event Missed Clear #28 1 28 E27 [27:27] Event Missed Clear #27 1 27 E26 [26:26] Event Missed Clear #26 1 26 E25 [25:25] Event Missed Clear #25 1 25 E24 [24:24] Event Missed Clear #24 1 24 E23 [23:23] Event Missed Clear #23 1 23 E22 [22:22] Event Missed Clear #22 1 22 E21 [21:21] Event Missed Clear #21 1 21 E20 [20:20] Event Missed Clear #20 1 20 E19 [19:19] Event Missed Clear #19 1 19 E18 [18:18] Event Missed Clear #18 1 18 E17 [17:17] Event Missed Clear #17 1 17 E16 [16:16] Event Missed Clear #16 1 16 E15 [15:15] Event Missed Clear #15 1 15 E14 [14:14] Event Missed Clear #14 1 14 E13 [13:13] Event Missed Clear #13 1 13 E12 [12:12] Event Missed Clear #12 1 12 E11 [11:11] Event Missed Clear #11 1 11 E10 [10:10] Event Missed Clear #10 1 10 E9 [9:9] Event Missed Clear #9 1 9 E8 [8:8] Event Missed Clear #8 1 8 E7 [7:7] Event Missed Clear #7 1 7 E6 [6:6] Event Missed Clear #6 1 6 E5 [5:5] Event Missed Clear #5 1 5 E4 [4:4] Event Missed Clear #4 1 4 E3 [3:3] Event Missed Clear #3 1 3 E2 [2:2] Event Missed Clear #2 1 2 E1 [1:1] Event Missed Clear #1 1 1 E0 [0:0] Event Missed Clear #0 1 0 0 EMCRH 0x30C 32 Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC. E63 [31:31] Event Missed Clear #63 1 31 E62 [30:30] Event Missed Clear #62 1 30 E61 [29:29] Event Missed Clear #61 1 29 E60 [28:28] Event Missed Clear #60 1 28 E59 [27:27] Event Missed Clear #59 1 27 E58 [26:26] Event Missed Clear #58 1 26 E57 [25:25] Event Missed Clear #57 1 25 E56 [24:24] Event Missed Clear #56 1 24 E55 [23:23] Event Missed Clear #55 1 23 E54 [22:22] Event Missed Clear #54 1 22 E53 [21:21] Event Missed Clear #53 1 21 E52 [20:20] Event Missed Clear #52 1 20 E51 [19:19] Event Missed Clear #51 1 19 E50 [18:18] Event Missed Clear #50 1 18 E49 [17:17] Event Missed Clear #49 1 17 E48 [16:16] Event Missed Clear #48 1 16 E47 [15:15] Event Missed Clear #47 1 15 E46 [14:14] Event Missed Clear #46 1 14 E45 [13:13] Event Missed Clear #45 1 13 E44 [12:12] Event Missed Clear #44 1 12 E43 [11:11] Event Missed Clear #43 1 11 E42 [10:10] Event Missed Clear #42 1 10 E41 [9:9] Event Missed Clear #41 1 9 E40 [8:8] Event Missed Clear #40 1 8 E39 [7:7] Event Missed Clear #39 1 7 E38 [6:6] Event Missed Clear #38 1 6 E37 [5:5] Event Missed Clear #37 1 5 E36 [4:4] Event Missed Clear #36 1 4 E35 [3:3] Event Missed Clear #35 1 3 E34 [2:2] Event Missed Clear #34 1 2 E33 [1:1] Event Missed Clear #33 1 1 E32 [0:0] Event Missed Clear #32 1 0 0 QEMR 0x310 32 QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt. RES31 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event Missed #7 1 7 E6 [6:6] Event Missed #6 1 6 E5 [5:5] Event Missed #5 1 5 E4 [4:4] Event Missed #4 1 4 E3 [3:3] Event Missed #3 1 3 E2 [2:2] Event Missed #2 1 2 E1 [1:1] Event Missed #1 1 1 E0 [0:0] Event Missed #0 1 0 0 QEMCR 0x314 32 QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC. RES32 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event Missed Clear #7 1 7 E6 [6:6] Event Missed Clear #6 1 6 E5 [5:5] Event Missed Clear #5 1 5 E4 [4:4] Event Missed Clear #4 1 4 E3 [3:3] Event Missed Clear #3 1 3 E2 [2:2] Event Missed Clear #2 1 2 E1 [1:1] Event Missed Clear #1 1 1 E0 [0:0] Event Missed Clear #0 1 0 0 CCERR 0x318 32 CC Error Register RES33 [31:17] RESERVE FIELD 15 17 TCERR [16:16] Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt. 1 16 RES34 [15:8] RESERVE FIELD 8 8 QTHRXCD7 [7:7] Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 7 QTHRXCD6 [6:6] Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 6 QTHRXCD5 [5:5] Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 5 QTHRXCD4 [4:4] Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 4 QTHRXCD3 [3:3] Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 3 QTHRXCD2 [2:2] Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 2 QTHRXCD1 [1:1] Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 1 QTHRXCD0 [0:0] Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 0 0 CCERRCLR 0x31C 32 CC Error Clear Register RES35 [31:17] RESERVE FIELD 15 17 TCERR [16:16] Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect. 1 16 RES36 [15:8] RESERVE FIELD 8 8 QTHRXCD7 [7:7] Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect. 1 7 QTHRXCD6 [6:6] Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect. 1 6 QTHRXCD5 [5:5] Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect. 1 5 QTHRXCD4 [4:4] Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect. 1 4 QTHRXCD3 [3:3] Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect. 1 3 QTHRXCD2 [2:2] Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect. 1 2 QTHRXCD1 [1:1] Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect. 1 1 QTHRXCD0 [0:0] Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect. 1 0 0 EEVAL 0x320 32 Error Eval Register RES37 [31:2] RESERVE FIELD 30 2 SET [1:1] Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect. 1 1 EVAL [0:0] Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect. 1 0 0 DRAEM 0x340 32 DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. E31 [31:31] DMA Region Access enable for Region M bit #31 1 31 E30 [30:30] DMA Region Access enable for Region M bit #30 1 30 E29 [29:29] DMA Region Access enable for Region M bit #29 1 29 E28 [28:28] DMA Region Access enable for Region M bit #28 1 28 E27 [27:27] DMA Region Access enable for Region M bit #27 1 27 E26 [26:26] DMA Region Access enable for Region M bit #26 1 26 E25 [25:25] DMA Region Access enable for Region M bit #25 1 25 E24 [24:24] DMA Region Access enable for Region M bit #24 1 24 E23 [23:23] DMA Region Access enable for Region M bit #23 1 23 E22 [22:22] DMA Region Access enable for Region M bit #22 1 22 E21 [21:21] DMA Region Access enable for Region M bit #21 1 21 E20 [20:20] DMA Region Access enable for Region M bit #20 1 20 E19 [19:19] DMA Region Access enable for Region M bit #19 1 19 E18 [18:18] DMA Region Access enable for Region M bit #18 1 18 E17 [17:17] DMA Region Access enable for Region M bit #17 1 17 E16 [16:16] DMA Region Access enable for Region M bit #16 1 16 E15 [15:15] DMA Region Access enable for Region M bit #15 1 15 E14 [14:14] DMA Region Access enable for Region M bit #14 1 14 E13 [13:13] DMA Region Access enable for Region M bit #13 1 13 E12 [12:12] DMA Region Access enable for Region M bit #12 1 12 E11 [11:11] DMA Region Access enable for Region M bit #11 1 11 E10 [10:10] DMA Region Access enable for Region M bit #10 1 10 E9 [9:9] DMA Region Access enable for Region M bit #9 1 9 E8 [8:8] DMA Region Access enable for Region M bit #8 1 8 E7 [7:7] DMA Region Access enable for Region M bit #7 1 7 E6 [6:6] DMA Region Access enable for Region M bit #6 1 6 E5 [5:5] DMA Region Access enable for Region M bit #5 1 5 E4 [4:4] DMA Region Access enable for Region M bit #4 1 4 E3 [3:3] DMA Region Access enable for Region M bit #3 1 3 E2 [2:2] DMA Region Access enable for Region M bit #2 1 2 E1 [1:1] DMA Region Access enable for Region M bit #1 1 1 E0 [0:0] DMA Region Access enable for Region M bit #0 1 0 0 DRAEHM 0x344 32 DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. E63 [31:31] DMA Region Access enable for Region M bit #63 1 31 E62 [30:30] DMA Region Access enable for Region M bit #62 1 30 E61 [29:29] DMA Region Access enable for Region M bit #61 1 29 E60 [28:28] DMA Region Access enable for Region M bit #60 1 28 E59 [27:27] DMA Region Access enable for Region M bit #59 1 27 E58 [26:26] DMA Region Access enable for Region M bit #58 1 26 E57 [25:25] DMA Region Access enable for Region M bit #57 1 25 E56 [24:24] DMA Region Access enable for Region M bit #56 1 24 E55 [23:23] DMA Region Access enable for Region M bit #55 1 23 E54 [22:22] DMA Region Access enable for Region M bit #54 1 22 E53 [21:21] DMA Region Access enable for Region M bit #53 1 21 E52 [20:20] DMA Region Access enable for Region M bit #52 1 20 E51 [19:19] DMA Region Access enable for Region M bit #51 1 19 E50 [18:18] DMA Region Access enable for Region M bit #50 1 18 E49 [17:17] DMA Region Access enable for Region M bit #49 1 17 E48 [16:16] DMA Region Access enable for Region M bit #48 1 16 E47 [15:15] DMA Region Access enable for Region M bit #47 1 15 E46 [14:14] DMA Region Access enable for Region M bit #46 1 14 E45 [13:13] DMA Region Access enable for Region M bit #45 1 13 E44 [12:12] DMA Region Access enable for Region M bit #44 1 12 E43 [11:11] DMA Region Access enable for Region M bit #43 1 11 E42 [10:10] DMA Region Access enable for Region M bit #42 1 10 E41 [9:9] DMA Region Access enable for Region M bit #41 1 9 E40 [8:8] DMA Region Access enable for Region M bit #40 1 8 E39 [7:7] DMA Region Access enable for Region M bit #39 1 7 E38 [6:6] DMA Region Access enable for Region M bit #38 1 6 E37 [5:5] DMA Region Access enable for Region M bit #37 1 5 E36 [4:4] DMA Region Access enable for Region M bit #36 1 4 E35 [3:3] DMA Region Access enable for Region M bit #35 1 3 E34 [2:2] DMA Region Access enable for Region M bit #34 1 2 E33 [1:1] DMA Region Access enable for Region M bit #33 1 1 E32 [0:0] DMA Region Access enable for Region M bit #32 1 0 0 QRAEN 0x380 32 QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt. RES38 [31:8] RESERVE FIELD 24 8 E7 [7:7] QDMA Region Access enable for Region M bit #7 1 7 E6 [6:6] QDMA Region Access enable for Region M bit #6 1 6 E5 [5:5] QDMA Region Access enable for Region M bit #5 1 5 E4 [4:4] QDMA Region Access enable for Region M bit #4 1 4 E3 [3:3] QDMA Region Access enable for Region M bit #3 1 3 E2 [2:2] QDMA Region Access enable for Region M bit #2 1 2 E1 [1:1] QDMA Region Access enable for Region M bit #1 1 1 E0 [0:0] QDMA Region Access enable for Region M bit #0 1 0 0 QNE0 0x400 32 Event Queue Entry Diagram for Queue n - Entry 0 RES39 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE1 0x404 32 Event Queue Entry Diagram for Queue n - Entry 1 RES40 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE2 0x408 32 Event Queue Entry Diagram for Queue n - Entry 2 RES41 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE3 0x40C 32 Event Queue Entry Diagram for Queue n - Entry 3 RES42 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE4 0x410 32 Event Queue Entry Diagram for Queue n - Entry 4 RES43 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE5 0x414 32 Event Queue Entry Diagram for Queue n - Entry 5 RES44 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE6 0x418 32 Event Queue Entry Diagram for Queue n - Entry 6 RES45 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE7 0x41C 32 Event Queue Entry Diagram for Queue n - Entry 7 RES46 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE8 0x420 32 Event Queue Entry Diagram for Queue n - Entry 8 RES47 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE9 0x424 32 Event Queue Entry Diagram for Queue n - Entry 9 RES48 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE10 0x428 32 Event Queue Entry Diagram for Queue n - Entry 0 RES49 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE11 0x42C 32 Event Queue Entry Diagram for Queue n - Entry 11 RES50 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE12 0x430 32 Event Queue Entry Diagram for Queue n - Entry 12 RES51 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE13 0x434 32 Event Queue Entry Diagram for Queue n - Entry 13 RES52 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE14 0x438 32 Event Queue Entry Diagram for Queue n - Entry 14 RES53 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE15 0x43C 32 Event Queue Entry Diagram for Queue n - Entry 15 RES54 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QSTATN 0x600 32 QSTATn Register Set RES55 [31:25] RESERVE FIELD 7 25 THRXCD [24:24] Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit. 1 24 RES56 [23:21] RESERVE FIELD 3 21 WM [20:16] Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full) 5 16 RES57 [15:13] RESERVE FIELD 3 13 NUMVAL [12:8] Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full) 5 8 RES58 [7:4] RESERVE FIELD 4 4 STRTPTR [3:0] Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry) 4 0 0 QWMTHRA 0x620 32 Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors. RES59 [31:13] RESERVE FIELD 19 13 Q1 [12:8] Queue Threshold for Q1 value 5 8 RES60 [7:5] RESERVE FIELD 3 5 Q0 [4:0] Queue Threshold for Q0 value 5 0 0 CCSTAT 0x640 32 CC Status Register RES61 [31:24] RESERVE FIELD 8 24 QUEACTV7 [23:23] Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7. 1 23 QUEACTV6 [22:22] Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6. 1 22 QUEACTV5 [21:21] Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5. 1 21 QUEACTV4 [20:20] Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4. 1 20 QUEACTV3 [19:19] Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3. 1 19 QUEACTV2 [18:18] Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2. 1 18 QUEACTV1 [17:17] Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1. 1 17 QUEACTV0 [16:16] Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0. 1 16 RES62 [15:14] RESERVE FIELD 2 14 COMPACTV [13:8] Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63. 6 8 RES63 [7:5] RESERVE FIELD 3 5 ACTV [4:4] Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy. 1 4 RES64 [3:3] RESERVE FIELD 1 3 TRACTV [2:2] Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active. 1 2 QEVTACTV [1:1] QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC. 1 1 EVTACTV [0:0] DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC. 1 0 0 AETCTL 0x700 32 Advanced Event Trigger Control EN [31:31] AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled. 1 31 RES65 [30:14] RESERVE FIELD 17 14 ENDINT [13:8] AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low) 6 8 RES66 [7:7] RESERVE FIELD 1 7 TYPE [6:6] AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events 1 6 STRTEVT [5:0] AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high) 6 0 0 AETSTAT 0x704 32 Advanced Event Trigger Stat RES67 [31:1] RESERVE FIELD 31 1 STAT [0:0] AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high. 1 0 0 AETCMD 0x708 32 AET Command RES68 [31:1] RESERVE FIELD 31 1 CLR [0:0] AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.. 1 0 0 ER 0x1000 32 Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ERH 0x1004 32 Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ECR 0x1008 32 Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ECRH 0x100C 32 Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ESR 0x1010 32 Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ESRH 0x1014 32 Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 CER 0x1018 32 Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 CERH 0x101C 32 Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EER 0x1020 32 Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EERH 0x1024 32 Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EECR 0x1028 32 Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EECRH 0x102C 32 Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EESR 0x1030 32 Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EESRH 0x1034 32 Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SER 0x1038 32 Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SERH 0x103C 32 Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SECR 0x1040 32 Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SECRH 0x1044 32 Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 IER 0x1050 32 Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IERH 0x1054 32 Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IECR 0x1058 32 Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IECRH 0x105C 32 Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IESR 0x1060 32 Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IESRH 0x1064 32 Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IPR 0x1068 32 Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IPRH 0x106C 32 Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 ICR 0x1070 32 Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 ICRH 0x1074 32 Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IEVAL 0x1078 32 Interrupt Eval Register RES69 [31:2] RESERVE FIELD 30 2 SET [1:1] Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect. 1 1 EVAL [0:0] Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.. 1 0 0 QER 0x1080 32 QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set. RES70 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEER 0x1084 32 QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En. RES71 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEECR 0x1088 32 QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. RES72 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEESR 0x108C 32 QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.. RES73 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSER 0x1090 32 QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. RES74 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSECR 0x1094 32 QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.. RES75 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ER_RN 0x2000 32 Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ERH_RN 0x2004 32 Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ECR_RN 0x2008 32 Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ECRH_RN 0x200C 32 Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ESR_RN 0x2010 32 Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ESRH_RN 0x2014 32 Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 CER_RN 0x2018 32 Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 CERH_RN 0x201C 32 Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EER_RN 0x2020 32 Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EERH_RN 0x2024 32 Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EECR_RN 0x2028 32 Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EECRH_RN 0x202C 32 Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EESR_RN 0x2030 32 Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EESRH_RN 0x2034 32 Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SER_RN 0x2038 32 Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SERH_RN 0x203C 32 Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SECR_RN 0x2040 32 Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SECRH_RN 0x2044 32 Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 IER_RN 0x2050 32 Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IERH_RN 0x2054 32 Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IECR_RN 0x2058 32 Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IECRH_RN 0x205C 32 Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IESR_RN 0x2060 32 Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IESRH_RN 0x2064 32 Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IPR_RN 0x2068 32 Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IPRH_RN 0x206C 32 Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 ICR_RN 0x2070 32 Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 ICRH_RN 0x2074 32 Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IEVAL_RN 0x2078 32 Interrupt Eval Register RES76 [31:2] RESERVE FIELD 30 2 SET [1:1] Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect. 1 1 EVAL [0:0] Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.. 1 0 0 QER_RN 0x2080 32 QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set. RES77 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEER_RN 0x2084 32 QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En. RES78 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEECR_RN 0x2088 32 QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. RES79 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEESR_RN 0x208C 32 QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.. RES80 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSER_RN 0x2090 32 QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. RES81 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSECR_RN 0x2094 32 QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.. RES82 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 OPT 0x4000 32 Options Parameter PRIV [31:31] Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege 1 31 RES83 [30:28] RESERVE FIELD 3 28 PRIVID [27:24] Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. 4 24 ITCCHEN [23:23] Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled. 1 23 TCCHEN [22:22] Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled. 1 22 ITCINTEN [21:21] Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER[TCC] bit must be set to 1 to generate interrupt) 1 21 TCINTEN [20:20] Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER[TCC] bit must be set to 1 to generate interrupt) 1 20 WIMODE [19:19] Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission) 1 19 RES84 [18:18] RESERVE FIELD 1 18 TCC [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER[TCC]) for chaining or in IER (bit IER[TCC]) for interrupts. 6 12 TCCMODE [11:11] Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally . 1 11 FWID [10:8] FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC. 3 8 RES85 [7:4] RESERVE FIELD 4 4 STATIC [3:3] Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed. 1 3 SYNCDIM [2:2] Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements 1 2 DAM [1:1] Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 SAM [0:0] Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 SRC 0x4004 32 Source Address SRC [31:0] Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true. 32 0 0 ABCNT 0x4008 32 A and B byte count BCNT [31:16] BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ... 16 16 ACNT [15:0] ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT. 16 0 0 DST 0x400C 32 Destination Address DST [31:0] Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true. 32 0 0 BIDX 0x4010 32 Register description is not available DBIDX [31:16] Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers. 16 16 SBIDX [15:0] Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers. 16 0 0 LNK 0x4014 32 Link and Reload parameters BCNTRLD [31:16] BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field. 16 16 LINK [15:0] Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field. 16 0 0 CIDX 0x4018 32 Register description is not available DCIDX [31:16] Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame. 16 16 SCIDX [15:0] Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame. 16 0 0 CCNT 0x401C 32 C byte count RES86 [31:16] RESERVE FIELD 16 16 CCNT [15:0] CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation. 16 0 0 TPCC_A 0x56000000 0 16416 registers TPCC PID 0x0 32 Peripheral ID Register SCHEME [31:30] PID Scheme: Used to distinguish between old ID scheme and current. Spare bit to encode future schemes EDMA uses 'new scheme' indicated with value of 0x1. 2 30 RES1 [29:28] RESERVE FIELD 2 28 FUNC [27:16] Function indicates a software compatible module family. 12 16 RTL [15:11] RTL Version 5 11 MAJOR [10:8] Major Revision 3 8 CUSTOM [7:6] Custom revision field: Not used on this version of EDMA. 2 6 MINOR [5:0] Minor Revision 6 0 0 CCCFG 0x4 32 CC Configuration Register RES2 [31:26] RESERVE FIELD 6 26 MPEXIST [25:25] Memory Protection Existence MPEXIST = 0 : No memory protection. MPEXIST = 1 : Memory Protection logic included. 1 25 CHMAPEXIST [24:24] Channel Mapping Existence CHMAPEXIST = 0 : No Channel mapping. CHMAPEXIST = 1 : Channel mapping logic included. 1 24 RES3 [23:22] RESERVE FIELD 2 22 NUMREGN [21:20] Number of MP and Shadow regions 2 20 RES4 [19:19] RESERVE FIELD 1 19 NUMTC [18:16] Number of Queues/Number of TCs 3 16 RES5 [15:15] RESERVE FIELD 1 15 NUMPAENTRY [14:12] Number of PaRAM entries 3 12 RES6 [11:11] RESERVE FIELD 1 11 NUMINTCH [10:8] Number of Interrupt Channels 3 8 RES7 [7:7] RESERVE FIELD 1 7 NUMQDMACH [6:4] Number of QDMA Channels 3 4 RES8 [3:3] RESERVE FIELD 1 3 NUMDMACH [2:0] Number of DMA Channels 3 0 0 QCHMAPN 0x200 32 QDMA Channel N Mapping Register RES10 [31:14] RESERVE FIELD 18 14 PAENTRY [13:5] PaRAM Entry number for QDMA Channel N. 9 5 TRWORD [4:2] TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized. 3 2 0 DMAQNUMN 0x240 32 DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel. RES11 [31:31] RESERVE FIELD 1 31 E7 [30:28] DMA Queue Number for event #7 3 28 RES12 [27:27] RESERVE FIELD 1 27 E6 [26:24] DMA Queue Number for event #6 3 24 RES13 [23:23] RESERVE FIELD 1 23 E5 [22:20] DMA Queue Number for event #5 3 20 RES14 [19:19] RESERVE FIELD 1 19 E4 [18:16] DMA Queue Number for event #4 3 16 RES15 [15:15] RESERVE FIELD 1 15 E3 [14:12] DMA Queue Number for event #3 3 12 RES16 [11:11] RESERVE FIELD 1 11 E2 [10:8] DMA Queue Number for event #2 3 8 RES17 [7:7] RESERVE FIELD 1 7 E1 [6:4] DMA Queue Number for event #1 3 4 RES18 [3:3] RESERVE FIELD 1 3 E0 [2:0] DMA Queue Number for event #0 3 0 0 QDMAQNUM 0x260 32 QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel. RES19 [31:31] RESERVE FIELD 1 31 E7 [30:28] QDMA Queue Number for event #7 3 28 RES20 [27:27] RESERVE FIELD 1 27 E6 [26:24] QDMA Queue Number for event #6 3 24 RES21 [23:23] RESERVE FIELD 1 23 E5 [22:20] QDMA Queue Number for event #5 3 20 RES22 [19:19] RESERVE FIELD 1 19 E4 [18:16] QDMA Queue Number for event #4 3 16 RES23 [15:15] RESERVE FIELD 1 15 E3 [14:12] QDMA Queue Number for event #3 3 12 RES24 [11:11] RESERVE FIELD 1 11 E2 [10:8] QDMA Queue Number for event #2 3 8 RES25 [7:7] RESERVE FIELD 1 7 E1 [6:4] QDMA Queue Number for event #1 3 4 RES26 [3:3] RESERVE FIELD 1 3 E0 [2:0] QDMA Queue Number for event #0 3 0 0 QUETCMAP 0x280 32 Queue to TC Mapping RES27 [31:7] RESERVE FIELD 25 7 TCNUMQ1 [6:4] TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to. 3 4 RES28 [3:3] RESERVE FIELD 1 3 TCNUMQ0 [2:0] TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to. 3 0 0 QUEPRI 0x284 32 Queue Priority RES29 [31:7] RESERVE FIELD 25 7 PRIQ1 [6:4] Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands. 3 4 RES30 [3:3] RESERVE FIELD 1 3 PRIQ0 [2:0] Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands. 3 0 0 EMR 0x300 32 Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt. E31 [31:31] Event Missed #31 1 31 E30 [30:30] Event Missed #30 1 30 E29 [29:29] Event Missed #29 1 29 E28 [28:28] Event Missed #28 1 28 E27 [27:27] Event Missed #27 1 27 E26 [26:26] Event Missed #26 1 26 E25 [25:25] Event Missed #25 1 25 E24 [24:24] Event Missed #24 1 24 E23 [23:23] Event Missed #23 1 23 E22 [22:22] Event Missed #22 1 22 E21 [21:21] Event Missed #21 1 21 E20 [20:20] Event Missed #20 1 20 E19 [19:19] Event Missed #19 1 19 E18 [18:18] Event Missed #18 1 18 E17 [17:17] Event Missed #17 1 17 E16 [16:16] Event Missed #16 1 16 E15 [15:15] Event Missed #15 1 15 E14 [14:14] Event Missed #14 1 14 E13 [13:13] Event Missed #13 1 13 E12 [12:12] Event Missed #12 1 12 E11 [11:11] Event Missed #11 1 11 E10 [10:10] Event Missed #10 1 10 E9 [9:9] Event Missed #9 1 9 E8 [8:8] Event Missed #8 1 8 E7 [7:7] Event Missed #7 1 7 E6 [6:6] Event Missed #6 1 6 E5 [5:5] Event Missed #5 1 5 E4 [4:4] Event Missed #4 1 4 E3 [3:3] Event Missed #3 1 3 E2 [2:2] Event Missed #2 1 2 E1 [1:1] Event Missed #1 1 1 E0 [0:0] Event Missed #0 1 0 0 EMRH 0x304 32 Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER) Set Events (ESR) and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including QEMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt. E63 [31:31] Event Missed #63 1 31 E62 [30:30] Event Missed #62 1 30 E61 [29:29] Event Missed #61 1 29 E60 [28:28] Event Missed #60 1 28 E59 [27:27] Event Missed #59 1 27 E58 [26:26] Event Missed #58 1 26 E57 [25:25] Event Missed #57 1 25 E56 [24:24] Event Missed #56 1 24 E55 [23:23] Event Missed #55 1 23 E54 [22:22] Event Missed #54 1 22 E53 [21:21] Event Missed #53 1 21 E52 [20:20] Event Missed #52 1 20 E51 [19:19] Event Missed #51 1 19 E50 [18:18] Event Missed #50 1 18 E49 [17:17] Event Missed #49 1 17 E48 [16:16] Event Missed #48 1 16 E47 [15:15] Event Missed #47 1 15 E46 [14:14] Event Missed #46 1 14 E45 [13:13] Event Missed #45 1 13 E44 [12:12] Event Missed #44 1 12 E43 [11:11] Event Missed #43 1 11 E42 [10:10] Event Missed #42 1 10 E41 [9:9] Event Missed #41 1 9 E40 [8:8] Event Missed #40 1 8 E39 [7:7] Event Missed #39 1 7 E38 [6:6] Event Missed #38 1 6 E37 [5:5] Event Missed #37 1 5 E36 [4:4] Event Missed #36 1 4 E35 [3:3] Event Missed #35 1 3 E34 [2:2] Event Missed #34 1 2 E33 [1:1] Event Missed #33 1 1 E32 [0:0] Event Missed #32 1 0 0 EMCR 0x308 32 Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC. E31 [31:31] Event Missed Clear #31 1 31 E30 [30:30] Event Missed Clear #30 1 30 E29 [29:29] Event Missed Clear #29 1 29 E28 [28:28] Event Missed Clear #28 1 28 E27 [27:27] Event Missed Clear #27 1 27 E26 [26:26] Event Missed Clear #26 1 26 E25 [25:25] Event Missed Clear #25 1 25 E24 [24:24] Event Missed Clear #24 1 24 E23 [23:23] Event Missed Clear #23 1 23 E22 [22:22] Event Missed Clear #22 1 22 E21 [21:21] Event Missed Clear #21 1 21 E20 [20:20] Event Missed Clear #20 1 20 E19 [19:19] Event Missed Clear #19 1 19 E18 [18:18] Event Missed Clear #18 1 18 E17 [17:17] Event Missed Clear #17 1 17 E16 [16:16] Event Missed Clear #16 1 16 E15 [15:15] Event Missed Clear #15 1 15 E14 [14:14] Event Missed Clear #14 1 14 E13 [13:13] Event Missed Clear #13 1 13 E12 [12:12] Event Missed Clear #12 1 12 E11 [11:11] Event Missed Clear #11 1 11 E10 [10:10] Event Missed Clear #10 1 10 E9 [9:9] Event Missed Clear #9 1 9 E8 [8:8] Event Missed Clear #8 1 8 E7 [7:7] Event Missed Clear #7 1 7 E6 [6:6] Event Missed Clear #6 1 6 E5 [5:5] Event Missed Clear #5 1 5 E4 [4:4] Event Missed Clear #4 1 4 E3 [3:3] Event Missed Clear #3 1 3 E2 [2:2] Event Missed Clear #2 1 2 E1 [1:1] Event Missed Clear #1 1 1 E0 [0:0] Event Missed Clear #0 1 0 0 EMCRH 0x30C 32 Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC. E63 [31:31] Event Missed Clear #63 1 31 E62 [30:30] Event Missed Clear #62 1 30 E61 [29:29] Event Missed Clear #61 1 29 E60 [28:28] Event Missed Clear #60 1 28 E59 [27:27] Event Missed Clear #59 1 27 E58 [26:26] Event Missed Clear #58 1 26 E57 [25:25] Event Missed Clear #57 1 25 E56 [24:24] Event Missed Clear #56 1 24 E55 [23:23] Event Missed Clear #55 1 23 E54 [22:22] Event Missed Clear #54 1 22 E53 [21:21] Event Missed Clear #53 1 21 E52 [20:20] Event Missed Clear #52 1 20 E51 [19:19] Event Missed Clear #51 1 19 E50 [18:18] Event Missed Clear #50 1 18 E49 [17:17] Event Missed Clear #49 1 17 E48 [16:16] Event Missed Clear #48 1 16 E47 [15:15] Event Missed Clear #47 1 15 E46 [14:14] Event Missed Clear #46 1 14 E45 [13:13] Event Missed Clear #45 1 13 E44 [12:12] Event Missed Clear #44 1 12 E43 [11:11] Event Missed Clear #43 1 11 E42 [10:10] Event Missed Clear #42 1 10 E41 [9:9] Event Missed Clear #41 1 9 E40 [8:8] Event Missed Clear #40 1 8 E39 [7:7] Event Missed Clear #39 1 7 E38 [6:6] Event Missed Clear #38 1 6 E37 [5:5] Event Missed Clear #37 1 5 E36 [4:4] Event Missed Clear #36 1 4 E35 [3:3] Event Missed Clear #35 1 3 E34 [2:2] Event Missed Clear #34 1 2 E33 [1:1] Event Missed Clear #33 1 1 E32 [0:0] Event Missed Clear #32 1 0 0 QEMR 0x310 32 QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced.. If any bit in the QEMR register is set (and all errors (including EMR/CCERR) were previously clear) then an error will be signaled with TPCC error interrupt. RES31 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event Missed #7 1 7 E6 [6:6] Event Missed #6 1 6 E5 [5:5] Event Missed #5 1 5 E4 [4:4] Event Missed #4 1 4 E3 [3:3] Event Missed #3 1 3 E2 [2:2] Event Missed #2 1 2 E1 [1:1] Event Missed #1 1 1 E0 [0:0] Event Missed #0 1 0 0 QEMCR 0x314 32 QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC. RES32 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event Missed Clear #7 1 7 E6 [6:6] Event Missed Clear #6 1 6 E5 [5:5] Event Missed Clear #5 1 5 E4 [4:4] Event Missed Clear #4 1 4 E3 [3:3] Event Missed Clear #3 1 3 E2 [2:2] Event Missed Clear #2 1 2 E1 [1:1] Event Missed Clear #1 1 1 E0 [0:0] Event Missed Clear #0 1 0 0 CCERR 0x318 32 CC Error Register RES33 [31:17] RESERVE FIELD 15 17 TCERR [16:16] Transfer Completion Code Error: TCCERR = 0 : Total number of allowed TCCs outstanding has not been reached. TCCERR = 1 : Total number of allowed TCCs has been reached. TCCERR can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors were previously clear) then an error will be signaled with TPCC error interrupt. 1 16 RES34 [15:8] RESERVE FIELD 8 8 QTHRXCD7 [7:7] Queue Threshold Error for Q7: QTHRXCD7 = 0 : Watermark/threshold has not been exceeded. QTHRXCD7 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD7 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 7 QTHRXCD6 [6:6] Queue Threshold Error for Q6: QTHRXCD6 = 0 : Watermark/threshold has not been exceeded. QTHRXCD6 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD6 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 6 QTHRXCD5 [5:5] Queue Threshold Error for Q5: QTHRXCD5 = 0 : Watermark/threshold has not been exceeded. QTHRXCD5 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD5 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 5 QTHRXCD4 [4:4] Queue Threshold Error for Q4: QTHRXCD4 = 0 : Watermark/threshold has not been exceeded. QTHRXCD4 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD4 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 4 QTHRXCD3 [3:3] Queue Threshold Error for Q3: QTHRXCD3 = 0 : Watermark/threshold has not been exceeded. QTHRXCD3 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD3 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 3 QTHRXCD2 [2:2] Queue Threshold Error for Q2: QTHRXCD2 = 0 : Watermark/threshold has not been exceeded. QTHRXCD2 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD2 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 2 QTHRXCD1 [1:1] Queue Threshold Error for Q1: QTHRXCD1 = 0 : Watermark/threshold has not been exceeded. QTHRXCD1 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD1 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 1 QTHRXCD0 [0:0] Queue Threshold Error for Q0: QTHRXCD0 = 0 : Watermark/threshold has not been exceeded. QTHRXCD0 = 1 : Watermark/threshold has been exceeded. CCERR.QTHRXCD0 can be cleared by writing a '1' to corresponding bit in CCERRCLR register. If any bit in the CCERR register is set (and all errors (including EMR/QEMR) were previously clear) then an error will be signaled with the TPCC error interrupt. 1 0 0 CCERRCLR 0x31C 32 CC Error Clear Register RES35 [31:17] RESERVE FIELD 15 17 TCERR [16:16] Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N. Writes of '0' have no affect. 1 16 RES36 [15:8] RESERVE FIELD 8 8 QTHRXCD7 [7:7] Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect. 1 7 QTHRXCD6 [6:6] Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect. 1 6 QTHRXCD5 [5:5] Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect. 1 5 QTHRXCD4 [4:4] Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect. 1 4 QTHRXCD3 [3:3] Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect. 1 3 QTHRXCD2 [2:2] Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect. 1 2 QTHRXCD1 [1:1] Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect. 1 1 QTHRXCD0 [0:0] Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect. 1 0 0 EEVAL 0x320 32 Error Eval Register RES37 [31:2] RESERVE FIELD 30 2 SET [1:1] Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR. CPU write of '0' has no effect. 1 1 EVAL [0:0] Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers. CPU write of '0' has no effect. 1 0 0 DRAEM 0x340 32 DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. E31 [31:31] DMA Region Access enable for Region M bit #31 1 31 E30 [30:30] DMA Region Access enable for Region M bit #30 1 30 E29 [29:29] DMA Region Access enable for Region M bit #29 1 29 E28 [28:28] DMA Region Access enable for Region M bit #28 1 28 E27 [27:27] DMA Region Access enable for Region M bit #27 1 27 E26 [26:26] DMA Region Access enable for Region M bit #26 1 26 E25 [25:25] DMA Region Access enable for Region M bit #25 1 25 E24 [24:24] DMA Region Access enable for Region M bit #24 1 24 E23 [23:23] DMA Region Access enable for Region M bit #23 1 23 E22 [22:22] DMA Region Access enable for Region M bit #22 1 22 E21 [21:21] DMA Region Access enable for Region M bit #21 1 21 E20 [20:20] DMA Region Access enable for Region M bit #20 1 20 E19 [19:19] DMA Region Access enable for Region M bit #19 1 19 E18 [18:18] DMA Region Access enable for Region M bit #18 1 18 E17 [17:17] DMA Region Access enable for Region M bit #17 1 17 E16 [16:16] DMA Region Access enable for Region M bit #16 1 16 E15 [15:15] DMA Region Access enable for Region M bit #15 1 15 E14 [14:14] DMA Region Access enable for Region M bit #14 1 14 E13 [13:13] DMA Region Access enable for Region M bit #13 1 13 E12 [12:12] DMA Region Access enable for Region M bit #12 1 12 E11 [11:11] DMA Region Access enable for Region M bit #11 1 11 E10 [10:10] DMA Region Access enable for Region M bit #10 1 10 E9 [9:9] DMA Region Access enable for Region M bit #9 1 9 E8 [8:8] DMA Region Access enable for Region M bit #8 1 8 E7 [7:7] DMA Region Access enable for Region M bit #7 1 7 E6 [6:6] DMA Region Access enable for Region M bit #6 1 6 E5 [5:5] DMA Region Access enable for Region M bit #5 1 5 E4 [4:4] DMA Region Access enable for Region M bit #4 1 4 E3 [3:3] DMA Region Access enable for Region M bit #3 1 3 E2 [2:2] DMA Region Access enable for Region M bit #2 1 2 E1 [1:1] DMA Region Access enable for Region M bit #1 1 1 E0 [0:0] DMA Region Access enable for Region M bit #0 1 0 0 DRAEHM 0x344 32 DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. E63 [31:31] DMA Region Access enable for Region M bit #63 1 31 E62 [30:30] DMA Region Access enable for Region M bit #62 1 30 E61 [29:29] DMA Region Access enable for Region M bit #61 1 29 E60 [28:28] DMA Region Access enable for Region M bit #60 1 28 E59 [27:27] DMA Region Access enable for Region M bit #59 1 27 E58 [26:26] DMA Region Access enable for Region M bit #58 1 26 E57 [25:25] DMA Region Access enable for Region M bit #57 1 25 E56 [24:24] DMA Region Access enable for Region M bit #56 1 24 E55 [23:23] DMA Region Access enable for Region M bit #55 1 23 E54 [22:22] DMA Region Access enable for Region M bit #54 1 22 E53 [21:21] DMA Region Access enable for Region M bit #53 1 21 E52 [20:20] DMA Region Access enable for Region M bit #52 1 20 E51 [19:19] DMA Region Access enable for Region M bit #51 1 19 E50 [18:18] DMA Region Access enable for Region M bit #50 1 18 E49 [17:17] DMA Region Access enable for Region M bit #49 1 17 E48 [16:16] DMA Region Access enable for Region M bit #48 1 16 E47 [15:15] DMA Region Access enable for Region M bit #47 1 15 E46 [14:14] DMA Region Access enable for Region M bit #46 1 14 E45 [13:13] DMA Region Access enable for Region M bit #45 1 13 E44 [12:12] DMA Region Access enable for Region M bit #44 1 12 E43 [11:11] DMA Region Access enable for Region M bit #43 1 11 E42 [10:10] DMA Region Access enable for Region M bit #42 1 10 E41 [9:9] DMA Region Access enable for Region M bit #41 1 9 E40 [8:8] DMA Region Access enable for Region M bit #40 1 8 E39 [7:7] DMA Region Access enable for Region M bit #39 1 7 E38 [6:6] DMA Region Access enable for Region M bit #38 1 6 E37 [5:5] DMA Region Access enable for Region M bit #37 1 5 E36 [4:4] DMA Region Access enable for Region M bit #36 1 4 E35 [3:3] DMA Region Access enable for Region M bit #35 1 3 E34 [2:2] DMA Region Access enable for Region M bit #34 1 2 E33 [1:1] DMA Region Access enable for Region M bit #33 1 1 E32 [0:0] DMA Region Access enable for Region M bit #32 1 0 0 QRAEN 0x380 32 QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt. RES38 [31:8] RESERVE FIELD 24 8 E7 [7:7] QDMA Region Access enable for Region M bit #7 1 7 E6 [6:6] QDMA Region Access enable for Region M bit #6 1 6 E5 [5:5] QDMA Region Access enable for Region M bit #5 1 5 E4 [4:4] QDMA Region Access enable for Region M bit #4 1 4 E3 [3:3] QDMA Region Access enable for Region M bit #3 1 3 E2 [2:2] QDMA Region Access enable for Region M bit #2 1 2 E1 [1:1] QDMA Region Access enable for Region M bit #1 1 1 E0 [0:0] QDMA Region Access enable for Region M bit #0 1 0 0 QNE0 0x400 32 Event Queue Entry Diagram for Queue n - Entry 0 RES39 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE1 0x404 32 Event Queue Entry Diagram for Queue n - Entry 1 RES40 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE2 0x408 32 Event Queue Entry Diagram for Queue n - Entry 2 RES41 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE3 0x40C 32 Event Queue Entry Diagram for Queue n - Entry 3 RES42 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE4 0x410 32 Event Queue Entry Diagram for Queue n - Entry 4 RES43 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE5 0x414 32 Event Queue Entry Diagram for Queue n - Entry 5 RES44 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE6 0x418 32 Event Queue Entry Diagram for Queue n - Entry 6 RES45 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE7 0x41C 32 Event Queue Entry Diagram for Queue n - Entry 7 RES46 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE8 0x420 32 Event Queue Entry Diagram for Queue n - Entry 8 RES47 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE9 0x424 32 Event Queue Entry Diagram for Queue n - Entry 9 RES48 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE10 0x428 32 Event Queue Entry Diagram for Queue n - Entry 0 RES49 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE11 0x42C 32 Event Queue Entry Diagram for Queue n - Entry 11 RES50 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE12 0x430 32 Event Queue Entry Diagram for Queue n - Entry 12 RES51 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE13 0x434 32 Event Queue Entry Diagram for Queue n - Entry 13 RES52 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE14 0x438 32 Event Queue Entry Diagram for Queue n - Entry 14 RES53 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QNE15 0x43C 32 Event Queue Entry Diagram for Queue n - Entry 15 RES54 [31:8] RESERVE FIELD 24 8 ETYPE [7:6] Event Type: Specifies the specific Event Type for the given entry in the Event Queue. 2 6 ENUM [5:0] Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (ER/ESR/CER) ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (QER) ENUM will range between 0 and NUM_QDMACH (up to 7). 6 0 0 QSTATN 0x600 32 QSTATn Register Set RES55 [31:25] RESERVE FIELD 7 25 THRXCD [24:24] Threshold Exceeded: THRXCD = 0 : Threshold specified by QWMTHR(A B).Qn has not been exceeded. THRXCD = 1 : Threshold specified by QWMTHR(A B).Qn has been exceeded. QSTATn.THRXCD is cleared via CCERR.WMCLRn bit. 1 24 RES56 [23:21] RESERVE FIELD 3 21 WM [20:16] Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn.WM is cleared via CCERR.WMCLRn bit. Legal values = 0x0 (empty) to 0x10 (full) 5 16 RES57 [15:13] RESERVE FIELD 3 13 NUMVAL [12:8] Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values = 0x0 (empty) to 0x10 (full) 5 8 RES58 [7:4] RESERVE FIELD 4 4 STRTPTR [3:0] Start Pointer: Represents the offset to the head entry of QueueN in units of entries. Always enabled. Legal values = 0x0 (0th entry) to 0xF (15th entry) 4 0 0 QWMTHRA 0x620 32 Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors. RES59 [31:13] RESERVE FIELD 19 13 Q1 [12:8] Queue Threshold for Q1 value 5 8 RES60 [7:5] RESERVE FIELD 3 5 Q0 [4:0] Queue Threshold for Q0 value 5 0 0 CCSTAT 0x640 32 CC Status Register RES61 [31:24] RESERVE FIELD 8 24 QUEACTV7 [23:23] Queue 7 Active QUEACTV7 = 0 : No Evts are queued in Q7. QUEACTV7 = 1 : At least one TR is queued in Q7. 1 23 QUEACTV6 [22:22] Queue 6 Active QUEACTV6 = 0 : No Evts are queued in Q6. QUEACTV6 = 1 : At least one TR is queued in Q6. 1 22 QUEACTV5 [21:21] Queue 5 Active QUEACTV5 = 0 : No Evts are queued in Q5. QUEACTV5 = 1 : At least one TR is queued in Q5. 1 21 QUEACTV4 [20:20] Queue 4 Active QUEACTV4 = 0 : No Evts are queued in Q4. QUEACTV4 = 1 : At least one TR is queued in Q4. 1 20 QUEACTV3 [19:19] Queue 3 Active QUEACTV3 = 0 : No Evts are queued in Q3. QUEACTV3 = 1 : At least one TR is queued in Q3. 1 19 QUEACTV2 [18:18] Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2. 1 18 QUEACTV1 [17:17] Queue 1 Active QUEACTV1 = 0 : No Evts are queued in Q1. QUEACTV1 = 1 : At least one TR is queued in Q1. 1 17 QUEACTV0 [16:16] Queue 0 Active QUEACTV0 = 0 : No Evts are queued in Q0. QUEACTV0 = 1 : At least one TR is queued in Q0. 1 16 RES62 [15:14] RESERVE FIELD 2 14 COMPACTV [13:8] Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit. COMPACTV = 0 : No completion requests outstanding. COMPACTV = 1: Total of '1' completion request outstanding. ... COMPACTV = 63 : Total of 63 completion requests are outstanding. No additional TRs will be submitted until count is less than 63. 6 8 RES63 [7:5] RESERVE FIELD 3 5 ACTV [4:4] Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals. The ACTV bit must remain high through the life of a TR. ACTV = 0 : Channel is idle. ACTV = 1 : Channel is busy. 1 4 RES64 [3:3] RESERVE FIELD 1 3 TRACTV [2:2] Transfer Request Active: TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active. 1 2 QEVTACTV [1:1] QDMA Event Active: QEVTACTV = 0 : No enabled QDMA Events are active within the CC. QEVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC. 1 1 EVTACTV [0:0] DMA Event Active: EVTACTV = 0 : No enabled DMA Events are active within the CC. EVTACTV = 1 : At least one enabled DMA Event (ER & EER ESR CER) is active within the CC. 1 0 0 AETCTL 0x700 32 Advanced Event Trigger Control EN [31:31] AET Enable: EN = 0 : AET event generation is disabled. EN = 1 : AET event generation is enabled. 1 31 RES65 [30:14] RESERVE FIELD 17 14 ENDINT [13:8] AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low) 6 8 RES66 [7:7] RESERVE FIELD 1 7 TYPE [6:6] AET Event Type: TYPE = 0 : Event specified by STARTEVT applies to DMA Events (set by ER ESR or CER) TYPE = 1 : Event specified by STARTEVT applies to QDMA Events 1 6 STRTEVT [5:0] AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high) 6 0 0 AETSTAT 0x704 32 Advanced Event Trigger Stat RES67 [31:1] RESERVE FIELD 31 1 STAT [0:0] AET Status: AETSTAT = 0 : tpcc_aet is currently low. AETSTAT = 1 : tpcc_aet is currently high. 1 0 0 AETCMD 0x708 32 AET Command RES68 [31:1] RESERVE FIELD 31 1 CLR [0:0] AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared. CPU write of '0' has no effect.. 1 0 0 ER 0x1000 32 Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ERH 0x1004 32 Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ECR 0x1008 32 Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ECRH 0x100C 32 Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ESR 0x1010 32 Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ESRH 0x1014 32 Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 CER 0x1018 32 Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 CERH 0x101C 32 Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EER 0x1020 32 Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EERH 0x1024 32 Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EECR 0x1028 32 Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EECRH 0x102C 32 Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EESR 0x1030 32 Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EESRH 0x1034 32 Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SER 0x1038 32 Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SERH 0x103C 32 Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SECR 0x1040 32 Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SECRH 0x1044 32 Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 IER 0x1050 32 Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IERH 0x1054 32 Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IECR 0x1058 32 Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IECRH 0x105C 32 Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IESR 0x1060 32 Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IESRH 0x1064 32 Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IPR 0x1068 32 Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IPRH 0x106C 32 Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 ICR 0x1070 32 Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 ICRH 0x1074 32 Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IEVAL 0x1078 32 Interrupt Eval Register RES69 [31:2] RESERVE FIELD 30 2 SET [1:1] Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect. 1 1 EVAL [0:0] Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.. 1 0 0 QER 0x1080 32 QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set. RES70 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEER 0x1084 32 QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En. RES71 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEECR 0x1088 32 QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. RES72 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEESR 0x108C 32 QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.. RES73 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSER 0x1090 32 QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. RES74 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSECR 0x1094 32 QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.. RES75 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ER_RN 0x2000 32 Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EER register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECR pseudo-register. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ERH_RN 0x2004 32 Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. ERH.En bit is set when the input event #n transitions from inactive (low) to active (high) regardless of the state of EERH.En bit. ER.En bit is cleared when the corresponding event is prioritized and serviced. If the ERH.En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the EERH register is set then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the ECRH pseudo-register. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ECR_RN 0x2008 32 Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ECRH_RN 0x200C 32 Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 ESR_RN 0x2010 32 Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 ESRH_RN 0x2014 32 Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 CER_RN 0x2018 32 Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CER.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CER.En bit is cleared when the corresponding event is prioritized and serviced. If the CER.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CER.En cannot be set or cleared via software. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 CERH_RN 0x201C 32 Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. CERH.En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface or is generated internally via Early Completion path. CERH.En bit is cleared when the corresponding event is prioritized and serviced. If the CERH.En bit is already set and the corresponding chaining completion code is returned from the TC then the corresponding bit in the Event Missed Register is set. CERH.En cannot be set or cleared via software. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EER_RN 0x2020 32 Event Enable Register: Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note that if a bit is set in ER.En while EER.En is disabled no action is taken. If EER.En is enabled at a later point (and ER.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EER.En is not directly writeable. Events can be enabled via writes to EESR and can be disabled via writes to EECR register. EER.En = 0: ER.En is not enabled to trigger DMA transfers. EER.En = 1: ER.En is enabled to trigger DMA transfers. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EERH_RN 0x2024 32 Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events. ERH.En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register (CERH) or Event Set Register (ESRH). Note that if a bit is set in ERH.En while EERH.En is disabled no action is taken. If EERH.En is enabled at a later point (and ERH.En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' EERH.En is not directly writeable. Events can be enabled via writes to EESRH and can be disabled via writes to EECRH register. EERH.En = 0: ER.En is not enabled to trigger DMA transfers. EERH.En = 1: ER.En is enabled to trigger DMA transfers. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EECR_RN 0x2028 32 Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EECRH_RN 0x202C 32 Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 EESR_RN 0x2030 32 Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set. CPU write of '0' has no effect.. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 EESRH_RN 0x2034 32 Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set. CPU write of '0' has no effect.. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SER_RN 0x2038 32 Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SERH_RN 0x203C 32 Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 SECR_RN 0x2040 32 Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers. CPU write of '1' to the SECR.En bit clears the SER register. CPU write of '0' has no effect. E31 [31:31] Event #31 1 31 E30 [30:30] Event #30 1 30 E29 [29:29] Event #29 1 29 E28 [28:28] Event #28 1 28 E27 [27:27] Event #27 1 27 E26 [26:26] Event #26 1 26 E25 [25:25] Event #25 1 25 E24 [24:24] Event #24 1 24 E23 [23:23] Event #23 1 23 E22 [22:22] Event #22 1 22 E21 [21:21] Event #21 1 21 E20 [20:20] Event #20 1 20 E19 [19:19] Event #19 1 19 E18 [18:18] Event #18 1 18 E17 [17:17] Event #17 1 17 E16 [16:16] Event #16 1 16 E15 [15:15] Event #15 1 15 E14 [14:14] Event #14 1 14 E13 [13:13] Event #13 1 13 E12 [12:12] Event #12 1 12 E11 [11:11] Event #11 1 11 E10 [10:10] Event #10 1 10 E9 [9:9] Event #9 1 9 E8 [8:8] Event #8 1 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 SECRH_RN 0x2044 32 Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers. CPU write of '1' to the SECRH.En bit clears the SERH register. CPU write of '0' has no effect. E63 [31:31] Event #63 1 31 E62 [30:30] Event #62 1 30 E61 [29:29] Event #61 1 29 E60 [28:28] Event #60 1 28 E59 [27:27] Event #59 1 27 E58 [26:26] Event #58 1 26 E57 [25:25] Event #57 1 25 E56 [24:24] Event #56 1 24 E55 [23:23] Event #55 1 23 E54 [22:22] Event #54 1 22 E53 [21:21] Event #53 1 21 E52 [20:20] Event #52 1 20 E51 [19:19] Event #51 1 19 E50 [18:18] Event #50 1 18 E49 [17:17] Event #49 1 17 E48 [16:16] Event #48 1 16 E47 [15:15] Event #47 1 15 E46 [14:14] Event #46 1 14 E45 [13:13] Event #45 1 13 E44 [12:12] Event #44 1 12 E43 [11:11] Event #43 1 11 E42 [10:10] Event #42 1 10 E41 [9:9] Event #41 1 9 E40 [8:8] Event #40 1 8 E39 [7:7] Event #39 1 7 E38 [6:6] Event #38 1 6 E37 [5:5] Event #37 1 5 E36 [4:4] Event #36 1 4 E35 [3:3] Event #35 1 3 E34 [2:2] Event #34 1 2 E33 [1:1] Event #33 1 1 E32 [0:0] Event #32 1 0 0 IER_RN 0x2050 32 Int Enable Register: IER.In is not directly writeable. Interrupts can be enabled via writes to IESR and can be disabled via writes to IECR register. IER.In = 0: IPR.In is NOT enabled for interrupts. IER.In = 1: IPR.In IS enabled for interrupts. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IERH_RN 0x2054 32 Int Enable Register (High Part): IERH.In is not directly writeable. Interrupts can be enabled via writes to IESRH and can be disabled via writes to IECRH register. IERH.In = 0: IPRH.In is NOT enabled for interrupts. IERH.In = 1: IPRH.In IS enabled for interrupts. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IECR_RN 0x2058 32 Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IECRH_RN 0x205C 32 Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IESR_RN 0x2060 32 Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set. CPU write of '0' has no effect.. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IESRH_RN 0x2064 32 Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set. CPU write of '0' has no effect.. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IPR_RN 0x2068 32 Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected. IPR.In bit is cleared via software by writing a '1' to ICR.In bit. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 IPRH_RN 0x206C 32 Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected. IPRH.In bit is cleared via software by writing a '1' to ICRH.In bit. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 ICR_RN 0x2070 32 Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared. CPU write of '0' has no effect. All IPR.In bits must be cleared before additional interrupts will be asserted by CC. I31 [31:31] Interrupt associated with TCC #31 1 31 I30 [30:30] Interrupt associated with TCC #30 1 30 I29 [29:29] Interrupt associated with TCC #29 1 29 I28 [28:28] Interrupt associated with TCC #28 1 28 I27 [27:27] Interrupt associated with TCC #27 1 27 I26 [26:26] Interrupt associated with TCC #26 1 26 I25 [25:25] Interrupt associated with TCC #25 1 25 I24 [24:24] Interrupt associated with TCC #24 1 24 I23 [23:23] Interrupt associated with TCC #23 1 23 I22 [22:22] Interrupt associated with TCC #22 1 22 I21 [21:21] Interrupt associated with TCC #21 1 21 I20 [20:20] Interrupt associated with TCC #20 1 20 I19 [19:19] Interrupt associated with TCC #19 1 19 I18 [18:18] Interrupt associated with TCC #18 1 18 I17 [17:17] Interrupt associated with TCC #17 1 17 I16 [16:16] Interrupt associated with TCC #16 1 16 I15 [15:15] Interrupt associated with TCC #15 1 15 I14 [14:14] Interrupt associated with TCC #14 1 14 I13 [13:13] Interrupt associated with TCC #13 1 13 I12 [12:12] Interrupt associated with TCC #12 1 12 I11 [11:11] Interrupt associated with TCC #11 1 11 I10 [10:10] Interrupt associated with TCC #10 1 10 I9 [9:9] Interrupt associated with TCC #9 1 9 I8 [8:8] Interrupt associated with TCC #8 1 8 I7 [7:7] Interrupt associated with TCC #7 1 7 I6 [6:6] Interrupt associated with TCC #6 1 6 I5 [5:5] Interrupt associated with TCC #5 1 5 I4 [4:4] Interrupt associated with TCC #4 1 4 I3 [3:3] Interrupt associated with TCC #3 1 3 I2 [2:2] Interrupt associated with TCC #2 1 2 I1 [1:1] Interrupt associated with TCC #1 1 1 I0 [0:0] Interrupt associated with TCC #0 1 0 0 ICRH_RN 0x2074 32 Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared. CPU write of '0' has no effect. All IPRH.In bits must be cleared before additional interrupts will be asserted by CC. I63 [31:31] Interrupt associated with TCC #63 1 31 I62 [30:30] Interrupt associated with TCC #62 1 30 I61 [29:29] Interrupt associated with TCC #61 1 29 I60 [28:28] Interrupt associated with TCC #60 1 28 I59 [27:27] Interrupt associated with TCC #59 1 27 I58 [26:26] Interrupt associated with TCC #58 1 26 I57 [25:25] Interrupt associated with TCC #57 1 25 I56 [24:24] Interrupt associated with TCC #56 1 24 I55 [23:23] Interrupt associated with TCC #55 1 23 I54 [22:22] Interrupt associated with TCC #54 1 22 I53 [21:21] Interrupt associated with TCC #53 1 21 I52 [20:20] Interrupt associated with TCC #52 1 20 I51 [19:19] Interrupt associated with TCC #51 1 19 I50 [18:18] Interrupt associated with TCC #50 1 18 I49 [17:17] Interrupt associated with TCC #49 1 17 I48 [16:16] Interrupt associated with TCC #48 1 16 I47 [15:15] Interrupt associated with TCC #47 1 15 I46 [14:14] Interrupt associated with TCC #46 1 14 I45 [13:13] Interrupt associated with TCC #45 1 13 I44 [12:12] Interrupt associated with TCC #44 1 12 I43 [11:11] Interrupt associated with TCC #43 1 11 I42 [10:10] Interrupt associated with TCC #42 1 10 I41 [9:9] Interrupt associated with TCC #41 1 9 I40 [8:8] Interrupt associated with TCC #40 1 8 I39 [7:7] Interrupt associated with TCC #39 1 7 I38 [6:6] Interrupt associated with TCC #38 1 6 I37 [5:5] Interrupt associated with TCC #37 1 5 I36 [4:4] Interrupt associated with TCC #36 1 4 I35 [3:3] Interrupt associated with TCC #35 1 3 I34 [2:2] Interrupt associated with TCC #34 1 2 I33 [1:1] Interrupt associated with TCC #33 1 1 I32 [0:0] Interrupt associated with TCC #32 1 0 0 IEVAL_RN 0x2078 32 Interrupt Eval Register RES76 [31:2] RESERVE FIELD 30 2 SET [1:1] Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn). CPU write of '0' has no effect. 1 1 EVAL [0:0] Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn). CPU write of '0' has no effect.. 1 0 0 QER_RN 0x2080 32 QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. QER.En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. QER.En bit is cleared when the corresponding event is prioritized and serviced. QER.En is also cleared when user writes a '1' to the QSECR.En bit. If the QER.En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and QEER register is set then the corresponding bit in the QDMA Event Missed Register is set. RES77 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEER_RN 0x2084 32 QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N. QEER.En is not directly writeable. QDMA channels can be enabled via writes to QEESR and can be disabled via writes to QEECR register. QEER.En = 1 The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in QER.En. QEER.En = 0 The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in QER.En. RES78 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEECR_RN 0x2088 32 QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared. CPU write of '0' has no effect.. RES79 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QEESR_RN 0x208C 32 QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set. CPU write of '0' has no effect.. RES80 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSER_RN 0x2090 32 QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events. RES81 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 QSECR_RN 0x2094 32 QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register). CPU write of '1' to the QSECR.En bit clears the QSER.En and QER.En register fields. CPU write of '0' has no effect.. RES82 [31:8] RESERVE FIELD 24 8 E7 [7:7] Event #7 1 7 E6 [6:6] Event #6 1 6 E5 [5:5] Event #5 1 5 E4 [4:4] Event #4 1 4 E3 [3:3] Event #3 1 3 E2 [2:2] Event #2 1 2 E1 [1:1] Event #1 1 1 E0 [0:0] Event #0 1 0 0 OPT 0x4000 32 Options Parameter PRIV [31:31] Privilege level: privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. PRIV = 0 : User level privilege PRIV = 1 : Supervisor level privilege 1 31 RES83 [30:28] RESERVE FIELD 3 28 PRIVID [27:24] Privilege ID: Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus. 4 24 ITCCHEN [23:23] Intermediate transfer completion chaining enable: 0: Intermediate transfer complete chaining is disabled. 1: Intermediate transfer complete chaining is enabled. 1 23 TCCHEN [22:22] Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled. 1 22 ITCINTEN [21:21] Intermediate transfer completion interrupt enable: 0: Intermediate transfer complete interrupt is disabled. 1: Intermediate transfer complete interrupt is enabled (corresponding IER[TCC] bit must be set to 1 to generate interrupt) 1 21 TCINTEN [20:20] Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled (corresponding IER[TCC] bit must be set to 1 to generate interrupt) 1 20 WIMODE [19:19] Backward compatibility mode: 0: Normal operation 1 : WI Backwards Compatibility mode forces BCNT to be adjusted by '1' upon TR submission (0 means 1 1 means 2 ... ) and forces ACNT to be treated as a word-count (left shifted by 2 by hardware to create byte cnt for TR submission) 1 19 RES84 [18:18] RESERVE FIELD 1 18 TCC [17:12] Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER (bit CER[TCC]) for chaining or in IER (bit IER[TCC]) for interrupts. 6 12 TCCMODE [11:11] Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt. 0: Normal Completion A transfer is considered completed after the transfer parameters are returned to the CC from the TC (which was returned from the peripheral). 1: Early Completion A transfer is considered completed after the CC submits a TR to the TC. CC generates completion code internally . 1 11 FWID [10:8] FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC. 3 8 RES85 [7:4] RESERVE FIELD 4 4 STATIC [3:3] Static Entry: 0: Entry is updated as normal 1: Entry is static Count and Address updates are not updated after TRP is submitted. Linking is not performed. 1 3 SYNCDIM [2:2] Transfer Synchronization Dimension: 0: A-Sync Each event triggers the transfer of ACNT elements. 1: AB-Sync Each event triggers the transfer of BCNT arrays of ACNT elements 1 2 DAM [1:1] Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC. 0: INCR Dst addressing within an array increments. Dst is not a FIFO. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width. 1 1 SAM [0:0] Source Address Mode: Source Address Mode within an array. Pass-thru to TC. 0: INCR Src addressing within an array increments. Source is not a FIFO. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width. 1 0 0 SRC 0x4004 32 Source Address SRC [31:0] Source Address: The 32-bit source address parameters specify the starting byte address of the source . If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true. 32 0 0 ABCNT 0x4008 32 A and B byte count BCNT [31:16] BCNT : Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation valid values for BCNT can be anywhere between 1 and 65535. Therefore the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame and BCNT=0 means 0 arrays in the frame. In normal mode a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the programmed BCNT value will be incremented by '1' before submission to TC. I.e. 0 means 1 1 means 2 2 means 3 ... 16 16 ACNT [15:0] ACNT : number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the OPT.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0 it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition the ACNT definition will disregard the 2 msbits. I.e. a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer resulting in null or dummy operation dependent on the state of BCNT and CCNT. 16 0 0 DST 0x400C 32 Destination Address DST [31:0] Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by the OPT.FWID field. No errors are recognized here but TC will assert error if this is not true. 32 0 0 BIDX 0x4010 32 Register description is not available DBIDX [31:16] Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers. 16 16 SBIDX [15:0] Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers. 16 0 0 LNK 0x4014 32 Link and Reload parameters BCNTRLD [31:16] BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT not thus BCNTRLD is a don't care field. 16 16 LINK [15:0] Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e. after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore if the user uses the literal address with a range from 0x4000 to 0x7FFF it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000 thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs) behavior is undefined for the user (i.e. don't have to test it). In the former case (2 msbs) user should be able to take advantage of this feature (i.e. do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid/Secure state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e. a value of 0x3FFE is a non-NULL PaRAM link field. 16 0 0 CIDX 0x4018 32 Register description is not available DCIDX [31:16] Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a ABsync transfer is the first array in the frame. 16 16 SCIDX [15:0] Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied the current array in an A-sync transfer is the last array in the frame while the current array in a AB-sync transfer is the first array in the frame. 16 0 0 CCNT 0x401C 32 C byte count RES86 [31:16] RESERVE FIELD 16 16 CCNT [15:0] CCNT : Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation. 16 0 0 APP_RCM 0x56040000 0 4148 registers PID 0x0 32 PID register 16 16 5 11 3 8 2 6 6 0 0 APP_CPU_CLKCTL 0x4 32 APP_CPU_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 srcsel [15:4] Select the source clock: 0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. 12 4 Reserved [3:0] Reserved 4 0 0 APP_CPU_CLKSTAT 0x8 32 APP_CPU_CLKSTAT currclk [11:4] Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK 8 4 currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_CAN_CLKCTL 0xC 32 APP_CAN_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 srcsel [15:4] 0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLKFor other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. 12 4 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_CAN_CLKSTAT 0x10 32 APP_CAN_CLKSTAT currclk [11:4] Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK 8 4 currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_SPI_CLKCTL 0x14 32 APP_SPI_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 srcsel [15:4] 0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. 12 4 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_SPI_CLKSTAT 0x18 32 APP_SPI_CLKSTAT currclk [11:4] Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK 8 4 currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_SPI_BUSIF_CLKCTL 0x1C 32 APP_SPI_BUSIF_CLKCTL divr [11:0] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 0 0 APP_SPI_BUSIF_CLKSTAT 0x20 32 APP_SPI_BUSIF_CLKSTAT currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_QSPI_CLKCTL 0x24 32 APP_QSPI_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 srcsel [15:4] 0x0 : OSC_CLK 0x1 : OSC_CLKX2 0x2 : MDLL_CLK 0x3 : FAST_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. 12 4 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_QSPI_CLKSTAT 0x28 32 APP_QSPI_CLKSTAT currclk [11:4] Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK 8 4 currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 TOPSS_CLKCTL 0x2C 32 TOPSS_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 srcsel [15:4] 0x0 : OSC_CLK 0x1 : SLOW_CLK 0x2 : MDLL 0x3 : FAST_CLK 0x4 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. 12 4 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 TOPSS_CLKSTAT 0x30 32 TOPSS_CLKSTAT currclk [11:4] Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK 8 4 currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_RTI_CLKCTL 0x34 32 APP_RTI_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 srcsel [15:4] 0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK (Ungated OSC_CLK for RTI in Sleep mode) 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. 12 4 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_RTI_CLKSTAT 0x38 32 APP_RTI_CLKSTAT currclk [11:4] Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK 8 4 currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_WD_CLKCTL 0x3C 32 APP_WD_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 srcsel [15:4] 0x0 : OSC_CLK 0x1 : XREF_IN 0x2 : OSC_CLK 0x3 : SLOW_CLK 0x4 : SLOW_CLK 0x5 : SLOW_CLK 0x6 : SLOW_CLK 0x7 : SLOW_CLK For other values if the lower 3 bits matches with above, corresponding clock is selected. Data should be loaded as multibit. For example: if Clock source 0x5 should be selected then 0x555 should be configured to the register. 12 4 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_WD_CLKSTAT 0x40 32 APP_WD_CLKSTAT currclk [11:4] Current Clock selected by GCM Clock Mux 0x1 : XTALCLK 0x2 : XTALCLKX2 0x4 : MDLL 0x8 : APLL/DPLL 0x10 : RCCLK 8 4 currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_UART_0_CLKCTL 0x44 32 APP_UART_0_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_UART_0_CLKSTAT 0x48 32 APP_UART_0_CLKSTAT currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_UART_1_CLKCTL 0x4C 32 APP_UART_1_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_UART_1_CLKSTAT 0x50 32 APP_UART_1_CLKSTAT currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_I2C_CLKCTL 0x54 32 APP_I2C_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_I2C_CLKSTAT 0x58 32 APP_I2C_CLKSTAT currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 APP_LIN_CLKCTL 0x5C 32 APP_LIN_CLKCTL divr [27:16] Divide value 0x0 : div1 0x1 : div2 0x2 : div3 . . 0xF = div16 Data should be loaded as multibit. For example: if divider value of '0x8' should be selected then '0x888' should be configured to the register. 12 16 gate [3:0] 0x0 : Enable the Clock 0x7 : Gate the clock 4 0 0 APP_LIN_CLKSTAT 0x60 32 APP_LIN_CLKSTAT currdivr [3:0] Gives the current divr setting used by the clock divider. 4 0 0 RESERVED0 0x64 32 RESERVED0 wphres [31:24] Reserved 8 24 rores [15:8] Reserved 8 8 rwres [7:0] Bit 2:0 - Software reset for hwass cba3to2 and m64top32 bridge instances in appss. (reset value - 0) Bit 5:3 - Software reset for fecss p2p async bridge instance in appss. (reset value - 0) 0x0 : Release the reset 0x7 : Assert the reset Bit 31:6 - Reserved 8 0 0 RESERVED1 0x68 32 RESERVED1 wphres [31:24] Reserved 8 24 rores [15:8] Reserved 8 8 rwres [7:0] Reserved 8 0 0 RESERVED2 0x6C 32 RESERVED2 wphres [31:24] Reserved 8 24 rores [15:8] Reserved 8 8 rwres [7:0] Reserved 8 0 0 RESERVED3 0x70 32 RESERVED3 wphres [31:24] Reserved 8 24 rores [15:8] Reserved 8 8 rwres [7:0] Reserved 8 0 0 IPCFGCLKGATE0 0x74 32 IPCFGCLKGATE0 app_i2c [29:27] 0x0 : Enable the Clock 0x7 : Gate the clock 3 27 app_dcc [26:24] 0x0 : Enable the Clock 0x7 : Gate the clock 3 24 app_wd [23:21] 0x0 : Enable the Clock 0x7 : Gate the clock 3 21 app_rti [20:18] 0x0 : Enable the Clock 0x7 : Gate the clock 3 18 app_esm [17:15] 0x0 : Enable the Clock 0x7 : Gate the clock 3 15 tpcc_a [14:12] 0x0 : Enable the Clock 0x7 : Gate the clock 3 12 tptc_a1 [11:9] 0x0 : Enable the Clock 0x7 : Gate the clock 3 9 tptc_a0 [8:6] 0x0 : Enable the Clock 0x7 : Gate the clock 3 6 app_qspi [5:3] 0x0 : Enable the Clock 0x7 : Gate the clock 3 3 xbara [2:0] Reserved Setting this bit does not cause any affect to any logic 3 0 0 IPCFGCLKGATE1 0x78 32 IPCFGCLKGATE1 res [29:27] 0x0 : Enable the Clock 0x7 : Gate the clock 3 27 app_ctrl [26:24] 0x0 : Enable the Clock 0x7 : Gate the clock 3 24 app_crc [23:21] 0x0 : Enable the Clock 0x7 : Gate the clock 3 21 app_pwm [20:18] 0x0 : Enable the Clock 0x7 : Gate the clock 3 18 app_lin [17:15] 0x0 : Enable the Clock 0x7 : Gate the clock 3 15 app_can [14:12] 0x0 : Enable the Clock 0x7 : Gate the clock 3 12 app_spi_1 [11:9] 0x0 : Enable the Clock 0x7 : Gate the clock 3 9 app_spi_0 [8:6] 0x0 : Enable the Clock 0x7 : Gate the clock 3 6 app_uart_1 [5:3] 0x0 : Enable the Clock 0x7 : Gate the clock 3 3 app_uart_0 [2:0] 0x0 : Enable the Clock 0x7 : Gate the clock 3 0 0 IPCFGCLKGATE2 0x7C 32 IPCFGCLKGATE2 pcr6 [14:12] 0x0 : Enable the Clock 0x7 : Gate the clock 3 12 pcr5 [11:9] 0x0 : Enable the Clock 0x7 : Gate the clock 3 9 hwass [8:6] 0x0 : Enable the Clock 0x7 : Gate the clock 3 6 rs232 [5:3] 0x0 : Enable the Clock 0x7 : Gate the clock 3 3 gio [2:0] 0x0 : Enable the Clock 0x7 : Gate the clock 3 0 0 BLOCKRESET0 0x80 32 BLOCKRESET0 app_i2c [29:27] 0x0 : Release the reset 0x7 : Assert the reset 3 27 app_dcc [26:24] 0x0 : Release the reset 0x7 : Assert the reset 3 24 app_wd [23:21] 0x0 : Release the reset 0x7 : Assert the reset 3 21 app_rti [20:18] 0x0 : Release the reset 0x7 : Assert the reset 3 18 app_esm [17:15] 0x0 : Release the reset 0x7 : Assert the reset 3 15 tpcc_a [14:12] 0x0 : Release the reset 0x7 : Assert the reset 3 12 tptc_a1 [11:9] 0x0 : Release the reset 0x7 : Assert the reset 3 9 tptc_a0 [8:6] 0x0 : Release the reset 0x7 : Assert the reset 3 6 app_qspi [5:3] 0x0 : Release the reset 0x7 : Assert the reset 3 3 hwass [2:0] 0x0 : Release the reset 0x7 : Assert the reset 3 0 0 BLOCKRESET1 0x84 32 BLOCKRESET1 topss [29:27] 0x0 : Release the reset 0x7 : Assert the reset 3 27 app_ctrl [26:24] 0x0 : Release the reset 0x7 : Assert the reset 3 24 app_crc [23:21] 0x0 : Release the reset 0x7 : Assert the reset 3 21 app_pwm [20:18] 0x0 : Release the reset 0x7 : Assert the reset 3 18 app_lin [17:15] 0x0 : Release the reset 0x7 : Assert the reset 3 15 app_can [14:12] 0x0 : Release the reset 0x7 : Assert the reset 3 12 app_spi_1 [11:9] 0x0 : Release the reset 0x7 : Assert the reset 3 9 app_spi_0 [8:6] 0x0 : Release the reset 0x7 : Assert the reset 3 6 app_uart_1 [5:3] 0x0 : Release the reset 0x7 : Assert the reset 3 3 app_uart_0 [2:0] 0x0 : Release the reset 0x7 : Assert the reset 3 0 0 BLOCKRESET2 0x88 32 BLOCKRESET2 frc [8:6] 0x0 : Release the reset 0x7 : Assert the reset 3 6 rs232 [5:3] 0x0 : Release the reset 0x7 : Assert the reset 3 3 reserved [2:0] Reserved 3 0 0 PLATFORM_SIGNATURE 0x8C 32 PLATFORM_SIGNATURE signature [31:0] Platform signature to identify the platform 32 0 0 POWERMODE 0x90 32 POWERMODE CM3_DEEPSLEEP_STATUS [3:3] CM3 Core Deep Sleep Status 1 3 CM3_SLEEP_STATUS [2:2] CM3 Core Sleep Status 1 2 DEEPSLEEP [1:1] 0x0 : CM4 CORE DEEP SLEEP 0x1 : DEVICE DEEP SLEEP 1 1 SLEEP [0:0] 0x0 : CM4 CORE SLEEP 0x1 : DEVICE SLEEP 1 0 0 RST_WFICHECK 0x94 32 RST_WFICHECK cpu [2:0] Writing '000' will disable check for WFI before local reset assertion of app cpu 3 0 0 RST_ASSERTDLY 0x98 32 RST_ASSERTDLY common [7:0] Value decides number of cycles reset should be asserted for cpu 8 0 0 RST2ASSERTDLY 0x9C 32 RST2ASSERTDLY cpu [15:8] Value decides number of cycles to be held before asserting reset for app cpu 8 8 0 RST_FSM_TRIG 0xA0 32 RST_FSM_TRIG cpu [2:0] FSM Reset Trigger 3 0 0 RST_CAUSE 0xA4 32 RST_CAUSE common [7:0] Reset cause register for APP CPU 0x00 - All cleared 0x01 - Power On Reset (PoR) 0x02 - Subsystem Reset (Combination of Warm Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_APP_PD_SOFT_RESET and PoR reset) 0x04 - STC RESET 0x08 - Reserved 0x10 - CPU Only Reset triggered by writing to LPRADAR:APP_RCM:RST_FSM_TRIG<RST_FSM_TRIG_CPU> (self triggered CPU reset during MEMSWAP/ECLIPSE mode to wait for WFI to assert the reset to CPU) 0x20 - Core Reset initiated from PRCM using LPRADAR:TOP_PRCM:RST_SOFT_APP_CORE_SYSRESET_REQ (reset CPU unconditionally - by debugger) or LPRADAR:TOP_PRCM:APP_CORE_SYSRESET_PARAM_WAKEUP_OUT_STATE 0x40 - Reserved 8 0 0 RST_CAUSE_CLR 0xA8 32 RST_CAUSE_CLR cpu [2:0] Writing '111' will clear the RST_CAUSE register 3 0 0 XTALCLK_CLK_GATE 0xAC 32 XTALCLK_CLK_GATE XTALCLK_CLK_GATE [2:0] RESERVED 3 0 0 XTALCLKX2_CLK_GATE 0xB0 32 XTALCLKX2_CLK_GATE XTALCLKX2_CLK_GATE [2:0] Writing 3'b111 will gate the XTALX2 clock.Writing 3'b000 will ungate the clock. 3 0 0 APLLDIV2_CLK_GATE 0xB4 32 APLLDIV2_CLK_GATE APLLDIV2_CLK_GATE [2:0] Writing 3'b111 will gate the APLL/2clock to EDCC.Writing 3'b000 will ungate the clock. 3 0 0 DFT_APPSS_LSTC_CLK_GATE 0xB8 32 DFT_APPSS_LSTC_CLK_GATE DFT_APPSS_LSTC_CLK_GATE [2:0] Writing 3'b111 will gate the clock to LSTC.Writing 3'b000 will ungate the clock. 3 0 0 DFT_APPSS_LSTC_VBUSP_CLK_GATE 0xBC 32 DFT_APPSS_LSTC_VBUSP_CLK_GATE enable [2:0] 3'b000 : Gate clock to LSTC VBUSP 3'b111 : Ungate Clock to LSTC VBUSP 3 0 0 APP_ROM_CLOCK_GATE 0xC0 32 APP_ROM_CLOCK_GATE enable [2:0] 3'b000 : Ungate clock to APP ROM 3'b111 : Gate Clock to APP ROM 3 0 0 APP_RAM1_CLOCK_GATE 0xC4 32 APP_RAM1_CLOCK_GATE enable [2:0] 3'b000 : Ungate clock to APP RAM1 3'b111 : Gate Clock to APP_RAM1 3 0 0 APP_RAM2_CLOCK_GATE 0xC8 32 APP_RAM2_CLOCK_GATE enable [2:0] 3'b000 : Ungate clock to APP RAM2 3'b111 : Gate Clock to APP RAM2 3 0 0 APP_RAM3_CLOCK_GATE 0xCC 32 APP_RAM3_CLOCK_GATE enable [2:0] 3'b000 : Ungate clock to APP RAM3 3'b111 : Gate Clock to APP RAM3 3 0 0 CFG_XBARA_DYNAMIC_CG 0xD0 32 CFG_XBARA_DYNAMIC_CG enable [2:0] Enable APPSS crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. When the feature is enabed, the CM4 should monitor for any possible pending transactions from various masters like DMA/NWA and if no transaction is expected to be iniated by the masters, the CM4 executes WFI. On ssertion of WFI signal, the clock to crossbar is gated. The clock is automatically ungated under two conditions (i) when the WFI signal is deasserted by any interrupted (ii) when any of the APPSS TPCC triggers are asserted. Instead of WFI, cfg_xbara_set_dynamic_cg also can be used to start the clock gating. 0 - Dynamic clock gating feature is disabled. The clock to APPSS crossbar is not gated dynamically. The clock to APPSS crossbar is gated/ungated as per device ice level power states. 3 0 0 CFG_TPTC1_DYNAMIC_CG 0xD4 32 CFG_TPTC1_DYNAMIC_CG enable [2:0] Enable APPSS TPTC1 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc1_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC1 crossbar is not gated dynamically. The clock to APPSS TPTC1 crossbar is gated/ungated as per device ice level power states. 3 0 0 CFG_TPTC2_DYNAMIC_CG 0xD8 32 CFG_TPTC2_DYNAMIC_CG enable [2:0] Enable APPSS TPTC2 crossbar dynamic clock gating. 1 - Dynamic clock gating feature is enabled. Same behaviour as cfg_xbara_dynamic_cg_en - for both entry to clock gating and exit from clock gating. WFI or cfg_tptc2_set_dynamic_cg 0 - Dynamic clock gating feature is disabled. The clock to APPSS TPTC2 crossbar is not gated dynamically. The clock to APPSS TPTC2 crossbar is gated/ungated as per device ice level power states 3 0 0 CFG_XBARA_SET_DYNAMIC_CG 0xDC 32 CFG_XBARA_SET_DYNAMIC_CG set [0:0] Start APPSS crossbar dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock. 1 0 0 CFG_TPTC1_SET_DYNAMIC_CG 0xE0 32 CFG_TPTC1_SET_DYNAMIC_CG set [0:0] Start APPSS tptc1 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock. 1 0 0 CFG_TPTC2_SET_DYNAMIC_CG 0xE4 32 CFG_TPTC2_SET_DYNAMIC_CG set [0:0] Start APPSS tptc2 dynamic clock gating. This is used instead of WFI. 1 - Start the clock gating. In order to start again, write 0 followed by 1. Rise edge is detected internally, to start the clock gating. 0 - Clock is ungated. Fall edge is detected internally to ungate the clock. 1 0 0 CM4_FORCE_HCLK_GATE 0xE8 32 CM4_FORCE_HCLK_GATE enable [2:0] 3'b000 - CM4 HCLK is ungated 3'b111 - CM4 HCLK is gated 3 0 0 LIN_SCI_DIV 0xEC 32 LIN_SCI_DIV val [7:0] ICG Based Divider for LIN 8 0 0 APP_LSTC_EN 0xF0 32 APP_LSTC_EN enable [0:0] Enable vbusp_req and clk_en for app lstc 1 0 0 LOCK0_KICK0 0x1008 32 - KICK0 component [31:0] - KICK0 component 32 0 0 LOCK0_KICK1 0x100C 32 - KICK1 component [31:0] - KICK1 component 32 0 0 intr_raw_status 0x1010 32 Interrupt Raw Status/Set Register [3:3] Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 0 0 intr_enabled_status_clear 0x1014 32 Interrupt Enabled Status/Clear register [3:3] Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 0 0 intr_enable 0x1018 32 Interrupt Enable register [3:3] Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 0 0 intr_enable_clear 0x101C 32 Interrupt Enable Clear register [3:3] Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 0 0 eoi 0x1020 32 EOI register [7:0] EOI vector value. Write this with interrupt distribution value in the chip. 8 0 0 fault_address 0x1024 32 Fault Address register [31:0] Fault Address. 32 0 0 fault_type_status 0x1028 32 Fault Type Status register [6:6] Non-secure access. 1 6 [5:0] Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault 6 0 0 fault_attr_status 0x102C 32 Fault Attribute Status register [31:20] XID. 12 20 [19:8] Route ID. 12 8 [7:0] Privilege ID. 8 0 0 fault_clear 0x1030 32 Fault Clear register [0:0] Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect. 1 0 0 APP_CTRL 0x56060000 0 4148 registers PID 0x0 32 PID register 16 16 5 11 3 8 2 6 6 0 0 HW_REG0 0x4 32 HW_REG0 hwreg0 [31:0] HW reserved Regsiter 32 0 0 HW_REG1 0x8 32 HW_REG1 hwreg1 [31:0] HW reserved Regsiter 32 0 0 PREVIOUS_NAME 0xC 32 PREVIOUS_NAME hwreg2 [31:0] HW reserved Regsiter 32 0 0 HW_REG3 0x10 32 HW_REG3 hwreg3 [31:0] HW reserved Regsiter 32 0 0 HW_REG4 0x14 32 HW_REG4 hwreg4 [31:0] HW reserved Regsiter 32 0 0 HW_REG5 0x18 32 HW_REG5 hwreg5 [31:0] HW reserved Regsiter 32 0 0 HW_REG6 0x1C 32 HW_REG6 hwreg6 [31:0] HW reserved Regsiter 32 0 0 HW_REG7 0x20 32 HW_REG7 hwreg7 [31:0] HW reserved Regsiter 32 0 0 APPSS_SW_INT 0x24 32 APPSS_SW_INT pulse [3:0] Write_pulse bit field: writing 1'b1 to each bit will trigger SW_INT<0-3> respectively to CM4. 4 0 0 APPSS_IPC_RFS 0x28 32 APPSS_IPC_RFS command [31:4] Used by software to communicate commands and response. It is 7-bits per interrupt. 28 4 host_intr [3:0] Write_pulse bit field: Writing 1'b1 to each bit will trigger HOST_INTR <0-3> respectively to CM3. 4 0 0 APPSS_CAPEVNT_SEL 0x2C 32 APPSS_CAPEVNT_SEL src1 [23:12] 5:0 : Selects the interrupt to route to RTI Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 11:6: Selects the interrupt to route to WDT Capture event 1 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 1 12 12 src0 [11:0] 5:0 : Selects the interrupt to route to RTI Capture event 0 6'd0 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd1 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd2 : FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : LIN_INT1 6'd5 : LIN_INT0 6'd6 : MCAN_FE_INT7 6'd7 : MCAN_FE_INT1 6'd8 : MCAN_FE_INT2 6'd9 : MCAN_FE_INT3 6'd10 : MCAN_FE_INT4 6'd11 : MCAN_FE_INT5 6'd12 : MCAN_FE_INT6 6'd13 : MCAN_INT0 6'd14 : MCAN_INT1 6'd15 : SYNC_IN 11:6: Selects the interrupt to route to WDT Capture event 0 6'd0 : MUXED_FECSS_CHIRPTIMER_CHIRP_START_AND_CHIRP_END 6'd1 : MUXED_FECSS_CHIRPTIMER_BURST_START_AND_BURST_END 6'd2 : FECSS_CHIRPTIMER_FRAME_END 6'd3 : FECSS_FRAMETIMER_FRAME_START 6'd4 : MUXED_FECSS_CHIRP_AVAIL_IRQ_AND_ADC_VALID_START_AND_SYNC_IN 6'd5 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 6'd6 : FECSS_FRAME_START_OFFSET_INTR_TIME2 6'd7 : FECSS_FRAME_START_OFFSET_INTR_TIME3 6'd8 : FECSS_BURST_START_OFFSET_TIME 6'd9 : FECSS_IPC_RFS_FEC_INTR 0 12 0 0 APPSS_DMA_REQ_SEL 0x30 32 APPSS_DMA_REQ_SEL select [31:0] Reserved for R&D. Do not touch 32 0 0 APPSS_DMA1_REQ_SEL 0x34 32 APPSS_DMA1_REQ_SEL select [31:0] Reserved for R&D. Do not touch 32 0 0 APPSS_IRQ_REQ_SEL 0x38 32 APPSS_IRQ_REQ_SEL select [31:0] Configuration register APPSS_IRQ_REQ_SEL is used to select the interrupt for CM4. Below are the bit definitions 0 : 0x0 = Map 0th IRQ from compare block of RTI (RTI1) to IRQ43 : 0x1 = Map 0th IRQ from compare block of WDT (RTI2) to IRQ43 1 : 0x0 = Map 1st IRQ from compare block of RTI (RTI1) to IRQ44 : 0x1 = Map 1st IRQ from compare block of WDT (RTI2) to IRQ44 2 : 0x0 = Map 2nd IRQ from compare block of RTI (RTI1) to IRQ45 : 0x1 = Map 2nd IRQ from compare block of WDT (RTI2) to IRQ45 3 : 0x0 = Map 3rd IRQ from compare block of RTI (RTI1) to IRQ46 : 0x1 = Map 3rd IRQ from compare block of WDT (RTI2) to IRQ46 5:4 : 0x00 = Selects time base IRQ from RTI (RTI1) to IRQ47 : 0x01 = Selects time base IRQ from WDT (RTI2) to IRQ47 : 0x10 = Selects gpadc_ifm_done to IRQ47 : 0x11 = Reserved 7:6 : 0x00 = Selects capture event 0 of RTI to IRQ48 and Selects capture event 1 of IRQ from RTI to IRQ49 : 0x01 = Selects capture event 0 of WDT to IRQ48 and Selects capture event 1 of IRQ from WDT to IRQ49 : 0x10 = Selects PWM Interrupt 0 to IRQ48 and PWM Interrupt 1 to IRQ49 : 0x11 = Selects OVL_REQ of RTI (RTI1) to IRQ48 and OVL_REQ of WDT to IRQ49 8 : 0x0 = mcan_fe_int7 connected to IRQ29 : 0x1 = debugss txdata_available interrupt connected to IRQ29. 9 : 0x0 = Used for TPPCA trigger. Dma read interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 62 : 0x1 = Used for TPPCA trigger. dma read interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 62 10 : 0x0 = Used for TPPCA trigger. dma write interrupt of SPI1/A channel routed to TPCCA (DMA) trigger 63 : 0x1 = Used for TPPCA trigger. dma write interrupt of SPI2/B channel routed to TPCCA (DMA) trigger 63 11 : 0x0 = Timing Engine Chirptimer_chirp_start to IRQ30 : 0x1 = Timing Engine Chirptimer_chirp_end to IRQ30 12 : 0x0 = Timing Engine Chirptimer_burst_start to IRQ31 : 0x1 = Timing Engine Chirptimer_burst_end to IRQ31 14:13: 0x00 = chirp_avail_irq to IRQ34 : 0x01 = adc_valid_start to IRQ34 : 0x10 = SYNC_in to IRQ34 15 : Reserved 16 : 0x0 = mcan_fe_int6 connected to IRQ28 : 0x1 = spi2_int_req connected to IRQ28 18:17: 0x00 = DCC_DONE Interrupt connected to IRQ12 : 0x01 = CM4 LBIST Interrupt connected to IRQ12 : 0x10 = CM3 LBIST Interrupt connected to IRQ12 : 0x11 = TOP PBIST Interrupt connected to IRQ12 20:19: 0x00 = I2C_INT Interrupt connected to IRQ19 : 0x01 = CM4 LBIST Interrupt connected to IRQ19 : 0x10 = CM3 LBIST Interrupt connected to IRQ19 : 0x11 = TOP PBIST Interrupt connected to IRQ19 21 : 0x0 = APPSS_TPCC1_ERRAGG connected to IRQ16 : 0x1 = CTI_TRIGOUT2 connected to IRQ16 22 : 0x0 = APPSS_TPCC2_ERRAGG connected to IRQ18 : 0x1 = CTI_TRIGOUT3 connected to IRQ18 32 0 0 APPSS_SPI_TRIG_SRC 0x3C 32 APPSS_SPI_TRIG_SRC trig_spib [26:16] RESERVED 11 16 trig_spia [1:0] RESERVED 2 0 0 APPSS_RAM1A_MEM_INIT 0x40 32 APPSS_RAM1A_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM1 partion0 bank. Value in each row is initialized to 0x0C_0000_0000 1 0 0 APPSS_RAM1A_MEM_INIT_DONE 0x44 32 APPSS_RAM1A_MEM_INIT_DONE mem_init_done [0:0] This field will be high once initialization of APPSS_RAM1 partion0 banks is finished. Writing '1' would clear the bit. 1 0 0 APPSS_RAM1A_MEM_INIT_STATUS 0x48 32 APPSS_RAM1A_MEM_INIT_STATUS mem_status [0:0] 1'b0: No initialization is happening for APPSS_RAM1 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM1 partion0 bank 1 0 0 APPSS_RAM2A_MEM_INIT 0x4C 32 APPSS_RAM2A_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM2 partion0 bank. Value in each row is initialized to 0x0C_0000_0000 1 0 0 APPSS_RAM2A_MEM_INIT_DONE 0x50 32 APPSS_RAM2A_MEM_INIT_DONE mem_init_done [0:0] This field will be high once initialization of APPSS_RAM2 partion0 banks is finished. Writing '1' would clear the bit. 1 0 0 APPSS_RAM2A_MEM_INIT_STATUS 0x54 32 APPSS_RAM2A_MEM_INIT_STATUS mem_status [0:0] 1'b0: No initialization is happening for APPSS_RAM2 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM2 partion0 bank 1 0 0 APPSS_RAM3A_MEM_INIT 0x58 32 APPSS_RAM3A_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initialization of APPSS_RAM3 partion0 bank. Value in each row is initialized to 0x0C_0000_0000 1 0 0 APPSS_RAM3A_MEM_INIT_DONE 0x5C 32 APPSS_RAM3A_MEM_INIT_DONE mem_init_done [0:0] This field will be high once initialization of APPSS_RAM3 partion0 banks is finished. Writing '1' would clear the bit. 1 0 0 APPSS_RAM3A_MEM_INIT_STATUS 0x60 32 APPSS_RAM3A_MEM_INIT_STATUS mem_status [0:0] 1'b0: No initialization is happening for APPSS_RAM3 partion0 bank 1'b1: Initialization is in progress for APPSS_RAM3 partion0 bank 1 0 0 HWASS_SHRD_RAM0_MEM_INIT 0x64 32 HWASS_SHRD_RAM0_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition0. Value in each row is initialized to 0x0 1 0 0 HWASS_SHRD_RAM0_MEM_INIT_DONE 0x68 32 HWASS_SHRD_RAM0_MEM_INIT_DONE mem_init_done [0:0] This field will be high once intialization of HWASS Shared RAM parition0 is finished. Writing '1' would clear the bit 1 0 0 HWASS_SHRD_RAM0_MEM_INIT_STATUS 0x6C 32 HWASS_SHRD_RAM0_MEM_INIT_STATUS mem_status [0:0] 1'b0: No initialization is happening for HWASS Shared RAM parition0 1'b1: Initialization is in progress for HWASS Shared RAM parition0 1 0 0 HWASS_SHRD_RAM1_MEM_INIT 0x70 32 HWASS_SHRD_RAM1_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initializing the HWASS Shared RAM parition1. Value in each row is initialized to 0x0 1 0 0 HWASS_SHRD_RAM1_MEM_INIT_DONE 0x74 32 HWASS_SHRD_RAM1_MEM_INIT_DONE mem_init_done [0:0] This field will be high once intialization of HWASS Shared RAM parition1 is finished. Writing '1' would clear the bit 1 0 0 HWASS_SHRD_RAM1_MEM_INIT_STATUS 0x78 32 HWASS_SHRD_RAM1_MEM_INIT_STATUS mem_status [0:0] 1'b0: No initialization is happening for HWASS Shared RAM parition1 1'b1: Initialization is in progress for HWASS Shared RAM parition1 1 0 0 APPSS_TPCC_MEMINIT_START 0x7C 32 APPSS_TPCC_MEMINIT_START tpcc_b_meminit_start [16:16] Write_pulse bit field: Writing 1'b1 will start initializing the TPCCB 1 16 tpcc_a_meminit_start [0:0] Write_pulse bit field: Writing 1'b1 will start initializing the TPCCA 1 0 0 APPSS_TPCC_MEMINIT_DONE 0x80 32 APPSS_TPCC_MEMINIT_DONE tpcc_b_meminit_done [16:16] This field will be high once intialization of TPCCB is finished. Writing '1' would clear the bit 1 16 tpcc_a_meminit_done [0:0] This field will be high once intialization of TPCCA is finished. Writing '1' would clear the bit 1 0 0 APPSS_TPCC_MEMINIT_STATUS 0x84 32 APPSS_TPCC_MEMINIT_STATUS tpcc_b_meminit_status [16:16] 1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB 1 16 tpcc_a_meminit_status [0:0] 1'b0: No initialization is happening for TPCCA 1'b1: Initialization is in progress for TPCCB 1 0 0 APPSS_SPIA_CFG 0x88 32 APPSS_SPIA_CFG spia_iodft_en [28:28] 1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode 1 28 spia_int_trig_polarity [24:24] SPIA trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1 1 24 spia_trig_gate_en [16:16] When set the TRIGGER s are un-gated only when chip-select is active 1 16 spia_cs_trigsrc_en [8:8] MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source 1 8 spiasync2sen [0:0] Donot touch the field. Used as Tie-off for IP-config. 1 0 0 APPSS_SPIB_CFG 0x8C 32 APPSS_SPIB_CFG spib_iodft_en [28:28] 1: Enable loop back of MOSI to MISO - Master mode Enable loop back of MISO to MOSI - Slave mode 1 28 spib_int_trig_polarity [24:24] SPIB trigger source polarity select. 0 - Polarity 0, 1 -Polarity 1 1 24 spib_trig_gate_en [16:16] When set the TRIGGER s are un-gated only when chip-select is active 1 16 spib_cs_trigsrc_en [8:8] MIBSPIB CS Trigger SRC enable 1 : Use CS as trigger source 1 8 spibsync2sen [0:0] Donot touch the field. Used as Tie-off for IP-config. 1 0 0 APPSS_EPWM_CFG 0x90 32 APPSS_EPWM_CFG epwm_config [31:0] bit0: SW syncin for EPWM1 bit1: SW syncin for EPWM2 bit2: SW syncin for EPWM3 bit8:9 : select bits for EPWM1 '0' : external syncin '1' : reserved '2' : sw syncin '3' : reserved bit10:11 : select bits for EPWM2 '0' : external syncin '1' : chained from EPWM1 '2' : sw syncin '3' : reserved bit12:13 : select bits for EPWM3 '0' : external syncin '1' : chained from EPWM2 '2' : sw syncin '3' : reserved bit24:TBCLKEN for EPWM1 bit25:TBCLKEN for EPWM2 bit26:TBCLKEN for EPWM3 32 0 0 RESERVED 0x94 32 RESERVED gio_config [31:0] bit0 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT0 to IRQ bit1 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT1to IRQ bit2: writing '1' will slect negedge for pulse generation of GIO_PAD_INT2 to IRQ bit3 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT3 to IRQ bit4 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT4 to IRQ bit5 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT5 to IRQ bit6 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT6 to IRQ bit7 : writing '1' will slect negedge for pulse generation of GIO_PAD_INT7 to IRQ 32 0 0 APPSS_MCAN_FE_AND_LIN_INTR_SEL 0x98 32 APPSS_MCAN_FE_AND_LIN_INTR_SEL lin_intr_sel [3:3] Writing a value would select the LIN interrupt in combination with HW_SYNC_IN and CAN filter events for Frame timer 0 : 0th interrupt bit is selected 1 : 1st interrupt bit is selected 1 3 mcan_fe_sel [2:0] Writing a value 'N' would select Nth filter interrupt combination with SYNC_IN(IO) for triggering timing engine Example: writing 3'd<1-7> selects MCAN_FE_INT<1-7> respectively 3 0 0 APPSS_MCANA_INT_CLR 0x9C 32 APPSS_MCANA_INT_CLR mcan_int_clr [31:0] Interrupt Clear for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit<0-31> clears interrupt source <0-31> respectively in MCANA 32 0 0 APPSS_MCANA_INT_MASK 0xA0 32 APPSS_MCANA_INT_MASK mcan_int_mask [31:0] Interrupt Mask for 32 MCANSS TX DMA interrupts. Writing 1'b1 to bit<0-31> masks interrupt source <0-31> respectively in MCANA 32 0 0 APPSS_MCANA_INT_STAT 0xA4 32 APPSS_MCANA_INT_STAT mcan_int_status [31:0] Interrupt status for 32 MCANSS TX DMA interrupts. 1'b1 in bit<0-31> gives pending status for interrupt <0-31> respectively in MCANA 32 0 0 APPSS_CM4_GLOBAL_CONFIG 0xA8 32 APPSS_CM4_GLOBAL_CONFIG teinit [0:0] Reserved 1 0 0 RESERVED1 0xAC 32 RESERVED1 res [31:0] reserved 32 0 0 APPSS_CM4_ROM_ECLIPSE 0xB0 32 APPSS_CM4_ROM_ECLIPSE memswap_wait [10:8] writing 3'b111 ensures ROM-Eclipsing happens only after CPU sys reset. Orelse it will be a immediate change. 3 8 memswap [2:0] writing '111' ensures eclipsing of CPU_ROM immediately if memswap_wait is not set. If memswap_wait is set then ROM is eclipsed after CPU sys reset assertion. 3 0 0 APPSS_CM4_STATUS_REG 0xB4 32 APPSS_CM4_STATUS_REG memswap [0:0] reading 1: confirms ROM is Eclipsed from with RAM for the CPU. 1 0 0 APPSS_AHB_CTRL 0xB8 32 APPSS_AHB_CTRL cpu0_ahb_init [0:0] Ti internal Register. Modifying this register is not recommended Signal decides whehter ahb interface is enabled or not. 1 0 0 ESM_GATING0 0xBC 32 ESM_GATING0 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_7 32 0 0 ESM_GATING1 0xC0 32 ESM_GATING1 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_15 32 0 0 ESM_GATING2 0xC4 32 ESM_GATING2 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_23 32 0 0 ESM_GATING3 0xC8 32 ESM_GATING3 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP2_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP2_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP2_ERROR_31 32 0 0 ESM_GATING4 0xCC 32 ESM_GATING4 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_0 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_1 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_7 32 0 0 ESM_GATING5 0xD0 32 ESM_GATING5 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_8 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_9 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_15 32 0 0 ESM_GATING6 0xD4 32 ESM_GATING6 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_16 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_17 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_23 32 0 0 ESM_GATING7 0xD8 32 ESM_GATING7 esm_gating [31:0] bit3:0 : writing '000' will ungate the ESM_GRP3_ERROR_24 bit7:4 : writing '000' will ungate the ESM_GRP3_ERROR_25 bit31:28 : writing '000' will ungate the ESM_GRP3_ERROR_31 32 0 0 APPSS_CM4_HALT 0xDC 32 APPSS_CM4_HALT halt [2:0] RESERVED 3 0 0 APPSS_CM4_EVENT 0xE0 32 APPSS_CM4_EVENT cpu0_event [2:0] Reserved Register for R & D 3 0 0 SPIA_IO_CFG 0xE4 32 SPIA_IO_CFG miso_oen_by_cs [16:16] RESERVED 1 16 cs_pol [8:8] RESERVED 1 8 cs_deact [0:0] RESERVED 1 0 0 SPIB_IO_CFG 0xE8 32 SPIB_IO_CFG miso_oen_by_cs [16:16] RESERVED 1 16 cs_pol [8:8] RESERVED 1 8 cs_deact [0:0] RESERVED 1 0 0 SPI_HOST_IRQ 0xEC 32 SPI_HOST_IRQ host_irq [0:0] RESERVED 1 0 0 TPTC_DBS_CONFIG 0xF0 32 TPTC_DBS_CONFIG tptc_b1 [13:12] Default burst size tieoff value for TPTC_B1 2 12 tptc_b0 [9:8] Default burst size tieoff value for TPTC_B0 2 8 tptc_a1 [5:4] Default burst size tieoff value for TPTC_A1 2 4 tptc_a0 [1:0] Default burst size tieoff value for TPTC_A0 2 0 0 TPCC_PARITY_CTRL 0xF4 32 TPCC_PARITY_CTRL tpcc_b_parity_err_clr [20:20] Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_b_parity_addr 1 20 tpcc_a_parity_err_clr [16:16] Write pulse bit field: parity clear bit. Writing 1'b1 will clear the tpcc_a_parity_addr 1 16 tpcc_b_parity_testen [12:12] parity test enable for tpcc b 1 12 tpcc_b_parity_en [8:8] parity en for tpcc b 1 8 tpcc_a_parity_testen [4:4] parity test enable for tpcc a 1 4 tpcc_a_parity_en [0:0] writing 1'b1 enables parity for TPCC_A 1 0 0 TPCC_PARITY_STATUS 0xF8 32 TPCC_PARITY_STATUS tpcc_b_parity_addr [23:16] address where parity error happened for tpccb 8 16 tpcc_a_parity_addr [7:0] address where parity error happened for tpcca 8 0 0 APPSS_DBG_ACK_CTL0 0xFC 32 APPSS_DBG_ACK_CTL0 lin [28:28] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 28 scib [24:24] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 24 scia [20:20] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 20 i2c [16:16] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 16 mcrc [12:12] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 12 wdt [8:8] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 8 rti [4:4] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 4 can [0:0] Enable Suspend control for the peripheral. 0 :Peripheral not suspended along with processor 1: Peripehal Suspended along with procesor 1 0 0 DEBUGSS_CSETB_FLUSH 0x100 32 DEBUGSS_CSETB_FLUSH CSETB_FULL [10:10] RESERVED 1 10 CSETB_ACQ_COMPLETE [9:9] RESERVED 1 9 CSETB_FLUSHINACK [8:8] RESERVED 1 8 CSETB_FLUSHIN [0:0] RESERVED 1 0 0 CPSW_CONTROL 0x104 32 CPSW_CONTROL rgmii1_id_mode [16:16] Reserved 1 16 rmii_ref_clk_oe_n [8:8] Reserved 1 8 port1_mode_sel [0:0] Reserved 1 0 0 APPSS_ERRAGG_MASK0 0x108 32 APPSS_ERRAGG_MASK0 app_ahb_slv_rd [25:25] Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 25 app_ahb_slv_wr [24:24] Mask Interrupt from AHB slaves to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 24 fec_erroragg [23:23] Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 23 app_shared_mem [22:22] Mask Interrupt from APP_SHARED_MEM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 22 app_ahb [21:21] Mask Interrupt from APP_AHB to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 21 app_mpu [20:20] Mask Interrupt from APP_MPU to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 20 top_efuse_ctrl_wr [19:19] Mask Interrupt from TOP_EFUSE_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 19 top_efuse_ctrl_rd [18:18] Mask Interrupt from FEC_ERRORAGG to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 18 top_prcm_wr [17:17] Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 17 top_prcm_rd [16:16] Mask Interrupt from TOP_PRCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 16 frame_timer_wr [15:15] Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 15 frame_timer_rd [14:14] Mask Interrupt from FRAME_TIMER to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 14 apll_ctrl_wr [13:13] Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 13 apll_ctrl_rd [12:12] Mask Interrupt from APLL_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 12 topss_ctrl_wr [11:11] Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 11 topss_ctrl_rd [10:10] Mask Interrupt from TOPSS_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 10 plldig_ctrl_wr [9:9] Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 9 plldig_ctrl_rd [8:8] Mask Interrupt from PLLDIG_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 8 adcbuff_ctrl_wr [7:7] Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 7 adcbuff_ctrl_rd [6:6] Mask Interrupt from ADCBUFF_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 6 app_idalloc_wr [5:5] Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 5 app_idalloc_rd [4:4] Mask Interrupt from APP_IDALLOC to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 4 app_ctrl_wr [3:3] Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 3 app_ctrl_rd [2:2] Mask Interrupt from APP_CTRL to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 2 app_rcm_wr [1:1] Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 1 app_rcm_rd [0:0] Mask Interrupt from APP_RCM to aggregated Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 0 0 APPSS_ERRAGG_STATUS0 0x10C 32 APPSS_ERRAGG_STATUS0 app_ahb_slv_rd [25:25] Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 25 app_ahb_slv_wr [24:24] Status of Interrupt from AHB_SLAVE Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 24 fec_erroragg [23:23] Status of Interrupt from FEC_ERRORAGG Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 23 app_shared_mem_err [22:22] Status of Interrupt from APP_SHARED_MEM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 22 app_ahb_wr [21:21] Status of Interrupt from APP_AHB Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 21 app_mpu_rd [20:20] Status of Interrupt from APP_MPU Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 20 top_efuse_ctrl_wr [19:19] Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 19 top_efuse_ctrl_rd [18:18] Status of Interrupt from TOP_EFUSE_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 18 top_prcm_wr [17:17] Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 17 top_prcm_rd [16:16] Status of Interrupt from TOP_PRCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 16 frame_timer_wr [15:15] Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 15 frame_timer_rd [14:14] Status of Interrupt from FRAME_TIMER Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 14 apll_ctrl_wr [13:13] Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 13 apll_ctrl_rd [12:12] Status of Interrupt from APLL_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 12 topss_ctrl_wr [11:11] Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 11 topss_ctrl_rd [10:10] Status of Interrupt from TOPSS_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 10 plldig_ctrl_wr [9:9] Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 9 plldig_ctrl_rd [8:8] Status of Interrupt from PLLDIG_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 8 adcbuff_ctrl_wr [7:7] Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 7 adcbuff_ctrl_rd [6:6] Status of Interrupt from ADCBUFF_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 6 app_idalloc_wr [5:5] Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 5 app_idalloc_rd [4:4] Status of Interrupt from APP_IDALLOC Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 4 app_ctrl_wr [3:3] Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 3 app_ctrl_rd [2:2] Status of Interrupt from APP_CTRL Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 2 app_rcm_wr [1:1] Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 1 app_rcm_rd [0:0] Status of Interrupt from APP_RCM Set only if Interupt is unmasked in APPSS_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt. 1 0 0 APPSS_TPCC_A_ERRAGG_MASK 0x190 32 APPSS_TPCC_A_ERRAGG_MASK tptc_a1_read_access_error [26:26] Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 26 tptc_a0_read_access_error [25:25] Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 25 tpcc_a_read_access_error [24:24] Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 24 tptc_a1_write_access_error [18:18] Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 18 tptc_a0_write_access_error [17:17] Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 17 tpcc_a_write_access_error [16:16] Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 16 tpcc_a_par_err [4:4] Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 4 tptc_a1_err [3:3] Mask Error from TPTC_A1 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 3 tptc_a0_err [2:2] Mask Error from TPTC_A0 to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 2 tpcc_a_mpint [1:1] Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 1 tpcc_a_errint [0:0] Mask Error from TPCC_A to aggregated Error TPCC_A_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 0 0 APPSS_TPCC_A_ERRAGG_STATUS 0x194 32 APPSS_TPCC_A_ERRAGG_STATUS tptc_a1_read_access_error [26:26] Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 26 tptc_a0_read_access_error [25:25] Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 25 tpcc_a_read_access_error [24:24] Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 24 tptc_a1_write_access_error [18:18] Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 18 tptc_a0_write_access_error [17:17] Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 17 tpcc_a_write_access_error [16:16] Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 16 tpcc_a_par_err [4:4] Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 4 tptc_a1_err [3:3] Status of Error from TPTC_A1. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 3 tptc_a0_err [2:2] Status of Error from TPTC_A0. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 2 tpcc_a_mpint [1:1] Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 1 tpcc_a_errint [0:0] Status of Error from TPCC_A. Set only if Interupt is unmasked in TPCC_A_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 0 0 APPSS_TPCC_A_ERRAGG_STATUS_RAW 0x198 32 APPSS_TPCC_A_ERRAGG_STATUS_RAW tptc_a1_read_access_error [26:26] Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 26 tptc_a0_read_access_error [25:25] Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 25 tpcc_a_read_access_error [24:24] Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 24 tptc_a1_write_access_error [18:18] Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 18 tptc_a0_write_access_error [17:17] Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 17 tpcc_a_write_access_error [16:16] Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 16 tpcc_a_par_err [4:4] Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 4 tptc_a1_err [3:3] Raw Status of Error from TPTC_A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 3 tptc_a0_err [2:2] Raw Status of Error from TPTC_A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 2 tpcc_a_mpint [1:1] Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 1 tpcc_a_errint [0:0] Raw Status of Error from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_ERRAGG_MASK 1 0 0 APPSS_TPCC_A_INTAGG_MASK 0x214 32 APPSS_TPCC_A_INTAGG_MASK tptc_a1 [17:17] Mask Interrupt from TPTC A1 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 17 tptc_a0 [16:16] Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 16 tpcc_a_int7 [8:8] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 8 tpcc_a_int6 [7:7] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 7 tpcc_a_int5 [6:6] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 6 tpcc_a_int4 [5:5] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 5 tpcc_a_int3 [4:4] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 4 tpcc_a_int2 [3:3] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 3 tpcc_a_int1 [2:2] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 2 tpcc_a_int0 [1:1] Mask Interrupt from TPCC A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 1 tpcc_a_intg [0:0] Mask Interrupt from TPCC_A to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 0 0 HW_SPARE_WPH 0x218 32 HW_SPARE_WPH tptc_a1 [17:17] Status of Interrupt from TPTC A1. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 17 tptc_a0 [16:16] Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 16 tpcc_a_int7 [8:8] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 8 tpcc_a_int6 [7:7] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 7 tpcc_a_int5 [6:6] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 6 tpcc_a_int4 [5:5] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 5 tpcc_a_int3 [4:4] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 4 tpcc_a_int2 [3:3] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 3 tpcc_a_int1 [2:2] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 2 tpcc_a_int0 [1:1] Status of Interrupt from TPCC A Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 1 tpcc_a_intg [0:0] Status of Interrupt from TPCC_A. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 0 0 APPSS_TPCC_A_INTAGG_STATUS_RAW 0x21C 32 APPSS_TPCC_A_INTAGG_STATUS_RAW tptc_a1 [17:17] Raw Status of Interrupt from TPTC A1. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK 1 17 tptc_a0 [16:16] Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK 1 16 tpcc_a_int7 [8:8] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 8 tpcc_a_int6 [7:7] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 7 tpcc_a_int5 [6:6] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 6 tpcc_a_int4 [5:5] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 5 tpcc_a_int3 [4:4] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 4 tpcc_a_int2 [3:3] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 3 tpcc_a_int1 [2:2] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 2 tpcc_a_int0 [1:1] Raw Status of Interrupt from TPCC A. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK 1 1 tpcc_a_intg [0:0] Raw Status of Interrupt from TPCC_A. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 0 0 APPSS_TPCC_B_ERRAGG_MASK 0x274 32 APPSS_TPCC_B_ERRAGG_MASK tptc_b1_read_access_error [26:26] Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 26 tptc_b0_read_access_error [25:25] Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 25 tpcc_b_read_access_error [24:24] Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 24 tptc_b0_write_access_error [17:17] Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 17 tpcc_b_write_access_error [16:16] Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 16 tptc_b1_write_access_error [14:14] Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 14 tpcc_b_par_err [4:4] Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 4 tptc_b1_err [3:3] Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 3 tptc_b0_err [2:2] Mask Error from TPTC_B0 to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 2 tpcc_b_mpint [1:1] Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 1 tpcc_b_errint [0:0] Mask Error from TPCC_B to aggregated Error TPCC_B_ERRAGG 1 : Error is Masked 0 : Error is Unmasked 1 0 0 APPSS_TPCC_B_ERRAGG_STATUS 0x278 32 APPSS_TPCC_B_ERRAGG_STATUS tptc_b1_read_access_error [26:26] Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 26 tptc_b0_read_access_error [25:25] Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 25 tpcc_b_read_access_error [24:24] Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 24 tptc_b0_write_access_error [17:17] Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 17 tpcc_b_write_access_error [16:16] Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 16 tptc_b1_write_access_error [14:14] Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 14 tpcc_b_par_err [4:4] Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 4 tptc_b1_err [3:3] Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 3 tptc_b0_err [2:2] Status of Error from TPTC_B0. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 2 tpcc_b_mpint [1:1] Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 1 tpcc_b_errint [0:0] Status of Error from TPCC_B. Set only if Interupt is unmasked in TPCC_B_ERRAGG_MASK Wrie 0x1 to clear this Error. 1 0 0 APPSS_TPCC_B_ERRAGG_STATUS_RAW 0x27C 32 APPSS_TPCC_B_ERRAGG_STATUS_RAW tptc_b1_read_access_error [26:26] Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 26 tptc_b0_read_access_error [25:25] Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 25 tpcc_b_read_access_error [24:24] Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 24 tptc_b0_write_access_error [17:17] Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 17 tpcc_b_write_access_error [16:16] Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 16 tptc_b1_write_access_error [14:14] Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 14 tpcc_b_par_err [4:4] Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 4 tptc_b1_err [3:3] Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 3 tptc_b0_err [2:2] Raw Status of Error from TPTC_B0. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 2 tpcc_b_mpint [1:1] Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 1 tpcc_b_errint [0:0] Raw Status of Error from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_B_ERRAGG_MASK 1 0 0 APPSS_TPCC_B_INTAGG_MASK 0x2EC 32 APPSS_TPCC_B_INTAGG_MASK tptc_b1 [17:17] Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 17 tptc_b0 [16:16] Mask Interrupt from TPTC A0 to aggregated Interrupt TPCC_A_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 16 tpcc_b_int7 [8:8] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 8 tpcc_b_int6 [7:7] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 7 tpcc_b_int5 [6:6] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 6 tpcc_b_int4 [5:5] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 5 tpcc_b_int3 [4:4] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 4 tpcc_b_int2 [3:3] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 3 tpcc_b_int1 [2:2] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 2 tpcc_b_int0 [1:1] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 1 tpcc_b_intg [0:0] Mask Interrupt from TPCC_B to aggregated Interrupt TPCC_B_INTAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 0 0 APPSS_TPCC_B_INTAGG_STATUS 0x2F0 32 APPSS_TPCC_B_INTAGG_STATUS tptc_b1 [17:17] Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 17 tptc_b0 [16:16] Status of Interrupt from TPTC A0. Set only if Interupt is unmasked in TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 16 tpcc_b_int7 [8:8] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 8 tpcc_b_int6 [7:7] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 7 tpcc_b_int5 [6:6] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 6 tpcc_b_int4 [5:5] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 5 tpcc_b_int3 [4:4] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 4 tpcc_b_int2 [3:3] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 3 tpcc_b_int1 [2:2] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 2 tpcc_b_int0 [1:1] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 1 tpcc_b_intg [0:0] Status of Interrupt from TPCC_B. Set only if Interupt is unmasked in TPCC_B_INTAGG_MASK Wrie 0x1 to clear this interrupt. 1 0 0 APPSS_TPCC_B_INTAGG_STATUS_RAW 0x2F4 32 APPSS_TPCC_B_INTAGG_STATUS_RAW tptc_b1 [17:17] Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK 1 17 tptc_b0 [16:16] Raw Status of Interrupt from TPTC A0. Set irrespective if the Interupt is masked or unmasked in TPCC_A_INTAGG_MASK 1 16 tpcc_b_int7 [8:8] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 8 tpcc_b_int6 [7:7] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 7 tpcc_b_int5 [6:6] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 6 tpcc_b_int4 [5:5] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 5 tpcc_b_int3 [4:4] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 4 tpcc_b_int2 [3:3] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 3 tpcc_b_int1 [2:2] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 2 tpcc_b_int0 [1:1] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 1 tpcc_b_intg [0:0] Raw Status of Interrupt from TPCC_B. Set irrespective if the Interupt is masked or unmasked in TPCC_C_INTAGG_MASK 1 0 0 APPSS_MPU_ERRAGG_MASK 0x2F8 32 APPSS_MPU_ERRAGG_MASK fecss_mpu [16:16] Mask Interrupt from FECSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 16 appss_mpu [0:0] Mask Interrupt from APSS MPU to aggregated Interrupt MPU_PROT_AGG_ERR 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 0 0 APPSS_MPU_ERRAGG_STATUS 0x2FC 32 APPSS_MPU_ERRAGG_STATUS fecss_mpu [16:16] Status of Interrupt from FECSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt. 1 16 appss_mpu [0:0] Status of Interrupt from APSS MPU. Set only if Interupt is unmasked in APPSS_MPU_ERRAGG_MASK Wrie 0x1 to clear this interrupt. 1 0 0 APPSS_MPU_ERRAGG_STATUS_RAW 0x300 32 APPSS_MPU_ERRAGG_STATUS_RAW fecss_mpu [16:16] Raw Status of FECSS MPU PROT ERR. Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK 1 16 appss_mpu [0:0] Raw Status of Interrupt from APSS MPU PROT ERR Set irrespective if the Interupt is masked or unmasked in APPSS_MPU_ERRAGG_MASK 1 0 0 APPSS_QSPI_CONFIG 0x304 32 APPSS_QSPI_CONFIG clk_loopback [8:8] Reserved 1 8 ext_clk [0:0] Reserved 1 0 0 APPSS_CTI_TRIG_SEL 0x308 32 APPSS_CTI_TRIG_SEL trig8_sel [7:0] Used for selecting the trigger source for 8th trigger of CTI 8 0 0 APPSS_DBGSS_CTI_TRIG_SEL 0x30C 32 APPSS_DBGSS_CTI_TRIG_SEL trig3 [23:16] Reserved 8 16 trig2 [15:8] Reserved 8 8 trig1 [7:0] Reserved 8 0 0 APPSS_BOOT_INFO_REG0 0x310 32 APPSS_BOOT_INFO_REG0 config [31:0] Reserved Register for Software use 32 0 0 APPSS_BOOT_INFO_REG1 0x314 32 APPSS_BOOT_INFO_REG1 config [31:0] Reserved Register for Software use 32 0 0 APPSS_BOOT_INFO_REG2 0x318 32 APPSS_BOOT_INFO_REG2 config [31:0] Reserved Register for Software use 32 0 0 APPSS_BOOT_INFO_REG3 0x31C 32 APPSS_BOOT_INFO_REG3 config [31:0] Reserved Register for Software use 32 0 0 APPSS_BOOT_INFO_REG4 0x320 32 APPSS_BOOT_INFO_REG4 config [31:0] Reserved Register for Software use 32 0 0 APPSS_BOOT_INFO_REG5 0x324 32 APPSS_BOOT_INFO_REG5 config [31:0] Reserved Register for Software use 32 0 0 APPSS_BOOT_INFO_REG6 0x328 32 APPSS_BOOT_INFO_REG6 config [31:0] Reserved Register for Software use 32 0 0 APPSS_BOOT_INFO_REG7 0x32C 32 APPSS_BOOT_INFO_REG7 config [31:0] Reserved Register for Software use 32 0 0 APPSS_TPTC_ECCAGGR_CLK_CNTRL 0x330 32 APPSS_TPTC_ECCAGGR_CLK_CNTRL tptc_B0 [2:2] Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection) 1 2 tptc_A1 [1:1] Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection) 1 1 tptc_A0 [0:0] Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection) 1 0 0 APPSS_TPTC_BOUNDARY_CFG 0x334 32 APPSS_TPTC_BOUNDARY_CFG tptc_b1_size [29:24] 6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB 6 24 tptc_b0_size [21:16] 6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB 6 16 tptc_a1_size [13:8] 6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB 6 8 tptc_a0_size [5:0] 6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e. 512 KB 6 0 0 APPSS_TPTC_XID_REORDER_CFG 0x338 32 APPSS_TPTC_XID_REORDER_CFG tptc_b1_disable [24:24] writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B1 1 24 tptc_b0_disable [16:16] writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_B0 1 16 tptc_a1_disable [8:8] writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A1 1 8 tptc_a0_disable [0:0] writing 1'b1 will disable the CID-RID-SID reodering feature for TPTC_A0 1 0 0 HW_Sync_FE_CTRL 0x33C 32 HW_Sync_FE_CTRL fe2_sel [8:8] RESERVED 1 8 fe1_sel [0:0] RESERVED 1 0 0 HW_SPARE_REG1 0x340 32 HW_SPARE_REG1 NU [31:0] Resereved for R&D 32 0 0 HW_SPARE_REG2 0x344 32 HW_SPARE_REG2 NU [31:0] Resereved for R&D 32 0 0 HW_SPARE_REG3 0x348 32 HW_SPARE_REG3 NU [31:0] Resereved for R&D 32 0 0 NERROR_MASK 0x34C 32 NERROR_MASK mask [0:0] writing 1'b1 will mask the Nerror propagation to pad Writing 1'b0 will unmask the Nerror propagation to pad 1 0 0 HW_SPARE_RW0 0x350 32 HW_SPARE_RW0 hw_spare_rw0 [31:0] Bit 0: Writing 1'b1 will mask the hwa local ram agg serr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg serr propagation to ESM Bit 1 : Writing 1'b1 will mask the hwa local ram agg uerr propagation to ESM Writing 1'b0 will unmask the hwa local ram agg uerr propagation to ESM Bit 2 to 31 Reserved 32 0 0 HW_SPARE_RW1 0x354 32 HW_SPARE_RW1 hw_spare_rw1 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RW2 0x358 32 HW_SPARE_RW2 hw_spare_rw2 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RW3 0x35C 32 HW_SPARE_RW3 hw_spare_rw3 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RW4 0x360 32 HW_SPARE_RW4 hw_spare_rw4 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RW5 0x364 32 HW_SPARE_RW5 hw_spare_rw5 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RO0 0x368 32 HW_SPARE_RO0 hw_spare_ro0 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RO1 0x36C 32 HW_SPARE_RO1 hw_spare_ro1 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RO2 0x370 32 HW_SPARE_RO2 hw_spare_ro2 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RO3 0x374 32 HW_SPARE_RO3 hw_spare_ro3 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_REC 0x378 32 HW_SPARE_REC hw_spare_rec31 [31:31] Reserved for HW R&D 1 31 hw_spare_rec30 [30:30] Reserved for HW R&D 1 30 hw_spare_rec29 [29:29] Reserved for HW R&D 1 29 hw_spare_rec28 [28:28] Reserved for HW R&D 1 28 hw_spare_rec27 [27:27] Reserved for HW R&D 1 27 hw_spare_rec26 [26:26] Reserved for HW R&D 1 26 hw_spare_rec25 [25:25] Reserved for HW R&D 1 25 hw_spare_rec24 [24:24] Reserved for HW R&D 1 24 hw_spare_rec23 [23:23] Reserved for HW R&D 1 23 hw_spare_rec22 [22:22] Reserved for HW R&D 1 22 hw_spare_rec21 [21:21] Reserved for HW R&D 1 21 hw_spare_rec20 [20:20] Reserved for HW R&D 1 20 hw_spare_rec19 [19:19] Reserved for HW R&D 1 19 hw_spare_rec18 [18:18] Reserved for HW R&D 1 18 hw_spare_rec17 [17:17] Reserved for HW R&D 1 17 hw_spare_rec16 [16:16] Reserved for HW R&D 1 16 hw_spare_rec15 [15:15] Reserved for HW R&D 1 15 hw_spare_rec14 [14:14] Reserved for HW R&D 1 14 hw_spare_rec13 [13:13] Reserved for HW R&D 1 13 hw_spare_rec12 [12:12] Reserved for HW R&D 1 12 hw_spare_rec11 [11:11] Reserved for HW R&D 1 11 hw_spare_rec10 [10:10] Reserved for HW R&D 1 10 hw_spare_rec9 [9:9] Reserved for HW R&D 1 9 hw_spare_rec8 [8:8] Reserved for HW R&D 1 8 hw_spare_rec7 [7:7] Reserved for HW R&D 1 7 hw_spare_rec6 [6:6] Reserved for HW R&D 1 6 hw_spare_rec5 [5:5] Reserved for HW R&D 1 5 hw_spare_rec4 [4:4] Reserved for HW R&D 1 4 hw_spare_rec3 [3:3] Reserved for HW R&D 1 3 hw_spare_rec2 [2:2] Reserved for HW R&D 1 2 hw_spare_rec1 [1:1] Reserved for HW R&D 1 1 hw_spare_rec0 [0:0] Reserved for HW R&D 1 0 0 APP_CTRL 0x37C 32 APP_CTRL ecc_disable_2k_ram [0:0] Reserved 1 0 0 WIC_CTRL 0x380 32 WIC_CTRL wicmask [31:0] 1 => The corresponding interrupt is Masked (interrupt will not be generated) 0 => The corresponding interrupt is UnMasked (interrupt will be generated) 0 : ESM_HI_IRQ (NMI) 1 : ESM_LO_IRQ (INT#1) 2 : FECSS_FRAMETIMER_FRAME_START (INT#33) 3 : MUXED_FECSS_FRAME_START_OFFSET_INTR_TIME1 (INT#35) 4 : FECSS_FRAME_START_OFFSET_INTR_TIME2 (INT#36) 5 : FECSS_FRAME_START_OFFSET_INTR_TIME3 (INT#37) 6 : FECSS_BURST_START_OFFSET_TIME(INT#38) 7 : MUXED_APPSS_RTI1_RTI2_INT_REQ0(INT#43) 8 : MUXED_APPSS_RTI1_RTI2_INT_REQ1(INT#44) 9 : MUXED_APPSS_RTI1_RTI2_INT_REQ2(INT#45) 10 : MUXED_APPSS_RTI1_RTI2_INT_REQ3(INT#46) 11 : APPSS_SPI_IRQ_REQ(INT#14) 12 : SPI2_IRQ_REQ (part of INT#28) 13 : APPSS_LIN_INT0 (INT#10) 14 : APPSS_LIN_INT0 (INT#11) 15 : APPSS_MCAN_INT0(INT#21) 16 : APPSS_MCAN_INT1(INT#22) 17 : APPSS_SCI2_INT0(INT#62) 18 : APPSS_SCI2_INT0(INT#63) 19 : APPSS_SPI_IRQ_REQ(INT#14) 20 : SPI2_IRQ_REQ (part of INT#28) 21 : APPSS_LIN_INT0 (INT#10) 22 : APPSS_LIN_INT0 (INT#11) 23 : APPSS_MCAN_INT0(INT#21) 24 : APPSS_MCAN_INT1(INT#22) 25 : APPSS_SCI2_INT0(INT#62) 26 : APPSS_SCI2_INT0(INT#63) 27 : SYNC_IN 28 : RADAR_DEVICESLEEP_WAKEUP_INTERRUPT 29 to 31 : Reserved 32 0 0 WIC_STAT_CLR 0x384 32 WIC_STAT_CLR wicstatclr [31:0] 1 => Writing 1 to this bit, will clear the WIC_STAT status register of the corresponding bit. Self-clearing 0 => Writing 0 to this bit, leavesWIC_STAT status register unchanged for the corresponding bit. 32 0 0 WIC_STAT 0x388 32 WIC_STAT wicstat [31:0] 1 => Interrupt bit set. The interupt bit is sticky bit. Should be cleared using WIC_STAT_CLR register or subsystem reset. 0 -> Interrupt bit not set. Sticky bits keep their value when they changed to logical 1 and is cleared only by writing 1 to WIC_STAT_CLR register. 32 0 0 WICEN 0x38C 32 WICEN wicen [0:0] 1 :> Wakeup Interrupt Controller (WIC) of CM4 is Enabled 0 :> Disabled 1 0 0 FORCEFCLKACTIVE 0x390 32 FORCEFCLKACTIVE forcefclkactive [0:0] 1 :> Forces FCLK to be active and inhibits CM4 Entering CPU DeepSleep mode 0 :> Allows gating of FCLK based on CPU DEEPSLEEP entry mechanism 1 0 0 FECSS_CLK_GATE 0x394 32 FECSS_CLK_GATE grp2 [5:3] Multibit: Writing 3'b111 will gate ADC_CLK going to DFE and Timing Engine 3 3 grp1 [2:0] Multibit: Writing 3'b111 will gate FEC_SYS_CLK and FECSS peripheral clocks except DFE and Timing Engine 3 0 0 APPSS_SHARED_MEM_CLK_GATE 0x398 32 APPSS_SHARED_MEM_CLK_GATE mem1_app_enable [3:3] 1'b1 : Enable APP CLK ICG for second 128KB of shared mem 1'b0 : Disable APP CLK ICG for second 128 KB of shared mem 1 3 mem1_hwa_enable [2:2] 1'b1 : Enable HWA CLK ICG for second 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for second 128 KB of shared mem 1 2 mem0_app_enable [1:1] 1'b1 : Enable APP CLK ICG for first 128KB of shared mem 1'b0 : Disable APP CLK ICG for first 128 KB of shared mem 1 1 mem0_hwa_enable [0:0] 1'b1 : Enable HWA CLK ICG for first 128 KB of shared mem 1'b0 : Disable HWA CLK ICG for first 128 KB of shared mem 1 0 0 APPSS_MEM_INIT_SLICE_SEL 0x39C 32 APPSS_MEM_INIT_SLICE_SEL cfg_bank2 [4:3] Selects the APPSS RAM2 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_2A (16KB) Bit#1 : Selects RAM_2B (112KB) 1 => RAM partition selected for mem_init operation 0 => RAM partition not selected for mem_init operation. 2 3 cfg_bank1 [2:0] Selects the APPSS RAM1 partition that needs to be initialized. More than 1 partitions can be selected for mem_init. Bit#0 : Selects RAM_1A (64KB) Bit#1 : Selects RAM_1B (64KB) Bit#2 : Selects RAM_1C (128KB) 1 => RAM selected for mem_init operation 0 => RAM not selected for mem_init operation. 3 0 0 APPSS_QSPI_CHAR_EXT_CLK_EN 0x3A0 32 APPSS_QSPI_CHAR_EXT_CLK_EN enable [0:0] Selects the QSPI system clock. Only for DFT purposes. This should not be changed for functional operation. 0 => QSPI_CLK from APPSS RCM 1 => SPI1_CLK from APPSS RCM 1 0 0 APPSS_QSPI_EXT_CLK_EN 0x3A4 32 APPSS_QSPI_EXT_CLK_EN enable [0:0] Selects the QSPI interface clock. This register bit is used only for AC CHAR operation and not for functional usage. 0 => default QSPI IP clock return from PAD 1 => SPI1 IF CLK. (McSPI IF clock). 1 0 0 SPI1_SMART_IDLE 0x3A8 32 SPI1_SMART_IDLE wakeup_raw [5:5] Description: RAW status of CLKSTOP_WAKEUP from SPI1 module. This should be interpreted along with SPI1_SMART_IDLE_WAKEUP SPI1_SMART_IDLE_WAKEUP_RAW, SPI1_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status 1 5 ack_raw [4:4] Description: RAW status of CLKSTOP_ACK from McSPI (SPI1) module. This should be interpreted along with SPI1_SMART_IDLE_ACK SPI1_SMART_IDLE_ACK_RAW, SPI1_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status 1 4 wakeup [3:3] This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear. 1 3 auto_en [2:2] It is used to select smart idle mode. 1 => Automatic mode - Entry to smart idle mode Is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP 1 2 ack [1:1] 1 => SPI1 in smart idle mode 0 => SPI1 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear. 1 1 enable [0:0] 1 => Smart IDLE mode enabled. When set, request the clock gating of SPI1 module. 0 => Disable Smart IDLE mode for SPI1 1 0 0 SPI2_SMART_IDLE 0x3AC 32 SPI2_SMART_IDLE wakeup_raw [5:5] Description: RAW status of CLKSTOP_WAKEUP from SPI2 module. This should be interpreted along with SPI2_SMART_IDLE_WAKEUP SPI2_SMART_IDLE_WAKEUP_RAW, SPI2_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status 1 5 ack_raw [4:4] Description: RAW status of CLKSTOP_ACK from McSPI (SPI2) module. This should be interpreted along with SPI2_SMART_IDLE_ACK SPI2_SMART_IDLE_ACK_RAW, SPI2_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status 1 4 wakeup [3:3] This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear. 1 3 auto_en [2:2] It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP 1 2 ack [1:1] 1 => SPI2 in smart idle mode 0 => SPI2 not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear. 1 1 enable [0:0] 1 => Smart IDLE mode enabled. When set, request the clock gating of SPI2 module. 0 => Disable Smart IDLE mode for SPI2 1 0 0 CAN_SMART_IDLE 0x3B0 32 CAN_SMART_IDLE wakeup_raw [5:5] Description: RAW status of CLKSTOP_WAKEUP from CANFD module. This should be interpreted along with CAN_SMART_IDLE_WAKEUP CAN_SMART_IDLE_WAKEUP_RAW, CAN_SMART_IDLE_WAKEUP 0 , 0 => WAKEUP is LOW from IP, and No pending WAKEUP status 0 , 1 => WAKEUP is LOW from IP, and pending WAKEUP status 1 , 0 => WAKEUP is HIGH from IP, and No pending WAKEUP status 1 , 1 => WAKEUP is HIGH from IP, and pending WAKEUP status 1 5 ack_raw [4:4] Description: RAW status of CLKSTOP_ACK from CANFD module. This should be interpreted along with CAN_SMART_IDLE_ACK CAN_SMART_IDLE_ACK_RAW, CAN_SMART_IDLE_ACK 0 , 0 => ACK is LOW from IP, and No pending ACK status 0 , 1 => ACK is LOW from IP, and pending ACK status 1 , 0 => ACK is HIGH from IP, and No pending ACK status 1 , 1 => ACK is HIGH from IP, and pending ACK status 1 4 wakeup [3:3] This register reflects the Wakeup Status of the IP. The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear. 1 3 auto_en [2:2] It is used to select smart idle mode. 1 => Automatic mode - In this mode, entry to smart idle mode is manual by setting SMART_IDLE_ENABLE = 1. When the wakeup Signal is asserted (based on the activity), The clkstop_req is pulled low automatically. 0 => Manual mode - The entry and exit to Smart Idle is user controlled based on polling SMART_IDLE_ACK and SMART_IDLE_WAKEUP 1 2 ack [1:1] 1 => CAN in smart idle mode0 => CAN not in smart idle mode The bit is sticky bit and the user is should clear once the status is read by write-1-to-clear. 1 1 enable [0:0] 1 => Smart IDLE mode enabled. When set, Request the clock gating of CAN module.0 => Disable Smart IDLE mode for CAN 1 0 0 LIN_SMART_IDLE 0x3B4 32 LIN_SMART_IDLE ack [1:1] 1 => LIN in smart idle mode0 => LIN not in smart idle mode 1 1 enable [0:0] 1 => Smart IDLE mode enabled. When set, Request the clock gating of LIN module.0 => Disable Smart IDLE mode for LIN 1 0 0 HWASS_CLK_GATE 0x3B8 32 HWASS_CLK_GATE enable [2:0] RESERVED 3 0 0 CFG_TIMEOUT_PCR3 0x3BC 32 CFG_TIMEOUT_PCR3 value [31:0] PCR3Timeout Value 32 0 0 RESERVED0 0x3C0 32 RESERVED0 reserved [15:0] RESERVED - POR Reset 16 0 0 APPSS_ERRAGG_MASK1 0x3C4 32 APPSS_ERRAGG_MASK1 cluster12_power_down_access_err [11:11] Mask Interrupt from cluster12_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 11 cluster11_power_down_access_err [10:10] Mask Interrupt from cluster11_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 10 cluster10_power_down_access_err [9:9] Mask Interrupt from cluster10_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 9 cluster9_power_down_access_err [8:8] Mask Interrupt from cluster9_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 8 cluster8_power_down_access_err [7:7] Mask Interrupt from cluster8_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 7 cluster7_power_down_access_err [6:6] Mask Interrupt from cluster7_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 6 cluster6_power_down_access_err [5:5] Mask Interrupt from cluster6_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 5 cluster5_power_down_access_err [4:4] Mask Interrupt from cluster5_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 4 cluster4_power_down_access_err [3:3] Mask Interrupt from cluster4_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 3 cluster3_power_down_access_err [2:2] Mask Interrupt from cluster3_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 2 cluster2_power_down_access_err [1:1] Mask Interrupt from cluster2_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 1 cluster1_power_down_access_err [0:0] Mask Interrupt from cluster1_power_down_access_err Interrupt APPSS_ACCESS_ERRAGG 1 : Interrupt is Masked 0 : Interrupt is Unmasked 1 0 0 APPSS_ERRAGG_STATUS1 0x3C8 32 APPSS_ERRAGG_STATUS1 cluster12_power_down_access_err [11:11] Status of Interrupt from cluster12_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 11 cluster11_power_down_access_err [10:10] Status of Interrupt from cluster11_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 10 cluster10_power_down_access_err [9:9] Status of Interrupt from cluster10_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 9 cluster9_power_down_access_err [8:8] Status of Interrupt from cluster9_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 8 cluster8_power_down_access_err [7:7] Status of Interrupt from cluster8_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 7 cluster7_power_down_access_err [6:6] Status of Interrupt from cluster7_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 6 cluster6_power_down_access_err [5:5] Status of Interrupt from cluster6_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 5 cluster5_power_down_access_err [4:4] Status of Interrupt from cluster5_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 4 cluster4_power_down_access_err [3:3] Status of Interrupt from cluster4_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 3 cluster3_power_down_access_err [2:2] Status of Interrupt from cluster3_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 2 cluster2_power_down_access_err [1:1] Status of Interrupt from cluster2_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 1 cluster1_power_down_access_err [0:0] Status of Interrupt from cluster1_power_down_access_err Set only if Interupt is unmasked in APPSS_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt. 1 0 0 FORCEHCLKACTIVE 0x3CC 32 FORCEHCLKACTIVE forcehclkactive [0:0] 1 :> Gate HCLK 0 :> UnGate HCLK 1 0 0 APPSS_RAM1_OWRITE_ERR 0x3D0 32 APPSS_RAM1_OWRITE_ERR err [0:0] RAM1 ahb2sram write error - Sticky Bit 1 0 0 APPSS_RAM1_OWRITE_ERR_ADDR 0x3D4 32 APPSS_RAM1_OWRITE_ERR_ADDR address [31:0] RAM1 ahb2sram write error Address 32 0 0 APPSS_RAM2_OWRITE_ERR 0x3D8 32 APPSS_RAM2_OWRITE_ERR err [0:0] RAM2 ahb2sram write error - Sticky Bit 1 0 0 APPSS_RAM2_OWRITE_ERR_ADDR 0x3DC 32 APPSS_RAM2_OWRITE_ERR_ADDR address [31:0] RAM2 ahb2sram write error Address 32 0 0 APPSS_RAM3_OWRITE_ERR 0x3E0 32 APPSS_RAM3_OWRITE_ERR err [0:0] RAM3 ahb2sram write error - Sticky Bit 1 0 0 APPSS_RAM3_OWRITE_ERR_ADDR 0x3E4 32 APPSS_RAM3_OWRITE_ERR_ADDR address [31:0] RAM3 ahb2sram write error Address 32 0 0 APPSS_SHRD_RAM_OWRITE_ERR 0x3E8 32 APPSS_SHRD_RAM_OWRITE_ERR err [0:0] SHARED RAM ahb2sram write error - Sticky Bit 1 0 0 APPSS_SHRD_RAM_OWRITE_ERR_ADDR 0x3EC 32 APPSS_SHRD_RAM_OWRITE_ERR_ADDR address [31:0] SHARED RAM ahb2sram write error Address 32 0 0 APPSS_OWRITE_ERR_AGGR 0x3F0 32 APPSS_OWRITE_ERR_AGGR err [0:0] Ored error of all write error signals -Sticky Bit 1 0 0 HW_SPARE_RW6 0x3F4 32 HW_SPARE_RW6 hw_spare_rw6 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RW7 0x3F8 32 HW_SPARE_RW7 hw_spare_rw7 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RW8 0x3FC 32 HW_SPARE_RW8 hw_spare_rw8 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_RW9 0x400 32 HW_SPARE_RW9 hw_spare_rw9 [31:0] Reserved for HW R&D 32 0 0 HW_SPARE_HWA_RW0 0x404 32 HW_SPARE_HWA_RW0 hw_spare_hwa_rw0 [31:0] Reserved for HW R&D 32 0 0 LOCK0_KICK0 0x1008 32 - KICK0 component [31:0] - KICK0 component 32 0 0 LOCK0_KICK1 0x100C 32 - KICK1 component [31:0] - KICK1 component 32 0 0 intr_raw_status 0x1010 32 Interrupt Raw Status/Set Register [3:3] Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 0 0 intr_enabled_status_clear 0x1014 32 Interrupt Enabled Status/Clear register [3:3] Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 0 0 intr_enable 0x1018 32 Interrupt Enable register [3:3] Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 0 0 intr_enable_clear 0x101C 32 Interrupt Enable Clear register [3:3] Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 0 0 eoi 0x1020 32 EOI register [7:0] EOI vector value. Write this with interrupt distribution value in the chip. 8 0 0 fault_address 0x1024 32 Fault Address register [31:0] Fault Address. 32 0 0 fault_type_status 0x1028 32 Fault Type Status register [6:6] Non-secure access. 1 6 [5:0] Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault 6 0 0 fault_attr_status 0x102C 32 Fault Attribute Status register [31:20] XID. 12 20 [19:8] Route ID. 12 8 [7:0] Privilege ID. 8 0 0 fault_clear 0x1030 32 Fault Clear register [0:0] Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect. 1 0 0 APP_HWA_ADCBUF_CTRL 0x56080000 0 4148 registers PID 0x0 32 PID register 16 16 5 11 3 8 2 6 6 0 0 HW_REG0 0x4 32 HW_REG0 HW_REG0 [31:0] Reserved 32 0 0 ADCBUFCFG1 0x8 32 ADCBUFCFG1 ADCBUF_RST [17:17] Writing 1'b1 : Resets ADC BUFFER Control logic. Writing 1'b0: Releases the reset for ADC BUFFER control logic. 1 17 ADCBUFPIPOSEL [16:16] TI Internal Feature Ping-pong select value from ADC Buffer Packing logic. Even in SW override mode, this register will indicate the ping-pong select signal generated from the ADC Buffer Packing logic and not the override value. 1 16 ADCBUFCONTSTOPPL [15:15] Stop Pulse for Continuous mode. The data capture will stop once this register is set. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse 1 15 ADCBUFCONTSTRTPL [14:14] Start Pulse for Continuous mode. The data capture will start from Address 0 once this register is set. All the other configurations like Enable, Sample Count are expected to be programmed before this pulse. Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode : Its a wspecial access type, write to this field will generate a pulse 1 14 ADCBUFCONTMODEEN [13:13] Continuous mode enable for ADC Buffer. This is set when a fixed number of samples have to be stored in Ping/Pong and not depend on Chirp time-lines (Eg: Analog Lab characterization to stream out continuous data from DFE). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode 1 13 ADCBUFPIPOOVRVAL [11:11] TI Internal Feature SW override value for ADC Buffer Ping Pong select 1 11 ADCBUFPIPOOVRCNT [10:10] TI Internal Feature Override control for ADC Buffer Ping Pong select 1 10 RX3EN [9:9] TI Reserved 1 9 RX2EN [8:8] Enable for Rx2 write 1 8 RX1EN [7:7] Enable for Rx1 write 1 7 RX0EN [6:6] Enable for Rx0 write 1 6 ADCBUFPIPOSELINV [1:1] TI Internal Feature Inversion control for ADC Buffer Ping-pong select. By default ADC Buffer write starts with Pong write. By setting this bit to 1, it will start from Ping write after reset. 1 1 ADCBUFWRSOURCE [0:0] TI Internal Feature Write source for ADC Buffer. 0 --> DFE, 1 --> HWASS Interconnect 1 0 0 ADCBUFCFG1_EXTD 0xC 32 ADCBUFCFG1_EXTD ADCBUFINTGENDLY [31:0] TI Intenal Feature. No of clocks to delay the ping-pong switch and interrupt generation w.r.t ADC Valid fall pulse. This will enable dithering the DSP activity for successive ping-pong switch cycles. This will not delay the ping pong toggle which will happen immediately after ADC Valid fall. 32 0 0 ADCBUFCFG2 0x10 32 ADCBUFCFG2 ADCBUFADDRX1 [26:16] 128 bit Address offset to be added to the internal address pointer for Rx1 writes in Non-interleaved mode. 11 16 ADCBUFADDRX0 [10:0] 128 bit Address offset to be added to the internal address pointer for Rx0 writes in Non-interleaved mode. 11 0 0 ADCBUFCFG3 0x14 32 ADCBUFCFG3 ADCBUFADDRX3 [26:16] TI Reserved 11 16 ADCBUFADDRX2 [10:0] 128 bit Address offset to be added to the internal address pointer for Rx2 writes in Non-interleaved mode. 11 0 0 ADCBUFCFG4 0x18 32 ADCBUFCFG4 ADCBUFPNGSELTGLDIS [30:30] TI Internal Feature 0 --> Delay Interrupt Gen and Ping/Pong toggle together based on cfg_interrupt_gen_delay, 1 --> Delay only Interrupt Gen based on cfg_interrupt_gen_delay. But toggle Ping/Pong select signal as soon as the write is complete. 1 30 ADCBUFNUMCHRPPING [20:16] Number of chirps to be stored in Ping / Pong buffer. This register should be programmed with one less than the actual number needed. 5 16 ADCBUFSAMPCNT [15:0] No of samples to store in each Ping and Pong register in continuous mode of ADC Buffer. In real only mode this refers to the number of real samples and in complex mode, this refers to number of complex samples. This refers to the number of samples per channel. This counter increments once for every new sample from DFE (as long as 1 or more channels are enabled). The max allowed value varies depending on other configurations (No of channels enabled and real/complex data). Continous mode is expected to be only used for CZ and ADC Buffer Testpattern mode 16 0 0 ADCBUFINTGENDITHERDLY 0x1C 32 ADCBUFINTGENDITHERDLY ADCBUFINTGENDITHERDLY [31:0] TI Internal Feature. Additional dithering delay added on the Chirp Avilable interrupt 32 0 0 ADCBUFF_PING_MEM_INIT 0x20 32 ADCBUFF_PING_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUFF PING Memory . Value in each row is initialized to 0x00_0000_0000 1 0 0 ADCBUFF_PING_MEM_DONE 0x24 32 ADCBUFF_PING_MEM_DONE mem_init_done [0:0] This field will be high once initialization of ADCBUFF PING Memory is finished. Writing '1' would clear the bit. 1 0 0 ADCBUFF_PING_MEM_STATUS 0x28 32 ADCBUFF_PING_MEM_STATUS mem_init_status [0:0] 1'b0: No initialization is happening for ADCBUF PING Memory 1'b1: Initialization is in progress for ADCBUF PING Memory 1 0 0 ADCBUFF_PONG_MEM_INIT 0x2C 32 ADCBUFF_PONG_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initialization of ADCBUF PONG Memory . Value in each row is initialized to 0x00_0000_0000 1 0 0 ADCBUFF_PONG_MEM_DONE 0x30 32 ADCBUFF_PONG_MEM_DONE mem_init_done [0:0] This field will be high once initialization of ADCBUF PONG Memory is finished. Writing '1' would clear the bit. 1 0 0 ADCBUFF_PONG_MEM_STATUS 0x34 32 ADCBUFF_PONG_MEM_STATUS mem_init_status [0:0] 1'b0: No initialization is happening for ADCBUF PONG Memory 1'b1: Initialization is in progress for ADCBUF PONG Memory 1 0 0 HWASS_SHRD_RAM_MEM_INIT 0x38 32 HWASS_SHRD_RAM_MEM_INIT mem_init [0:0] Write_pulse bit field: Writing 1'b1 will start initialization of HWASS 160 kb shared memory bank . Value in each row is initialized to 0x00_0000_0000 1 0 0 HWASS_SHRD_RAM_MEM_DONE 0x3C 32 HWASS_SHRD_RAM_MEM_DONE mem_init_done [0:0] This field will be high once initialization of HWASS 160 kb shared memory bank is finished. Writing '1' would clear the bit. 1 0 0 HWASS_SHRD_RAM_MEM_STATUS 0x40 32 HWASS_SHRD_RAM_MEM_STATUS mem_init_status [0:0] 1'b0: No initialization is happening for HWASS 160kb shared memory bank 1'b1: Initialization is in progress for HWASS 160kb shared memory bank 1 0 0 HWASS_SHRD_RAM_ACCESS_ERROR_MASK 0x44 32 HWASS_SHRD_RAM_ACCESS_ERROR_MASK shmem_access_error_mask [0:0] When 1'b1 : shared ram access error is masked. 1'b0 : shared ram access error is not masked. 1 0 0 HWASS_SHRD_RAM_ACCESS_ERROR_STATUS 0x48 32 HWASS_SHRD_RAM_ACCESS_ERROR_STATUS shmem_access_error_status [0:0] This field will be high whenever the invalid address of shared memory is accessed and the interrupt is not masked. 1 0 0 HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW 0x4C 32 HWASS_SHRD_RAM_ACCESS_ERROR_STATUS_RAW shmem_access_errror_status_raw [0:0] Indicates the shared ram access error (raw status). Set irrespective of HWASS_SHRD_RAM_ACCESS_ERROR_MASK bit 1 0 0 HWASS_EDMA_CLOCK_GATE_CONTROL 0x50 32 HWASS_EDMA_CLOCK_GATE_CONTROL hwa_edma_clock_gating_en [2:0] Writing 3'b111 will gate the clock to HWA EDMA.Writing 3'b000 will ungate the clock 3 0 0 HWASS_RAM_160KB_CLOCK_GATE 0x54 32 HWASS_RAM_160KB_CLOCK_GATE enable [2:0] 3'b000 : Ungate clock to 160KB RAM 3'b111 : Gate Clock to 160KB RAM 3 0 0 LOCK0_KICK0 0x1008 32 - KICK0 component [31:0] - KICK0 component 32 0 0 LOCK0_KICK1 0x100C 32 - KICK1 component [31:0] - KICK1 component 32 0 0 intr_raw_status 0x1010 32 Interrupt Raw Status/Set Register [3:3] Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 0 0 intr_enabled_status_clear 0x1014 32 Interrupt Enabled Status/Clear register [3:3] Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 0 0 intr_enable 0x1018 32 Interrupt Enable register [3:3] Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 0 0 intr_enable_clear 0x101C 32 Interrupt Enable Clear register [3:3] Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 0 0 eoi 0x1020 32 EOI register [7:0] EOI vector value. Write this with interrupt distribution value in the chip. 8 0 0 fault_address 0x1024 32 Fault Address register [31:0] Fault Address. 32 0 0 fault_type_status 0x1028 32 Fault Type Status register [6:6] Non-secure access. 1 6 [5:0] Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault 6 0 0 fault_attr_status 0x102C 32 Fault Attribute Status register [31:20] XID. 12 20 [19:8] Route ID. 12 8 [7:0] Privilege ID. 8 0 0 fault_clear 0x1030 32 Fault Clear register [0:0] Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect. 1 0 0 APP_ECC_AGG 0x56F7EC00 0 784 registers APP_ECC_AGG AGGR_REVISION 0x0 32 Revision parameters SCHEME [31:30] Scheme - (RO ) 2 30 BU [29:28] bu - (RO ) 2 28 MODULE_ID [27:16] Module ID - (RO ) 12 16 REVRTL [15:11] RTL version - (RO ) 5 11 REVMAJ [10:8] Major version - (RO ) 3 8 CUSTOM [7:6] Custom version - (RO ) 2 6 REVMIN [5:0] Minor version - (RO ) 6 0 0 ECC_VECTOR 0x8 32 ECC Vector Register RES1 [31:25] RESERVE FIELD 7 25 RD_SVBUS_DONE [24:24] Status to indicate if read on serial VBUS is complete - (RO ) 1 24 RD_SVBUS_ADDRESS [23:16] Read address - (RW ) 8 16 RD_SVBUS [15:15] Write 1 to trigger a read on the serial VBUS - (RW ) 1 15 RES2 [14:11] RESERVE FIELD 4 11 ECC_VECTOR [10:0] Value written to select the corresponding ECC RAM for control or status - (RW ) 11 0 0 MISC_STATUS 0xC 32 Misc Status RES3 [31:11] RESERVE FIELD 21 11 NUM_RAMS [10:0] Indicates the number of RAMS serviced by the ECC aggregator - (RO ) 11 0 0 ECC_WRAP_REVISION 0x10 32 Revision parameters SCHEME [31:30] Scheme - (RO ) 2 30 BU [29:28] bu - (RO ) 2 28 MODULE_ID [27:16] Module ID - (RO ) 12 16 REVRTL [15:11] RTL version - (RO ) 5 11 REVMAJ [10:8] Major version - (RO ) 3 8 CUSTOM [7:6] Custom version - (RO ) 2 6 REVMIN [5:0] Minor version - (RO ) 6 0 0 CONTROL 0x14 32 ECC Control Register RES4 [31:9] RESERVE FIELD 23 9 CHECK_SVBUS_TIMEOUT [8:8] check for svbus timeout errors - (RW ) 1 8 CHECK_PARITY [7:7] check for parity errors - (RW ) 1 7 ERROR_ONCE [6:6] Force Error only once - (RW ) 1 6 FORCE_N_ROW [5:5] Force Error on any RAM read - (RW ) 1 5 FORCE_DED [4:4] Force Double Bit Error - (RW ) 1 4 FORCE_SEC [3:3] Force Single Bit Error - (RW ) 1 3 ENABLE_RMW [2:2] Enable rmw - (RW ) 1 2 ECC_CHECK [1:1] Enable ECC check - (RW ) 1 1 ECC_ENABLE [0:0] Enable ECC - (RW ) 1 0 0 ERROR_CTRL1 0x18 32 ECC Error Control1 Register ECC_ROW [31:0] Row address where single or double-bit error needs to be applied. This is ignored if force_n_row is set - (RW ) 32 0 0 ERROR_CTRL2 0x1C 32 ECC Error Control2 Register ECC_BIT2 [31:16] Data bit that needs to be flipped if double bit error needs to be forced - (RW ) 16 16 ECC_BIT1 [15:0] Data bit that needs to be flipped when force_sec is set - (RW ) 16 0 0 ERROR_STATUS1 0x20 32 ECC Error Status1 Register ECC_BIT1 [31:16] Data bit that corresponds to the single-bit error - (RO ) 16 16 CLR_CTRL_REG_ERR [15:15] Clear control reg error Error Status you must also re write the contorl ergister itself to clear this - (RW ) 1 15 CLR_PARITY_ERR [14:13] Clear parity Error Status - (RW decr) 2 13 CLR_ECC_OTHER [12:12] Clear other Error Status - (RW ) 1 12 CLR_ECC_DED [11:10] Clear Double Bit Error Status - (RW decr) 2 10 CLR_ECC_SEC [9:8] Clear Single Bit Error Status - (RW decr) 2 8 CTR_REG_ERR [7:7] control register error pending Level interrupt - (RW 1 7 PARITY_ERR [6:5] Level parity error Error Status - (RW ) 2 5 ECC_OTHER [4:4] successive single-bit errors have occurred while a writeback is still pending Level interrupt - (RW 1 4 ECC_DED [3:2] Level Double Bit Error Status - (RW incr) 2 2 ECC_SEC [1:0] Level Single Bit Error Status - (RW incr) 2 0 0 ERROR_STATUS2 0x24 32 ECC Error Status2 Register ECC_ROW [31:0] Row address where the single or double-bit error has occurred - (RO ) 32 0 0 ERROR_STATUS3 0x28 32 ECC Error Status3 Register RES5 [31:10] RESERVE FIELD 22 10 CLR_SVBUS_TIMEOUT_ERR [9:9] Clear svbus timeout Error Status - (RW ) 1 9 RES6 [8:2] RESERVE FIELD 7 2 SVBUS_TIMEOUT_ERR [1:1] Level svbus timeout error Error Status - (RW ) 1 1 WB_PEND [0:0] delayed write back pending Status - (RO ) 1 0 0 SEC_EOI_REG 0x3C 32 EOI Register RES7 [31:1] RESERVE FIELD 31 1 EOI_WR [0:0] EOI Register - (RW ) 1 0 0 SEC_STATUS_REG0 0x40 32 Interrupt Status Register 0 RES8 [31:14] RESERVE FIELD 18 14 ADCPONG_RAMECC_PEND [13:13] Interrupt Pending Status for adcpong_ramecc_pend - (RW ) 1 13 ADCPING_RAMECC_PEND [12:12] Interrupt Pending Status for adcping_ramecc_pend - (RW ) 1 12 SHARED_MEM2_RAMECC_PEND [11:11] Interrupt Pending Status for shared_mem2_ramecc_pend - (RW ) 1 11 HWA_PARAM_MEM_PEND [10:10] Interrupt Pending Status for hwa_param_mem_pend - (RW ) 1 10 SHARED_MEM1_RAMECC_PEND [9:9] Interrupt Pending Status for shared_mem1_ramecc_pend - (RW ) 1 9 SHARED_MEM0_RAMECC_PEND [8:8] Interrupt Pending Status for shared_mem0_ramecc_pend - (RW ) 1 8 HWA_TPTC2_PEND [7:7] Interrupt Pending Status for hwa_tptc2_pend - (RW ) 1 7 HWA_TPTC1_PEND [6:6] Interrupt Pending Status for hwa_tptc1_pend - (RW ) 1 6 APP_SS_TPTC2_PEND [5:5] Interrupt Pending Status for app_ss_tptc2_pend - (RW ) 1 5 APP_SS_TPTC1_PEND [4:4] Interrupt Pending Status for app_ss_tptc1_pend - (RW ) 1 4 APP_SS_RAM3_PEND [3:3] Interrupt Pending Status for app_ss_ram3_pend - (RW ) 1 3 APP_SS_RAM2_PEND [2:2] Interrupt Pending Status for app_ss_ram2_pend - (RW ) 1 2 APP_SS_RAM1_PEND [1:1] Interrupt Pending Status for app_ss_ram1_pend - (RW ) 1 1 APP_SS_ROM_PEND [0:0] Interrupt Pending Status for app_ss_rom_pend - (RW ) 1 0 0 SEC_ENABLE_SET_REG0 0x80 32 Interrupt Enable Set Register 0 RES9 [31:14] RESERVE FIELD 18 14 ADCPONG_RAMECC_ENABLE_SET [13:13] Interrupt Enable Set Register for adcpong_ramecc_pend - (RW ) 1 13 ADCPING_RAMECC_ENABLE_SET [12:12] Interrupt Enable Set Register for adcping_ramecc_pend - (RW ) 1 12 SHARED_MEM2_RAMECC_ENABLE_SET [11:11] Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW ) 1 11 HWA_PARAM_MEM_ENABLE_SET [10:10] Interrupt Enable Set Register for hwa_param_mem_pend - (RW ) 1 10 SHARED_MEM1_RAMECC_ENABLE_SET [9:9] Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW ) 1 9 SHARED_MEM0_RAMECC_ENABLE_SET [8:8] Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW ) 1 8 HWA_TPTC2_ENABLE_SET [7:7] Interrupt Enable Set Register for hwa_tptc2_pend - (RW ) 1 7 HWA_TPTC1_ENABLE_SET [6:6] Interrupt Enable Set Register for hwa_tptc1_pend - (RW ) 1 6 APP_SS_TPTC2_ENABLE_SET [5:5] Interrupt Enable Set Register for app_ss_tptc2_pend - (RW ) 1 5 APP_SS_TPTC1_ENABLE_SET [4:4] Interrupt Enable Set Register for app_ss_tptc1_pend - (RW ) 1 4 APP_SS_RAM3_ENABLE_SET [3:3] Interrupt Enable Set Register for app_ss_ram3_pend - (RW ) 1 3 APP_SS_RAM2_ENABLE_SET [2:2] Interrupt Enable Set Register for app_ss_ram2_pend - (RW ) 1 2 APP_SS_RAM1_ENABLE_SET [1:1] Interrupt Enable Set Register for app_ss_ram1_pend - (RW ) 1 1 APP_SS_ROM_ENABLE_SET [0:0] Interrupt Enable Set Register for app_ss_rom_pend - (RW ) 1 0 0 SEC_ENABLE_CLR_REG0 0xC0 32 Interrupt Enable Clear Register 0 RES10 [31:14] RESERVE FIELD 18 14 ADCPONG_RAMECC_ENABLE_CLR [13:13] Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW ) 1 13 ADCPING_RAMECC_ENABLE_CLR [12:12] Interrupt Enable Clear Register for adcping_ramecc_pend - (RW ) 1 12 SHARED_MEM2_RAMECC_ENABLE_CLR [11:11] Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW ) 1 11 HWA_PARAM_MEM_ENABLE_CLR [10:10] Interrupt Enable Clear Register for hwa_param_mem_pend - (RW ) 1 10 SHARED_MEM1_RAMECC_ENABLE_CLR [9:9] Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW ) 1 9 SHARED_MEM0_RAMECC_ENABLE_CLR [8:8] Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW ) 1 8 HWA_TPTC2_ENABLE_CLR [7:7] Interrupt Enable Clear Register for hwa_tptc2_pend - (RW ) 1 7 HWA_TPTC1_ENABLE_CLR [6:6] Interrupt Enable Clear Register for hwa_tptc1_pend - (RW ) 1 6 APP_SS_TPTC2_ENABLE_CLR [5:5] Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW ) 1 5 APP_SS_TPTC1_ENABLE_CLR [4:4] Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW ) 1 4 APP_SS_RAM3_ENABLE_CLR [3:3] Interrupt Enable Clear Register for app_ss_ram3_pend - (RW ) 1 3 APP_SS_RAM2_ENABLE_CLR [2:2] Interrupt Enable Clear Register for app_ss_ram2_pend - (RW ) 1 2 APP_SS_RAM1_ENABLE_CLR [1:1] Interrupt Enable Clear Register for app_ss_ram1_pend - (RW ) 1 1 APP_SS_ROM_ENABLE_CLR [0:0] Interrupt Enable Clear Register for app_ss_rom_pend - (RW ) 1 0 0 DED_EOI_REG 0x13C 32 EOI Register RES11 [31:1] RESERVE FIELD 31 1 EOI_WR [0:0] EOI Register - (RW ) 1 0 0 DED_STATUS_REG0 0x140 32 Interrupt Status Register 0 RES12 [31:14] RESERVE FIELD 18 14 ADCPONG_RAMECC_PEND [13:13] Interrupt Pending Status for adcpong_ramecc_pend - (RW ) 1 13 ADCPING_RAMECC_PEND [12:12] Interrupt Pending Status for adcping_ramecc_pend - (RW ) 1 12 SHARED_MEM2_RAMECC_PEND [11:11] Interrupt Pending Status for shared_mem2_ramecc_pend - (RW ) 1 11 HWA_PARAM_MEM_PEND [10:10] Interrupt Pending Status for hwa_param_mem_pend - (RW ) 1 10 SHARED_MEM1_RAMECC_PEND [9:9] Interrupt Pending Status for shared_mem1_ramecc_pend - (RW ) 1 9 SHARED_MEM0_RAMECC_PEND [8:8] Interrupt Pending Status for shared_mem0_ramecc_pend - (RW ) 1 8 HWA_TPTC2_PEND [7:7] Interrupt Pending Status for hwa_tptc2_pend - (RW ) 1 7 HWA_TPTC1_PEND [6:6] Interrupt Pending Status for hwa_tptc1_pend - (RW ) 1 6 APP_SS_TPTC2_PEND [5:5] Interrupt Pending Status for app_ss_tptc2_pend - (RW ) 1 5 APP_SS_TPTC1_PEND [4:4] Interrupt Pending Status for app_ss_tptc1_pend - (RW ) 1 4 APP_SS_RAM3_PEND [3:3] Interrupt Pending Status for app_ss_ram3_pend - (RW ) 1 3 APP_SS_RAM2_PEND [2:2] Interrupt Pending Status for app_ss_ram2_pend - (RW ) 1 2 APP_SS_RAM1_PEND [1:1] Interrupt Pending Status for app_ss_ram1_pend - (RW ) 1 1 APP_SS_ROM_PEND [0:0] Interrupt Pending Status for app_ss_rom_pend - (RW ) 1 0 0 DED_ENABLE_SET_REG0 0x180 32 Interrupt Enable Set Register 0 RES13 [31:14] RESERVE FIELD 18 14 ADCPONG_RAMECC_ENABLE_SET [13:13] Interrupt Enable Set Register for adcpong_ramecc_pend - (RW ) 1 13 ADCPING_RAMECC_ENABLE_SET [12:12] Interrupt Enable Set Register for adcping_ramecc_pend - (RW ) 1 12 SHARED_MEM2_RAMECC_ENABLE_SET [11:11] Interrupt Enable Set Register for shared_mem2_ramecc_pend - (RW ) 1 11 HWA_PARAM_MEM_ENABLE_SET [10:10] Interrupt Enable Set Register for hwa_param_mem_pend - (RW ) 1 10 SHARED_MEM1_RAMECC_ENABLE_SET [9:9] Interrupt Enable Set Register for shared_mem1_ramecc_pend - (RW ) 1 9 SHARED_MEM0_RAMECC_ENABLE_SET [8:8] Interrupt Enable Set Register for shared_mem0_ramecc_pend - (RW ) 1 8 HWA_TPTC2_ENABLE_SET [7:7] Interrupt Enable Set Register for hwa_tptc2_pend - (RW ) 1 7 HWA_TPTC1_ENABLE_SET [6:6] Interrupt Enable Set Register for hwa_tptc1_pend - (RW ) 1 6 APP_SS_TPTC2_ENABLE_SET [5:5] Interrupt Enable Set Register for app_ss_tptc2_pend - (RW ) 1 5 APP_SS_TPTC1_ENABLE_SET [4:4] Interrupt Enable Set Register for app_ss_tptc1_pend - (RW ) 1 4 APP_SS_RAM3_ENABLE_SET [3:3] Interrupt Enable Set Register for app_ss_ram3_pend - (RW ) 1 3 APP_SS_RAM2_ENABLE_SET [2:2] Interrupt Enable Set Register for app_ss_ram2_pend - (RW ) 1 2 APP_SS_RAM1_ENABLE_SET [1:1] Interrupt Enable Set Register for app_ss_ram1_pend - (RW ) 1 1 APP_SS_ROM_ENABLE_SET [0:0] Interrupt Enable Set Register for app_ss_rom_pend - (RW ) 1 0 0 DED_ENABLE_CLR_REG0 0x1C0 32 Interrupt Enable Clear Register 0 RES14 [31:14] RESERVE FIELD 18 14 ADCPONG_RAMECC_ENABLE_CLR [13:13] Interrupt Enable Clear Register for adcpong_ramecc_pend - (RW ) 1 13 ADCPING_RAMECC_ENABLE_CLR [12:12] Interrupt Enable Clear Register for adcping_ramecc_pend - (RW ) 1 12 SHARED_MEM2_RAMECC_ENABLE_CLR [11:11] Interrupt Enable Clear Register for shared_mem2_ramecc_pend - (RW ) 1 11 HWA_PARAM_MEM_ENABLE_CLR [10:10] Interrupt Enable Clear Register for hwa_param_mem_pend - (RW ) 1 10 SHARED_MEM1_RAMECC_ENABLE_CLR [9:9] Interrupt Enable Clear Register for shared_mem1_ramecc_pend - (RW ) 1 9 SHARED_MEM0_RAMECC_ENABLE_CLR [8:8] Interrupt Enable Clear Register for shared_mem0_ramecc_pend - (RW ) 1 8 HWA_TPTC2_ENABLE_CLR [7:7] Interrupt Enable Clear Register for hwa_tptc2_pend - (RW ) 1 7 HWA_TPTC1_ENABLE_CLR [6:6] Interrupt Enable Clear Register for hwa_tptc1_pend - (RW ) 1 6 APP_SS_TPTC2_ENABLE_CLR [5:5] Interrupt Enable Clear Register for app_ss_tptc2_pend - (RW ) 1 5 APP_SS_TPTC1_ENABLE_CLR [4:4] Interrupt Enable Clear Register for app_ss_tptc1_pend - (RW ) 1 4 APP_SS_RAM3_ENABLE_CLR [3:3] Interrupt Enable Clear Register for app_ss_ram3_pend - (RW ) 1 3 APP_SS_RAM2_ENABLE_CLR [2:2] Interrupt Enable Clear Register for app_ss_ram2_pend - (RW ) 1 2 APP_SS_RAM1_ENABLE_CLR [1:1] Interrupt Enable Clear Register for app_ss_ram1_pend - (RW ) 1 1 APP_SS_ROM_ENABLE_CLR [0:0] Interrupt Enable Clear Register for app_ss_rom_pend - (RW ) 1 0 0 AGGR_ENABLE_SET 0x200 32 AGGR interrupt enable set Register RES15 [31:2] RESERVE FIELD 30 2 TIMEOUT [1:1] interrupt enable set for svbus timeout errors - (RW ) 1 1 PARITY [0:0] interrupt enable set for parity errors - (RW ) 1 0 0 AGGR_ENABLE_CLR 0x204 32 AGGR interrupt enable clear Register RES16 [31:2] RESERVE FIELD 30 2 TIMEOUT [1:1] interrupt enable clear for svbus timeout errors - (RW ) 1 1 PARITY [0:0] interrupt enable clear for parity errors - (RW ) 1 0 0 AGGR_STATUS_SET 0x208 32 AGGR interrupt status set Register RES17 [31:4] RESERVE FIELD 28 4 TIMEOUT [3:2] interrupt status set for svbus timeout errors - (RW incr) 2 2 PARITY [1:0] interrupt status set for parity errors - (RW incr) 2 0 0 AGGR_STATUS_CLR 0x20C 32 AGGR interrupt status clear Register RES18 [31:4] RESERVE FIELD 28 4 TIMEOUT [3:2] interrupt status clear for svbus timeout errors - (RW decr) 2 2 PARITY [1:0] interrupt status clear for parity errors - (RW decr) 2 0 0 APP_RTI 0x56F7F000 0 192 registers APP_RTI RTIGCTRL 0x0 32 Global Control Register starts / stops the counters RESERVED2 [31:20] Reserved. Reads return 0 and writes have no effect 12 20 NTUSEL [19:16] NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ‘0’ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ‘0’ 4 16 COS [15:15] COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode 1 15 RESERVED1 [14:2] Reserved. Reads return 0 and writes have no effect 13 2 CNT1EN [1:1] CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical). 1 1 CNT0EN [0:0] CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical). 1 0 0 RTITBCTRL 0x4 32 Timebase Control selection which source triggers free running counter 0 RESERVED3 [31:2] Reserved 30 2 INC [1:1] INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock 1 1 TBEXT [0:0] TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme 1 0 0 RTICAPCTRL 0x8 32 Capture Control controls the capture source for the counters RESERVED4 [31:2] Reserved. Reads return 0 and writes have no effect 30 2 CAPCNTR1 [1:1] CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 1 1 CAPCNTR0 [0:0] CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant 1 0 0 RTICOMPCTRL 0xC 32 Compare Control controls the source for the compare registers RESERVED8 [31:13] Reserved. Reads return 0 and writes have no effect 19 13 COMP3SEL [12:12] COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 12 RESERVED7 [11:9] Reserved. Reads return 0 and writes have no effect 3 9 COMP2SEL [8:8] COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 8 RESERVED6 [7:5] Reserved. Reads return 0 and writes have no effect 3 5 COMP1SEL [4:4] COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 4 RESERVED5 [3:1] Reserved. Reads return 0 and writes have no effect 3 1 COMP0SEL [0:0] COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 0 0 RTIFRC0 0x10 32 Free Running Counter 0 current value of free running counter 0 FRC0 [31:0] FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. 32 0 0 RTIUC0 0x14 32 Up Counter 0 current value of prescale counter 0 UC0 [31:0] UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows. 32 0 0 RTICPUC0 0x18 32 Compare Up Counter 0 compare value compared with prescale counter 0 CPUC0 [31:0] This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 ≠ 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed 32 0 0 RTICAFRC0 0x20 32 Capture Free Running Counter 0 current value of free running counter 0 on external event CAFRC0 [31:0] CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event 32 0 0 RTICAUC0 0x24 32 Capture Up Counter 0 current value of prescale counter 0 on external event CAUC0 [31:0] CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event 32 0 0 RTIFRC1 0x30 32 Free Running Counter 1 current value of free running counter 1 FRC1 [31:0] FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. 32 0 0 RTIUC1 0x34 32 Up Counter 1 current value of prescale counter 1 UC1 [31:0] UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows. 32 0 0 RTICPUC1 0x38 32 Compare Up Counter 1 compare value compared with prescale counter 1 CPUC1 [31:0] This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 ≠ 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed 32 0 0 RTICAFRC1 0x40 32 Capture Free Running Counter 1 current value of free running counter 1 on external event CAFRC1 [31:0] CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event 32 0 0 RTICAUC1 0x44 32 Capture Up Counter 1 current value of prescale counter 1 on external event CAUC1 [31:0] CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event 32 0 0 RTICOMP0 0x50 32 Compare 0 compare value to be compared with the counters COMP0 [31:0] COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP0 0x54 32 Update Compare 0 value to be added to the compare register 0 value on compare match UDCP0 [31:0] UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value 32 0 0 RTICOMP1 0x58 32 Compare 1 compare value to be compared with the counters COMP1 [31:0] COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP1 0x5C 32 Update Compare 1 value to be added to the compare register 1 value on compare match UDCP1 [31:0] UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value 32 0 0 RTICOMP2 0x60 32 Compare 2 compare value to be compared with the counters COMP2 [31:0] COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP2 0x64 32 Update Compare 2 value to be added to the compare register 2 value on compare match UDCP2 [31:0] UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value 32 0 0 RTICOMP3 0x68 32 Compare 3 compare value to be compared with the counters COMP3 [31:0] COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP3 0x6C 32 Update Compare 3 value to be added to the compare register 3 value on compare match UDCP3 [31:0] UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value 32 0 0 RTITBLCOMP 0x70 32 Timebase Low Compare compare value to activate edge detection circuit TBLCOMP [31:0] TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match. 32 0 0 RTITBHCOMP 0x74 32 Timebase High Compare compare value to deactivate edge detection circuit TBHCOMP [31:0] TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match. 32 0 0 RTISETINT 0x80 32 Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation RESERVED11 [31:19] Reserved. Reads return 0 and writes have no effect 13 19 SETOVL1INT [18:18] SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 18 SETOVL0INT [17:17] SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 17 SETTBINT [16:16] SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 16 RESERVED10 [15:12] Reserved. Reads return 0 and writes have no effect 4 12 SETDMA3 [11:11] SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 11 SETDMA2 [10:10] SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 10 SETDMA1 [9:9] SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 9 SETDMA0 [8:8] SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 8 RESERVED9 [7:4] Reserved. Reads return 0 and writes have no effect 4 4 SETINT3 [3:3] SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 3 SETINT2 [2:2] SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 2 SETINT1 [1:1] SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 1 SETINT0 [0:0] SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 0 0 RTICLEARINT 0x84 32 Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation RESERVED14 [31:19] Reserved. Reads return 0 and writes have no effect 13 19 CLEAROVL1INT [18:18] CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 18 CLEAROVL0INT [17:17] CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 17 CLEARTBINT [16:16] CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 16 RESERVED13 [15:12] Reserved. Reads return 0 and writes have no effect 4 12 CLEARDMA3 [11:11] CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 11 CLEARDMA2 [10:10] CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 10 CLEARDMA1 [9:9] CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 9 CLEARDMA0 [8:8] CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 8 RESERVED12 [7:4] Reserved. Reads return 0 and writes have no effect 4 4 CLEARINT3 [3:3] CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 3 CLEARINT2 [2:2] CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 2 CLEARINT1 [1:1] CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 1 CLEARINT0 [0:0] CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 0 0 RTIINTFLAG 0x88 32 Interrupt Flags interrupt pending bits RESERVED16 [31:19] Reserved. Reads return 0 and writes have no effect 13 19 OVL1INT [18:18] OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 18 OVL0INT [17:17] OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 17 TBINT [16:16] User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 16 RESERVED15 [15:4] Reserved. Reads return 0 and writes have no effect 12 4 INT3 [3:3] INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 3 INT2 [2:2] INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 2 INT1 [1:1] INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 1 INT0 [0:0] INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 0 0 RTIDWDCTRL 0x90 32 Digital Watchdog Control Enables the Digital Watchdog DWDCTRL [31:0] DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again. 32 0 0 RTIDWDPRLD 0x94 32 Digital Watchdog Preload sets the experation time of the Digital Watchdog RESERVED17 [31:12] Reserved. Reads return 0 and writes have no effect 20 12 DWDPRLD [11:0] DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095 12 0 0 RTIWDSTATUS 0x98 32 Watchdog Status reflects the status of Analog and Digital Watchdog RESERVED18 [31:6] Reserved. Reads return 0 and writes have no effect 26 6 DWWD_ST [5:5] DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD. 1 5 ENDTIMEVIOL [4:4] END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. 1 4 STARTTIMEVIOL [3:3] START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. 1 3 KEYST [2:2] KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0 1 2 DWDST [1:1] DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0 1 1 AWDST [0:0] AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 –> 1 threshold not exceeded 1 = AWD pin 0 –> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0 1 0 0 RTIWDKEY 0x9C 32 Watchdog Key correct written key values discharge the external capacitor RESERVED19 [31:16] Reserved. Reads return 0 and writes have no effect 16 16 WDKEY [15:0] WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1’s. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation. 16 0 0 RTIDWDCNTR 0xA0 32 Digital Watchdog Down Counter current value of DWD down counter RESERVED20 [31:25] Reserved. Reads return 0 and writes have no effect 7 25 DWDCNTR [24:0] DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don’t have an effect. 25 0 0 RTIWWDRXNCTRL 0xA4 32 Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset RESERVED21 [31:4] Reserved. Reads return 0 and writes have no effect 28 4 WWDRXN [3:0] WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced. 4 0 0 RTIWWDSIZECTRL 0xA8 32 Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog WWDSIZE [31:0] WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then 32 0 0 RTIINTCLRENABLE 0xAC 32 RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts RESERVED25 [31:28] Reserved. Reads return 0 and writes have no effect 4 28 INTCLRENABLE3 [27:24] INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt. 4 24 RESERVED24 [23:20] Reserved. Reads return 0 and writes have no effect 4 20 INTCLRENABLE2 [19:16] INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt. 4 16 RESERVED23 [15:12] Reserved. Reads return 0 and writes have no effect 4 12 INTCLRENABLE1 [11:8] INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt. 4 8 RESERVED22 [7:4] Reserved. Reads return 0 and writes have no effect 4 4 INTCLRENABLE0 [3:0] INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. 4 0 0 RTICOMP0CLR 0xB0 32 Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line COMP0CLR [31:0] COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTICOMP1CLR 0xB4 32 Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line COMP1CLR [31:0] COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTICOMP2CLR 0xB8 32 Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line COMP2CLR [31:0] COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTICOMP3CLR 0xBC 32 Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line COMP3CLR [31:0] COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 APP_WD 0x56F7F400 0 192 registers APP_WD RTIGCTRL 0x0 32 Global Control Register starts / stops the counters RESERVED2 [31:20] Reserved. Reads return 0 and writes have no effect 12 20 NTUSEL [19:16] NTUSEL: Select NTU signal. These bits determine which NTU input signal is used as external timebase. There are up to four inputs supported with four valid selection combinations. Any invalid selection value written to the NTUSEL bit-field will result in a TIED LOW being used as the NTU signal. The NTU signal will also be TIED LOW in case of a single-bit flip as it will result in an invalid combination of NTUSEL. User and privilege mode (read): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ‘0’ Privilege mode (write): 0000 = NTU0 0101 = NTU1 1010 = NTU2 1111 = NTU3 other = tied to ‘0’ 4 16 COS [15:15] COS: Continue On Suspend. This bit determines if both counters are stopped when the device goes into debug mode or if they continue counting. User and privilege mode (read): 0 = counters are stopped while in debug mode 1 = counters are running while in debug mode Privilege mode (write): 0 = stop counters in debug mode 1 = continue counting in debug mode 1 15 RESERVED1 [14:2] Reserved. Reads return 0 and writes have no effect 13 2 CNT1EN [1:1] CNT1EN: Counter 1 Enable. The CNT1EN bit starts and stops the operation of counter block 1 (UC1 and FRC1). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bit destination address (physical). 1 1 CNT0EN [0:0] CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0). User and privilege mode (read): 0 = counters are stopped 1 = counters are running Privilege mode (write): 0 = stop counters 1 = start counters Gives the absolute 32 bits source address (physical). 1 0 0 RTITBCTRL 0x4 32 Timebase Control selection which source triggers free running counter 0 RESERVED3 [31:2] Reserved 30 2 INC [1:1] INC: Increment Free Running Counter 0. This bit determines wether the Free Running Counter 0 is automatically incremented if a failing clock on the NTUx signal is detected. User and privilege mode (read): 0 = FRC0 will not be incremented 1 = FRC0 will be incremented Privilege mode (write): 0 = Do not increment FRC0 on failing external clock 1 = Increment FRC0 on failing external clock 1 1 TBEXT [0:0] TBEXT: Timebase External. The Timebase External bit selects whether the Free Running Counter 0 is clocked by the internal Up Counter 0 or from the external signal NTUx. Since setting the TBEXT bit to 1 resets Up Counter 0, Free Running Counter 0 will not be incremented in this occurence. The only source which is able to increment Free Running Counter 0 is NTUx. When the Timebase Supervisor circuit detects a missing clockedge, then the TBEXT bit is reset. The selection if the external signal should be used, can only be done by software. User and privilege mode (read): 0 = UC0 clocks FRC0 1 = NTUx clocks FRC0 Privilege mode (write): 0 = MUX is switched to internal UC0 clocking scheme 1 = MUX is switched to external NTUx clocking scheme 1 0 0 RTICAPCTRL 0x8 32 Capture Control controls the capture source for the counters RESERVED4 [31:2] Reserved. Reads return 0 and writes have no effect 30 2 CAPCNTR1 [1:1] CAPCNTR1: Capture Counter 1. This bit determines, which external interrupt source triggers a capture event of both UC1 and FRC1. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 1 1 CAPCNTR0 [0:0] CAPCNTR0: Capture Counter 0. This bit determines, which external interrupt source triggers a capture event of both UC0 and FRC0. User and privilege mode (read): 0 = capture event is triggered by Capture Event Source 0 1 = capture event is triggered by Capture Event Source 1 Privilege mode (write): 0 = enable capture event triggered by Capture Event Source 0 1 = enable capture event triggered by Capture Event Source 1 11 indexed 10 reserved 01 post-increment 00 constant 1 0 0 RTICOMPCTRL 0xC 32 Compare Control controls the source for the compare registers RESERVED8 [31:13] Reserved. Reads return 0 and writes have no effect 19 13 COMP3SEL [12:12] COMPSEL3: Compare Select 3. This bit determines the counter with which the compare value hold in compare register 3 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 12 RESERVED7 [11:9] Reserved. Reads return 0 and writes have no effect 3 9 COMP2SEL [8:8] COMPSEL2: Compare Select 2. This bit determines the counter with which the compare value hold in compare register 2 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 8 RESERVED6 [7:5] Reserved. Reads return 0 and writes have no effect 3 5 COMP1SEL [4:4] COMPSEL1: Compare Select 1. This bit determines the counter with which the compare value hold in compare register 1 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 4 RESERVED5 [3:1] Reserved. Reads return 0 and writes have no effect 3 1 COMP0SEL [0:0] COMPSEL0: Compare Select 0. This bit determines the counter with which the compare value hold in compare register 0 is compared. User and privilege mode (read): 0 = value will be compared with FRC 0 1 = value will be compared with FRC 1 Privilege mode (write): 0 = enable compare with FRC 0 1 = enable compare with FRC 1 1 0 0 RTIFRC0 0x10 32 Free Running Counter 0 current value of free running counter 0 FRC0 [31:0] FRC0: Free Running Counter 0. This registers holds the current value of the Free Running Counter 0 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. 32 0 0 RTIUC0 0x14 32 Up Counter 0 current value of prescale counter 0 UC0 [31:0] UC0: Up Counter 0. This registers holds the current value of the Up Counter 0 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 0. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 0 and Free Running Counter 0. User and privilege mode (read): value of the counter when the Free Running Counter 0 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC0 and RTIFRC0. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC0 then it can take a long time until a compare matches, since RTIUC0 has to count up until it overflows. 32 0 0 RTICPUC0 0x18 32 Compare Up Counter 0 compare value compared with prescale counter 0 CPUC0 [31:0] This registers holds the compare value, which is compared with the Up Counter 0. When the compare matches, Free Running counter 0 is incremented. The Up Counter is set to zero when the counter value matches the CPUC0 value. The value set in this prescales the RTI clock. If CPUC0 = 0: then, frequency = RTICLK/ (2^32) If CPUC0 ≠ 0: then , frequency = RTICLK/(CPUC0 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed 32 0 0 RTICAFRC0 0x20 32 Capture Free Running Counter 0 current value of free running counter 0 on external event CAFRC0 [31:0] CAFRC0: Capture Free Running Counter 0. This registers captures the current value of the Free Running Counter 0 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 0 on a capture event 32 0 0 RTICAUC0 0x24 32 Capture Up Counter 0 current value of prescale counter 0 on external event CAUC0 [31:0] CAUC0: Capture Up Counter 0. This registers captures the current value of the Up Counter 0 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 0 and Free Running Counter 0. So the RTICAFRC0 register has to be read first, before the RTICAUC0 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 0 on a capture event 32 0 0 RTIFRC1 0x30 32 Free Running Counter 1 current value of free running counter 1 FRC1 [31:0] FRC1: Free Running Counter 1. This registers holds the current value of the Free Running Counter 1 and will be updated continuously. User and privilege mode (read): current value of the counter Privilege mode (write): The counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. 32 0 0 RTIUC1 0x34 32 Up Counter 1 current value of prescale counter 1 UC1 [31:0] UC1: Up Counter 1. This registers holds the current value of the Up Counter 1 and prescales the RTI clock. It will be only updated by a previous read of Free Running Counter 1. This gives effectively a 64 bit read of both counters, without having the problem of a counter being updated between two consecutive reads on Up Counter 1 and Free Running Counter 1. User and privilege mode (read): value of the counter when the Free Running Counter 1 was read Privilege mode (write): the counter can be preset by writing to this register. The counter increments then from this written value upwards. Note: Presetting counters If counters have to be preset, they have to be stopped from counting in the RTIGCTRL register in order to ensure consistency between RTIUC1 and RTIFRC1. Note: Preset value concern If the preset value is bigger than the compare value stored in register RTICPUC1 then it can take a long time until a compare matches, since RTIUC1 has to count up until it overflows. 32 0 0 RTICPUC1 0x38 32 Compare Up Counter 1 compare value compared with prescale counter 1 CPUC1 [31:0] This registers holds the compare value, which is compared with the Up Counter 1. When the compare matches, Free Running Counter 1 is incremented. The Up Counter is set to zero when the counter value matches the CPUC1 value. The value set in this prescales the RTI clock. If CPUC1 = 0: then, frequency = RTICLK/ (2^32) If CPUC1 ≠ 0: then , frequency = RTICLK/(CPUC1 + 1) User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed 32 0 0 RTICAFRC1 0x40 32 Capture Free Running Counter 1 current value of free running counter 1 on external event CAFRC1 [31:0] CAFRC1: Capture Free Running Counter 1. This registers captures the current value of the Free Running Counter 1 when a event occurs, controlled by the external capture control block. User and privilege mode (read): value of Free Running Counter 1 on a capture event 32 0 0 RTICAUC1 0x44 32 Capture Up Counter 1 current value of prescale counter 1 on external event CAUC1 [31:0] CAUC1: Capture Up Counter 1. This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC1 register is the corresponding value to the RTICAFRC1 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event 32 0 0 RTICOMP0 0x50 32 Compare 0 compare value to be compared with the counters COMP0 [31:0] COMP0: Compare 0. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP0 0x54 32 Update Compare 0 value to be added to the compare register 0 value on compare match UDCP0 [31:0] UDCP0: Update Compare 0 Register. This registers holds a value, which is added to the value in the compare 0 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 0 register on the next compare match Privilege mode (write): new update value 32 0 0 RTICOMP1 0x58 32 Compare 1 compare value to be compared with the counters COMP1 [31:0] COMP1: compare1. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP1 0x5C 32 Update Compare 1 value to be added to the compare register 1 value on compare match UDCP1 [31:0] UDCP1: Update compare1 Register. This registers holds a value, which is added to the value in the compare1 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare1 register on the next compare match Privilege mode (write): new update value 32 0 0 RTICOMP2 0x60 32 Compare 2 compare value to be compared with the counters COMP2 [31:0] COMP2: compare 2. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP2 0x64 32 Update Compare 2 value to be added to the compare register 2 value on compare match UDCP2 [31:0] UDCP2: Update compare 2 Register. This registers holds a value, which is added to the value in the compare 2 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 2 register on the next compare match Privilege mode (write): new update value 32 0 0 RTICOMP3 0x68 32 Compare 3 compare value to be compared with the counters COMP3 [31:0] COMP3: compare 3. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, an interrupt is flagged. With this register it is also possible to initiate a DMA request. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTIUDCP3 0x6C 32 Update Compare 3 value to be added to the compare register 3 value on compare match UDCP3 [31:0] UDCP3: Update compare 3 Register. This registers holds a value, which is added to the value in the compare 3 register each time a compare matches. This gives the possibility to generate periodic interrupts without software intervention. User and privilege mode (read): value to be added to the compare 3 register on the next compare match Privilege mode (write): new update value 32 0 0 RTITBLCOMP 0x70 32 Timebase Low Compare compare value to activate edge detection circuit TBLCOMP [31:0] TBLCOMP: Timebase Low Compare Value. This value determines when the edge detection circuit starts monitoring the NTUx signal. It will be compared with Up Counter 0. User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match. 32 0 0 RTITBHCOMP 0x74 32 Timebase High Compare compare value to deactivate edge detection circuit TBHCOMP [31:0] TBHCOMP: Timebase High Compare Value. This value determines when the edge detection circuit will stop monitoring the NTUx signal. It will be compared with Up Counter 0. RTITBHCOMP has to be less than RTICPUC0, since RTIUC0 will be reset when RTICPUC0 is reached. Example: The NTUx edge detection circuit should be active +/- 10 RTICLK cycles around RTICPUC0. RTICPUC0 = 0x00000050 RTITBLCOMP = 0x000046 RTITBHCOMP = 0x00000009 User and privilege mode (read): current compare value Privilege mode (write when TBEXT = 0): the compare value is updated Privilege mode (write when TBEXT = 1): the compare value is not changed Note: Reset behavior A reset does not generate a compare match. 32 0 0 RTISETINT 0x80 32 Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation RESERVED11 [31:19] Reserved. Reads return 0 and writes have no effect 13 19 SETOVL1INT [18:18] SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 18 SETOVL0INT [17:17] SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 17 SETTBINT [16:16] SETTBINT: Set Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 16 RESERVED10 [15:12] Reserved. Reads return 0 and writes have no effect 4 12 SETDMA3 [11:11] SETDMA3: Set Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 11 SETDMA2 [10:10] SETDMA2: Set Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 10 SETDMA1 [9:9] SETDMA1: Set Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 9 SETDMA0 [8:8] SETDMA0: Set Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 8 RESERVED9 [7:4] Reserved. Reads return 0 and writes have no effect 4 4 SETINT3 [3:3] SETINT3: Set Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 3 SETINT2 [2:2] SETINT2: Set Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 2 SETINT1 [1:1] SETINT1: Set Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 1 SETINT0 [0:0] SETINT0: Set Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 0 0 RTICLEARINT 0x84 32 Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation RESERVED14 [31:19] Reserved. Reads return 0 and writes have no effect 13 19 CLEAROVL1INT [18:18] CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 18 CLEAROVL0INT [17:17] CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 17 CLEARTBINT [16:16] CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 16 RESERVED13 [15:12] Reserved. Reads return 0 and writes have no effect 4 12 CLEARDMA3 [11:11] CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 11 CLEARDMA2 [10:10] CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 10 CLEARDMA1 [9:9] CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 9 CLEARDMA0 [8:8] CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 8 RESERVED12 [7:4] Reserved. Reads return 0 and writes have no effect 4 4 CLEARINT3 [3:3] CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 3 CLEARINT2 [2:2] CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 2 CLEARINT1 [1:1] CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 1 CLEARINT0 [0:0] CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 0 0 RTIINTFLAG 0x88 32 Interrupt Flags interrupt pending bits RESERVED16 [31:19] Reserved. Reads return 0 and writes have no effect 13 19 OVL1INT [18:18] OVL1INT: Free Running Counter 1 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 18 OVL0INT [17:17] OVL0INT: Free Running Counter 0 Overflow Interrupt Flag. User and privilege mode (read): determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 17 TBINT [16:16] User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge. It will not be set by clearing TBEXT by software. determines if an interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 16 RESERVED15 [15:4] Reserved. Reads return 0 and writes have no effect 12 4 INT3 [3:3] INT3: Interrupt Flag 3. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 3 INT2 [2:2] INT2: Interrupt Flag 2. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 2 INT1 [1:1] INT1: Interrupt Flag 1. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 1 INT0 [0:0] INT0: Interrupt Flag 0. User and privilege mode (read): determines if a interrupt is pending 0 = no interrupt pending 1 = interrupt pending Privilege mode (write): 0 = leaves the bit unchanged 1 = set the bit to 0 1 0 0 RTIDWDCTRL 0x90 32 Digital Watchdog Control Enables the Digital Watchdog DWDCTRL [31:0] DWDCTRL: Digital Watchdog Control. User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again. 32 0 0 RTIDWDPRLD 0x94 32 Digital Watchdog Preload sets the experation time of the Digital Watchdog RESERVED17 [31:12] Reserved. Reads return 0 and writes have no effect 20 12 DWDPRLD [11:0] DWDPRLD: Digital Watchdog Preload Value. User and priviledge mode (read): A read from this register in any CPU mode returns the current preload value. Priviledge mode (write): If the DWD is always enabled after reset is released: The DWD starts counting down from the reset value of the counter, that is, 0x002DFFFF. The application can configure the DWD preload register any time before this down counter expires. When the application services the DWD, the preload register contents are copied left-justified into the DWD down counter and it starts counting down from that value. If the DWD is implemented such that the down counter is enabled by software: The DWD preload register can be configured only when the DWD is disabled. Therefore, the application can only configure the DWD preload register before it enables the DWD down counter. The expiration time of the DWD Down Counter can be determined with following equation: texp = (RTIDWDPRLD+1) x 2 ^ 13 / RTICLK1 where: RTIDWDPRLD = 0...4095 12 0 0 RTIWDSTATUS 0x98 32 Watchdog Status reflects the status of Analog and Digital Watchdog RESERVED18 [31:6] Reserved. Reads return 0 and writes have no effect 26 6 DWWD_ST [5:5] DWWD ST: Windowed Watchdog Status. This bit denotes whether the time-window defined by the windowed watchdog configuration has been violated, or if a wrong key or key sequence was written to service the watchdog. User and priviledge mode (read): 0 = no time-window violation has occurred. 1 = a time-window violation has occurred. The watchdog will generate either a system reset or a non-maskable interrupt to the CPU in this case. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. This will also clear all other status flags in the RTIWDSTATUS register except for the AWD ST flag. Clearing of the status flags will deassert the non-maskable interrupt generated due to violation of the DWWD. 1 5 ENDTIMEVIOL [4:4] END TIME VIOL: Windowed Watchdog End Time Violation Status. This bit denotes whether the end-time defined by the windowed watchdog configuration has been violated. This bit is effectively a copy of the DWD ST status flag. User and priviledge mode (read): 0 = no end-time window violation has occurred. 1 = the end-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. 1 4 STARTTIMEVIOL [3:3] START TIME VIOL: Windowed Watchdog Start Time Violation Status. This bit denotes whether the start-time defined by the windowed watchdog configuration has been violated. This indicates that the WWD was serviced before the service window was opened. User and priviledge mode (read): 0 = no start-time window violation has occurred. 1 = the start-time defined by the windowed watchdog configuration has been violated. Priviledge mode (write): 0 = leaves the current value unchanged. 1 = clears the bit to 0. 1 3 KEYST [2:2] KEYST: Watchdog KeyStatus. This bit denotes a reset generated by a wrong key or a wrong key-sequence written to the RTIWDKEY register. User and priviledge mode (read): 0 = no wrong key or key-sequence written 1 = wrong key or key-sequence written to RTIWDKEY register Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0 1 2 DWDST [1:1] DWDST: Digital Watchdog Status. This bit is effectively a copy of the END TIME VIOL status flag and is maintained for compatibility reasons. User and priviledge mode (read): 0 = DWD timeout period not expired 1 = DWD timeout period has expired Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0 1 1 AWDST [0:0] AWDST: Analog Watchdog Status. User and priviledge mode (read): 0 = AWD pin 0 –> 1 threshold not exceeded 1 = AWD pin 0 –> 1 threshold exceeded Priviledge mode (write): 0 = leaves the current value unchanged 1 = clears the bit to 0 1 0 0 RTIWDKEY 0x9C 32 Watchdog Key correct written key values discharge the external capacitor RESERVED19 [31:16] Reserved. Reads return 0 and writes have no effect 16 16 WDKEY [15:0] WDKEY: Watchdog Key. User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1’s. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation. 16 0 0 RTIDWDCNTR 0xA0 32 Digital Watchdog Down Counter current value of DWD down counter RESERVED20 [31:25] Reserved. Reads return 0 and writes have no effect 7 25 DWDCNTR [24:0] DWDCNTR: Digital Watchdog Down Counter. The value of the DWDCNTR after a system reset is 0x002D_FFFF. When the DWD is enabled and the DWD counter starts counting down from this value with an RTICLK1 time base of 3MHz, a watchdog reset will be generated in 1 second. User and privilege mode (read): Reads return the current counter value. Privilege mode (write): Writes don’t have an effect. 25 0 0 RTIWWDRXNCTRL 0xA4 32 Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset RESERVED21 [31:4] Reserved. Reads return 0 and writes have no effect 28 4 WWDRXN [3:0] WWDRXN: Digital Windowed Watchdog Reaction. User and privilege mode (read), privileged mode (write): 0x5 = This is the default value. The windowed watchdog will cause a reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. 0xA = The windowed watchdog will generate a non-maskable interrupt to the CPU if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Writing any other value will cause a system reset if the watchdog is serviced outside the time window defined by the configuration, or if the watchdog is not serviced at all. Note: Configuration of DWWD Reaction The DWWD reaction can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDRXN is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDRXN is made when the watchdog service window is already open, then the change in configuration takes effect only after the watchdog is serviced. 4 0 0 RTIWWDSIZECTRL 0xA8 32 Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog WWDSIZE [31:0] WWDSIZE: Digital Windowed Watchdog Window Size. User and privilege mode (read), privileged mode (write): Value written to WWDSIZE Window Size 0x00000005 100% (Functionality same as the time-out digital watchdog.) 0x00000050 50% 0x00000500 25% 0x00005000 12.5% 0x00050000 6.25% 0x00500000 3.125% Any other value 3.125% Note: Incorrect value being written to watchdog window size control register If an incorerct value is written to the WWDSIZE field, or if a system disturbance causes the WWDSIZE field to have a value other than 0x5, 0x50, 0x500, 0x5000, 0x50000, or 0x500000, then the window size will be configured to be 3.125%. This increases the chances of getting a reset due to the windowed watchdog, which enables the system to handle the cause for the incorrect configuration. Note: Configuration of DWWD Window Size The DWWD window size can be selected by the application even when the DWWD counter is already enabled. If a change to the WWDSIZE is made before the watchdog service window is opened, then the change in the configuration takes effect immediately. If a change to the WWDSIZE is made when the watchdog service window is already open, then 32 0 0 RTIINTCLRENABLE 0xAC 32 RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts RESERVED25 [31:28] Reserved. Reads return 0 and writes have no effect 4 28 INTCLRENABLE3 [27:24] INTCLRENABLE3. Enables the auto-clear functionality on the compare 3 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 3 interrupt is disabled. Any other value = Auto-clear for compare 3 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 3 interrupt. Any other value = Enables the auto-clear functionality on the compare 3 interrupt. 4 24 RESERVED24 [23:20] Reserved. Reads return 0 and writes have no effect 4 20 INTCLRENABLE2 [19:16] INTCLRENABLE2. Enables the auto-clear functionality on the compare 2 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 2 interrupt is disabled. Any other value = Auto-clear for compare 2 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 2 interrupt. Any other value = Enables the auto-clear functionality on the compare 2 interrupt. 4 16 RESERVED23 [15:12] Reserved. Reads return 0 and writes have no effect 4 12 INTCLRENABLE1 [11:8] INTCLRENABLE1. Enables the auto-clear functionality on the compare 1 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 1 interrupt is disabled. Any other value = Auto-clear for compare 1 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 1 interrupt. Any other value = Enables the auto-clear functionality on the compare 1 interrupt. 4 8 RESERVED22 [7:4] Reserved. Reads return 0 and writes have no effect 4 4 INTCLRENABLE0 [3:0] INTCLRENABLE0. Enables the auto-clear functionality on the compare 0 interrupt. User and Privileged mode (read): 0x5 = Auto-clear for compare 0 interrupt is disabled. Any other value = Auto-clear for compare 0 interrupt is enabled. Privileged mode (write): 0x5 = Disables the auto-clear functionality on the compare 0 interrupt. Any other value = Enables the auto-clear functionality on the compare 0 interrupt. 4 0 0 RTICOMP0CLR 0xB0 32 Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line COMP0CLR [31:0] COMP0CLR: Compare 0 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the compare 0 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTICOMP1CLR 0xB4 32 Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line COMP1CLR [31:0] COMP1CLR: Compare 1 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 1 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTICOMP2CLR 0xB8 32 Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line COMP2CLR [31:0] COMP2CLR: Compare 2 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 2 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 RTICOMP3CLR 0xBC 32 Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line COMP3CLR [31:0] COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode (read): current compare value Privilege mode (write): update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. 32 0 0 APP_DCC 0x56F7F800 0 59 registers APP_DCC DCCGCTRL 0x0 32 Starts / stops the counters clears the error signal NU [31:16] Reserved 16 16 DONENA [15:12] The DONEENA bit enables/disables the done signal. 0101 = disabled & 1010 = enabled 4 12 SINGLESHOT [11:8] Single/Continuous checking mode. 0101 = Continuous & 1010 = Single 4 8 ERRENA [7:4] The ERRENA bit enables/disables the error signal. 0101 = disabled & 1010 = enabled 4 4 DCCENA [3:0] The DCCENA bit starts and stops the operation of the dcc 0101 = disabled & 1010 = enabled 4 0 0 DCCREV 0x4 32 Module version SCHEME [31:30] SCHEME. - (RO ) 2 30 NU1 [29:28] Reserved 2 28 FUNC [27:16] Functional release number - (RO ) 12 16 RTL [15:11] Design Release Number - (RO ) 5 11 MAJOR [10:8] Major Revision Number - (RO ) 3 8 CUSTOM [7:6] Indicates a special version of the module. May not be supported by standard software - (RO ) 2 6 MINOR [5:0] Minor revision number. - (RO ) 6 0 0 DCCCNTSEED0 0x8 32 Seed value for the counter attached to clock source 0 NU3 [31:20] Reserved 12 20 COUNTSEED0 [19:0] The seed value for Counter 0. The seed value that gets loaded into counter 0 (clock source 0) 20 0 0 DCCVALIDSEED0 0xC 32 Seed value for the timeout counter attached to clock source 0 NU4 [31:16] Reserved 16 16 VALIDSEED0 [15:0] The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0 16 0 0 DCCCNTSEED1 0x10 32 Seed value for the counter attached to clock source 1 NU5 [31:20] Reserved 12 20 COUNTSEED1 [19:0] The seed value for Counter 1. The seed value that gets loaded into counter 1 (clock source 1 20 0 0 DCCSTAT 0x14 32 Contains the error & done flag bit NU6 [31:2] Reserved 30 2 DONE [1:1] Indicates whether or not an done has occured. Writing a 1 to this bit clears the flag. 1 1 ERR [0:0] Indicates whether or not an error has occured. Writing a 1 to this bit clears the flag. 1 0 0 DCCCNT0 0x18 32 Value of the counter attached to clock source 0 NU7 [31:20] Reserved 12 20 COUNT0 [19:0] This field contains the current value of counter 0. - (RO ) 20 0 0 DCCVALID0 0x1C 32 Value of the valid counter attached to clock source 0 NU8 [31:16] Reserved 16 16 VALID0 [15:0] This field contains the current value of valid counter 0. - (RO ) 16 0 0 DCCCNT1 0x20 32 Value of the counter attached to clock source 1 NU9 [31:20] Reserved 12 20 COUNT1 [19:0] This field contains the current value of counter 1. - (RO ) 20 0 0 DCCCLKSSRC1 0x24 32 Clock source1 selection control NU11 [31:16] Reserved 16 16 KEY_B4 [15:12] Key Programing (1010 is the KEY Value) 4 12 NU10 [11:4] Reserved 8 4 CLK_SRC1 [3:0] RCOSC Input1_clksrc[10] CANFD_GCM Input1_clksrc[9] APPSS_GCM Input1_clksrc[8] OSC_CLK Input1_clksrc[7] LIN_CLK Input1_clksrc[6] MDLL_CLK Input1_clksrc[5] SYNTH_CLK Input1_clksrc[4] RAMPGEN/DFE CLK Input1_clksrc[3] GPADC CLK Input1_clksrc[2] FECSS_GCM Input1_clksrc[1] fast_clk(muxed apll and pll_dig_clk )(root mux) Input1_clksrc[0] 4 0 0 DCCCLKSSRC0 0x28 32 Clock source0 selection control NU13 [31:16] Reserved 16 16 KEY_B4 [15:12] Key Programing (1010 is the KEY Value) 4 12 NU12 [11:4] Reserved 8 4 CLK_SRC0 [3:0] APLL clock 400MHz Input0_clksrc[2] PLL_DIG clock 400MHz Input0_clksrc[1] OSC_CLK Input0_clksrc[0] 4 0 0 DCCGCTRL2 0x30 32 Global control register 2 NU13 20 12 FIFO_NONERR [11:8] FIFO update on Non-Error Enables/disables FIFO writes without the error event on completion of comparison window. 0101: Counter values are captured to non-full FIFO only upon Error event Others: Write counter values to non-full FIFO upon completion of comparison window regardless of error or not. Note this setting is applicable only in Continuous mode; in single shot mode FIFO captures counts only on Error. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors. 4 8 FIFO_READ [7:4] FIFO Read Enable Enables the counter read registers reflect FIFO output instead of live counter value. 0101: Counter value is read directly. Others: FIFO output is read Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors. 4 4 CONT_ON_ERR [3:0] Continue on Error enable Continues to next window of comparison despite the error condition. 0101: Comparison and counter reload is stopped from advancing if error is detected. Others: Counters get reloaded with seed and continue counting despite the error condition. Note: The user should write 1010 to these enable fields to enable each feature to avoid single soft errors. 4 0 0 DCCSTATUS2 0x34 32 FIFO status register NU14 [31:6] Reserved 26 6 COUNT1_FIFO_FULL [5:5] Count1 FIFO Full Indicates whether Count1 FIFO is Full. 0: Count1 FIFO is not Full 1: Count1 FIFO is Full. 1 5 VALID0_FIFO_FULL [4:4] Valid0 FIFO Full Indicates whether Valid0 FIFO is Full. 0: Valid0 FIFO is not Full 1: Valid0 FIFO is Full. 1 4 COUNT0_FIFO_FULL [3:3] Count0 FIFO Full Indicates whether Count0 FIFO is Full. 0: Count0 FIFO is not Full 1: Count0 FIFO is Full. 1 3 COUNT1_FIFO_EMPTY [2:2] Count1 FIFO Empty Indicates whether Count1 FIFO is Empty. 0: Count1 FIFO is not empty 1: Count1 FIFO is empty. 1 2 VALID0_FIFO_EMPTY [1:1] Valid0 FIFO Empty Indicates whether Valid0 FIFO is Empty. 0: Valid0 FIFO is not empty 1: Valid0 FIFO is empty. 1 1 COUNT0_FIFO_EMPTY [0:0] Count0 FIFO Empty Indicates whether Count0 FIFO is Empty. 0: Count0 FIFO is not empty 1: Count0 FIFO is empty. 1 0 0 DCCERRCNT 0x38 32 Error count register NU15 [31:10] Reserved 22 10 ERRCNT [9:0] Counts the number of errors after the last write to this register or reset. If reached terminal count the count freezes. User needs to clear it. 10 0 0 APP_ESM 0x56F7FC00 0 220 registers APP_ESM ESMIEPSR1 0x0 32 ESM Enable ERROR Pin Action/Response Register 1 IEPSET [31:0] Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR1 register. 32 0 0 ESMIEPCR1 0x4 32 ESM Disable ERROR Pin Action/Response Register 1 IEPCLR [31:0] Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR1 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR1 register. 32 0 0 ESMIESR1 0x8 32 ESM Interrupt Enable Set/Status Register 1 INTENSET [31:0] Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register. 32 0 0 ESMIECR1 0xC 32 ESM Interrupt Enable Clear/Status Register 1 INTENCLR [31:0] Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register. 32 0 0 ESMILSR1 0x10 32 Interrupt Level Set/Status Register 1 INTLVLSET [31:0] Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR1 register. 32 0 0 ESMILCR1 0x14 32 Interrupt Level Clear/Status Register 1 INTLVLCLR [31:0] Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR1 register. 32 0 0 ESMSR1 0x18 32 ESM Status Register 1 ESF [31:0] Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called. 32 0 0 ESMSR2 0x1C 32 ESM Status Register 2 ESF [31:0] Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. ESMSSR2 is not impacted by this action. Note: In normal operation the flag gets cleared when reading the appropriate vector in the ESMIOFFHR offset register. Reading ESMIOFFHR will not clear the ESMSR1 and the shadow register ESMSSR2. 32 0 0 ESMSR3 0x20 32 ESM Status Register 3 ESF [31:0] Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit. 32 0 0 ESMEPSR 0x24 32 ESM ERROR Pin Status Register RESERVED [31:1] Read returns 0. Writes have no effect. 31 1 EPSF [0:0] ERROR Pin Status Flag. Provides status information for the ERROR Pin. Read/Write in User and Privileged mode. 0 Read: ERROR Pin is low (active) if any error has occurred. Write: Writes have no effect. 1 Read: ERROR Pin is high if no error has occurred. Write: Writes have no effect. Note: This flag will be set to 1 after PORRST. The value will be unchanged after nRST. The ERROR pin status remains un-changed during after nRST. 1 0 0 ESMIOFFHR 0x28 32 ESM Interrupt Offset High Register RESERVED [31:9] Read returns 0. Writes have no effect. 23 9 INTOFFH [8:0] Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the high level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 0, error Group2. ... 40h Interrupt pending for channel 31, error Group2. 41h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not clear ESMSR1 and ESMSSR2 and the offset register gets updated. User and privileged mode (write): Writes have no effect. 9 0 0 ESMIOFFLR 0x2C 32 ESM Interrupt Offset Low Register RESERVED [31:8] Read returns 0. Writes have no effect. 24 8 INTOFFL [7:0] Offset Low Level Interrupt. This vector gives the channel number of the highest pending interrupt request for the low level interrupt line. Inside a group, channel 0 has highest priority and channel 31 has lowest priority. User and privileged mode (read): Returns number of pending interrupt with the highest priority for the low level interrupt line. 0 No pending interrupt. 1h Interrupt pending for channel 0, error Group1. ... 20h Interrupt pending for channel 31, error Group1. 21h Interrupt pending for channel 32, error Group1. ... 60h Interrupt pending for channel 63, error Group1. Note: Reading the interrupt vector will not clear the corresponding flag in the ESMSR1 register. Group2 interrupts are fixed to the high level interrupt line only. User and privileged mode (write): Writes have no effect. 8 0 0 ESMLTCR 0x30 32 ESM Low-Time Counter Register RESERVED [31:16] Read returns 0. Writes have no effect. 16 16 LTCP [15:0] ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin. The low-time counter is triggered by the peripheral clock (VCLK). Note: Low time counter is set to the default preload value of the ESMLTCPR in the following cases: 1. Reset (power on reset or warm reset) 2. An error occurs 3. User forces an error 16 0 0 ESMLTCPR 0x34 32 ESM Low-Time Counter Preload Register RESERVED [31:16] Read returns 0. Writes have no effect. 16 16 LTCP [15:0] ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter. Note: Only LTCP.15 and LTCP.14 are configurable (privileged mode write). 16 0 0 ESMEKR 0x38 32 ESM Error Key Register RESERVED [31:4] Read returns 0. Writes have no effect. 28 4 EKEY [3:0] Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. User and privileged mode (read): Returns current value of the EKEY. Privileged mode (write): 0 Activates normal mode (recommended default mode). Ah Forces error on ERROR pin. 5h The ERROR pin set to high when the low time counter (LTC) has completed; then the EKEY bit will switch back to normal mode (EKEY = 0000) All other values Activates normal mode. 4 0 0 ESMSSR2 0x3C 32 ESM Status Shadow Register 2 ESF [31:0] Error Status Flag. Shadow register for status information on pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred. Write: Leaves the bit unchanged. 1 Read: Error occurred. Write: Clears the bit. ESMSR2 is not impacted by this action. Note: Errors are stored until they are cleared by the software or at power-on reset (PORRST). 32 0 0 ESMIEPSR4 0x40 32 ESM Enable ERROR Pin Action/Response Register 4 IEPSET [31:0] Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR4 register. 32 0 0 ESMIEPCR4 0x44 32 ESM Disable ERROR Pin Action/Response Register 4 IEPCLR [31:0] Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR4 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR4 register. 32 0 0 ESMIESR4 0x48 32 ESM Interrupt Enable Set/Status Register 4 INTENSET [31:0] Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR4 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR4 register. 32 0 0 ESMIECR4 0x4C 32 ESM Interrupt Enable Clear/Status Register 4 INTENCLR [31:0] Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR4 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR4 register. 32 0 0 ESMILSR4 0x50 32 Interrupt Level Set/Status Register 4 INTLVLSET [31:0] Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR4 register. 32 0 0 ESMILCR4 0x54 32 Interrupt Level Clear/Status Register 4 INTLVLCLR [31:0] Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR4 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR4 register. 32 0 0 ESMSR4 0x58 32 ESM Status Register 4 ESF [31:0] Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called. 32 0 0 ESMIEPSR7 0x80 32 ESM Enable ERROR Pin Action/Response Register 7 IEPSET [31:0] Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR7 register. 32 0 0 ESMIEPCR7 0x84 32 ESM Disable ERROR Pin Action/Response Register 7 IEPCLR [31:0] Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR7 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR7 register. 32 0 0 ESMIESR7 0x88 32 ESM Interrupt Enable Set/Status Register 7 INTENSET [31:0] Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR7 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR7 register. 32 0 0 ESMIECR7 0x8C 32 ESM Interrupt Enable Clear/Status Register 7 INTENCLR [31:0] Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR7 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR7 register. 32 0 0 ESMILSR7 0x90 32 Interrupt Level Set/Status Register 7 INTLVLSET [31:0] Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR7 register. 32 0 0 ESMILCR7 0x94 32 Interrupt Level Clear/Status Register 7 INTLVLCLR [31:0] Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR7 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR7 register. 32 0 0 ESMSR7 0x98 32 ESM Status Register 7 ESF [31:0] Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called. 32 0 0 ESMIEPSR10 0xC0 32 ESM Enable ERROR Pin Action/Response Register 10 IEPSET [31:0] Enable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding clear bit in the ESMIEPCR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Enables failure influence on ERROR pin and sets the corresponding clear bit in the ESMIEPCR10 register. 32 0 0 ESMIEPCR10 0xC4 32 ESM Disable ERROR Pin Action/Response Register 10 IEPCLR [31:0] Disable ERROR Pin Action/Response on Group 1. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Failure on channel x has no influence on ERROR pin. Write: Leaves the bit and the corresponding set bit in the ESMIEPSR10 register unchanged. 1 Read: Failure on channel x has influence on ERROR pin. Write: Disables failure influence on ERROR pin and clears the corresponding set bit in the ESMIEPSR10 register. 32 0 0 ESMIESR10 0xC8 32 ESM Interrupt Enable Set/Status Register 10 INTENSET [31:0] Set interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding clear bit in the ESMIECR10 register unchanged. 1 Read: Interrupt is enabled. Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR10 register. 32 0 0 ESMIECR10 0xCC 32 ESM Interrupt Enable Clear/Status Register 10 INTENCLR [31:0] Clear Interrupt Enable Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt is disabled. Write: Leaves the bit and the corresponding set bit in the ESMIESR10 register unchanged. 1 Read: Interrupt is enabled. Write: Disables interrupt and clears the corresponding set bit in the ESMIESR10 register. 32 0 0 ESMILSR10 0xD0 32 Interrupt Level Set/Status Register 10 INTLVLSET [31:0] Set Interrupt Priority Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding clear bit in the ESMILCR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in the ESMILCR10 register. 32 0 0 ESMILCR10 0xD4 32 Interrupt Level Clear/Status Register 10 INTLVLCLR [31:0] Clear Interrupt Priority. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: Interrupt of channel x is mapped to low level interrupt line. Write: Leaves the bit and the corresponding set bit in the ESMILSR10 register unchanged. 1 Read: Interrupt of channel x is mapped to high level interrupt line. Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in the ESMILSR10 register. 32 0 0 ESMSR10 0xD8 32 ESM Status Register 10 ESF [31:0] Error Status Flag. Provides status information on a pending error. Read in User and Privileged mode. Write in Privileged mode only. 0 Read: No error occurred; no interrupt is pending. Write: Leaves the bit unchanged. 1 Read: Error occurred; interrupt is pending. Write: Clears the bit. Note: After nRST, if one of these flags are set and the corresponding interrupt are enabled, the interrupt service routine will be called. 32 0 0 APP_UART_1 0x57F7F000 0 148 registers APP_UART SCIGCR0 0x0 32 The SCIGCR0 register defines the module reset RESERVED [31:1] Reserved 31 1 RESET [0:0] GIO reset 1 0 0 SCIGCR1 0x4 32 The SCIGCR1 register defines the frame format, protocol, and communication mode used by the SCI RESERVED4 [31:26] Reserved 6 26 TXENA [25:25] Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set 1 25 RXENA [24:24] Allows the receiver to transfer data from the shift buffer to the receive buffer 1 24 RESERVED3 [23:18] Reserved 6 18 CONT [17:17] This bit has an effect only when a program is being debugged with an emulator, and it determines how the SCI operates when the program is suspended 1 17 LOOP_BACK [16:16] Enable bit for loopback mode 1 16 RESERVED2 [15:10] Reserved 6 10 POWERDOWN [9:9] When the POWERDOWN bit is set, the SCI attempts to enter local low-power mode 1 9 SLEEP [8:8] In a multiprocessor configuration, this bit controls the receive sleep function. Clearing this bit brings the SCI out of sleep mode 1 8 SW_nRESET [7:7] Software reset (active low) 1 7 RESERVED1 [6:6] Reserved 1 6 CLOCK [5:5] SCI internal clock enable 1 5 STOP [4:4] SCI number of stop bits 1 4 PARITY [3:3] SCI parity odd/even selection 1 3 PARITY_ENA [2:2] SCI parity enable 1 2 TIMING_MODE [1:1] SCI timing mode bit (0=Isosynchronous timing,1=Asynchronous timing) 1 1 COMM_MODE [0:0] SCI communication mode bit (0=Idle-line mode, 1=Address-bit mode) 1 0 0 RESERVED1 0x8 32 Reserved RESERVED [31:0] Reserved 32 0 0 SCISETINT 0xC 32 SCI Set Interrupt Register RESERVED4 [31:27] Reserved 5 27 SET_FE_INT [26:26] Set Framing-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 26 SET_OE_INT [25:25] Set Overrun-Error Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 25 SET_PE_INT [24:24] Set Parity Interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 24 RESERVED3 [23:19] Reserved 5 19 SET_RX_DMA_ALL [18:18] Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames) 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request for address and data frames 1 18 SET_RX_DMA [17:17] To select receiver DMA requests, this bit must be set. If it is cleared, interrupt requests are generated depending on bit SCISETINT.9 User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request 1 17 SET_TX_DMA [16:16] To select DMA requests for the transmitter, this bit must be set. If it is cleared, interrupt requests are generated depending on SET TX INT bit (SCISETINT.8) User and privilege mode (read): 0 = TX interrupt request selected 1 = TX DMA request selected User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 16 RESERVED2 [15:10] Reserved 6 10 SET_RX_INT [9:9] Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 9 SET_TX_INT [8:8] Set Transmitter interrupt. Setting this bit enables the SCI to generate a transmit interrupt as data is being transferred from SCITD to SCITXSHF and the TXRDY bit is being set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 8 RESERVED1 [7:2] Reserved 6 2 SET_WAKEUP_INT [1:1] Set Wake-up interrupt User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 1 SET_BRKDT_INT [0:0] Set Break-detect interrupt. Setting this bit enables the SCI to generate an error interrupt if a break condition is detected on the SCIRX pin. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 0 0 SCICLEARINT 0x10 32 SCI Clear Interrupt Register RESERVED4 [31:27] Reserved 5 27 CLR_FE_INT [26:26] Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 26 CLR_OE_INT [25:25] Clear Overrun-Error Interrupt. This bit disables the SCI overrun interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 25 CLR_PE_INT [24:24] Clear Parity Interrupt. Setting this bit disables the SCI Parity error interrupt. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt 1 24 RESERVED3 [23:19] Reserved 5 19 CLR_RX_DMA_ALL [18:18] User and privilege mode (read): 0 = DMA request is disabled for address frames (RX interrupt request is enabled for address frames). DMA request is enabled for data frames. 1 = DMA request is enabled for address and data frames User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request for address frames 1 18 CLR_RX_DMA [17:17] Clear RX DMA request. This bit disalbes the receive DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 17 CLR_TX_DMA [16:16] Clear TX DMA request. This bit disables the transmit DMA request when set. User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable DMA request 1 16 RESERVED2 [15:10] Reserved 6 10 CLR_RX_INT [9:9] Clear Receiver interrupt. This bit disables the receiver interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 9 CLR_TX_INT [8:8] Clear Transmitter interrupt. This bit disables the transmitter interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 8 RESERVED1 [7:2] Reserved 6 2 CLR_WAKEUP_INT [1:1] Clear Wake-up interrupt. This bit disables the wakeup interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 1 CLR_BRKDT_INT [0:0] Clear Break-detect interrupt. This bit disables the Break-detect interrupt when set. User and privilege mode (read): 0 = Interrupt is disabled 1 = Interrupt is enabled User and privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = disable interrupt 1 0 0 SCISETINTLVL 0x14 32 SCI Set Interrupt Level Register RESERVED5 [31:27] Reserved 5 27 SET_FE_INT_LVL [26:26] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 26 SET_OE_INT_LVL [25:25] Clear Overrun-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 25 SET_PE_INT_LVL [24:24] Clear Parity Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 24 RESERVED4 [23:19] Reserved 5 19 SET_RX_DMA_ALL_INT_LVL [18:18] User and privilege mode (read): 0 = RX interrupt request for address frames mapped to INT0 line. 1 = RX interrupt request for address frames mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 18 RESERVED3 [17:16] Reserved 2 16 SET_INC_BR_INT_LVL [15:15] Reserved 1 15 RESERVED2 [14:10] Reserved 5 10 SET_RX_INT_LVL [9:9] Clear Receiver interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 9 SET_TX_INT_LVL [8:8] Clear Transmitter interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 8 RESERVED1 [7:2] Reserved 6 2 SET_WAKEUP_INT_LVL [1:1] Clear Wake-up interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 1 SET_BRKDT_INT_LVL [0:0] Clear Break-detect interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Clear interrupt level to line INT1 1 0 0 SCICLEARINTLVL 0x18 32 SCI Clear Interrupt Level Register RESERVED5 [31:27] Reserved 5 27 CLR_FE_INT_LVL [26:26] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 26 CLR_OE_INT_LVL [25:25] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 25 CLR_PE_INT_LVL [24:24] Clear Framing-Error Interrupt Level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 24 RESERVED4 [23:19] Reserved 5 19 CLR_RX_DMA_ALL_INT_LVL [18:18] Clear receive DMA ALL interrupt level. User and privilege mode (read): 0 = RX interrupt request for address frames is mapped to INT0 line. 1 = RX interrupt request for address frames is mapped to INT1 line. User and privilege mode (write): 0 = Leaves the corresponding bit unchanged. 1 = Reset interrupt level to line INT0. 1 18 RESERVED3 [17:16] Reserved 2 16 CLR_INC_BR_INT_LVL 1 15 RESERVED2 [14:10] Reserved 5 10 CLR_RX_INT_LVL [9:9] Clear Receiver interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 9 CLR_TX_INT_LVL [8:8] Clear Transmitter interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 8 RESERVED1 [7:2] Reserved 6 2 CLR_WAKEUP_INT_LVL [1:1] Clear Wake-up interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 1 CLR_BRKDT_INT_LVL [0:0] Clear Break-detect interrupt level. User and privilege mode (read): 0 = Interrupt level mapped to INT0 line 1 = Interrupt level mapped to INT1 line User and privilege mode (write): 0 = Leaves the corresponding bit unchanged 1 = Reset interrupt level to line INT0 1 0 0 SCIFLR 0x1C 32 SCI Flags Register RESERVED3 [31:27] Reserved 5 27 FE [26:26] SCI framing error flag Read: 0=No framing error detected 1=Framing error detected Write: 0=No effect 1=Clears this bit to 0 1 26 OE [25:25] SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD 1 25 PE [24:24] SCI parity error flag. This bit is set when a parity error is detected in the received data 1 24 RESERVED2 [23:13] Reserved 11 13 RXWAKE [12:12] Receiver wake-up detect flag. The SCI sets this bit to indicate that the data currently in SCIRD is an address 1 12 TX_EMPTY [11:11] Transmitter empty flag. The value of this flag indicates the contents of the transmitter’s buffer register (SCITD) and shift register (SCITXSHF) 1 11 TXWAKE [10:10] SCI transmitter wake-up method select. The TXWAKE bit controls whether the data in SCITD should be sent as an address or data frame using multiprocessor communication format 1 10 RXRDY [9:9] SCI receiver ready flag. The receiver sets this bit to indicate that the SCIRD contains new data and is ready to be read by the CPU or DMA. 1 9 TXRDY [8:8] Transmitter buffer register ready flag. When set, this bit indicates that the transmit buffer register (SCITD) is ready to receive another character. 1 8 RESERVED1 [7:4] Reserved 4 4 Bus_busy_flag [3:3] This bit indicates whether the receiver is in the process of receiving a frame. 1 3 IDLE [2:2] SCI receiver in idle state. While this bit is set, the SCI looks for an idle period to resynchronize itself with the bit stream. 1 2 WAKEUP [1:1] Wake-up flag. This bit is set by the SCI when receiver or transmitter activity has taken the module out of power-down mode. 1 1 BRKDT [0:0] SCI break-detect flag. This bit is set when the SCI detects a break condition on the SCIRX pin. 1 0 0 SCIINTVECT0 0x20 32 SCI Interrupt Offset Vector 0 Register RESERVED [31:4] Reserved 28 4 INTVECT0 [3:0] Interrupt vector offset for INT0 4 0 0 SCIINTVECT1 0x24 32 SCI Interrupt Offset Vector 1 Register RESERVED [31:4] Reserved 28 4 INTVECT1 [3:0] Interrupt vector offset for INT1 4 0 0 SCICHAR 0x28 32 SCI Character Control Register RESERVED [31:3] Reserved 29 3 CHAR [2:0] Sets the SCI data length from 1 to 8 bits 3 0 0 SCIBAUD 0x2C 32 SCI Baud Rate Selection Register RESERVED [31:24] Reserved 8 24 BAUD [23:0] SCI 24-bit baud selection 24 0 0 SCIED 0x30 32 Receiver Emulation Data Buffer RESERVED [31:8] Reserved 24 8 ED [7:0] Receiver Emulation Data Buffer 8 0 0 SCIRD 0x34 32 Receiver Data Buffer RESERVED [31:8] Reserved 24 8 RD [7:0] Contains received data. 8 0 0 SCITD 0x38 32 Transmit Data Buffer Register RESERVED [31:8] Reserved 24 8 TD [7:0] Contains Data to be transmitted. This is pushed to SCITXSHF(shift register) when TXENA bit is set in SCRGCR1 register. 8 0 0 SCIPIO0 0x3C 32 SCI Pin I/O Control Register 0 RESERVED [31:3] Reserved 29 3 TX_FUNC [2:2] Defines the function of pin SCITX. 0=SCITX is a general-purpose digital I/O pin. 1=SCITX is the SCI transmit pin. 1 2 RX_FUNC [1:1] Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin 1 1 CLK_FUNC [0:0] Clock function. Defines the function of pin SCICLK. 0=SCICLK is a general-purpose digital I/O pin. 1=SCICLK is the SCI serial clock pin. 1 0 0 SCIPIO1 0x40 32 SCI Pin I/O Control Register 1 RESERVED [31:3] Reserved 29 3 TX_DIR [2:2] Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 11 for bit values. 0=SCITX is a general-purpose input pin. 1=SCITX is a general-purpose output pin 1 2 RX_DIR [1:1] Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 12 for bit values. 0=SCIRX is a general-purpose input pin. 1=SCIRX is a general-purpose output pin 1 1 CLK_DIR [0:0] Clock data direction. Determines the data direction on the SCICLK pin. The direction is defined differently depending upon the value of the CLK FUNC bit 0=SCICLK is a general-purpose input pin. 1=SCICLK is a general-purpose output pin 1 0 0 SCIPIO2 0x44 32 SCI Pin I/O Control Register 2 RESERVED [31:3] Reserved 29 3 TX_DATA_IN [2:2] Contains current value on the SCITX pin. 0=SCITX value is logic low. 1=SCITX value is logic high. 1 2 RX_DATA_IN [1:1] Contains current value on the SCIRX pin. 0=SCIRX value is logic low. 1=SCIRX value is logic high. 1 1 CLK_DATA_IN [0:0] Contains the current value on pin SCICLK. 0=Pin SCICLK value is logic low. 1=Pin SCICLK value is logic high. 1 0 0 SCIPIO3 0x48 32 SCI Pin I/O Control Register 3 RESERVED [31:3] Reserved 29 3 TX_DATA_OUT [2:2] Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.) 0=Output value on SCITX is a 0 (logic low). 1=Output value on SCITX is a 1 (logic high). 1 2 RX_DATA_OUT [1:1] Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) 0=Output value on SCIRX is 0 (logic low). 1=Output value on SCIRX is 1 (logic high). 1 1 CLK_DATA_OUT [0:0] Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) 0=Output value on SCICLK is a 0 (logic low). 1=Output value on SCICLK is a 1 (logic high). 1 0 0 SCIPIO4 0x4C 32 SCI Pin I/O Control Register 4 RESERVED [31:3] Reserved 29 3 TX_DATA_SET [2:2] Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.) 1 2 RX_DATA_SET [1:1] Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DIR = 1 (SCIRX pin is a general-purpose output.) 1 1 CLK_DATA_SET [0:0] Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DIR = 1 (SCICLK pin is a general-purpose output.) 1 0 0 SCIPIO5 0x50 32 SCI Pin I/O Control Register 5 RESERVED [31:3] Reserved 29 3 TX_DATA_CLR [2:2] Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.) 1 2 RX_DATA_CLR [1:1] Clears the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCITX pin is a general-purpose I/O.) RX DIR = 1 (SCITX pin is a general-purpose output.) 1 1 CLK_DATA_CLR [0:0] Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DIR = 1 (SCITX pin is a general-purpose output.) 1 0 0 SCIPIO6 0x54 32 SCI Pin I/O Control Register 6 RESERVED [31:3] Reserved 29 3 TX_PDR [2:2] TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1 1 2 RX_PDR [1:1] RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1 1 1 CLK_PDR [0:0] CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1 1 0 0 SCIPIO7 0x58 32 SCI Pin I/O Control Register 7 RESERVED [31:3] Reserved 29 3 TX_PD [2:2] TX pin Pull Control Disable Disables pull control capability in the output pin SCITX. 0=Pull Control on SCITX pin is enabled. 1=Pull Control on SCITX pin is disabled. 1 2 RX_PD [1:1] RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX. 0=Pull Control on SCIRX pin is enabled. 1=Pull Control on SCIRX pin is disabled. 1 1 CLK_PD [0:0] CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK. 0=Pull Control on SCICLK pin is enabled. 1=Pull Control on SCICLK pin is disabled. 1 0 0 SCIPIO8 0x5C 32 SCI Pin I/O Control Register 8 RESERVED [31:3] Reserved 29 3 TX_PSL [2:2] TX pin Pull Select Selects pull type in the output pin SCITX. 0=Pull-Down is on SCITX pin. 1=Pull-Up is on SCITX pin. 1 2 RX_PSL [1:1] RX pin Pull Select Selects pull type in the output pin SCIRX. 0=Pull-Down is on SCIRX pin. 1=Pull-Up is on SCIRX pin. 1 1 CLK_PSL [0:0] CLK pin Pull Select Selects pull type in the output pin SCICLK. 0=Pull-Down is on SCICLK pin. 1=Pull-Up is on SCICLK pin. 1 0 0 RESERVED2 0x60 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED3 0x64 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED4 0x68 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED5 0x6C 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED6 0x70 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED7 0x74 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED8 0x78 32 Reserved RESERVED [31:0] Reserved 32 0 0 RESERVED9 0x7C 32 Reserved RESERVED [31:0] Reserved 32 0 0 SCIPIO9 0x80 32 SCI Pin I/O Control Register 9 RESERVED [31:3] Reserved 29 3 TX_SL [2:2] This bit controls the slew rate for the SCITX pin. 0=The normal output buffer is used for SCITX pin 1=The output buffer with slew control is used for SCITX pin. 1 2 RX_SL [1:1] This bit controls the slew rate for the SCIRX pin. 0=The normal output buffer is used for SCIRX pin 1=The output buffer with slew control is used for SCIRX pin 1 1 CLK_SL [0:0] This bit controls the slew rate for the SCICLK pin. 0=The normal output buffer is used for SCICLK pin 1=The output buffer with slew control is used for SCICLK pin 1 0 0 SCIIODCTRL 0x90 32 SCI IO DFT Control RESERVED4 [31:27] Reserved 5 27 FEN [26:26] Frame Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Frame Error. The stop bit received is ANDed with ’0’ and passed to the stop bit check circuitry. 0 = No effect. 1 26 PEN [25:25] Parity Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create a Parity Error. The parity bit received is toggled so that a parity error occurs. 0 = No effect 1 25 BRKDT_ENA [24:24] Break Detect Error Enable. User and Privileged Mode Reads and Writes: 1 = This bit is used to create BRKDT Error. The stop bit of the frame is ANDed with ‘0’ and passed to the RSM so that a frame error occurs. Then the RX pin is forced to continuous low for 10 TBITS so that a BRKDT error occurs. 0 = No effect. 1 24 RESERVED3 [23:21] Reserved 3 21 PIN_SAMPLE_MASK [20:19] PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry. PIN SAMPLE MASK: 00 -- No Mask, 01 -- Invert the TX Pin value at 7th SCLK, 10 -- Invert the TX Pin value at 8th SCLK, 11 -- Invert the TX Pin value at 9th SCLK. 2 19 TX_SHIFT [18:16] These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay. 3 16 RESERVED2 [15:12] Reserved 4 12 IODFTENA [11:8] These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous. (Not applicable to Start Bit) TX SHIFT: 000 -- No Delay, 001 -- Delay by 1 SCLK, 010 -- Delay by 2 SCLKs, 011 -- Delay by 3 SCLKs, 100 -- Delay by 4 SCLKs, 101 -- Delay by 5 SCLKs, 110 -- Delay by 6 SCLKs, 111 -- No Delay. 4 8 RESERVED1 [7:2] Reserved 6 2 LBP_ENA [1:1] Module loopback enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback is enabled in module I/O DFT mode(when IODFTENA = 1010) 0=Digital loopback is enabled. 1 1 RXP_ENA [0:0] Module Analog loopback through receive pin enable. user and privileged mode reads: Write only in privileged mode: write/read : 1=Analog loopback through receive pin. 0=Analog loopback through transmit pin. 1 0 0 APP_SPI_1 0x57F7F400 0 420 registers APP_SPI HL_REV 0x0 32 IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility SCHEME [31:30] Used to distinguish between old scheme and current - (RO ) 2 30 RSVD [29:28] Reserved These bits are initialized to zero and writes to them are ignored - (RO ) 2 28 FUNC [27:16] Function indicates a software compatible module family If there is no level of software compatibility a new Func number [and hence REVISION] should be assigned - (RO ) 12 16 R_RTL [15:11] RTL Version [R] maintained by IP design owner RTL follows a numbering such as XYRZ which are explained in this table R changes ONLY when: [1] PDS uploads occur which may have been due to spec changes [2] Bug fixes occur [3] Resets to '0' when X or Y changes Design team has an internal 'Z' [customer invisible] number which increments on every drop that happens due to DV and RTL updates Z resets to 0 when R increments - (RO ) 5 11 X_MAJOR [10:8] Major Revision [X] maintained by IP specification owner X changes ONLY when: [1] There is a major feature addition An example would be adding Master Mode to Utopia Level2 The Func field [or Class/Type in old PID format] will remain the same X does NOT change due to: [1] Bug fixes [2] Change in feature parameters - (RO ) 3 8 CUSTOM [7:6] Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers - (RO ) 2 6 Y_MINOR [5:0] Minor Revision [Y] maintained by IP specification owner Y changes ONLY when: [1] Features are scaled [up or down] Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available [2] When feature creeps from Is-Not list to Is list But this may not be the case once it sees silicon; in which case X will change Y does NOT change due to: [1] Bug fixes [2] Typos or clarifications [3] major functional/feature change/addition/deletion Instead these changes may be reflected via R S X as applicable Spec owner maintains a customer-invisible number 'S' which changes due to: [1] Typos/clarifications [2] Bug documentation Note that this bug is not due to a spec change but due to implementation Nevertheless the spec tracks the IP bugs An RTL release [say for silicon PG11] that occurs due to bug fix should document the corresponding spec number [XYS] in its release notes - (RO ) 6 0 0 HL_HWINFO 0x4 32 Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide. RSVD [31:7] Reserved These bits are initialized to zero and writes to them are ignored - (RO ) 25 7 RETMODE [6:6] This bit field indicates whether the retention mode is supported using the pin PIRFFRET - (RO ) 1 6 FFNBYTE [5:1] FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter only MSB bits from 8 down to 4 are taken into account - (RO ) 5 1 USEFIFO [0:0] Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management - (RO ) 1 0 0 HL_SYSCONFIG 0x10 32 Clock management configuration RSVD [31:4] Reserved - (RO ) 28 4 IDLEMODE [3:2] Configuration of the local target state management mode By definition target can handle read/write transaction as long as it is out of IDLE state - (RW ) 2 2 FREEEMU [1:1] Sensitivity to emulation [debug] suspend input signal - (RW ) 1 1 SOFTRESET [0:0] Software reset [Optional] - (RW ) 1 0 0 REVISION 0x100 32 This register contains the hard coded RTL revision number. RESERVED_13 [31:8] Reads returns 0 - (RO ) 24 8 REV [7:0] IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 10 0x21 for 21 - (RO 8 0 0 SYSCONFIG 0x110 32 This register allows controlling various parameters of the OCP interface. RESERVED_14 [31:10] Reads returns 0 - (RO ) 22 10 CLOCKACTIVITY [9:8] Clocks activity during wake up mode period - (RW ) 2 8 RESERVED_15 [7:5] Reads returns 0 - (RO ) 3 5 SIDLEMODE [4:3] Power management - (RW ) 2 3 ENAWAKEUP [2:2] WakeUp feature control - (RW ) 1 2 SOFTRESET [1:1] Software reset During reads it always returns 0 - (RW ) 1 1 AUTOIDLE [0:0] Internal OCP Clock gating strategy - (RW ) 1 0 0 SYSSTATUS 0x114 32 This register provides status information about the module excluding the interrupt status information RESERVED_16 [31:1] Reserved for module specific status information Read returns 0 - (RO ) 31 1 RESETDONE [0:0] Internal Reset Monitoring - (RO ) 1 0 0 IRQSTATUS 0x118 32 The interrupt status regroups all the status of the module internal events that can generate an interrupt RESERVED_8 [31:18] Reads returns 0 - (RO ) 14 18 EOW [17:17] End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] - (RW ) 1 17 WKS [16:16] Wake Up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - (RW ) 1 16 RESERVED_7 [15:15] Reads returns 0 - (RO ) 1 15 RX3_FULL [14:14] Receiver register is full or almost full Only when Channel 3 is enabled - (RW ) 1 14 TX3_UNDERFLOW [13:13] Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled - (RW ) 1 13 TX3_EMPTY [12:12] Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event - (RW ) 1 12 RESERVED_9 [11:11] Reads returns 0 - (RO ) 1 11 RX2_FULL [10:10] Receiver register full or almost full Channel 2 - (RW ) 1 10 TX2_UNDERFLOW [9:9] Transmitter register underflow Channel 2 - (RW ) 1 9 TX2_EMPTY [8:8] Transmitter register empty or almost empty Channel 2 - (RW ) 1 8 RESERVED_10 [7:7] Reads returns 0 - (RO ) 1 7 RX1_FULL [6:6] Receiver register full or almost full Channel 1 - (RW ) 1 6 TX1_UNDERFLOW [5:5] Transmitter register underflow Channel 1 - (RW ) 1 5 TX1_EMPTY [4:4] Transmitter register empty or almost empty Channel 1 - (RW ) 1 4 RX0_OVERFLOW [3:3] Receiver register overflow [slave mode only] Channel 0 - (RW ) 1 3 RX0_FULL [2:2] Receiver register full or almost full Channel 0 - (RW ) 1 2 TX0_UNDERFLOW [1:1] Transmitter register underflow Channel 0 - (RW ) 1 1 TX0_EMPTY [0:0] Transmitter register empty or almost empty Channel 0 - (RW ) 1 0 0 IRQENABLE 0x11C 32 This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis. RESERVED_5 [31:18] Reads return 0 - (RO ) 14 18 EOW_ENABLE [17:17] End of Word count Interrupt Enable - (RW ) 1 17 WKE [16:16] Wake Up event interrupt Enable in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - (RW ) 1 16 RESERVED_4 [15:15] Reads returns 0 - (RO ) 1 15 RX3_FULL_ENABLE [14:14] Receiver register Full Interrupt Enable Ch 3 - (RW ) 1 14 TX3_UNDERFLOW_ENABLE [13:13] Transmitter register Underflow Interrupt Enable Ch 3 - (RW ) 1 13 TX3_EMPTY_ENABLE [12:12] Transmitter register Empty Interrupt Enable Ch3 - (RW ) 1 12 RESERVED_6 [11:11] Reads return 0 - (RO ) 1 11 RX2_FULL_ENABLE [10:10] Receiver register Full Interrupt Enable Ch 2 - (RW ) 1 10 TX2_UNDERFLOW_ENABLE [9:9] Transmitter register Underflow Interrupt Enable Ch 2 - (RW ) 1 9 TX2_EMPTY_ENABLE [8:8] Transmitter register Empty Interrupt Enable Ch 2 - (RW ) 1 8 RESERVED_3 [7:7] Reads return 0 - (RO ) 1 7 RX1_FULL_ENABLE [6:6] Receiver register Full Interrupt Enable Ch 1 - (RW ) 1 6 TX1_UNDERFLOW_ENABLE [5:5] Transmitter register Underflow Interrupt Enable Ch 1 - (RW ) 1 5 TX1_EMPTY_ENABLE [4:4] Transmitter register Empty Interrupt Enable Ch 1 - (RW ) 1 4 RX0_OVERFLOW_ENABLE [3:3] Receiver register Overflow Interrupt Enable Ch 0 - (RW ) 1 3 RX0_FULL_ENABLE [2:2] Receiver register Full Interrupt Enable Ch 0 - (RW ) 1 2 TX0_UNDERFLOW_ENABLE [1:1] Transmitter register Underflow Interrupt Enable Ch 0 - (RW ) 1 1 TX0_EMPTY_ENABLE [0:0] Transmitter register Empty Interrupt Enable Ch 0 - (RW ) 1 0 0 WAKEUPENABLE 0x120 32 The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis. RESERVED_18 [31:1] Reads returns 0 - (RO ) 31 1 WKEN [0:0] WakeUp functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] - (RW ) 1 0 0 SYST 0x124 32 This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode. RESERVED_17 [31:12] Reads returns 0 - (RO ) 20 12 SSB [11:11] Set status bit - (RW ) 1 11 SPIENDIR [10:10] Set the direction of the SPIEN[3:0] lines and SPICLK line - (RW ) 1 10 SPIDATDIR1 [9:9] Set the direction of the SPIDAT[1] - (RW ) 1 9 SPIDATDIR0 [8:8] Set the direction of the SPIDAT[0] - (RW ) 1 8 WAKD [7:7] SWAKEUP output [signal data value of internal signal to system] The signal is driven high or low according to the value written into this register bit - (RW ) 1 7 SPICLK [6:6] SPICLK line [signal data value] If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the CLKSPI line [high or low] and a write into this bit has no effect If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the CLKSPI line is driven high or low according to the value written into this register - (RW ) 1 6 SPIDAT_1 [5:5] SPIDAT[1] line [signal data value] If MCSPI_SYST[SPIDATDIR1] = 0 [output mode direction] the SPIDAT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR1] = 1 [input mode direction] this bit returns the value on the SPIDAT[1] line [high or low] and a write into this bit has no effect - (RW ) 1 5 SPIDAT_0 [4:4] SPIDAT[0] line [signal data value] If MCSPI_SYST[SPIDATDIR0] = 0 [output mode direction] the SPIDAT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIDATDIR0] = 1 [input mode direction] this bit returns the value on the SPIDAT[0] line [high or low] and a write into this bit has no effect - (RW ) 1 4 SPIEN_3 [3:3] SPIEN[3] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[3] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[3] line [high or low] and a write into this bit has no effect - (RW ) 1 3 SPIEN_2 [2:2] SPIEN[2] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[2] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[2] line [high or low] and a write into this bit has no effect - (RW ) 1 2 SPIEN_1 [1:1] SPIEN[1] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[1] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[1] line [high or low] and a write into this bit has no effect - (RW ) 1 1 SPIEN_0 [0:0] SPIEN[0] line [signal data value] If MCSPI_SYST[SPIENDIR] = 0 [output mode direction] the SPIENT[0] line is driven high or low according to the value written into this register If MCSPI_SYST[SPIENDIR] = 1 [input mode direction] this bit returns the value on the SPIEN[0] line [high or low] and a write into this bit has no effect - (RW ) 1 0 0 MODULCTRL 0x128 32 This register is dedicated to the configuration of the serial port interface. RESERVED_11 [31:9] Reads returns 0 - (RO ) 23 9 FDAA [8:8] FIFO DMA Address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256 bit aligned address If this bit is set the enabled channel which uses the FIFO has its datas managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX[i] and MCSPI_RX[i] registers - (RW ) 1 8 MOA [7:7] Multiple word ocp access: This register can only be used when a channel is enabled using a FIFO It allows the system to perform multiple SPI word access for a single 32-bit OCP word access This is possible for WL < 16 - (RW ) 1 7 INITDLY [6:4] Initial spi delay for first transfer: This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first spi word after channel enabled and corresponding TX register filled This Delay is based on SPI output frequency clock No clock output provided to the boundary and chip select is not active in 4 pin mode within this period - (RW ) 3 4 SYSTEM_TEST [3:3] Enables the system test mode - (RW ) 1 3 MS [2:2] Master/ Slave - (RW ) 1 2 PIN34 [1:1] Pin mode selection: This register is used to configure the SPI pin mode in master or slave mode If asserted the controller only use SIMOSOMI and SPICLK clock pin for spi transfers - (RW ) 1 1 SINGLE [0:0] Single channel / Multi Channel [master mode only] - (RW ) 1 0 0 CH0CONF 0x12C 32 This register is dedicated to the configuration of the channel 0 RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS0 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 SPIENSLV [22:21] Channel 0 only and slave mode only: SPI slave select signal detection Reserved bits for other cases - (RW ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH0STAT 0x130 32 This register provides status information about transmitter and receiver registers of channel 0 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH0CTRL 0x134 32 This register is dedicated to enable the channel 0 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX0 0x138 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 0 Data to transmit - (RW ) 32 0 0 RX0 0x13C 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 0 Received Data - (RO ) 32 0 0 CH1CONF 0x140 32 This register is dedicated to the configuration of the channel. RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS1 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 RESERVED_1 [22:21] read returns 0 - (RO ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH1STAT 0x144 32 This register provides status information about transmitter and receiver registers of channel 1 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH1CTRL 0x148 32 This register is dedicated to enable the channel 1 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX1 0x14C 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 1 Data to transmit - (RW ) 32 0 0 RX1 0x150 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 1 Received Data - (RO ) 32 0 0 CH2CONF 0x154 32 This register is dedicated to the configuration of the channel 2 RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS2 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 RESERVED_1 [22:21] read returns 0 - (RO ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH2STAT 0x158 32 This register provides status information about transmitter and receiver registers of channel 2 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH2CTRL 0x15C 32 This register is dedicated to enable the channel 2 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX2 0x160 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 2 Data to transmit - (RW ) 32 0 0 RX2 0x164 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 2 Received Data - (RO ) 32 0 0 CH3CONF 0x168 32 This register is dedicated to the configuration of the channel 3 RESERVED_0 [31:30] read returns 0 - (RO ) 2 30 CLKG [29:29] Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values - (RW ) 1 29 FFER [28:28] FIFO enabled for receive:Only one channel can have this bit field set - (RW ) 1 28 FFEW [27:27] FIFO enabled for Transmit:Only one channel can have this bit field set - (RW ) 1 27 TCS3 [26:25] Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock - (RW ) 2 25 SBPOL [24:24] Start bit polarity - (RW ) 1 24 SBE [23:23] Start bit enable for SPI transfer - (RW ) 1 23 RESERVED_1 [22:21] read returns 0 - (RO ) 2 21 FORCE [20:20] Manual SPIEN assertion to keep SPIEN active between SPI words [single channel master mode only] - (RW ) 1 20 TURBO [19:19] Turbo mode - (RW ) 1 19 IS [18:18] Input Select - (RW ) 1 18 DPE1 [17:17] Transmission Enable for data line 1 [SPIDATAGZEN[1]] - (RW ) 1 17 DPE0 [16:16] Transmission Enable for data line 0 [SPIDATAGZEN[0]] - (RW ) 1 16 DMAR [15:15] DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel - (RW ) 1 15 DMAW [14:14] DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel - (RW ) 1 14 TRM [13:12] Transmit/Receive modes - (RW ) 2 12 WL [11:7] SPI word length - (RW ) 5 7 EPOL [6:6] SPIEN polarity - (RW ) 1 6 CLKD [5:2] Frequency divider for SPICLK [only when the module is a Master SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 - (RW ) 4 2 POL [1:1] SPICLK polarity - (RW ) 1 1 PHA [0:0] SPICLK phase - (RW ) 1 0 0 CH3STAT 0x16C 32 This register provides status information about transmitter and receiver registers of channel 3 RESERVED_2 [31:7] Read returns 0 - (RO ) 25 7 RXFFF [6:6] Channel "i" FIFO Receive Buffer Full Status - (RO ) 1 6 RXFFE [5:5] Channel "i" FIFO Receive Buffer Empty Status - (RO ) 1 5 TXFFF [4:4] Channel "i" FIFO Transmit Buffer Full Status - (RO ) 1 4 TXFFE [3:3] Channel "i" FIFO Transmit Buffer Empty Status - (RO ) 1 3 EOT [2:2] Channel "i" End of transfer Status The definitions of beginning and end of transfer vary with master versus slave and the transfer format [Transmit/Receive modes Turbo mode] See dedicated chapters for details - (RO ) 1 2 TXS [1:1] Channel "i" Transmitter Register Status - (RO ) 1 1 RXS [0:0] Channel "i" Receiver Register Status - (RO ) 1 0 0 CH3CTRL 0x170 32 This register is dedicated to enable the channel 3 RESERVED_2 [31:16] Read returns 0 - (RO ) 16 16 EXTCLK [15:8] Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio - (RW ) 8 8 RESERVED_1 [7:1] Read returns 0 - (RO ) 7 1 EN [0:0] Channel Enable - (RW ) 1 0 0 TX3 0x174 32 This register contains a single SPI word to transmit on the serial link what ever SPI word length is. TDATA [31:0] Channel 3 Data to transmit - (RW ) 32 0 0 RX3 0x178 32 This register contains a single SPI word received through the serial link what ever SPI word length is. RDATA [31:0] Channel 3 Received Data - (RO ) 32 0 0 XFERLEVEL 0x17C 32 This register provides transfer levels needed while using FIFO buffer during transfer. WCNT [31:16] Spi word counterThis register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO bufferWhen transfer had started a read back in this register returns the current SPI word transfer index - (RW ) 16 16 AFL [15:8] Buffer Almost Full This register holds the programmable almost full level value used to determine almost full buffer condition If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_MODULCTRL[AFL] must be set with n-1The size of this register is defined by the generic parameter FFNBYTE - (RW ) 8 8 AEL [7:0] Buffer Almost EmptyThis register holds the programmable almost empty level value used to determine almost empty buffer condition If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes then the buffer MCSPI_MODULCTRL[AEL] must be set with n-1 - (RW ) 8 0 0 DAFTX 0x180 32 This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled. DAFTDATA [31:0] FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to "1" and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to this register return a null value - (RW ) 32 0 0 DAFRX 0x1A0 32 This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled. DAFRDATA [31:0] FIFO Data to transmit with DMA 256 bit aligned address This Register is only is used when MCSPI_MODULCTRL[FDAA] is set to "1" and only one of the MCSPI_CH[i]CONF[FFEW] of enabled channels is set If these conditions are not respected any access to this register return a null value - (RO ) 32 0 0 APP_I2C 0x57F7F800 0 100 registers APP_I2C ICOAR 0x0 32 I2C Own Address register NU [31:10] Reserved 22 10 A9_A0 [9:0] Own address. Use in both 7- and 10-bit address mode. Note that usercan program the I2C own address to any value as long as it does notconflict with other components in the system. 10 0 0 ICIMR 0x4 32 I2C Interrupt Mask/Status register NU [31:7] Reserved 25 7 AAS [6:6] Address As Slave interrupt mask bit. Setting a"1" to this bit unmasks the Address As Slave interrupt. Setting a"0" to this bit masks the Address As Slave interrupt. 1 6 SCD [5:5] Stop Condition Detection mask bit. Setting a"1" to this bit unmasks the Stop Condition Detection interrupt. Setting a "0" to this bit masks the Stop Condition Detection interrupt. 1 5 ICXRDY [4:4] Transmit Data Ready interrupt mask bit. Setting a"1" to this bit unmasks the Transmit Data Ready interrupt. Setting a"0" to this bit masks the Transmit Data Ready interrupt. 1 4 ICRRDY [3:3] Receive Data Ready interrupt mask bit. Setting a"1" to this bit unmasks the Receive Data Ready interrupt. Setting a"0" to this bit masks the Receive Data Ready interrupt. 1 3 ARDY [2:2] Register access ready interrupt mask bit. Setting a"1" to this bit unmasks the Register access ready interrupt. Setting a"0" to this bit masks the Register access ready interrupt. 1 2 NACK [1:1] No Acknowledgement interrupt mask bit. Setting a"1" to this bit unmasks the No Acknowledgement interrupt. Setting a"0" to this bit masks the No Acknowledgement interrupt. 1 1 AL [0:0] Arbitration Lost interrupt mask bit. Setting a"1" to this bit unmasks the Arbitration Lost interrupt. Setting a"0" to this bit masks the Arbitration Lost interrupt. 1 0 0 ICSTR 0x8 32 I2C Interrupt Status register NU2 [31:15] Reserved 17 15 SDIR [14:14] Slave Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a slave receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C slave is a transmitter. In DLB mode (which the configuration should be master-transmitter slave-receiver) this bit is clear to '0'. Writing a"1" to this bit to clear it. 1 14 NACKSNT [13:13] A No Acknowledge is sent due to NACKMOD is set to a"1". NACKSNT =0: A No Acknowledge is not sent. NACKSNT =1: A No Acknowledge is sent. Writing a"1" to this bit to clear it. 1 13 BB [12:12] Bus Busy. This bit indicates the state of the serial bus. BB=0: The bus is free. BB=1: The bus is occupied. On reception of a"start" condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after reception of a"stop" condition. BB is kept to"0" regardless SCL state when the I2C is in reset (IRS_=0). If the IRS_ is set to"1" during transaction between other I2C devices the BB bit is set at the first falling edge of SCL or START condition. - (RW ) 1 12 RSFULL [11:11] Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register (ICRSR) is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR read access. RSFULL is clear when reading the ICDRR. RSFULL is set to"1" when the I2C has recognized an overrun. The contents of ICDRR are NOT lost in this case. In repeat mode since double buffer (ICRSR and ICDRR) behaves like a single buffer RSFULL is set to"1" every time the data is received. RSFULL is clear as a result of reading the ICDRR. - (RW ) 1 11 XSMT [10:10] Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register (ICXSR) is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_ is cleared when underflow has occurred. XSMT_ is set to"1" as a result of writing to ICDXR. In repeat mode if the I2C in master transmitter mode is holding transfer with XSMT_=0 (i.e. waiting for further action) and the STT or STP bit is set XSMT_ is set to"1" by hardware. 1 10 AAS [9:9] Address As Slave. This bit is set to 1 by the device when it has recognized its own slave address or an address of all (8) zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - (RW ) 1 9 AD0 [8:8] Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call). The AD0 bit is reset to 0 (default value) when a"start" or"stop" condition is detected. - (RW ) 1 8 NU1 [7:6] Reserved 2 6 SCD [5:5] Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by reading ICIVR (as 110) or writing '1' to itself. 1 5 ICXRDY [4:4] Transmit Data Ready interrupt flag bit. ICXRDY is set to"1" is generated when the transmitted data has been copied from ICDXR to the transmit-shift register (ICXSR). ICRXDY is clear to"0" when the ICDXR is written. This bit can also be polled by the CPU to write a new transmitted data into the ICDXR. Write '1' to this bit will set it and DXR Write will clear it. 1 4 ICRRDY [3:3] Receive Data Ready interrupt flag bit. ICRRDY is set to"1" when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to"0" when the ICDRR is read. This bit can also be polled by the CPU to read the received data in the ICDRR. Write '1' or DRR Read will clear it. 1 3 ARDY [2:2] Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let it knows that the I2C registers are ready to be accessed again. When RM=0 ARDY is set when the internal data count is passed 0 if STP register bit has not been set. When RM=1 ARDY is set at each byte end. If the I2C is in FDF mode(FDF=1) ARDY is set just after Start condition. This bit is automatically cleared by hardware when writing data to ICDXR in transmit mode reading data from ICDRR in receive mode or setting STT or STP bit. Write '1' will clear it. 1 2 NACK [1:1] No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in "master" mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR (as 010) will clear it. 1 1 AL [0:0] Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the "master" mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C attempts to start a transfer while BB (bus busy) is 1. When this is set to 1 due to arbitration lost the MST/STT/STP bits are clear the I2C becomes a slave. Write '1' or Read the ICIVR (as 001) will clear it. 1 0 0 ICCLKL 0xC 32 I2C Clock Divider Low register NU [31:16] Reserved 16 16 ICCL15_ICCL0 [15:0] Low time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL low time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0). 16 0 0 ICCLKH 0x10 32 I2C Clock Divider High register NU [31:16] Reserved 16 16 ICCH15_ICCLH0 [15:0] High time I 2 C SCL Clock Division Factor. They are used to divide down the master clock to create the SCL high time transition frequency. This register must be configured while the I2C is still in reset (IRS_=0). 16 0 0 ICCNT 0x14 32 I2C Data Count register NU [31:16] Reserved 16 16 ICDC15_ICDC0 [15:0] Data count. This data count register is used to generate a Stop condition if a Stop condition is specified (STP=1). . ICCNT=1 data count is 1 :::::::::::::::::::::::::::::::::::::::::::: :::::::::::::::::::::::::::::::::::::::::::: ICCNT=0FFFFh data count is 65535 ICCNT=0data counter is 65536 Note that ICCNT is a don"t care when RM is set to 1. 16 0 0 ICDRR 0x18 32 I2C Data Receive register NU [31:8] Reserved 24 8 D7_D0 [7:0] Receive data 8 0 0 ICSAR 0x1C 32 I2C Slave Address register NU [31:10] Reserved 22 10 A9_A0 [9:0] Slave address. Use in both 7- and 10-bit address mode. 10 0 0 ICDXR 0x20 32 I2C Data Transmit register NU [31:8] Reserved 24 8 D7_D0 [7:0] Transmit data 8 0 0 ICMDR 0x24 32 I2C Mode register NU2 [31:16] Reserved 16 16 NACKMOD [15:15] No Acknowledge (NACK) mode. This bit is used to send an Acknowledge (ACK) or a No Acknowledge (NACK) to the transmitter. This bit is only applicable when the I2C is in receiver mode. In master receiver mode when the internal data count counter decrements to zero the I2C sends a NACK. The master receiver I2C finishes a transfer when it sends a NACK. The I2C ignores ICCNT when NACKMOD is '1'. The NACKMOD bit should be set before the rising edge of the last data bit (bit 8) if a NACK must be sent and this bit is cleared once a NACK has been sent. NACKMOD=0 the I2C sends an ACK to the transmitter during the acknowledge cycle. NACKMOD=1 the I2C sends a NACK to the transmitter during the acknowledge cycle. 1 15 FREE [14:14] Free Running. This bit is used to determine the state of the I2C when a breakpoint is encountered in the HLL debugger. FREE=0: (default) Stops immediately if SCL is low and keep driving SCL low whether I2C is master transmitter/receiver. If SCL is high I2C waits until SCL becomes low and then stops. If the I2C is a slave it will stop when the transmission/receiving completes. FREE=1: The I2C runs free. 1 14 STT [13:13] Start Condition (Master only mode). This bit can be set to a"1" by the CPU to generate a Start condition. In master mode when setting Start to"1" generates a Start condition. It is reset to "0" by the hardware after the Start condition has been generated. The Start/Stop bits can be configured to generate different transfer formats. Note that the STT and STP can be used to terminate the repeat mode. ____________________________________________________ STT___STP____Conditions_______________Bus Activities _1_____0________Start___________________S-A-D _0_____1________Stop_____________________P _1_____1________Start-Stop (ICCNT= n)______S-A-D..(n)..D-P _1_____0________Start (ICCNT= n)__________S-A-D..(n)..D ____________________________________________________ 1 13 NU1 [12:12] Reserved for IDLEEN (IDLE Enable on 5509). - (RW ) 1 12 STP [11:11] Stop Condition (Master mode only). This bit can be set to a"1" by the CPU to generate a Stop condition. It is reset to "0" by the hardware after the Stop condition has been generated. The Stop condition is generated when ICCNT passes 0 when the I2C is in non-repeat mode(RM=0). 1 11 MST [10:10] Master. MST=0: The I 2 C peripheral is in the"slave" mode and clock is received from the"master" device. MST=1: The I 2 C peripheral is in the"master" mode and it generates the clock. This bit is clear when the transfer completed. 1 10 TRX [9:9] Transmitter. TRX=0: The I 2 C is in the"receiver" mode and data on data line SDA is shifted into the data register ICDRR. TRX=1: The I 2 C is in the"transmitter" mode and the data in ICDXR is shifted out on data line SDA. The operating modes (not in FDF mode) are defined as follows. In FDF mode TRX must be configured even if the I2C is in slave mode because there is no address/direction byte in FDF mode. ______________________________ MST___TRX___Operating Modes _0______x_____"slave receiver" _0______x_____"slave transmitter" _1______0_____"master receiver" _1______1_____"master transmitter" ______________________________ 1 9 XA [8:8] Expanded Address. XA=0: (default) 7-bit address mode (normal address mode). XA=1: 10-bit address mode (expanded address mode) Please note that XA needs to be configured even if the I2C is in slave mode. 1 8 RM [7:7] Repeat Mode. This bit is set to a"1" by the CPU to put the I2C in the repeat mode. In this mode data is continuously transmitted out of the ICDXR until the STP bit is set to"1" regardless of ICCNT value. This bit is don"t care if the I2C is configured in slave mode. _________________________________________________________ RM___STT___STP___Conditions_____Bus Activities_______Mode _0_____0_____0_______Idle___________None___________NA _0_____0_____1_______Stop____________P____________NA _0_____1_____0_____(Re)Start_______S-A-D..(n)..D____Repeat n _0_____1_____1_____(Re)Start-Stop___S-A-D..(n)..D-P__Repeat n _1_____0_____0_______Idle___________none___________NA _1_____0_____1_______Stop____________P ___________NA _1_____1_____0_____(Re)Start_______S-A-D-D-D.._____Continuous _1_____1_____1_____Reserved________None___________NA _________________________________________________________ 1 7 DLB [6:6] Digital Loop Back (in master transmit mode only). This bit is set to a"1" by the CPU to put the I2C in the loop back mode. In this mode data transmitted out of the ICDXR will be received in the ICDRR after ((CPU freq/I2C freq)8) CPU cycles via an internal path. The address of the ICOAR is output on SDA. 1 6 IRS [5:5] I2C Reset Not. This can be set to a"0" by the CPU to put the I2C in reset or to a"1" to take the I2C out of reset. When this bit is reset to 0 all status bits in ICSTR and ICIVR are set to default values. Note that if this bit is reset during a transfer it can cause the I2C bus hang (SDA and SCL are tri-stated). 1 5 STB [4:4] Start Byte (Master only mode). The Start Byte mode bit is set to 1 by the CPU to configure the I2C in Start byte mode the I2C sends "00000001"� regardless ICSAR value. Refer to the Philip I2C spec for more details. 1 4 FDF [3:3] Free Data Format. This bit can be set to"1" by the CPU to configure the I2C in Free Data Format mode. ______________________________________________ FDF___MST___TRX______Operating mode _0______0_____ x____Slave in non FDF mode _0______1_____0____Master receive in non FDF mode _0______1_____1____Master transmit in non FDF mode _1______0_____0____Slave receiver in FDF mode _1______0_____1____Slave transmitter in FDF mode _1______1_____0____Master receiver in FDF mode _1______1_____1____Master transmitter in FDF mode ______________________________________________ 1 3 BC2_BC1_BC0 [2:0] Bit Count : Bit Count 2, Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted. __________________________________________ BC2_BC1_BC0__Bits/byte in FDF__Bits/byte w/ ACK _0___0___1_____NA (reserved)____ NA (reserved) _0___1___0________2______________3_______ _0___1___1________3______________4_______ _1___0___0________4______________5_______ _1___0___1________5______________6_______ _1___1___0________6______________7_______ _1___1___1________7______________8_______ _0___0___0________8______________9_______ __________________________________________ 3 0 0 ICIVR 0x28 32 I2C Interrupt Vector register NU2 [31:12] Reserved. 20 12 TESTMD [11:8] Reserved for internal testing. 4 8 NU1 [7:3] Reserved. 5 3 INTCODE [2:0] Interrupt code. The binary-coded-interrupt vector indicates which interrupt has occurred. Reading the ICIVR clears the interrupt code except ARDY(011) RRDY(100) and XRDY(101). Interrupt code for ARDY RRDY and XRDY is cleared when ARDY ICRRDY and ICXRDY bits in the ICSTR is cleared to default value respectively. If other interrupts are pending a new interrupt is generated. If there are more than one interrupt flag reading the ICIVR clears the highest priority interrupt code. Reading the ICIVR also clears corresponding status bit in the ICSTR except ARDY ICRRDY ICXRDY and AAS. Note that users must read (clear) the ICIVR before doing another start otherwise the ICIVR could contain incorrect (old interrupt flags) value. ________________________________________________ Interrupt Code____________Interrupt Occurred__________ _000_(default)_________________None _001_(highest priority)____Arbitration Lost interrupt _010__________________No Acknowledgement interrupt _011__________________Register Access Ready interrupt _100__________________Receive Data Ready interrupt _101__________________Transmit Data Ready interrupt _110__________________Stop Condition Detection _111_(lowest priority)_____Address As Slave - (RW) ________________________________________________ 3 0 0 ICEMDR 0x2C 32 I2C Extended Mode register NU [31:2] Reserved. - (RW ) 30 2 IGNACK [1:1] Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave. IGNACK=1 The master transmitter will ignore a NACK received from the slave. 1 1 BCM [0:0] Backward Compatibility Mode. This bit affects the I2C interrupt behavior. Refer to appendix A for details. 1 0 0 ICPSC 0x30 32 I2C Prescaler register NU [31:8] Reserved. 24 8 IPSC7_IPSC0 [7:0] 8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module. This register must be initialized while the I2C is still in reset (IRS_=0). The value takes effect on the rising edge of IRS_. 8 0 0 ICPID1 0x34 32 I2C Peripheral ID register 1 NU [31:16] Reserved. 16 16 CLASS [15:8] Identifies the class of peripheral. This value should be 0x01 - (RW ) 8 8 REVISION [7:0] Identifies the revision level of the I2C. This value should be incremented each time the design is revised. - (RW ) 8 0 0 ICPID2 0x38 32 I2C Peripheral ID register 2 NU [31:8] Reserved. 24 8 TYPE [7:0] Identifies the type of peripheral. This value should be 0x05 - (RW ) 8 0 0 ICDMAC 0x3C 32 I2C DMA Control Register NU [31:2] Reserved. - (RW ) 30 2 TXDMAEN [1:1] Transmit DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICTEVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICTEVT_POR pin is never asserted. RXDMAEN=0: DMA transmit event is disabled. RXDMAEN=1: DMA transmit event is enabled. (Default) 1 1 RXDMAEN [0:0] Receive DMA enable. This bit controls the receive DMA event pin to the system. When this bit is 1 the DMA event is enabled and ICREVT_POR pin is asserted when the DMA transfer is required. When this bit is 0 the ICREVT_POR pin is never asserted. RXDMAEN=0: DMA receive event is disabled. RXDMAEN=1: DMA receive event is enabled. (Default) 1 0 0 I2C_RESERVED1 0x40 32 Reserved NU [31:0] Reserved. 32 0 0 I2C_RESERVED2 0x44 32 Reserved NU [31:0] Reserved. 32 0 0 ICPFUNC 0x48 32 I2C Pin Function register NU [31:1] Reserved. 31 1 PFUNC0 [0:0] Controls the function of the I2C SCL and SDA pins. 0 = Pins function as SCL and SDA 1 = Pins functions as GPIO Note: No hardware protection is required to disable I2C function when the PFUNC[0] and IRS_ bits are both set to one. When PFUNC[0] is"1" (GPIO mode) the sub-module which controls the I2C function receives the value"1" for SCL and SDA. IRS_ can be set to"1" regardless of PFUNC[0] and the I2C function works whenever the IRS_ bit is"1". The user is expected to hold I2C in reset via IRS_ bit when changing to/from GPIO mode via the PFUNC[0] bit. 1 0 0 ICPDIR 0x4C 32 I2C Pin Direction register NU [31:2] Reserved 30 2 PDIR1 [1:1] Controls the direction of the I2C SDA pin when configured as GPIO. 0 = SDA pin functions as input 1 = SDA pin functions as output 1 1 PDIR0 [0:0] Controls the direction of the I2C SCL pin when configured as GPIO. 0 = SCL pin functions as input 1 = SCL pin functions as output 1 0 0 ICPDIN 0x50 32 I2C Pin Data In register NU [31:2] Reserved 30 2 PDIN1 [1:1] Indicates the logic level present on the SDA pin. Reads: 0 = Logic low present at SDA pin regardless of PFUNC setting. 1 = Logic high present at SDA pin regardless of PFUNC setting. Writes: Writes have no effect. - (RW ) 1 1 PDIN0 [0:0] Indicates the logic level present on the SCL pin. Reads: 0 = Logic low present at SCL pin regardless of PFUNC setting. 1 = Logic high present at SCL pin regardless of PFUNC setting. Writes: Writes have no effect - (RW ) 1 0 0 ICPDOUT 0x54 32 I2C Pin Data Out register NU [31:2] Reserved 30 2 PDOUT1 [1:1] Controls the level driven on the SDA pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SDA pin driven low 1 = SDA pin driven high. Note: If SDA is connected to an open-drain buffer at the chiplevel the I2C cannot drive SDA to high. 1 1 PDOUT0 [0:0] Controls the level driven on the SCL pin when configured as GPIO output. Reads: Reads return register values not GPIO pin levels. Writes: 0 = SCL pin driven low 1 = SCL pin driven high Note: If SCL is connected to an open-drain buffer at the chiplevel the I2C cannot drive SCL to high. 1 0 0 ICPDSET 0x58 32 I2C Pin Data Set register NU [31:2] Reserved 30 2 PDSET1 [1:1] Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is set to logic high. 1 1 PDSET0 [0:0] Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is set to logic high. 1 0 0 ICPDCLR 0x5C 32 I2C Pin Data Clear register NU [31:2] Reserved 30 2 PDCLR1 [1:1] Used to clear PDOUT[1] bit which corresponds to the SDA pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[1] bit is cleared to logic low. 1 1 PDCLR0 [0:0] Used to clear PDOUT[0] bit which corresponds to the SCL pin. Reads: Reads should return 0. User documentation should say reads are indeterminate. Writes: 0 = no effect 1 = PDOUT[0] bit is cleared to logic low. 1 0 0 ICPDRV 0x60 32 I2C Pin Driver Mode Register NU [31:2] Reserved 30 2 PDRV1 [1:1] Used to select driver mode of output buffer for SDA pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SDA_POR port. Actual function depends on I/O buffer and chip implementation. 1 1 PDRV0 [0:0] Used to select driver mode of output buffer for SCL pin. 0 = I2C mode. 1 = GPIO mode. Note: Value of this register is reflected on the PDRV_SCL_POR port. Actual function depends on I/O buffer and chip implementation. 1 0 0 APP_PWM 0x57F7FC00 0 116 registers APP_PWM TBCTL_TBSTS 0x0 32 Time-Base Control Register/ Status Register Reserved [31:19] Reserved 13 19 TBSTS_CTRMAX [18:18] Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value. Write: No effect. 1 Read: Indicates that the time-base counter reached the maximum value 0xFFFF. Write: Clears the latched event. 1 18 TBSTS_SYNCI [17:17] Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred. Write: No effect. 1 Read: Indicates that an external synchronization event has occurred (EPWMxSYNCI). Write: Clears the latched event. 1 17 TBSTS_CTRDIR [16:16] Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via TBCTL[CTRMODE]. 0 Time-Base Counter is currently counting down. 1 Time-Base Counter is currently counting up. 1 16 TBCTL_FREE,_SOFT [15:14] Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0 Stop after the next time-base counter increment or decrement 1h Stop when counter completes a whole cycle: • Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD) • Down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) • Up-down-count mode: stop when the time-base counter = 0x0000 (TBCTR = 0x0000) 2h-3h Free run 2 14 TBCTL_PHSDIR [13:13] Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization event occurs and a new phase value is loaded from the phase (TBPHS) register. This is irrespective of the direction of the counter before the synchronization event.. In the up-count and down-count modes this bit is ignored. 0 Count down after the synchronization event. 1 Count up after the synchronization event 1 13 TBCTL_CLKDIV [12:10] Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value. TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128 3 10 TBCTL_HSPCLKDIV [9:7] High Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value: TBCLK = VCLK3 / (HSPCLKDIV � CLKDIV) 0 /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14 3 7 TBCTL_SWFSYNC [6:6] Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0. 1 Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00. 1 6 TBCTL_SYNCOSEL [5:4] Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0 EPWMxSYNC: 1h CTR = zero: Time-base counter equal to zero (TBCTR = 0x0000) 2h CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB) 3h Disable EPWMxSYNCO signal 2 4 TBCTL_PRDLD [3:3] Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter, TBCTR, is equal to zero. A write or read to the TBPRD register accesses the shadow register. 1 Load the TBPRD register immediately without using a shadow register. A write or read to the TBPRD register directly accesses the active register. 1 3 TBCTL_PHSEN [2:2] Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit, or when a digital compare sync event occurs. 1 2 TBCTL_CTRMODE [1:0] Counter Mode The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0 Up-count mode 1h Down-count mode 2h Up-down-count mode 3h Stop-freeze counter operation (default on reset) 2 0 0 TBPHS 0x4 32 Time-Base Phase Register TBPHS [31:16] Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. • If TBCTL[PHSEN] = 0, then the synchronization event is ignored and the time-base counter is not loaded with the phase. • If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a synchronization event occurs. The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization. 16 16 Reserved [15:0] Reserved 16 0 0 TBCTR_TBPRD 0x8 32 Time-Base Counter Register/ Period Register TBPRD [31:16] Time-Base Period Register These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed. • If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the active register will be loaded from the shadow register when the timebase counter equals zero. • If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. • The active and shadow registers share the same memory map address. 16 16 TBCTR [15:0] Time-Base Counter Register Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed. 16 0 0 CMPCTL 0xC 32 Counter-Compare Control Register Reserved4 [31:26] Reserved 6 26 SHDWBFULL [25:25] Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs. 0 CMPB shadow FIFO not full yet 1 Indicates the CMPB shadow FIFO is full; a CPU write will overwrite current shadow value. 1 25 SHDWAFULL [24:24] Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self clears once a load-strobe occurs. 0 CMPA shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value 1 24 Reserved3 [23:23] Reserved 1 23 SHDWBMODE [22:22] Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action. 1 22 Reserved2 [21:21] Reserved 1 21 SHDWAMODE [20:20] Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 1 Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action 1 20 LOADBMODE [19:18] Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible) 2 18 LOADAMODE [17:16] Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in immediate mode (CMPCTL[SHDWAMODE] = 1). 0 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000) 1h Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) 2h Load on either CTR = Zero or CTR = PRD 3h Freeze (no loads possible) 2 16 Reserved1 [15:0] Reserved 16 0 0 CMPA 0x10 32 Counter-Compare A Register CMPA [31:16] Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare A" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: • Do nothing; the event is ignored. • Clear: Pull the EPWMxA and/or EPWMxB signal low • Set: Pull the EPWMxA and/or EPWMxB signal high • Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this register is shadowed. • If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event will load the active register from the shadow register. • Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is currently full. • If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. • In either mode, the active and shadow registers share the same memory map address. 16 16 Reserved [15:0] Reserved 16 0 0 CMPB_AQCTLA 0x14 32 Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA) Reserved [31:28] Reserved 4 28 AQCTLA_CBD [27:26] Action when the time-base counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low 2 26 AQCTLA_CBU [25:24] Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low 2 24 AQCTLA_CAD [23:22] Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low 2 22 AQCTLA_CAU [21:20] Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low 2 20 AQCTLA_PRD [19:18] Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low 2 18 AQCTLA_ZRO [17:16] Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxA output low. 2h Set: force EPWMxA output high. 3h Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low 2 16 CMPB [15:0] The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare B" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: • Do nothing. event is ignored. • Clear: Pull the EPWMxA and/or EPWMxB signal low • Set: Pull the EPWMxA and/or EPWMxB signal high • Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL[SHDWBMODE] bit. By default this register is shadowed. • If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL[LOADBMODE] bit field determines which event will load the active register from the shadow register: • Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow register is currently full. • If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. • In either mode, the active and shadow registers share the same memory map address 16 0 0 AQCTLB_AQSFRC 0x18 32 Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register Reserved1 [31:24] Reserved 8 24 AQSFRC_RLDCSF [23:22] AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register). 2 22 AQSFRC_OTSFB [21:21] One-Time Software Forced Event on Output B 0 Writing a 0 has no effect. Always reads back a 0 This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated.) This is a one-shot forced event. It can be overridden by another subsequent event on output B. 1 Initiates a single s/w forced event 1 21 AQSFRC_ACTSFB [20:19] Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High, High -> Low) Note: This action is not qualified by counter direction (CNT_dir) 2 19 AQSFRC_OTSFA [18:18] One-Time Software Forced Event on Output A 0 Writing a 0 has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 1 Initiates a single software forced event 1 18 AQSFRC_ACTSFA [17:16] Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir) 2 16 Reserved2 [15:12] Reserved 4 12 AQCTLB_CBD [11:10] Action when the counter equals the active CMPB register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low 2 10 AQCTLB_CBU [9:8] Action when the counter equals the active CMPB register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low 2 8 AQCTLB_CAD [7:6] Action when the counter equals the active CMPA register and the counter is decrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low 2 6 AQCTLB_CAU [5:4] Action when the counter equals the active CMPA register and the counter is incrementing. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low 2 4 AQCTLB_PRD [3:2] Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low 2 2 AQCTLB_ZRO [1:0] Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0 Do nothing (action disabled) 1h Clear: force EPWMxB output low. 2h Set: force EPWMxB output high. 3h Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. 2 0 0 AQCSFRC_DBCTL 0x1C 32 Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set DBCTL_HALFCYCLE [31:31] Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate. 1 Half cycle clocking enabled. The dead-band counters are clocked at TBCLK � 2. 1 31 Reserved1 [30:22] Reserved 9 22 DBCTL_IN_MODE [21:20] Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays. 0 EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 1h EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 2h EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 3h EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal. 2 20 DBCTL_POLSEL [19:18] Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0,0. Other enhanced modes are also possible, but not regarded as typical usage modes. 0 Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 1h Active low complementary (ALC) mode. EPWMxA is inverted. 2h Active high complementary (AHC). EPWMxB is inverted. 3h Active low (AL) mode. Both EPWMxA and EPWMxB are inverted 2 18 DBCTL_OUT_MODE [17:16] Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0 Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 1h Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE]. 2h The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by DBCTL[IN_MODE]. Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. 3h Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE]. 2 16 Reserved2 [15:4] Reserved 12 4 AQCSFRC_CSFB [3:2] Continuous Software Force on Output B In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use AQSFRC[RLDCSF]. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output B 2h Forces a continuous high on output B 3h Software forcing is disabled and has no effect 2 2 AQCSFRC_CSFA [1:0] Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0 Forcing disabled, that is, has no effect 1h Forces a continuous low on output A 2h Forces a continuous high on output A 3h Software forcing is disabled and has no effect 2 0 0 DBRED_DBFED 0x20 32 Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register Reserved1 [31:26] Reserved 6 26 DBFED_DEL [25:16] Falling Edge Delay Count. 10-bit counter 10 16 Reserved2 [15:10] Reserved 6 10 DBRED_DEL [9:0] Rising Edge Delay Count. 10-bit counter 10 0 0 TZSEL_TZDCSEL 0x24 32 Trip Zone Digital Compare Select Register/ Trip-Zone Select Register Reserved1 [31:28] Reserved 4 28 TZDCSEL_DCBEVT2 [27:25] Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved 3 25 TZDCSEL_DCBEVT1 [24:22] Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low, DCBL = don't care 2h DCBH = high, DCBL = don't care 3h DCBL = low, DCBH = don't care 4h DCBL = high, DCBH = don't care 5h DCBL = high, DCBH = low 6h-7h Reserved 3 22 TZDCSEL_DCAEVT2 [21:19] Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved 3 19 TZDCSEL_DCAEVT1 [18:16] Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low, DCAL = don't care 2h DCAH = high, DCAL = don't care 3h DCAL = low, DCAH = don't care 4h DCAL = high, DCAH = don't care 5h DCAL = high, DCAH = low 6h-7h Reserved 3 16 TZSEL_DCBEVT1 [15:15] Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCBEVT1 as one-shot-trip source for this ePWM module 1 15 TZSEL_DCAEVT1 [14:14] Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module. 1 Enable DCAEVT1 as one-shot-trip source for this ePWM module 1 14 TZSEL_OSHT6 [13:13] Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module. 1 Enable TZ6 as a one-shot trip source for this ePWM module 1 13 TZSEL_OSHT5 [12:12] Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module 1 12 TZSEL_OSHT4 [11:11] Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module 1 11 TZSEL_OSHT3 [10:10] Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module 1 10 TZSEL_OSHT2 [9:9] Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module 1 9 TZSEL_OSHT1 [8:8] Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module 1 8 TZSEL_DCBEVT2 [7:7] Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module 1 7 TZSEL_DCAEVT2 [6:6] Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module 1 6 TZSEL_CBC6 [5:5] Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module 1 5 TZSEL_CBC5 [4:4] Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module 1 4 TZSEL_CBC4 [3:3] Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module 1 3 TZSEL_CBC3 [2:2] Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module 1 2 TZSEL_CBC2 [1:1] Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module 1 1 TZSEL_CBC1 [0:0] Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module 1 0 0 TZCTL_TZEINT 0x28 32 Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register Reserved3 [31:23] Reserved 9 23 TZEINT_DCBEVT2 [22:22] Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled 1 22 TZEINT_DCBEVT1 [21:21] Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled 1 21 TZEINT_DCAEVT2 [20:20] Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled 1 20 TZEINT_DCAEVT1 [19:19] Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled 1 19 TZEINT_OST [18:18] Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt 1 18 TZEINT_CBC [17:17] Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation. 1 Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT VIM interrupt 1 17 Reserved2 [16:16] Reserved 1 16 Reserved1 [15:12] Reserved 4 12 TZCTL_DCBEVT2 [11:10] Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled 2 10 TZCTL_DCBEVT1 [9:8] Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state. 2h Force EPWMxB to a low state. 3h Do Nothing, trip action is disabled 2 8 TZCTL_DCAEVT2 [7:6] Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled 2 6 TZCTL_DCAEVT1 [5:4] Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state. 2h Force EPWMxA to a low state. 3h Do Nothing, trip action is disabled 2 4 TZCTL_TZB [3:2] When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state 2h Force EPWMxB to a low state 3h Do nothing, no action is taken on EPWMxB. 2 2 TZCTL_TZA [1:0] When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register. 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing, no action is taken on EPWMxA 2 0 0 TZFLG_TZCLR 0x2C 32 Trip-Zone Flag Register/ Trip-Zone Clear Register Reserved1 [31:23] Reserved 9 23 TZCLR_DCBEVT2 [22:22] Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT2 event trip condition. 1 22 TZCLR_DCBEVT1 [21:21] Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCBEVT1 event trip condition 1 21 TZCLR_DCAEVT2 [20:20] Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT2 event trip condition 1 20 TZCLR_DCAEVT1 [19:19] Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 clears the DCAEVT1 event trip condition. 1 19 TZCLR_OST [18:18] Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition. 1 18 TZCLR_CBC [17:17] Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect. Always reads back a 0. 1 Clears this Trip (set) condition. 1 17 TZCLR_INT [16:16] Global Interrupt Clear Flag 0 Has no effect. Always reads back a 0. 1 Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]). NOTE: No further EPWMx_TZINT VIM interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. 1 16 Reserved2 [15:7] Reserved 9 7 TZFLG_DCBEVT2 [6:6] Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2 1 6 TZFLG_DCBEVT1 [5:5] Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1 1 5 TZFLG_DCAEVT2 [4:4] Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2 1 4 TZFLG_DCAEVT1 [3:3] Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1 1 3 TZFLG_OST [2:2] Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred. 1 Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the TZCLR register 1 2 TZFLG_CBC [1:1] Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred. 1 Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The TZFLG[CBC] bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the signal is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the signal is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is cleared. This bit is cleared by writing the appropriate value to the TZCLR register 1 1 TZFLG_INT [0:0] Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated. 1 Indicates an EPWMx_TZINT VIM interrupt was generated because of a trip condition. No further EPWMx_TZINT VIM interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register 1 0 0 TZFRC_ETSEL 0x30 32 Trip-Zone Force Register / Event-Trigger Selection Register ETSEL_SOCBEN [31:31] Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB. 1 Enable EPWMxSOCB pulse 1 31 ETSEL_SOCBSEL [30:28] EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated. 0 Enable DCBEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing 3 28 ETSEL_SOCAEN [27:27] Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA. 1 Enable EPWMxSOCA pulse. 1 27 ETSEL_SOCASEL [26:24] EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated. 0 Enable DCAEVT1.soc event 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing 3 24 Reserved1 [23:20] Reserved 4 20 ETSEL_INTEN [19:19] Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation 1 19 ETSEL_INTSEL [18:16] ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero. (TBCTR = 0x0000) 2h Enable event time-base counter equal to period (TBCTR = TBPRD) 3h Enable event time-base counter equal to zero or period (TBCTR = 0x0000 or TBCTR = TBPRD). This mode is useful in up-down count mode. 4h Enable event time-base counter equal to CMPA when the timer is incrementing. 5h Enable event time-base counter equal to CMPA when the timer is decrementing. 6h Enable event: time-base counter equal to CMPB when the timer is incrementing. 7h Enable event: time-base counter equal to CMPB when the timer is decrementing. 3 16 Reserved3 [15:7] Reserved 9 7 TZFRC_DCBEVT2 [6:6] Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit. 1 6 TZFRC_DCBEVT1 [5:5] Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit 1 5 TZFRC_DCAEVT2 [4:4] Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect. This bit always reads back 0. 1 Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit 1 4 TZFRC_DCAEVT1 [3:3] Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect. This bit always reads back 0 1 Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit 1 3 TZFRC_OST [2:2] Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a one-shot trip event and sets the TZFLG[OST] bit 1 2 TZFRC_CBC [1:1] Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored. Always reads back a 0. 1 Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit. 1 1 Reserved2 [0:0] Reserved 1 0 0 ETPS_ETFLG 0x34 32 Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register Reserved2 [31:20] Reserved 12 20 ETFLG_SOCB [19:19] Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag bit is set. 1 19 ETFLG_SOCA [18:18] Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue to pulse even if the flag bit is set. 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA output will continue to be generated even if the flag bit is set 1 18 Reserved1 [17:17] Reserved 1 17 ETFLG_INT [16:16] Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG[INT] bit is still set. If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared 1 16 ETPS_SOCBCNT [15:14] ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred 2 14 ETPS_SOCBPRD [13:12] ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled (ETSEL[SOCBEN] = 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG[SOCB] = 1). Once the SOCB pulse is generated, the ETPS[SOCBCNT] bits will automatically be cleared. 0 Disable the SOCB event counter. No EPWMxSOCB pulse will be generated 1h Generate the EPWMxSOCB pulse on the first event: ETPS[SOCBCNT] = 0,1 2h Generate the EPWMxSOCB pulse on the second event: ETPS[SOCBCNT] = 1,0 3h Generate the EPWMxSOCB pulse on the third event: ETPS[SOCBCNT] = 1,1 2 12 ETPS_SOCACNT [11:10] ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred. 2 10 ETPS_SOCAPRD [9:8] ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled (ETSEL[SOCAEN] = 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG[SOCA] = 1). Once the SOCA pulse is generated, the ETPS[SOCACNT] bits will automatically be cleared. 0 Disable the SOCA event counter. No EPWMxSOCA pulse will be generated 1h Generate the EPWMxSOCA pulse on the first event: ETPS[SOCACNT] = 0,1 2h Generate the EPWMxSOCA pulse on the second event: ETPS[SOCACNT] = 1,0 3h Generate the EPWMxSOCA pulse on the third event: ETPS[SOCACNT] = 1,1 2 8 Reserved3 [7:4] Reserved 4 4 ETPS_INTCNT [3:2] ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD]. 0 No events have occurred. 1h 1 event has occurred. 2h 2 events have occurred. 3h 3 events have occurred. 2 2 ETPS_INTPRD [1:0] ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt status flag is set from a previous interrupt (ETFLG[INT] = 1) then no interrupt will be generated until the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETPS[INTCNT] bits will automatically be cleared. Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear. Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented. 0 Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored. 1h Generate an interrupt on the first event INTCNT = 01 (first event) 2h Generate interrupt on ETPS[INTCNT] = 1,0 (second event) 3h Generate interrupt on ETPS[INTCNT] = 1,1 (third event) 2 0 0 ETCLR_ETFRC 0x38 32 Event-Trigger Clear Register/ Event-Trigger Force Register Reserved4 [31:20] Reserved 12 20 ETFRC_SOCB [19:19] SOCB Force Bit. The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0 Has no effect. Always reads back a 0. 1 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit. This bit is used for test purposes 1 19 ETFRC_SOCA [18:18] SOCA Force Bit. The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes 1 18 Reserved3 [17:17] Reserved 1 17 ETFRC_INT [16:16] INT Force Bit. The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0 Writing 0 to this bit will be ignored. Always reads back a 0. 1 Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes 1 16 Reserved2 [15:4] Reserved 12 4 ETCLR_SOCB [3:3] ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCB] flag bit 1 3 ETCLR_SOCA [2:2] ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[SOCA] flag bit 1 2 Reserved1 [1:1] Reserved 1 1 ETCLR_INT [0:0] ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect. Always reads back a 0 1 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated 1 0 0 PCCTL 0x3C 32 PWM-Chopper Control Register Reserved [31:11] Reserved 21 11 CHPDUTY [10:8] Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved 3 8 CHPFREQ [7:5] Chopping Clock Frequency 0 Divide by 1 (no prescale, = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz VCLK3) 5h Divide by 6 (2.08 MHz at 100 MHz VCLK3) 6h Divide by 7 (1.78 MHz at 100 MHz VCLK3) 7h Divide by 8 (1.56 MHz at 100 MHz VCLK3) 3 5 OSHTWTH [4:1] One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide ( = 400 nS at 100 MHz VCLK3) 5h 6 x VCLK3 / 8 wide ( = 480 nS at 100 MHz VCLK3) 6h 7 x VCLK3 / 8 wide ( = 560 nS at 100 MHz VCLK3) 7h 8 x VCLK3 / 8 wide ( = 640 nS at 100 MHz VCLK3) 8h 9 x VCLK3 / 8 wide ( = 720 nS at 100 MHz VCLK3) 9h 10 x VCLK3 / 8 wide ( = 800 nS at 100 MHz VCLK3) Ah 11 x VCLK3 / 8 wide ( = 880 nS at 100 MHz VCLK3) Bh 12 x VCLK3 / 8 wide ( = 960 nS at 100 MHz VCLK3) Ch 13 x VCLK3 / 8 wide ( = 1040 nS at 100 MHz VCLK3) Dh 14 x VCLK3 / 8 wide ( = 1120 nS at 100 MHz VCLK3) Eh 15 x VCLK3 / 8 wide ( = 1200 nS at 100 MHz VCLK3) Fh 16 x VCLK3 / 8 wide ( = 1280 nS at 100 MHz VCLK3) 4 1 CHPEN [0:0] PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function 1 0 0 Reserved1 0x40 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved2 0x44 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved3 0x48 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved4 0x4C 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved5 0x50 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved6 0x54 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved7 0x58 32 Reserved Reserved [31:0] Reserved 32 0 0 Reserved8 0x5C 32 Reserved Reserved [31:0] Reserved 32 0 0 DCTRIPSEL_DCACTL 0x60 32 Digital Compare Trip Select Register/ Digital Compare A Control Register Reserved2 [31:26] Reserved 6 26 DCACTL_EVT2FRC_SYNCSEL [25:25] DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal 1 25 DCACTL_EVT2SRCSEL [24:24] DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal 1 24 Reserved1 [23:20] Reserved 4 20 DCACTL_EVT1SYNCE [19:19] DCAEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled 1 19 DCACTL_EVT1SOCE [18:18] DCAEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled 1 18 DCACTL_EVT1FRC_SYNCSEL [17:17] DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal 1 17 DCACTL_EVT1SRCSEL [16:16] DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal 1 16 DCTRIPSEL_DCBLCOMPSEL [15:12] Digital Compare B Low Input Select Defines the source for the DCBL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved. 4 12 DCTRIPSEL_DCBHCOMPSEL [11:8] Digital Compare B High Input Select Defines the source for the DCBH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved. 4 8 DCTRIPSEL_DCALCOMPSEL [7:4] Digital Compare A Low Input Select Defines the source for the DCAL input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved. 4 4 DCTRIPSEL_DCAHCOMPSEL [3:0] Digital Compare A High Input Select Defines the source for the DCAH input. The TZ signals, when used as trip signals, are treated as normal inputs and can be defined as active high or active low. 0 TZ1 input 1h TZ2 input 2h TZ3 input All other values Values not shown are reserved. If a device does not have a particular comparitor, then that option is reserved. 4 0 0 DCBCTL_DCFCTL 0x64 32 Digital Compare B Control Register/ Digital Compare Filter Control Register Reserved3 [31:22] Reserved 10 22 DCFCTL_PULSESEL [21:20] Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved 2 20 DCFCTL_BLANKINV [19:19] Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted 1 19 DCFCTL_BLANKE [18:18] Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled 1 18 DCFCTL_SRCSEL [17:16] Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal 2 16 Reserved2 [15:10] Reserved 6 10 DCBCTL_EVT2FRC_SYNCSEL [9:9] DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal 1 9 DCBCTL_EVT2SRCSEL [8:8] DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal 1 8 Reserved1 [7:4] Reserved 4 4 DCBCTL_EVT1SYNCE [3:3] DCBEVT1 SYNC, Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled 1 3 DCBCTL_EVT1SOCE [2:2] DCBEVT1 SOC, Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled 1 2 DCBCTL_EVT1FRC_SYNCSEL [1:1] DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal 1 1 DCBCTL_EVT1SRCSEL [0:0] DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal 1 0 0 DCCAPCTL_DCFOFFSET 0x68 32 Digital Compare Capture Control Register/ Digital Compare Filter Offset Register DCFOFFSET_OFFSET [31:16] Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the DCFCTL[PULSESEL] bit. This offset register is shadowed and the active register is loaded at the reference point defined by DCFCTL[PULSESEL]. The offset counter is also initialized and begins to count down when the active register is loaded. When the counter expires, the blanking window is applied. If the blanking window is currently active, then the blanking window counter is restarted. 16 16 Reserved [15:2] Reserved 14 2 DCCAPCTL_SHDWMODE [1:1] TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return the shadow register contents. 1 Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will always return the active register contents 1 1 DCCAPCTL_CAPE [0:0] TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture. 1 Enable the time-base counter capture. 1 0 0 DCFOFFSETCNT_DCFWINDOW 0x6C 32 Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register Reserved1 [31:24] Reserved 8 24 DCFWINDOW_WINDOW [23:16] Blanking Window Width 0 No blanking window is generated. 1h-FFh Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs, the window counter is loaded and begins to count down. If the blanking window is currently active and the offset counter expires, the blanking window counter is restarted. The blanking window can cross a PWM period boundary. 8 16 DCFOFFSETCNT_OFFSETCNT [15:0] Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the DCFCTL[PULSESEL] bit. The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop. 16 0 0 DCFWINDOWCNT_DCCAP 0x70 32 Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register DCCAP [31:16] Digital Compare Time-Base Counter Capture To enable time-base counter capture, set the DCCAPCLT[CAPE] bit to 1. If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event. Further capture events are ignored until the next period or zero as selected by the DCFCTL[PULSESEL] bit. Shadowing of DCCAP is enabled and disabled by the DCCAPCTL[SHDWMODE] bit. By default this register is shadowed. • If DCCAPCTL[SHDWMODE] = 0, then the shadow is enabled. In this mode, the active register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the DCFCTL[PULSESEL] bit. CPU reads of this register will return the shadow register value. • If DCCAPCTL[SHDWMODE] = 1, then the shadow register is disabled. In this mode, CPU reads will return the active register value. The active and shadow registers share the same memory map address. 16 16 Reserved1 [15:8] Reserved 8 8 DCFWINDOWCNT [7:0] 0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again. 8 0 0 TOP_IO_MUX 0x5A000000 0 112 registers TOP_IO_MUX PADAA_cfg_reg 0x0 32 PADAA_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAB_cfg_reg 0x4 32 PADAB_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAC_cfg_reg 0x8 32 PADAC_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAD_cfg_reg 0xC 32 PADAD_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAE_cfg_reg 0x10 32 PADAE_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAF_cfg_reg 0x14 32 PADAF_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAG_cfg_reg 0x18 32 PADAG_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAH_cfg_reg 0x1C 32 PADAH_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAI_cfg_reg 0x20 32 PADAI_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAJ_cfg_reg 0x24 32 PADAJ_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAK_cfg_reg 0x28 32 PADAK_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAL_cfg_reg 0x2C 32 PADAL_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAM_cfg_reg 0x30 32 PADAM_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAN_cfg_reg 0x34 32 PADAN_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAO_cfg_reg 0x38 32 PADAO_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAP_cfg_reg 0x3C 32 PADAP_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAQ_cfg_reg 0x40 32 PADAQ_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAR_cfg_reg 0x44 32 PADAR_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAS_cfg_reg 0x48 32 PADAS_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAT_cfg_reg 0x4C 32 PADAT_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAU_cfg_reg 0x50 32 PADAU_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAV_cfg_reg 0x54 32 PADAV_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAW_cfg_reg 0x58 32 PADAW_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 PADAX_cfg_reg 0x5C 32 PADAX_cfg_reg NU [31:11] Reserved 21 11 sc1 [10:10] IO Slew rate control : 0 : higher slew rate. 1: Lower slew rate. 1 10 pupdsel [9:9] Pullup/PullDown Selection 0 -- Pull Down 1 9 pi [8:8] Pull Inhibit/Pull Disable 0 -- Enable 1 8 oe_override [7:7] Active Low Output Override, 0: Output is enabled 1: Output disabled 1 7 oe_override_ctrl [6:6] Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware 1 6 ie_override [5:5] Input Override, 1: Input is enabled 0: input disabled (mask the value from the PAD and send only 0 to the core) 1 5 ie_override_ctrl [4:4] Control to select IE_OVERRIDE : Write 1 to select Override value (IE_OVERRIDE) to control IOs RXACTIVE instead of the control from hardware 1 4 func_sel [3:0] Function select 4 0 0 USERMODEEN 0x60 32 USERMODEEN USERMODEEN [31:0] Write 0XADADADAD to enable user mode write access to IO CFG space 32 0 0 PADGLBLCFGREG 0x64 32 PADGLBLCFGREG PADGLBLCFGREG [31:0] 2:0 : global_ie_n_ctl - Write 3'b111 to pass global_ie_n_val to IE_N/RXACTIVE_N pin of all the IOs. 3 : global_ie_n_val - Active low 10:8 : global_oe_n_ctl - Write 3'b111 to pass global_oe_n_val to OE_N/GZ pin of all the IOs. 11 : global_oe_n_val - Active low 18:16 : global_pi_ctl - Write 3'b111 to pass global_pi_val and global_pu_val to all the IOs 19 : global_pi_val 20 : global_pu_val 32 0 0 IOCFGKICK0 0x68 32 IOCFGKICK0 IOCFGKICK0 [31:0] Kicker 0 Register. The value 83E7 0B13h must be written to KICK0 as part of the process to unlock the CPU write access to the above PIN MUX registers (including IOCFGKICK1) 32 0 0 IOCFGKICK1 0x6C 32 IOCFGKICK1 IOCFGKICK1 [31:0] Kicker 1 Register. The value 95A4 F1E0h must be written to the KICK1 as part of the process to unlock the CPU write access to above PINMUX registers (excluding IOCFGKICK0). IOCFGKICK0 has to be written with 83E70B13h to enable access to IOCFGKICK1. 32 0 0 APP_PRCM 0x5A040000 0 7216 registers PID 0x0 32 PID register 16 16 5 11 3 8 2 6 6 0 0 CPUCLKCTL 0x4 32 CPUCLKCTL currclk [31:24] Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK 8 24 currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 srcsel [3:0] Slect the source clock:#br#0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected. 4 0 0 CANCLKCTL 0x8 32 CANCLKCTL currclk [31:24] Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK 8 24 currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 srcsel [3:0] 0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected. 4 0 0 SPICLKCTL 0xC 32 SPICLKCTL currclk [31:24] Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK 8 24 currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 srcsel [3:0] 0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected. 4 0 0 QSPICLKCTL 0x10 32 QSPICLKCTL currclk [31:24] Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK 8 24 currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 srcsel [3:0] 0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected. 4 0 0 TOPSSCLKCTL 0x14 32 TOPSSCLKCTL currclk [31:24] Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK 8 24 currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 srcsel [3:0] 0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected. 4 0 0 RTICLKCTL 0x18 32 RTICLKCTL currclk [31:24] Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK 8 24 currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 srcsel [3:0] 0x0 : XTALCLK#br#0x1 : REFCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected. 4 0 0 WDTCLKCTL 0x1C 32 WDTCLKCTL currclk [31:24] Current Clock selected by GCM Clock Mux#br#0x1 : XTALCLK#br#0x2 : XTALCLKX2#br#0x4 : MDLL#br#0x8 : APLL/DPLL#br#0x10 : RCCLK 8 24 currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 srcsel [3:0] 0x0 : XTALCLK#br#0x1 : XTALCLKX2#br#0x2 : MDLL#br#0x3 : APLL/DPLL#br#0x4 : RCCLK#br#For other values if the lower 3 bits matches with above, corresponding clock is selected. 4 0 0 UART1CLKCTL 0x20 32 UART1CLKCTL currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 0 UART2CLKCTL 0x24 32 UART2CLKCTL currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 0 I2CCLKCTL 0x28 32 I2CCLKCTL currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 0 LINCLKCTL 0x2C 32 LINCLKCTL currdivr [19:16] Gives the current divr setting used by the clock divider. 4 16 switchen [12:12] 1'b1 : Switch to the new divide ratio set by divr bits above. This happens when output clock of the divider is transitioning from 0->1, 1 12 divr [11:8] Divide value#br#0x0 : div1#br#0x1 : div2#br#0x2 : div3#br#.#br#.#br#0xF = div16 4 8 gate [7:4] 0x0 : Enable the Clock#br#0x7 : Gate the clock 4 4 0 RESERVED0 0x30 32 RESERVED0 wphres 8 24 rores 8 8 rwres 8 0 0 RESERVED1 0x34 32 RESERVED1 wphres 8 24 rores 8 8 rwres 8 0 0 RESERVED2 0x38 32 RESERVED2 wphres 8 24 rores 8 8 rwres 8 0 0 RESERVED3 0x3C 32 RESERVED3 wphres 8 24 rores 8 8 rwres 8 0 0 VBUSCLKGATE0 0x40 32 VBUSCLKGATE0 i2c [29:27] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 27 dcc [26:24] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 24 wdt [23:21] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 21 rti [20:18] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 18 esm [17:15] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 15 tpcc [14:12] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 12 tptc2 [11:9] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 9 tptc1 [8:6] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 6 qspi [5:3] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 3 xbara [2:0] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 0 0 VBUSCLKGATE1 0x44 32 VBUSCLKGATE1 res [29:27] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 27 ctrl_reg [26:24] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 24 crc [23:21] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 21 pwm [20:18] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 18 lin [17:15] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 15 can [14:12] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 12 spi2 [11:9] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 9 spi1 [8:6] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 6 uart2 [5:3] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 3 uart1 [2:0] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 0 0 VBUSCLKGATE2 0x48 32 VBUSCLKGATE2 res5 [29:27] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 27 res4 [26:24] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 24 res3 [23:21] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 21 res2 [20:18] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 18 res1 [17:15] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 15 res0 [14:12] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 12 pcr6 [11:9] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 9 pcr5 [8:6] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 6 pcr4 [5:3] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 3 pcr3 [2:0] 0x0 : Enable the Clock#br#0x7 : Gate the clock 3 0 0 BLOCKRESET0 0x4C 32 BLOCKRESET0 i2c [29:27] 0x0 : Release the reset#br#0x7 : Assert the reset 3 27 dcc [26:24] 0x0 : Release the reset#br#0x7 : Assert the reset 3 24 wdt [23:21] 0x0 : Release the reset#br#0x7 : Assert the reset 3 21 rti [20:18] 0x0 : Release the reset#br#0x7 : Assert the reset 3 18 esm [17:15] 0x0 : Release the reset#br#0x7 : Assert the reset 3 15 tpcc [14:12] 0x0 : Release the reset#br#0x7 : Assert the reset 3 12 tptc2 [11:9] 0x0 : Release the reset#br#0x7 : Assert the reset 3 9 tptc1 [8:6] 0x0 : Release the reset#br#0x7 : Assert the reset 3 6 qspi [5:3] 0x0 : Release the reset#br#0x7 : Assert the reset 3 3 res [2:0] 0x0 : Release the reset#br#0x7 : Assert the reset 3 0 0 BLOCKRESET1 0x50 32 BLOCKRESET1 res [29:27] 0x0 : Release the reset#br#0x7 : Assert the reset 3 27 ctrl_reg [26:24] 0x0 : Release the reset#br#0x7 : Assert the reset 3 24 crc [23:21] 0x0 : Release the reset#br#0x7 : Assert the reset 3 21 pwm [20:18] 0x0 : Release the reset#br#0x7 : Assert the reset 3 18 lin [17:15] 0x0 : Release the reset#br#0x7 : Assert the reset 3 15 can [14:12] 0x0 : Release the reset#br#0x7 : Assert the reset 3 12 spi2 [11:9] 0x0 : Release the reset#br#0x7 : Assert the reset 3 9 spi1 [8:6] 0x0 : Release the reset#br#0x7 : Assert the reset 3 6 uart2 [5:3] 0x0 : Release the reset#br#0x7 : Assert the reset 3 3 uart1 [2:0] 0x0 : Release the reset#br#0x7 : Assert the reset 3 0 0 LOCK0_KICK0 0x1008 32 - KICK0 component [31:0] - KICK0 component 32 0 0 LOCK0_KICK1 0x100C 32 - KICK1 component [31:0] - KICK1 component 32 0 0 intr_raw_status 0x1010 32 Interrupt Raw Status/Set Register [3:3] Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 0 0 intr_enabled_status_clear 0x1014 32 Interrupt Enabled Status/Clear register [3:3] Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 0 0 intr_enable 0x1018 32 Interrupt Enable register [3:3] Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 0 0 intr_enable_clear 0x101C 32 Interrupt Enable Clear register [3:3] Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 0 0 eoi 0x1020 32 EOI register [7:0] EOI vector value. Write this with interrupt distribution value in the chip. 8 0 0 fault_address 0x1024 32 Fault Address register [31:0] Fault Address. 32 0 0 fault_type_status 0x1028 32 Fault Type Status register [6:6] Non-secure access. 1 6 [5:0] Fault Type #br# 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 #br# 01_0000 = Supervisor write fault - priv = 1 dir = 0 #br# 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 #br# 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 #br# 00_0010 = User write fault - priv = 0 dir = 0 #br# 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 #br# 00_0000 = No fault 6 0 0 fault_attr_status 0x102C 32 Fault Attribute Status register [31:20] XID. 12 20 [19:8] Route ID. 12 8 [7:0] Privilege ID. 8 0 0 fault_clear 0x1030 32 Fault Clear register [0:0] Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect. 1 0 0 TOP_GIO 0x5AF7FC00 0 340 registers TOP_GIO GIOGCR 0x0 32 GIO reset NU0 [31:1] Reserved 31 1 RESET [0:0] GIO reset 1 0 0 GIOPWDN 0x4 32 GIO power down mode register NU [31:1] Reserved 31 1 GIOPWDN [0:0] Writing to the GIOPWDN bit is only allowed in privilege mode. Reading of the GIOPWDN bit is allowed in all modes. Privilege mode (write): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode User mode (write): Writes have no effect in user mode. User or privilege mode (read): 0 = Normal operation; clocks enabled to GIO module 1 = Power-down mode 1 0 0 GIOINTDET 0x8 32 Interrupt detection select for pins [0:1] GIO[7:0]. GIOINTDET_3 [31:24] Interrupt detection select for pins GIOD[7:0]. 8 24 GIOINTDET_2 [23:16] Interrupt detection select for pins GIOC[7:0]. 8 16 GIOINTDET_1 [15:8] Interrupt detection select for pins GIOB[7:0]. 8 8 GIOINTDET_0 [7:0] Interrupt detection select for pins GIOA[7:0]. 8 0 0 GIOPOL 0xC 32 Interrupt polarity select for pins [0:1] GIO[7:0]. GIOPOL_3 [31:24] Interrupt polarity select for pins GIOD[7:0] 8 24 GIOPOL_2 [23:16] Interrupt polarity select for pins GIOC[7:0] 8 16 GIOPOL_1 [15:8] Interrupt polarity select for pins GIOB[7:0] 8 8 GIOPOL_0 [7:0] Interrupt polarity select for pins GIOA[7:0] 8 0 0 GIOENASET 0x10 32 Interrupt enable for pins [0:1] GIO[7:0]. GIOENASET_3 [31:24] Interrupt enable for pins GIOD [7:0] 8 24 GIOENASET_2 [23:16] Interrupt enable for pins GIOC [7:0] 8 16 GIOENASET_1 [15:8] Interrupt enable for pins GIOB [7:0] 8 8 GIOENASET_0 [7:0] Interrupt enable for pins GIOA [7:0] 8 0 0 GIOENACLR 0x14 32 Interrupt enable for pins [0:1] GIO[7:0]. GIOENACLR_3 [31:24] Interrupt enable for pins GIOD [7:0] 8 24 GIOENACLR_2 [23:16] Interrupt enable for pins GIOC [7:0] 8 16 GIOENACLR_1 [15:8] Interrupt enable for pins GIOB [7:0] 8 8 GIOENACLR_0 [7:0] Interrupt enable for pins GIOA [7:0] 8 0 0 GIOLVLSET 0x18 32 GIO high priority interrupt for pins [0:1] GIO[7:0]. GIOLVLSET_3 [31:24] GIO high priority interrupt for pins GIOD[7:0] 8 24 GIOLVLSET_2 [23:16] GIO high priority interrupt for pins GIOC[7:0] 8 16 GIOLVLSET_1 [15:8] GIO high priority interrupt for pins GIOB[7:0] 8 8 GIOLVLSET_0 [7:0] GIO high priority interrupt for pins GIOA[7:0] 8 0 0 GIOLVLCLR 0x1C 32 GIO low priority interrupt for pins [0:1] GIO[7:0]. GIOLVLCLR_3 [31:24] GIO low priority interrupt for pins GIOD[7:0] 8 24 GIOLVLCLR_2 [23:16] GIO low priority interrupt for pins GIOC[7:0] 8 16 GIOLVLCLR_1 [15:8] GIO low priority interrupt for pins GIOB[7:0] 8 8 GIOLVLCLR_0 [7:0] GIO low priority interrupt for pins GIOA[7:0] 8 0 0 GIOFLG 0x20 32 GIO flag for pins [0:1] GIO[7:0]. GIOFLG_3 [31:24] GIO flag for pins GIOD[7:0] 8 24 GIOFLG_2 [23:16] GIO flag for pins GIOC[7:0] 8 16 GIOFLG_1 [15:8] GIO flag for pins GIOB[7:0] 8 8 GIOFLG_0 [7:0] GIO flag for pins GIOA[7:0] 8 0 0 GIOOFFA 0x24 32 Index bits for currently pending high-priority interrupt Register A NU1 [31:6] Reserved 26 6 GIOOFFA [5:0] Index bits for currently pending high-priority interrupt Register A 6 0 0 GIOOFFB 0x28 32 Index bits for currently pending high-priority interrupt Register B NU2 [31:6] Reserved 26 6 GIOOFFB [5:0] Index bits for currently pending high-priority interrupt Register B 6 0 0 GIOEMUA 0x2C 32 GIO emulation register A NU3 [31:6] Reserved 26 6 GIOEMUA [5:0] GIO emulation register A 6 0 0 GIOEMUB 0x30 32 GIO emulation register B NU4 [31:6] Reserved 26 6 GIOEMUB [5:0] GIO emulation register B 6 0 0 GIODIRA 0x34 32 GIO data direction of pins in Port A NU5 [31:8] Reserved 24 8 GIODIRA [7:0] GIO data direction of pins in Port A 8 0 0 GIODINA 0x38 32 GIO data input for pins in port A NU11 [31:8] Reserved 24 8 GIODINA [7:0] GIO data input for pins in port A 8 0 0 GIODOUTA 0x3C 32 GIO data output for pins in port A NU17 [31:8] Reserved 24 8 GIODOUTA [7:0] GIO data output for pins in port A 8 0 0 GIOSETA 0x40 32 GIO data set for port A NU23 [31:8] Reserved 24 8 GIODSETA [7:0] GIO data set for port A 8 0 0 GIOCLRA 0x44 32 GIO data clear for port A NU29 [31:8] Reserved 24 8 GIODCLRA [7:0] GIO data clear for port A 8 0 0 GIOPDRA 0x48 32 GIO open drain for port A NU35 [31:8] Reserved 24 8 GIOPDRA [7:0] GIO open drain for port A 8 0 0 GIOPULDISA 0x4C 32 GIO pul disable for port A NU [31:8] Reserved 24 8 GIOPULDISA [7:0] GIO pull disable for port A 8 0 0 GIOPSLA 0x50 32 GIO pul select for port A NU35 [31:8] Reserved 24 8 GIOPSLA [7:0] GIO pull select for port A 8 0 0 GIODIRB 0x54 32 GIO data direction of pins in Port B NU6 [31:8] Reserved 24 8 GIODIRB [7:0] GIO data direction of pins in Port B 8 0 0 GIODINB 0x58 32 GIO data input for pins in port B NU12 [31:8] Reserved 24 8 GIODINB [7:0] GIO data input for pins in port B 8 0 0 GIODOUTB 0x5C 32 GIO data output for pins in port B NU18 [31:8] Reserved 24 8 GIODOUTB [7:0] GIO data output for pins in port B 8 0 0 GIOSETB 0x60 32 GIO data set for port B NU24 [31:8] Reserved 24 8 GIODSETB [7:0] GIO data set for port B 8 0 0 GIOCLRB 0x64 32 GIO data clear for port B NU30 [31:8] Reserved 24 8 GIODCLRB [7:0] GIO data clear for port B 8 0 0 GIOPDRB 0x68 32 GIO open drain for port B NU36 [31:8] Reserved 24 8 GIOPDRB [7:0] GIO open drain for port B 8 0 0 GIOPULDISB 0x6C 32 GIO pul disable for port B NU36 [31:8] Reserved 24 8 GIOPULDISB [7:0] GIO pull disable for port B 8 0 0 GIOPSLB 0x70 32 GIO pul select for port B NU36 [31:8] Reserved 24 8 GIOPSLB [7:0] GIO pull select for port B 8 0 0 GIODIRC 0x74 32 GIO data direction of pins in Port C NU7 [31:8] Reserved 24 8 GIODIRC [7:0] GIO data direction of pins in Port C 8 0 0 GIODINC 0x78 32 GIO data input for pins in port C NU13 [31:8] Reserved 24 8 GIODINC [7:0] GIO data input for pins in port C 8 0 0 GIODOUTC 0x7C 32 GIO data output for pins in port C NU19 [31:8] Reserved 24 8 GIODOUTC [7:0] GIO data output for pins in port C 8 0 0 GIOSETC 0x80 32 GIO data set for port C NU25 [31:8] Reserved 24 8 GIODSETC [7:0] GIO data set for port C 8 0 0 GIOCLRC 0x84 32 GIO data clear for port C NU31 [31:8] Reserved 24 8 GIODCLRC [7:0] GIO data clear for port C 8 0 0 GIOPDRC 0x88 32 GIO open drain for port C NU37 [31:8] Reserved 24 8 GIOPDRC [7:0] GIO open drain for port C 8 0 0 GIOPULDISC 0x8C 32 GIO pul disable for port C NU37 [31:8] Reserved 24 8 GIOPULDISC [7:0] GIO pull disable for port C 8 0 0 GIOPSLC 0x90 32 GIO pul select for port C NU37 [31:8] Reserved 24 8 GIOPSLC [7:0] GIO pull select for port C 8 0 0 GIODIRD 0x94 32 GIO data direction of pins in Port D NU8 [31:8] Reserved 24 8 GIODIRD [7:0] GIO data direction of pins in Port D 8 0 0 GIODIND 0x98 32 GIO data input for pins in port D NU14 [31:8] Reserved 24 8 GIODIND [7:0] GIO data input for pins in port D 8 0 0 GIODOUTD 0x9C 32 GIO data output for pins in port D NU20 [31:8] Reserved 24 8 GIODOUTD [7:0] GIO data output for pins in port D 8 0 0 GIOSETD 0xA0 32 GIO data set for port D NU26 [31:8] Reserved 24 8 GIODSETD [7:0] GIO data set for port D 8 0 0 GIOCLRD 0xA4 32 GIO data clear for port D NU32 [31:8] Reserved 24 8 GIODCLRD [7:0] GIO data clear for port D 8 0 0 GIOPDRD 0xA8 32 GIO open drain for port D NU38 [31:8] Reserved 24 8 GIOPDRD [7:0] GIO open drain for port D 8 0 0 GIOPULDISD 0xAC 32 GIO pul disable for port D NU38 [31:8] Reserved 24 8 GIOPULDISD [7:0] GIO pull disable for port D 8 0 0 GIOPSLD 0xB0 32 GIO pul select for port D NU38 [31:8] Reserved 24 8 GIOPSLD [7:0] GIO pull select for port D 8 0 0 GIODIRE 0xB4 32 GIO data direction of pins in Port E NU9 [31:8] Reserved 24 8 GIODIRE [7:0] GIO data direction of pins in Port E 8 0 0 GIODINE 0xB8 32 GIO data input for pins in port E NU15 [31:8] Reserved 24 8 GIODINE [7:0] GIO data input for pins in port E 8 0 0 GIODOUTE 0xBC 32 GIO data output for pins in port E NU21 [31:8] Reserved 24 8 GIODOUTE [7:0] GIO data output for pins in port E 8 0 0 GIOSETE 0xC0 32 GIO data set for port E NU27 [31:8] Reserved 24 8 GIODSETE [7:0] GIO data set for port E 8 0 0 GIOCLRE 0xC4 32 GIO data clear for port E NU33 [31:8] Reserved 24 8 GIODCLRE [7:0] GIO data clear for port E 8 0 0 GIOPDRE 0xC8 32 GIO open drain for port E NU39 [31:8] Reserved 24 8 GIOPDRE [7:0] GIO open drain for port E 8 0 0 GIOPULDISE 0xCC 32 GIO pul disable for port E NU39 [31:8] Reserved 24 8 GIOPULDISE [7:0] GIO pull disable for port E 8 0 0 GIOPSLE 0xD0 32 GIO pul select for port E NU39 [31:8] Reserved 24 8 GIOPSLE [7:0] GIO pull select for port E 8 0 0 GIODIRF 0xD4 32 GIO data direction of pins in Port F NU10 [31:8] Reserved 24 8 GIODIRF [7:0] GIO data direction of pins in Port F 8 0 0 GIODINF 0xD8 32 GIO data input for pins in Port F NU16 [31:8] Reserved 24 8 GIODINF [7:0] GIO data input for pins in port F 8 0 0 GIODOUTF 0xDC 32 GIO data output for pins in Port F NU22 [31:8] Reserved 24 8 GIODOUTF [7:0] GIO data output for pins in port F 8 0 0 GIOSETF 0xE0 32 GIO data set for Port F NU28 [31:8] Reserved 24 8 GIODSETF [7:0] GIO data set for port F 8 0 0 GIOCLRF 0xE4 32 GIO data clear for Port F NU34 [31:8] Reserved 24 8 GIODCLRF [7:0] GIO data clear for port F 8 0 0 GIOPDRF 0xE8 32 GIO open drain for Port F NU40 [31:8] Reserved 24 8 GIOPDRF [7:0] GIO open drain for port F 8 0 0 GIOPULDISF 0xEC 32 GIO pul disable for port F NU40 [31:8] Reserved 24 8 GIOPULDISF [7:0] GIO pull disable for port F 8 0 0 GIOPSLF 0xF0 32 GIO pul select for port F NU40 [31:8] Reserved 24 8 GIOPSLF [7:0] GIO pull select for port F 8 0 0 GIODIRG 0xF4 32 GIO data direction of pins in Port G NU9 [31:8] Reserved 24 8 GIODIRG [7:0] GIO data direction of pins in Port G 8 0 0 GIODING 0xF8 32 GIO data input for pins in port G NU15 [31:8] Reserved 24 8 GIODING [7:0] GIO data input for pins in port G 8 0 0 GIODOUTG 0xFC 32 GIO data output for pins in port G NU21 [31:8] Reserved 24 8 GIODOUTG [7:0] GIO data output for pins in port G 8 0 0 GIOSETG 0x100 32 GIO data set for port G NU27 [31:8] Reserved 24 8 GIODSETG [7:0] GIO data set for port G 8 0 0 GIOCLRG 0x104 32 GIO data clear for port G NU33 [31:8] Reserved 24 8 GIODCLRG [7:0] GIO data clear for port G 8 0 0 GIOPDRG 0x108 32 GIO open drain for port G NU39 [31:8] Reserved 24 8 GIOPDRG [7:0] GIO open drain for port G 8 0 0 GIOPULDISG 0x10C 32 GIO pul disable for port G NU39 [31:8] Reserved 24 8 GIOPULDISG [7:0] GIO pull disable for port G 8 0 0 GIOPSLG 0x110 32 GIO pul select for port G NU39 [31:8] Reserved 24 8 GIOPSLG [7:0] GIO pull select for port G 8 0 0 GIODIRH 0x114 32 GIO data direction of pins in Port H NU10 [31:8] Reserved 24 8 GIODIRH [7:0] GIO data direction of pins in Port H 8 0 0 GIODINH 0x118 32 GIO data input for pins in Port H NU16 [31:8] Reserved 24 8 GIODINH [7:0] GIO data input for pins in port H 8 0 0 GIODOUTH 0x11C 32 GIO data output for pins in Port H NU22 [31:8] Reserved 24 8 GIODOUTH [7:0] GIO data output for pins in port H 8 0 0 GIOSETH 0x120 32 GIO data set for Port H NU28 [31:8] Reserved 24 8 GIODSETH [7:0] GIO data set for port H 8 0 0 GIOCLRH 0x124 32 GIO data clear for Port H NU34 [31:8] Reserved 24 8 GIODCLRH [7:0] GIO data clear for port H 8 0 0 GIOPDRH 0x128 32 GIO open drain for Port H NU40 [31:8] Reserved 24 8 GIOPDRH [7:0] GIO open drain for port H 8 0 0 GIOPULDISH 0x12C 32 GIO pul disable for port H NU40 [31:8] Reserved 24 8 GIOPULDISH [7:0] GIO pull disable for port H 8 0 0 GIOPSLH 0x130 32 GIO pul select for port H NU40 [31:8] Reserved 24 8 GIOPSLH [7:0] GIO pull select for port H 8 0 0 GIOSRCA 0x134 32 GIO slew rate select for port A NU35 [31:8] Reserved 24 8 GIOSRCA [7:0] GIO slew rate control for port A 8 0 0 GIOSRCB 0x138 32 GIO slew rate select for port B NU36 [31:8] Reserved 24 8 GIOSRCB [7:0] GIO slew rate control for port B 8 0 0 GIOSRCC 0x13C 32 GIO slew rate select for port C NU37 [31:8] Reserved 24 8 GIOSRCC [7:0] GIO slew rate control for port C 8 0 0 GIOSRCD 0x140 32 GIO slew rate select for port D NU38 [31:8] Reserved 24 8 GIOSRCD [7:0] GIO slew rate control for port D 8 0 0 GIOSRCE 0x144 32 GIO slew rate select for port E NU39 [31:8] Reserved 24 8 GIOSRCE [7:0] GIO slew rate control for port E 8 0 0 GIOSRCF 0x148 32 GIO slew rate select for port F NU40 [31:8] Reserved 24 8 GIOSRCF [7:0] GIO slew rate control for port F 8 0 0 GIOSRCG 0x14C 32 GIO slew rate select for port G NU39 [31:8] Reserved 24 8 GIOSRCG [7:0] GIO slew rate control for port G 8 0 0 GIOSRCH 0x150 32 GIO slew rate select for port H NU40 [31:8] Reserved 24 8 GIOSRCH [7:0] GIO slew rate control for port H 8 0 0 TOPSS_CTRL 0x5B020000 0 4148 registers PID 0x0 32 PID register 16 16 5 11 3 8 2 6 6 0 0 XTAL_FREQ 0x4 32 XTAL_FREQ clkm_xtal_freq [1:0] XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz 2 0 0 SOP_MODE 0x8 32 SOP_MODE sop_mode [1:0] SOP MODE, 0x0 = Device Management Mode 0x1 = Application Mode 0x2 = Test mode 0x3 = Debug Mode 2 0 0 RS232_BITINTERVAL_0_1 0xC 32 RS232_BITINTERVAL_0_1 rs232_bitinterval_1 [27:16] BIT Interval value for 40MHz XTAL 12 16 rs232_bitinterval_0 [11:0] BIT Interval value for 25MHz XTAL 12 0 0 RS232_BITINTERVAL_2_3 0x10 32 RS232_BITINTERVAL_2_3 rs232_bitinterval_3 [27:16] BIT Interval value for 38.4MHz XTAL 12 16 rs232_bitinterval_2 [11:0] BIT Interval value for 26MHz XTAL 12 0 0 DIG_SYNC_SELECT 0x14 32 DIG_SYNC_SELECT dig_sync_select [1:0] Selects dig_sync_in for FRC 2'b00: dig_sync_in 2'b01: mcan_intr 2'b10: lin_intr 2 0 0 LIMP_MODE_GEN_EN 0x18 32 LIMP_MODE_GEN_EN limp_mode_plldig_lockmon [24:24] status reg for limp_mode_plldig_lockmon 1 24 limp_mode_dcc [16:16] status reg for limp_mode_dcc 1 16 PLLDIG_LOCKMON_ESM_ERR_GEN_ENABLE [13:11] Enable PLLDIG lockmon to generate esm error 3'b000: PLLDIG lockmon will not generate esm error (multibit 000) 3'b111 : PLLDIG lockmon will generate esm error (multibit 111) 3 11 plldig_lockmon_limp_gen_enable [10:8] Enable PLLDIG lockmon to generate Limp mode 3'b000: PLLDIG lockmon will not generate Limp mode (multibit 000) 3'b111 : PLLDIG lockmon will generate Limp mode (multibit 111) 3 8 dcc_error_limp_gen_enable [2:0] Enable EDCC Error to generate Limp mode 3'b000: EDCC Error will not generate Limp mode (multibit 000) 3'b111 : EDCC Error will generate Limp mode (multibit 111) 3 0 0 CTI_INTR_MUX_SEL 0x1C 32 CTI_INTR_MUX_SEL CTI3_intr_mux_select [26:24] CTI3 mux select 3'b000: FRAMETIMER_FRAME_START 3'b001: FRAME_START_OFFSET_INTR_TIME1 3'b010: BURST_START_OFFSET_TIME 3'b011: CHIRPTIMER_BURST_START 3'b100: CHIRPTIMER_BURST_END 3 24 CTI2_intr_mux_select [17:16] CTI2 mux select 2'b00: CHIRP_AVAIL_IRQ 2'b01: ADC_VALID_START 2'b10: CHIRPTIMER_CHIRP_START 2'b11: CHIRPTIMER_CHIRP_END 2 16 CTI1_intr_mux_select [10:8] CTI1 mux select 3'b000: app_rti_int_req0 3'b001: app_rti_int_req1 3'b010: tpcc_1_intagg 3'b011: tpcc_2_intagg 3'b100: hwa_loop_int 3'b101: hwa_paramdone_int 3 8 CTI0_intr_mux_select [1:0] CTI0 mux select 2'b00: ESM_LO_IRQ 2'b01: FEC_INTRundefined 2'b10: FEC_INTRundefined 2 0 0 SECAP_TX_DATA 0x20 32 SECAP_TX_DATA JTAGTXDATA [31:0] This register is used to pass data to the system security logic. The data is transmit from the external JTAG interface and hence is the Rx path for the SECAP interface. 32 0 0 SECAP_TX_CONTROL 0x24 32 SECAP_TX_CONTROL TXDATA_AVAIL [31:31] Tx Interrupt to indicate avaliablity of TXDATA . 1 - TXDATA available ; 0 - TXDATA not available 1 31 JTAGTXCONTROL [30:0] This register is provides the handshake for the JTAGTXDATA Register and can also be used to pass control information to the system security logic. 31 0 0 SECAP_RX_DATA 0x28 32 SECAP_RX_DATA JTAGRXDATA [31:0] This register is used to pass data from the system security logic. The data is transmit from the SECAP interface to external JTAG interface and hence is the Tx path for the SECAP interface. 32 0 0 SECAP_RX_CONTROL 0x2C 32 SECAP_RX_CONTROL RXDATA_AVAIL [31:31] Tx Interrupt to indicate avaliablity of RXDATA . 1 - RXDATA available ; 0 - RXDATA not available 1 31 JTAGRXCONTROL [30:0] This register is provides the handshake for the JTAGRXDATA Register and can also be used to pass control information from the system security logic 31 0 0 dft_proc_dmled_exec 0x30 32 dft_proc_dmled_exec obs_status [17:15] dft_proc_dmled_obs_status 3 15 cm3_status [14:12] dft_proc_dmled_cm3_status 3 12 cm4_status [11:9] dft_proc_dmled_cm4_status 3 9 obs_exec [8:6] dft_proc_dmled_obs_exec 3 6 cm3_exec [5:3] dft_proc_dmled_cm3_exec 3 3 cm4_exec [2:0] dft_proc_dmled_cm4_exec 3 0 0 dft_proc_dmled_status 0x34 32 dft_proc_dmled_status RESERVED [31:0] RESERVED 32 0 0 dft_config_reg 0x38 32 dft_config_reg ctrl [31:0] bitundefined: dft_dmled_status_obs_sel 32 0 0 dft_pbist_st_key 0x3C 32 dft_pbist_st_key reg [31:0] dft_pbist_st_key 32 0 0 dft_pbist_st_rst 0x40 32 dft_pbist_st_rst reg [31:0] dft_pbist_st_rst 32 0 0 TOP_INTMASK 0x44 32 TOP_INTMASK set [31:0] Mask Interrupt from frame timer 1 : Interrupt is Masked 0 : Interrupt is Unmasked Bit 0 - Mask Interrupts from Frame Timer Bit 31:0 - Reserved 32 0 0 DEBUG_STATUS_AON_1 0x48 32 DEBUG_STATUS_AON_1 bgap_hib_ref_cap_charge_en [21:21] status reg for bgap_hib_ref_cap_charge_en 1 21 bgap_hib_cap_sw_en [20:20] status reg for bgap_hib_cap_sw_en 1 20 bgap_cap_charge_en [19:19] status reg for bgap_cap_charge_en 1 19 bgap_cap_sw_enz [18:18] status reg for bgap_cap_sw_enz 1 18 bgap_en [17:17] status reg for bgap_en 1 17 bgap_state [16:13] status reg for bgap_state 4 13 dig_ka_ldo_en [12:12] status reg for dig_ka_ldo_en 1 12 dig_ldo_en [11:11] status reg for dig_ldo_en 1 11 dig_ldo_state [10:7] status reg for dig_ldo_state 4 7 sram_ka_ldo_en [6:6] status reg for sram_ka_ldo_en 1 6 sram_ldo_en [5:5] status reg for sram_ldo_en 1 5 sram_ldo_state [4:0] status reg for sram_ldo_state 5 0 0 DEBUG_STATUS_AON_2 0x4C 32 DEBUG_STATUS_AON_2 clkm_xt_drive [24:20] status reg for clkm_xt_drive 5 20 clkm_xtal_freq [19:18] status reg for clkm_xtal_freq 2 18 clkm_limp_mode [17:17] status reg for clkm_limp_mode 1 17 clkm_host_clk_req_output_en [16:16] status reg for clkm_host_clk_req_output_en 1 16 clkm_host_clk_req [15:15] status reg for clkm_host_clk_req 1 15 clkm_first_wake_up [14:14] status reg for clkm_first_wake_up 1 14 clkm_oscillator_clk_valid [13:13] status reg for clkm_oscillator_clk_valid 1 13 clkm_xtal_det_status [12:12] status reg for clkm_xtal_det_status 1 12 clkm_xtal_det_en [11:11] status reg for clkm_xtal_det_en 1 11 clkm_slicer_en [10:10] status reg for clkm_slicer_en 1 10 clkm_xtal_en [9:9] status reg for clkm_xtal_en 1 9 clkm_slicer_bias_en [8:8] status reg for clkm_slicer_bias_en 1 8 clkm_slicer_ldo_en [7:7] status reg for clkm_slicer_ldo_en 1 7 clkm_xtal_det_status_in [6:6] status reg for clkm_xtal_det_status_in 1 6 clkm_state [5:0] status reg for clkm_state 6 0 0 DEBUG_STATUS_AON_3 0x50 32 DEBUG_STATUS_AON_3 wakeup_source_frc [9:9] status reg for wakeup_source_frc 1 9 wakeup_source_rtc [8:8] status reg for wakeup_source_rtc 1 8 wakeup_source_gpio [7:7] status reg for wakeup_source_gpio 1 7 wakeup_source_spi [6:6] status reg for wakeup_source_spi 1 6 wakeup_source_uart [5:5] status reg for wakeup_source_uart 1 5 wakeup_source_sleep_counter [4:4] status reg for wakeup_source_sleep_counter 1 4 radar_state [3:0] status reg for radar_state 4 0 0 DEBUG_STATUS_AON_4 0x54 32 DEBUG_STATUS_AON_4 testdbg_logic_pscon_fsm [19:15] status reg for testdbg_logic_pscon_fsm 5 15 hwa_logic_pscon_fsm [14:10] status reg for hwa_logic_pscon_fsm 5 10 fec_logic_pscon_fsm [9:5] status reg for fec_logic_pscon_fsm 5 5 app_logic_pscon_fsm [4:0] status reg for app_logic_pscon_fsm 5 0 0 DEBUG_STATUS_AON_5 0x58 32 DEBUG_STATUS_AON_5 fec_grp4mem_pscon_fsm [23:20] status reg for fec_grp4mem_pscon_fsm 4 20 fec_mem_pscon_fsm [19:16] status reg for fec_mem_pscon_fsm 4 16 hwa_grp3_mem_pscon_fsm [15:12] status reg for hwa_grp3_mem_pscon_fsm 4 12 app_grp2_mem_pscon_fsm [11:8] status reg for app_grp2_mem_pscon_fsm 4 8 app_grp1_mem_pscon_fsm [7:4] status reg for app_grp1_mem_pscon_fsm 4 4 app_mem_pscon_fsm [3:0] status reg for app_mem_pscon_fsm 4 0 0 DEBUG_STATUS_AON_6 0x5C 32 DEBUG_STATUS_AON_6 test_dbg_pd_pwr_req [7:7] status reg for test_dbg_pd_pwr_req 1 7 hwa_pd_pwr_req [6:6] status reg for hwa_pd_pwr_req 1 6 fec_pd_pwr_req [5:5] status reg for fec_pd_pwr_req 1 5 app_pd_pwr_req [4:4] status reg for app_pd_pwr_req 1 4 test_dbg_pd_is_sleep [3:3] status reg for test_dbg_pd_is_sleep 1 3 hwa_pd_is_sleep [2:2] status reg for hwa_pd_is_sleep 1 2 fec_pd_is_sleep [1:1] status reg for fec_pd_is_sleep 1 1 app_pd_is_sleep [0:0] status reg for app_pd_is_sleep 1 0 0 DEBUG_STATUS_AON_7 0x60 32 DEBUG_STATUS_AON_7 test_dbg_pd_pgoodout [27:27] status reg for test_dbg_pd_pgoodout 1 27 test_dbg_pd_ponout [26:26] status reg for test_dbg_pd_ponout 1 26 test_dbg_pd_pgoodin [25:25] status reg for test_dbg_pd_pgoodin 1 25 test_dbg_pd_ponin [24:24] status reg for test_dbg_pd_ponin 1 24 test_dbg_pd_isoscan [23:23] status reg for test_dbg_pd_isoscan 1 23 test_dbg_pd_iso_ram [22:22] status reg for test_dbg_pd_iso_ram 1 22 test_dbg_pd_iso [21:21] status reg for test_dbg_pd_iso 1 21 hwa_pd_pgoodout [20:20] status reg for hwa_pd_pgoodout 1 20 hwa_pd_ponout [19:19] status reg for hwa_pd_ponout 1 19 hwa_pd_pgoodin [18:18] status reg for hwa_pd_pgoodin 1 18 hwa_pd_ponin [17:17] status reg for hwa_pd_ponin 1 17 hwa_pd_isoscan [16:16] status reg for hwa_pd_isoscan 1 16 hwa_pd_iso_ram [15:15] status reg for hwa_pd_iso_ram 1 15 hwa_pd_iso [14:14] status reg for hwa_pd_iso 1 14 fec_pd_pgoodout [13:13] status reg for fec_pd_pgoodout 1 13 fec_pd_ponout [12:12] status reg for fec_pd_ponout 1 12 fec_pd_pgoodin [11:11] status reg for fec_pd_pgoodin 1 11 fec_pd_ponin [10:10] status reg for fec_pd_ponin 1 10 fec_pd_isoscan [9:9] status reg for fec_pd_isoscan 1 9 fec_pd_iso_ram [8:8] status reg for fec_pd_iso_ram 1 8 fec_pd_iso [7:7] status reg for fec_pd_iso 1 7 app_pd_pgoodout [6:6] status reg for app_pd_pgoodout 1 6 app_pd_ponout [5:5] status reg for app_pd_ponout 1 5 app_pd_pgoodin [4:4] status reg for app_pd_pgoodin 1 4 app_pd_ponin [3:3] status reg for app_pd_ponin 1 3 app_pd_isoscan [2:2] status reg for app_pd_isoscan 1 2 app_pd_iso_ram [1:1] status reg for app_pd_iso_ram 1 1 app_pd_iso [0:0] status reg for app_pd_iso 1 0 0 DEBUG_STATUS_AON_8 0x64 32 DEBUG_STATUS_AON_8 app_pd_mem_grp2_agoodin [23:23] status reg for app_pd_mem_grp2_agoodin 1 23 app_pd_mem_grp2_aonin [22:22] status reg for app_pd_mem_grp2_aonin 1 22 app_pd_mem_grp2_agoodout [21:21] status reg for app_pd_mem_grp2_agoodout 1 21 app_pd_mem_grp2_aonout [20:20] status reg for app_pd_mem_grp2_aonout 1 20 app_pd_mem_grp1_agoodin [19:18] status reg for app_pd_mem_grp1_agoodin 2 18 app_pd_mem_grp1_aonin [17:16] status reg for app_pd_mem_grp1_aonin 2 16 app_pd_mem_grp1_agoodout [15:14] status reg for app_pd_mem_grp1_agoodout 2 14 app_pd_mem_grp1_aonout [13:12] status reg for app_pd_mem_grp1_aonout 2 12 app_pd_mem_agoodin [11:9] status reg for app_pd_mem_agoodin 3 9 app_pd_mem_aonin [8:6] status reg for app_pd_mem_aonin 3 6 app_pd_mem_agoodout [5:3] status reg for app_pd_mem_agoodout 3 3 app_pd_mem_aonout [2:0] status reg for app_pd_mem_aonout 3 0 0 DEBUG_STATUS_AON_9 0x68 32 DEBUG_STATUS_AON_9 app_pd_mem_grp2_dftrtagood [11:11] status reg for app_pd_mem_grp2_dftrtagood 1 11 app_pd_mem_grp2_dftrtaon [10:10] status reg for app_pd_mem_grp2_dftrtaon 1 10 app_pd_mem_grp1_dftrtagood [9:8] status reg for app_pd_mem_grp1_dftrtagood 2 8 app_pd_mem_grp1_dftrtaon [7:6] status reg for app_pd_mem_grp1_dftrtaon 2 6 app_pd_mem_dftrtagood [5:3] status reg for app_pd_mem_dftrtagood 3 3 app_pd_mem_dftrtaon [2:0] status reg for app_pd_mem_dftrtaon 3 0 0 DEBUG_STATUS_AON_10 0x6C 32 DEBUG_STATUS_AON_10 hwa_pd_mem_grp3_dftrtagood [17:15] status reg for hwa_pd_mem_grp3_dftrtagood 3 15 hwa_pd_mem_grp3_dftrtaon [14:12] status reg for hwa_pd_mem_grp3_dftrtaon 3 12 hwa_pd_mem_grp3_agoodin [11:9] status reg for hwa_pd_mem_grp3_agoodin 3 9 hwa_pd_mem_grp3_aonin [8:6] status reg for hwa_pd_mem_grp3_aonin 3 6 hwa_pd_mem_grp3_agoodout [5:3] status reg for hwa_pd_mem_grp3_agoodout 3 3 hwa_pd_mem_grp3_aonout [2:0] status reg for hwa_pd_mem_grp3_aonout 3 0 0 DEBUG_STATUS_AON_11 0x70 32 DEBUG_STATUS_AON_11 fec_pd_mem_grp4_dftrtagood [17:16] status reg for fec_pd_mem_grp4_dftrtagood 2 16 fec_pd_mem_grp4_dftrtaon [15:14] status reg for fec_pd_mem_grp4_dftrtaon 2 14 fec_pd_mem_dftrtagood [13:13] status reg for fec_pd_mem_dftrtagood 1 13 fec_pd_mem_dftrtaon [12:12] status reg for fec_pd_mem_dftrtaon 1 12 fec_pd_mem_grp4_agoodin [11:10] status reg for fec_pd_mem_grp4_agoodin 2 10 fec_pd_mem_grp4_aonin [9:8] status reg for fec_pd_mem_grp4_aonin 2 8 fec_pd_mem_grp4_agoodout [7:6] status reg for fec_pd_mem_grp4_agoodout 2 6 fec_pd_mem_grp4_aonout [5:4] status reg for fec_pd_mem_grp4_aonout 2 4 fec_pd_mem_agoodin [3:3] status reg for fec_pd_mem_agoodin 1 3 fec_pd_mem_aonin [2:2] status reg for fec_pd_mem_aonin 1 2 fec_pd_mem_agoodout [1:1] status reg for fec_pd_mem_agoodout 1 1 fec_pd_mem_aonout [0:0] status reg for fec_pd_mem_aonout 1 0 0 DEBUG_STATUS_AON_12 0x74 32 DEBUG_STATUS_AON_12 vnwa_switch_screen_en [13:13] status reg for vnwa_switch_screen_en 1 13 vnwa_switch_weak_process [12:12] status reg for vnwa_switch_weak_process 1 12 fec_pd_mem_grp4_vnwa_switch_en [11:11] status reg for fec_pd_mem_grp4_vnwa_switch_en 1 11 hwa_pd_mem_grp3_vnwa_switch_en [10:10] status reg for hwa_pd_mem_grp3_vnwa_switch_en 1 10 app_pd_mem_grp2_vnwa_switch_en [9:9] status reg for app_pd_mem_grp2_vnwa_switch_en 1 9 app_pd_mem_grp1_vnwa_switch_en [8:8] status reg for app_pd_mem_grp1_vnwa_switch_en 1 8 fec_pd_mem_gpr4_lowres_switch_en [7:7] status reg for fec_pd_mem_gpr4_lowres_switch_en 1 7 hwa_pd_mem_gpr3_lowres_switch_en [6:6] status reg for hwa_pd_mem_gpr3_lowres_switch_en 1 6 app_pd_mem_grp2_lowres_switch_en [5:5] status reg for app_pd_mem_grp2_lowres_switch_en 1 5 app_pd_mem_grp1_lowres_switch_en [4:4] status reg for app_pd_mem_grp1_lowres_switch_en 1 4 fec_pd_mem_grp4_highres_switch_en [3:3] status reg for fec_pd_mem_grp4_highres_switch_en 1 3 hwa_pd_mem_grp3_highres_switch_en [2:2] status reg for hwa_pd_mem_grp3_highres_switch_en 1 2 app_pd_mem_grp2_highres_switch_en [1:1] status reg for app_pd_mem_grp2_highres_switch_en 1 1 app_pd_mem_grp1_highres_switch_en [0:0] status reg for app_pd_mem_grp1_highres_switch_en 1 0 0 DEBUG_STATUS_AON_13 0x78 32 DEBUG_STATUS_AON_13 hwa_pd_clkgate_en [2:2] status reg for hwa_pd_clkgate_en 1 2 fec_pd_clkgate_en [1:1] status reg for fec_pd_clkgate_en 1 1 app_pd_clkgate_en [0:0] status reg for app_pd_clkgate_en 1 0 0 DEBUG_STATUS_AON_14 0x7C 32 DEBUG_STATUS_AON_14 fec_pd_core_rstn [8:8] status reg for fec_pd_core_rstn 1 8 app_pd_core_rstn [7:7] status reg for app_pd_core_rstn 1 7 hwa_pd_warm_rstn [6:6] status reg for hwa_pd_warm_rstn 1 6 fec_pd_warm_rstn [5:5] status reg for fec_pd_warm_rstn 1 5 app_pd_warm_rstn [4:4] status reg for app_pd_warm_rstn 1 4 test_dbg_pd_por_rstn [3:3] status reg for test_dbg_pd_por_rstn 1 3 hwa_pd_por_rstn [2:2] status reg for hwa_pd_por_rstn 1 2 fec_pd_por_rstn [1:1] status reg for fec_pd_por_rstn 1 1 app_pd_por_rstn [0:0] status reg for app_pd_por_rstn 1 0 0 DEBUG_STATUS_AON_15 0x80 32 DEBUG_STATUS_AON_15 LVDS_DIS [4:4] status reg for LVDS_DIS 1 4 TEST_DIS [3:3] status reg for TEST_DIS 1 3 RS232_DIS [2:2] status reg for RS232_DIS 1 2 JTAG_DIS [1:1] status reg for JTAG_DIS 1 1 DIS_JTAG [0:0] status reg for DIS_JTAG 1 0 0 DEBUG_STATUS_AON_16 0x84 32 DEBUG_STATUS_AON_16 icemelter_powakeemu [0:0] status reg for icemelter_powakeemu 1 0 0 APPSS_DYNAMIC_CLK_GATE_STATUS 0x88 32 APPSS_DYNAMIC_CLK_GATE_STATUS tptc2 [2:2] Dynamic Clock gate Status of TPTC2 1 - Clock is Enabled 0 - Clock is Gated. 1 2 tptc1 [1:1] Dynamic Clock gate Status of TPTC1 1 - Clock is Enabled 0 - Clock is Gated. 1 1 xbara [0:0] Dynamic Clock gate Status of XBARA 1 - Clock is Enabled 0 - Clock is Gated. 1 0 0 LOCK0_KICK0 0x1008 32 - KICK0 component [31:0] - KICK0 component 32 0 0 LOCK0_KICK1 0x100C 32 - KICK1 component [31:0] - KICK1 component 32 0 0 intr_raw_status 0x1010 32 Interrupt Raw Status/Set Register [3:3] Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 0 0 intr_enabled_status_clear 0x1014 32 Interrupt Enabled Status/Clear register [3:3] Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 0 0 intr_enable 0x1018 32 Interrupt Enable register [3:3] Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 0 0 intr_enable_clear 0x101C 32 Interrupt Enable Clear register [3:3] Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 0 0 eoi 0x1020 32 EOI register [7:0] EOI vector value. Write this with interrupt distribution value in the chip. 8 0 0 fault_address 0x1024 32 Fault Address register [31:0] Fault Address. 32 0 0 fault_type_status 0x1028 32 Fault Type Status register [6:6] Non-secure access. 1 6 [5:0] Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault 6 0 0 fault_attr_status 0x102C 32 Fault Attribute Status register [31:20] XID. 12 20 [19:8] Route ID. 12 8 [7:0] Privilege ID. 8 0 0 fault_clear 0x1030 32 Fault Clear register [0:0] Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect. 1 0 0 PLLDIG_CTRL 0x5B040000 0 4148 registers PID 0x0 32 PID register 16 16 5 11 3 8 2 6 6 0 0 PLLDIG_EN 0x4 32 PLLDIG_EN cfg_plldig_lockmon_enable [18:16] PLL DIG lockmon enable 0x0 = PLL DIG lockmon disbale 0x7 = PLL DIG lockmon enable 3 16 cfg_pll_auto_switch_enable [10:8] PLL DIG and APLL auto switch enable 0x0 = PLL DIG wont be auto turn off when APLL is enable 0x7 = PLL DIG will be auto turn off when APLL is enable 3 8 cfg_plldig_en [2:0] PLL DIG enable 0x0 = PLL DIG disable 0x7 = PLL DIG enable 3 0 0 PLLDIG_MDIV_NDIV 0x8 32 PLLDIG_MDIV_NDIV cfg_plldig_ndiv [22:16] NDIV value for the PLL DIG Input clock divider settings .NDIV value directly programs the 7-bit pre- divider. Divide value ranges from 2 to 127. NDIV value has to be chosen based on the REF_CLKIN frequency so as to get the internal reference frequency of the PLL closest to 2Mhz 7 16 cfg_plldig_mdiv [8:0] MDIV value for the PLL DIG Feedback divider settings. MDIV value directly programs the 9-bit feedback divider. Divide value ranges from 2 to 511. MDIV value has to be chosen to generate the required clock out frequency from the 2Mhz internal PLL reference 9 0 0 PLLDIG_CTRL 0xC 32 PLLDIG_CTRL cfg_plldig_ctrl [31:0] PLL DIG test controls 32 0 0 PLLDIG_MODE_EN 0x10 32 PLLDIG_MODE_EN cfg_plldig_lowfreq_mode_en [16:16] PLL DIG high frequency mode operation, Divide by 2 the PLL clock out 1 16 cfg_plldig_highfreq_mode_en [0:0] PLL DIG high frequency mode operation 1 0 0 PLLDIG_APLL_SW_DIS_DELAY1 0x14 32 PLLDIG_APLL_SW_DIS_DELAY1 cfg_plldig_auto_switch_delay [31:16] Delay to switch the PLL clock source when the auto PLL switch mode is enable 16 16 cfg_apll_auto_switch_delay [15:0] Delay to switch the PLL clock source when the auto PLL switch mode is enable 16 0 0 PLLDIG_APLL_SW_DIS_DELAY2 0x18 32 PLLDIG_APLL_SW_DIS_DELAY2 cfg_apll_disable_delay [31:16] Delay between the PLL clock source switching and disabling of the APLL 16 16 cfg_plldig_disable_delay [15:0] Delay between the PLL clock source switching and disabling of the PLL DIG 16 0 0 PLLDIG_OVERRIDE 0x1C 32 PLLDIG_OVERRIDE cfg_ov_final_plldig_apll_mux_sel [5:3] Override control for the fast clock src mux select 0x0 = PLL DIG selected as fast clock 0x7 = APLL selected as fast clock 3 3 cfg_sel_ov_final_plldig_apll_mux_sel [2:0] Mux select control to select the override value of the fast clock src mux select 0x0 = functional value selected for the fast clock src mux select 0x7 = Override value selected for the fast clock src mux select 3 0 0 PLLDIG_STATUS 0x20 32 PLLDIG_STATUS plldig_lockmon [8:8] PLL DIG lockmon status 1 8 clkm_xtal_freq [1:0] XTAL clock frequency status, 0x0 = 25MHz 0x1 = 40MHz 0x2 = 26MHz 0x3 = 38.4MHz 2 0 0 FAST_CLK_MUX_POSTDIV 0x24 32 FAST_CLK_MUX_POSTDIV divr [15:4] Divider value for FAST selected clock. Data should be loaded as multibit. For example: if divider value of 8 (1000) needs to be selected then '100010001000' should be configured to the register. 12 4 currdivr [3:0] Status shows the current divider value choosen for FAST_CLK. 4 0 0 FAST_CLK_STATUS 0x28 32 FAST_CLK_STATUS currclk [1:0] Current Clock selected by GCM Clock Mux 0x1 : PLLDIG 0x2 : APLL 2 0 0 LOCK0_KICK0 0x1008 32 - KICK0 component [31:0] - KICK0 component 32 0 0 LOCK0_KICK1 0x100C 32 - KICK1 component [31:0] - KICK1 component 32 0 0 intr_raw_status 0x1010 32 Interrupt Raw Status/Set Register [3:3] Proxy0 access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Raw status is read. Write a 1 to set the status. Writing a 0 has no effect. 1 0 0 intr_enabled_status_clear 0x1014 32 Interrupt Enabled Status/Clear register [3:3] Proxy0 access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 1 [0:0] Protection violation error. Enabled status is read. Write a 1 to clear the status. Writing a 0 has no effect. 1 0 0 intr_enable 0x1018 32 Interrupt Enable register [3:3] Proxy0 access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable. Write a 1 to set the enable. Writing a 0 has no effect. 1 0 0 intr_enable_clear 0x101C 32 Interrupt Enable Clear register [3:3] Proxy0 access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 3 [2:2] Kick access violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 2 [1:1] Addressing violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 1 [0:0] Protection violation error enable clear. Write a 1 to clear the enable. Writing a 0 has no effect. 1 0 0 eoi 0x1020 32 EOI register [7:0] EOI vector value. Write this with interrupt distribution value in the chip. 8 0 0 fault_address 0x1024 32 Fault Address register [31:0] Fault Address. 32 0 0 fault_type_status 0x1028 32 Fault Type Status register [6:6] Non-secure access. 1 6 [5:0] Fault Type 10_0000 = Supervisor read fault - priv = 1 dir = 1 dtype != 1 01_0000 = Supervisor write fault - priv = 1 dir = 0 00_1000 = Supervisor execute fault - priv = 1 dir = 1 dtype = 1 00_0100 = User read fault - priv = 0 dir = 1 dtype = 1 00_0010 = User write fault - priv = 0 dir = 0 00_0001 = User execute fault - priv = 0 dir = 1 dtype = 1 00_0000 = No fault 6 0 0 fault_attr_status 0x102C 32 Fault Attribute Status register [31:20] XID. 12 20 [19:8] Route ID. 12 8 [7:0] Privilege ID. 8 0 0 fault_clear 0x1030 32 Fault Clear register [0:0] Fault clear. Writing a 1 clears the current fault. Writing a 0 has no effect. 1 0 0 PBIST 0x5C020000 0 464 registers PBIST RESERVED 0x0 32 Reserved RESERVED [31:0] Reserved 32 0 0 PBIST_DLR 0x164 16 Datalogger 0 DLR1 [15:8] Datalogger Register [8] : Reserevd [9] : Default Testing Mode. When in this mode, ROM-based testing is kicked off. If the intention is to perform go/no-go testing via config, write to both this bit and bit [2] of the Datalogger Register simultaneously [15:10] : Reserevd 8 8 DLR0 [7:0] Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode. Setting this bit to 1 enables the PBIST controller to execute test algorithms that are stored in the PBIST ROM [3] : Do not change this bit from its default value of 1 [4] : Config access mode. Setting this bit allows the host processor to configure the PBIST controller registers [7:5] : Reserved 8 0 0 PBIST_PC 0x16C 5 Program Control PBIST_PC [4:0] TI Internal Register.Reserved for HW RnD 5 0 0 PBIST_PACT 0x180 1 Pbist Active PBIST_PACT [0:0] Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks. Setting this bit asserts an internal signal that is used as the clock gate enable. As long as this bit is 0, any access to PBIST will not go through, and PBIST will remain in an almost zero-power mode. Value 0 = Disable internal PBIST clocks Value 1 = Enable internal PBIST clocks 1 0 0 PBIST_OVR 0x188 4 PBIST Overrides PBIST_OVR [3:0] TI Internal Register.Reserved for HW RnD 4 0 0 PBIST_FSFR0 0x190 32 Fail status fail - port 0 Reserved [31:1] TI Internal Register.Reserved for HW RnD 31 1 PBIST_FSFR0 [0:0] Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure 1 0 0 PBIST_FSFR1 0x194 32 Fail status fail - port 1 Reserved [31:1] TI Internal Register.Reserved for HW RnD 31 1 PBIST_FSFR1 [0:0] Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test. Value 0 = No failure occurred Value 1 = Indicates a failure 1 0 0 PBIST_ROM 0x1C0 2 Rom Mask PBIST_ROM [1:0] Rom Mask . This two-bit register sets appropriate ROM access modes for the PBIST controller. Value 0h = No information is used from ROM Value 1h = Only RAM Group information from ROM Vaule 2h = Only Algorithm information from ROM Value 3h = Both Algorithm and RAM information from ROM. This option should be selected for application self-test. 2 0 0 PBIST_ALGO 0x1C4 32 ROM Algorithm Mask 0 ALGO3 [31:24] This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm. 8 24 ALGO2 [23:16] This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm. 8 16 ALGO1 [15:8] This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm. 8 8 ALGO0 [7:0] This register is used to indicate the algorithm(s) to be used for the memory self-test routine. Each bit corresponds to a specific algorithm. Writing a value 1 to the particular bit, enables the corresponding algorithm. Writing a value 0 to the particular bit, disables the corresponding algorithm. 8 0 0 PBIST_RINFOL 0x1C8 32 RAM Info Mask Lower 0 RINFOL3 [31:24] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 24 RINFOL2 [23:16] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 16 RINFOL1 [15:8] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 8 RINFOL0 [7:0] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 0 0 PBIST_RINFOU 0x1CC 32 RAM Info Mask Upper 0 RINFOU3 [31:24] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 24 RINFOU2 [23:16] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 16 RINFOU1 [15:8] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 8 RINFOU0 [7:0] This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register. For an algorithmto be executed on a particular memory group, the corresponding bit in this register must be set to 1. The default value of this register is all 1s, which means all the memory groups are selected. Writing a value 0 to the particular bit, disables the corresponding memory group. 8 0 0 TOP_DEBUGSS 0x5CA00000 0 73728 registers TOP_DEBUGSS ONEMCU_APB_BASE 0x0 32 Start Address of ROM Table ONEMCU_APB_BASE [31:0] OneMCU APB Space : Start Address of ROM Table 32 0 0 ONEMCU_APB_BASE_END 0xFFC 32 End Address of ROM Table ONEMCU_APB_BASE_END [31:0] OneMCU APB Space : Endt Address of ROM Table 32 0 0 ONEMCU_CTI_CONTROL 0x1000 32 http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html ONEMCU_CTI_CONTROL [31:0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html 32 0 0 ONEMCU_CTI_INTACK 0x1010 32 ONEMCU_CTI_INTACK ONEMCU_CTI_INTACK 32 0 0 ONEMCU_CTI_APPSET 0x1014 32 ONEMCU_CTI_APPSET ONEMCU_CTI_APPSET 32 0 0 ONEMCU_CTI_APPCLEAR 0x1018 32 ONEMCU_CTI_APPCLEAR ONEMCU_CTI_APPCLEAR 32 0 0 ONEMCU_CTI_APPPULSE 0x101C 32 ONEMCU_CTI_APPPULSE ONEMCU_CTI_APPPULSE 32 0 0 ONEMCU_CTI_INEN0 0x1020 32 ONEMCU_CTI_INEN0 ONEMCU_CTI_INEN0 32 0 0 ONEMCU_CTI_INEN1 0x1024 32 ONEMCU_CTI_INEN1 ONEMCU_CTI_INEN1 32 0 0 ONEMCU_CTI_INEN2 0x1028 32 ONEMCU_CTI_INEN2 ONEMCU_CTI_INEN2 32 0 0 ONEMCU_CTI_INEN3 0x102C 32 ONEMCU_CTI_INEN3 ONEMCU_CTI_INEN3 32 0 0 ONEMCU_CTI_INEN4 0x1030 32 ONEMCU_CTI_INEN4 ONEMCU_CTI_INEN4 32 0 0 ONEMCU_CTI_INEN5 0x1034 32 ONEMCU_CTI_INEN5 ONEMCU_CTI_INEN5 32 0 0 ONEMCU_CTI_INEN6 0x1038 32 ONEMCU_CTI_INEN6 ONEMCU_CTI_INEN6 32 0 0 ONEMCU_CTI_INEN7 0x103C 32 ONEMCU_CTI_INEN7 ONEMCU_CTI_INEN7 32 0 0 ONEMCU_CTI_OUTEN0 0x10A0 32 ONEMCU_CTI_OUTEN0 ONEMCU_CTI_OUTEN0 32 0 0 ONEMCU_CTI_OUTEN1 0x10A4 32 ONEMCU_CTI_OUTEN1 ONEMCU_CTI_OUTEN1 32 0 0 ONEMCU_CTI_OUTEN2 0x10A8 32 ONEMCU_CTI_OUTEN2 ONEMCU_CTI_OUTEN2 32 0 0 ONEMCU_CTI_OUTEN3 0x10AC 32 ONEMCU_CTI_OUTEN3 ONEMCU_CTI_OUTEN3 32 0 0 ONEMCU_CTI_OUTEN4 0x10B0 32 ONEMCU_CTI_OUTEN4 ONEMCU_CTI_OUTEN4 32 0 0 ONEMCU_CTI_OUTEN5 0x10B4 32 ONEMCU_CTI_OUTEN5 ONEMCU_CTI_OUTEN5 32 0 0 ONEMCU_CTI_OUTEN6 0x10B8 32 ONEMCU_CTI_OUTEN6 ONEMCU_CTI_OUTEN6 32 0 0 ONEMCU_CTI_OUTEN7 0x10BC 32 ONEMCU_CTI_OUTEN7 ONEMCU_CTI_OUTEN7 32 0 0 ONEMCU_CTI_TRIGINSTATUS 0x1130 32 ONEMCU_CTI_TRIGINSTATUS ONEMCU_CTI_TRIGINSTATUS 32 0 0 ONEMCU_CTI_TRIGOUTSTATUS 0x1134 32 ONEMCU_CTI_TRIGOUTSTATUS ONEMCU_CTI_TRIGOUTSTATUS 32 0 0 ONEMCU_CTI_CHINSTATUS 0x1138 32 ONEMCU_CTI_CHINSTATUS ONEMCU_CTI_CHINSTATUS 32 0 0 ONEMCU_CTI_CHOUTSTATUS 0x113C 32 ONEMCU_CTI_CHOUTSTATUS ONEMCU_CTI_CHOUTSTATUS 32 0 0 ONEMCU_CTI_GATE 0x1140 32 ONEMCU_CTI_GATE ONEMCU_CTI_GATE 32 0 0 ONEMCU_CTI_ASICCTL 0x1144 32 ONEMCU_CTI_ASICCTL ONEMCU_CTI_ASICCTL 32 0 0 ONEMCU_CTI_ITCHINACK 0x1EDC 32 ONEMCU_CTI_ITCHINACK ONEMCU_CTI_ITCHINACK 32 0 0 ONEMCU_CTI_ITTRIGINACK 0x1EE0 32 ONEMCU_CTI_ITTRIGINACK ONEMCU_CTI_ITTRIGINACK 32 0 0 ONEMCU_CTI_ITCHOUT 0x1EE4 32 ONEMCU_CTI_ITCHOUT ONEMCU_CTI_ITCHOUT 32 0 0 ONEMCU_CTI_ITTRIGOUT 0x1EE8 32 ONEMCU_CTI_ITTRIGOUT ONEMCU_CTI_ITTRIGOUT 32 0 0 ONEMCU_CTI_ITCHOUTACK 0x1EEC 32 ONEMCU_CTI_ITCHOUTACK ONEMCU_CTI_ITCHOUTACK 32 0 0 ONEMCU_CTI_ITTRIGOUTACK 0x1EF0 32 ONEMCU_CTI_ITTRIGOUTACK ONEMCU_CTI_ITTRIGOUTACK 32 0 0 ONEMCU_CTI_ITCHIN 0x1EF4 32 ONEMCU_CTI_ITCHIN ONEMCU_CTI_ITCHIN 32 0 0 ONEMCU_CTI_ITTRIGIN 0x1EF8 32 ONEMCU_CTI_ITTRIGIN ONEMCU_CTI_ITTRIGIN 32 0 0 ONEMCU_CTI_ITCTRL 0x1F00 32 ONEMCU_CTI_ITCTRL ONEMCU_CTI_ITCTRL 32 0 0 ONEMCU_CTI_Claim_Tag_Set 0x1FA0 32 ONEMCU_CTI_Claim_Tag_Set ONEMCU_CTI_Claim_Tag_Set 32 0 0 ONEMCU_CTI_Claim_Tag_Clear 0x1FA4 32 ONEMCU_CTI_Claim_Tag_Clear ONEMCU_CTI_Claim_Tag_Clear 32 0 0 ONEMCU_CTI_Lock_Access_Register 0x1FB0 32 ONEMCU_CTI_Lock_Access_Register ONEMCU_CTI_Lock_Access_Register 32 0 0 ONEMCU_CTI_Lock_Status_Register 0x1FB4 32 ONEMCU_CTI_Lock_Status_Register ONEMCU_CTI_Lock_Status_Register 32 0 0 ONEMCU_CTI_Authentication_Status 0x1FB8 32 ONEMCU_CTI_Authentication_Status ONEMCU_CTI_Authentication_Status 32 0 0 ONEMCU_CTI_Device_ID 0x1FC8 32 ONEMCU_CTI_Device_ID ONEMCU_CTI_Device_ID 32 0 0 ONEMCU_CTI_Device_Type_Identifier 0x1FCC 32 ONEMCU_CTI_Device_Type_Identifier ONEMCU_CTI_Device_Type_Identifier 32 0 0 ONEMCU_CTI_PeripheralID4 0x1FD0 32 ONEMCU_CTI_PeripheralID4 ONEMCU_CTI_PeripheralID4 32 0 0 ONEMCU_CTI_PeripheralID5 0x1FD4 32 ONEMCU_CTI_PeripheralID5 ONEMCU_CTI_PeripheralID5 32 0 0 ONEMCU_CTI_PeripheralID6 0x1FD8 32 ONEMCU_CTI_PeripheralID6 ONEMCU_CTI_PeripheralID6 32 0 0 ONEMCU_CTI_PeripheralID7 0x1FDC 32 ONEMCU_CTI_PeripheralID7 ONEMCU_CTI_PeripheralID7 32 0 0 ONEMCU_CTI_PeripheralID0 0x1FE0 32 ONEMCU_CTI_PeripheralID0 ONEMCU_CTI_PeripheralID0 32 0 0 ONEMCU_CTI_PeripheralID1 0x1FE4 32 ONEMCU_CTI_PeripheralID1 ONEMCU_CTI_PeripheralID1 32 0 0 ONEMCU_CTI_PeripheralID2 0x1FE8 32 ONEMCU_CTI_PeripheralID2 ONEMCU_CTI_PeripheralID2 32 0 0 ONEMCU_CTI_PeripheralID3 0x1FEC 32 ONEMCU_CTI_PeripheralID3 ONEMCU_CTI_PeripheralID3 32 0 0 ONEMCU_CTI_Component_ID0 0x1FF0 32 ONEMCU_CTI_Component_ID0 ONEMCU_CTI_Component_ID0 32 0 0 ONEMCU_CTI_Component_ID1 0x1FF4 32 ONEMCU_CTI_Component_ID1 ONEMCU_CTI_Component_ID1 32 0 0 ONEMCU_CTI_Component_ID2 0x1FF8 32 ONEMCU_CTI_Component_ID2 ONEMCU_CTI_Component_ID2 32 0 0 ONEMCU_CTI_Component_ID3 0x1FFC 32 ONEMCU_CTI_Component_ID3 ONEMCU_CTI_Component_ID3 32 0 0 ONEMCU_TPIU_SPORTSZ 0x2000 32 Supported port sizes ONEMCU_TPIU_SPORTSZ [31:0] Supported port sizes 32 0 0 ONEMCU_TPIU_CPORTSZ 0x2004 32 Current port size ONEMCU_TPIU_CPORTSZ [31:0] Current port size 32 0 0 ONEMCU_TPIU_STRIGM 0x2100 32 Supported trigger modes ONEMCU_TPIU_STRIGM [31:0] Supported trigger modes 32 0 0 ONEMCU_TPIU_TRIGCNT 0x2104 32 Trigger counter value ONEMCU_TPIU_TRIGCNT [31:0] Trigger counter value 32 0 0 ONEMCU_TPIU_TRIGMUL 0x2108 32 Trigger multiplier ONEMCU_TPIU_TRIGMUL [31:0] Trigger multiplier 32 0 0 ONEMCU_TPIU_STSTPTRN 0x2200 32 Supported test pattern/modes ONEMCU_TPIU_STSTPTRN [31:0] Supported test pattern/modes 32 0 0 ONEMCU_TPIU_CTSTPTRN 0x2204 32 Current test pattern/mode ONEMCU_TPIU_CTSTPTRN [31:0] Current test pattern/mode 32 0 0 ONEMCU_TPIU_TPRCNTR 0x2208 32 Test pattern repeat counter ONEMCU_TPIU_TPRCNTR [31:0] Test pattern repeat counter 32 0 0 ONEMCU_TPIU_FFSTS 0x2300 32 Formatter and flush status ONEMCU_TPIU_FFSTS [31:0] Formatter and flush status 32 0 0 ONEMCU_TPIU_FFCTRL 0x2304 32 Formatter and flush control ONEMCU_TPIU_FFCTRL [31:0] Formatter and flush control 32 0 0 ONEMCU_TPIU_FSCNTR 0x2308 32 Formatter synchronization counter ONEMCU_TPIU_FSCNTR [31:0] Formatter synchronization counter 32 0 0 ONEMCU_TPIU_EXCTLIN 0x2400 32 EXTCTL In Port ONEMCU_TPIU_EXCTLIN [31:0] EXTCTL In Port 32 0 0 ONEMCU_TPIU_EXCTLOUT 0x2404 32 EXTCTL Out Port ONEMCU_TPIU_EXCTLOUT [31:0] EXTCTL Out Port 32 0 0 ONEMCU_TPIU_ITTRFLINACK 0x2EE4 32 Integration Register, ITTRFLINACK ONEMCU_TPIU_ITTRFLINACK [31:0] Integration Register, ITTRFLINACK 32 0 0 ONEMCU_TPIU_ITTRFLIN 0x2EE8 32 Integration Register, ITTRFLIN ONEMCU_TPIU_ITTRFLIN [31:0] Integration Register, ITTRFLIN 32 0 0 ONEMCU_TPIU_ITATBDATA0 0x2EEC 32 Integration Register, ITATBDATA0 ONEMCU_TPIU_ITATBDATA0 [31:0] Integration Register, ITATBDATA0 32 0 0 ONEMCU_TPIU_ITATBCTR2 0x2EF0 32 Integration Register, ITATBCTR2 ONEMCU_TPIU_ITATBCTR2 [31:0] Integration Register, ITATBCTR2 32 0 0 ONEMCU_TPIU_ITATBCTR1 0x2EF4 32 Integration Register, ITATBCTR1 ONEMCU_TPIU_ITATBCTR1 [31:0] Integration Register, ITATBCTR1 32 0 0 ONEMCU_TPIU_ITATBCTR0 0x2EF8 32 Integration Register, ITATBCTR0 ONEMCU_TPIU_ITATBCTR0 [31:0] Integration Register, ITATBCTR0 32 0 0 ONEMCU_TPIU_ITCTRL 0x2F00 32 Integration Mode Control Register ONEMCU_TPIU_ITCTRL [31:0] Integration Mode Control Register 32 0 0 ONEMCU_TPIU_CLAIMSET 0x2FA0 32 Claim Tag Set ONEMCU_TPIU_CLAIMSET [31:0] Claim Tag Set 32 0 0 ONEMCU_TPIU_CLAIMCLR 0x2FA4 32 Claim Tag Clear ONEMCU_TPIU_CLAIMCLR [31:0] Claim Tag Clear 32 0 0 ONEMCU_TPIU_LAR 0x2FB0 32 Lock status ONEMCU_TPIU_LAR [31:0] Lock status 32 0 0 ONEMCU_TPIU_LSR 0x2FB4 32 Lock Access ONEMCU_TPIU_LSR [31:0] Lock Access 32 0 0 ONEMCU_TPIU_AUTHSTATUS 0x2FB8 32 Authentication status ONEMCU_TPIU_AUTHSTATUS [31:0] Authentication status 32 0 0 ONEMCU_TPIU_DEVID 0x2FC8 32 Device ID ONEMCU_TPIU_DEVID [31:0] Device ID 32 0 0 ONEMCU_TPIU_DEVTYPE 0x2FCC 32 Device type identifier ONEMCU_TPIU_DEVTYPE [31:0] Device type identifier 32 0 0 ONEMCU_TPIU_PIDR4 0x2FD0 32 Peripheral ID4 ONEMCU_TPIU_PIDR4 [31:0] Peripheral ID4 32 0 0 ONEMCU_TPIU_PIDR5 0x2FD4 32 Peripheral ID5 ONEMCU_TPIU_PIDR5 [31:0] Peripheral ID5 32 0 0 ONEMCU_TPIU_PIDR6 0x2FD8 32 Peripheral ID6 ONEMCU_TPIU_PIDR6 [31:0] Peripheral ID6 32 0 0 ONEMCU_TPIU_PIDR7 0x2FDC 32 Peripheral ID7 ONEMCU_TPIU_PIDR7 [31:0] Peripheral ID7 32 0 0 ONEMCU_TPIU_PIDR0 0x2FE0 32 Peripheral ID0 ONEMCU_TPIU_PIDR0 [31:0] Peripheral ID0 32 0 0 ONEMCU_TPIU_PIDR1 0x2FE4 32 Peripheral ID1 ONEMCU_TPIU_PIDR1 [31:0] Peripheral ID1 32 0 0 ONEMCU_TPIU_PIDR2 0x2FE8 32 Peripheral ID2 ONEMCU_TPIU_PIDR2 [31:0] Peripheral ID2 32 0 0 ONEMCU_TPIU_PIDR3 0x2FEC 32 Peripheral ID3 ONEMCU_TPIU_PIDR3 [31:0] Peripheral ID3 32 0 0 ONEMCU_TPIU_CIDR0 0x2FF0 32 Component ID0 ONEMCU_TPIU_CIDR0 [31:0] Component ID0 32 0 0 ONEMCU_TPIU_CIDR1 0x2FF4 32 Component ID1 ONEMCU_TPIU_CIDR1 [31:0] Component ID1 32 0 0 ONEMCU_TPIU_CIDR2 0x2FF8 32 Component ID2 ONEMCU_TPIU_CIDR2 [31:0] Component ID2 32 0 0 ONEMCU_TPIU_CIDR3 0x2FFC 32 Component ID3 ONEMCU_TPIU_CIDR3 [31:0] Component ID3 32 0 0 APP_CM4_CTI_CONTROL 0x10000 32 http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html APP_CM4_CTI_CONTROL [31:0] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDGDIHE.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0480e/CHDHBDIA.html 32 0 0 APP_CM4_CTI_INTACK 0x10010 32 APP_CM4_CTI_INTACK APP_CM4_CTI_INTACK 32 0 0 APP_CM4_CTI_APPSET 0x10014 32 APP_CM4_CTI_APPSET APP_CM4_CTI_APPSET 32 0 0 APP_CM4_CTI_APPCLEAR 0x10018 32 APP_CM4_CTI_APPCLEAR APP_CM4_CTI_APPCLEAR 32 0 0 APP_CM4_CTI_APPPULSE 0x1001C 32 APP_CM4_CTI_APPPULSE APP_CM4_CTI_APPPULSE 32 0 0 APP_CM4_CTI_INEN0 0x10020 32 APP_CM4_CTI_INEN0 APP_CM4_CTI_INEN0 32 0 0 APP_CM4_CTI_INEN1 0x10024 32 APP_CM4_CTI_INEN1 APP_CM4_CTI_INEN1 32 0 0 APP_CM4_CTI_INEN2 0x10028 32 APP_CM4_CTI_INEN2 APP_CM4_CTI_INEN2 32 0 0 APP_CM4_CTI_INEN3 0x1002C 32 APP_CM4_CTI_INEN3 APP_CM4_CTI_INEN3 32 0 0 APP_CM4_CTI_INEN4 0x10030 32 APP_CM4_CTI_INEN4 APP_CM4_CTI_INEN4 32 0 0 APP_CM4_CTI_INEN5 0x10034 32 APP_CM4_CTI_INEN5 APP_CM4_CTI_INEN5 32 0 0 APP_CM4_CTI_INEN6 0x10038 32 APP_CM4_CTI_INEN6 APP_CM4_CTI_INEN6 32 0 0 APP_CM4_CTI_INEN7 0x1003C 32 APP_CM4_CTI_INEN7 APP_CM4_CTI_INEN7 32 0 0 APP_CM4_CTI_OUTEN0 0x100A0 32 APP_CM4_CTI_OUTEN0 APP_CM4_CTI_OUTEN0 32 0 0 APP_CM4_CTI_OUTEN1 0x100A4 32 APP_CM4_CTI_OUTEN1 APP_CM4_CTI_OUTEN1 32 0 0 APP_CM4_CTI_OUTEN2 0x100A8 32 APP_CM4_CTI_OUTEN2 APP_CM4_CTI_OUTEN2 32 0 0 APP_CM4_CTI_OUTEN3 0x100AC 32 APP_CM4_CTI_OUTEN3 APP_CM4_CTI_OUTEN3 32 0 0 APP_CM4_CTI_OUTEN4 0x100B0 32 APP_CM4_CTI_OUTEN4 APP_CM4_CTI_OUTEN4 32 0 0 APP_CM4_CTI_OUTEN5 0x100B4 32 APP_CM4_CTI_OUTEN5 APP_CM4_CTI_OUTEN5 32 0 0 APP_CM4_CTI_OUTEN6 0x100B8 32 APP_CM4_CTI_OUTEN6 APP_CM4_CTI_OUTEN6 32 0 0 APP_CM4_CTI_OUTEN7 0x100BC 32 APP_CM4_CTI_OUTEN7 APP_CM4_CTI_OUTEN7 32 0 0 APP_CM4_CTI_TRIGINSTATUS 0x10130 32 APP_CM4_CTI_TRIGINSTATUS APP_CM4_CTI_TRIGINSTATUS 32 0 0 APP_CM4_CTI_TRIGOUTSTATUS 0x10134 32 APP_CM4_CTI_TRIGOUTSTATUS APP_CM4_CTI_TRIGOUTSTATUS 32 0 0 APP_CM4_CTI_CHINSTATUS 0x10138 32 APP_CM4_CTI_CHINSTATUS APP_CM4_CTI_CHINSTATUS 32 0 0 APP_CM4_CTI_CHOUTSTATUS 0x1013C 32 APP_CM4_CTI_CHOUTSTATUS APP_CM4_CTI_CHOUTSTATUS 32 0 0 APP_CM4_CTI_GATE 0x10140 32 APP_CM4_CTI_GATE APP_CM4_CTI_GATE 32 0 0 APP_CM4_CTI_ASICCTL 0x10144 32 APP_CM4_CTI_ASICCTL APP_CM4_CTI_ASICCTL 32 0 0 APP_CM4_CTI_ITCHINACK 0x10EDC 32 APP_CM4_CTI_ITCHINACK APP_CM4_CTI_ITCHINACK 32 0 0 APP_CM4_CTI_ITTRIGINACK 0x10EE0 32 APP_CM4_CTI_ITTRIGINACK APP_CM4_CTI_ITTRIGINACK 32 0 0 APP_CM4_CTI_ITCHOUT 0x10EE4 32 APP_CM4_CTI_ITCHOUT APP_CM4_CTI_ITCHOUT 32 0 0 APP_CM4_CTI_ITTRIGOUT 0x10EE8 32 APP_CM4_CTI_ITTRIGOUT APP_CM4_CTI_ITTRIGOUT 32 0 0 APP_CM4_CTI_ITCHOUTACK 0x10EEC 32 APP_CM4_CTI_ITCHOUTACK APP_CM4_CTI_ITCHOUTACK 32 0 0 APP_CM4_CTI_ITTRIGOUTACK 0x10EF0 32 APP_CM4_CTI_ITTRIGOUTACK APP_CM4_CTI_ITTRIGOUTACK 32 0 0 APP_CM4_CTI_ITCHIN 0x10EF4 32 APP_CM4_CTI_ITCHIN APP_CM4_CTI_ITCHIN 32 0 0 APP_CM4_CTI_ITTRIGIN 0x10EF8 32 APP_CM4_CTI_ITTRIGIN APP_CM4_CTI_ITTRIGIN 32 0 0 APP_CM4_CTI_ITCTRL 0x10F00 32 APP_CM4_CTI_ITCTRL APP_CM4_CTI_ITCTRL 32 0 0 APP_CM4_CTI_Claim_Tag_Set 0x10FA0 32 APP_CM4_CTI_Claim_Tag_Set APP_CM4_CTI_Claim_Tag_Set 32 0 0 APP_CM4_CTI_Claim_Tag_Clear 0x10FA4 32 APP_CM4_CTI_Claim_Tag_Clear APP_CM4_CTI_Claim_Tag_Clear 32 0 0 APP_CM4_CTI_Lock_Access_Register 0x10FB0 32 APP_CM4_CTI_Lock_Access_Register APP_CM4_CTI_Lock_Access_Register 32 0 0 APP_CM4_CTI_Lock_Status_Register 0x10FB4 32 APP_CM4_CTI_Lock_Status_Register APP_CM4_CTI_Lock_Status_Register 32 0 0 APP_CM4_CTI_Authentication_Status 0x10FB8 32 APP_CM4_CTI_Authentication_Status APP_CM4_CTI_Authentication_Status 32 0 0 APP_CM4_CTI_Device_ID 0x10FC8 32 APP_CM4_CTI_Device_ID APP_CM4_CTI_Device_ID 32 0 0 APP_CM4_CTI_Device_Type_Identifier 0x10FCC 32 APP_CM4_CTI_Device_Type_Identifier APP_CM4_CTI_Device_Type_Identifier 32 0 0 APP_CM4_CTI_PeripheralID4 0x10FD0 32 APP_CM4_CTI_PeripheralID4 APP_CM4_CTI_PeripheralID4 32 0 0 APP_CM4_CTI_PeripheralID5 0x10FD4 32 APP_CM4_CTI_PeripheralID5 APP_CM4_CTI_PeripheralID5 32 0 0 APP_CM4_CTI_PeripheralID6 0x10FD8 32 APP_CM4_CTI_PeripheralID6 APP_CM4_CTI_PeripheralID6 32 0 0 APP_CM4_CTI_PeripheralID7 0x10FDC 32 APP_CM4_CTI_PeripheralID7 APP_CM4_CTI_PeripheralID7 32 0 0 APP_CM4_CTI_PeripheralID0 0x10FE0 32 APP_CM4_CTI_PeripheralID0 APP_CM4_CTI_PeripheralID0 32 0 0 APP_CM4_CTI_PeripheralID1 0x10FE4 32 APP_CM4_CTI_PeripheralID1 APP_CM4_CTI_PeripheralID1 32 0 0 APP_CM4_CTI_PeripheralID2 0x10FE8 32 APP_CM4_CTI_PeripheralID2 APP_CM4_CTI_PeripheralID2 32 0 0 APP_CM4_CTI_PeripheralID3 0x10FEC 32 APP_CM4_CTI_PeripheralID3 APP_CM4_CTI_PeripheralID3 32 0 0 APP_CM4_CTI_Component_ID0 0x10FF0 32 APP_CM4_CTI_Component_ID0 APP_CM4_CTI_Component_ID0 32 0 0 APP_CM4_CTI_Component_ID1 0x10FF4 32 APP_CM4_CTI_Component_ID1 APP_CM4_CTI_Component_ID1 32 0 0 APP_CM4_CTI_Component_ID2 0x10FF8 32 APP_CM4_CTI_Component_ID2 APP_CM4_CTI_Component_ID2 32 0 0 APP_CM4_CTI_Component_ID3 0x10FFC 32 APP_CM4_CTI_Component_ID3 APP_CM4_CTI_Component_ID3 32 0 0 FEC_CM3_CTI_CONTROL 0x11000 32 http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdjefbi.html http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/Chdefejc.html FEC_CM3_CTI_CONTROL 32 0 0 FEC_CM3_CTI_INTACK 0x11010 32 FEC_CM3_CTI_INTACK FEC_CM3_CTI_INTACK 32 0 0 FEC_CM3_CTI_APPSET 0x11014 32 FEC_CM3_CTI_APPSET FEC_CM3_CTI_APPSET 32 0 0 FEC_CM3_CTI_APPCLEAR 0x11018 32 FEC_CM3_CTI_APPCLEAR FEC_CM3_CTI_APPCLEAR 32 0 0 FEC_CM3_CTI_APPPULSE 0x1101C 32 FEC_CM3_CTI_APPPULSE FEC_CM3_CTI_APPPULSE 32 0 0 FEC_CM3_CTI_INEN0 0x11020 32 FEC_CM3_CTI_INEN0 FEC_CM3_CTI_INEN0 32 0 0 FEC_CM3_CTI_INEN1 0x11024 32 FEC_CM3_CTI_INEN1 FEC_CM3_CTI_INEN1 32 0 0 FEC_CM3_CTI_INEN2 0x11028 32 FEC_CM3_CTI_INEN2 FEC_CM3_CTI_INEN2 32 0 0 FEC_CM3_CTI_INEN3 0x1102C 32 FEC_CM3_CTI_INEN3 FEC_CM3_CTI_INEN3 32 0 0 FEC_CM3_CTI_INEN4 0x11030 32 FEC_CM3_CTI_INEN4 FEC_CM3_CTI_INEN4 32 0 0 FEC_CM3_CTI_INEN5 0x11034 32 FEC_CM3_CTI_INEN5 FEC_CM3_CTI_INEN5 32 0 0 FEC_CM3_CTI_INEN6 0x11038 32 FEC_CM3_CTI_INEN6 FEC_CM3_CTI_INEN6 32 0 0 FEC_CM3_CTI_INEN7 0x1103C 32 FEC_CM3_CTI_INEN7 FEC_CM3_CTI_INEN7 32 0 0 FEC_CM3_CTI_OUTEN0 0x110A0 32 FEC_CM3_CTI_OUTEN0 FEC_CM3_CTI_OUTEN0 32 0 0 FEC_CM3_CTI_OUTEN1 0x110A4 32 FEC_CM3_CTI_OUTEN1 FEC_CM3_CTI_OUTEN1 32 0 0 FEC_CM3_CTI_OUTEN2 0x110A8 32 FEC_CM3_CTI_OUTEN2 FEC_CM3_CTI_OUTEN2 32 0 0 FEC_CM3_CTI_OUTEN3 0x110AC 32 FEC_CM3_CTI_OUTEN3 FEC_CM3_CTI_OUTEN3 32 0 0 FEC_CM3_CTI_OUTEN4 0x110B0 32 FEC_CM3_CTI_OUTEN4 FEC_CM3_CTI_OUTEN4 32 0 0 FEC_CM3_CTI_OUTEN5 0x110B4 32 FEC_CM3_CTI_OUTEN5 FEC_CM3_CTI_OUTEN5 32 0 0 FEC_CM3_CTI_OUTEN6 0x110B8 32 FEC_CM3_CTI_OUTEN6 FEC_CM3_CTI_OUTEN6 32 0 0 FEC_CM3_CTI_OUTEN7 0x110BC 32 FEC_CM3_CTI_OUTEN7 FEC_CM3_CTI_OUTEN7 32 0 0 FEC_CM3_CTI_TRIGINSTATUS 0x11130 32 FEC_CM3_CTI_TRIGINSTATUS FEC_CM3_CTI_TRIGINSTATUS 32 0 0 FEC_CM3_CTI_TRIGOUTSTATUS 0x11134 32 FEC_CM3_CTI_TRIGOUTSTATUS FEC_CM3_CTI_TRIGOUTSTATUS 32 0 0 FEC_CM3_CTI_CHINSTATUS 0x11138 32 FEC_CM3_CTI_CHINSTATUS FEC_CM3_CTI_CHINSTATUS 32 0 0 FEC_CM3_CTI_CHOUTSTATUS 0x1113C 32 FEC_CM3_CTI_CHOUTSTATUS FEC_CM3_CTI_CHOUTSTATUS 32 0 0 FEC_CM3_CTI_GATE 0x11140 32 FEC_CM3_CTI_GATE FEC_CM3_CTI_GATE 32 0 0 FEC_CM3_CTI_ASICCTL 0x11144 32 FEC_CM3_CTI_ASICCTL FEC_CM3_CTI_ASICCTL 32 0 0 FEC_CM3_CTI_ITCHINACK 0x11EDC 32 FEC_CM3_CTI_ITCHINACK FEC_CM3_CTI_ITCHINACK 32 0 0 FEC_CM3_CTI_ITTRIGINACK 0x11EE0 32 FEC_CM3_CTI_ITTRIGINACK FEC_CM3_CTI_ITTRIGINACK 32 0 0 FEC_CM3_CTI_ITCHOUT 0x11EE4 32 FEC_CM3_CTI_ITCHOUT FEC_CM3_CTI_ITCHOUT 32 0 0 FEC_CM3_CTI_ITTRIGOUT 0x11EE8 32 FEC_CM3_CTI_ITTRIGOUT FEC_CM3_CTI_ITTRIGOUT 32 0 0 FEC_CM3_CTI_ITCHOUTACK 0x11EEC 32 FEC_CM3_CTI_ITCHOUTACK FEC_CM3_CTI_ITCHOUTACK 32 0 0 FEC_CM3_CTI_ITTRIGOUTACK 0x11EF0 32 FEC_CM3_CTI_ITTRIGOUTACK FEC_CM3_CTI_ITTRIGOUTACK 32 0 0 FEC_CM3_CTI_ITCHIN 0x11EF4 32 FEC_CM3_CTI_ITCHIN FEC_CM3_CTI_ITCHIN 32 0 0 FEC_CM3_CTI_ITTRIGIN 0x11EF8 32 FEC_CM3_CTI_ITTRIGIN FEC_CM3_CTI_ITTRIGIN 32 0 0 FEC_CM3_CTI_ITCTRL 0x11F00 32 FEC_CM3_CTI_ITCTRL FEC_CM3_CTI_ITCTRL 32 0 0 FEC_CM3_CTI_Claim_Tag_Set 0x11FA0 32 FEC_CM3_CTI_Claim_Tag_Set FEC_CM3_CTI_Claim_Tag_Set 32 0 0 FEC_CM3_CTI_Claim_Tag_Clear 0x11FA4 32 FEC_CM3_CTI_Claim_Tag_Clear FEC_CM3_CTI_Claim_Tag_Clear 32 0 0 FEC_CM3_CTI_Lock_Access_Register 0x11FB0 32 FEC_CM3_CTI_Lock_Access_Register FEC_CM3_CTI_Lock_Access_Register 32 0 0 FEC_CM3_CTI_Lock_Status_Register 0x11FB4 32 FEC_CM3_CTI_Lock_Status_Register FEC_CM3_CTI_Lock_Status_Register 32 0 0 FEC_CM3_CTI_Authentication_Status 0x11FB8 32 FEC_CM3_CTI_Authentication_Status FEC_CM3_CTI_Authentication_Status 32 0 0 FEC_CM3_CTI_Device_ID 0x11FC8 32 FEC_CM3_CTI_Device_ID FEC_CM3_CTI_Device_ID 32 0 0 FEC_CM3_CTI_Device_Type_Identifier 0x11FCC 32 FEC_CM3_CTI_Device_Type_Identifier FEC_CM3_CTI_Device_Type_Identifier 32 0 0 FEC_CM3_CTI_PeripheralID4 0x11FD0 32 FEC_CM3_CTI_PeripheralID4 FEC_CM3_CTI_PeripheralID4 32 0 0 FEC_CM3_CTI_PeripheralID5 0x11FD4 32 FEC_CM3_CTI_PeripheralID5 FEC_CM3_CTI_PeripheralID5 32 0 0 FEC_CM3_CTI_PeripheralID6 0x11FD8 32 FEC_CM3_CTI_PeripheralID6 FEC_CM3_CTI_PeripheralID6 32 0 0 FEC_CM3_CTI_PeripheralID7 0x11FDC 32 FEC_CM3_CTI_PeripheralID7 FEC_CM3_CTI_PeripheralID7 32 0 0 FEC_CM3_CTI_PeripheralID0 0x11FE0 32 FEC_CM3_CTI_PeripheralID0 FEC_CM3_CTI_PeripheralID0 32 0 0 FEC_CM3_CTI_PeripheralID1 0x11FE4 32 FEC_CM3_CTI_PeripheralID1 FEC_CM3_CTI_PeripheralID1 32 0 0 FEC_CM3_CTI_PeripheralID2 0x11FE8 32 FEC_CM3_CTI_PeripheralID2 FEC_CM3_CTI_PeripheralID2 32 0 0 FEC_CM3_CTI_PeripheralID3 0x11FEC 32 FEC_CM3_CTI_PeripheralID3 FEC_CM3_CTI_PeripheralID3 32 0 0 FEC_CM3_CTI_Component_ID0 0x11FF0 32 FEC_CM3_CTI_Component_ID0 FEC_CM3_CTI_Component_ID0 32 0 0 FEC_CM3_CTI_Component_ID1 0x11FF4 32 FEC_CM3_CTI_Component_ID1 FEC_CM3_CTI_Component_ID1 32 0 0 FEC_CM3_CTI_Component_ID2 0x11FF8 32 FEC_CM3_CTI_Component_ID2 FEC_CM3_CTI_Component_ID2 32 0 0 FEC_CM3_CTI_Component_ID3 0x11FFC 32 FEC_CM3_CTI_Component_ID3 FEC_CM3_CTI_Component_ID3 32 0 0 APP_CFG_QSPI 0x78000000 0 116 registers APP_CFG_QSPI PID 0x0 32 PID SCHEME [31:30] The scheme of the register used. This indicates the PDR3.5 Method 2 30 Reserved [29:28] Always read as 0 2 28 FUNC [27:16] The function of the module being used 12 16 RTL [15:11] RTL Release Version The PDR release number of this IP 5 11 MAJOR [10:8] Major Release Number 3 8 CUSTOM [7:6] Custom IP 2 6 MINOR [5:0] Minor Release Number 6 0 0 MSS_QSPI_Reserved1 0x4 32 Reserved Reserved_1 [31:0] Reserved 32 0 0 MSS_QSPI_Reserved2 0x8 32 Reserved Reserved_2 [31:0] Reserved 32 0 0 MSS_QSPI_Reserved3 0xC 32 Reserved Reserved_3 [31:0] Reserved 32 0 0 SYSCONFIG 0x10 32 SYSCONFIG Reserved3 [31:6] Always read as 0 26 6 Reserved2 [5:4] Always read as 0 2 4 IDLEMODE [3:2] Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module "swakeup" output(s) is (are) implemented 2 2 Reserved1 [1:0] Always read as 0 2 0 0 MSS_QSPI_Reserved4 0x14 32 Reserved Reserved_4 [31:0] Reserved 32 0 0 MSS_QSPI_Reserved5 0x18 32 Reserved Reserved_5 [31:0] Reserved 32 0 0 MSS_QSPI_Reserved6 0x1C 32 Reserved Reserved_6 [31:0] Reserved 32 0 0 INTR_STATUS_RAW_SET 0x20 32 INTR Interrupt Status Raw/Set Register Reserved [31:2] Always read as 0 30 2 WIRQ_RAW [1:1] Word Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect 1 1 FIRQ_RAW [0:0] Frame Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect 1 0 0 INTR_STATUS_ENABLED_CLEAR 0x24 32 INTR Interrupt Status Enabled/Clear Register Reserved [31:2] Always read as 0 30 2 WIRQ_ENA [1:1] Word Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect 1 1 FIRQ_ENA [0:0] Frame Interrupt Enabled Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect 1 0 0 INTR_ENABLE_SET 0x28 32 INTR Interrupt Enable/Set Register Reserved [31:2] Always read as 0 30 2 WIRQ_ENA_SET [1:1] Word Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect 1 1 FIRQ_ENA_SET [0:0] Frame Interrupt Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect 1 0 0 INTR_ENABLE_CLEAR 0x2C 32 INTR Interrupt Enable/Clear Register Reserved [31:2] Always read as 0 30 2 WIRQ_ENA_CLR [1:1] Word Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect 1 1 FIRQ_ENA_CLR [0:0] Frame Interrupt Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect 1 0 0 INTC_EOI 0x30 32 EOI Register EOI_VECTOR [31:0] Number associated with the ipgenericirq for intr output. There are 1 interrupt outputs Write 0x0 : Write to intr IP Generic Any other write value is ignored. 32 0 0 MSS_QSPI_Reserved7 0x34 32 Reserved Reserved_7 [31:0] Reserved 32 0 0 MSS_QSPI_Reserved8 0x38 32 Reserved Reserved_8 [31:0] Reserved 32 0 0 MSS_QSPI_Reserved9 0x3C 32 Reserved Reserved_9 [31:0] Reserved 32 0 0 SPI_CLOCK_CNTRL 0x40 32 SPI Clock Control Register (SPICC) CLKEN [31:31] Clock Enable. 0- Data clock is turned off 1- Data clock is enabled 1 31 Reserved [30:16] Always read as 0 15 16 DCLK_DIV [15:0] Serial data clock divide by ratio 16 0 0 SPI_DC 0x44 32 SPI Data Control Register (SPIDC) Reserved4 [31:29] Always read as 0 3 29 DD3 [28:27] Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active 2 27 CKPH3 [26:26] Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge 1 26 CSP3 [25:25] Chip select polarity for chip select 3 0- Active low 1- Active high 1 25 CKP3 [24:24] Clock polarity for chip select 3 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 1 24 Reserved3 [23:21] Always read as 0 3 21 DD2 [20:19] Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active 2 19 CKPH2 [18:18] Clock phase for chip select 2. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge 1 18 CSP2 [17:17] Chip select polarity for chip select 2 0- Active low 1- Active high 1 17 CKP2 [16:16] Clock polarity for chip select 2 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 1 16 Reserved2 [15:13] Always read as 0 3 13 DD1 [12:11] Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active 2 11 CKPH1 [10:10] Clock phase for chip select 1. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge 1 10 CSP1 [9:9] Chip select polarity for chip select 1 0- Active low 1- Active high 1 9 CKP1 [8:8] Clock polarity for chip select 1 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 1 8 Reserved1 [7:5] Always read as 0 3 5 DD0 [4:3] Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after the CS_N goes active 2 3 CKPH0 [2:2] Clock phase for chip select 0. If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out on rising edge; input on falling edge 1 2 CSP0 [1:1] Chip select polarity for chip select 0 0- Active low 1- Active high 1 1 CKP0 [0:0] Clock polarity for chip select 0 0- When data is not being transferred, SCK = 0 1- When data is not being transferred, SCK = 1 1 0 0 SPI_CMD 0x48 32 SPI Command Register (SPICR) Reserved3 [31:30] Always read as 0 2 30 CSNUM [29:28] Device select. Sets the active chip select for the transfer 00- Chip Select 0 active 01- Chip Select 1 active 10- Chip Select 2 active 11- Chip Select 3 active 2 28 Reserved2 [27:26] Always read as 0 2 26 WLEN [25:19] Word length. Sets the size of the individual transfers from 1 – 128 bits 0- 1 bit 1- 2 bits … 127 – 128 bits 7 19 CMD [18:16] Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 – Reserved 101 – 3 pin Read Single 110 – 3 pin Write Single 111 – 6 pin Read Quad 3 16 FIRQ [15:15] Frame count interrupt enable 1 15 WIRQ [14:14] Word count interrupt enable 1 14 Reserved1 [13:12] Always read as 0 2 12 FLEN [11:0] Frame Length 0- 1 word 1- 2 words … 4095 – 4096 words 12 0 0 SPI_STATUS 0x4C 32 SPI Status Register (SPISR) Reserved2 [31:28] Always read as 0 4 28 WDCNT [27:16] Word count. This field will reflect the 1-4096 words transferred 12 16 Reserved1 [15:3] Always read as 0 13 3 FC [2:2] Frame complete. This bit is set after all of the requested words have been transmitted. 0- Transfer is not complete 1- Transfer is complete This bit is reset when the SPI Status Register is read 1 2 WC [1:1] Word complete. This bit is set after each word transfer is completed. 0- Word transfer is not complete 1- Word transfer is complete This bit is reset when the SPI Status Register is read 1 1 BUSY [0:0] Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words, the bit will clear to signal that it is ok to read/write the data registers. 0- Idle 1- Busy 1 0 0 SPI_DATA 0x50 32 SPI Data Register (SPIDR) DATA [31:0] Data register for read and write operations 32 0 0 SPI_SETUP0 0x54 32 Memory Mapped SPI Setup0 Register Reserved2 [31:29] Always read as 0 3 29 NUM_D_BITS [28:24] Number of dummy bits to use if NUM_D_BYTES = 0 5 24 WCMD [23:16] Write Command 8 16 Reserved1 [15:14] Always read as 0 2 14 READ_TYPE [13:12] Determines if the read command is a single, dual or quad read mode command 00 – Normal read (all data input on spi_din) 01 – Dual read (odd bytes input on spi_din; even on spi_dout) 10 – Normal read (all data input on spi_din) 11 – Quad read (uses spi_qdin0/1) 2 12 NUM_D_BYTES [11:10] Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits 2 10 NUM_A_BYTES [9:8] Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes 2 8 RCMD [7:0] Read Command 8 0 0 SPI_SETUP1 0x58 32 Memory Mapped SPI Setup1 Register Reserved2 [31:29] Always read as 0 3 29 NUM_D_BITS [28:24] Number of dummy bits to use if NUM_D_BYTES = 0 5 24 WCMD [23:16] Write Command 8 16 Reserved1 [15:14] Always read as 0 2 14 READ_TYPE [13:12] Determines if the read command is a single, dual or quad read mode command 00 – Normal read (all data input on spi_din) 01 – Dual read (odd bytes input on spi_din; even on spi_dout) 10 – Normal read (all data input on spi_din) 11 – Quad read (uses spi_qdin0/1) 2 12 NUM_D_BYTES [11:10] Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits 2 10 NUM_A_BYTES [9:8] Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes 2 8 RCMD [7:0] Read Command 8 0 0 SPI_SETUP2 0x5C 32 Memory Mapped SPI Setup2 Register Reserved2 [31:29] Always read as 0 3 29 NUM_D_BITS [28:24] Number of dummy bits to use if NUM_D_BYTES = 0 5 24 WCMD [23:16] Write Command 8 16 Reserved1 [15:14] Always read as 0 2 14 READ_TYPE [13:12] Determines if the read command is a single, dual or quad read mode command 00 – Normal read (all data input on spi_din) 01 – Dual read (odd bytes input on spi_din; even on spi_dout) 10 – Normal read (all data input on spi_din) 11 – Quad read (uses spi_qdin0/1) 2 12 NUM_D_BYTES [11:10] Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits 2 10 NUM_A_BYTES [9:8] Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes 2 8 RCMD [7:0] Read Command 8 0 0 SPI_SETUP3 0x60 32 Memory Mapped SPI Setup3 Register Reserved2 [31:29] Always read as 0 3 29 NUM_D_BITS [28:24] Number of dummy bits to use if NUM_D_BYTES = 0 5 24 WCMD [23:16] Write Command 8 16 Reserved1 [15:14] Always read as 0 2 14 READ_TYPE [13:12] Determines if the read command is a single, dual or quad read mode command 00 – Normal read (all data input on spi_din) 01 – Dual read (odd bytes input on spi_din; even on spi_dout) 10 – Normal read (all data input on spi_din) 11 – Quad read (uses spi_qdin0/1) 2 12 NUM_D_BYTES [11:10] Number of dummy bytes to be used for fast read. 0 = use the value in NUM_D_BITS 1 = use 8 bits; 2 = use 16 bits; 3 = use 24 bits 2 10 NUM_A_BYTES [9:8] Number of address bytes to be sent. 0 = 1 byte; 1 = 2 bytes; 2 = 3 bytes; 3 = 4 bytes 2 8 RCMD [7:0] Read Command 8 0 0 SPI_SWITCH 0x64 32 Memory Mapped SPI Switch Register Reserved [31:2] Always read as 0 30 2 MM_INT_EN [1:1] Memory Mapped mode interrupt enable. 0 – Interrupts are disabled during memory mapped operations 1 – Word Count interrupt is enabled for memory mapped operations 1 1 MMPT_S [0:0] MMPT select. If 0 (default) config port has is selected to control config of core SPI module. If 1, Memory Mapped Protocol Translator is selected to control config port of core SPI module. 1 0 0 SPI_DATA1 0x68 32 SPI Data Register (SPIDR1) DATA [31:0] Data register for read and write operations 32 0 0 SPI_DATA2 0x6C 32 SPI Data Register (SPIDR2) DATA [31:0] Data register for read and write operations 32 0 0 SPI_DATA3 0x70 32 SPI Data Register (SPIDR3) DATA [31:0] Data register for read and write operations 32 0 0