StarFive VisionFive 2 v1.3B 0.1 From StarFive VisionFive 2 v1.3B,model device generator 8 32 32 read-write clint From starfive,jh7110-clint, peripheral generator 0x2000000 0 0x10000 registers msip_0 MSIP Register for hart 0 0x0 32 0 control [0:0] read-write msip_1 MSIP Register for hart 1 0x4 32 0 control [0:0] read-write msip_2 MSIP Register for hart 2 0x8 32 0 control [0:0] read-write msip_3 MSIP Register for hart 3 0xC 32 0 control [0:0] read-write msip_4 MSIP Register for hart 4 0x10 32 0 control [0:0] read-write mtimecmp_0 MTIMECMP Register for hart 0 0x4000 64 0 cycles [63:0] read-write mtimecmp_1 MTIMECMP Register for hart 1 0x4008 64 0 cycles [63:0] read-write mtimecmp_2 MTIMECMP Register for hart 2 0x4010 64 0 cycles [63:0] read-write mtimecmp_3 MTIMECMP Register for hart 3 0x4018 64 0 cycles [63:0] read-write mtimecmp_4 MTIMECMP Register for hart 4 0x4020 64 0 cycles [63:0] read-write mtime MTIME Register 0xBFF8 64 0 cycles [63:0] read-write starfive_jh7110_ccache_0 From starfive,jh7110-ccache, peripheral generator 0x2010000 0 0x4000 registers sifive_ccache0_0 From sifive,ccache0, peripheral generator 0x2010000 0 0x4000 registers cache_0 From cache, peripheral generator 0x2010000 0 0x4000 registers plic From starfive,jh7110-plic, peripheral generator 0xC000000 0 0x4000000 registers priority_1 PRIORITY Register for interrupt id 1 0x4 32 0 priority [31:0] read-write priority_2 PRIORITY Register for interrupt id 2 0x8 32 0 priority [31:0] read-write priority_3 PRIORITY Register for interrupt id 3 0xC 32 0 priority [31:0] read-write priority_4 PRIORITY Register for interrupt id 4 0x10 32 0 priority [31:0] read-write priority_5 PRIORITY Register for interrupt id 5 0x14 32 0 priority [31:0] read-write priority_6 PRIORITY Register for interrupt id 6 0x18 32 0 priority [31:0] read-write priority_7 PRIORITY Register for interrupt id 7 0x1C 32 0 priority [31:0] read-write priority_8 PRIORITY Register for interrupt id 8 0x20 32 0 priority [31:0] read-write priority_9 PRIORITY Register for interrupt id 9 0x24 32 0 priority [31:0] read-write priority_10 PRIORITY Register for interrupt id 10 0x28 32 0 priority [31:0] read-write priority_11 PRIORITY Register for interrupt id 11 0x2C 32 0 priority [31:0] read-write priority_12 PRIORITY Register for interrupt id 12 0x30 32 0 priority [31:0] read-write priority_13 PRIORITY Register for interrupt id 13 0x34 32 0 priority [31:0] read-write priority_14 PRIORITY Register for interrupt id 14 0x38 32 0 priority [31:0] read-write priority_15 PRIORITY Register for interrupt id 15 0x3C 32 0 priority [31:0] read-write priority_16 PRIORITY Register for interrupt id 16 0x40 32 0 priority [31:0] read-write priority_17 PRIORITY Register for interrupt id 17 0x44 32 0 priority [31:0] read-write priority_18 PRIORITY Register for interrupt id 18 0x48 32 0 priority [31:0] read-write priority_19 PRIORITY Register for interrupt id 19 0x4C 32 0 priority [31:0] read-write priority_20 PRIORITY Register for interrupt id 20 0x50 32 0 priority [31:0] read-write priority_21 PRIORITY Register for interrupt id 21 0x54 32 0 priority [31:0] read-write priority_22 PRIORITY Register for interrupt id 22 0x58 32 0 priority [31:0] read-write priority_23 PRIORITY Register for interrupt id 23 0x5C 32 0 priority [31:0] read-write priority_24 PRIORITY Register for interrupt id 24 0x60 32 0 priority [31:0] read-write priority_25 PRIORITY Register for interrupt id 25 0x64 32 0 priority [31:0] read-write priority_26 PRIORITY Register for interrupt id 26 0x68 32 0 priority [31:0] read-write priority_27 PRIORITY Register for interrupt id 27 0x6C 32 0 priority [31:0] read-write priority_28 PRIORITY Register for interrupt id 28 0x70 32 0 priority [31:0] read-write priority_29 PRIORITY Register for interrupt id 29 0x74 32 0 priority [31:0] read-write priority_30 PRIORITY Register for interrupt id 30 0x78 32 0 priority [31:0] read-write priority_31 PRIORITY Register for interrupt id 31 0x7C 32 0 priority [31:0] read-write priority_32 PRIORITY Register for interrupt id 32 0x80 32 0 priority [31:0] read-write priority_33 PRIORITY Register for interrupt id 33 0x84 32 0 priority [31:0] read-write priority_34 PRIORITY Register for interrupt id 34 0x88 32 0 priority [31:0] read-write priority_35 PRIORITY Register for interrupt id 35 0x8C 32 0 priority [31:0] read-write priority_36 PRIORITY Register for interrupt id 36 0x90 32 0 priority [31:0] read-write priority_37 PRIORITY Register for interrupt id 37 0x94 32 0 priority [31:0] read-write priority_38 PRIORITY Register for interrupt id 38 0x98 32 0 priority [31:0] read-write priority_39 PRIORITY Register for interrupt id 39 0x9C 32 0 priority [31:0] read-write priority_40 PRIORITY Register for interrupt id 40 0xA0 32 0 priority [31:0] read-write priority_41 PRIORITY Register for interrupt id 41 0xA4 32 0 priority [31:0] read-write priority_42 PRIORITY Register for interrupt id 42 0xA8 32 0 priority [31:0] read-write priority_43 PRIORITY Register for interrupt id 43 0xAC 32 0 priority [31:0] read-write priority_44 PRIORITY Register for interrupt id 44 0xB0 32 0 priority [31:0] read-write priority_45 PRIORITY Register for interrupt id 45 0xB4 32 0 priority [31:0] read-write priority_46 PRIORITY Register for interrupt id 46 0xB8 32 0 priority [31:0] read-write priority_47 PRIORITY Register for interrupt id 47 0xBC 32 0 priority [31:0] read-write priority_48 PRIORITY Register for interrupt id 48 0xC0 32 0 priority [31:0] read-write priority_49 PRIORITY Register for interrupt id 49 0xC4 32 0 priority [31:0] read-write priority_50 PRIORITY Register for interrupt id 50 0xC8 32 0 priority [31:0] read-write priority_51 PRIORITY Register for interrupt id 51 0xCC 32 0 priority [31:0] read-write priority_52 PRIORITY Register for interrupt id 52 0xD0 32 0 priority [31:0] read-write priority_53 PRIORITY Register for interrupt id 53 0xD4 32 0 priority [31:0] read-write priority_54 PRIORITY Register for interrupt id 54 0xD8 32 0 priority [31:0] read-write priority_55 PRIORITY Register for interrupt id 55 0xDC 32 0 priority [31:0] read-write priority_56 PRIORITY Register for interrupt id 56 0xE0 32 0 priority [31:0] read-write priority_57 PRIORITY Register for interrupt id 57 0xE4 32 0 priority [31:0] read-write priority_58 PRIORITY Register for interrupt id 58 0xE8 32 0 priority [31:0] read-write priority_59 PRIORITY Register for interrupt id 59 0xEC 32 0 priority [31:0] read-write priority_60 PRIORITY Register for interrupt id 60 0xF0 32 0 priority [31:0] read-write priority_61 PRIORITY Register for interrupt id 61 0xF4 32 0 priority [31:0] read-write priority_62 PRIORITY Register for interrupt id 62 0xF8 32 0 priority [31:0] read-write priority_63 PRIORITY Register for interrupt id 63 0xFC 32 0 priority [31:0] read-write priority_64 PRIORITY Register for interrupt id 64 0x100 32 0 priority [31:0] read-write priority_65 PRIORITY Register for interrupt id 65 0x104 32 0 priority [31:0] read-write priority_66 PRIORITY Register for interrupt id 66 0x108 32 0 priority [31:0] read-write priority_67 PRIORITY Register for interrupt id 67 0x10C 32 0 priority [31:0] read-write priority_68 PRIORITY Register for interrupt id 68 0x110 32 0 priority [31:0] read-write priority_69 PRIORITY Register for interrupt id 69 0x114 32 0 priority [31:0] read-write priority_70 PRIORITY Register for interrupt id 70 0x118 32 0 priority [31:0] read-write priority_71 PRIORITY Register for interrupt id 71 0x11C 32 0 priority [31:0] read-write priority_72 PRIORITY Register for interrupt id 72 0x120 32 0 priority [31:0] read-write priority_73 PRIORITY Register for interrupt id 73 0x124 32 0 priority [31:0] read-write priority_74 PRIORITY Register for interrupt id 74 0x128 32 0 priority [31:0] read-write priority_75 PRIORITY Register for interrupt id 75 0x12C 32 0 priority [31:0] read-write priority_76 PRIORITY Register for interrupt id 76 0x130 32 0 priority [31:0] read-write priority_77 PRIORITY Register for interrupt id 77 0x134 32 0 priority [31:0] read-write priority_78 PRIORITY Register for interrupt id 78 0x138 32 0 priority [31:0] read-write priority_79 PRIORITY Register for interrupt id 79 0x13C 32 0 priority [31:0] read-write priority_80 PRIORITY Register for interrupt id 80 0x140 32 0 priority [31:0] read-write priority_81 PRIORITY Register for interrupt id 81 0x144 32 0 priority [31:0] read-write priority_82 PRIORITY Register for interrupt id 82 0x148 32 0 priority [31:0] read-write priority_83 PRIORITY Register for interrupt id 83 0x14C 32 0 priority [31:0] read-write priority_84 PRIORITY Register for interrupt id 84 0x150 32 0 priority [31:0] read-write priority_85 PRIORITY Register for interrupt id 85 0x154 32 0 priority [31:0] read-write priority_86 PRIORITY Register for interrupt id 86 0x158 32 0 priority [31:0] read-write priority_87 PRIORITY Register for interrupt id 87 0x15C 32 0 priority [31:0] read-write priority_88 PRIORITY Register for interrupt id 88 0x160 32 0 priority [31:0] read-write priority_89 PRIORITY Register for interrupt id 89 0x164 32 0 priority [31:0] read-write priority_90 PRIORITY Register for interrupt id 90 0x168 32 0 priority [31:0] read-write priority_91 PRIORITY Register for interrupt id 91 0x16C 32 0 priority [31:0] read-write priority_92 PRIORITY Register for interrupt id 92 0x170 32 0 priority [31:0] read-write priority_93 PRIORITY Register for interrupt id 93 0x174 32 0 priority [31:0] read-write priority_94 PRIORITY Register for interrupt id 94 0x178 32 0 priority [31:0] read-write priority_95 PRIORITY Register for interrupt id 95 0x17C 32 0 priority [31:0] read-write priority_96 PRIORITY Register for interrupt id 96 0x180 32 0 priority [31:0] read-write priority_97 PRIORITY Register for interrupt id 97 0x184 32 0 priority [31:0] read-write priority_98 PRIORITY Register for interrupt id 98 0x188 32 0 priority [31:0] read-write priority_99 PRIORITY Register for interrupt id 99 0x18C 32 0 priority [31:0] read-write priority_100 PRIORITY Register for interrupt id 100 0x190 32 0 priority [31:0] read-write priority_101 PRIORITY Register for interrupt id 101 0x194 32 0 priority [31:0] read-write priority_102 PRIORITY Register for interrupt id 102 0x198 32 0 priority [31:0] read-write priority_103 PRIORITY Register for interrupt id 103 0x19C 32 0 priority [31:0] read-write priority_104 PRIORITY Register for interrupt id 104 0x1A0 32 0 priority [31:0] read-write priority_105 PRIORITY Register for interrupt id 105 0x1A4 32 0 priority [31:0] read-write priority_106 PRIORITY Register for interrupt id 106 0x1A8 32 0 priority [31:0] read-write priority_107 PRIORITY Register for interrupt id 107 0x1AC 32 0 priority [31:0] read-write priority_108 PRIORITY Register for interrupt id 108 0x1B0 32 0 priority [31:0] read-write priority_109 PRIORITY Register for interrupt id 109 0x1B4 32 0 priority [31:0] read-write priority_110 PRIORITY Register for interrupt id 110 0x1B8 32 0 priority [31:0] read-write priority_111 PRIORITY Register for interrupt id 111 0x1BC 32 0 priority [31:0] read-write priority_112 PRIORITY Register for interrupt id 112 0x1C0 32 0 priority [31:0] read-write priority_113 PRIORITY Register for interrupt id 113 0x1C4 32 0 priority [31:0] read-write priority_114 PRIORITY Register for interrupt id 114 0x1C8 32 0 priority [31:0] read-write priority_115 PRIORITY Register for interrupt id 115 0x1CC 32 0 priority [31:0] read-write priority_116 PRIORITY Register for interrupt id 116 0x1D0 32 0 priority [31:0] read-write priority_117 PRIORITY Register for interrupt id 117 0x1D4 32 0 priority [31:0] read-write priority_118 PRIORITY Register for interrupt id 118 0x1D8 32 0 priority [31:0] read-write priority_119 PRIORITY Register for interrupt id 119 0x1DC 32 0 priority [31:0] read-write priority_120 PRIORITY Register for interrupt id 120 0x1E0 32 0 priority [31:0] read-write priority_121 PRIORITY Register for interrupt id 121 0x1E4 32 0 priority [31:0] read-write priority_122 PRIORITY Register for interrupt id 122 0x1E8 32 0 priority [31:0] read-write priority_123 PRIORITY Register for interrupt id 123 0x1EC 32 0 priority [31:0] read-write priority_124 PRIORITY Register for interrupt id 124 0x1F0 32 0 priority [31:0] read-write priority_125 PRIORITY Register for interrupt id 125 0x1F4 32 0 priority [31:0] read-write priority_126 PRIORITY Register for interrupt id 126 0x1F8 32 0 priority [31:0] read-write priority_127 PRIORITY Register for interrupt id 127 0x1FC 32 0 priority [31:0] read-write priority_128 PRIORITY Register for interrupt id 128 0x200 32 0 priority [31:0] read-write priority_129 PRIORITY Register for interrupt id 129 0x204 32 0 priority [31:0] read-write priority_130 PRIORITY Register for interrupt id 130 0x208 32 0 priority [31:0] read-write priority_131 PRIORITY Register for interrupt id 131 0x20C 32 0 priority [31:0] read-write priority_132 PRIORITY Register for interrupt id 132 0x210 32 0 priority [31:0] read-write priority_133 PRIORITY Register for interrupt id 133 0x214 32 0 priority [31:0] read-write priority_134 PRIORITY Register for interrupt id 134 0x218 32 0 priority [31:0] read-write priority_135 PRIORITY Register for interrupt id 135 0x21C 32 0 priority [31:0] read-write priority_136 PRIORITY Register for interrupt id 136 0x220 32 0 priority [31:0] read-write pending_0 PENDING Register for interrupt ids 31 to 0 0x1000 32 0 pending [31:0] read-write pending_1 PENDING Register for interrupt ids 63 to 32 0x1004 32 0 pending [31:0] read-write pending_2 PENDING Register for interrupt ids 95 to 64 0x1008 32 0 pending [31:0] read-write pending_3 PENDING Register for interrupt ids 127 to 96 0x100C 32 0 pending [31:0] read-write pending_4 PENDING Register for interrupt ids 136 to 128 0x1010 32 0 pending [31:0] read-write enable_0_0 ENABLE Register for interrupt ids 31 to 0 for hart 0 0x2000 0 enable [31:0] read-write enable_1_0 ENABLE Register for interrupt ids 63 to 32 for hart 0 0x2004 0 enable [31:0] read-write enable_2_0 ENABLE Register for interrupt ids 95 to 64 for hart 0 0x2008 0 enable [31:0] read-write enable_3_0 ENABLE Register for interrupt ids 127 to 96 for hart 0 0x200C 0 enable [31:0] read-write enable_4_0 ENABLE Register for interrupt ids 136 to 128 for hart 0 0x2010 0 enable [31:0] read-write enable_0_1 ENABLE Register for interrupt ids 31 to 0 for hart 1 0x2080 0 enable [31:0] read-write enable_1_1 ENABLE Register for interrupt ids 63 to 32 for hart 1 0x2084 0 enable [31:0] read-write enable_2_1 ENABLE Register for interrupt ids 95 to 64 for hart 1 0x2088 0 enable [31:0] read-write enable_3_1 ENABLE Register for interrupt ids 127 to 96 for hart 1 0x208C 0 enable [31:0] read-write enable_4_1 ENABLE Register for interrupt ids 136 to 128 for hart 1 0x2090 0 enable [31:0] read-write enable_0_2 ENABLE Register for interrupt ids 31 to 0 for hart 2 0x2100 0 enable [31:0] read-write enable_1_2 ENABLE Register for interrupt ids 63 to 32 for hart 2 0x2104 0 enable [31:0] read-write enable_2_2 ENABLE Register for interrupt ids 95 to 64 for hart 2 0x2108 0 enable [31:0] read-write enable_3_2 ENABLE Register for interrupt ids 127 to 96 for hart 2 0x210C 0 enable [31:0] read-write enable_4_2 ENABLE Register for interrupt ids 136 to 128 for hart 2 0x2110 0 enable [31:0] read-write enable_0_3 ENABLE Register for interrupt ids 31 to 0 for hart 3 0x2180 0 enable [31:0] read-write enable_1_3 ENABLE Register for interrupt ids 63 to 32 for hart 3 0x2184 0 enable [31:0] read-write enable_2_3 ENABLE Register for interrupt ids 95 to 64 for hart 3 0x2188 0 enable [31:0] read-write enable_3_3 ENABLE Register for interrupt ids 127 to 96 for hart 3 0x218C 0 enable [31:0] read-write enable_4_3 ENABLE Register for interrupt ids 136 to 128 for hart 3 0x2190 0 enable [31:0] read-write enable_0_4 ENABLE Register for interrupt ids 31 to 0 for hart 4 0x2200 0 enable [31:0] read-write enable_1_4 ENABLE Register for interrupt ids 63 to 32 for hart 4 0x2204 0 enable [31:0] read-write enable_2_4 ENABLE Register for interrupt ids 95 to 64 for hart 4 0x2208 0 enable [31:0] read-write enable_3_4 ENABLE Register for interrupt ids 127 to 96 for hart 4 0x220C 0 enable [31:0] read-write enable_4_4 ENABLE Register for interrupt ids 136 to 128 for hart 4 0x2210 0 enable [31:0] read-write threshold_0 PRIORITY THRESHOLD Register for hart 0 0x200000 32 0 priority [31:0] read-write claimplete_0 CLAIM and COMPLETE Register for hart 0 0x200004 32 0 claimplete [31:0] read-write threshold_1 PRIORITY THRESHOLD Register for hart 1 0x201000 32 0 priority [31:0] read-write claimplete_1 CLAIM and COMPLETE Register for hart 1 0x201004 32 0 claimplete [31:0] read-write threshold_2 PRIORITY THRESHOLD Register for hart 2 0x202000 32 0 priority [31:0] read-write claimplete_2 CLAIM and COMPLETE Register for hart 2 0x202004 32 0 claimplete [31:0] read-write threshold_3 PRIORITY THRESHOLD Register for hart 3 0x203000 32 0 priority [31:0] read-write claimplete_3 CLAIM and COMPLETE Register for hart 3 0x203004 32 0 claimplete [31:0] read-write threshold_4 PRIORITY THRESHOLD Register for hart 4 0x204000 32 0 priority [31:0] read-write claimplete_4 CLAIM and COMPLETE Register for hart 4 0x204004 32 0 claimplete [31:0] read-write uart0 From snps,dw-apb-uart, peripheral generator 0x10000000 0 0x10000 registers uart0 27 rbr Receive Buffer Register 0x0 32 0 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 32 0 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only dll Divisor Latch Low 0x0 32 0 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write dlh Divisor Latch High 0x4 32 0 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write ier Interrupt Enable Register 0x4 32 0 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write iir Interrupt Identity Register 0x8 32 1 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only fcr FIFO Control Register 0x8 32 0 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xc 32 0 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write mcr Modem Control Register 0x10 32 0 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 32 0 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Line Status Register 0x18 32 0 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1c 32 0 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 32 0 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 32 0 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write srbr0 Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr0 Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr1 Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr1 Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr2 Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr2 Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr3 Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr3 Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr4 Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr4 Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr5 Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr5 Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr6 Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr6 Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr7 Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr7 Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr8 Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr8 Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr9 Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr9 Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr10 Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr10 Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr11 Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr11 Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr12 Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr12 Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr13 Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr13 Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr14 Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr14 Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr15 Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr15 Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only far FIFO Access Register 0x70 32 0 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 32 0 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 32 0 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only usr UART Status Register 0x7c 32 0 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 32 0 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 32 0 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 32 0 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8c 32 0 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 32 0 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 32 0 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 32 0 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9c 32 0 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xa0 32 0 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write htx Halt TX 0xa4 32 0 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xa8 32 0 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xf4 32 0 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 0 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 1146552592 ctr This register contains the peripherals identification code. [31:0] read-only uart1 From snps,dw-apb-uart, peripheral generator 0x10010000 0 0x10000 registers uart1 28 rbr Receive Buffer Register 0x0 32 0 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 32 0 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only dll Divisor Latch Low 0x0 32 0 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write dlh Divisor Latch High 0x4 32 0 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write ier Interrupt Enable Register 0x4 32 0 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write iir Interrupt Identity Register 0x8 32 1 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only fcr FIFO Control Register 0x8 32 0 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xc 32 0 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write mcr Modem Control Register 0x10 32 0 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 32 0 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Line Status Register 0x18 32 0 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1c 32 0 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 32 0 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 32 0 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write srbr0 Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr0 Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr1 Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr1 Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr2 Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr2 Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr3 Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr3 Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr4 Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr4 Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr5 Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr5 Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr6 Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr6 Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr7 Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr7 Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr8 Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr8 Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr9 Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr9 Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr10 Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr10 Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr11 Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr11 Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr12 Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr12 Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr13 Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr13 Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr14 Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr14 Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr15 Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr15 Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only far FIFO Access Register 0x70 32 0 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 32 0 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 32 0 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only usr UART Status Register 0x7c 32 0 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 32 0 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 32 0 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 32 0 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8c 32 0 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 32 0 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 32 0 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 32 0 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9c 32 0 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xa0 32 0 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write htx Halt TX 0xa4 32 0 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xa8 32 0 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xf4 32 0 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 0 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 1146552592 ctr This register contains the peripherals identification code. [31:0] read-only uart2 From snps,dw-apb-uart, peripheral generator 0x10020000 0 0x10000 registers uart2 29 rbr Receive Buffer Register 0x0 32 0 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 32 0 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only dll Divisor Latch Low 0x0 32 0 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write dlh Divisor Latch High 0x4 32 0 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write ier Interrupt Enable Register 0x4 32 0 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write iir Interrupt Identity Register 0x8 32 1 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only fcr FIFO Control Register 0x8 32 0 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xc 32 0 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write mcr Modem Control Register 0x10 32 0 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 32 0 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Line Status Register 0x18 32 0 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1c 32 0 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 32 0 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 32 0 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write srbr0 Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr0 Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr1 Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr1 Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr2 Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr2 Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr3 Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr3 Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr4 Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr4 Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr5 Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr5 Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr6 Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr6 Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr7 Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr7 Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr8 Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr8 Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr9 Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr9 Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr10 Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr10 Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr11 Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr11 Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr12 Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr12 Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr13 Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr13 Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr14 Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr14 Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr15 Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr15 Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only far FIFO Access Register 0x70 32 0 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 32 0 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 32 0 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only usr UART Status Register 0x7c 32 0 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 32 0 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 32 0 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 32 0 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8c 32 0 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 32 0 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 32 0 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 32 0 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9c 32 0 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xa0 32 0 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write htx Halt TX 0xa4 32 0 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xa8 32 0 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xf4 32 0 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 0 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 1146552592 ctr This register contains the peripherals identification code. [31:0] read-only i2c0 From snps,designware-i2c, peripheral generator 0x10030000 0 0x10000 registers i2c0 30 con DesignWare I2C CON 0x0 32 0 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write tar DesignWare I2C TAR 0x4 32 0 address_7bit Target address, 7-bit mode [6:0] read-write address_10bit Target address, 10-bit mode [9:0] read-write mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write sar DesignWare I2C SAR 0x8 32 0 address_7bit Slave address, 7-bit mode [6:0] read-write address_10bit Slave address, 10-bit mode [9:0] read-write data_cmd DesignWare I2C Data Command 0x10 32 0 dat Data Command Data Byte [7:0] read-write read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 32 0 ss_scl_hcnt ss_scl_hcnt [31:0] read-write ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 32 0 ss_scl_lcnt ss_scl_lcnt [31:0] read-write fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1c 32 0 fs_scl_hcnt fs_scl_hcnt [31:0] read-write fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 32 0 fs_scl_lcnt fs_scl_lcnt [31:0] read-write hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 32 0 hs_scl_hcnt hs_scl_hcnt [31:0] read-write hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 32 0 hs_scl_lcnt hs_scl_lcnt [31:0] read-write intr_stat DesignWare I2C Interrupt Status 0x2c 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 32 0 rx_tl rx_tl [31:0] read-write tx_tl DesignWare I2C TX TL 0x3c 32 0 tx_tl tx_tl [31:0] read-write clr_intr DesignWare I2C Clear Interrrupt 0x40 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write clr_rx_under DesignWare I2C Clear RX Underrun 0x44 32 0 clr_rx_under clr_rx_under [31:0] read-write clr_rx_over DesignWare I2C Clear RX Overrun 0x48 32 0 clr_rx_over clr_rx_over [31:0] read-write clr_tx_over DesignWare I2C Clear TX Overrun 0x4c 32 0 clr_tx_over clr_tx_over [31:0] read-write clr_rd_req DesignWare I2C Clear Read Request 0x50 32 0 clr_rd_req clr_rd_req [31:0] read-write clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 32 0 clr_tx_abrt clr_tx_abrt [31:0] read-write clr_rx_done DesignWare I2C Clear RX Done 0x58 32 0 clr_rx_done clr_rx_done [31:0] read-write clr_activity DesignWare I2C Clear Activity 0x5c 32 0 clr_activity clr_activity [31:0] read-write clr_stop_det DesignWare I2C Clear Stop DET 0x60 32 0 clr_stop_det clr_stop_det [31:0] read-write clr_start_det DesignWare I2C Clear Start DET 0x64 32 0 clr_start_det clr_start_det [31:0] read-write clr_gen_call DesignWare I2C Clear General Call 0x68 32 0 clr_gen_call clr_gen_call [31:0] read-write enable DesignWare I2C Enable 0x6c 32 0 abort abort [1:1] read-write status DesignWare I2C Status 0x70 32 0 activity activity [0:0] read-only tfe tfe [2:2] read-only rfne rfne [3:3] read-only master_activity master_activity [5:5] read-only slave_activity slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 32 0 txflr txflr [31:0] read-write rxflr DesignWare I2C RX Failure 0x78 32 0 rxflr rxflr [31:0] read-write sda_hold DesignWare I2C SDA Hold 0x7c 32 0 sda_hold sda_hold [31:0] read-write tx_abrt_source DesignWare I2C TX Abort Source 0x80 32 0 b7_addr_noack b7_addr_noack [0:0] read-only b10_addr1_noack b10_addr1_noack [1:1] read-only b10_addr2_noack b10_addr2_noack [2:2] read-only txdata_noack txdata_noack [3:3] read-only gcall_noack gcall_noack [4:4] read-only gcall_read gcall_read [5:5] read-only sbyte_ackdet sbyte_ackdet [7:7] read-only sbyte_norstrt sbyte_norstrt [9:9] read-only b10_rd_norstrt b10_rd_norstrt [10:10] read-only master_dis master_dis [11:11] read-only arb_lost arb_lost [12:12] read-only slave_flush_txfifo slave_flush_txfifo [13:13] read-only slave_arblost slave_arblost [14:14] read-only slave_rd_intx slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9c 32 0 activity activity [0:0] read-write tfe tfe [2:2] read-write rfne rfne [3:3] read-write master_activity master_activity [5:5] read-write slave_activity slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xa8 32 0 clr_restart_det clr_restart_det [31:0] read-write comp_param_1 DesignWare I2C Compatibility Parameter 1 0xf4 32 0 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only comp_version DesignWare I2C Compatibility Version 0xf8 32 0 comp_version comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xfc 32 0 comp_type comp_type [31:0] read-only i2c1 From snps,designware-i2c, peripheral generator 0x10040000 0 0x10000 registers i2c1 31 con DesignWare I2C CON 0x0 32 0 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write tar DesignWare I2C TAR 0x4 32 0 address_7bit Target address, 7-bit mode [6:0] read-write address_10bit Target address, 10-bit mode [9:0] read-write mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write sar DesignWare I2C SAR 0x8 32 0 address_7bit Slave address, 7-bit mode [6:0] read-write address_10bit Slave address, 10-bit mode [9:0] read-write data_cmd DesignWare I2C Data Command 0x10 32 0 dat Data Command Data Byte [7:0] read-write read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 32 0 ss_scl_hcnt ss_scl_hcnt [31:0] read-write ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 32 0 ss_scl_lcnt ss_scl_lcnt [31:0] read-write fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1c 32 0 fs_scl_hcnt fs_scl_hcnt [31:0] read-write fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 32 0 fs_scl_lcnt fs_scl_lcnt [31:0] read-write hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 32 0 hs_scl_hcnt hs_scl_hcnt [31:0] read-write hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 32 0 hs_scl_lcnt hs_scl_lcnt [31:0] read-write intr_stat DesignWare I2C Interrupt Status 0x2c 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 32 0 rx_tl rx_tl [31:0] read-write tx_tl DesignWare I2C TX TL 0x3c 32 0 tx_tl tx_tl [31:0] read-write clr_intr DesignWare I2C Clear Interrrupt 0x40 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write clr_rx_under DesignWare I2C Clear RX Underrun 0x44 32 0 clr_rx_under clr_rx_under [31:0] read-write clr_rx_over DesignWare I2C Clear RX Overrun 0x48 32 0 clr_rx_over clr_rx_over [31:0] read-write clr_tx_over DesignWare I2C Clear TX Overrun 0x4c 32 0 clr_tx_over clr_tx_over [31:0] read-write clr_rd_req DesignWare I2C Clear Read Request 0x50 32 0 clr_rd_req clr_rd_req [31:0] read-write clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 32 0 clr_tx_abrt clr_tx_abrt [31:0] read-write clr_rx_done DesignWare I2C Clear RX Done 0x58 32 0 clr_rx_done clr_rx_done [31:0] read-write clr_activity DesignWare I2C Clear Activity 0x5c 32 0 clr_activity clr_activity [31:0] read-write clr_stop_det DesignWare I2C Clear Stop DET 0x60 32 0 clr_stop_det clr_stop_det [31:0] read-write clr_start_det DesignWare I2C Clear Start DET 0x64 32 0 clr_start_det clr_start_det [31:0] read-write clr_gen_call DesignWare I2C Clear General Call 0x68 32 0 clr_gen_call clr_gen_call [31:0] read-write enable DesignWare I2C Enable 0x6c 32 0 abort abort [1:1] read-write status DesignWare I2C Status 0x70 32 0 activity activity [0:0] read-only tfe tfe [2:2] read-only rfne rfne [3:3] read-only master_activity master_activity [5:5] read-only slave_activity slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 32 0 txflr txflr [31:0] read-write rxflr DesignWare I2C RX Failure 0x78 32 0 rxflr rxflr [31:0] read-write sda_hold DesignWare I2C SDA Hold 0x7c 32 0 sda_hold sda_hold [31:0] read-write tx_abrt_source DesignWare I2C TX Abort Source 0x80 32 0 b7_addr_noack b7_addr_noack [0:0] read-only b10_addr1_noack b10_addr1_noack [1:1] read-only b10_addr2_noack b10_addr2_noack [2:2] read-only txdata_noack txdata_noack [3:3] read-only gcall_noack gcall_noack [4:4] read-only gcall_read gcall_read [5:5] read-only sbyte_ackdet sbyte_ackdet [7:7] read-only sbyte_norstrt sbyte_norstrt [9:9] read-only b10_rd_norstrt b10_rd_norstrt [10:10] read-only master_dis master_dis [11:11] read-only arb_lost arb_lost [12:12] read-only slave_flush_txfifo slave_flush_txfifo [13:13] read-only slave_arblost slave_arblost [14:14] read-only slave_rd_intx slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9c 32 0 activity activity [0:0] read-write tfe tfe [2:2] read-write rfne rfne [3:3] read-write master_activity master_activity [5:5] read-write slave_activity slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xa8 32 0 clr_restart_det clr_restart_det [31:0] read-write comp_param_1 DesignWare I2C Compatibility Parameter 1 0xf4 32 0 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only comp_version DesignWare I2C Compatibility Version 0xf8 32 0 comp_version comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xfc 32 0 comp_type comp_type [31:0] read-only i2c2 From snps,designware-i2c, peripheral generator 0x10050000 0 0x10000 registers i2c2 32 con DesignWare I2C CON 0x0 32 0 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write tar DesignWare I2C TAR 0x4 32 0 address_7bit Target address, 7-bit mode [6:0] read-write address_10bit Target address, 10-bit mode [9:0] read-write mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write sar DesignWare I2C SAR 0x8 32 0 address_7bit Slave address, 7-bit mode [6:0] read-write address_10bit Slave address, 10-bit mode [9:0] read-write data_cmd DesignWare I2C Data Command 0x10 32 0 dat Data Command Data Byte [7:0] read-write read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 32 0 ss_scl_hcnt ss_scl_hcnt [31:0] read-write ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 32 0 ss_scl_lcnt ss_scl_lcnt [31:0] read-write fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1c 32 0 fs_scl_hcnt fs_scl_hcnt [31:0] read-write fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 32 0 fs_scl_lcnt fs_scl_lcnt [31:0] read-write hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 32 0 hs_scl_hcnt hs_scl_hcnt [31:0] read-write hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 32 0 hs_scl_lcnt hs_scl_lcnt [31:0] read-write intr_stat DesignWare I2C Interrupt Status 0x2c 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 32 0 rx_tl rx_tl [31:0] read-write tx_tl DesignWare I2C TX TL 0x3c 32 0 tx_tl tx_tl [31:0] read-write clr_intr DesignWare I2C Clear Interrrupt 0x40 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write clr_rx_under DesignWare I2C Clear RX Underrun 0x44 32 0 clr_rx_under clr_rx_under [31:0] read-write clr_rx_over DesignWare I2C Clear RX Overrun 0x48 32 0 clr_rx_over clr_rx_over [31:0] read-write clr_tx_over DesignWare I2C Clear TX Overrun 0x4c 32 0 clr_tx_over clr_tx_over [31:0] read-write clr_rd_req DesignWare I2C Clear Read Request 0x50 32 0 clr_rd_req clr_rd_req [31:0] read-write clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 32 0 clr_tx_abrt clr_tx_abrt [31:0] read-write clr_rx_done DesignWare I2C Clear RX Done 0x58 32 0 clr_rx_done clr_rx_done [31:0] read-write clr_activity DesignWare I2C Clear Activity 0x5c 32 0 clr_activity clr_activity [31:0] read-write clr_stop_det DesignWare I2C Clear Stop DET 0x60 32 0 clr_stop_det clr_stop_det [31:0] read-write clr_start_det DesignWare I2C Clear Start DET 0x64 32 0 clr_start_det clr_start_det [31:0] read-write clr_gen_call DesignWare I2C Clear General Call 0x68 32 0 clr_gen_call clr_gen_call [31:0] read-write enable DesignWare I2C Enable 0x6c 32 0 abort abort [1:1] read-write status DesignWare I2C Status 0x70 32 0 activity activity [0:0] read-only tfe tfe [2:2] read-only rfne rfne [3:3] read-only master_activity master_activity [5:5] read-only slave_activity slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 32 0 txflr txflr [31:0] read-write rxflr DesignWare I2C RX Failure 0x78 32 0 rxflr rxflr [31:0] read-write sda_hold DesignWare I2C SDA Hold 0x7c 32 0 sda_hold sda_hold [31:0] read-write tx_abrt_source DesignWare I2C TX Abort Source 0x80 32 0 b7_addr_noack b7_addr_noack [0:0] read-only b10_addr1_noack b10_addr1_noack [1:1] read-only b10_addr2_noack b10_addr2_noack [2:2] read-only txdata_noack txdata_noack [3:3] read-only gcall_noack gcall_noack [4:4] read-only gcall_read gcall_read [5:5] read-only sbyte_ackdet sbyte_ackdet [7:7] read-only sbyte_norstrt sbyte_norstrt [9:9] read-only b10_rd_norstrt b10_rd_norstrt [10:10] read-only master_dis master_dis [11:11] read-only arb_lost arb_lost [12:12] read-only slave_flush_txfifo slave_flush_txfifo [13:13] read-only slave_arblost slave_arblost [14:14] read-only slave_rd_intx slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9c 32 0 activity activity [0:0] read-write tfe tfe [2:2] read-write rfne rfne [3:3] read-write master_activity master_activity [5:5] read-write slave_activity slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xa8 32 0 clr_restart_det clr_restart_det [31:0] read-write comp_param_1 DesignWare I2C Compatibility Parameter 1 0xf4 32 0 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only comp_version DesignWare I2C Compatibility Version 0xf8 32 0 comp_version comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xfc 32 0 comp_type comp_type [31:0] read-only spi0 From arm,pl022, peripheral generator 0x10060000 0 0x10000 registers spi0 33 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 16 0 dss Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data [3:0] read-write frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [6:6] read-write scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 16 0 lbm Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write sse Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] read-write ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 16 0 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xc 16 0 tfe Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only tnf Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only rne Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only rff Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only bsy PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 16 0 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 16 0 rorim Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write rtim Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write rxim Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write txim Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked [2:2] read-write ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 16 0 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1c 16 0 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 16 0 roric Clears the SSPRORINTR interrupt [0:0] read-write rtic Clears the SSPRTINTR interrupt [1:1] read-write ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 16 0 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe0 16 0 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe4 16 0 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe8 16 0 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfec 16 0 configuration These bits read back as 0x80 [7:0] read-only ssp_pcell_id0 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff0 16 0 ssp_pcell_id0 The bits are read as 0xD [7:0] read-only ssp_pcell_id1 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff4 16 0 ssp_pcell_id1 The bits are read as 0xF0 [7:0] read-only ssp_pcell_id2 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff8 16 0 ssp_pcell_id2 The bits are read as 0x5 [7:0] read-only ssp_pcell_id3 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xffc 16 0 ssp_pcell_id3 The bits are read as 0xB1 [7:0] read-only arm_primecell_0 From arm,primecell, peripheral generator 0x10060000 0 0x10000 registers rohm_dh2228fv_0 From rohm,dh2228fv, peripheral generator 0x0 0 0x0 registers spi1 From arm,pl022, peripheral generator 0x10070000 0 0x10000 registers spi1 34 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 16 0 dss Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data [3:0] read-write frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [6:6] read-write scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 16 0 lbm Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write sse Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] read-write ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 16 0 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xc 16 0 tfe Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only tnf Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only rne Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only rff Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only bsy PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 16 0 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 16 0 rorim Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write rtim Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write rxim Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write txim Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked [2:2] read-write ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 16 0 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1c 16 0 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 16 0 roric Clears the SSPRORINTR interrupt [0:0] read-write rtic Clears the SSPRTINTR interrupt [1:1] read-write ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 16 0 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe0 16 0 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe4 16 0 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe8 16 0 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfec 16 0 configuration These bits read back as 0x80 [7:0] read-only ssp_pcell_id0 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff0 16 0 ssp_pcell_id0 The bits are read as 0xD [7:0] read-only ssp_pcell_id1 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff4 16 0 ssp_pcell_id1 The bits are read as 0xF0 [7:0] read-only ssp_pcell_id2 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff8 16 0 ssp_pcell_id2 The bits are read as 0x5 [7:0] read-only ssp_pcell_id3 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xffc 16 0 ssp_pcell_id3 The bits are read as 0xB1 [7:0] read-only arm_primecell_1 From arm,primecell, peripheral generator 0x10070000 0 0x10000 registers spi2 From arm,pl022, peripheral generator 0x10080000 0 0x10000 registers spi2 35 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 16 0 dss Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data [3:0] read-write frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [6:6] read-write scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 16 0 lbm Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write sse Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] read-write ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 16 0 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xc 16 0 tfe Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only tnf Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only rne Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only rff Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only bsy PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 16 0 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 16 0 rorim Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write rtim Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write rxim Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write txim Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked [2:2] read-write ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 16 0 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1c 16 0 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 16 0 roric Clears the SSPRORINTR interrupt [0:0] read-write rtic Clears the SSPRTINTR interrupt [1:1] read-write ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 16 0 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe0 16 0 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe4 16 0 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe8 16 0 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfec 16 0 configuration These bits read back as 0x80 [7:0] read-only ssp_pcell_id0 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff0 16 0 ssp_pcell_id0 The bits are read as 0xD [7:0] read-only ssp_pcell_id1 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff4 16 0 ssp_pcell_id1 The bits are read as 0xF0 [7:0] read-only ssp_pcell_id2 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff8 16 0 ssp_pcell_id2 The bits are read as 0x5 [7:0] read-only ssp_pcell_id3 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xffc 16 0 ssp_pcell_id3 The bits are read as 0xB1 [7:0] read-only arm_primecell_2 From arm,primecell, peripheral generator 0x10080000 0 0x10000 registers starfive_jh7110_tdm_0 From starfive,jh7110-tdm, peripheral generator 0x10090000 0 0x1000 registers starfive_jh7110_usb_phy_0 From starfive,jh7110-usb-phy, peripheral generator 0x10200000 0 0x10000 registers starfive_jh7110_pcie_phy_0 From starfive,jh7110-pcie-phy, peripheral generator 0x10210000 0 0x10000 registers starfive_jh7110_pcie_phy_1 From starfive,jh7110-pcie-phy, peripheral generator 0x10220000 0 0x10000 registers stgcrg From starfive,jh7110-stgcrg, peripheral generator 0x10230000 0 0x10000 registers clk_hifi4_core Clock HIFI4 Core 0x0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_usb_apb Clock USB APB 0x4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_usb_utmi_apb Clock USB UTMI APB 0x8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_usb_axi Clock USB AXI 0xc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_usb_ipm Clock USB AXI 0x10 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_usb_stb Clock USB STB 0x14 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 [23:0] read-write clk_usb_app125 Clock USB APP 125 0x18 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_usb_refclk Clock USB Reference Clock 0x1c 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_u0_pcie_axi_mst0 U0 Clock PCIe AXI MST 0 0x20 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_pcie_apb U0 Clock PCIe APB 0x24 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_pcie_tl U0 Clock PCIe TL 0x28 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_pcie_axi_mst0 U1 Clock PCIe AXI MST 0 0x2c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_pcie_apb U1 Clock PCIe APB 0x30 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_pcie_tl U1 Clock PCIe TL 0x34 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_pcie01_slv_dec_main Clock PCIe 01 SLV DEC Main 0x38 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_sec_hclk Clock Security HCLK 0x3c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_sec_misc_ahb Clock Security Miscellaneous AHB 0x40 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_stg_mtrx_group0_main Clock STG MTRX Group 0 Main 0x44 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_stg_mtrx_group0_bus Clock STG MTRX Group 0 Bus 0x48 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_stg_mtrx_group0_stg Clock STG MTRX Group 0 STG 0x4c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_stg_mtrx_group1_main Clock STG MTRX Group 1 Main 0x50 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_stg_mtrx_group1_bus Clock STG MTRX Group 1 Bus 0x54 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_stg_mtrx_group1_stg Clock STG MTRX Group 1 STG 0x58 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_stg_mtrx_group1_hifi Clock STG MTRX Group 1 HIFI 0x5c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_e2_rtc Clock E2 RTC 0x60 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 [23:0] read-write clk_e2_core Clock E2 Core 0x64 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_e2_dbg Clock E2 DBG 0x68 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_dma_axi Clock DMA AXI 0x6c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_dma_ahb Clock DMA AHB 0x70 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write soft_rst_addr_sel Software RESET Address Selector 0x74 32 0 u0_stg_syscon_presetn 1: Assert reset, 0: De-assert reset [0:0] read-write u0_hifi4_core 1: Assert reset, 0: De-assert reset [1:1] read-write u0_hifi4_axi 1: Assert reset, 0: De-assert reset [2:2] read-write u0_sec_top_hreesetn 1: Assert reset, 0: De-assert reset [3:3] read-write u0_e2_core 1: Assert reset, 0: De-assert reset [4:4] read-write u0_dma_axi 1: Assert reset, 0: De-assert reset [5:5] read-write u0_dma_ahb 1: Assert reset, 0: De-assert reset [6:6] read-write u0_usb_axi 1: Assert reset, 0: De-assert reset [7:7] read-write u0_usb_apb 1: Assert reset, 0: De-assert reset [8:8] read-write u0_usb_utmi_apb 1: Assert reset, 0: De-assert reset [9:9] read-write u0_usb_pwrup 1: Assert reset, 0: De-assert reset [10:10] read-write u0_pcie_axi_mst0 1: Assert reset, 0: De-assert reset [11:11] read-write u0_pcie_axi_slv0 1: Assert reset, 0: De-assert reset [12:12] read-write u0_pcie_axi_slv 1: Assert reset, 0: De-assert reset [13:13] read-write u0_pci_brg 1: Assert reset, 0: De-assert reset [14:14] read-write u0_pcie_pcie 1: Assert reset, 0: De-assert reset [15:15] read-write u0_pcie_apb 1: Assert reset, 0: De-assert reset [16:16] read-write u1_pcie_axi_mst0 1: Assert reset, 0: De-assert reset [17:17] read-write u1_pcie_axi_slv0 1: Assert reset, 0: De-assert reset [18:18] read-write u1_pcie_axi_slv 1: Assert reset, 0: De-assert reset [19:19] read-write u1_pcie_brg 1: Assert reset, 0: De-assert reset [20:20] read-write u1_pcie_pcie 1: Assert reset, 0: De-assert reset [21:21] read-write u1_pcie_apb 1: Assert reset, 0: De-assert reset [22:22] read-write stgcrg_rst_stat STGCRG RESET Status 0x78 32 0 u0_stg_syscon_presetn 1: Assert reset, 0: De-assert reset [0:0] read-write u0_hifi4_core 1: Assert reset, 0: De-assert reset [1:1] read-write u0_hifi4_axi 1: Assert reset, 0: De-assert reset [2:2] read-write u0_sec_top_hreesetn 1: Assert reset, 0: De-assert reset [3:3] read-write u0_e2_core 1: Assert reset, 0: De-assert reset [4:4] read-write u0_dma_axi 1: Assert reset, 0: De-assert reset [5:5] read-write u0_dma_ahb 1: Assert reset, 0: De-assert reset [6:6] read-write u0_usb_axi 1: Assert reset, 0: De-assert reset [7:7] read-write u0_usb_apb 1: Assert reset, 0: De-assert reset [8:8] read-write u0_usb_utmi_apb 1: Assert reset, 0: De-assert reset [9:9] read-write u0_usb_pwrup 1: Assert reset, 0: De-assert reset [10:10] read-write u0_pcie_axi_mst0 1: Assert reset, 0: De-assert reset [11:11] read-write u0_pcie_axi_slv0 1: Assert reset, 0: De-assert reset [12:12] read-write u0_pcie_axi_slv 1: Assert reset, 0: De-assert reset [13:13] read-write u0_pci_brg 1: Assert reset, 0: De-assert reset [14:14] read-write u0_pcie_pcie 1: Assert reset, 0: De-assert reset [15:15] read-write u0_pcie_apb 1: Assert reset, 0: De-assert reset [16:16] read-write u1_pcie_axi_mst0 1: Assert reset, 0: De-assert reset [17:17] read-write u1_pcie_axi_slv0 1: Assert reset, 0: De-assert reset [18:18] read-write u1_pcie_axi_slv 1: Assert reset, 0: De-assert reset [19:19] read-write u1_pcie_brg 1: Assert reset, 0: De-assert reset [20:20] read-write u1_pcie_pcie 1: Assert reset, 0: De-assert reset [21:21] read-write u1_pcie_apb 1: Assert reset, 0: De-assert reset [22:22] read-write stg_syscon From starfive,jh7110-stg-syscon, peripheral generator 0x10240000 0 0x1000 registers stg_syscfg_0 STG SYCONSAIF SYSCFG 0 0x0 32 0 scfg_hprot_sd_0 scfg_hprot_sd_0 [3:0] read-write scfg_hprot_sd_1 scfg_hprot_sd_1 [7:4] read-write u0_usb_adp_en u0_usb_adp_en [8:8] read-only u0_usb_adp_probe_ana u0_usb_adp_probe_ana [9:9] read-write u0_usb_adp_probe_en u0_usb_adp_probe_en [10:10] read-only u0_usb_adp_sense_ana u0_usb_adp_sense_ana [11:11] read-write u0_usb_adp_sense_en u0_usb_adp_sense_en [12:12] read-only u0_usb_adp_sink_current_en u0_usb_adp_sink_current_en [13:13] read-only u0_usb_adp_source_current_en u0_usb_adp_source_current_en [14:14] read-only u0_usb_bc_en u0_usb_bc_en [15:15] read-only u0_usb_chrg_vbus u0_usb_chrg_vbus [16:16] read-write u0_usb_dcd_comp_sts u0_usb_dcd_comp_sts [17:17] read-write u0_usb_dischrg_vbus u0_usb_dischrg_vbus [18:18] read-write u0_usb_dm_vdat_ref_comp_en u0_usb_dm_vdat_ref_comp_en [19:19] read-only u0_usb_dm_vdat_ref_comp_sts u0_usb_dm_vdat_ref_comp_sts [20:20] read-write u0_usb_dm_vlgc_comp_en u0_usb_dm_vlgc_comp_en [21:21] read-only u0_usb_dm_vlgc_comp_sts u0_usb_dm_vlgc_comp_sts [22:22] read-write u0_usb_dp_vdat_ref_comp_en u0_usb_dp_vdat_ref_comp_en [23:23] read-only u0_usb_dp_vdat_ref_comp_sts u0_usb_dp_vdat_ref_comp_sts [24:24] read-write u0_usb_host_system_err u0_usb_host_system_err [25:25] read-write u0_usb_hsystem_err_ext u0_usb_hsystem_err_ext [26:26] read-only u0_usb_idm_sink_en u0_usb_idm_sink_en [27:27] read-only u0_usb_idp_sink_en u0_usb_idp_sink_en [28:28] read-only u0_usb_idp_src_en u0_usb_idp_src_en [29:29] read-only stg_syscfg_1 STG SYSCONSAIF SYSCFG 4 0x4 32 0 u0_usb_lowest_belt LTM interface to software [11:0] read-only u0_usb_ltm_host_req LTM interface to software [12:12] read-only u0_usb_ltm_host_req_halt LTM interface to software [13:13] read-write u0_usb_mdctrl_clk_sel u0_usb_mdctrl_clk_sel [14:14] read-write u0_usb_mdctrl_clk_status u0_usb_mdctrl_clk_status [15:15] read-only u0_usb_mode_strap Can onlly be changed when pwrup_rst_n is low [18:16] read-write u0_usb_otg_suspendm u0_usb_otg_suspendm [19:19] read-write u0_usb_otg_suspendm_byps u0_usb_otg_suspendm_byps [20:20] read-write u0_usb_phy_bvalid u0_usb_phy_bvalid [21:21] read-only u0_usb_pll_en u0_usb_pll_en [22:22] read-write u0_usb_refclk_mode u0_usb_refclk_mode [23:23] read-write u0_cdn_usb_rid_comp_sts_0 u0_cdn_usb_rid_comp_sts_0 [24:24] read-write u0_cdn_usb_rid_comp_sts_1 u0_cdn_usb_rid_comp_sts_1 [25:25] read-write u0_cdn_usb_rid_comp_sts_2 u0_cdn_usb_rid_comp_sts_2 [26:26] read-write u0_usb_rid_float_comp_en u0_usb_rid_float_comp_en [27:27] read-only u0_usb_rid_float_comp_sts u0_usb_rid_float_comp_sts [28:28] read-write u0_usb_rid_gnd_comp_sts u0_usb_rid_gnd_comp_sts [29:29] read-write u0_usb_rid_nonfloat_comp_en u0_usb_rid_nonfloat_comp_en [30:30] read-only u0_usb_rx_dm u0_usb_rx_dm [31:31] read-only stg_syscfg_2 STG SYSCONSAIF SYSCFG 8 0x8 32 0 u0_usb_rx_dp u0_usb_rx_dp [0:0] read-only u0_usb_rx_rcv u0_usb_rx_rcv [1:1] read-only u0_usb_self_test For software bist_test [2:2] read-write u0_usb_sessend u0_usb_sessend [3:3] read-only u0_usb_sessvalid u0_usb_sessvalid [4:4] read-only u0_usb_sof u0_usb_sof [5:5] read-only u0_usb_test_bist For software bist_test [6:6] read-only u0_usb_usbdev_main_power_off_ack u0_usb_usbdev_main_power_off_ack [7:7] read-only u0_usb_usbdev_main_power_off_ready u0_usb_usbdev_main_power_off_ready [8:8] read-only u0_usb_usbdev_main_power_off_req u0_usb_usbdev_main_power_off_req [9:9] read-write u0_usb_usbdev_main_power_on_ready u0_usb_usbdev_main_power_on_ready [10:10] read-only u0_usb_usbdev_main_power_on_req u0_usb_usbdev_main_power_on_req [11:11] read-only u0_usb_usbdev_main_power_on_valid u0_usb_usbdev_main_power_on_valid [12:12] read-write u0_usb_usbdev_power_off_ack u0_usb_usbdev_power_off_ack [13:13] read-only u0_usb_usbdev_power_off_ready u0_usb_usbdev_power_off_ready [14:14] read-only u0_usb_usbdev_power_off_req u0_usb_usbdev_power_off_req [15:15] read-write u0_usb_usbdev_power_on_ready u0_usb_usbdev_power_on_ready [16:16] read-only u0_usb_usbdev_power_on_req u0_usb_usbdev_power_on_req [17:17] read-only u0_usb_usbdev_power_on_valid u0_usb_usbdev_power_on_valid [18:18] read-write u0_usb_utmi_dmpulldown_sit u0_usb_utmi_dmpulldown_sit [19:19] read-write u0_usb_utmi_dppulldown_sit u0_usb_utmi_dppulldown_sit [20:20] read-write u0_usb_utmi_fslsserialmode_sit u0_usb_utmi_fslsserialmode_sit [21:21] read-write u0_usb_utmi_hostdisconnect_sit u0_usb_utmi_hostdisconnect_sit [22:22] read-only u0_usb_utmi_iddig_sit u0_usb_utmi_iddig_sit [23:23] read-only u0_usb_utmi_idpullup_sit u0_usb_utmi_idpullup_sit [24:24] read-write u0_usb_utmi_linestate_sit u0_usb_utmi_linestate_sit [26:25] read-only u0_usb_utmi_opmode_sit u0_usb_utmi_opmode_sit [28:27] read-write u0_usb_utmi_rxactive_sit u0_usb_utmi_rxactive_sit [29:29] read-only u0_usb_utmi_rxerror_sit u0_usb_utmi_rxerror_sit [30:30] read-only u0_usb_utmi_rxvalid_sit u0_usb_utmi_rxvalid_sit [31:31] read-only stg_syscfg_3 STG SYSCONSAIF SYSCFG 12 0xc 32 0 u0_usb_utmi_rxvalidh_sit u0_usb_utmi_rxvalidh_sit [0:0] read-only u0_usb_utmi_sessvld u0_usb_utmi_sessvld [1:1] read-write u0_usb_utmi_termselect_sit u0_usb_utmi_termselect_sit [2:2] read-write u0_usb_utmi_tx_dat_sit u0_usb_utmi_tx_dat_sit [3:3] read-write u0_usb_utmi_tx_enable_n_sit u0_usb_utmi_tx_enable_n_sit [4:4] read-write u0_usb_utmi_tx_se0_sit u0_usb_utmi_tx_se0_sit [5:5] read-write u0_usb_utmi_txbitstuffenable_sit u0_usb_utmi_txbitstuffenable_sit [6:6] read-write u0_usb_utmi_txready_sit u0_usb_utmi_txready_sit [7:7] read-only u0_usb_utmi_txvalid_sit u0_usb_utmi_txvalid_sit [8:8] read-write u0_usb_utmi_txvalidh_sit u0_usb_utmi_txvalidh_sit [9:9] read-write u0_usb_utmi_vbusvalid_sit u0_usb_utmi_vbusvalid_sit [10:10] read-only u0_usb_utmi_xcvrselect_sit u0_usb_utmi_xcvrselect_sit [12:11] read-write u0_usb_utmi_vdm_src_en u0_usb_utmi_vdm_src_en [13:13] read-only u0_usb_utmi_vdp_src_en u0_usb_utmi_vdp_src_en [14:14] read-only u0_usb_wakeup u0_usb_wakeup [15:15] read-write u0_usb_xhc_d0_ack u0_usb_xhc_d0_ack [16:16] read-only u0_usb_xhc_d0_req u0_usb_xhc_d0_req [17:17] read-write stg_syscfg_4 STG SYSCONSAIF SYSCFG 16 0x10 32 0 u0_usb_xhci_debug_bus u0_usb_xhci_debug_bus [31:0] read-only stg_syscfg_5 STG SYSCONSAIF SYSCFG 20 0x14 32 0 u0_usb_xhci_debug_link_state u0_usb_xhci_debug_link_state [30:0] read-only stg_syscfg_6 STG SYSCONSAIF SYSCFG 24 0x18 32 0 u0_usb_xhci_debug_sel u0_usb_xhci_debug_sel [4:0] read-write u0_usb_xhci_main_power_off_ack u0_usb_xhci_main_power_off_ack [5:5] read-only u0_usb_xhci_main_power_off_req u0_usb_xhci_main_power_off_req [6:6] read-only u0_usb_xhci_main_power_on_ready u0_usb_xhci_main_power_on_ready [7:7] read-write u0_usb_xhci_main_power_on_req u0_usb_xhci_main_power_on_req [8:8] read-only u0_usb_xhci_main_power_on_valid u0_usb_xhci_main_power_on_valid [9:9] read-write u0_usb_xhci_power_off_ack u0_usb_xhci_power_off_ack [10:10] read-only u0_usb_xhci_power_off_ready u0_usb_xhci_power_off_ready [11:11] read-only u0_usb_xhci_power_off_req u0_usb_xhci_power_off_req [12:12] read-write u0_usb_xhci_power_on_ready u0_usb_xhci_power_on_ready [13:13] read-only u0_usb_xhci_power_on_req u0_usb_xhci_power_on_req [14:14] read-only u0_usb_xhci_power_on_valid u0_usb_xhci_power_on_valid [15:15] read-write u0_e2_cease_from_tile_0 u0_e2_cease_from_tile_0 [16:16] read-only u0_e2_debug_from_tile_0 u0_e2_debug_from_tile_0 [17:17] read-only u0_e2_halt_from_tile_0 u0_e2_halt_from_tile_0 [18:18] read-only stg_syscfg_7 STG SYSCONSAIF SYSCFG 28 0x1c 32 0 u0_e2_nmi_exception_vector u0_e2_nmi_exception_vector [31:0] read-write stg_syscfg_8 STG SYSCONSAIF SYSCFG 32 0x20 32 0 u0_e2_nmi_interrupt_vector u0_e2_nmi_interrupt_vector [31:0] read-write stg_syscfg_9 STG SYSCONSAIF SYSCFG 36 0x24 32 0 u0_e2_reset_vector_0 u0_e2_reset_vector_0 [31:0] read-write stg_syscfg_10 STG SYSCONSAIF SYSCFG 40 0x28 32 0 u0_e2_wfi_from_tile_0 u0_e2_wfi_from_tile_0 [0:0] read-only stg_syscfg_11 STG SYSCONSAIF SYSCFG 44 0x2c 32 0 u0_hifi4_altresetvec Reset Vector Address [31:0] read-write stg_syscfg_12 STG SYSCONSAIF SYSCFG 48 0x30 32 0 u0_hifi4_breakin Debug signal [0:0] read-write u0_hifi4_breakinack Debug signal [1:1] read-only u0_hifi4_breakout Debug signal [2:2] read-only u0_hifi4_breakoutack Debug signal [3:3] read-write u0_hifi4_debugmode Debug signal [4:4] read-only u0_hifi4_doubleexceptionerror Fault Handling Signals [5:5] read-only u0_hifi4_iram0loadstore Indicates that iram0 works [6:6] read-only u0_hifi4_iram1loadstore Indicates that iram1 works [7:7] read-only u0_hifi4_ocdhaltonreset Debug signal [8:8] read-write u0_hifi4_pfatalerror Fault Handling Signals [9:9] read-only stg_syscfg_13 STG SYSCONSAIF SYSCFG 52 0x34 32 0 u0_hifi4_pfaultinfo Fault Handling Signals [31:0] read-only stg_syscfg_14 STG SYSCONSAIF SYSCFG 56 0x38 32 0 u0_hifi4_pfaultinfovalid Fault Handling Signals [0:0] read-only u0_hifi4_prid Module ID [16:1] read-write u0_hifi4_pwaitmode Wait Mode [17:17] read-only u0_hifi4_runstall Run Stall [18:18] read-write stg_syscfg_15 STG SYSCONSAIF SYSCFG 60 0x3c 32 0 u0_hifi4_scfg_dsp_mst_offset_master Indicates that master port remap address [11:0] read-write u0_hifi4_scfg_dsp_mst_offset_dma Indicates the DMA port remap address [27:16] read-write stg_syscfg_16 STG SYSCONSAIF SYSCFG 64 0x40 32 0 u0_hifi4_scfg_dsp_slv_offset The value indicates the slave port remap address [31:0] read-write stg_syscfg_17 STG SYSCONSAIF SYSCFG 68 0x44 32 0 u0_hifi4_scfg_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [0:0] read-write u0_hifi4_scfg_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [1:1] read-write u0_hifi4_scfg_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [3:2] read-write u0_hifi4_scfg_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [5:4] read-write u0_hifi4_scfg_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [7:6] read-write u0_hifi4_scfg_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write u0_hifi4_scfg_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write u0_hifi4_scfg_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write u0_hifi4_statvectorsel When the value is 1, it indicates that the AltResetVec is valid [12:12] read-write u0_hifi4_trigin_idma DMA port trigger [13:13] read-write u0_hifi4_trigout_idma DMA port trigger [14:14] read-only u0_hifi4_xocdmode Debug signal [15:15] read-only u0_pcie_align_detect u0_pcie_align_detect [16:16] read-only stg_syscfg_18 STG SYSCONSAIF SYSCFG 72 0x48 32 0 u0_pcie_axi4_mst0_aratomop_31_0 u0_pcie_axi4_mst0_aratomop_31_0 [31:0] read-only stg_syscfg_19 STG SYSCONSAIF SYSCFG 76 0x4c 32 0 u0_pcie_axi4_mst0_aratomop_63_32 u0_pcie_axi4_mst0_aratomop_63_32 [31:0] read-only stg_syscfg_20 STG SYSCONSAIF SYSCFG 80 0x50 32 0 u0_pcie_axi4_mst0_aratomop_95_64 u0_pcie_axi4_mst0_aratomop_95_64 [31:0] read-only stg_syscfg_21 STG SYSCONSAIF SYSCFG 84 0x54 32 0 u0_pcie_axi4_mst0_aratomop_127_96 u0_pcie_axi4_mst0_aratomop_127_96 [31:0] read-only stg_syscfg_22 STG SYSCONSAIF SYSCFG 88 0x58 32 0 u0_pcie_axi4_mst0_aratomop_159_128 u0_pcie_axi4_mst0_aratomop_159_128 [31:0] read-only stg_syscfg_23 STG SYSCONSAIF SYSCFG 92 0x5c 32 0 u0_pcie_axi4_mst0_aratomop_191_160 u0_pcie_axi4_mst0_aratomop_191_160 [31:0] read-only stg_syscfg_24 STG SYSCONSAIF SYSCFG 96 0x60 32 0 u0_pcie_axi4_mst0_aratomop_223_192 u0_pcie_axi4_mst0_aratomop_223_192 [31:0] read-only stg_syscfg_25 STG SYSCONSAIF SYSCFG 100 0x64 32 0 u0_pcie_axi4_mst0_aratomop_255_224 u0_pcie_axi4_mst0_aratomop_255_224 [31:0] read-only stg_syscfg_26 STG SYSCONSAIF SYSCFG 104 0x68 32 0 u0_pcie_axi4_mst0_aratomop_257_256 u0_pcie_axi4_mst0_aratomop_257_256 [1:0] read-only u0_pcie_axi4_mst0_arfunc u0_pcie_axi4_mst0_arfunc [16:2] read-only u0_pcie_axi4_mst0_arregion u0_pcie_axi4_mst0_arregion [20:17] read-only stg_syscfg_27 STG SYSCONSAIF SYSCFG 108 0x6c 32 0 u0_pcie_axi4_mst0_aruser_31_0 u0_pcie_axi4_mst0_aruser_31_0 [31:0] read-only stg_syscfg_28 STG SYSCONSAIF SYSCFG 112 0x70 32 0 u0_pcie_axi4_mst0_aruser_63_32 u0_pcie_axi4_mst0_aruser_63_32 [31:0] read-only stg_syscfg_29 STG SYSCONSAIF SYSCFG 116 0x74 32 0 u0_pcie_axi4_mst0_awfunc u0_pcie_axi4_mst0_awfunc [14:0] read-only u0_pcie_axi4_mst0_awregion u0_pcie_axi4_mst0_awregion [18:15] read-only stg_syscfg_30 STG SYSCONSAIF SYSCFG 120 0x78 32 0 u0_pcie_axi4_mst0_a2user_31_0 u0_pcie_axi4_mst0_a2user_31_0 [31:0] read-only stg_syscfg_31 STG SYSCONSAIF SYSCFG 124 0x7c 32 0 u0_pcie_axi4_mst0_awuser_42_32 u0_pcie_axi4_mst0_awuser_42_32 [10:0] read-only u0_pcie_axi4_mst0_rderr u0_pcie_axi4_mst0_rderr [18:11] read-write stg_syscfg_32 STG SYSCONSAIF SYSCFG 128 0x80 32 0 u0_pcie_axi4_mst0_ruser u0_pcie_axi4_mst0_ruser [31:0] read-write stg_syscfg_33 STG SYSCONSAIF SYSCFG 132 0x84 32 0 u0_pcie_axi4_mst0_wderr u0_pcie_axi4_mst0_wderr [7:0] read-only stg_syscfg_34 STG SYSCONSAIF SYSCFG 136 0x88 32 0 u0_pcie_axi4_slv0_aratomop_31_0 u0_pcie_axi4_slv0_aratomop_31_0 [31:0] read-write stg_syscfg_35 STG SYSCONSAIF SYSCFG 140 0x8c 32 0 u0_pcie_axi4_slv0_aratomop_63_32 u0_pcie_axi4_slv0_aratomop_63_32 [31:0] read-write stg_syscfg_36 STG SYSCONSAIF SYSCFG 144 0x90 32 0 u0_pcie_axi4_slv0_aratomop_95_64 u0_pcie_axi4_slv0_aratomop_95_64 [31:0] read-write stg_syscfg_37 STG SYSCONSAIF SYSCFG 148 0x94 32 0 u0_pcie_axi4_slv0_aratomop_127_96 u0_pcie_axi4_slv0_aratomop_127_96 [31:0] read-write stg_syscfg_38 STG SYSCONSAIF SYSCFG 152 0x98 32 0 u0_pcie_axi4_slv0_aratomop_159_128 u0_pcie_axi4_slv0_aratomop_159_128 [31:0] read-write stg_syscfg_39 STG SYSCONSAIF SYSCFG 156 0x9c 32 0 u0_pcie_axi4_slv0_aratomop_191_160 u0_pcie_axi4_slv0_aratomop_191_160 [31:0] read-write stg_syscfg_40 STG SYSCONSAIF SYSCFG 160 0xa0 32 0 u0_pcie_axi4_slv0_aratomop_223_192 u0_pcie_axi4_slv0_aratomop_223_192 [31:0] read-write stg_syscfg_41 STG SYSCONSAIF SYSCFG 164 0xa4 32 0 u0_pcie_axi4_slv0_aratomop_255_224 u0_pcie_axi4_slv0_aratomop_255_224 [31:0] read-write stg_syscfg_42 STG SYSCONSAIF SYSCFG 168 0xa8 32 0 u0_pcie_axi4_slv0_aratomop_257_256 u0_pcie_axi4_slv0_aratomop_257_256 [1:0] read-write u0_pcie_axi4_slv0_arfunc u0_pcie_axi4_slv0_arfunc [16:2] read-write u0_pcie_axi4_slv0_arregion u0_pcie_axi4_slv0_arregion [20:17] read-write stg_syscfg_43 STG SYSCONSAIF SYSCFG 172 0xac 32 0 u0_pcie_axi4_slv0_aruser_31_0 u0_pcie_axi4_slv0_aruser_31_0 [31:0] read-write stg_syscfg_44 STG SYSCONSAIF SYSCFG 176 0xb0 32 0 u0_pcie_axi4_slv0_aruser_40_32 u0_pcie_axi4_slv0_aruser_40_32 [8:0] read-write u0_pcie_axi4_slv0_awfunc u0_pcie_axi4_slv0_awfunc [23:9] read-write u0_pcie_axi4_slv0_awregion u0_pcie_axi4_slv0_awregion [27:24] read-write stg_syscfg_45 STG SYSCONSAIF SYSCFG 180 0xb4 32 0 u0_pcie_axi4_slv0_awuser_31_0 u0_pcie_axi4_slv0_awuser_31_0 [31:0] read-write stg_syscfg_46 STG SYSCONSAIF SYSCFG 184 0xb8 32 0 u0_pcie_axi4_slv0_awuser_40_32 u0_pcie_axi4_slv0_awuser_40_32 [8:0] read-write u0_pcie_axi4_slv0_rderr u0_pcie_axi4_slv0_rderr [16:9] read-only stg_syscfg_47 STG SYSCONSAIF SYSCFG 188 0xbc 32 0 u0_pcie_axi4_slv0_ruser u0_pcie_axi4_slv0_ruser [31:0] read-only stg_syscfg_48 STG SYSCONSAIF SYSCFG 192 0xc0 32 0 u0_pcie_axi4_slv0_wderr u0_pcie_axi4_slv0_wderr [7:0] read-write u0_pcie_axi4_slvl_arfunc u0_pcie_axi4_slvl_arfunc [22:8] read-only stg_syscfg_49 STG SYSCONSAIF SYSCFG 196 0xc4 32 0 u0_pcie_axi4_slvl_awfunc u0_pcie_axi4_slvl_awfunc [14:0] read-write u0_pcie_bus_width_o u0_pcie_bus_width_o [16:15] read-only u0_pcie_bypass_codec u0_pcie_bypass_codec [17:17] read-write u0_pcie_ckref_src u0_pcie_ckref_src [19:18] read-write u0_pcie_clk_sel u0_pcie_clk_sel [21:20] read-write u0_pcie_clkreq u0_pcie_clkreq [22:22] read-write stg_syscfg_50 STG SYSCONSAIF SYSCFG 200 0xc8 32 0 u0_pcie_k_phyparam_31_0 u0_pcie_k_phyparam_31_0 [31:0] read-write stg_syscfg_51 STG SYSCONSAIF SYSCFG 204 0xcc 32 0 u0_pcie_k_phyparam_63_32 u0_pcie_k_phyparam_63_32 [31:0] read-write stg_syscfg_52 STG SYSCONSAIF SYSCFG 208 0xd0 32 0 u0_pcie_k_phyparam_95_64 u0_pcie_k_phyparam_95_64 [31:0] read-write stg_syscfg_53 STG SYSCONSAIF SYSCFG 212 0xd4 32 0 u0_pcie_k_phyparam_127_96 u0_pcie_k_phyparam_127_96 [31:0] read-write stg_syscfg_54 STG SYSCONSAIF SYSCFG 216 0xd8 32 0 u0_pcie_k_phyparam_159_128 u0_pcie_k_phyparam_159_128 [31:0] read-write stg_syscfg_55 STG SYSCONSAIF SYSCFG 220 0xdc 32 0 u0_pcie_k_phyparam_191_160 u0_pcie_k_phyparam_191_160 [31:0] read-write stg_syscfg_56 STG SYSCONSAIF SYSCFG 224 0xe0 32 0 u0_pcie_k_phyparam_223_192 u0_pcie_k_phyparam_223_192 [31:0] read-write stg_syscfg_57 STG SYSCONSAIF SYSCFG 228 0xe4 32 0 u0_pcie_k_phyparam_255_224 u0_pcie_k_phyparam_255_224 [31:0] read-write stg_syscfg_58 STG SYSCONSAIF SYSCFG 232 0xe8 32 0 u0_pcie_k_phyparam_287_256 u0_pcie_k_phyparam_287_256 [31:0] read-write stg_syscfg_59 STG SYSCONSAIF SYSCFG 236 0xec 32 0 u0_pcie_k_phyparam_319_288 u0_pcie_k_phyparam_319_288 [31:0] read-write stg_syscfg_60 STG SYSCONSAIF SYSCFG 240 0xf0 32 0 u0_pcie_k_phyparam_351_320 u0_pcie_k_phyparam_351_320 [31:0] read-write stg_syscfg_61 STG SYSCONSAIF SYSCFG 244 0xf4 32 0 u0_pcie_k_phyparam_383_352 u0_pcie_k_phyparam_383_352 [31:0] read-write stg_syscfg_62 STG SYSCONSAIF SYSCFG 248 0xf8 32 0 u0_pcie_k_phyparam_415_384 u0_pcie_k_phyparam_415_384 [31:0] read-write stg_syscfg_63 STG SYSCONSAIF SYSCFG 252 0xfc 32 0 u0_pcie_k_phyparam_447_416 u0_pcie_k_phyparam_447_416 [31:0] read-write stg_syscfg_64 STG SYSCONSAIF SYSCFG 256 0x100 32 0 u0_pcie_k_phyparam_479_448 u0_pcie_k_phyparam_479_448 [31:0] read-write stg_syscfg_65 STG SYSCONSAIF SYSCFG 260 0x104 32 0 u0_pcie_k_phyparam_511_480 u0_pcie_k_phyparam_511_480 [31:0] read-write stg_syscfg_66 STG SYSCONSAIF SYSCFG 264 0x108 32 0 u0_pcie_k_phyparam_543_512 u0_pcie_k_phyparam_543_512 [31:0] read-write stg_syscfg_67 STG SYSCONSAIF SYSCFG 268 0x10c 32 0 u0_pcie_k_phyparam_575_544 u0_pcie_k_phyparam_575_544 [31:0] read-write stg_syscfg_68 STG SYSCONSAIF SYSCFG 272 0x110 32 0 u0_pcie_k_phyparam_607_576 u0_pcie_k_phyparam_607_576 [31:0] read-write stg_syscfg_69 STG SYSCONSAIF SYSCFG 276 0x114 32 0 u0_pcie_k_phyparam_639_608 u0_pcie_k_phyparam_639_608 [31:0] read-write stg_syscfg_70 STG SYSCONSAIF SYSCFG 280 0x118 32 0 u0_pcie_k_phyparam_671_640 u0_pcie_k_phyparam_671_640 [31:0] read-write stg_syscfg_71 STG SYSCONSAIF SYSCFG 284 0x11c 32 0 u0_pcie_k_phyparam_703_672 u0_pcie_k_phyparam_703_672 [31:0] read-write stg_syscfg_72 STG SYSCONSAIF SYSCFG 288 0x120 32 0 u0_pcie_k_phyparam_735_704 u0_pcie_k_phyparam_735_704 [31:0] read-write stg_syscfg_73 STG SYSCONSAIF SYSCFG 292 0x124 32 0 u0_pcie_k_phyparam_767_736 u0_pcie_k_phyparam_767_736 [31:0] read-write stg_syscfg_74 STG SYSCONSAIF SYSCFG 296 0x128 32 0 u0_pcie_k_phyparam_799_768 u0_pcie_k_phyparam_799_768 [31:0] read-write stg_syscfg_75 STG SYSCONSAIF SYSCFG 300 0x12c 32 0 u0_pcie_k_phyparam_831_800 u0_pcie_k_phyparam_831_800 [31:0] read-write stg_syscfg_76 STG SYSCONSAIF SYSCFG 304 0x130 32 0 u0_pcie_k_phyparam_839_832 u0_pcie_k_phyparam_839_832 [7:0] read-write u0_pcie_k_rp_nep u0_pcie_k_rp_nep [8:8] read-write u0_pcie_l1sub_entack u0_pcie_l1sub_entack [9:9] read-only u0_pcie_l1sub_entreq u0_pcie_l1sub_entreq [10:10] read-write stg_syscfg_77 STG SYSCONSAIF SYSCFG 308 0x134 32 0 u0_pcie_local_interrupt_in u0_pcie_local_interrupt_in [31:0] read-write stg_syscfg_78 STG SYSCONSAIF SYSCFG 312 0x138 32 0 u0_pcie_mperstn u0_pcie_mperstn [0:0] read-write u0_pcie_pcie_ebuf_mode u0_pcie_pcie_ebuf_mode [1:1] read-write u0_pcie_pcie_phy_test_cfg u0_pcie_pcie_phy_test_cfg [24:2] read-write u0_pcie_pcie_rx_eq_training u0_pcie_pcie_rx_eq_training [25:25] read-write u0_pcie_pcie_rxterm_en u0_pcie_pcie_rxterm_en [26:26] read-write u0_pcie_pcie_tx_onezeros u0_pcie_pcie_tx_onezeros [27:27] read-write stg_syscfg_79 STG SYSCONSAIF SYSCFG 316 0x13c 32 0 u0_pcie_pf0_offset u0_pcie_pf0_offset [19:0] read-write stg_syscfg_80 STG SYSCONSAIF SYSCFG 320 0x140 32 0 u0_pcie_pf1_offset u0_pcie_pf1_offset [19:0] read-write stg_syscfg_81 STG SYSCONSAIF SYSCFG 324 0x144 32 0 u0_pcie_pf2_offset u0_pcie_pf2_offset [19:0] read-write stg_syscfg_82 STG SYSCONSAIF SYSCFG 328 0x148 32 0 u0_pcie_pf3_offset u0_pcie_pf3_offset [19:0] read-write u0_pcie_phy_mode u0_pcie_phy_mode [21:20] read-write u0_pcie_pl_clkrem_allow u0_pcie_pl_clkrem_allow [22:22] read-write u0_pcie_pl_clkreq_oen u0_pcie_pl_clkreq_oen [23:23] read-only u0_pcie_pl_equ_phase u0_pcie_pl_equ_phase [25:24] read-only u0_pcie_pl_ltssm u0_pcie_pl_ltssm [30:26] read-only stg_syscfg_83 STG SYSCONSAIF SYSCFG 332 0x14c 32 0 u0_pcie_pl_pclk_rate u0_pcie_pl_pclk_rate [4:0] read-only stg_syscfg_84 STG SYSCONSAIF SYSCFG 336 0x150 32 0 u0_pcie_pl_sideband_in_31_0 u0_pcie_pl_sideband_in_31_0 [31:0] read-only stg_syscfg_85 STG SYSCONSAIF SYSCFG 340 0x154 32 0 u0_pcie_pl_sideband_in_63_32 u0_pcie_pl_sideband_in_63_32 [31:0] read-only stg_syscfg_86 STG SYSCONSAIF SYSCFG 344 0x158 32 0 u0_pcie_pl_sideband_out_31_0 u0_pcie_pl_sideband_out_31_0 [31:0] read-only stg_syscfg_87 STG SYSCONSAIF SYSCFG 348 0x15c 32 0 u0_pcie_pl_sideband_out_63_32 u0_pcie_pl_sideband_out_63_32 [31:0] read-only stg_syscfg_88 STG SYSCONSAIF SYSCFG 352 0x160 32 0 u0_pcie_pl_wake_in u0_pcie_pl_wake_in [0:0] read-write u0_pcie_pl_wake_oen u0_pcie_pl_wake_oen [1:1] read-only u0_pcie_rx_standby_0 u0_pcie_rx_standby_0 [2:2] read-only stg_syscfg_89 STG SYSCONSAIF SYSCFG 356 0x164 32 0 u0_pcie_test_in_31_0 u0_pcie_test_in_31_0 [31:0] read-write stg_syscfg_90 STG SYSCONSAIF SYSCFG 360 0x168 32 0 u0_pcie_test_in_63_32 u0_pcie_test_in_63_32 [31:0] read-write stg_syscfg_91 STG SYSCONSAIF SYSCFG 364 0x16c 32 0 u0_pcie_test_out_bridge_31_0 u0_pcie_test_out_bridge_31_0 [31:0] read-only stg_syscfg_92 STG SYSCONSAIF SYSCFG 368 0x170 32 0 u0_pcie_test_out_bridge_63_32 u0_pcie_test_out_bridge_63_32 [31:0] read-only stg_syscfg_93 STG SYSCONSAIF SYSCFG 372 0x174 32 0 u0_pcie_test_out_bridge_95_64 u0_pcie_test_out_bridge_95_64 [31:0] read-only stg_syscfg_94 STG SYSCONSAIF SYSCFG 376 0x178 32 0 u0_pcie_test_out_bridge_127_96 u0_pcie_test_out_bridge_127_96 [31:0] read-only stg_syscfg_95 STG SYSCONSAIF SYSCFG 380 0x17c 32 0 u0_pcie_test_out_bridge_159_128 u0_pcie_test_out_bridge_159_128 [31:0] read-only stg_syscfg_96 STG SYSCONSAIF SYSCFG 384 0x180 32 0 u0_pcie_test_out_bridge_191_160 u0_pcie_test_out_bridge_191_160 [31:0] read-only stg_syscfg_97 STG SYSCONSAIF SYSCFG 388 0x184 32 0 u0_pcie_test_out_bridge_223_192 u0_pcie_test_out_bridge_223_192 [31:0] read-only stg_syscfg_98 STG SYSCONSAIF SYSCFG 392 0x188 32 0 u0_pcie_test_out_bridge_255_224 u0_pcie_test_out_bridge_255_224 [31:0] read-only stg_syscfg_99 STG SYSCONSAIF SYSCFG 396 0x18c 32 0 u0_pcie_test_out_bridge_287_256 u0_pcie_test_out_bridge_287_256 [31:0] read-only stg_syscfg_100 STG SYSCONSAIF SYSCFG 400 0x190 32 0 u0_pcie_test_out_bridge_319_288 u0_pcie_test_out_bridge_319_288 [31:0] read-only stg_syscfg_101 STG SYSCONSAIF SYSCFG 404 0x194 32 0 u0_pcie_test_out_bridge_351_320 u0_pcie_test_out_bridge_351_320 [31:0] read-only stg_syscfg_102 STG SYSCONSAIF SYSCFG 408 0x198 32 0 u0_pcie_test_out_bridge_383_352 u0_pcie_test_out_bridge_383_352 [31:0] read-only stg_syscfg_103 STG SYSCONSAIF SYSCFG 412 0x19c 32 0 u0_pcie_test_out_bridge_415_384 u0_pcie_test_out_bridge_415_384 [31:0] read-only stg_syscfg_104 STG SYSCONSAIF SYSCFG 416 0x1a0 32 0 u0_pcie_test_out_bridge_447_416 u0_pcie_test_out_bridge_447_416 [31:0] read-only stg_syscfg_105 STG SYSCONSAIF SYSCFG 420 0x1a4 32 0 u0_pcie_test_out_bridge_479_448 u0_pcie_test_out_bridge_479_448 [31:0] read-only stg_syscfg_106 STG SYSCONSAIF SYSCFG 424 0x1a8 32 0 u0_pcie_test_out_bridge_511_480 u0_pcie_test_out_bridge_511_480 [31:0] read-only stg_syscfg_107 STG SYSCONSAIF SYSCFG 428 0x1ac 32 0 u0_pcie_test_out_pcie_31_0 u0_pcie_test_out_pcie_31_0 [31:0] read-only stg_syscfg_108 STG SYSCONSAIF SYSCFG 432 0x1b0 32 0 u0_pcie_test_out_pcie_63_32 u0_pcie_test_out_pcie_63_32 [31:0] read-only stg_syscfg_109 STG SYSCONSAIF SYSCFG 436 0x1b4 32 0 u0_pcie_test_out_pcie_95_64 u0_pcie_test_out_pcie_95_64 [31:0] read-only stg_syscfg_110 STG SYSCONSAIF SYSCFG 440 0x1b8 32 0 u0_pcie_test_out_pcie_127_96 u0_pcie_test_out_pcie_127_96 [31:0] read-only stg_syscfg_111 STG SYSCONSAIF SYSCFG 444 0x1bc 32 0 u0_pcie_test_out_pcie_159_128 u0_pcie_test_out_pcie_159_128 [31:0] read-only stg_syscfg_112 STG SYSCONSAIF SYSCFG 448 0x1c0 32 0 u0_pcie_test_out_pcie_191_160 u0_pcie_test_out_pcie_191_160 [31:0] read-only stg_syscfg_113 STG SYSCONSAIF SYSCFG 452 0x1c4 32 0 u0_pcie_test_out_pcie_223_192 u0_pcie_test_out_pcie_223_192 [31:0] read-only stg_syscfg_114 STG SYSCONSAIF SYSCFG 456 0x1c8 32 0 u0_pcie_test_out_pcie_255_224 u0_pcie_test_out_pcie_255_224 [31:0] read-only stg_syscfg_115 STG SYSCONSAIF SYSCFG 460 0x1cc 32 0 u0_pcie_test_out_pcie_287_256 u0_pcie_test_out_pcie_287_256 [31:0] read-only stg_syscfg_116 STG SYSCONSAIF SYSCFG 464 0x1d0 32 0 u0_pcie_test_out_pcie_319_288 u0_pcie_test_out_pcie_319_288 [31:0] read-only stg_syscfg_117 STG SYSCONSAIF SYSCFG 468 0x1d4 32 0 u0_pcie_test_out_pcie_351_320 u0_pcie_test_out_pcie_351_320 [31:0] read-only stg_syscfg_118 STG SYSCONSAIF SYSCFG 472 0x1d8 32 0 u0_pcie_test_out_pcie_383_352 u0_pcie_test_out_pcie_383_352 [31:0] read-only stg_syscfg_119 STG SYSCONSAIF SYSCFG 476 0x1dc 32 0 u0_pcie_test_out_pcie_415_384 u0_pcie_test_out_pcie_415_384 [31:0] read-only stg_syscfg_120 STG SYSCONSAIF SYSCFG 480 0x1e0 32 0 u0_pcie_test_out_pcie_447_416 u0_pcie_test_out_pcie_447_416 [31:0] read-only stg_syscfg_121 STG SYSCONSAIF SYSCFG 484 0x1e4 32 0 u0_pcie_test_out_pcie_479_448 u0_pcie_test_out_pcie_479_448 [31:0] read-only stg_syscfg_122 STG SYSCONSAIF SYSCFG 488 0x1e8 32 0 u0_pcie_test_out_pcie_511_480 u0_pcie_test_out_pcie_511_480 [31:0] read-only stg_syscfg_123 STG SYSCONSAIF SYSCFG 492 0x1ec 32 0 u0_pcie_test_sel u0_pcie_test_sel [3:0] read-write u0_pcie_tl_clock_freq u0_pcie_tl_clock_freq [25:4] read-write stg_syscfg_124 STG SYSCONSAIF SYSCFG 496 0x1f0 32 0 u0_pcie_tl_ctrl_hotplug u0_pcie_tl_ctrl_hotplug [15:0] read-only u0_pcie_tl_report_hotplug u0_pcie_tl_report_hotplug [31:16] read-write stg_syscfg_125 STG SYSCONSAIF SYSCFG 500 0x1f4 32 0 u0_pcie_tx_pattern u0_pcie_tx_pattern [1:0] read-write u0_pcie_usb3_bus_width u0_pcie_usb3_bus_width [3:2] read-write u0_pcie_usb3_phy_enable u0_pcie_usb3_phy_enable [4:4] read-write u0_pcie_usb3_rate u0_pcie_usb3_rate [6:5] read-write u0_pcie_usb3_rx_standby u0_pcie_usb3_rx_standby [7:7] read-write u0_pcie_xwdecerr u0_pcie_xwdecerr [8:8] read-only u0_pcie_xwerrclr u0_pcie_xwerrclr [9:9] read-write u0_pcie_xwslverr u0_pcie_xwslverr [10:10] read-only u0_sec_top_sramcfg_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [11:11] read-write u0_sec_top_sramcfg_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [12:12] read-write u0_sec_top_sramcfg_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [14:13] read-write u0_sec_top_sramcfg_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [16:15] read-write u0_sec_top_sramcfg_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [18:17] read-write u0_sec_top_sramcfg_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [20:19] read-write u0_sec_top_sramcfg_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [21:21] read-write u0_sec_top_sramcfg_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [22:22] read-write u0_plda_pcie_align_detect u0_plda_pcie_align_detect [23:23] read-only stg_syscfg_126 STG SYSCONSAIF SYSCFG 504 0x1f8 32 0 u0_pcie_axi4_mst0_aratomop_31_0 u0_pcie_axi4_mst0_aratomop_31_0 [31:0] read-only stg_syscfg_127 STG SYSCONSAIF SYSCFG 508 0x1fc 32 0 u0_pcie_axi4_mst0_aratomop_63_32 u0_pcie_axi4_mst0_aratomop_63_32 [31:0] read-only stg_syscfg_128 STG SYSCONSAIF SYSCFG 512 0x200 32 0 u0_pcie_axi4_mst0_aratomop_95_64 u0_pcie_axi4_mst0_aratomop_95_64 [31:0] read-only stg_syscfg_129 STG SYSCONSAIF SYSCFG 516 0x204 32 0 u0_pcie_axi4_mst0_aratomop_127_96 u0_pcie_axi4_mst0_aratomop_127_96 [31:0] read-only stg_syscfg_130 STG SYSCONSAIF SYSCFG 520 0x208 32 0 u0_pcie_axi4_mst0_aratomop_159_128 u0_pcie_axi4_mst0_aratomop_159_128 [31:0] read-only stg_syscfg_131 STG SYSCONSAIF SYSCFG 524 0x20c 32 0 u0_pcie_axi4_mst0_aratomop_191_160 u0_pcie_axi4_mst0_aratomop_191_160 [31:0] read-only stg_syscfg_132 STG SYSCONSAIF SYSCFG 528 0x210 32 0 u0_pcie_axi4_mst0_aratomop_223_192 u0_pcie_axi4_mst0_aratomop_223_192 [31:0] read-only stg_syscfg_133 STG SYSCONSAIF SYSCFG 532 0x214 32 0 u0_pcie_axi4_mst0_aratomop_255_224 u0_pcie_axi4_mst0_aratomop_255_224 [31:0] read-only stg_syscfg_134 STG SYSCONSAIF SYSCFG 536 0x218 32 0 u0_pcie_axi4_mst0_aratomop_257_256 u0_pcie_axi4_mst0_aratomop_257_256 [1:0] read-only u0_pcie_axi4_mst0_arfunc u0_pcie_axi4_mst0_arfunc [16:2] read-only u0_pcie_axi4_mst0_arregion u0_pcie_axi4_mst0_arregion [20:17] read-only stg_syscfg_135 STG SYSCONSAIF SYSCFG 540 0x21c 32 0 u1_pcie_axi4_mst0_aruser_31_0 u1_pcie_axi4_mst0_aruser_31_0 [31:0] read-only stg_syscfg_136 STG SYSCONSAIF SYSCFG 544 0x220 32 0 u1_pcie_axi4_mst0_aruser_52_32 u1_pcie_axi4_mst0_aruser_52_32 [20:0] read-only stg_syscfg_137 STG SYSCONSAIF SYSCFG 548 0x224 32 0 u1_pcie_axi4_mst0_awfunc u1_pcie_axi4_mst0_awfunc [14:0] read-only u1_pcie_axi4_mst0_awregion u1_pcie_axi4_mst0_awregion [18:15] read-only stg_syscfg_138 STG SYSCONSAIF SYSCFG 552 0x228 32 0 u1_pcie_axi4_mst0_awuser_31_0 u1_pcie_axi4_mst0_awuser_31_0 [31:0] read-only stg_syscfg_139 STG SYSCONSAIF SYSCFG 556 0x22c 32 0 u1_pcie_axi4_mst0_awuser_42_32 u1_pcie_axi4_mst0_awuser_42_32 [10:0] read-only u1_pcie_axi4_mst0_rderr u1_pcie_axi4_mst0_rderr [18:11] read-write stg_syscfg_140 STG SYSCONSAIF SYSCFG 560 0x230 32 0 u1_pcie_axi4_mst0_ruser u1_pcie_axi4_mst0_ruser [31:0] read-write stg_syscfg_141 STG SYSCONSAIF SYSCFG 564 0x234 32 0 u1_pcie_axi4_mst0_wderr u1_pcie_axi4_mst0_wderr [7:0] read-only stg_syscfg_142 STG SYSCONSAIF SYSCFG 568 0x238 32 0 u1_pcie_axi4_slv0_aratomop_31_0 u1_pcie_axi4_slv0_aratomop_31_0 [31:0] read-write stg_syscfg_143 STG SYSCONSAIF SYSCFG 572 0x23c 32 0 u1_pcie_axi4_slv0_aratomop_63_32 u1_pcie_axi4_slv0_aratomop_63_32 [31:0] read-write stg_syscfg_144 STG SYSCONSAIF SYSCFG 576 0x240 32 0 u1_pcie_axi4_slv0_aratomop_95_64 u1_pcie_axi4_slv0_aratomop_95_64 [31:0] read-write stg_syscfg_145 STG SYSCONSAIF SYSCFG 580 0x244 32 0 u1_pcie_axi4_slv0_aratomop_127_96 u1_pcie_axi4_slv0_aratomop_127_96 [31:0] read-write stg_syscfg_146 STG SYSCONSAIF SYSCFG 584 0x248 32 0 u1_pcie_axi4_slv0_aratomop_159_128 u1_pcie_axi4_slv0_aratomop_159_128 [31:0] read-write stg_syscfg_147 STG SYSCONSAIF SYSCFG 588 0x24c 32 0 u1_pcie_axi4_slv0_aratomop_191_160 u1_pcie_axi4_slv0_aratomop_191_160 [31:0] read-write stg_syscfg_148 STG SYSCONSAIF SYSCFG 592 0x250 32 0 u1_pcie_axi4_slv0_aratomop_223_192 u1_pcie_axi4_slv0_aratomop_223_192 [31:0] read-write stg_syscfg_149 STG SYSCONSAIF SYSCFG 596 0x254 32 0 u1_pcie_axi4_slv0_aratomop_255_224 u1_pcie_axi4_slv0_aratomop_255_224 [31:0] read-write stg_syscfg_150 STG SYSCONSAIF SYSCFG 600 0x258 32 0 u1_pcie_axi4_mst0_aratomop_257_256 u1_pcie_axi4_mst0_aratomop_257_256 [1:0] read-write u1_pcie_axi4_slv0_arfunc u1_pcie_axi4_slv0_arfunc [16:2] read-write u1_pcie_axi4_slv0_arregion u1_pcie_axi4_slv0_arregion [20:17] read-write stg_syscfg_151 STG SYSCONSAIF SYSCFG 604 0x25c 32 0 u1_pcie_axi4_slv0_aruser_31_0 u1_pcie_axi4_slv0_aruser_31_0 [31:0] read-write stg_syscfg_152 STG SYSCONSAIF SYSCFG 608 0x260 32 0 u1_pcie_axi4_slv0_aruser_40_32 u1_pcie_axi4_slv0_aruser_40_32 [8:0] read-write u1_pcie_axi4_slv0_awfunc u1_pcie_axi4_slv0_awfunc [23:9] read-write u1_pcie_axi4_slv0_awregion u1_pcie_axi4_slv0_awregion [27:24] read-write stg_syscfg_153 STG SYSCONSAIF SYSCFG 612 0x264 32 0 u1_pcie_axi4_slv0_awuser_31_0 u1_pcie_axi4_slv0_awuser_31_0 [31:0] read-write stg_syscfg_154 STG SYSCONSAIF SYSCFG 616 0x268 32 0 u1_pcie_axi4_slv0_awuser_40_32 u1_pcie_axi4_slv0_awuser_40_32 [8:0] read-write u1_pcie_axi4_slv0_rderr u1_pcie_axi4_slv0_rderr [16:9] read-only stg_syscfg_155 STG SYSCONSAIF SYSCFG 620 0x26c 32 0 u1_pcie_axi4_slv0_ruser u1_pcie_axi4_slv0_ruser [31:0] read-only stg_syscfg_156 STG SYSCONSAIF SYSCFG 624 0x270 32 0 u1_pcie_axi4_slv0_wderr u1_pcie_axi4_slv0_wderr [7:0] read-write u1_pcie_axi4_slvl_arfunc u1_pcie_axi4_slvl_arfunc [22:8] read-write stg_syscfg_157 STG SYSCONSAIF SYSCFG 628 0x274 32 0 u1_pcie_axi4_slvl_awfunc u1_pcie_axi4_slvl_awfunc [14:0] read-write u1_pcie_bus_width_o u1_pcie_bus_width_o [16:15] read-only u1_pcie_bypass_codec u1_pcie_bypass_codec [17:17] read-write u1_pcie_ckref_src u1_pcie_ckref_src [19:18] read-write u1_pcie_clk_sel u1_pcie_clk_sel [21:20] read-write u1_pcie_clkreq u1_pcie_clkreq [22:22] read-write stg_syscfg_158 STG SYSCONSAIF SYSCFG 632 0x278 32 0 u1_plda_pcie_k_phyparam_31_0 u1_plda_pcie_k_phyparam_31_0 [31:0] read-write stg_syscfg_159 STG SYSCONSAIF SYSCFG 636 0x27c 32 0 u1_plda_pcie_k_phyparam_63_32 u1_plda_pcie_k_phyparam_63_32 [31:0] read-write stg_syscfg_160 STG SYSCONSAIF SYSCFG 640 0x280 32 0 u1_plda_pcie_k_phyparam_95_64 u1_plda_pcie_k_phyparam_95_64 [31:0] read-write stg_syscfg_161 STG SYSCONSAIF SYSCFG 644 0x284 32 0 u1_plda_pcie_k_phyparam_127_96 u1_plda_pcie_k_phyparam_127_96 [31:0] read-write stg_syscfg_162 STG SYSCONSAIF SYSCFG 648 0x288 32 0 u1_plda_pcie_k_phyparam_159_128 u1_plda_pcie_k_phyparam_159_128 [31:0] read-write stg_syscfg_163 STG SYSCONSAIF SYSCFG 652 0x28c 32 0 u1_plda_pcie_k_phyparam_191_160 u1_plda_pcie_k_phyparam_191_160 [31:0] read-write stg_syscfg_164 STG SYSCONSAIF SYSCFG 656 0x290 32 0 u1_plda_pcie_k_phyparam_223_192 u1_plda_pcie_k_phyparam_223_192 [31:0] read-write stg_syscfg_165 STG SYSCONSAIF SYSCFG 660 0x294 32 0 u1_plda_pcie_k_phyparam_255_224 u1_plda_pcie_k_phyparam_255_224 [31:0] read-write stg_syscfg_166 STG SYSCONSAIF SYSCFG 664 0x298 32 0 u1_plda_pcie_k_phyparam_287_256 u1_plda_pcie_k_phyparam_287_256 [31:0] read-write stg_syscfg_167 STG SYSCONSAIF SYSCFG 668 0x29c 32 0 u1_plda_pcie_k_phyparam_319_288 u1_plda_pcie_k_phyparam_319_288 [31:0] read-write stg_syscfg_168 STG SYSCONSAIF SYSCFG 672 0x2a0 32 0 u1_plda_pcie_k_phyparam_351_320 u1_plda_pcie_k_phyparam_351_320 [31:0] read-write stg_syscfg_169 STG SYSCONSAIF SYSCFG 676 0x2a4 32 0 u1_plda_pcie_k_phyparam_383_352 u1_plda_pcie_k_phyparam_383_352 [31:0] read-write stg_syscfg_170 STG SYSCONSAIF SYSCFG 680 0x2a8 32 0 u1_plda_pcie_k_phyparam_415_384 u1_plda_pcie_k_phyparam_415_384 [31:0] read-write stg_syscfg_171 STG SYSCONSAIF SYSCFG 684 0x2ac 32 0 u1_plda_pcie_k_phyparam_447_416 u1_plda_pcie_k_phyparam_447_416 [31:0] read-write stg_syscfg_172 STG SYSCONSAIF SYSCFG 688 0x2b0 32 0 u1_plda_pcie_k_phyparam_479_448 u1_plda_pcie_k_phyparam_479_448 [31:0] read-write stg_syscfg_173 STG SYSCONSAIF SYSCFG 692 0x2b4 32 0 u1_plda_pcie_k_phyparam_511_480 u1_plda_pcie_k_phyparam_511_480 [31:0] read-write stg_syscfg_174 STG SYSCONSAIF SYSCFG 696 0x2b8 32 0 u1_plda_pcie_k_phyparam_543_512 u1_plda_pcie_k_phyparam_543_512 [31:0] read-write stg_syscfg_175 STG SYSCONSAIF SYSCFG 700 0x2bc 32 0 u1_plda_pcie_k_phyparam_575_544 u1_plda_pcie_k_phyparam_575_544 [31:0] read-write stg_syscfg_176 STG SYSCONSAIF SYSCFG 704 0x2c0 32 0 u1_plda_pcie_k_phyparam_607_576 u1_plda_pcie_k_phyparam_607_576 [31:0] read-write stg_syscfg_177 STG SYSCONSAIF SYSCFG 708 0x2c4 32 0 u1_plda_pcie_k_phyparam_639_608 u1_plda_pcie_k_phyparam_639_608 [31:0] read-write stg_syscfg_178 STG SYSCONSAIF SYSCFG 712 0x2c8 32 0 u1_plda_pcie_k_phyparam_671_640 u1_plda_pcie_k_phyparam_671_640 [31:0] read-write stg_syscfg_179 STG SYSCONSAIF SYSCFG 716 0x2cc 32 0 u1_plda_pcie_k_phyparam_703_672 u1_plda_pcie_k_phyparam_703_672 [31:0] read-write stg_syscfg_180 STG SYSCONSAIF SYSCFG 720 0x2d0 32 0 u1_plda_pcie_k_phyparam_735_704 u1_plda_pcie_k_phyparam_735_704 [31:0] read-write stg_syscfg_181 STG SYSCONSAIF SYSCFG 724 0x2d4 32 0 u1_plda_pcie_k_phyparam_767_736 u1_plda_pcie_k_phyparam_767_736 [31:0] read-write stg_syscfg_182 STG SYSCONSAIF SYSCFG 728 0x2d8 32 0 u1_plda_pcie_k_phyparam_799_768 u1_plda_pcie_k_phyparam_799_768 [31:0] read-write stg_syscfg_183 STG SYSCONSAIF SYSCFG 732 0x2dc 32 0 u1_plda_pcie_k_phyparam_831_800 u1_plda_pcie_k_phyparam_831_800 [31:0] read-write stg_syscfg_184 STG SYSCONSAIF SYSCFG 736 0x2e0 32 0 u1_pcie_k_phyparam_839_832 u1_pcie_k_phyparam_839_832 [7:0] read-write u1_pcie_k_rp_nep u1_pcie_k_rp_nep [8:8] read-write u1_pcie_l1sub_entack u1_pcie_l1sub_entack [9:9] read-only u1_pcie_l1sub_entreq u1_pcie_l1sub_entreq [10:10] read-write stg_syscfg_185 STG SYSCONSAIF SYSCFG 740 0x2e4 32 0 u1_pcie_local_interrupt_in u1_pcie_local_interrupt_in [31:0] read-write stg_syscfg_186 STG SYSCONSAIF SYSCFG 744 0x2e8 32 0 u1_pcie_mperstn u1_pcie_mperstn [0:0] read-write u1_pcie_pcie_ebuf_mode u1_pcie_pcie_ebuf_mode [1:1] read-write u1_pcie_pcie_phy_test_cfg u1_pcie_pcie_phy_test_cfg [24:2] read-write u1_pcie_pcie_rx_eq_training u1_pcie_pcie_rx_eq_training [25:25] read-write u1_pcie_pcie_rxterm_en u1_pcie_pcie_rxterm_en [26:26] read-write u1_pcie_pcie_tx_oneszeros u1_pcie_pcie_tx_oneszeros [27:27] read-write stg_syscfg_187 STG SYSCONSAIF SYSCFG 748 0x2ec 32 0 u1_pcie_pf0_offset u1_pcie_pf0_offset [19:0] read-write stg_syscfg_188 STG SYSCONSAIF SYSCFG 752 0x2f0 32 0 u1_pcie_pf1_offset u1_pcie_pf1_offset [19:0] read-write stg_syscfg_189 STG SYSCONSAIF SYSCFG 756 0x2f4 32 0 u1_pcie_pf2_offset u1_pcie_pf2_offset [19:0] read-write stg_syscfg_190 STG SYSCONSAIF SYSCFG 760 0x2f8 32 0 u1_pcie_pf3_offset u1_pcie_pf3_offset [19:0] read-write u1_pcie_phy_mode u1_pcie_phy_mode [21:20] read-write u1_pcie_pl_clkrem_allow u1_pcie_pl_clkrem_allow [22:22] read-write u1_pcie_pl_clkreq_oen u1_pcie_pl_clkreq_oen [23:23] read-only u1_pcie_pl_equ_phase u1_pcie_pl_equ_phase [25:24] read-only u1_pcie_pl_ltssm u1_pcie_pl_ltssm [30:26] read-only stg_syscfg_191 STG SYSCONSAIF SYSCFG 764 0x2fc 32 0 u1_pcie_pl_pclk_rate u1_pcie_pl_pclk_rate [4:0] read-only stg_syscfg_192 STG SYSCONSAIF SYSCFG 768 0x300 32 0 u1_pcie_pl_sideband_in_31_0 u1_pcie_pl_sideband_in_31_0 [31:0] read-write stg_syscfg_193 STG SYSCONSAIF SYSCFG 772 0x304 32 0 u1_pcie_pl_sideband_in_63_32 u1_pcie_pl_sideband_in_63_32 [31:0] read-write stg_syscfg_194 STG SYSCONSAIF SYSCFG 776 0x308 32 0 u1_pcie_pl_sideband_out_31_0 u1_pcie_pl_sideband_out_31_0 [31:0] read-write stg_syscfg_195 STG SYSCONSAIF SYSCFG 780 0x30c 32 0 u1_pcie_pl_sideband_out_63_32 u1_pcie_pl_sideband_out_63_32 [31:0] read-write stg_syscfg_196 STG SYSCONSAIF SYSCFG 784 0x310 32 0 u1_pcie_pl_wake_in u1_pcie_pl_wake_in [0:0] read-write u1_pcie_pl_wake_oen u1_pcie_pl_wake_oen [1:1] read-only u1_pcie_rx_standby_o u1_pcie_rx_standby_o [2:2] read-only stg_syscfg_197 STG SYSCONSAIF SYSCFG 788 0x314 32 0 u1_pcie_test_in_31_0 u1_pcie_test_in_31_0 [31:0] read-write stg_syscfg_198 STG SYSCONSAIF SYSCFG 792 0x318 32 0 u1_pcie_test_in_63_32 u1_pcie_test_in_63_32 [31:0] read-write stg_syscfg_199 STG SYSCONSAIF SYSCFG 796 0x31c 32 0 u1_pcie_test_out_bridge_31_0 u1_pcie_test_out_bridge_31_0 [31:0] read-write stg_syscfg_200 STG SYSCONSAIF SYSCFG 800 0x320 32 0 u1_pcie_test_out_bridge_63_32 u1_pcie_test_out_bridge_63_32 [31:0] read-write stg_syscfg_201 STG SYSCONSAIF SYSCFG 804 0x324 32 0 u1_pcie_test_out_bridge_95_64 u1_pcie_test_out_bridge_95_64 [31:0] read-write stg_syscfg_202 STG SYSCONSAIF SYSCFG 808 0x328 32 0 u1_pcie_test_out_bridge_127_96 u1_pcie_test_out_bridge_127_96 [31:0] read-write stg_syscfg_203 STG SYSCONSAIF SYSCFG 812 0x32c 32 0 u1_pcie_test_out_bridge_159_128 u1_pcie_test_out_bridge_159_128 [31:0] read-write stg_syscfg_204 STG SYSCONSAIF SYSCFG 816 0x330 32 0 u1_pcie_test_out_bridge_191_160 u1_pcie_test_out_bridge_191_160 [31:0] read-write stg_syscfg_205 STG SYSCONSAIF SYSCFG 820 0x334 32 0 u1_pcie_test_out_bridge_223_192 u1_pcie_test_out_bridge_223_192 [31:0] read-write stg_syscfg_206 STG SYSCONSAIF SYSCFG 824 0x338 32 0 u1_pcie_test_out_bridge_255_224 u1_pcie_test_out_bridge_255_224 [31:0] read-write stg_syscfg_207 STG SYSCONSAIF SYSCFG 828 0x33c 32 0 u1_pcie_test_out_bridge_287_256 u1_pcie_test_out_bridge_287_256 [31:0] read-write stg_syscfg_208 STG SYSCONSAIF SYSCFG 832 0x340 32 0 u1_pcie_test_out_bridge_319_288 u1_pcie_test_out_bridge_319_288 [31:0] read-write stg_syscfg_209 STG SYSCONSAIF SYSCFG 836 0x344 32 0 u1_pcie_test_out_bridge_351_320 u1_pcie_test_out_bridge_351_320 [31:0] read-write stg_syscfg_210 STG SYSCONSAIF SYSCFG 840 0x348 32 0 u1_pcie_test_out_bridge_383_352 u1_pcie_test_out_bridge_383_352 [31:0] read-write stg_syscfg_211 STG SYSCONSAIF SYSCFG 844 0x34c 32 0 u1_pcie_test_out_bridge_415_384 u1_pcie_test_out_bridge_415_384 [31:0] read-write stg_syscfg_212 STG SYSCONSAIF SYSCFG 848 0x350 32 0 u1_pcie_test_out_bridge_447_416 u1_pcie_test_out_bridge_447_416 [31:0] read-write stg_syscfg_213 STG SYSCONSAIF SYSCFG 852 0x354 32 0 u1_pcie_test_out_bridge_479_448 u1_pcie_test_out_bridge_479_448 [31:0] read-write stg_syscfg_214 STG SYSCONSAIF SYSCFG 856 0x358 32 0 u1_pcie_test_out_bridge_511_480 u1_pcie_test_out_bridge_511_480 [31:0] read-write stg_syscfg_215 STG SYSCONSAIF SYSCFG 860 0x35c 32 0 u1_pcie_test_out_pcie_31_0 u1_pcie_test_out_pcie_31_0 [31:0] read-only stg_syscfg_216 STG SYSCONSAIF SYSCFG 864 0x360 32 0 u1_pcie_test_out_pcie_63_32 u1_pcie_test_out_pcie_63_32 [31:0] read-only stg_syscfg_217 STG SYSCONSAIF SYSCFG 868 0x364 32 0 u1_pcie_test_out_pcie_95_64 u1_pcie_test_out_pcie_95_64 [31:0] read-only stg_syscfg_218 STG SYSCONSAIF SYSCFG 872 0x368 32 0 u1_pcie_test_out_pcie_127_96 u1_pcie_test_out_pcie_127_96 [31:0] read-only stg_syscfg_219 STG SYSCONSAIF SYSCFG 876 0x36c 32 0 u1_pcie_test_out_pcie_159_128 u1_pcie_test_out_pcie_159_128 [31:0] read-only stg_syscfg_220 STG SYSCONSAIF SYSCFG 880 0x370 32 0 u1_pcie_test_out_pcie_191_160 u1_pcie_test_out_pcie_191_160 [31:0] read-only stg_syscfg_221 STG SYSCONSAIF SYSCFG 884 0x374 32 0 u1_pcie_test_out_pcie_223_192 u1_pcie_test_out_pcie_223_192 [31:0] read-only stg_syscfg_222 STG SYSCONSAIF SYSCFG 888 0x378 32 0 u1_pcie_test_out_pcie_255_224 u1_pcie_test_out_pcie_255_224 [31:0] read-only stg_syscfg_223 STG SYSCONSAIF SYSCFG 892 0x37c 32 0 u1_pcie_test_out_pcie_287_256 u1_pcie_test_out_pcie_287_256 [31:0] read-only stg_syscfg_224 STG SYSCONSAIF SYSCFG 896 0x380 32 0 u1_pcie_test_out_pcie_319_288 u1_pcie_test_out_pcie_319_288 [31:0] read-only stg_syscfg_225 STG SYSCONSAIF SYSCFG 900 0x384 32 0 u1_pcie_test_out_pcie_351_320 u1_pcie_test_out_pcie_351_320 [31:0] read-only stg_syscfg_226 STG SYSCONSAIF SYSCFG 904 0x388 32 0 u1_pcie_test_out_pcie_383_352 u1_pcie_test_out_pcie_383_352 [31:0] read-only stg_syscfg_227 STG SYSCONSAIF SYSCFG 908 0x38c 32 0 u1_pcie_test_out_pcie_415_384 u1_pcie_test_out_pcie_415_384 [31:0] read-only stg_syscfg_228 STG SYSCONSAIF SYSCFG 912 0x390 32 0 u1_pcie_test_out_pcie_447_416 u1_pcie_test_out_pcie_447_416 [31:0] read-only stg_syscfg_229 STG SYSCONSAIF SYSCFG 916 0x394 32 0 u1_pcie_test_out_pcie_479_448 u1_pcie_test_out_pcie_479_448 [31:0] read-only stg_syscfg_230 STG SYSCONSAIF SYSCFG 920 0x398 32 0 u1_pcie_test_out_pcie_511_480 u1_pcie_test_out_pcie_511_480 [31:0] read-only stg_syscfg_231 STG SYSCONSAIF SYSCFG 924 0x39c 32 0 u1_pcie_test_sel u1_pcie_test_sel [3:0] read-write u1_pcie_tl_clock_freq u1_pcie_tl_clock_freq [25:4] read-write stg_syscfg_232 STG SYSCONSAIF SYSCFG 928 0x3a0 32 0 u1_pcie_tl_ctrl_hotplug u1_pcie_tl_ctrl_hotplug [15:0] read-only u1_pcie_tl_report_hotplug u1_pcie_tl_report_hotplug [31:16] read-write stg_syscfg_233 STG SYSCONSAIF SYSCFG 932 0x3a4 32 0 u1_pcie_tx_pattern u1_pcie_tx_pattern [1:0] read-write u1_pcie_usb3_bus_width u1_pcie_usb3_bus_width [3:2] read-write u1_pcie_usb3_phy_enable u1_pcie_usb3_phy_enable [4:4] read-write u1_pcie_usb3_rate u1_pcie_usb3_rate [6:5] read-write u1_pcie_usb3_rx_standby u1_pcie_usb3_rx_standby [7:7] read-write u1_pcie_xwdecerr u1_pcie_xwdecerr [8:8] read-only u1_pcie_xwerrclr u1_pcie_xwerrclr [9:9] read-write u1_pcie_xwslverr u1_pcie_xwslverr [10:10] read-only syscon_0 From syscon, peripheral generator 0x10240000 0 0x1000 registers uart3 From snps,dw-apb-uart, peripheral generator 0x12000000 0 0x10000 registers uart3 40 rbr Receive Buffer Register 0x0 32 0 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 32 0 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only dll Divisor Latch Low 0x0 32 0 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write dlh Divisor Latch High 0x4 32 0 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write ier Interrupt Enable Register 0x4 32 0 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write iir Interrupt Identity Register 0x8 32 1 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only fcr FIFO Control Register 0x8 32 0 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xc 32 0 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write mcr Modem Control Register 0x10 32 0 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 32 0 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Line Status Register 0x18 32 0 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1c 32 0 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 32 0 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 32 0 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write srbr0 Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr0 Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr1 Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr1 Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr2 Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr2 Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr3 Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr3 Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr4 Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr4 Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr5 Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr5 Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr6 Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr6 Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr7 Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr7 Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr8 Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr8 Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr9 Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr9 Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr10 Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr10 Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr11 Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr11 Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr12 Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr12 Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr13 Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr13 Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr14 Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr14 Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr15 Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr15 Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only far FIFO Access Register 0x70 32 0 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 32 0 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 32 0 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only usr UART Status Register 0x7c 32 0 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 32 0 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 32 0 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 32 0 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8c 32 0 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 32 0 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 32 0 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 32 0 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9c 32 0 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xa0 32 0 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write htx Halt TX 0xa4 32 0 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xa8 32 0 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xf4 32 0 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 0 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 1146552592 ctr This register contains the peripherals identification code. [31:0] read-only uart4 From snps,dw-apb-uart, peripheral generator 0x12010000 0 0x10000 registers uart4 41 rbr Receive Buffer Register 0x0 32 0 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 32 0 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only dll Divisor Latch Low 0x0 32 0 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write dlh Divisor Latch High 0x4 32 0 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write ier Interrupt Enable Register 0x4 32 0 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write iir Interrupt Identity Register 0x8 32 1 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only fcr FIFO Control Register 0x8 32 0 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xc 32 0 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write mcr Modem Control Register 0x10 32 0 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 32 0 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Line Status Register 0x18 32 0 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1c 32 0 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 32 0 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 32 0 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write srbr0 Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr0 Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr1 Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr1 Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr2 Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr2 Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr3 Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr3 Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr4 Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr4 Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr5 Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr5 Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr6 Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr6 Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr7 Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr7 Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr8 Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr8 Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr9 Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr9 Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr10 Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr10 Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr11 Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr11 Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr12 Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr12 Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr13 Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr13 Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr14 Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr14 Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr15 Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr15 Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only far FIFO Access Register 0x70 32 0 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 32 0 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 32 0 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only usr UART Status Register 0x7c 32 0 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 32 0 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 32 0 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 32 0 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8c 32 0 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 32 0 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 32 0 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 32 0 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9c 32 0 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xa0 32 0 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write htx Halt TX 0xa4 32 0 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xa8 32 0 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xf4 32 0 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 0 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 1146552592 ctr This register contains the peripherals identification code. [31:0] read-only uart5 From snps,dw-apb-uart, peripheral generator 0x12020000 0 0x10000 registers uart5 42 rbr Receive Buffer Register 0x0 32 0 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 32 0 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only dll Divisor Latch Low 0x0 32 0 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write dlh Divisor Latch High 0x4 32 0 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write ier Interrupt Enable Register 0x4 32 0 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write iir Interrupt Identity Register 0x8 32 1 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only fcr FIFO Control Register 0x8 32 0 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xc 32 0 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write mcr Modem Control Register 0x10 32 0 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 32 0 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Line Status Register 0x18 32 0 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1c 32 0 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 32 0 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 32 0 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write srbr0 Shadow Receive Buffer Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr0 Shadow Transmit Holding Register 0: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x30 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr1 Shadow Receive Buffer Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr1 Shadow Transmit Holding Register 1: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x34 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr2 Shadow Receive Buffer Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr2 Shadow Transmit Holding Register 2: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x38 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr3 Shadow Receive Buffer Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr3 Shadow Transmit Holding Register 3: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x3c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr4 Shadow Receive Buffer Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr4 Shadow Transmit Holding Register 4: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x40 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr5 Shadow Receive Buffer Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr5 Shadow Transmit Holding Register 5: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x44 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr6 Shadow Receive Buffer Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr6 Shadow Transmit Holding Register 6: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x48 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr7 Shadow Receive Buffer Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr7 Shadow Transmit Holding Register 7: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x4c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr8 Shadow Receive Buffer Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr8 Shadow Transmit Holding Register 8: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x50 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr9 Shadow Receive Buffer Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr9 Shadow Transmit Holding Register 9: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x54 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr10 Shadow Receive Buffer Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr10 Shadow Transmit Holding Register 10: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x58 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr11 Shadow Receive Buffer Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr11 Shadow Transmit Holding Register 11: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x5c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr12 Shadow Receive Buffer Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr12 Shadow Transmit Holding Register 12: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x60 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr13 Shadow Receive Buffer Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr13 Shadow Transmit Holding Register 13: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x64 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr14 Shadow Receive Buffer Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr14 Shadow Transmit Holding Register 14: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x68 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only srbr15 Shadow Receive Buffer Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 srbr This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr15 Shadow Transmit Holding Register 15: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x6c 32 0 sthr This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only far FIFO Access Register 0x70 32 0 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 32 0 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 32 0 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only usr UART Status Register 0x7c 32 0 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 32 0 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 32 0 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 32 0 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8c 32 0 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 32 0 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 32 0 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 32 0 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9c 32 0 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xa0 32 0 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write htx Halt TX 0xa4 32 0 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xa8 32 0 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xf4 32 0 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 0 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xf8 32 1146552592 ctr This register contains the peripherals identification code. [31:0] read-only i2c3 From snps,designware-i2c, peripheral generator 0x12030000 0 0x10000 registers i2c3 43 con DesignWare I2C CON 0x0 32 0 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write tar DesignWare I2C TAR 0x4 32 0 address_7bit Target address, 7-bit mode [6:0] read-write address_10bit Target address, 10-bit mode [9:0] read-write mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write sar DesignWare I2C SAR 0x8 32 0 address_7bit Slave address, 7-bit mode [6:0] read-write address_10bit Slave address, 10-bit mode [9:0] read-write data_cmd DesignWare I2C Data Command 0x10 32 0 dat Data Command Data Byte [7:0] read-write read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 32 0 ss_scl_hcnt ss_scl_hcnt [31:0] read-write ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 32 0 ss_scl_lcnt ss_scl_lcnt [31:0] read-write fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1c 32 0 fs_scl_hcnt fs_scl_hcnt [31:0] read-write fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 32 0 fs_scl_lcnt fs_scl_lcnt [31:0] read-write hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 32 0 hs_scl_hcnt hs_scl_hcnt [31:0] read-write hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 32 0 hs_scl_lcnt hs_scl_lcnt [31:0] read-write intr_stat DesignWare I2C Interrupt Status 0x2c 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 32 0 rx_tl rx_tl [31:0] read-write tx_tl DesignWare I2C TX TL 0x3c 32 0 tx_tl tx_tl [31:0] read-write clr_intr DesignWare I2C Clear Interrrupt 0x40 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write clr_rx_under DesignWare I2C Clear RX Underrun 0x44 32 0 clr_rx_under clr_rx_under [31:0] read-write clr_rx_over DesignWare I2C Clear RX Overrun 0x48 32 0 clr_rx_over clr_rx_over [31:0] read-write clr_tx_over DesignWare I2C Clear TX Overrun 0x4c 32 0 clr_tx_over clr_tx_over [31:0] read-write clr_rd_req DesignWare I2C Clear Read Request 0x50 32 0 clr_rd_req clr_rd_req [31:0] read-write clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 32 0 clr_tx_abrt clr_tx_abrt [31:0] read-write clr_rx_done DesignWare I2C Clear RX Done 0x58 32 0 clr_rx_done clr_rx_done [31:0] read-write clr_activity DesignWare I2C Clear Activity 0x5c 32 0 clr_activity clr_activity [31:0] read-write clr_stop_det DesignWare I2C Clear Stop DET 0x60 32 0 clr_stop_det clr_stop_det [31:0] read-write clr_start_det DesignWare I2C Clear Start DET 0x64 32 0 clr_start_det clr_start_det [31:0] read-write clr_gen_call DesignWare I2C Clear General Call 0x68 32 0 clr_gen_call clr_gen_call [31:0] read-write enable DesignWare I2C Enable 0x6c 32 0 abort abort [1:1] read-write status DesignWare I2C Status 0x70 32 0 activity activity [0:0] read-only tfe tfe [2:2] read-only rfne rfne [3:3] read-only master_activity master_activity [5:5] read-only slave_activity slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 32 0 txflr txflr [31:0] read-write rxflr DesignWare I2C RX Failure 0x78 32 0 rxflr rxflr [31:0] read-write sda_hold DesignWare I2C SDA Hold 0x7c 32 0 sda_hold sda_hold [31:0] read-write tx_abrt_source DesignWare I2C TX Abort Source 0x80 32 0 b7_addr_noack b7_addr_noack [0:0] read-only b10_addr1_noack b10_addr1_noack [1:1] read-only b10_addr2_noack b10_addr2_noack [2:2] read-only txdata_noack txdata_noack [3:3] read-only gcall_noack gcall_noack [4:4] read-only gcall_read gcall_read [5:5] read-only sbyte_ackdet sbyte_ackdet [7:7] read-only sbyte_norstrt sbyte_norstrt [9:9] read-only b10_rd_norstrt b10_rd_norstrt [10:10] read-only master_dis master_dis [11:11] read-only arb_lost arb_lost [12:12] read-only slave_flush_txfifo slave_flush_txfifo [13:13] read-only slave_arblost slave_arblost [14:14] read-only slave_rd_intx slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9c 32 0 activity activity [0:0] read-write tfe tfe [2:2] read-write rfne rfne [3:3] read-write master_activity master_activity [5:5] read-write slave_activity slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xa8 32 0 clr_restart_det clr_restart_det [31:0] read-write comp_param_1 DesignWare I2C Compatibility Parameter 1 0xf4 32 0 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only comp_version DesignWare I2C Compatibility Version 0xf8 32 0 comp_version comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xfc 32 0 comp_type comp_type [31:0] read-only i2c4 From snps,designware-i2c, peripheral generator 0x12040000 0 0x10000 registers i2c4 44 con DesignWare I2C CON 0x0 32 0 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write tar DesignWare I2C TAR 0x4 32 0 address_7bit Target address, 7-bit mode [6:0] read-write address_10bit Target address, 10-bit mode [9:0] read-write mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write sar DesignWare I2C SAR 0x8 32 0 address_7bit Slave address, 7-bit mode [6:0] read-write address_10bit Slave address, 10-bit mode [9:0] read-write data_cmd DesignWare I2C Data Command 0x10 32 0 dat Data Command Data Byte [7:0] read-write read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 32 0 ss_scl_hcnt ss_scl_hcnt [31:0] read-write ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 32 0 ss_scl_lcnt ss_scl_lcnt [31:0] read-write fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1c 32 0 fs_scl_hcnt fs_scl_hcnt [31:0] read-write fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 32 0 fs_scl_lcnt fs_scl_lcnt [31:0] read-write hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 32 0 hs_scl_hcnt hs_scl_hcnt [31:0] read-write hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 32 0 hs_scl_lcnt hs_scl_lcnt [31:0] read-write intr_stat DesignWare I2C Interrupt Status 0x2c 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 32 0 rx_tl rx_tl [31:0] read-write tx_tl DesignWare I2C TX TL 0x3c 32 0 tx_tl tx_tl [31:0] read-write clr_intr DesignWare I2C Clear Interrrupt 0x40 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write clr_rx_under DesignWare I2C Clear RX Underrun 0x44 32 0 clr_rx_under clr_rx_under [31:0] read-write clr_rx_over DesignWare I2C Clear RX Overrun 0x48 32 0 clr_rx_over clr_rx_over [31:0] read-write clr_tx_over DesignWare I2C Clear TX Overrun 0x4c 32 0 clr_tx_over clr_tx_over [31:0] read-write clr_rd_req DesignWare I2C Clear Read Request 0x50 32 0 clr_rd_req clr_rd_req [31:0] read-write clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 32 0 clr_tx_abrt clr_tx_abrt [31:0] read-write clr_rx_done DesignWare I2C Clear RX Done 0x58 32 0 clr_rx_done clr_rx_done [31:0] read-write clr_activity DesignWare I2C Clear Activity 0x5c 32 0 clr_activity clr_activity [31:0] read-write clr_stop_det DesignWare I2C Clear Stop DET 0x60 32 0 clr_stop_det clr_stop_det [31:0] read-write clr_start_det DesignWare I2C Clear Start DET 0x64 32 0 clr_start_det clr_start_det [31:0] read-write clr_gen_call DesignWare I2C Clear General Call 0x68 32 0 clr_gen_call clr_gen_call [31:0] read-write enable DesignWare I2C Enable 0x6c 32 0 abort abort [1:1] read-write status DesignWare I2C Status 0x70 32 0 activity activity [0:0] read-only tfe tfe [2:2] read-only rfne rfne [3:3] read-only master_activity master_activity [5:5] read-only slave_activity slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 32 0 txflr txflr [31:0] read-write rxflr DesignWare I2C RX Failure 0x78 32 0 rxflr rxflr [31:0] read-write sda_hold DesignWare I2C SDA Hold 0x7c 32 0 sda_hold sda_hold [31:0] read-write tx_abrt_source DesignWare I2C TX Abort Source 0x80 32 0 b7_addr_noack b7_addr_noack [0:0] read-only b10_addr1_noack b10_addr1_noack [1:1] read-only b10_addr2_noack b10_addr2_noack [2:2] read-only txdata_noack txdata_noack [3:3] read-only gcall_noack gcall_noack [4:4] read-only gcall_read gcall_read [5:5] read-only sbyte_ackdet sbyte_ackdet [7:7] read-only sbyte_norstrt sbyte_norstrt [9:9] read-only b10_rd_norstrt b10_rd_norstrt [10:10] read-only master_dis master_dis [11:11] read-only arb_lost arb_lost [12:12] read-only slave_flush_txfifo slave_flush_txfifo [13:13] read-only slave_arblost slave_arblost [14:14] read-only slave_rd_intx slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9c 32 0 activity activity [0:0] read-write tfe tfe [2:2] read-write rfne rfne [3:3] read-write master_activity master_activity [5:5] read-write slave_activity slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xa8 32 0 clr_restart_det clr_restart_det [31:0] read-write comp_param_1 DesignWare I2C Compatibility Parameter 1 0xf4 32 0 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only comp_version DesignWare I2C Compatibility Version 0xf8 32 0 comp_version comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xfc 32 0 comp_type comp_type [31:0] read-only i2c5 From snps,designware-i2c, peripheral generator 0x12050000 0 0x10000 registers i2c5 45 con DesignWare I2C CON 0x0 32 0 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write tar DesignWare I2C TAR 0x4 32 0 address_7bit Target address, 7-bit mode [6:0] read-write address_10bit Target address, 10-bit mode [9:0] read-write mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write sar DesignWare I2C SAR 0x8 32 0 address_7bit Slave address, 7-bit mode [6:0] read-write address_10bit Slave address, 10-bit mode [9:0] read-write data_cmd DesignWare I2C Data Command 0x10 32 0 dat Data Command Data Byte [7:0] read-write read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 32 0 ss_scl_hcnt ss_scl_hcnt [31:0] read-write ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 32 0 ss_scl_lcnt ss_scl_lcnt [31:0] read-write fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1c 32 0 fs_scl_hcnt fs_scl_hcnt [31:0] read-write fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 32 0 fs_scl_lcnt fs_scl_lcnt [31:0] read-write hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 32 0 hs_scl_hcnt hs_scl_hcnt [31:0] read-write hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 32 0 hs_scl_lcnt hs_scl_lcnt [31:0] read-write intr_stat DesignWare I2C Interrupt Status 0x2c 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 32 0 rx_tl rx_tl [31:0] read-write tx_tl DesignWare I2C TX TL 0x3c 32 0 tx_tl tx_tl [31:0] read-write clr_intr DesignWare I2C Clear Interrrupt 0x40 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write clr_rx_under DesignWare I2C Clear RX Underrun 0x44 32 0 clr_rx_under clr_rx_under [31:0] read-write clr_rx_over DesignWare I2C Clear RX Overrun 0x48 32 0 clr_rx_over clr_rx_over [31:0] read-write clr_tx_over DesignWare I2C Clear TX Overrun 0x4c 32 0 clr_tx_over clr_tx_over [31:0] read-write clr_rd_req DesignWare I2C Clear Read Request 0x50 32 0 clr_rd_req clr_rd_req [31:0] read-write clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 32 0 clr_tx_abrt clr_tx_abrt [31:0] read-write clr_rx_done DesignWare I2C Clear RX Done 0x58 32 0 clr_rx_done clr_rx_done [31:0] read-write clr_activity DesignWare I2C Clear Activity 0x5c 32 0 clr_activity clr_activity [31:0] read-write clr_stop_det DesignWare I2C Clear Stop DET 0x60 32 0 clr_stop_det clr_stop_det [31:0] read-write clr_start_det DesignWare I2C Clear Start DET 0x64 32 0 clr_start_det clr_start_det [31:0] read-write clr_gen_call DesignWare I2C Clear General Call 0x68 32 0 clr_gen_call clr_gen_call [31:0] read-write enable DesignWare I2C Enable 0x6c 32 0 abort abort [1:1] read-write status DesignWare I2C Status 0x70 32 0 activity activity [0:0] read-only tfe tfe [2:2] read-only rfne rfne [3:3] read-only master_activity master_activity [5:5] read-only slave_activity slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 32 0 txflr txflr [31:0] read-write rxflr DesignWare I2C RX Failure 0x78 32 0 rxflr rxflr [31:0] read-write sda_hold DesignWare I2C SDA Hold 0x7c 32 0 sda_hold sda_hold [31:0] read-write tx_abrt_source DesignWare I2C TX Abort Source 0x80 32 0 b7_addr_noack b7_addr_noack [0:0] read-only b10_addr1_noack b10_addr1_noack [1:1] read-only b10_addr2_noack b10_addr2_noack [2:2] read-only txdata_noack txdata_noack [3:3] read-only gcall_noack gcall_noack [4:4] read-only gcall_read gcall_read [5:5] read-only sbyte_ackdet sbyte_ackdet [7:7] read-only sbyte_norstrt sbyte_norstrt [9:9] read-only b10_rd_norstrt b10_rd_norstrt [10:10] read-only master_dis master_dis [11:11] read-only arb_lost arb_lost [12:12] read-only slave_flush_txfifo slave_flush_txfifo [13:13] read-only slave_arblost slave_arblost [14:14] read-only slave_rd_intx slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9c 32 0 activity activity [0:0] read-write tfe tfe [2:2] read-write rfne rfne [3:3] read-write master_activity master_activity [5:5] read-write slave_activity slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xa8 32 0 clr_restart_det clr_restart_det [31:0] read-write comp_param_1 DesignWare I2C Compatibility Parameter 1 0xf4 32 0 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only comp_version DesignWare I2C Compatibility Version 0xf8 32 0 comp_version comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xfc 32 0 comp_type comp_type [31:0] read-only x_powers_axp15060_0 From x-powers,axp15060, peripheral generator 0x36 0 0x36 registers i2c6 From snps,designware-i2c, peripheral generator 0x12060000 0 0x10000 registers i2c6 46 con DesignWare I2C CON 0x0 32 0 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write tar DesignWare I2C TAR 0x4 32 0 address_7bit Target address, 7-bit mode [6:0] read-write address_10bit Target address, 10-bit mode [9:0] read-write mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write sar DesignWare I2C SAR 0x8 32 0 address_7bit Slave address, 7-bit mode [6:0] read-write address_10bit Slave address, 10-bit mode [9:0] read-write data_cmd DesignWare I2C Data Command 0x10 32 0 dat Data Command Data Byte [7:0] read-write read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 32 0 ss_scl_hcnt ss_scl_hcnt [31:0] read-write ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 32 0 ss_scl_lcnt ss_scl_lcnt [31:0] read-write fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1c 32 0 fs_scl_hcnt fs_scl_hcnt [31:0] read-write fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 32 0 fs_scl_lcnt fs_scl_lcnt [31:0] read-write hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 32 0 hs_scl_hcnt hs_scl_hcnt [31:0] read-write hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 32 0 hs_scl_lcnt hs_scl_lcnt [31:0] read-write intr_stat DesignWare I2C Interrupt Status 0x2c 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 32 0 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 32 0 rx_tl rx_tl [31:0] read-write tx_tl DesignWare I2C TX TL 0x3c 32 0 tx_tl tx_tl [31:0] read-write clr_intr DesignWare I2C Clear Interrrupt 0x40 32 0 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write clr_rx_under DesignWare I2C Clear RX Underrun 0x44 32 0 clr_rx_under clr_rx_under [31:0] read-write clr_rx_over DesignWare I2C Clear RX Overrun 0x48 32 0 clr_rx_over clr_rx_over [31:0] read-write clr_tx_over DesignWare I2C Clear TX Overrun 0x4c 32 0 clr_tx_over clr_tx_over [31:0] read-write clr_rd_req DesignWare I2C Clear Read Request 0x50 32 0 clr_rd_req clr_rd_req [31:0] read-write clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 32 0 clr_tx_abrt clr_tx_abrt [31:0] read-write clr_rx_done DesignWare I2C Clear RX Done 0x58 32 0 clr_rx_done clr_rx_done [31:0] read-write clr_activity DesignWare I2C Clear Activity 0x5c 32 0 clr_activity clr_activity [31:0] read-write clr_stop_det DesignWare I2C Clear Stop DET 0x60 32 0 clr_stop_det clr_stop_det [31:0] read-write clr_start_det DesignWare I2C Clear Start DET 0x64 32 0 clr_start_det clr_start_det [31:0] read-write clr_gen_call DesignWare I2C Clear General Call 0x68 32 0 clr_gen_call clr_gen_call [31:0] read-write enable DesignWare I2C Enable 0x6c 32 0 abort abort [1:1] read-write status DesignWare I2C Status 0x70 32 0 activity activity [0:0] read-only tfe tfe [2:2] read-only rfne rfne [3:3] read-only master_activity master_activity [5:5] read-only slave_activity slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 32 0 txflr txflr [31:0] read-write rxflr DesignWare I2C RX Failure 0x78 32 0 rxflr rxflr [31:0] read-write sda_hold DesignWare I2C SDA Hold 0x7c 32 0 sda_hold sda_hold [31:0] read-write tx_abrt_source DesignWare I2C TX Abort Source 0x80 32 0 b7_addr_noack b7_addr_noack [0:0] read-only b10_addr1_noack b10_addr1_noack [1:1] read-only b10_addr2_noack b10_addr2_noack [2:2] read-only txdata_noack txdata_noack [3:3] read-only gcall_noack gcall_noack [4:4] read-only gcall_read gcall_read [5:5] read-only sbyte_ackdet sbyte_ackdet [7:7] read-only sbyte_norstrt sbyte_norstrt [9:9] read-only b10_rd_norstrt b10_rd_norstrt [10:10] read-only master_dis master_dis [11:11] read-only arb_lost arb_lost [12:12] read-only slave_flush_txfifo slave_flush_txfifo [13:13] read-only slave_arblost slave_arblost [14:14] read-only slave_rd_intx slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9c 32 0 activity activity [0:0] read-write tfe tfe [2:2] read-write rfne rfne [3:3] read-write master_activity master_activity [5:5] read-write slave_activity slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xa8 32 0 clr_restart_det clr_restart_det [31:0] read-write comp_param_1 DesignWare I2C Compatibility Parameter 1 0xf4 32 0 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only comp_version DesignWare I2C Compatibility Version 0xf8 32 0 comp_version comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xfc 32 0 comp_type comp_type [31:0] read-only spi3 From arm,pl022, peripheral generator 0x12070000 0 0x10000 registers spi3 47 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 16 0 dss Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data [3:0] read-write frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [6:6] read-write scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 16 0 lbm Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write sse Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] read-write ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 16 0 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xc 16 0 tfe Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only tnf Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only rne Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only rff Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only bsy PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 16 0 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 16 0 rorim Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write rtim Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write rxim Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write txim Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked [2:2] read-write ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 16 0 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1c 16 0 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 16 0 roric Clears the SSPRORINTR interrupt [0:0] read-write rtic Clears the SSPRTINTR interrupt [1:1] read-write ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 16 0 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe0 16 0 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe4 16 0 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe8 16 0 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfec 16 0 configuration These bits read back as 0x80 [7:0] read-only ssp_pcell_id0 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff0 16 0 ssp_pcell_id0 The bits are read as 0xD [7:0] read-only ssp_pcell_id1 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff4 16 0 ssp_pcell_id1 The bits are read as 0xF0 [7:0] read-only ssp_pcell_id2 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff8 16 0 ssp_pcell_id2 The bits are read as 0x5 [7:0] read-only ssp_pcell_id3 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xffc 16 0 ssp_pcell_id3 The bits are read as 0xB1 [7:0] read-only arm_primecell_3 From arm,primecell, peripheral generator 0x12070000 0 0x10000 registers spi4 From arm,pl022, peripheral generator 0x12080000 0 0x10000 registers spi4 48 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 16 0 dss Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data [3:0] read-write frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [6:6] read-write scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 16 0 lbm Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write sse Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] read-write ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 16 0 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xc 16 0 tfe Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only tnf Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only rne Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only rff Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only bsy PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 16 0 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 16 0 rorim Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write rtim Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write rxim Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write txim Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked [2:2] read-write ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 16 0 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1c 16 0 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 16 0 roric Clears the SSPRORINTR interrupt [0:0] read-write rtic Clears the SSPRTINTR interrupt [1:1] read-write ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 16 0 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe0 16 0 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe4 16 0 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe8 16 0 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfec 16 0 configuration These bits read back as 0x80 [7:0] read-only ssp_pcell_id0 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff0 16 0 ssp_pcell_id0 The bits are read as 0xD [7:0] read-only ssp_pcell_id1 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff4 16 0 ssp_pcell_id1 The bits are read as 0xF0 [7:0] read-only ssp_pcell_id2 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff8 16 0 ssp_pcell_id2 The bits are read as 0x5 [7:0] read-only ssp_pcell_id3 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xffc 16 0 ssp_pcell_id3 The bits are read as 0xB1 [7:0] read-only arm_primecell_4 From arm,primecell, peripheral generator 0x12080000 0 0x10000 registers spi5 From arm,pl022, peripheral generator 0x12090000 0 0x10000 registers spi5 49 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 16 0 dss Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data [3:0] read-write frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [6:6] read-write scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 16 0 lbm Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write sse Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] read-write ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 16 0 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xc 16 0 tfe Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only tnf Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only rne Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only rff Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only bsy PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 16 0 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 16 0 rorim Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write rtim Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write rxim Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write txim Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked [2:2] read-write ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 16 0 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1c 16 0 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 16 0 roric Clears the SSPRORINTR interrupt [0:0] read-write rtic Clears the SSPRTINTR interrupt [1:1] read-write ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 16 0 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe0 16 0 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe4 16 0 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe8 16 0 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfec 16 0 configuration These bits read back as 0x80 [7:0] read-only ssp_pcell_id0 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff0 16 0 ssp_pcell_id0 The bits are read as 0xD [7:0] read-only ssp_pcell_id1 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff4 16 0 ssp_pcell_id1 The bits are read as 0xF0 [7:0] read-only ssp_pcell_id2 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff8 16 0 ssp_pcell_id2 The bits are read as 0x5 [7:0] read-only ssp_pcell_id3 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xffc 16 0 ssp_pcell_id3 The bits are read as 0xB1 [7:0] read-only arm_primecell_5 From arm,primecell, peripheral generator 0x12090000 0 0x10000 registers spi6 From arm,pl022, peripheral generator 0x120A0000 0 0x10000 registers spi6 50 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 16 0 dss Data Size Select - 0000, 0001, 0010: Reserved, 0011: 4-bit data, 0100: 5-bit data, 6-bit data, 0110: 7-bit data, 0111: 8-bit data, 1000: 9-bit data, 1001: 10-bit data, 1010: 11-bit data, 1011: 12-bit data, 1100: 13-bit data, 1101: 14-bit data, 1110: 15-bit data, 1111: 16-bit data [3:0] read-write frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [6:6] read-write scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 16 0 lbm Loop back mode - 0: Normal serial port operation enabled, 1: Output of transmit serial shifter is connected to input of receive serial shifter internally [0:0] read-write sse Synchronous serial port enable - 0: SSP operation disabled, 1: SSP operation enabled [1:1] read-write ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0 - 0: Device configured as master (default), 1: Device configured as slave [2:2] read-write sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 16 0 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xc 16 0 tfe Transmit FIFO empty, RO - 0: Transmit FIFO is not empty, 1: Transmit FIFO is empty. [0:0] read-only tnf Transmit FIFO not full, RO - 0: Transmit FIFO is full, 1: Transmit FIFO is not full. [1:1] read-only rne Receive FIFO not empty, RO - 0: Receive FIFO is empty, 1: Receive FIFO is not empty. [2:2] read-only rff Receive FIFO full, RO - 0: Receive FIFO is not full, 1: Receive FIFO is full. [3:3] read-only bsy PrimeCell SSP busy flag, RO - 0: SSP is idle, 1: SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 16 0 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 16 0 rorim Receive overrun interrupt mask - 0: Receive FIFO written to while full condition interrupt is masked, 1: Receive FIFO written to while full condition interrupt is not masked [0:0] read-write rtim Receive timeout interrupt mask - 0: Receive FIFO not empty and no read prior to timeout period interrupt is masked, 1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked [1:1] read-write rxim Receive FIFO interrupt mask - 0: Receive FIFO half full or less condition interrupt is masked, 1: Receive FIFO half full or less condition interrupt is not masked [2:2] read-write txim Transmit FIFO interrupt mask - 0: Transmit FIFO half empty or less condition interrupt is masked, 1: Transmit FIFO half empty or less condition interrupt is not masked [2:2] read-write ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 16 0 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1c 16 0 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 16 0 roric Clears the SSPRORINTR interrupt [0:0] read-write rtic Clears the SSPRTINTR interrupt [1:1] read-write ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 16 0 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe0 16 0 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe4 16 0 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfe8 16 0 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xfec 16 0 configuration These bits read back as 0x80 [7:0] read-only ssp_pcell_id0 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff0 16 0 ssp_pcell_id0 The bits are read as 0xD [7:0] read-only ssp_pcell_id1 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff4 16 0 ssp_pcell_id1 The bits are read as 0xF0 [7:0] read-only ssp_pcell_id2 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xff8 16 0 ssp_pcell_id2 The bits are read as 0x5 [7:0] read-only ssp_pcell_id3 The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xffc 16 0 ssp_pcell_id3 The bits are read as 0xB1 [7:0] read-only arm_primecell_6 From arm,primecell, peripheral generator 0x120A0000 0 0x10000 registers starfive_jh7110_temp_0 From starfive,jh7110-temp, peripheral generator 0x120E0000 0 0x10000 registers starfive_jh7110_qspi_0 From starfive,jh7110-qspi, peripheral generator 0x13010000 0 0x10000 registers qspi From cdns,qspi-nor, peripheral generator 0x13010000 0 0x10000 registers qspi 20 config Cadence QSPI Configuration 0x0 32 0 enable Enable the QSPI controller [0:0] read-write enb_dir_acc_ctrl Enable direct access controller [7:7] read-write decode Enable the QSPI decoder [9:9] read-write chipselect Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111 [13:10] read-write dma Enable Direct Memory Access [15:15] read-write baud Set the QSPI BAUD rate divisor [22:19] read-write dtr_proto Enable DTR Protocol [24:24] read-write dual_opcode Enable Dual Opcode Mode [30:30] read-write idle Set Idle [31:31] read-write rd_instr Cadence QSPI Read Instruction 0x4 32 0 opcode Instruction Opcode [7:0] read-write type_instr Type of Instruction [9:8] read-write type_addr Type of Address [13:12] read-write type_data type_data [17:16] read-write mode_en Mode [20:20] read-write dummy Send dummy signal to stall the device [28:24] read-write wr_instr Cadence QSPI Write Instruction 0x8 32 0 opcode Instruction Opcode [7:0] read-write type_addr Type of Address [13:12] read-write type_data type_data [17:16] read-write delay Cadence QSPI Delay 0xc 32 0 tslch TSLCH Delay Value [7:0] read-write tchsh TCHSH Delay Value [15:8] read-write tsd2d TSD2D Delay Value [23:16] read-write tshsl TSHSL Delay Value [31:24] read-write read_capture Cadence QSPI Read Capture 0x10 32 0 bypass Bypass the Read Capture [0:0] read-write delay Read Capture Delay Value [4:1] read-write size Cadence QSPI Size Configuration 0x14 32 0 address Address Size in Bytes [3:0] read-write page Page Size in Bytes [15:4] read-write block Block Size in Bytes [21:16] read-write sram_partition Cadence QSPI SRAM Partition Size 0x18 32 0 size Partition size in bytes [31:0] read-write indirect_trigger Cadence QSPI Indirect Trigger Address 0x1c 32 0 address address [31:0] read-write dma Cadence QSPI Direct Memory Access 0x20 32 0 single single [7:0] read-write burst burst [15:8] read-write remap Cadence QSPI Remap Address 0x24 32 0 address address [31:0] read-write mode_bit Cadence QSPI Mode Bit(s) 0x28 32 0 mode mode [31:0] read-write sdram_level Cadence QSPI SDRAM Level 0x2c 32 0 rd SDRAM Read Level [15:0] read-only wr SDRAM Write Level [31:16] read-only wr_completion_ctrl Cadence QSPI Write Completion Control 0x38 32 0 disable_auto_poll SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register. [14:14] read-write irq_status Cadence QSPI IRQ Status 0x40 32 131071 mode_err Mode error interrupt [0:0] read-write underflow Buffer underflow interrupt [1:1] read-write ind_comp Indirect computation interrupt [2:2] read-write ind_rd_reject Indirect read rejection interrupt [3:3] read-write wr_protected_err Write protected error interrupt [4:4] read-write illegal_ahb_err Illegal AHB clock error interrupt [5:5] read-write watermark Watermark interrupt [6:6] read-write ind_sram_full Indirect SRAM full interrupt [12:12] read-write irq_mask Cadence QSPI IRQ Mask 0x44 32 70 mode_err Mode error interrupt [0:0] read-write underflow Buffer underflow interrupt [1:1] read-write ind_comp Indirect computation interrupt [2:2] read-write ind_rd_reject Indirect read rejection interrupt [3:3] read-write wr_protected_err Write protected error interrupt [4:4] read-write illegal_ahb_err Illegal AHB clock error interrupt [5:5] read-write watermark Watermark interrupt [6:6] read-write ind_sram_full Indirect SRAM full interrupt [12:12] read-write indirect_rd Cadence QSPI Indirect Read 0x60 32 0 start Start indirect read [0:0] read-write cancel Cancel indirect read [1:1] read-write done Indirect read done [5:5] read-write indirect_rd_watermark Cadence QSPI Indirect Read Watermark 0x64 32 0 watermark watermark [31:0] read-write indirect_rd_start_addr Cadence QSPI Indirect Read Start Address 0x68 32 0 address address [31:0] read-write indirect_rd_bytes Cadence QSPI Indirect Read Bytes 0x6c 32 0 bytes bytes [31:0] read-write indirect_wr Cadence QSPI Indirect Write 0x70 32 0 start Start indirect write [0:0] read-write cancel Cancel indirect write [1:1] read-write done Indirect write done [5:5] read-write indirect_wr_watermark Cadence QSPI Indirect Write Watermark 0x74 32 0 watermark watermark [31:0] read-write indirect_wr_start_addr Cadence QSPI Indirect Write Start Address 0x78 32 0 address address [31:0] read-write indirect_wr_bytes Cadence QSPI Indirect Write Bytes 0x7c 32 0 bytes bytes [31:0] read-write cmd_ctrl Cadence QSPI Command Control 0x90 32 0 execute Execute-in-Place (XIP) [0:0] read-write in_progress Command in progress [1:1] read-write dummy Dummy command [11:7] read-write wr_bytes Write bytes [14:12] read-write wr_en Write enable [15:15] read-write add_bytes Add command bytes [17:16] read-write addr_en Address enable [19:19] read-write rd_bytes Read bytes [22:20] read-write rd_en Read enable [23:23] read-write opcode Command opcode [31:24] read-write cmd_address Cadence QSPI Command Address 0x94 32 0 address address [31:0] read-write cmd_read_at_lower Cadence QSPI Command Read at Lower 0xa0 32 0 read_at_lower read_at_lower [31:0] read-write cmd_read_at_upper Cadence QSPI Command Read at Upper 0xa4 32 0 read_at_upper read_at_upper [31:0] read-write cmd_write_at_lower Cadence QSPI Command Write at Lower 0xa8 32 0 write_at_lower write_at_lower [31:0] read-write cmd_write_at_upper Cadence QSPI Command Write at Upper 0xac 32 0 write_at_upper write_at_upper [31:0] read-write polling_status Cadence QSPI Polling Status 0xb0 32 0 status status [15:0] read-write dummy dummy [20:16] read-write ext_lower Cadence QSPI Extension Lower 0xe0 32 0 stig stig [15:0] read-write write write [23:16] read-write read read [31:24] read-write jedec_spi_nor_0 From jedec,spi-nor, peripheral generator 0x0 0 0x0 registers starfive_jh7110_xspi_0 From starfive,jh7110-xspi, peripheral generator 0x21000000 0 0x400000 registers cdns_xspi_nor_0 From cdns,xspi-nor, peripheral generator 0x21000000 0 0x400000 registers jedec_spi_nor_1 From jedec,spi-nor, peripheral generator 0x0 0 0x0 registers syscrg From starfive,jh7110-syscrg, peripheral generator 0x13020000 0 0x10000 registers clk_cpu_root Clock CPU Root 0x0 32 0 clk_mux_sel Clock multiplexing selector: clk_osc, clk_pll0 [29:24] read-write clk_cpu_core Clock CPU Core 0x4 32 0 clk_divcfg Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1 [23:0] read-write clk_cpu_bus Clock CPU Bus 0x8 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_gpu_root Clock GPU Root 0xc 32 0 clk_mux_sel Clock multiplexing selector: clk_pll2, clk_pll1 [29:24] read-write clk_peripheral_root Clock Peripheral Root 0x10 32 0 clk_mux_sel Clock multiplexing selector: clk_pll0, clk_pll2 [29:24] read-write clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_bus_root Clock Bus Root 0x14 32 0 clk_mux_sel Clock multiplexing selector: clk_osc, clk_pll2 [29:24] read-write clk_nocstg_bus Clock NOCSTG Bus 0x18 32 0 clk_divcfg Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 [23:0] read-write clk_axi_cfg0 Clock AXI Configuration 0 0x1c 32 0 clk_divcfg Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 [23:0] read-write clk_stg_axiahb Clock STG AXI AHB 0x20 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_ahb0 Clock AHB 0 0x24 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_ahb1 Clock AHB 1 0x28 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_apb_bus Clock APB Bus 0x2c 32 0 clk_divcfg Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4 [23:0] read-write clk_apb0 Clock APB 0 0x30 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_pll0_div2 Clock PLL 0 Divider 2 0x34 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_pll1_div2 Clock PLL 1 Divider 2 0x38 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_pll2_div2 Clock PLL 2 Divider 2 0x3c 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_audio_root Clock Audio Root 0x40 32 0 clk_divcfg Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 [23:0] read-write clk_mclk_inner Clock MCLK Inner 0x44 32 0 clk_divcfg Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12 [23:0] read-write clk_mclk Clock MCLK 0x48 32 0 clk_mux_sel Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext [29:24] read-write clk_mclk_out Clock MCLK Out 0x4c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_isp_2x Clock ISP 2x 0x50 32 0 clk_mux_sel Clock multiplexing selector: clk_pll2, clk_pll1 [29:24] read-write clk_divcfg Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 [23:0] read-write clk_isp_axi Clock ISP AXI 0x54 32 0 clk_divcfg Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2 [23:0] read-write clk_gclk_0 Clock GCLK 0 0x58 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20 [23:0] read-write clk_gclk_1 Clock GCLK 1 0x5c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16 [23:0] read-write clk_gclk_2 Clock GCLK 2 0x60 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12 [23:0] read-write clk_u7mc_core_0 U7MC Core Clock 0 0x64 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_core_1 U7MC Core Clock 1 0x68 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_core_2 U7MC Core Clock 2 0x6c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_core_3 U7MC Core Clock 3 0x70 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_core_4 U7MC Core Clock 4 0x74 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_debug U7MC Debug Clock 0x78 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write u7mc_rtc_toggle U7MC RTC Toggle 0x7c 32 0 clk_divcfg Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6 [23:0] read-write clk_u7mc_trace_0 U7MC Trace Clock 0 0x80 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_trace_1 U7MC Trace Clock 1 0x84 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_trace_2 U7MC Trace Clock 2 0x88 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_trace_3 U7MC Trace Clock 3 0x8c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_trace_4 U7MC Trace Clock 4 0x90 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u7mc_trace_com U7MC Trace Clock COM 0x94 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_noc_bus_cpu_axi clk_u0_sft7110_noc_bus_clk_cpu_axi 0x98 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_noc_bus_axicfg0_axi clk_u0_sft7110_noc_bus_clk_axicfg0_axi 0x9c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_osc_div2 clk_osc_div2 0xa0 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_pll1_div4 clk_pll1_div4 0xa4 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_pll1_div8 clk_pll1_div8 0xa8 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_ddr_bus clk_ddr_bus 0xac 32 0 clk_mux_sel Clock multiplexing selector: clk_osc_div2, clk_pll1_div4, clk_pll1_div8 [29:24] read-write clk_u0_ddr_axi clk_u0_ddr_axi 0xb0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_gpu_core clk_gpu_core 0xb4 32 0 clk_divcfg Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 [23:0] read-write clk_u0_img_gpu_core_clk clk_u0_img_gpu_core_clk 0xb8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_img_gpu_sys_clk clk_u0_img_gpu_sys_clk 0xbc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_img_gpu_clk_apb clk_u0_img_gpu_clk_apb 0xc0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_gpu_rtc_toggle clk_u0_gpu_rtc_toggle 0xc4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12 [23:0] read-write clk_u0_noc_bus_gpu_axi clk_u0_sft7110_noc_bus_clk_gpu_axi 0xc8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_isp_ispcore_2x clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x 0xcc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_isp_axi clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi 0xd0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_noc_bus_isp_axi clk_u0_sft7110_noc_bus_clk_isp_axi 0xd4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_hifi4_core clk_hifi4_core 0xd8 32 0 clk_divcfg Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3 [23:0] read-write clk_hifi4_axi clk_hifi4_axi 0xdc 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_u0_axi_cfg1_dec_clk_main clk_u0_axi_cfg1_dec_clk_main 0xe0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_axi_cfg1_dec_clk_ahb clk_u0_axi_cfg1_dec_clk_ahb 0xe4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_vout_src clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src 0xe8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_vout_axi_divcfg Clock Video Output AXI DIVCFG 0xec 32 0 clk_divcfg Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 [23:0] read-write clk_noc_display_axi Clock NOC Display AXI 0xf0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_vout_ahb Clock Video Output AHB 0xf4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_vout_axi_icg Clock Video Output AXI ICG 0xf8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_vout_hdmi_tx0_mclk Clock Video Output HDMI TX0 MCLK 0xfc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_vout_mipi_phy Clock Video Output MIPI PHY Reference 0x100 32 0 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write clk_jpeg_codec_axi Clock JPEG Codec AXI 0x104 32 0 clk_divcfg Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 [23:0] read-write clk_codaj12_axi CODAJ12 Clock AXI 0x108 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_codaj12_core CODAJ12 Clock Core 0x10c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 [23:0] read-write clk_codaj12_apb CODAJ12 Clock APB 0x110 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_vdec_axi Clock Video Decoder AXI 0x114 32 0 clk_divcfg Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 [23:0] read-write clk_wave511_axi Clock WAVE511 AXI 0x118 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_wave511_bpu Clock WAVE511 BPU 0x11c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 [23:0] read-write clk_wave511_vce Clock WAVE511 VCE 0x120 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2 [23:0] read-write clk_wave511_apb Clock WAVE511 APB 0x124 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_wave511_jpg_arb Clock WAVE511 JPG ARB 0x128 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_wave511_jpg_main Clock WAVE511 JPG Main 0x12c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_noc_vdec_axi Clock NOC Video Decoder AXI 0x130 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_venc_axi Clock Video Encoder AXI 0x134 32 0 clk_divcfg Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 [23:0] read-write clk_wave420l_axi Clock WAVE420L AXI 0x138 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_wave420l_bpu Clock WAVE420L BPU 0x13c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 [23:0] read-write clk_wave420l_vce Clock WAVE420L VCE 0x140 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 [23:0] read-write clk_wave420l_apb Clock WAVE420L APB 0x144 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_noc_venc_axi Clock NOC Video Encoder AXI 0x148 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_axi_cfg0_dec_main_div Clock AXI Config 0 DEC Main Divider 0x14c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_axi_cfg0_dec_main Clock AXI Config 0 DEC Main 0x150 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_axi_cfg0_dec_hifi4 Clock AXI Config 0 DEC HIFI4 0x154 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_aximem_128b_axi Clock AXIMEM 128B AXI 0x158 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_qspi_ahb Clock QSPI AHB 0x15c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_qspi_apb Clock QSPI APB 0x160 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_qspi_ref_src Clock QSPI Reference Source 0x164 32 0 clk_divcfg Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10 [23:0] read-write clk_qspi_ref Clock QSPI Reference 0x168 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_mux_sel Clock multiplexing selector: clk_osc, clk_qspi_ref_src [29:24] read-write clk_u0_sd_ahb U0 SD Clock AHB 0x16c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_sd_ahb U1 SD Clock AHB 0x170 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_sd_card U0 SD Card Clock 0x174 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2 [23:0] read-write clk_u1_sd_card U1 SD Card Clock 0x178 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2 [23:0] read-write clk_usb_125m Clock USB 125M 0x17c 32 0 clk_divcfg Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write clk_noc_stg_axi Clock NOC STG AXI 0x180 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_gmac5_axi64_ahb Clock GMAC 5 AXI 64 AHB 0x184 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_gmac5_axi64_axi Clock GMAC 5 AXI 64 AXI 0x188 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_gmac_src Clock GMAC Source 0x18c 32 0 clk_divcfg Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 [23:0] read-write clk_gmac1_gtx Clock GMAC 1 GTX 0x190 32 0 clk_divcfg Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write clk_gmac1_rmii_rtx Clock GMAC 1 RMII RTX 0x194 32 0 clk_divcfg Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 [23:0] read-write clk_gmac5_axi64_ptp Clock GMAC 5 AXI 64 PTP 0x198 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10 [23:0] read-write clk_gmac5_axi64_rx Clock GMAC 5 AXI 64 RX 0x19c 32 0 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write clk_gmac5_axi64_rxi Clock GMAC 5 AXI 64 RX Inverter 0x1a0 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_gmac5_axi64_tx Clock GMAC 5 AXI 64 TX 0x1a4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_mux_sel Clock multiplexing selector: clk_gmac1_gtxclk, clk_gmac1_rmii_rtx [29:24] read-write clk_gmac5_axi64_txi Clock GMAC 5 AXI 64 TX Inverter 0x1a8 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_gmac1_gtxclk Clock GMAC 1 GTXC 0x1ac 32 0 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write clk_gmac0_gtx Clock GMAC 0 GTX 0x1b0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write clk_gmac0_ptp Clock GMAC 0 PTP 0x1b4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 [23:0] read-write clk_gmac_phy Clock GMAC PHY 0x1b8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 [23:0] read-write clk_gmac0_gtxclk Clock GMAC 0 GTXC 0x1bc 32 0 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write clk_pclk Clock SYS IOMUX PCLK 0x1c0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_mbox_apb Clock Mailbox APB 0x1c4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_internal_ctrl_apb Clock Internal Controller APB 0x1c8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_can_ctrl_apb U0 Clock CAN Controller APB 0x1cc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_can_ctrl_tim U0 Clock CAN Controller Timer 0x1d0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24 [23:0] read-write clk_u0_can_ctrl_can U0 Clock CAN Controller CAN 0x1d4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8 [23:0] read-write clk_u1_can_ctrl_apb U1 Clock CAN Controller APB 0x1d8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_can_ctrl_tim U1 Clock CAN Controller Timer 0x1dc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24 [23:0] read-write clk_u1_can_ctrl_can U1 Clock CAN Controller CAN 0x1e0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8 [23:0] read-write clk_pwm_apb Clock PWM APB 0x1e4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_wdt_apb Clock WDT APB 0x1e8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_wdt Clock WDT 0x1ec 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tim_apb Clock Timer APB 0x1f0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tim_0 Clock Timer 0 0x1f4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tim_1 Clock Timer 1 0x1f8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tim_2 Clock Timer 2 0x1fc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tim_3 Clock Timer 3 0x200 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_temp_sensor_apb Clock Temperature Sensor APB 0x204 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_temp_sensor Clock Temperature Sensor 0x208 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 [23:0] read-write clk_u0_spi_apb U0 Clock SPI APB 0x20c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_spi_apb U1 Clock SPI APB 0x210 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u2_spi_apb U2 Clock SPI APB 0x214 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u3_spi_apb U3 Clock SPI APB 0x218 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u4_spi_apb U4 Clock SPI APB 0x21c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u5_spi_apb U5 Clock SPI APB 0x220 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u6_spi_apb U6 Clock SPI APB 0x224 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_i2c_apb U0 Clock I2C APB 0x228 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_i2c_apb U1 Clock I2C APB 0x22c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u2_i2c_apb U2 Clock I2C APB 0x230 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u3_i2c_apb U3 Clock I2C APB 0x234 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u4_i2c_apb U4 Clock I2C APB 0x238 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u5_i2c_apb U5 Clock I2C APB 0x23c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u6_i2c_apb U6 Clock I2C APB 0x240 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_uart_apb U0 Clock UART APB 0x244 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_uart_core U0 Clock UART Core 0x248 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_uart_apb U1 Clock UART APB 0x24c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_uart_core U1 Clock UART Core 0x250 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u2_uart_apb U2 Clock UART APB 0x254 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u2_uart_core U2 Clock UART Core 0x258 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u3_uart_apb U3 Clock UART APB 0x25c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u3_uart_core U3 Clock UART Core 0x260 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 [23:0] read-write clk_u4_uart_apb U4 Clock UART APB 0x264 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u4_uart_core U4 Clock UART Core 0x268 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 [23:0] read-write clk_u5_uart_apb U5 Clock UART APB 0x26c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u5_uart_core U5 Clock UART Core 0x270 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 [23:0] read-write clk_pwmdac_apb Clock PWMDAC APB 0x274 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_pwmdac_core Clock PWMDAC Core 0x278 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12 [23:0] read-write clk_spdif_apb Clock SPDIF APB 0x27c 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_spdif_core Clock SPDIF Core 0x280 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_i2s_tx_apb U0 Clock I2S TX APB 0x284 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u0_i2stx_4ch0_bclk_mst U0 Clock I2S TX 0 BCLK MST 0x288 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 [23:0] read-write clk_u0_i2stx_4ch0_bclk_mst_inv U0 Clock I2S TX 0 BCLK MST Inverter 0x28c 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_i2stx0_lrck_mst Clock I2S TX 0 LRCK MST 0x290 32 0 clk_mux_sel Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst [29:24] read-write clk_divcfg Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 [23:0] read-write clk_u0_i2stx_bclk U0 Clock I2S TX BCLK 0x294 32 0 clk_mux_sel Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst, clk_i2stx_bclk_ext [29:24] read-write clk_u0_i2stx_bclk_neg U0 Clock I2S TX BCLK Negative 0x298 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_u0_i2stx_lrck U0 Clock I2S TX LRCK 0x29c 32 0 clk_mux_sel Clock multiplexing selector: clk_i2stx_4ch0_lrck_mst, clk_i2stx_lrck_ext [29:24] read-write clk_u1_i2s_tx_apb U1 Clock I2S TX APB 0x2a0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_u1_i2stx_4ch1_bclk_mst U1 Clock I2S TX 1 BCLK MST 0x2a4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 [23:0] read-write clk_u1_i2stx_4ch1_bclk_mst_inv U1 Clock I2S TX 1 BCLK MST Inverter 0x2a8 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_i2stx1_lrck_mst Clock I2S TX 1 LRCK MST 0x2ac 32 0 clk_mux_sel Clock multiplexing selector: clk_i2stx_4ch0_bclk_mst_inv, clk_i2stx_4ch0_bclk_mst [29:24] read-write clk_divcfg Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 [23:0] read-write clk_u1_i2stx_bclk U1 Clock I2S TX BCLK 0x2b0 32 0 clk_mux_sel Clock multiplexing selector: clk_i2stx_4ch1_bclk_mst, clk_i2stx_bclk_ext [29:24] read-write clk_u1_i2stx_bclk_neg U1 Clock I2S TX BCLK Negative 0x2b4 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_u1_i2stx_lrck U1 Clock I2S TX LRCK 0x2b8 32 0 clk_mux_sel Clock multiplexing selector: clk_i2stx_4ch1_lrck_mst, clk_i2stx_lrck_ext [29:24] read-write clk_i2s_apb Clock I2S APB 0x2bc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_i2s_bclk_mst Clock I2S BCLK MST 0x2c0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 [23:0] read-write clk_i2s_bclk_mst_inv Clock I2S BCLK MST Inverter 0x2c4 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_i2s_lrck_mst Clock I2S LRCK MST 0x2c8 32 0 clk_mux_sel Clock multiplexing selector: clk_i2srx_3ch_bclk_mst_inv, clk_i2srx_3ch_bclk_mst [29:24] read-write clk_divcfg Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 [23:0] read-write clk_i2s_bclk Clock I2S BCLK 0x2cc 32 0 clk_mux_sel Clock multiplexing selector: clk_i2srx_3ch_bclk_mst, clk_i2srx_3ch_bclk_ext [29:24] read-write clk_i2s_bclk_neg Clock I2S BCLK Negative 0x2d0 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_i2s_lrck Clock I2S LRCK 0x2d4 32 0 clk_mux_sel Clock multiplexing selector: clk_i2srx_3ch_lrck_mst, clk_i2srx_3ch_lrck_ext [29:24] read-write clk_pdm_dmic Clock PDM DMIC 0x2d8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8 [23:0] read-write clk_pdm_apb Clock PDM APB 0x2dc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tdm_ahb Clock TDM AHB 0x2e0 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tdm_apb Clock TDM APB 0x2e4 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_tdm_internal Clock TDM Internal 0x2e8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_divcfg Clock divider coefficient: Max=64, Default=1, Min=1, Typical=1 [23:0] read-write clk_tdm Clock TDM 0x2ec 32 0 clk_mux_sel Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext [29:24] read-write clk_tdm_neg Clock TDM Negative 0x2f0 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_jtag_trng Clock JTAG Certification TRNG 0x2f4 32 0 clk_divcfg Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 [23:0] read-write soft_rst_addr_sel_0 Software RESET 0 Address Selector 0x2f8 32 0 u0_jtag2apb_presetn 1: Assert reset, 0: De-assert reset [0:0] read-write u0_sys_syscon_presetn 1: Assert reset, 0: De-assert reset [1:1] read-write u0_sys_iomux_presetn 1: Assert reset, 0: De-assert reset [2:2] read-write u0_bus 1: Assert reset, 0: De-assert reset [3:3] read-write u0_debug 1: Assert reset, 0: De-assert reset [4:4] read-write u0_core_0 1: Assert reset, 0: De-assert reset [5:5] read-write u0_core_1 1: Assert reset, 0: De-assert reset [6:6] read-write u0_core_2 1: Assert reset, 0: De-assert reset [7:7] read-write u0_core3 1: Assert reset, 0: De-assert reset [8:8] read-write u0_core4 1: Assert reset, 0: De-assert reset [9:9] read-write u0_core_st_0 1: Assert reset, 0: De-assert reset [10:10] read-write u0_core_st_1 1: Assert reset, 0: De-assert reset [11:11] read-write u0_core_st_2 1: Assert reset, 0: De-assert reset [12:12] read-write u0_core_st_3 1: Assert reset, 0: De-assert reset [13:13] read-write u0_core_st_4 1: Assert reset, 0: De-assert reset [14:14] read-write u0_trace_0 1: Assert reset, 0: De-assert reset [15:15] read-write u0_trace_1 1: Assert reset, 0: De-assert reset [16:16] read-write u0_trace_2 1: Assert reset, 0: De-assert reset [17:17] read-write u0_trace_3 1: Assert reset, 0: De-assert reset [18:18] read-write u0_trace_4 1: Assert reset, 0: De-assert reset [19:19] read-write u0_trace_com 1: Assert reset, 0: De-assert reset [20:20] read-write u0_img_gpu_apb 1: Assert reset, 0: De-assert reset [21:21] read-write u0_img_gpu_doma 1: Assert reset, 0: De-assert reset [22:22] read-write u0_noc_bus_apb 1: Assert reset, 0: De-assert reset [23:23] read-write u0_noc_bus_axicfg0 1: Assert reset, 0: De-assert reset [24:24] read-write u0_noc_bus_cpu_axi 1: Assert reset, 0: De-assert reset [25:25] read-write u0_noc_bus_disp_axi 1: Assert reset, 0: De-assert reset [26:26] read-write u0_noc_bus_gpu_axi 1: Assert reset, 0: De-assert reset [27:27] read-write u0_noc_bus_isp_axi 1: Assert reset, 0: De-assert reset [28:28] read-write u0_noc_bus_ddrc 1: Assert reset, 0: De-assert reset [29:29] read-write u0_noc_bus_stg_axi 1: Assert reset, 0: De-assert reset [30:30] read-write u0_noc_bus_vdec_axi 1: Assert reset, 0: De-assert reset [31:31] read-write soft_rst_addr_sel_1 Software RESET 1 Address Selector 0x2fc 32 0 u0_noc_bus_venc_axi 1: Assert reset, 0: De-assert reset [0:0] read-write u0_axi_cfg1_dec_ahb 1: Assert reset, 0: De-assert reset [1:1] read-write u0_axi_cfg1_dec_main 1: Assert reset, 0: De-assert reset [2:2] read-write u0_axi_cfg0_dec_main 1: Assert reset, 0: De-assert reset [3:3] read-write u0_axi_cfg0_dec_main_div 1: Assert reset, 0: De-assert reset [4:4] read-write u0_axi_cfg0_dec_hifi4 1: Assert reset, 0: De-assert reset [5:5] read-write u0_ddr_axi 1: Assert reset, 0: De-assert reset [6:6] read-write u0_ddr_osc 1: Assert reset, 0: De-assert reset [7:7] read-write u0_ddr_apb 1: Assert reset, 0: De-assert reset [8:8] read-write u0_isp_top 1: Assert reset, 0: De-assert reset [9:9] read-write u0_isp_axi 1: Assert reset, 0: De-assert reset [10:10] read-write u0_vout_src 1: Assert reset, 0: De-assert reset [11:11] read-write u0_codaj12_axi 1: Assert reset, 0: De-assert reset [12:12] read-write u0_codaj12_core 1: Assert reset, 0: De-assert reset [13:13] read-write u0_codaj12_apb 1: Assert reset, 0: De-assert reset [14:14] read-write u0_wave511_axi 1: Assert reset, 0: De-assert reset [15:15] read-write u0_wave511_bpu 1: Assert reset, 0: De-assert reset [16:16] read-write u0_wave511_vce 1: Assert reset, 0: De-assert reset [17:17] read-write u0_wave511_apb 1: Assert reset, 0: De-assert reset [18:18] read-write u0_vdec_jpg_arb 1: Assert reset, 0: De-assert reset [19:19] read-write u0_vdec_jpg_arb_main 1: Assert reset, 0: De-assert reset [20:20] read-write u0_aximem_128b_axi 1: Assert reset, 0: De-assert reset [21:21] read-write u0_wave420l_axi 1: Assert reset, 0: De-assert reset [22:22] read-write u0_wave420l_bpu 1: Assert reset, 0: De-assert reset [23:23] read-write u0_wave420l_vce 1: Assert reset, 0: De-assert reset [24:24] read-write u0_wave420l_apb 1: Assert reset, 0: De-assert reset [25:25] read-write u1_aximem 1: Assert reset, 0: De-assert reset [26:26] read-write u2_aximem 1: Assert reset, 0: De-assert reset [27:27] read-write u0_intmem_rom_sram 1: Assert reset, 0: De-assert reset [28:28] read-write u0_qspi_ahb 1: Assert reset, 0: De-assert reset [29:29] read-write u0_qspi_apb 1: Assert reset, 0: De-assert reset [30:30] read-write u0_qspi_ref 1: Assert reset, 0: De-assert reset [31:31] read-write soft_rst_addr_sel_2 Software RESET 2 Address Selector 0x300 32 0 u0_sdio_ahb 1: Assert reset, 0: De-assert reset [0:0] read-write u1_sdi_ahb 1: Assert reset, 0: De-assert reset [1:1] read-write u1_gmac5_axi64 1: Assert reset, 0: De-assert reset [2:2] read-write u1_gmac5_axi64_hresetn 1: Assert reset, 0: De-assert reset [3:3] read-write u0_mailbox_presetn 1: Assert reset, 0: De-assert reset [4:4] read-write u0_spi_apb 1: Assert reset, 0: De-assert reset [5:5] read-write u1_spi_apb 1: Assert reset, 0: De-assert reset [6:6] read-write u2_spi_apb 1: Assert reset, 0: De-assert reset [7:7] read-write u3_spi_apb 1: Assert reset, 0: De-assert reset [8:8] read-write u4_spi_apb 1: Assert reset, 0: De-assert reset [9:9] read-write u5_spi_apb 1: Assert reset, 0: De-assert reset [10:10] read-write u6_spi_apb 1: Assert reset, 0: De-assert reset [11:11] read-write u0_i2c_apb 1: Assert reset, 0: De-assert reset [12:12] read-write u1_i2c_apb 1: Assert reset, 0: De-assert reset [13:13] read-write u2_i2c_apb 1: Assert reset, 0: De-assert reset [14:14] read-write u3_i2c_apb 1: Assert reset, 0: De-assert reset [15:15] read-write u4_i2c_apb 1: Assert reset, 0: De-assert reset [16:16] read-write u5_i2c_apb 1: Assert reset, 0: De-assert reset [17:17] read-write u6_i2c_apb 1: Assert reset, 0: De-assert reset [18:18] read-write u0_uart_apb 1: Assert reset, 0: De-assert reset [19:19] read-write u0_uart_core 1: Assert reset, 0: De-assert reset [20:20] read-write u1_uart_apb 1: Assert reset, 0: De-assert reset [21:21] read-write u1_uart_core 1: Assert reset, 0: De-assert reset [22:22] read-write u2_uart_apb 1: Assert reset, 0: De-assert reset [23:23] read-write u2_uart_core 1: Assert reset, 0: De-assert reset [24:24] read-write u3_uart_apb 1: Assert reset, 0: De-assert reset [25:25] read-write u3_uart_core 1: Assert reset, 0: De-assert reset [26:26] read-write u4_uart_apb 1: Assert reset, 0: De-assert reset [27:27] read-write u4_uart_core 1: Assert reset, 0: De-assert reset [28:28] read-write u5_uart_apb 1: Assert reset, 0: De-assert reset [29:29] read-write u6_uart_core 1: Assert reset, 0: De-assert reset [30:30] read-write u0_spdif_apb 1: Assert reset, 0: De-assert reset [31:31] read-write soft_rst_addr_sel_3 Software RESET 3 Address Selector 0x304 32 0 u0_pwmdac_apb 1: Assert reset, 0: De-assert reset [0:0] read-write u0_pdm_4mic_dmic 1: Assert reset, 0: De-assert reset [1:1] read-write u0_pdm_4mic_apb 1: Assert reset, 0: De-assert reset [2:2] read-write u0_i2srx_apb 1: Assert reset, 0: De-assert reset [3:3] read-write u0_i2srx_bclk 1: Assert reset, 0: De-assert reset [4:4] read-write u0_i2stx_apb 1: Assert reset, 0: De-assert reset [5:5] read-write u0_i2stx_bclk 1: Assert reset, 0: De-assert reset [6:6] read-write u1_i2stx_apb 1: Assert reset, 0: De-assert reset [7:7] read-write u1_i2stx_bclk 1: Assert reset, 0: De-assert reset [8:8] read-write u0_tdm16slot_ahb 1: Assert reset, 0: De-assert reset [9:9] read-write u0_tdm16slot_tdm 1: Assert reset, 0: De-assert reset [10:10] read-write u0_tdm16slot_apb 1: Assert reset, 0: De-assert reset [11:11] read-write u0_pwm_apb 1: Assert reset, 0: De-assert reset [12:12] read-write u0_dskit_wdt_rstn_apb 1: Assert reset, 0: De-assert reset [13:13] read-write u0_dskit_wdt 1: Assert reset, 0: De-assert reset [14:14] read-write u0_can_ctrl_apb 1: Assert reset, 0: De-assert reset [15:15] read-write u0_can_ctrl 1: Assert reset, 0: De-assert reset [16:16] read-write u0_can_ctrl_timer 1: Assert reset, 0: De-assert reset [17:17] read-write u1_can_ctrl_apb 1: Assert reset, 0: De-assert reset [18:18] read-write u1_can_ctrl_can 1: Assert reset, 0: De-assert reset [19:19] read-write u1_can_ctrl_timer 1: Assert reset, 0: De-assert reset [20:20] read-write u0_si5_timer_apb 1: Assert reset, 0: De-assert reset [21:21] read-write u0_si5_timer_0 1: Assert reset, 0: De-assert reset [22:22] read-write u0_si5_timer_1 1: Assert reset, 0: De-assert reset [23:23] read-write u0_si5_timer_2 1: Assert reset, 0: De-assert reset [24:24] read-write u0_si5_timer_3 1: Assert reset, 0: De-assert reset [25:25] read-write u0_int_ctrl_apb 1: Assert reset, 0: De-assert reset [26:26] read-write u0_temp_sensor_apb 1: Assert reset, 0: De-assert reset [27:27] read-write u0_temp_sensor 1: Assert reset, 0: De-assert reset [28:28] read-write u0_jtag_rst 1: Assert reset, 0: De-assert reset [29:29] read-write syscrg_rst_status_0 SYSCRG RESET Status 0 0x308 32 0 u0_jtag2apb_presetn 1: Assert reset, 0: De-assert reset [0:0] read-write u0_sys_syscon_presetn 1: Assert reset, 0: De-assert reset [1:1] read-write u0_sys_iomux_presetn 1: Assert reset, 0: De-assert reset [2:2] read-write u0_bus 1: Assert reset, 0: De-assert reset [3:3] read-write u0_debug 1: Assert reset, 0: De-assert reset [4:4] read-write u0_core_0 1: Assert reset, 0: De-assert reset [5:5] read-write u0_core_1 1: Assert reset, 0: De-assert reset [6:6] read-write u0_core_2 1: Assert reset, 0: De-assert reset [7:7] read-write u0_core3 1: Assert reset, 0: De-assert reset [8:8] read-write u0_core4 1: Assert reset, 0: De-assert reset [9:9] read-write u0_core_st_0 1: Assert reset, 0: De-assert reset [10:10] read-write u0_core_st_1 1: Assert reset, 0: De-assert reset [11:11] read-write u0_core_st_2 1: Assert reset, 0: De-assert reset [12:12] read-write u0_core_st_3 1: Assert reset, 0: De-assert reset [13:13] read-write u0_core_st_4 1: Assert reset, 0: De-assert reset [14:14] read-write u0_trace_0 1: Assert reset, 0: De-assert reset [15:15] read-write u0_trace_1 1: Assert reset, 0: De-assert reset [16:16] read-write u0_trace_2 1: Assert reset, 0: De-assert reset [17:17] read-write u0_trace_3 1: Assert reset, 0: De-assert reset [18:18] read-write u0_trace_4 1: Assert reset, 0: De-assert reset [19:19] read-write u0_trace_com 1: Assert reset, 0: De-assert reset [20:20] read-write u0_img_gpu_apb 1: Assert reset, 0: De-assert reset [21:21] read-write u0_img_gpu_doma 1: Assert reset, 0: De-assert reset [22:22] read-write u0_noc_bus_apb 1: Assert reset, 0: De-assert reset [23:23] read-write u0_noc_bus_axicfg0 1: Assert reset, 0: De-assert reset [24:24] read-write u0_noc_bus_cpu_axi 1: Assert reset, 0: De-assert reset [25:25] read-write u0_noc_bus_disp_axi 1: Assert reset, 0: De-assert reset [26:26] read-write u0_noc_bus_gpu_axi 1: Assert reset, 0: De-assert reset [27:27] read-write u0_noc_bus_isp_axi 1: Assert reset, 0: De-assert reset [28:28] read-write u0_noc_bus_ddrc 1: Assert reset, 0: De-assert reset [29:29] read-write u0_noc_bus_stg_axi 1: Assert reset, 0: De-assert reset [30:30] read-write u0_noc_bus_vdec_axi 1: Assert reset, 0: De-assert reset [31:31] read-write syscrg_rst_status_1 SYSCRG RESET Status 1 0x30c 32 0 u0_noc_bus_venc_axi 1: Assert reset, 0: De-assert reset [0:0] read-write u0_axi_cfg1_dec_ahb 1: Assert reset, 0: De-assert reset [1:1] read-write u0_axi_cfg1_dec_main 1: Assert reset, 0: De-assert reset [2:2] read-write u0_axi_cfg0_dec_main 1: Assert reset, 0: De-assert reset [3:3] read-write u0_axi_cfg0_dec_main_div 1: Assert reset, 0: De-assert reset [4:4] read-write u0_axi_cfg0_dec_hifi4 1: Assert reset, 0: De-assert reset [5:5] read-write u0_ddr_axi 1: Assert reset, 0: De-assert reset [6:6] read-write u0_ddr_osc 1: Assert reset, 0: De-assert reset [7:7] read-write u0_ddr_apb 1: Assert reset, 0: De-assert reset [8:8] read-write u0_isp_top 1: Assert reset, 0: De-assert reset [9:9] read-write u0_isp_axi 1: Assert reset, 0: De-assert reset [10:10] read-write u0_vout_src 1: Assert reset, 0: De-assert reset [11:11] read-write u0_codaj12_axi 1: Assert reset, 0: De-assert reset [12:12] read-write u0_codaj12_core 1: Assert reset, 0: De-assert reset [13:13] read-write u0_codaj12_apb 1: Assert reset, 0: De-assert reset [14:14] read-write u0_wave511_axi 1: Assert reset, 0: De-assert reset [15:15] read-write u0_wave511_bpu 1: Assert reset, 0: De-assert reset [16:16] read-write u0_wave511_vce 1: Assert reset, 0: De-assert reset [17:17] read-write u0_wave511_apb 1: Assert reset, 0: De-assert reset [18:18] read-write u0_vdec_jpg_arb 1: Assert reset, 0: De-assert reset [19:19] read-write u0_vdec_jpg_arb_main 1: Assert reset, 0: De-assert reset [20:20] read-write u0_aximem_128b_axi 1: Assert reset, 0: De-assert reset [21:21] read-write u0_wave420l_axi 1: Assert reset, 0: De-assert reset [22:22] read-write u0_wave420l_bpu 1: Assert reset, 0: De-assert reset [23:23] read-write u0_wave420l_vce 1: Assert reset, 0: De-assert reset [24:24] read-write u0_wave420l_apb 1: Assert reset, 0: De-assert reset [25:25] read-write u1_aximem 1: Assert reset, 0: De-assert reset [26:26] read-write u2_aximem 1: Assert reset, 0: De-assert reset [27:27] read-write u0_intmem_rom_sram 1: Assert reset, 0: De-assert reset [28:28] read-write u0_qspi_ahb 1: Assert reset, 0: De-assert reset [29:29] read-write u0_qspi_apb 1: Assert reset, 0: De-assert reset [30:30] read-write u0_qspi_ref 1: Assert reset, 0: De-assert reset [31:31] read-write syscrg_rst_status_2 SYSCRG RESET Status 2 0x310 32 0 u0_sdio_ahb 1: Assert reset, 0: De-assert reset [0:0] read-write u1_sdi_ahb 1: Assert reset, 0: De-assert reset [1:1] read-write u1_gmac5_axi64 1: Assert reset, 0: De-assert reset [2:2] read-write u1_gmac5_axi64_hresetn 1: Assert reset, 0: De-assert reset [3:3] read-write u0_mailbox_presetn 1: Assert reset, 0: De-assert reset [4:4] read-write u0_spi_apb 1: Assert reset, 0: De-assert reset [5:5] read-write u1_spi_apb 1: Assert reset, 0: De-assert reset [6:6] read-write u2_spi_apb 1: Assert reset, 0: De-assert reset [7:7] read-write u3_spi_apb 1: Assert reset, 0: De-assert reset [8:8] read-write u4_spi_apb 1: Assert reset, 0: De-assert reset [9:9] read-write u5_spi_apb 1: Assert reset, 0: De-assert reset [10:10] read-write u6_spi_apb 1: Assert reset, 0: De-assert reset [11:11] read-write u0_i2c_apb 1: Assert reset, 0: De-assert reset [12:12] read-write u1_i2c_apb 1: Assert reset, 0: De-assert reset [13:13] read-write u2_i2c_apb 1: Assert reset, 0: De-assert reset [14:14] read-write u3_i2c_apb 1: Assert reset, 0: De-assert reset [15:15] read-write u4_i2c_apb 1: Assert reset, 0: De-assert reset [16:16] read-write u5_i2c_apb 1: Assert reset, 0: De-assert reset [17:17] read-write u6_i2c_apb 1: Assert reset, 0: De-assert reset [18:18] read-write u0_uart_apb 1: Assert reset, 0: De-assert reset [19:19] read-write u0_uart_core 1: Assert reset, 0: De-assert reset [20:20] read-write u1_uart_apb 1: Assert reset, 0: De-assert reset [21:21] read-write u1_uart_core 1: Assert reset, 0: De-assert reset [22:22] read-write u2_uart_apb 1: Assert reset, 0: De-assert reset [23:23] read-write u2_uart_core 1: Assert reset, 0: De-assert reset [24:24] read-write u3_uart_apb 1: Assert reset, 0: De-assert reset [25:25] read-write u3_uart_core 1: Assert reset, 0: De-assert reset [26:26] read-write u4_uart_apb 1: Assert reset, 0: De-assert reset [27:27] read-write u4_uart_core 1: Assert reset, 0: De-assert reset [28:28] read-write u5_uart_apb 1: Assert reset, 0: De-assert reset [29:29] read-write u6_uart_core 1: Assert reset, 0: De-assert reset [30:30] read-write u0_spdif_apb 1: Assert reset, 0: De-assert reset [31:31] read-write syscrg_rst_status_3 SYSCRG RESET Status 3 0x314 32 0 u0_pwmdac_apb 1: Assert reset, 0: De-assert reset [0:0] read-write u0_pdm_4mic_dmic 1: Assert reset, 0: De-assert reset [1:1] read-write u0_pdm_4mic_apb 1: Assert reset, 0: De-assert reset [2:2] read-write u0_i2srx_apb 1: Assert reset, 0: De-assert reset [3:3] read-write u0_i2srx_bclk 1: Assert reset, 0: De-assert reset [4:4] read-write u0_i2stx_apb 1: Assert reset, 0: De-assert reset [5:5] read-write u0_i2stx_bclk 1: Assert reset, 0: De-assert reset [6:6] read-write u1_i2stx_apb 1: Assert reset, 0: De-assert reset [7:7] read-write u1_i2stx_bclk 1: Assert reset, 0: De-assert reset [8:8] read-write u0_tdm16slot_ahb 1: Assert reset, 0: De-assert reset [9:9] read-write u0_tdm16slot_tdm 1: Assert reset, 0: De-assert reset [10:10] read-write u0_tdm16slot_apb 1: Assert reset, 0: De-assert reset [11:11] read-write u0_pwm_apb 1: Assert reset, 0: De-assert reset [12:12] read-write u0_dskit_wdt_rstn_apb 1: Assert reset, 0: De-assert reset [13:13] read-write u0_dskit_wdt 1: Assert reset, 0: De-assert reset [14:14] read-write u0_can_ctrl_apb 1: Assert reset, 0: De-assert reset [15:15] read-write u0_can_ctrl 1: Assert reset, 0: De-assert reset [16:16] read-write u0_can_ctrl_timer 1: Assert reset, 0: De-assert reset [17:17] read-write u1_can_ctrl_apb 1: Assert reset, 0: De-assert reset [18:18] read-write u1_can_ctrl_can 1: Assert reset, 0: De-assert reset [19:19] read-write u1_can_ctrl_timer 1: Assert reset, 0: De-assert reset [20:20] read-write u0_si5_timer_apb 1: Assert reset, 0: De-assert reset [21:21] read-write u0_si5_timer_0 1: Assert reset, 0: De-assert reset [22:22] read-write u0_si5_timer_1 1: Assert reset, 0: De-assert reset [23:23] read-write u0_si5_timer_2 1: Assert reset, 0: De-assert reset [24:24] read-write u0_si5_timer_3 1: Assert reset, 0: De-assert reset [25:25] read-write u0_int_ctrl_apb 1: Assert reset, 0: De-assert reset [26:26] read-write u0_temp_sensor_apb 1: Assert reset, 0: De-assert reset [27:27] read-write u0_temp_sensor 1: Assert reset, 0: De-assert reset [28:28] read-write u0_jtag_rst 1: Assert reset, 0: De-assert reset [29:29] read-write sys_syscon From starfive,jh7110-sys-syscon, peripheral generator 0x13030000 0 0x1000 registers sys_syscfg_0 SYS SYSCONSAIF SYSCFG 0 0x0 32 0 e24_remap_haddr e24_remap_haddr [3:0] read-write hifi4_idma_remap_araddr hifi4_idma_remap_araddr [7:4] read-write hifi4_idma_remap_awaddr hifi4_idma_remap_awaddr [11:8] read-write hifi4_sys_remap_araddr hifi4_sys_remap_araddr [15:12] read-write hifi4_sys_remap_awaddr hifi4_sys_remap_awaddr [19:16] read-write jpg_remap_araddr jpg_remap_araddr [23:20] read-write jpg_remap_awaddr jpg_remap_awaddr [27:24] read-write sd0_remap_araddr sd0_remap_araddr [31:28] read-write sys_syscfg_1 SYS SYSCONSAIF SYSCFG 4 0x4 32 0 sd1_remap_awaddr sd1_remap_awaddr [3:0] read-write sec_haddr_remap sec_haddr_remap [7:4] read-write usb_araddr_remap usb_araddr_remap [11:8] read-write usb_awaddr_remap usb_awaddr_remap [15:12] read-write vdec_remap_awaddr vdec_remap_awaddr [19:16] read-write venc_remap_araddr venc_remap_araddr [23:20] read-write venc_remap_awaddr venc_remap_awaddr [27:24] read-write vout0_remap_araddr vout0_remap_araddr [31:28] read-write sys_syscfg_2 SYS SYSCONSAIF SYSCFG 8 0x8 32 0 vout0_remap_awaddr vout0_remap_awaddr [3:0] read-write vout1_remap_araddr vout1_remap_araddr [7:4] read-write vout1_remap_awaddr vout1_remap_awaddr [11:8] read-write sys_syscfg_3 SYS SYSCONSAIF SYSCFG 12: Set the GPIO voltage of all the 4 GPIO groups in this register 0xc 32 0 vout0_remap_awaddr_gpio0 0: GPIO Group 0 (GPIO21-35) voltage select 3.3V, 1: GPIO Group 0 (GPIO21-35) voltage select 1.8V [0:0] read-write vout0_remap_awaddr_gpio1 0: GPIO Group 1 (GPIO36-63) voltage select 3.3V, 1: GPIO Group 1 (GPIO36-63) voltage select 1.8V [1:1] read-write vout0_remap_awaddr_gpio2 0: GPIO Group 2 (GPIO0-6) voltage select 3.3V, 1: GPIO Group 2 (GPIO0-6) voltage select 1.8V [2:2] read-write vout0_remap_awaddr_gpio3 0: GPIO Group 3 (GPIO7-20) voltage select 3.3V, 1: GPIO Group 3 (GPIO7-20) voltage select 1.8V [3:3] read-write sys_syscfg_4 SYS SYSCONSAIF SYSCFG 16 0x10 32 0 coda12_cur_inst Tie 0 in JPU internal, do not care [1:0] read-only wave511_vpu_idle VPU monitoring signal [2:2] read-only can_ctrl_fd_enable_0 can_ctrl_fd_enable_0 [3:3] read-write can_ctrl_host_ecc_disable_0 can_ctrl_host_ecc_disable_0 [4:4] read-write can_ctrl_host_if_0 can_ctrl_host_if_0 [23:5] read-only qspi_sclk_dlychain_sel des_qspi_sclk_dla: clock delay [28:24] read-only sys_syscfg_5 SYS SYSCONSAIF SYSCFG 20 0x14 32 0 u0_cdns_qspi_scfg_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [0:0] read-write u0_cdns_qspi_scfg_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [1:1] read-write u0_cdns_qspi_scfg_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [3:2] read-write u0_cdns_qspi_scfg_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [5:4] read-write u0_cdns_qspi_scfg_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [7:6] read-write u0_cdns_qspi_scfg_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write u0_cdns_qspi_scfg_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write u0_cdns_qspi_scfg_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write u0_cdns_spdif_scfg_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [12:12] read-write u0_cdns_spdif_scfg_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [13:13] read-write u0_cdns_spdif_scfg_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [15:14] read-write u0_cdns_spdif_scfg_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [17:16] read-write u0_cdns_spdif_scfg_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [19:18] read-write u0_cdns_spdif_scfg_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [21:20] read-write u0_cdns_spdif_scfg_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [22:22] read-write u0_cdns_spdif_scfg_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [23:23] read-write spdif_trmodeo 1 for transmitter 0 for receiver [24:24] read-only i2c_ic_en I2C interface enable [25:25] read-only sdio_data_strobe_phase_ctrl Data strobe delay chain select [30:26] read-write sdio_hbig_endian AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface [31:31] read-write sys_syscfg_6 SYS SYSCONSAIF SYSCFG 24 0x18 32 0 sdio_m_hbig_endian AHB master bus interface endianess: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface [0:0] read-write i2srx_adc_en i2srx_adc_en [1:1] read-write intmem_rom_sram_scfg_disable_rom intmem_rom_sram_scfg_disable_rom [2:2] read-write u0_intmem_rom_sram_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [3:3] read-write u0_intmem_rom_sram_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [4:4] read-write u0_intmem_rom_sram_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [6:5] read-write u0_intmem_rom_sram_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [8:7] read-write u0_intmem_rom_sram_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [10:9] read-write u0_intmem_rom_sram_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [12:11] read-write u0_intmem_rom_sram_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [13:13] read-write u0_intmem_rom_sram_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [14:14] read-write jtag_daisy_chain_en_0 jtag_daisy_chain_en_0 [15:15] read-write jtag_daisy_chain_en_1 jtag_daisy_chain_en_1 [16:16] read-write pdrstn_usbpipe_plugen pdrstn_usbpipe_plugen [17:17] read-write pll0_cpi_bias pll0_cpi_bias [20:18] read-write pll0_cpp_bias pll0_cpp_bias [23:21] read-write pll0_dacpd pll0_dacpd [24:24] read-write pll0_dsmpd pll0_dsmpd [25:25] read-write sys_syscfg_7 SYS SYSCONSAIF SYSCFG 28 0x1c 32 0 pll0_fbdiv pll0_fbdiv [11:0] read-write sys_syscfg_8 SYS SYSCONSAIF SYSCFG 32 0x20 32 0 pll0_frac pll0_frac [23:0] read-write pll0_gvco_bias pll0_gvco_bias [25:24] read-write pll0_lock pll0_lock [26:26] read-only pll0_pd pll0_pd [27:27] read-write pll0_postdiv1 pll0_postdiv1 [29:28] read-write pll0_postdiv2 pll0_postdiv2 [31:30] read-write sys_syscfg_9 SYS SYSCONSAIF SYSCFG 36 0x24 32 0 pll0_prediv pll0_prediv [5:0] read-write pll0_testen pll0_testen [6:6] read-write pll0_testsel pll0_testsel [8:7] read-write pll1_cpi_bias pll1_cpi_bias [11:9] read-write pll1_cpp_bias pll1_cpp_bias [14:12] read-write pll1_dacpd pll1_dacpd [15:15] read-write pll1_dsmpd pll1_dsmpd [16:16] read-write pll1_fbdiv pll1_fbdiv [28:17] read-write sys_syscfg_10 SYS SYSCONSAIF SYSCFG 40 0x28 32 0 pll1_frac pll1_frac [23:0] read-write pll1_gvco_bias pll1_gvco_bias [25:24] read-write pll1_lock pll1_lock [26:26] read-only pll1_pd pll1_pd [27:27] read-write pll1_postdiv1 pll1_postdiv1 [29:28] read-write pll1_postdiv2 pll1_postdiv2 [31:30] read-write sys_syscfg_11 SYS SYSCONSAIF SYSCFG 44 0x2c 32 0 pll1_prediv pll1_prediv [5:0] read-write pll1_testen pll1_testen [6:6] read-write pll1_testsel pll1_testsel [8:7] read-write pll2_cpi_bias pll2_cpi_bias [11:9] read-write pll2_cpp_bias pll2_cpp_bias [14:12] read-write pll2_dacpd pll2_dacpd [15:15] read-write pll2_dsmpd pll2_dsmpd [16:16] read-write pll2_fbdiv pll2_fbdiv [28:17] read-write sys_syscfg_12 SYS SYSCONSAIF SYSCFG 48 0x30 32 0 pll2_frac pll2_frac [23:0] read-write pll2_gvco_bias pll2_gvco_bias [25:24] read-write pll2_lock pll2_lock [26:26] read-only pll2_pd pll2_pd [27:27] read-write pll2_postdiv1 pll2_postdiv1 [29:28] read-write pll2_postdiv2 pll2_postdiv2 [31:30] read-write sys_syscfg_13 SYS SYSCONSAIF SYSCFG 52 0x34 32 0 pll2_prediv pll2_prediv [5:0] read-write pll2_testen pll2_testen [6:6] read-write pll2_testsel pll2_testsel [8:7] read-write pll_test_mode PLL test mode, only used for PLL BIST through jtag2apb [9:9] read-write audio_i2sdin_sel audio_i2sdin_sel [17:10] read-write noc_bus_clock_gating_off noc_bus_clock_gating_off [18:18] read-write noc_bus_oic_evemon_start_0 noc_bus_oic_evemon_start_0 [19:19] read-write noc_bus_oic_evemon_trigger_0 noc_bus_oic_evemon_trigger_0 [20:20] read-only noc_bus_oic_evemon_start_1 noc_bus_oic_evemon_start_1 [21:21] read-write noc_bus_oic_evemon_trigger_1 noc_bus_oic_evemon_trigger_1 [22:22] read-only noc_bus_oic_evemon_start_2 noc_bus_oic_evemon_start_2 [23:23] read-write noc_bus_oic_evemon_trigger_2 noc_bus_oic_evemon_trigger_2 [24:24] read-only noc_bus_oic_evemon_start_3 noc_bus_oic_evemon_start_3 [25:25] read-write noc_bus_oic_evemon_trigger_3 noc_bus_oic_evemon_trigger_3 [26:26] read-only noc_bus_oic_evemon_start_4 noc_bus_oic_evemon_start_4 [27:27] read-write noc_bus_oic_evemon_trigger_4 noc_bus_oic_evemon_trigger_4 [28:28] read-only noc_bus_oic_evemon_start_5 noc_bus_oic_evemon_start_5 [29:29] read-write noc_bus_oic_evemon_trigger_5 noc_bus_oic_evemon_trigger_5 [30:30] read-only noc_bus_oic_evemon_start_6 noc_bus_oic_evemon_start_6 [31:31] read-write sys_syscfg_14 SYS SYSCONSAIF SYSCFG 56 0x38 32 0 noc_bus_oic_evemon_trigger_6 noc_bus_oic_evemon_trigger_6 [0:0] read-only noc_bus_oic_evemon_start_7 noc_bus_oic_evemon_start_7 [15:15] read-write noc_bus_oic_evemon_trigger_7 noc_bus_oic_evemon_trigger_7 [16:16] read-only noc_bus_oic_evemon_start_8 noc_bus_oic_evemon_start_8 [17:17] read-write noc_bus_oic_evemon_trigger_8 noc_bus_oic_evemon_trigger_8 [18:18] read-only noc_bus_oic_ignore_modifiable_0 noc_bus_oic_ignore_modifiable_0 [5:5] read-write noc_bus_oic_ignore_modifiable_1 noc_bus_oic_ignore_modifiable_1 [6:6] read-write noc_bus_oic_ignore_modifiable_2 noc_bus_oic_ignore_modifiable_2 [7:7] read-write noc_bus_oic_ignore_modifiable_3 noc_bus_oic_ignore_modifiable_3 [8:8] read-write noc_bus_oic_ignore_modifiable_4 noc_bus_oic_ignore_modifiable_4 [9:9] read-write sys_syscfg_15 SYS SYSCONSAIF SYSCFG 60 0x3c 32 0 noc_bus_oic_qch_clock_stop_threshold_0 noc_bus_oic_qch_clock_stop_threshold_0 [31:0] read-write sys_syscfg_16 SYS SYSCONSAIF SYSCFG 64 0x40 32 0 noc_bus_oic_qch_clock_stop_threshold_1 noc_bus_oic_qch_clock_stop_threshold_1 [31:0] read-write sys_syscfg_17 SYS SYSCONSAIF SYSCFG 68 0x44 32 0 noc_bus_oic_qch_clock_stop_threshold_2 noc_bus_oic_qch_clock_stop_threshold_2 [31:0] read-write sys_syscfg_18 SYS SYSCONSAIF SYSCFG 72 0x48 32 0 noc_bus_oic_qch_clock_stop_threshold_3 noc_bus_oic_qch_clock_stop_threshold_3 [31:0] read-write sys_syscfg_19 SYS SYSCONSAIF SYSCFG 76 0x4c 32 0 noc_bus_oic_qch_clock_stop_threshold_4 noc_bus_oic_qch_clock_stop_threshold_4 [31:0] read-write sys_syscfg_20 SYS SYSCONSAIF SYSCFG 80 0x50 32 0 noc_bus_oic_qch_clock_stop_threshold_5 noc_bus_oic_qch_clock_stop_threshold_5 [31:0] read-write sys_syscfg_21 SYS SYSCONSAIF SYSCFG 84 0x54 32 0 noc_bus_oic_qch_clock_stop_threshold_6 noc_bus_oic_qch_clock_stop_threshold_6 [31:0] read-write sys_syscfg_22 SYS SYSCONSAIF SYSCFG 88 0x58 32 0 noc_bus_oic_qch_clock_stop_threshold_7 noc_bus_oic_qch_clock_stop_threshold_7 [31:0] read-write sys_syscfg_23 SYS SYSCONSAIF SYSCFG 92 0x5c 32 0 noc_bus_oic_qch_clock_stop_threshold_8 noc_bus_oic_qch_clock_stop_threshold_8 [31:0] read-write sys_syscfg_24 SYS SYSCONSAIF SYSCFG 96 0x60 32 0 tdm16slot_clkpol tdm16slot_clkpol [0:0] read-only tdm16slot_pcm_ms tdm16slot_pcm_ms [1:1] read-only u0_trace_mtx_in0_0 u0_trace_mtx_in0_0 [6:2] read-write u0_trace_mtx_in1_0 u0_trace_mtx_in1_0 [11:7] read-write u0_trace_mtx_in0_1 u0_trace_mtx_in0_1 [16:12] read-write u0_trace_mtx_in1_1 u0_trace_mtx_in1_1 [21:17] read-write u0_trace_mtx_in0_2 u0_trace_mtx_in0_2 [26:22] read-write u0_trace_mtx_in1_2 u0_trace_mtx_in1_2 [31:27] read-write sys_syscfg_25 SYS SYSCONSAIF SYSCFG 100 0x64 32 0 u0_trace_mtx_scfg_c3_in0_ctl u0_trace_mtx_scfg_c3_in0_ctl [4:0] read-write u0_trace_mtx_scfg_c3_in1_ctl u0_trace_mtx_scfg_c3_in1_ctl [9:5] read-write u0_trace_mtx_scfg_c4_in0_ctl u0_trace_mtx_scfg_c4_in0_ctl [14:10] read-write u0_trace_mtx_scfg_c4_in1_ctl u0_trace_mtx_scfg_c4_in1_ctl [19:15] read-write u0_cease_from_tile_0 u0_cease_from_tile_0 [20:20] read-only u0_cease_from_tile_1 u0_cease_from_tile_1 [21:21] read-only u0_cease_from_tile_2 u0_cease_from_tile_2 [22:22] read-only u0_cease_from_tile_3 u0_cease_from_tile_3 [23:23] read-only u0_cease_from_tile_4 u0_cease_from_tile_4 [24:24] read-only u0_halt_from_tile_0 u0_halt_from_tile_0 [25:25] read-only u0_halt_from_tile_1 u0_halt_from_tile_1 [26:26] read-only u0_halt_from_tile_2 u0_halt_from_tile_2 [27:27] read-only u0_halt_from_tile_3 u0_halt_from_tile_3 [28:28] read-only u0_halt_from_tile_4 u0_halt_from_tile_4 [29:29] read-only sys_syscfg_26 SYS SYSCONSAIF SYSCFG 26 0x68 32 0 reset_vector_1_0 U0 U74MC Reset Vector 1: 0 [0:0] read-write reset_vector_1_1 U0 U74MC Reset Vector 1: 1 [1:1] read-write reset_vector_1_2 U0 U74MC Reset Vector 1: 2 [2:2] read-write reset_vector_1_3 U0 U74MC Reset Vector 1: 3 [3:3] read-write reset_vector_1_4 U0 U74MC Reset Vector 1: 4 [4:4] read-write reset_vector_1_5 U0 U74MC Reset Vector 1: 5 [5:5] read-write reset_vector_1_6 U0 U74MC Reset Vector 1: 6 [6:6] read-write reset_vector_1_7 U0 U74MC Reset Vector 1: 7 [7:7] read-write reset_vector_1_8 U0 U74MC Reset Vector 1: 8 [8:8] read-write reset_vector_1_9 U0 U74MC Reset Vector 1: 9 [9:9] read-write reset_vector_1_10 U0 U74MC Reset Vector 1: 10 [10:10] read-write reset_vector_1_11 U0 U74MC Reset Vector 1: 11 [11:11] read-write reset_vector_1_12 U0 U74MC Reset Vector 1: 12 [12:12] read-write reset_vector_1_13 U0 U74MC Reset Vector 1: 13 [13:13] read-write reset_vector_1_14 U0 U74MC Reset Vector 1: 14 [14:14] read-write reset_vector_1_15 U0 U74MC Reset Vector 1: 15 [15:15] read-write reset_vector_1_16 U0 U74MC Reset Vector 1: 16 [16:16] read-write reset_vector_1_17 U0 U74MC Reset Vector 1: 17 [17:17] read-write reset_vector_1_18 U0 U74MC Reset Vector 1: 18 [18:18] read-write reset_vector_1_19 U0 U74MC Reset Vector 1: 19 [19:19] read-write reset_vector_1_20 U0 U74MC Reset Vector 1: 20 [20:20] read-write reset_vector_1_21 U0 U74MC Reset Vector 1: 21 [21:21] read-write reset_vector_1_22 U0 U74MC Reset Vector 1: 22 [22:22] read-write reset_vector_1_23 U0 U74MC Reset Vector 1: 23 [23:23] read-write reset_vector_1_24 U0 U74MC Reset Vector 1: 24 [24:24] read-write reset_vector_1_25 U0 U74MC Reset Vector 1: 25 [25:25] read-write reset_vector_1_26 U0 U74MC Reset Vector 1: 26 [26:26] read-write reset_vector_1_27 U0 U74MC Reset Vector 1: 27 [27:27] read-write reset_vector_1_28 U0 U74MC Reset Vector 1: 28 [28:28] read-write reset_vector_1_29 U0 U74MC Reset Vector 1: 29 [29:29] read-write reset_vector_1_30 U0 U74MC Reset Vector 1: 30 [30:30] read-write reset_vector_1_31 U0 U74MC Reset Vector 1: 31 [31:31] read-write sys_syscfg_27 SYS SYSCONSAIF SYSCFG 27 0x6c 32 0 reset_vector_1_32 U0 U74MC Reset Vector 1: 32 [0:0] read-write reset_vector_1_33 U0 U74MC Reset Vector 1: 33 [1:1] read-write reset_vector_1_34 U0 U74MC Reset Vector 1: 34 [2:2] read-write reset_vector_1_35 U0 U74MC Reset Vector 1: 35 [3:3] read-write sys_syscfg_28 SYS SYSCONSAIF SYSCFG 28 0x70 32 0 reset_vector_2_0 U0 U74MC Reset Vector 2: 0 [0:0] read-write reset_vector_2_1 U0 U74MC Reset Vector 2: 1 [1:1] read-write reset_vector_2_2 U0 U74MC Reset Vector 2: 2 [2:2] read-write reset_vector_2_3 U0 U74MC Reset Vector 2: 3 [3:3] read-write reset_vector_2_4 U0 U74MC Reset Vector 2: 4 [4:4] read-write reset_vector_2_5 U0 U74MC Reset Vector 2: 5 [5:5] read-write reset_vector_2_6 U0 U74MC Reset Vector 2: 6 [6:6] read-write reset_vector_2_7 U0 U74MC Reset Vector 2: 7 [7:7] read-write reset_vector_2_8 U0 U74MC Reset Vector 2: 8 [8:8] read-write reset_vector_2_9 U0 U74MC Reset Vector 2: 9 [9:9] read-write reset_vector_2_10 U0 U74MC Reset Vector 2: 10 [10:10] read-write reset_vector_2_11 U0 U74MC Reset Vector 2: 11 [11:11] read-write reset_vector_2_12 U0 U74MC Reset Vector 2: 12 [12:12] read-write reset_vector_2_13 U0 U74MC Reset Vector 2: 13 [13:13] read-write reset_vector_2_14 U0 U74MC Reset Vector 2: 14 [14:14] read-write reset_vector_2_15 U0 U74MC Reset Vector 2: 15 [15:15] read-write reset_vector_2_16 U0 U74MC Reset Vector 2: 16 [16:16] read-write reset_vector_2_17 U0 U74MC Reset Vector 2: 17 [17:17] read-write reset_vector_2_18 U0 U74MC Reset Vector 2: 18 [18:18] read-write reset_vector_2_19 U0 U74MC Reset Vector 2: 19 [19:19] read-write reset_vector_2_20 U0 U74MC Reset Vector 2: 20 [20:20] read-write reset_vector_2_21 U0 U74MC Reset Vector 2: 21 [21:21] read-write reset_vector_2_22 U0 U74MC Reset Vector 2: 22 [22:22] read-write reset_vector_2_23 U0 U74MC Reset Vector 2: 23 [23:23] read-write reset_vector_2_24 U0 U74MC Reset Vector 2: 24 [24:24] read-write reset_vector_2_25 U0 U74MC Reset Vector 2: 25 [25:25] read-write reset_vector_2_26 U0 U74MC Reset Vector 2: 26 [26:26] read-write reset_vector_2_27 U0 U74MC Reset Vector 2: 27 [27:27] read-write reset_vector_2_28 U0 U74MC Reset Vector 2: 28 [28:28] read-write reset_vector_2_29 U0 U74MC Reset Vector 2: 29 [29:29] read-write reset_vector_2_30 U0 U74MC Reset Vector 2: 30 [30:30] read-write reset_vector_2_31 U0 U74MC Reset Vector 2: 31 [31:31] read-write sys_syscfg_29 SYS SYSCONSAIF SYSCFG 29 0x74 32 0 reset_vector_2_32 U0 U74MC Reset Vector 2: 32 [0:0] read-write reset_vector_2_33 U0 U74MC Reset Vector 2: 33 [1:1] read-write reset_vector_2_34 U0 U74MC Reset Vector 2: 34 [2:2] read-write reset_vector_2_35 U0 U74MC Reset Vector 2: 35 [3:3] read-write sys_syscfg_30 SYS SYSCONSAIF SYSCFG 30 0x78 32 0 reset_vector_3_0 U0 U74MC Reset Vector 3: 0 [0:0] read-write reset_vector_3_1 U0 U74MC Reset Vector 3: 1 [1:1] read-write reset_vector_3_2 U0 U74MC Reset Vector 3: 2 [2:2] read-write reset_vector_3_3 U0 U74MC Reset Vector 3: 3 [3:3] read-write reset_vector_3_4 U0 U74MC Reset Vector 3: 4 [4:4] read-write reset_vector_3_5 U0 U74MC Reset Vector 3: 5 [5:5] read-write reset_vector_3_6 U0 U74MC Reset Vector 3: 6 [6:6] read-write reset_vector_3_7 U0 U74MC Reset Vector 3: 7 [7:7] read-write reset_vector_3_8 U0 U74MC Reset Vector 3: 8 [8:8] read-write reset_vector_3_9 U0 U74MC Reset Vector 3: 9 [9:9] read-write reset_vector_3_10 U0 U74MC Reset Vector 3: 10 [10:10] read-write reset_vector_3_11 U0 U74MC Reset Vector 3: 11 [11:11] read-write reset_vector_3_12 U0 U74MC Reset Vector 3: 12 [12:12] read-write reset_vector_3_13 U0 U74MC Reset Vector 3: 13 [13:13] read-write reset_vector_3_14 U0 U74MC Reset Vector 3: 14 [14:14] read-write reset_vector_3_15 U0 U74MC Reset Vector 3: 15 [15:15] read-write reset_vector_3_16 U0 U74MC Reset Vector 3: 16 [16:16] read-write reset_vector_3_17 U0 U74MC Reset Vector 3: 17 [17:17] read-write reset_vector_3_18 U0 U74MC Reset Vector 3: 18 [18:18] read-write reset_vector_3_19 U0 U74MC Reset Vector 3: 19 [19:19] read-write reset_vector_3_20 U0 U74MC Reset Vector 3: 20 [20:20] read-write reset_vector_3_21 U0 U74MC Reset Vector 3: 21 [21:21] read-write reset_vector_3_22 U0 U74MC Reset Vector 3: 22 [22:22] read-write reset_vector_3_23 U0 U74MC Reset Vector 3: 23 [23:23] read-write reset_vector_3_24 U0 U74MC Reset Vector 3: 24 [24:24] read-write reset_vector_3_25 U0 U74MC Reset Vector 3: 25 [25:25] read-write reset_vector_3_26 U0 U74MC Reset Vector 3: 26 [26:26] read-write reset_vector_3_27 U0 U74MC Reset Vector 3: 27 [27:27] read-write reset_vector_3_28 U0 U74MC Reset Vector 3: 28 [28:28] read-write reset_vector_3_29 U0 U74MC Reset Vector 3: 29 [29:29] read-write reset_vector_3_30 U0 U74MC Reset Vector 3: 30 [30:30] read-write reset_vector_3_31 U0 U74MC Reset Vector 3: 31 [31:31] read-write sys_syscfg_31 SYS SYSCONSAIF SYSCFG 31 0x7c 32 0 reset_vector_3_32 U0 U74MC Reset Vector 3: 32 [0:0] read-write reset_vector_3_33 U0 U74MC Reset Vector 3: 33 [1:1] read-write reset_vector_3_34 U0 U74MC Reset Vector 3: 34 [2:2] read-write reset_vector_3_35 U0 U74MC Reset Vector 3: 35 [3:3] read-write sys_syscfg_32 SYS SYSCONSAIF SYSCFG 32 0x80 32 0 reset_vector_4_0 U0 U74MC Reset Vector 4: 0 [0:0] read-write reset_vector_4_1 U0 U74MC Reset Vector 4: 1 [1:1] read-write reset_vector_4_2 U0 U74MC Reset Vector 4: 2 [2:2] read-write reset_vector_4_3 U0 U74MC Reset Vector 4: 3 [3:3] read-write reset_vector_4_4 U0 U74MC Reset Vector 4: 4 [4:4] read-write reset_vector_4_5 U0 U74MC Reset Vector 4: 5 [5:5] read-write reset_vector_4_6 U0 U74MC Reset Vector 4: 6 [6:6] read-write reset_vector_4_7 U0 U74MC Reset Vector 4: 7 [7:7] read-write reset_vector_4_8 U0 U74MC Reset Vector 4: 8 [8:8] read-write reset_vector_4_9 U0 U74MC Reset Vector 4: 9 [9:9] read-write reset_vector_4_10 U0 U74MC Reset Vector 4: 10 [10:10] read-write reset_vector_4_11 U0 U74MC Reset Vector 4: 11 [11:11] read-write reset_vector_4_12 U0 U74MC Reset Vector 4: 12 [12:12] read-write reset_vector_4_13 U0 U74MC Reset Vector 4: 13 [13:13] read-write reset_vector_4_14 U0 U74MC Reset Vector 4: 14 [14:14] read-write reset_vector_4_15 U0 U74MC Reset Vector 4: 15 [15:15] read-write reset_vector_4_16 U0 U74MC Reset Vector 4: 16 [16:16] read-write reset_vector_4_17 U0 U74MC Reset Vector 4: 17 [17:17] read-write reset_vector_4_18 U0 U74MC Reset Vector 4: 18 [18:18] read-write reset_vector_4_19 U0 U74MC Reset Vector 4: 19 [19:19] read-write reset_vector_4_20 U0 U74MC Reset Vector 4: 20 [20:20] read-write reset_vector_4_21 U0 U74MC Reset Vector 4: 21 [21:21] read-write reset_vector_4_22 U0 U74MC Reset Vector 4: 22 [22:22] read-write reset_vector_4_23 U0 U74MC Reset Vector 4: 23 [23:23] read-write reset_vector_4_24 U0 U74MC Reset Vector 4: 24 [24:24] read-write reset_vector_4_25 U0 U74MC Reset Vector 4: 25 [25:25] read-write reset_vector_4_26 U0 U74MC Reset Vector 4: 26 [26:26] read-write reset_vector_4_27 U0 U74MC Reset Vector 4: 27 [27:27] read-write reset_vector_4_28 U0 U74MC Reset Vector 4: 28 [28:28] read-write reset_vector_4_29 U0 U74MC Reset Vector 4: 29 [29:29] read-write reset_vector_4_30 U0 U74MC Reset Vector 4: 30 [30:30] read-write reset_vector_4_31 U0 U74MC Reset Vector 4: 31 [31:31] read-write sys_syscfg_33 SYS SYSCONSAIF SYSCFG 132 0x84 32 0 reset_vector_4_32 U0 U74MC Reset Vector 4: 32 [0:0] read-write reset_vector_4_33 U0 U74MC Reset Vector 4: 33 [1:1] read-write reset_vector_4_34 U0 U74MC Reset Vector 4: 34 [2:2] read-write reset_vector_4_35 U0 U74MC Reset Vector 4: 35 [3:3] read-write u0_suppress_fetch_1 u0_suppress_fetch_1 [4:4] read-write u0_suppress_fetch_2 u0_suppress_fetch_2 [5:5] read-write u0_suppress_fetch_3 u0_suppress_fetch_3 [6:6] read-write u0_suppress_fetch_4 u0_suppress_fetch_4 [7:7] read-write u0_wfi_from_tile_0 u0_wfi_from_tile_0 [8:8] read-write u0_wfi_from_tile_1 u0_wfi_from_tile_1 [9:9] read-write u0_wfi_from_tile_2 u0_wfi_from_tile_2 [10:10] read-write u0_wfi_from_tile_3 u0_wfi_from_tile_3 [11:11] read-write u0_wfi_from_tile_4 u0_wfi_from_tile_4 [12:12] read-write u0_vdec_intsram_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [13:13] read-write u0_vdec_intsram_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [14:14] read-write u0_vdec_intsram_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [16:15] read-write u0_vdec_intsram_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [18:17] read-write u0_vdec_intsram_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [20:19] read-write u0_vdec_intsram_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [22:21] read-write u0_vdec_intsram_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [23:23] read-write u0_vdec_intsram_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [24:24] read-write sys_syscfg_34 SYS SYSCONSAIF SYSCFG 136 0x88 32 0 u0_venc_intsram_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [0:0] read-write u0_venc_intsram_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [1:1] read-write u0_venc_intsram_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [3:2] read-write u0_venc_intsram_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [5:4] read-write u0_venc_intsram_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [7:6] read-write u0_venc_intsram_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write u0_venc_intsram_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write u0_venc_intsram_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write wave420l_ipu_current_buffer This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter. [14:12] read-write wave420l_ipu_end_of_row This signal is flipped every time when the IPU completes writing a row. [15:15] read-write wave420l_ipu_new_frame This signal is flipped every time when the IPU completes writing a new frame. [16:16] read-write wave420l_vpu_idle VPU monitoring signal. This signal gives out an opposite value of VPU_BUSY register. [17:17] read-only can_ctrl_fd_enable_1 can_ctrl_fd_enable_1 [18:18] read-write can_ctrl_host_ecc_disable_1 can_ctrl_host_ecc_disable_1 [19:19] read-write sys_syscfg_35 SYS SYSCONSAIF SYSCFG 140 0x8c 32 0 can_ctrl_host_if_1 can_ctrl_host_if_1 [18:0] read-only u1_gmac5_axi64_scfg_ram_cfg_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [19:19] read-write u1_gmac5_axi64_scfg_ram_cfg_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [20:20] read-write u1_gmac5_axi64_scfg_ram_cfg_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [22:21] read-write u1_gmac5_axi64_scfg_ram_cfg_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [24:23] read-write u1_gmac5_axi64_scfg_ram_cfg_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [26:25] read-write u1_gmac5_axi64_scfg_ram_cfg_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [28:27] read-write u1_gmac5_axi64_scfg_ram_cfg_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [29:29] read-write u1_gmac5_axi64_scfg_ram_cfg_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [30:30] read-write sys_syscfg_36 SYS SYSCONSAIF SYSCFG 144 0x90 32 0 gmac5_axi64_mac_speed gmac5_axi64_mac_speed [1:0] read-only gmac5_axi64_phy_intf_sel Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. | Values: 0x0:(GMII or MII), 0x01:RGMII, 0x2:SGMII, 0x3:TBI, 0x4:RMII, 0x5:RTBI, 0x6:SMII, 0x7:REVMII [4:2] read-write sys_syscfg_37 SYS SYSCONSAIF SYSCFG 148 0x94 32 0 gmac5_axi64_ptp_timestamp_0_31 gmac5_axi64_ptp_timestamp_0_31 [31:0] read-only sys_syscfg_38 SYS SYSCONSAIF SYSCFG 152 0x98 32 0 gmac5_axi64_ptp_timestamp_32_63 gmac5_axi64_ptp_timestamp_32_63 [31:0] read-only sys_syscfg_39 SYS SYSCONSAIF SYSCFG 156 0x9c 32 0 i2c_ic_en_1 I2C interface enable. [0:0] read-only sdio_data_strobe_phase_ctrl_1 Data strobe delay chain select. [5:1] read-write sdio_hbig_endian_1 AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface [6:6] read-write sdio_m_hbig_endian_1 AHB bus interface endianness: 1: Big-endian AHB bus interface, 0: Little-endian AHB bus interface [7:7] read-write reset_ctrl_clr_reset_status_1 reset_ctrl_clr_reset_status_1 [8:8] read-write reset_ctrl_pll_timecnt_finish_1 reset_ctrl_pll_timecnt_finish_1 [9:9] read-only reset_ctrl_rstn_sw_1 reset_ctrl_rstn_sw_1 [10:10] read-write reset_ctrl_sys_reset_status_1 reset_ctrl_sys_reset_status_1 [14:11] read-only i2c_ic_en_2 I2C interface enable. [15:15] read-only i2c_ic_en_3 I2C interface enable. [16:16] read-only i2c_ic_en_4 I2C interface enable. [17:17] read-only i2c_ic_en_5 I2C interface enable. [18:18] read-only i2c_ic_en_6 I2C interface enable. [19:19] read-only syscon_1 From syscon, peripheral generator 0x13030000 0 0x1000 registers simple_mfd_0 From simple-mfd, peripheral generator 0x13030000 0 0x1000 registers sys_pinctrl From starfive,jh7110-sys-pinctrl, peripheral generator 0x13040000 0 0x10000 registers gpo_doen_0 SYS IOMUX CFG SAIF SYSCFG FMUX 0 DOEN 0x0 32 134283521 doen_0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_1 SYS IOMUX CFG SAIF SYSCFG FMUX 1 DOEN 0x4 32 65537 doen_4 The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_5 The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_6 The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_7 The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_2 SYS IOMUX CFG SAIF SYSCFG FMUX 2 DOEN 0x8 32 117506304 doen_8 The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_9 The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_10 The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_11 The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_3 SYS IOMUX CFG SAIF SYSCFG FMUX 3 DOEN 0xc 32 257 doen_12 The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_13 The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_14 The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_15 The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_4 SYS IOMUX CFG SAIF SYSCFG FMUX 4 DOEN 0x10 32 16777216 doen_16 The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_17 The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_18 The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_19 The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_5 SYS IOMUX CFG SAIF SYSCFG FMUX 5 DOEN 0x14 32 0 doen_20 The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_21 The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_22 The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_23 The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_6 SYS IOMUX CFG SAIF SYSCFG FMUX 6 DOEN 0x18 32 0 doen_24 The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_25 The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_26 The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_27 The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_7 SYS IOMUX CFG SAIF SYSCFG FMUX 7 DOEN 0x1c 32 0 doen_28 The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_29 The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_30 The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_31 The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_8 SYS IOMUX CFG SAIF SYSCFG FMUX 8 DOEN 0x20 32 0 doen_32 The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_33 The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_34 The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_35 The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_9 SYS IOMUX CFG SAIF SYSCFG FMUX 9 DOEN 0x24 32 589432325 doen_36 The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_37 The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_38 The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_39 The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_10 SYS IOMUX CFG SAIF SYSCFG FMUX 10 DOEN 0x28 32 16777217 doen_40 The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_41 The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_42 The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_43 The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_11 SYS IOMUX CFG SAIF SYSCFG FMUX 11 DOEN 0x2c 32 16777217 doen_44 The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_45 The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_46 The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_47 The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_12 SYS IOMUX CFG SAIF SYSCFG FMUX 12 DOEN 0x30 32 234949901 doen_48 The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_49 The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_50 The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_51 The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_13 SYS IOMUX CFG SAIF SYSCFG FMUX 13 DOEN 0x34 32 486611996 doen_52 The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_53 The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_54 The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_55 The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_14 SYS IOMUX CFG SAIF SYSCFG FMUX 14 DOEN 0x38 32 620831780 doen_56 The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_57 The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_58 The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_59 The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_doen_15 SYS IOMUX CFG SAIF SYSCFG FMUX 15 DOEN 0x3c 32 687941672 doen_60 The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write doen_61 The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write doen_62 The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write doen_63 The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write gpo_dout_0_3 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT 0x40 32 369098752 dout_0 The selected output signal for GPIO0. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_1 The selected output signal for GPIO1. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_2 The selected output signal for GPIO2. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_3 The selected output signal for GPIO3. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_4_7 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT 0x44 32 5120 dout_4 The selected output signal for GPIO4. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_5 The selected output signal for GPIO5. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_6 The selected output signal for GPIO6. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_7 The selected output signal for GPIO7. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_8_11 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT 0x48 32 352321536 dout_8 The selected output signal for GPIO8. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_9 The selected output signal for GPIO9. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_10 The selected output signal for GPIO10. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_11 The selected output signal for GPIO11. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_12_15 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT 0x4c 32 0 dout_12 The selected output signal for GPIO12. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_13 The selected output signal for GPIO13. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_14 The selected output signal for GPIO14. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_15 The selected output signal for GPIO15. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_16_19 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT 0x50 32 536870912 dout_16 The selected output signal for GPIO16. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_17 The selected output signal for GPIO17. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_18 The selected output signal for GPIO18. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_19 The selected output signal for GPIO19. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_20_23 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT 0x54 32 5570560 dout_20 The selected output signal for GPIO20. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_21 The selected output signal for GPIO21. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_22 The selected output signal for GPIO22. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_23 The selected output signal for GPIO23. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_24_27 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT 0x58 32 0 dout_24 The selected output signal for GPIO24. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_25 The selected output signal for GPIO25. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_26 The selected output signal for GPIO26. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_27 The selected output signal for GPIO27. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_28_31 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT 0x5c 32 0 dout_28 The selected output signal for GPIO28. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_29 The selected output signal for GPIO29. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_30 The selected output signal for GPIO30. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_31 The selected output signal for GPIO31. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_32_35 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT 0x60 32 218103808 dout_32 The selected output signal for GPIO32. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_33 The selected output signal for GPIO33. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_34 The selected output signal for GPIO34. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_35 The selected output signal for GPIO35. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_36_39 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT 0x64 32 1414729486 dout_36 The selected output signal for GPIO36. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_37 The selected output signal for GPIO37. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_38 The selected output signal for GPIO38. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_39 The selected output signal for GPIO39. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_40_43 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT 0x68 32 5132032 dout_40 The selected output signal for GPIO40. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_41 The selected output signal for GPIO41. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_42 The selected output signal for GPIO42. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_43 The selected output signal for GPIO43. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_44_47 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT 0x6c 32 5987328 dout_44 The selected output signal for GPIO44. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_45 The selected output signal for GPIO45. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_46 The selected output signal for GPIO46. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_47 The selected output signal for GPIO47. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_48_51 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT 0x70 32 536878623 dout_48 The selected output signal for GPIO48. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_49 The selected output signal for GPIO49. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_50 The selected output signal for GPIO50. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_51 The selected output signal for GPIO51. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_52_55 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT 0x74 32 1258309962 dout_52 The selected output signal for GPIO52. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_53 The selected output signal for GPIO53. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_54 The selected output signal for GPIO54. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_55 The selected output signal for GPIO55. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_56_59 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT 0x78 32 1476417111 dout_56 The selected output signal for GPIO56. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_57 The selected output signal for GPIO57. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_58 The selected output signal for GPIO58. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_59 The selected output signal for GPIO59. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpo_dout_60_63 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT 0x7c 32 1593859422 dout_60 The selected output signal for GPIO60. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [6:0] read-write dout_61 The selected output signal for GPIO61. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [14:8] read-write dout_62 The selected output signal for GPIO62. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [22:16] read-write dout_63 The selected output signal for GPIO63. The register value indicates the selected GPIO output index signal index from GPIO output signal list 0-107. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [30:24] read-write gpi_0 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 0 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x80 32 0 wave511_uart_rxsin The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write can_rxd_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write usb_over_current The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write spdif_spdi_fi The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_1 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 4 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x84 32 2 jtag_trstn The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write hdmi_cec_sda The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write hdmi_ddc_scl The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write hdmi_ddc_sda The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_2 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 8 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x88 32 2565632 hdmi_hpd The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write i2c_clk_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write i2c_data_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write sdio_detect_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_3 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 12 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x8c 32 185073664 sdio_int_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write sdio_write_prt_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write uart_sin_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write hifi4_jtck_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_4 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 16 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x90 32 68095500 hifi4_jtdi The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write hifi4_jtms The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write hifi4_jtrstn The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write jtag_tdi The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_5 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 20 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x94 32 6 jtag_tms The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write pdm_dmic_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write pdm_dmic_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write audio_i2srx_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_6 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 24 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x98 32 842203136 audio_i2srx_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write audio_i2srx_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write spi_clkin_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write spi_fssin_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_7 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 28 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x9c 32 820 spi_rxd_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write jtag_tck The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write mclk The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write i2srx_bclk_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_8 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 32 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xa0 32 0 i2srx_lrck_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write i2stx_bclk_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write i2stx_lrck_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write tdm_clk_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_9 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 36 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xa4 32 0 pcm_rxd_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write pcm_synon_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write can_rxd_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write i2c_clk_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_10 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 40 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xa8 32 0 i2c_data_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write sdio_detect_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write sdio_int_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write sdio_write_prt_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_11 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 44 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xac 32 0 sdio_ccmd_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write sdio_cdata_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write sdio_cdata_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write sdio_cdata_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_12 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 48 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xb0 32 0 sdio_cdata_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write sdio_cdata_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write sdio_cdata_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write sdio_cdata_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_13 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 52 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xb4 32 0 sdio_cdata_7 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write sdio_data_strobe The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write uart_cts_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write uart_sin_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_14 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 56 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xb8 32 3683895 spi_clkin_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write spi_fssin_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write spi_rxd_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write i2c_clk_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_15 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 60 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xbc 32 2764032 i2c_data_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write uart_cts_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write uart_sin_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write spi_clkin_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_16 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 64 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xc0 32 690487296 spi_fssin_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write spi_rxd_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write i2c_clk_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write i2c_data_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_17 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 68 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xc4 32 1010449173 uart_sin_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write spi_clkin_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write spi_fssin_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write spi_rxd_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_18 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 72 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xc8 32 774963200 i2c_clk_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write i2c_data_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write uart_cts_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write uart_sin_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_19 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 76 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xcc 32 4210239 spi_clkin_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write spi_fssin_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write spi_rxd_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write i2c_clk_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_20 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 80 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xd0 32 0 i2c_data_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write uart_cts_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write uart_sin_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write spi_clkin_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_21 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 84 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xd4 32 0 spi_fssin_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write spi_rxd_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write i2c_clk_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write i2c_data_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write gpi_22 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI 88 - The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0xd8 32 0 spi_clkin_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write spi_fssin_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write spi_rxd_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write ioirq_0 Enable GPIO IRQ function 0xdc 32 0 gpen_0 1: Enable, 0: Disable [0:0] read-write ioirq_1 SYS IOMUX CFGSAIF SYSCFG IOIRQ 224: GPIO Interrupt Edge Trigger Selector 0xe0 32 0 is_0 1: Edge trigger, 0: Level trigger [31:0] read-write ioirq_2 SYS IOMUX CFGSAIF SYSCFG IOIRQ 228: GPIO Interrupt Edge Trigger Selector 0xe4 32 0 is_1 1: Edge trigger, 0: Level trigger [31:0] read-write ioirq_3 SYS IOMUX CFGSAIF SYSCFG IOIRQ 232: GPIO Interrupt Clear 0xe8 32 0 ic_0 1: Do not clear the register, 0: Clear the register [31:0] read-write ioirq_4 SYS IOMUX CFGSAIF SYSCFG IOIRQ 236: GPIO Interrupt Clear 0xec 32 0 ic_1 1: Do not clear the register, 0: Clear the register [31:0] read-write ioirq_5 SYS IOMUX CFGSAIF SYSCFG IOIRQ 240: GPIO Interrupt Both Edge Trigger Selector 0xf0 32 0 ibe_0 1: Trigger on both edges, 0: Trigger on a single edge [31:0] read-write ioirq_6 SYS IOMUX CFGSAIF SYSCFG IOIRQ 244: GPIO Interrupt Both Edge Trigger Selector 0xf4 32 0 ibe_1 1: Trigger on both edges, 0: Trigger on a single edge [31:0] read-write ioirq_7 SYS IOMUX CFGSAIF SYSCFG IOIRQ 248: GPIO Interrupt Edge Value 0xf8 32 0 iev_0 1: Positive/Low, 0: Negative/High [31:0] read-write ioirq_8 SYS IOMUX CFGSAIF SYSCFG IOIRQ 252: GPIO Interrupt Edge Value 0xfc 32 0 iev_1 1: Positive/Low, 0: Negative/High [31:0] read-write ioirq_9 SYS IOMUX CFGSAIF SYSCFG IOIRQ 256: GPIO Interrupt Edge Mask Selector 0x100 32 0 ie_0 1: Unmask, 0: Mask [31:0] read-write ioirq_10 SYS IOMUX CFGSAIF SYSCFG IOIRQ 260: GPIO Interrupt Edge Mask Selector 0x104 32 0 ie_1 1: Unmask, 0: Mask [31:0] read-write ioirq_11 SYS IOMUX CFGSAIF SYSCFG IOIRQ 264: GPIO Register Interrupt Status 0x108 32 0 ris_0 Status of the edge trigger. The register can be cleared by writing gpio ic [31:0] read-only ioirq_12 SYS IOMUX CFGSAIF SYSCFG IOIRQ 268: GPIO Register Interrupt Status 0x10c 32 0 ris_1 Status of the edge trigger. The register can be cleared by writing gpio ic [31:0] read-only ioirq_13 SYS IOMUX CFGSAIF SYSCFG IOIRQ 272: GPIO Masked Interrupt Status 0x110 32 0 mis_0 The masked GPIO IRQ status [31:0] read-only ioirq_14 SYS IOMUX CFGSAIF SYSCFG IOIRQ 276: GPIO Masked Interrupt Status 0x114 32 0 mis_1 The masked GPIO IRQ status [31:0] read-only ioirq_15 SYS IOMUX CFGSAIF SYSCFG IOIRQ 280: GPIO Synchronization Status 0x118 32 0 in_sync2_0 Status of the gpio_in after synchronization [31:0] read-only ioirq_16 SYS IOMUX CFGSAIF SYSCFG IOIRQ 284: GPIO Synchronization Status 0x11c 32 0 in_sync2_1 Status of the gpio_in after synchronization [31:0] read-only gpio_0 SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO_0 0x120 32 17 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_1 SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO_1 0x124 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_2 SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO_2 0x128 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_3 SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO_3 0x12c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_4 SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO_4 0x130 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_5 SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO_5 0x134 32 0 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_6 SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO_6 0x138 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_7 SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO_7 0x13c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_8 SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO_8 0x140 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_9 SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO_9 0x144 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_10 SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO_10 0x148 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_11 SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO_11 0x14c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_12 SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO_12 0x150 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_13 SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO_13 0x154 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_14 SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO_14 0x158 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_15 SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO_15 0x15c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_16 SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO_16 0x160 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_17 SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO_17 0x164 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_18 SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO_18 0x168 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_19 SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO_19 0x16c 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_20 SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO_20 0x170 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_21 SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO_21 0x174 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_22 SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO_22 0x178 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_23 SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO_23 0x17c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_24 SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO_24 0x180 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_25 SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO_25 0x184 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_26 SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO_26 0x188 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_27 SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO_27 0x18c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_28 SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO_28 0x190 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_29 SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO_29 0x194 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_30 SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO_30 0x198 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_31 SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO_31 0x19c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_32 SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO_32 0x1a0 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_33 SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO_33 0x1a4 32 0 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_34 SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO_34 0x1a8 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_35 SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO_35 0x1ac 32 17 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_36 SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO_36 0x1b0 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_37 SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO_37 0x1b4 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_38 SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO_38 0x1b8 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_39 SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO_39 0x1bc 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_40 SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO_40 0x1c0 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_41 SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO_41 0x1c4 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_42 SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO_42 0x1c8 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_43 SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO_43 0x1cc 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_44 SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO_44 0x1d0 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_45 SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO_45 0x1d4 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_46 SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO_46 0x1d8 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_47 SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO_47 0x1dc 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_48 SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO_48 0x1e0 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_49 SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO_49 0x1e4 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_50 SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO_50 0x1e8 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_51 SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO_51 0x1ec 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_52 SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO_52 0x1f0 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_53 SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO_53 0x1f4 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_54 SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO_54 0x1f8 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_55 SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO_55 0x1fc 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_56 SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO_56 0x200 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_57 SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO_57 0x204 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_58 SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO_58 0x208 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_59 SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO_59 0x20c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_60 SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO_60 0x210 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_61 SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO_61 0x214 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_62 SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO_62 0x218 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gpio_63 SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO_63 0x21c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_clk SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK 0x220 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_cmd SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD 0x224 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_0 SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA_0 0x228 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_1 SYS IOMUX CFG SAIF SYSCFG PADCFG 556: SD0_DATA_1 0x22c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_2 SYS IOMUX CFG SAIF SYSCFG PADCFG 560: SD0_DATA_2 0x230 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_3 SYS IOMUX CFG SAIF SYSCFG PADCFG 564: SD0_DATA_3 0x234 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_4 SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA_4 0x238 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_5 SYS IOMUX CFG SAIF SYSCFG PADCFG 572: SD0_DATA_5 0x23c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_6 SYS IOMUX CFG SAIF SYSCFG PADCFG 576: SD0_DATA_6 0x240 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_data_7 SYS IOMUX CFG SAIF SYSCFG PADCFG 580: SD0_DATA_7 0x244 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write sd0_strb SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB 0x248 32 0 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write gmac1_mdc GPIO GMAC1 MDC Pad Configuration 0x24c 32 2 cfg cfg [1:0] read-write gmac1_mdio GPIO GMAC1 MDIO Pad Configuration 0x250 32 2 cfg cfg [1:0] read-write gmac1_rxd_0 GPIO GMAC1 RXD_0 Pad Configuration 0x254 32 2 cfg cfg [1:0] read-write gmac1_rxd_1 GPIO GMAC1 RXD_1 Pad Configuration 0x258 32 2 cfg cfg [1:0] read-write gmac1_rxd_2 GPIO GMAC1 RXD_2 Pad Configuration 0x25c 32 2 cfg cfg [1:0] read-write gmac1_rxd_3 GPIO GMAC1 RXD_3 Pad Configuration 0x260 32 2 cfg cfg [1:0] read-write gmac1_rxdv GPIO GMAC1 RXDV Pad Configuration 0x264 32 2 cfg cfg [1:0] read-write gmac1_rxc GPIO GMAC1 RXC Pad Configuration 0x268 32 2 cfg cfg [1:0] read-write gmac1_txd_0 GPIO GMAC1 TXD_0 Pad Configuration 0x26c 32 2 cfg cfg [1:0] read-write gmac1_txd_1 GPIO GMAC1 TXD_1 Pad Configuration 0x270 32 2 cfg cfg [1:0] read-write gmac1_txd_2 GPIO GMAC1 TXD_2 Pad Configuration 0x274 32 2 cfg cfg [1:0] read-write gmac1_txd_3 GPIO GMAC1 TXD_3 Pad Configuration 0x278 32 2 cfg cfg [1:0] read-write gmac1_txen GPIO GMAC1 TXEN Pad Configuration 0x27c 32 2 cfg cfg [1:0] read-write gmac1_txc GPIO GMAC1 TXC Pad Configuration 0x280 32 2 cfg cfg [1:0] read-write qspi_sclk SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK 0x284 32 8 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write qspi_csn_0 SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN_0 0x288 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write qspi_data_0 SYS IOMUX CFG SAIF SYSCFG PADCFG 652: QSPI_DATA_0 0x28c 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write qspi_data_1 SYS IOMUX CFG SAIF SYSCFG PADCFG 656: QSPI_DATA_1 0x290 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write qspi_data_2 SYS IOMUX CFG SAIF SYSCFG PADCFG 660: QSPI_DATA_2 0x294 32 1 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write qspi_data_3 SYS IOMUX CFG SAIF SYSCFG PADCFG 664: QSPI_DATA_3 0x298 32 9 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write func_sel_0 SYS IOMUX CFG SAIF SYSCFG 668 0x29c 32 0 pad_gmac1_rxc Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None [1:0] read-write pad_gpio_10 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [4:2] read-write pad_gpio_11 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [7:5] read-write pad_gpio_12 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [10:8] read-write pad_gpio_13 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [13:11] read-write pad_gpio_14 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [16:14] read-write pad_gpio_15 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [19:17] read-write pad_gpio_16 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [22:20] read-write pad_gpio_17 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [25:23] read-write pad_gpio_18 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [28:26] read-write pad_gpio_19 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [31:29] read-write func_sel_1 SYS IOMUX CFG SAIF SYSCFG 672 0x2a0 32 0 pad_gpio_20 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [2:0] read-write pad_gpio_21 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:3] read-write pad_gpio_22 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write pad_gpio_23 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [11:9] read-write pad_gpio_24 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write pad_gpio_25 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write pad_gpio_26 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write pad_gpio_27 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write pad_gpio_28 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write pad_gpio_29 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write func_sel_2 SYS IOMUX CFG SAIF SYSCFG 676 0x2a4 32 0 pad_gpio_30 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [2:0] read-write pad_gpio_31 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:3] read-write pad_gpio_32 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write pad_gpio_33 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [11:9] read-write pad_gpio_34 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write pad_gpio_35 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write pad_gpio_36 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write pad_gpio_37 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write pad_gpio_38 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write pad_gpio_39 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write pad_gpio_40 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [32:30] read-write func_sel_3 SYS IOMUX CFG SAIF SYSCFG 680 0x2a8 32 0 pad_gpio_41 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [2:0] read-write pad_gpio_42 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:3] read-write pad_gpio_43 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write pad_gpio_44 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [11:9] read-write pad_gpio_45 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write pad_gpio_46 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write pad_gpio_47 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write pad_gpio_48 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write pad_gpio_49 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write pad_gpio_50 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write pad_gpio_51 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [32:30] read-write func_sel_4 SYS IOMUX CFG SAIF SYSCFG 684 0x2ac 32 0 pad_gpio_52 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [1:0] read-write pad_gpio_53 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [3:2] read-write pad_gpio_54 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:4] read-write pad_gpio_56 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write pad_gpio_57 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write pad_gpio_58 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write pad_gpio_59 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write pad_gpio_60 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write pad_gpio_61 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write pad_gpio_62 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [32:30] read-write pad_gpio63 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [31:30] read-write func_sel_5 SYS IOMUX CFG SAIF SYSCFG 688 0x2b0 32 0 pad_gpio_6 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [1:0] read-write pad_gpio_7 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:3] read-write pad_gpio_8 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write pad_gpio_9 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [11:9] read-write vin_dvp_data_0 Function Selector of DVP_DATA[idx], see Function 2 for more information [13:11] read-write vin_dvp_data_10 Function Selector of DVP_DATA[idx], see Function 2 for more information [16:14] read-write vin_dvp_data_11 Function Selector of DVP_DATA[idx], see Function 2 for more information [19:17] read-write vin_dvp_data_1 Function Selector of DVP_DATA[idx], see Function 2 for more information [22:20] read-write vin_dvp_data_2 Function Selector of DVP_DATA[idx], see Function 2 for more information [25:23] read-write vin_dvp_data_3 Function Selector of DVP_DATA[idx], see Function 2 for more information [28:26] read-write vin_dvp_data_4 Function Selector of DVP_DATA[idx], see Function 2 for more information [31:29] read-write func_sel_6 SYS IOMUX CFG SAIF SYSCFG 692 0x2b4 32 0 vin_dvp_data_5 Function Selector of DVP_DATA[idx], see Function 2 for more information [2:0] read-write vin_dvp_data_6 Function Selector of DVP_DATA[idx], see Function 2 for more information [5:3] read-write vin_dvp_data_7 Function Selector of DVP_DATA[idx], see Function 2 for more information [8:6] read-write vin_dvp_data_8 Function Selector of DVP_DATA[idx], see Function 2 for more information [11:9] read-write vin_dvp_data_9 Function Selector of DVP_DATA[idx], see Function 2 for more information [14:12] read-write vin_dvp_hvalid Function Selector of DVP_HSYNC, see Function 2 for more information [17:15] read-write vin_dvp_vvalid Function Selector of DVP_VSYNC, see Function 2 for more information [20:18] read-write dvp_clk Function Selector of DVP_CLK, see Function 2 for more information [23:21] read-write starfive_jh7110_wdt_0 From starfive,jh7110-wdt, peripheral generator 0x13070000 0 0x10000 registers starfive_jh7110_crypto_0 From starfive,jh7110-crypto, peripheral generator 0x16000000 0 0x4000 registers arm_pl080_0 From arm,pl080, peripheral generator 0x16008000 0 0x4000 registers arm_primecell_7 From arm,primecell, peripheral generator 0x16008000 0 0x4000 registers trng From starfive,jh7110-trng, peripheral generator 0x1600C000 0 0x4000 registers ctrl TRNG CTRL Register 0x0 32 0 exec_nop Execute a NOP instruction [0:0] read-write gen_rand Generate a random number [1:1] read-write reseed Reseed the TRNG from noise sources [2:2] read-write stat TRNG STAT Register 0x4 32 0 nonce_mode TRNG Nonce operating mode [2:2] read-only r256 TRNG 256-bit random number operating mode [3:3] read-only mission_mode TRNG Mission Mode operating mode [8:8] read-only seeded TRNG Seeded operating mode [9:9] read-only last_reseed_0 TRNG Last Reseed 0 status [16:16] read-only last_reseed_1 TRNG Last Reseed 1 status [17:17] read-only last_reseed_2 TRNG Last Reseed 2 status [18:18] read-only last_reseed_3 TRNG Last Reseed 3 status [19:19] read-only last_reseed_4 TRNG Last Reseed 4 status [20:20] read-only last_reseed_5 TRNG Last Reseed 5 status [21:21] read-only last_reseed_6 TRNG Last Reseed 6 status [22:22] read-only last_reseed_7 TRNG Last Reseed 7 status [23:23] read-only srvc_rqst TRNG Service Request [27:27] read-only rand_generating TRNG Random Number Generating Status [30:30] read-only rand_seeding TRNG Random Number Seeding Status [31:31] read-only mode TRNG MODE Register 0x8 32 0 r256 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode [3:3] read-write smode TRNG SMODE Register 0xc 32 0 nonce_mode Nonce operation mode [2:2] read-write mission_mode Mission operation mode [8:8] read-write max_rejects TRNG Maximum Rejects [31:16] read-write ie TRNG Interrupt Enable Register 0x10 32 0 rand_rdy_en RAND Ready Enable [0:0] read-write seed_done_en Seed Done Enable [1:1] read-write lfsr_lockup_en LFSR Lockup Enable [4:4] read-write glbl_en Global Enable [31:31] read-write istat TRNG Interrupt Status Register 0x14 32 0 rand_rdy RAND Ready Enable [0:0] read-only seed_done Seed Done Enable [1:1] read-only lfsr_lockup_en LFSR Lockup Enable [4:4] read-only rand_0 TRNG RAND 0 Status Register 0x20 32 0 rand Random number bits [31:0] read-only rand_1 TRNG RAND 1 Status Register 0x24 32 0 rand Random number bits [31:0] read-only rand_2 TRNG RAND 2 Status Register 0x28 32 0 rand Random number bits [31:0] read-only rand_3 TRNG RAND 3 Status Register 0x2c 32 0 rand Random number bits [31:0] read-only rand_4 TRNG RAND 4 Status Register 0x30 32 0 rand Random number bits [31:0] read-only rand_5 TRNG RAND 5 Status Register 0x34 32 0 rand Random number bits [31:0] read-only rand_6 TRNG RAND 6 Status Register 0x38 32 0 rand Random number bits [31:0] read-only rand_7 TRNG RAND 7 Status Register 0x3c 32 0 rand Random number bits [31:0] read-only auto_rqsts Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter 0x60 32 0 rqsts Threshold number of reseed requests for auto-reseed counter [31:0] read-write auto_age Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer 0x64 32 0 age Countdown value for auto-reseed timer [31:0] read-write starfive_jh7110_mmc_0 From starfive,jh7110-mmc, peripheral generator 0x16010000 0 0x10000 registers starfive_jh7110_mmc_1 From starfive,jh7110-mmc, peripheral generator 0x16020000 0 0x10000 registers starfive_jh7110_dwmac_0 From starfive,jh7110-dwmac, peripheral generator 0x16030000 0 0x10000 registers snps_dwmac_0 From snps,dwmac, peripheral generator 0x16030000 0 0x10000 registers starfive_jh7110_dwmac_1 From starfive,jh7110-dwmac, peripheral generator 0x16040000 0 0x10000 registers snps_dwmac_1 From snps,dwmac, peripheral generator 0x16040000 0 0x10000 registers starfive_jh7110_axi_dma_0 From starfive,jh7110-axi-dma, peripheral generator 0x16050000 0 0x10000 registers aoncrg From starfive,jh7110-aoncrg, peripheral generator 0x17000000 0 0x10000 registers clk_osc Oscillator Clock 0x0 32 0 clk_divcfg Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 [23:0] read-write clk_aon_apb AON APB Function Clock 0x4 32 0 clk_mux_sel Clock multiplexing selector: clk_osc_div4, clk_osc [29:24] read-write clk_ahb_gmac5 AHB GMAC5 Clock 0x8 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_axi_gmac5 AXI GMAC5 Clock 0xc 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_gmac0_rmii_rtx GMAC0 RMII RTX Clock 0x10 32 0 clk_divcfg Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 [23:0] read-write clk_gmac5_axi64_tx GMAC5 AXI64 Clock Transmitter 0x14 32 0 clk_mux_sel Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx [29:24] read-write clk_gmac5_axi64_txi GMAC5 AXI64 Clock Transmission Inverter 0x18 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_gmac5_axi64_rx GMAC5 AXI64 Clock Receiver 0x1c 32 0 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write clk_gmac5_axi64_rxi GMAC5 AXI64 Clock Receiving Inverter 0x20 32 0 clk_polarity 1: Clock inverter, 0: Clock buffer [30:30] read-write clk_optc_apb OPTC APB Clock 0x24 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_rtc_hms_apb RTC HMS APB Clock 0x28 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write clk_rtc_internal RTC Internal Clock 0x2c 32 0 clk_divcfg Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750 [23:0] read-write clk_rtc_hms_osc32k RTC HMS Clock Oscillator 32K 0x30 32 0 clk_mux_sel Clock multiplexing selector: clk_rtc, clk_rtc_internal [29:24] read-write clk_rtc_hms_cal RTC HMS Clock Calculator 0x34 32 0 clk_icg 1: Clock enable, 0: Clock disable [31:31] read-write soft_rst_addr_sel Software RESET Address Selector 0x38 32 0 gmac5_axi64_axi 1: Assert reset, 0: De-assert reset [0:0] read-write gmac5_axi64_ahb 1: Assert reset, 0: De-assert reset [1:1] read-write aon_iomux_presetn 1: Assert reset, 0: De-assert reset [2:2] read-write pmu_apb 1: Assert reset, 0: De-assert reset [3:3] read-write pmu_wkup 1: Assert reset, 0: De-assert reset [4:4] read-write rtc_hms_apb 1: Assert reset, 0: De-assert reset [5:5] read-write rtc_hms_cal 1: Assert reset, 0: De-assert reset [6:6] read-write rtc_hms_osc32k 1: Assert reset, 0: De-assert reset [7:7] read-write aoncrg_rst_status AONCRG RESET Status 0x3c 32 0 gmac5_axi64_axi 1: Assert reset, 0: De-assert reset [0:0] read-write gmac5_axi64_ahb 1: Assert reset, 0: De-assert reset [1:1] read-write aon_iomux_presetn 1: Assert reset, 0: De-assert reset [2:2] read-write pmu_apb 1: Assert reset, 0: De-assert reset [3:3] read-write pmu_wkup 1: Assert reset, 0: De-assert reset [4:4] read-write rtc_hms_apb 1: Assert reset, 0: De-assert reset [5:5] read-write rtc_hms_cal 1: Assert reset, 0: De-assert reset [6:6] read-write rtc_hms_osc32k 1: Assert reset, 0: De-assert reset [7:7] read-write aon_syscon From starfive,jh7110-aon-syscon, peripheral generator 0x17010000 0 0x1000 registers aon_syscfg_0 AON SYSCONSAIF SYSCFG 0 0x0 32 0 aon_gp_reg aon_gp_reg [31:0] read-write aon_syscfg_1 AON SYSCONSAIF SYSCFG 4 0x4 32 0 u0_boot_ctrl_boot_status u0_boot_ctrl_boot_status [3:0] read-only aon_syscfg_2 AON SYSCONSAIF SYSCFG 8 0x8 32 0 u0_boot_ctrl_boot_vector_0_31 u0_boot_ctrl_boot_vector_0_31 [31:0] read-only aon_syscfg_3 AON SYSCONSAIF SYSCFG 12 0xc 32 0 u0_boot_ctrl_boot_vector_35_32 u0_boot_ctrl_boot_vector_35_32 [3:0] read-only gmac5_axi64_scfg_ram_cfg_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [4:4] read-write gmac5_axi64_scfg_ram_cfg_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [5:5] read-write gmac5_axi64_scfg_ram_cfg_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [7:6] read-write gmac5_axi64_scfg_ram_cfg_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write gmac5_axi64_scfg_ram_cfg_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [11:10] read-write gmac5_axi64_scfg_ram_cfg_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [13:12] read-write gmac5_axi64_scfg_ram_cfg_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [14:14] read-write gmac5_axi64_scfg_ram_cfg_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [15:15] read-write gmac5_axi64_mac_speed_o gmac5_axi64_mac_speed_o [17:16] read-only gmac5_axi64_phy_intf_sel_i Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII [20:18] read-write aon_syscfg_4 AON SYSCONSAIF SYSCFG 16 0x10 32 0 gmac5_axi64_ptp_timestamp_o_0_31 gmac5_axi64_ptp_timestamp_o_0_31 [31:0] read-only aon_syscfg_5 AON SYSCONSAIF SYSCFG 20 0x14 32 0 gmac5_axi64_ptp_timestamp_o_32_63 gmac5_axi64_ptp_timestamp_o_32_63 [31:0] read-only aon_syscfg_6 AON SYSCONSAIF SYSCFG 24 0x18 32 0 u0_otpc_chip_mode u0_otpc_chip_mode [0:0] read-only u0_otpc_crc_pass u0_otpc_crc_pass [1:1] read-only u0_otpc_dbg_enable u0_otpc_dbg_enable [2:2] read-only aon_syscfg_7 AON SYSCONSAIF SYSCFG 28 0x1c 32 0 u0_otpc_fl_func_lock u0_otpc_fl_func_lock [31:0] read-only aon_syscfg_8 AON SYSCONSAIF SYSCFG 32 0x20 32 0 u0_otpc_fl_pll0_lock u0_otpc_fl_pll0_lock [31:0] read-only aon_syscfg_9 AON SYSCONSAIF SYSCFG 36 0x24 32 0 u0_otpc_fl_pll1_lock u0_otpc_fl_pll1_lock [31:0] read-only aon_syscfg_10 AON SYSCONSAIF SYSCFG 40 0x28 32 0 u0_otpc_fl_sec_boot_lmt u0_otpc_fl_sec_boot_lmt [0:0] read-only u0_otpc_fl_xip u0_otpc_fl_xip [1:1] read-only u0_otpc_load_busy u0_otpc_load_busy [2:2] read-only u0_reset_ctrl_clr_reset_status u0_reset_ctrl_clr_reset_status [3:3] read-write u0_reset_ctrl_pll_timecnt_finish u0_reset_ctrl_pll_timecnt_finish [4:4] read-only u0_reset_ctrl_rstn_sw u0_reset_ctrl_rstn_sw [5:5] read-write u0_reset_ctrl_sys_reset_status u0_reset_ctrl_sys_reset_status [9:6] read-only syscon_2 From syscon, peripheral generator 0x17010000 0 0x1000 registers aon_pinctrl From starfive,jh7110-aon-pinctrl, peripheral generator 0x17020000 0 0x10000 registers fmux_0 AON IOMUX CFG SAIF SYSCFG FMUX 0 0x0 32 0 gpo_doen_0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [2:0] read-write gpo_doen_1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [10:8] read-write gpo_doen_2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [18:16] read-write gpo_doen_3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [26:24] read-write fmux_1 AON IOMUX CFG SAIF SYSCFG FMUX 4 0x4 32 0 gpo_dout_0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [3:0] read-write gpo_dout_1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [11:8] read-write gpo_dout_2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [19:16] read-write gpo_dout_3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [27:24] read-write fmux_2 AON IOMUX CFG SAIF SYSCFG FMUX 8 0x8 32 0 gpi_pmu_wakeup_0 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [2:0] read-write gpi_pmu_wakeup_1 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [10:8] read-write gpi_pmu_wakeup_2 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [18:16] read-write gpi_pmu_wakeup_3 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [26:24] read-write fmux_3 AON IOMUX CFG SAIF SYSCFG FMUX 12 0xc 32 0 gpen_0 Enable GPIO IRQ function. [0:0] read-write ioirq_0 AON IOMUX CFG SAIF SYSCFG IOIRQ 16 0x10 32 0 is 1: Edge trigger, 0: Level trigger [3:0] read-write ioirq_1 AON IOMUX CFG SAIF SYSCFG IOIRQ 20 0x14 32 0 ic 1: Do not clear the register, 0: Clear the register [3:0] read-write ioirq_2 AON IOMUX CFG SAIF SYSCFG IOIRQ 24 0x18 32 0 ibe 1: Trigger on both edges, 0: Trigger on a single edge [3:0] read-write ioirq_3 AON IOMUX CFG SAIF SYSCFG IOIRQ 28 0x1c 32 0 iev 1: Positive/Low, 0: Negative/High [3:0] read-write ioirq_4 AON IOMUX CFG SAIF SYSCFG IOIRQ 32 0x20 32 0 ie 1: Unmask, 0: Mask [3:0] read-write ioirq_5 AON IOMUX CFG SAIF SYSCFG IOIRQ 36 0x24 32 0 ris Status of the edge trigger, can be cleared by writing gpioic. [3:0] read-only ioirq_6 AON IOMUX CFG SAIF SYSCFG IOIRQ 40 0x28 32 0 mis The masked GPIO IRQ status. [3:0] read-only ioirq_7 AON IOMUX CFG SAIF SYSCFG IOIRQ 44 0x2c 32 0 in_sync2 Status of gpio_in after synchronization. [3:0] read-only testen AON IOMUX CFG SAIF SYSCFG 48 0x30 32 0 testen_pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [0:0] read-write rgpio_0 AON IOMUX CFG SAIF SYSCFG 52 0x34 32 0 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write rgpio_1 AON IOMUX CFG SAIF SYSCFG 56 0x38 32 0 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write rgpio_2 AON IOMUX CFG SAIF SYSCFG 60 0x3c 32 0 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write rgpio_3 AON IOMUX CFG SAIF SYSCFG 64 0x40 32 0 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger ebabled [6:6] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write rstn AON IOMUX CFG SAIF SYSCFG 68 0x44 32 0 smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled [0:0] read-write pos Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled [1:1] read-write rtc AON IOMUX CFG SAIF SYSCFG 76 0x4c 32 0 ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write osc AON IOMUX CFG SAIF SYSCFG 84 0x54 32 0 ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write gmac0_mdc AON IOMUX CFG SAIF SYSCFG 88 0x58 32 0 value value [1:0] read-write gmac0_mdio AON IOMUX CFG SAIF SYSCFG 92 0x5c 32 0 value value [1:0] read-write gmac0_rxd0 AON IOMUX CFG SAIF SYSCFG 96 0x60 32 0 value 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V [1:0] read-write gmac0_rxd1 AON IOMUX CFG SAIF SYSCFG 100 0x64 32 0 value value [1:0] read-write gmac0_rxd2 AON IOMUX CFG SAIF SYSCFG 104 0x68 32 0 value value [1:0] read-write gmac0_rxd3 AON IOMUX CFG SAIF SYSCFG 108 0x6c 32 0 value value [1:0] read-write gmac0_rxdv AON IOMUX CFG SAIF SYSCFG 112 0x70 32 0 value value [1:0] read-write gmac0_rxc AON IOMUX CFG SAIF SYSCFG 116 0x74 32 0 value value [1:0] read-write gmac0_txd0 AON IOMUX CFG SAIF SYSCFG 120 0x78 32 0 value value [1:0] read-write gmac0_txd1 AON IOMUX CFG SAIF SYSCFG 124 0x7c 32 0 value value [1:0] read-write gmac0_txd2 AON IOMUX CFG SAIF SYSCFG 128 0x80 32 0 value value [1:0] read-write gmac0_txd3 AON IOMUX CFG SAIF SYSCFG 132 0x84 32 0 value value [1:0] read-write gmac0_txen AON IOMUX CFG SAIF SYSCFG 136 0x88 32 0 value value [1:0] read-write gmac0_txc AON IOMUX CFG SAIF SYSCFG 140 0x8c 32 0 value value [1:0] read-write gmac0_rxc_func_sel AON IOMUX CFG SAIF SYSCFG 144 0x90 32 0 value Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None [1:0] read-write pmu From starfive,jh7110-pmu, peripheral generator 0x17030000 0 0x10000 registers pmu 106 hard_event_turn_on_mask Hardware Event Turn-On Mask 0x4 32 0 hard_event_0_on_mask RTC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [0:0] read-write hard_event_1_on_mask GMAC event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [1:1] read-write hard_event_2_on_mask RFU, 1: mask hardware event, 0: enable hardware event [2:2] read-write hard_event_3_on_mask RGPIO0 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [3:3] read-write hard_event_4_on_mask RGPIO1 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [4:4] read-write hard_event_5_on_mask RGPIO2 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [5:5] read-write hard_event_6_on_mask RGPIO3 event encourage turn-on sequence, 1: mask hardware event, 0: enable hardware event [6:6] read-write hard_event_7_on_mask GPU event, 1: mask hardware event, 0: enable hardware event [7:7] read-write soft_turn_on_power_mode Software Turn-On Power Mode 0xc 32 0 systop_power_mode SYSTOP turn-on power mode. [0:0] read-write cpu_power_mode CPU turn-on power mode. [1:1] read-write gpua_power_mode GPUA turn-on power mode. [2:2] read-write vdec_power_mode VDEC turn-on power mode. [3:3] read-write vout_power_mode VOUT turn-on power mode. [4:4] read-write isp_power_mode ISP turn-on power mode. [5:5] read-write venc_power_mode VENC turn-on power mode. [6:6] read-write soft_turn_off_power_mode Software Turn-Off Power Mode 0x10 32 0 systop_power_mode SYSTOP turn-off power mode. [0:0] read-write cpu_power_mode CPU turn-off power mode. [1:1] read-write gpua_power_mode GPUA turn-off power mode. [2:2] read-write vdec_power_mode VDEC turn-off power mode. [3:3] read-write vout_power_mode VOUT turn-off power mode. [4:4] read-write isp_power_mode ISP turn-off power mode. [5:5] read-write venc_power_mode VENC turn-off power mode. [6:6] read-write timeout_seq_thd Threshold Sequence Timeout 0x14 32 0 timeout_seq_thd Threshold Sequence Timeout [15:0] read-write pdc0 Powerdomain Cascade 0 0x18 32 0 pd0_off_cas Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [4:0] read-write pd0_on_cas Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [9:5] read-write pd1_off_cas Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [14:10] read-write pd1_on_cas Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [19:15] read-write pd2_off_cas Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [24:20] read-write pd2_on_cas Power domain 2 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [29:25] read-write pdc1 Powerdomain Cascade 1 0x1c 32 0 pd3_off_cas Power domain 3 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [4:0] read-write pd3_on_cas Power domain 3 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [9:5] read-write pd4_off_cas Power domain 4 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [14:10] read-write pd4_on_cas Power domain 4 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [19:15] read-write pd5_off_cas Power domain 5 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [24:20] read-write pd5_on_cas Power domain 5 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [29:25] read-write pdc2 Powerdomain Cascade 2 0x20 32 0 pd6_off_cas Power domain 6 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [4:0] read-write pd6_on_cas Power domain 6 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [9:5] read-write pd7_off_cas Power domain 7 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [14:10] read-write pd7_on_cas Power domain 7 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [19:15] read-write pd8_off_cas Power domain 8 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [24:20] read-write pd8_on_cas Power domain 8 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7, any other value is invalid. [29:25] read-write sw_encourage Software Encouragement 0x44 32 0 sw_encourage Software Encouragement [7:0] read-write tim TIMER Interrupt Mask 0x48 32 0 seq_done_mask Mask the sequence complete event. 0: mask, 1: unmask [0:0] read-write hw_req_mask Mask the hardware encouragement request. 0: mask, 1: unmask [1:1] read-write sw_fail_mask Mask the software encouragement failure event. 0: mask, 1: unmask [3:2] read-write hw_fail_mask Mask the hardware encouragement failure event. 0: mask, 1: unmask [5:4] read-write pch_fail_mask Mask the P-channel encouragement failure event. 0: mask, 1: unmask [8:6] read-write pch_bypass P-channel Bypass 0x4c 32 0 pch_bypass Bypass P-channel. 0: enable p-channel, 1: bypass p-channel [0:0] read-write pch_pstate P-channel PSTATE 0x50 32 0 pch_pstate P-channel state set [4:0] read-write pch_timeout P-channel Timeout Threshold 0x54 32 0 pch_timeout P-channel waiting device acknowledge timeout. [7:0] read-write lp_timeout LP Cell Control Timeout Threshold 0x58 32 0 lp_timeout LP Cell Control signal waiting carries acknowledge timeout. [7:0] read-write hard_turn_on_power_mode Hardware Turn-On Power Mode 0x5c 32 0 systop_power_mode SYSTOP turn-on power mode. [0:0] read-write cpu_power_mode CPU turn-on power mode. [1:1] read-write gpua_power_mode GPUA turn-on power mode. [2:2] read-write vdec_power_mode VDEC turn-on power mode. [3:3] read-write vout_power_mode VOUT turn-on power mode. [4:4] read-write isp_power_mode ISP turn-on power mode. [5:5] read-write venc_power_mode VENC turn-on power mode. [6:6] read-write current_power_mode Current Power Mode 0x80 32 0 systop_power_mode SYSTOP turn-on power mode. [0:0] read-write cpu_power_mode CPU turn-on power mode. [1:1] read-write gpua_power_mode GPUA turn-on power mode. [2:2] read-write vdec_power_mode VDEC turn-on power mode. [3:3] read-write vout_power_mode VOUT turn-on power mode. [4:4] read-write isp_power_mode ISP turn-on power mode. [5:5] read-write venc_power_mode VENC turn-on power mode. [6:6] read-write current_seq_state Current Sequence State 0x84 32 0 power_mode_cur Current sequence state. [1:0] read-only event_status PMU Event Status 0x88 32 0 seq_done_event Sequence complete. [0:0] read-only hw_req_event Hardware encouragement request. [1:1] read-only sw_fail_event Software encouragement failure. [3:2] read-only hw_fail_event Hardware encouragement failure. [5:4] read-only pch_fail_event P-channel failure. [8:6] read-only int_status PMU Interrupt Status 0x8c 32 0 seq_done_event Sequence complete. [0:0] read-only hw_req_event Hardware encouragement request. [1:1] read-only sw_fail_event Software encouragement failure. [3:2] read-only hw_fail_event Hardware encouragement failure. [5:4] read-only pch_fail_event P-channel failure. [8:6] read-only hw_event_crd Hardware Event Record 0x90 32 0 hw_event_crd Hardware Event Record. [7:0] read-only encourage_type_crd Hardware Event Type Record 0x94 32 0 encourage_type_crd Hardware/Software encouragement type record. 0: Software, 1: Hardware. [0:0] read-only pch_active P-channel PACTIVE Status 0x98 32 0 pch_active P-channel PACTIVE status. [10:0] read-only starfive_jh7110_ispcrg_0 From starfive,jh7110-ispcrg, peripheral generator 0x19810000 0 0x10000 registers starfive_jh7110_voutcrg_0 From starfive,jh7110-voutcrg, peripheral generator 0x295C0000 0 0x10000 registers