/dts-v1/;

/ {
	compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "StarFive VisionFive 2 v1.2A";

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		timebase-frequency = <0x3d0900>;

		S7_0: cpu@0 {
			compatible = "sifive,s7", "riscv";
			reg = <0x00>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x4000>;
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imac_zba_zbb";
			status = "disabled";
			phandle = <0x05>;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x0d>;
			};
		};

		U74_1: cpu@1 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x01>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			phandle = <0x06>;

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x0e>;
			};
		};

		U74_2: cpu@2 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x02>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			phandle = <0x07>;

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x0f>;
			};
		};

		U74_3: cpu@3 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x03>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			phandle = <0x08>;

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x10>;
			};
		};

		U74_4: cpu@4 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x04>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			phandle = <0x09>;

			cpu4_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x11>;
			};
		};
	};

	cpu_opp: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0x02>;
	};

	dvp_clk: dvp-clock {
		compatible = "fixed-clock";
		clock-output-names = "dvp_clk";
		#clock-cells = <0x00>;
		clock-frequency = <0x46cf710>;
		phandle = <0x35>;
	};

	gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac0_rgmii_rxin";
		#clock-cells = <0x00>;
		clock-frequency = <0x7735940>;
		phandle = <0x33>;
	};

	gmac0_rmii_refin: gmac0-rmii-refin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac0_rmii_refin";
		#clock-cells = <0x00>;
		clock-frequency = <0x2faf080>;
		phandle = <0x32>;
	};

	gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac1_rgmii_rxin";
		#clock-cells = <0x00>;
		clock-frequency = <0x7735940>;
		phandle = <0x20>;
	};

	gmac1_rmii_refin: gmac1-rmii-refin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac1_rmii_refin";
		#clock-cells = <0x00>;
		clock-frequency = <0x2faf080>;
		phandle = <0x1f>;
	};

	hdmitx0_pixelclk: hdmitx0-pixel-clock {
		compatible = "fixed-clock";
		clock-output-names = "hdmitx0_pixelclk";
		#clock-cells = <0x00>;
		clock-frequency = <0x11b3dc40>;
		phandle = <0x37>;
	};

	i2srx_bclk_ext: i2srx-bclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2srx_bclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		phandle = <0x23>;
	};

	i2srx_lrck_ext: i2srx-lrck-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2srx_lrck_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee00>;
		phandle = <0x24>;
	};

	i2stx_bclk_ext: i2stx-bclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2stx_bclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		phandle = <0x21>;
	};

	i2stx_lrck_ext: i2stx-lrck-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2stx_lrck_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee00>;
		phandle = <0x22>;
	};

	mclk_ext: mclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "mclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		phandle = <0x25>;
	};

	osc: oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc";
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		phandle = <0x1c>;
	};

	rtc_osc: rtc-oscillator {
		compatible = "fixed-clock";
		clock-output-names = "rtc_osc";
		#clock-cells = <0x00>;
		clock-frequency = <0x8000>;
		phandle = <0x34>;
	};

	stmmac_axi_setup: stmmac-axi-config {
		snps,lpi_en;
		snps,wr_osr_lmt = <0x0f>;
		snps,rd_osr_lmt = <0x0f>;
		snps,blen = <0x100 0x80 0x40 0x20 0x00 0x00 0x00>;
		phandle = <0x2e>;
	};

	tdm_ext: tdm-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "tdm_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee0000>;
		phandle = <0x16>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		clint: timer@2000000 {
			compatible = "starfive,jh7110-clint", "riscv,clint";
			reg = <0x00 0x2000000 0x00 0x10000>;
			interrupts-extended = <&cpu0_intc 0x03>, <&cpu0_intc 0x07>, <&cpu1_intc 0x03>, <&cpu1_intc 0x07>, <&cpu2_intc 0x03>, <&cpu2_intc 0x07>, <&cpu3_intc 0x03>, <&cpu3_intc 0x07>, <&cpu4_intc 0x03>, <&cpu4_intc 0x07>;
		};

		ccache: cache-controller@2010000 {
			compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
			reg = <0x00 0x2010000 0x00 0x4000>;
			interrupts = <0x01>, <0x02>, <0x03>, <0x04>;
			cache-block-size = <0x40>;
			cache-level = <0x02>;
			cache-sets = <0x800>;
			cache-size = <0x200000>;
			cache-unified;
			phandle = <0x01>;
		};

		sram: sram@8000000 {
			compatible = "starfive,jh7110-sram", "sifive,u74-mc-sram", "sifive,u74-mc-l2-lim";
			reg = <0x00 0x8000000 0x00 0x200000>;
		};

		plic: interrupt-controller@c000000 {
			compatible = "starfive,jh7110-plic", "riscv,plic";
			reg = <0x00 0xc000000 0x00 0x4000000>;
			interrupts-extended = <&cpu0_intc 0x0b>, <&cpu1_intc 0x0b>, <&cpu1_intc 0x09>, <&cpu2_intc 0x0b>, <&cpu2_intc 0x09>, <&cpu3_intc 0x0b>, <&cpu3_intc 0x09>, <&cpu4_intc 0x0b>, <&cpu4_intc 0x09>;
			interrupt-controller;
			#interrupt-cells = <0x01>;
			#address-cells = <0x00>;
			riscv,ndev = <0x88>;
			phandle = <0x0c>;
		};

		uart0: serial@10000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x10000000 0x00 0x10000>;
			clocks = <&syscrg 0x92>, <&syscrg 0x91>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg 0x53>;
			interrupts = <0x20>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pins>;
		};

		uart1: serial@10010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x10010000 0x00 0x10000>;
			clocks = <&syscrg 0x94>, <&syscrg 0x93>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg 0x55>;
			interrupts = <0x21>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
		};

		uart2: serial@10020000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x10020000 0x00 0x10000>;
			clocks = <&syscrg 0x96>, <&syscrg 0x95>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg 0x57>;
			interrupts = <0x22>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
		};

		i2c0: i2c@10030000 {
			compatible = "snps,designware-i2c";
			reg = <0x00 0x10030000 0x00 0x10000>;
			clocks = <&syscrg 0x8a>;
			clock-names = "ref";
			resets = <&syscrg 0x4c>;
			interrupts = <0x23>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "okay";
			clock-frequency = <0x186a0>;
			i2c-sda-hold-time-ns = <0x12c>;
			i2c-sda-falling-time-ns = <0x1fe>;
			i2c-scl-falling-time-ns = <0x1fe>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pins>;
		};

		i2c1: i2c@10040000 {
			compatible = "snps,designware-i2c";
			reg = <0x00 0x10040000 0x00 0x10000>;
			clocks = <&syscrg 0x8b>;
			clock-names = "ref";
			resets = <&syscrg 0x4d>;
			interrupts = <0x24>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		i2c2: i2c@10050000 {
			compatible = "snps,designware-i2c";
			reg = <0x00 0x10050000 0x00 0x10000>;
			clocks = <&syscrg 0x8c>;
			clock-names = "ref";
			resets = <&syscrg 0x4e>;
			interrupts = <0x25>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "okay";
			clock-frequency = <0x186a0>;
			i2c-sda-hold-time-ns = <0x12c>;
			i2c-sda-falling-time-ns = <0x1fe>;
			i2c-scl-falling-time-ns = <0x1fe>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2_pins>;
		};

		spi0: spi@10060000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00 0x10060000 0x00 0x10000>;
			clocks = <&syscrg 0x83>, <&syscrg 0x83>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&syscrg 0x45>;
			interrupts = <0x26>;
			arm,primecell-periphid = <0x41022>;
			num-cs = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&spi0_pins>;

			spi_dev0: spi@0 {
				compatible = "rohm,dh2228fv";
				reg = <0x00>;
				spi-max-frequency = <0x989680>;
			};
		};

		spi1: spi@10070000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00 0x10070000 0x00 0x10000>;
			clocks = <&syscrg 0x84>, <&syscrg 0x84>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&syscrg 0x46>;
			interrupts = <0x27>;
			arm,primecell-periphid = <0x41022>;
			num-cs = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		spi2: spi@10080000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00 0x10080000 0x00 0x10000>;
			clocks = <&syscrg 0x85>, <&syscrg 0x85>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&syscrg 0x47>;
			interrupts = <0x28>;
			arm,primecell-periphid = <0x41022>;
			num-cs = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		tdm: tdm@10090000 {
			compatible = "starfive,jh7110-tdm";
			reg = <0x00 0x10090000 0x00 0x1000>;
			clocks = <&syscrg 0xb8>, <&syscrg 0xb9>, <&syscrg 0xba>, <&syscrg 0xbb>, <&syscrg 0x11>, <&tdm_ext>;
			clock-names = "tdm_ahb", "tdm_apb", "tdm_internal", "tdm", "mclk_inner", "tdm_ext";
			resets = <&syscrg 0x69>, <&syscrg 0x6b>, <&syscrg 0x6a>;
			dmas = <&dma 0x14>, <&dma 0x15>;
			dma-names = "rx", "tx";
			#sound-dai-cells = <0x00>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&tdm_pins>;
		};

		dmc_ctrl: dmc@15700000 {
			compatible = "starfive,jh7110-dmc-ctrl", "openedges,omc";
			reg = <0x0 0x15700000 0x0 0x10000>;
			resets = <&syscrg 38>, <&syscrg 39>, <&syscrg 40>;
			reset-names = "axi", "osc", "apb";
			clock-frequency = <2133>;
		};

		dmc_phy: dmc@13000000 {
			compatible = "starfive,jh7110-dmc-phy", "openedges,ophy";
			reg = <0x0 0x13000000 0x0 0x10000>;
			resets = <&syscrg 38>, <&syscrg 39>, <&syscrg 40>;
			reset-names = "axi", "osc", "apb";
			clock-frequency = <2133>;
		};

		usb0: usb@10100000 {
			compatible = "starfive,jh7110-usb";
			ranges = <0x00 0x00 0x10100000 0x100000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			starfive,stg-syscon = <&stg_syscon 0x04>;
			clocks = <&stgcrg 0x04>, <&stgcrg 0x05>, <&stgcrg 0x01>, <&stgcrg 0x03>, <&stgcrg 0x02>;
			clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
			resets = <&stgcrg 0x0a>, <&stgcrg 0x08>, <&stgcrg 0x07>, <&stgcrg 0x09>;
			reset-names = "pwrup", "apb", "axi", "utmi_apb";
			status = "disabled";
			dr_mode = "peripheral";

			usb_cdns3: usb@0 {
				compatible = "cdns,usb3";
				reg = <0x00 0x10000>, <0x10000 0x10000>, <0x20000 0x10000>;
				reg-names = "otg", "xhci", "dev";
				interrupts = <0x64>, <0x6c>, <0x6e>;
				interrupt-names = "host", "peripheral", "otg";
				phys = <&usbphy0>;
				phy-names = "cdns3,usb2-phy";
			};
		};

		usbphy0: phy@10200000 {
			compatible = "starfive,jh7110-usb-phy";
			reg = <0x00 0x10200000 0x00 0x10000>;
			clocks = <&syscrg 0x5f>, <&stgcrg 0x06>;
			clock-names = "125m", "app_125m";
			#phy-cells = <0x00>;
			phandle = <0x1b>;
		};

		pciephy0: phy@10210000 {
			compatible = "starfive,jh7110-pcie-phy";
			reg = <0x00 0x10210000 0x00 0x10000>;
			#phy-cells = <0x00>;
		};

		pciephy1: phy@10220000 {
			compatible = "starfive,jh7110-pcie-phy";
			reg = <0x00 0x10220000 0x00 0x10000>;
			#phy-cells = <0x00>;
		};

		stgcrg: clock-controller@10230000 {
			compatible = "starfive,jh7110-stgcrg";
			reg = <0x00 0x10230000 0x00 0x10000>;
			clocks = <&osc>, <&syscrg 0x36>, <&syscrg 0x08>, <&syscrg 0x5f>, <&syscrg 0x02>, <&syscrg 0x37>, <&syscrg 0x06>, <&syscrg 0x0b>;
			clock-names = "osc", "hifi4_core", "stg_axiahb", "usb_125m", "cpu_bus", "hifi4_axi", "nocstg_bus", "apb_bus";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			phandle = <0x1a>;
		};

		stg_syscon: syscon@10240000 {
			compatible = "starfive,jh7110-stg-syscon", "syscon";
			reg = <0x00 0x10240000 0x00 0x1000>;
			phandle = <0x19>;
		};

		uart3: serial@12000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x12000000 0x00 0x10000>;
			clocks = <&syscrg 0x98>, <&syscrg 0x97>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg 0x59>;
			interrupts = <0x2d>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
		};

		uart4: serial@12010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x12010000 0x00 0x10000>;
			clocks = <&syscrg 0x9a>, <&syscrg 0x99>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg 0x5b>;
			interrupts = <0x2e>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
		};

		uart5: serial@12020000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x12020000 0x00 0x10000>;
			clocks = <&syscrg 0x9c>, <&syscrg 0x9b>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg 0x5d>;
			interrupts = <0x2f>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
		};

		i2c3: i2c@12030000 {
			compatible = "snps,designware-i2c";
			reg = <0x00 0x12030000 0x00 0x10000>;
			clocks = <&syscrg 0x8d>;
			clock-names = "ref";
			resets = <&syscrg 0x4f>;
			interrupts = <0x30>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		i2c4: i2c@12040000 {
			compatible = "snps,designware-i2c";
			reg = <0x00 0x12040000 0x00 0x10000>;
			clocks = <&syscrg 0x8e>;
			clock-names = "ref";
			resets = <&syscrg 0x50>;
			interrupts = <0x31>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		i2c5: i2c@12050000 {
			compatible = "snps,designware-i2c";
			reg = <0x00 0x12050000 0x00 0x10000>;
			clocks = <&syscrg 0x8f>;
			clock-names = "ref";
			resets = <&syscrg 0x51>;
			interrupts = <0x32>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "okay";
			clock-frequency = <0x186a0>;
			i2c-sda-hold-time-ns = <0x12c>;
			i2c-sda-falling-time-ns = <0x1fe>;
			i2c-scl-falling-time-ns = <0x1fe>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c5_pins>;
		};

		i2c6: i2c@12060000 {
			compatible = "snps,designware-i2c";
			reg = <0x00 0x12060000 0x00 0x10000>;
			clocks = <&syscrg 0x90>;
			clock-names = "ref";
			resets = <&syscrg 0x52>;
			interrupts = <0x33>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "okay";
			clock-frequency = <0x186a0>;
			i2c-sda-hold-time-ns = <0x12c>;
			i2c-sda-falling-time-ns = <0x1fe>;
			i2c-scl-falling-time-ns = <0x1fe>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c6_pins>;
		};

		spi3: spi@12070000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00 0x12070000 0x00 0x10000>;
			clocks = <&syscrg 0x86>, <&syscrg 0x86>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&syscrg 0x48>;
			interrupts = <0x34>;
			arm,primecell-periphid = <0x41022>;
			num-cs = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		spi4: spi@12080000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00 0x12080000 0x00 0x10000>;
			clocks = <&syscrg 0x87>, <&syscrg 0x87>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&syscrg 0x49>;
			interrupts = <0x35>;
			arm,primecell-periphid = <0x41022>;
			num-cs = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		spi5: spi@12090000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00 0x12090000 0x00 0x10000>;
			clocks = <&syscrg 0x88>, <&syscrg 0x88>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&syscrg 0x4a>;
			interrupts = <0x36>;
			arm,primecell-periphid = <0x41022>;
			num-cs = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		spi6: spi@120a0000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00 0x120a0000 0x00 0x10000>;
			clocks = <&syscrg 0x89>, <&syscrg 0x89>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&syscrg 0x4b>;
			interrupts = <0x37>;
			arm,primecell-periphid = <0x41022>;
			num-cs = <0x01>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			status = "disabled";
		};

		sfctemp: temperature-sensor@120e0000 {
			compatible = "starfive,jh7110-temp";
			reg = <0x00 0x120e0000 0x00 0x10000>;
			clocks = <&syscrg 0x82>, <&syscrg 0x81>;
			clock-names = "sense", "bus";
			resets = <&syscrg 0x7c>, <&syscrg 0x7b>;
			reset-names = "sense", "bus";
			#thermal-sensor-cells = <0x00>;
			phandle = <0x0a>;
		};

		qspi: spi@13010000 {
			compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
			reg = <0x00 0x13010000 0x00 0x10000>;
			interrupts = <0x19>;
			clocks = <&syscrg 0x5a>, <&syscrg 0x57>, <&syscrg 0x58>;
			clock-names = "ref", "ahb", "apb";
			resets = <&syscrg 0x3e>, <&syscrg 0x3d>, <&syscrg 0x3f>;
			reset-names = "qspi", "qspi-ocp", "rstc_ref";
			cdns,fifo-depth = <0x100>;
			cdns,fifo-width = <0x04>;
			cdns,trigger-address = <0x00>;
			status = "okay";
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			qspi_nor_flash: flash@0 {
				compatible = "jedec,spi-nor";
				reg = <0x00>;
				cdns,read-delay = <0x05>;
				spi-max-frequency = <0xb71b00>;
				cdns,tshsl-ns = <0x01>;
				cdns,tsd2d-ns = <0x01>;
				cdns,tchsh-ns = <0x01>;
				cdns,tslch-ns = <0x01>;
			};
		};

		xspi: spi@21000000 {
			compatible = "starfive,jh7110-xspi", "cdns,xspi-nor";
			reg = <0x00 0x21000000 0x00 0x400000>;
			clocks = <&syscrg 0x5a>, <&syscrg 0x57>, <&syscrg 0x58>;
			clock-names = "ref", "ahb", "apb";
			resets = <&syscrg 0x3e>, <&syscrg 0x3d>, <&syscrg 0x3f>;
			reset-names = "xspi", "qspi", "rstc_ref";
			cdns,fifo-depth = <0x100>;
			cdns,fifo-width = <0x04>;
			cdns,trigger-address = <0x00>;
			status = "okay";
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			xspi_nor_flash: flash@0 {
				compatible = "jedec,spi-nor";
				reg = <0x00>;
				cdns,read-delay = <0x05>;
				spi-max-frequency = <0xb71b00>;
				cdns,tshsl-ns = <0x01>;
				cdns,tsd2d-ns = <0x01>;
				cdns,tchsh-ns = <0x01>;
				cdns,tslch-ns = <0x01>;
			};
		};

                ptc: pwm@120d0000 {
                        compatible = "starfive,jh7110-pwm", "opencores,pwm-v1";
                        reg = <0x0 0x120d0000 0x0 0x10000>;
                        clocks = <&syscrg 121>;
                        resets = <&syscrg 108>;
                        #pwm-cells = <3>;
                        status = "disabled";
                };

		syscrg: clock-controller@13020000 {
			compatible = "starfive,jh7110-syscrg";
			reg = <0x00 0x13020000 0x00 0x10000>;
			clocks = <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, <&tdm_ext>, <&mclk_ext>, <&pllclk 0x00>, <&pllclk 0x01>, <&pllclk 0x02>;
			clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", "tdm_ext", "mclk_ext", "pll0_out", "pll1_out", "pll2_out";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			phandle = <0x03>;
		};

		sys_syscon: syscon@13030000 {
			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
			reg = <0x00 0x13030000 0x00 0x1000>;
			phandle = <0x28>;

			pllclk: clock-controller {
				compatible = "starfive,jh7110-pll";
				clocks = <&osc>;
				#clock-cells = <0x01>;
				phandle = <0x26>;
			};
		};

		sysgpio: pinctrl@13040000 {
			compatible = "starfive,jh7110-sys-pinctrl";
			reg = <0x00 0x13040000 0x00 0x10000>;
			clocks = <&syscrg 0x70>;
			resets = <&syscrg 0x02>;
			interrupts = <0x56>;
			interrupt-controller;
			#interrupt-cells = <0x01>;
			gpio-controller;
			#gpio-cells = <0x02>;
			phandle = <0x38>;

			i2c0_pins: i2c0-0 {
				phandle = <0x13>;

				i2c-pins {
					pinmux = <0x9001439>, <0xa00183a>;
					bias-disable;
					input-enable;
					input-schmitt-enable;
				};
			};

			i2c2_pins: i2c2-0 {
				phandle = <0x14>;

				i2c-pins {
					pinmux = <0x3b007803>, <0x3c007c02>;
					bias-disable;
					input-enable;
					input-schmitt-enable;
				};
			};

			i2c5_pins: i2c5-0 {
				phandle = <0x1d>;

				i2c-pins {
					pinmux = <0x4f00a813>, <0x5000ac14>;
					bias-disable;
					input-enable;
					input-schmitt-enable;
				};
			};

			i2c6_pins: i2c6-0 {
				phandle = <0x1e>;

				i2c-pins {
					pinmux = <0x5600b810>, <0x5700bc11>;
					bias-disable;
					input-enable;
					input-schmitt-enable;
				};
			};

			mmc0_pins: mmc0-0 {
				phandle = <0x29>;

				rst-pins {
					pinmux = <0xff13003e>;
					bias-pull-up;
					drive-strength = <0x0c>;
					input-disable;
					input-schmitt-disable;
					slew-rate = <0x00>;
				};

				mmc-pins {
					pinmux = <0x440>, <0x441>, <0x442>, <0x443>, <0x444>, <0x445>, <0x446>, <0x447>, <0x448>, <0x449>;
					bias-pull-up;
					drive-strength = <0x0c>;
					input-enable;
				};
			};

			mmc1_pins: mmc1-0 {
				phandle = <0x2c>;

				clk-pins {
					pinmux = <0xff37000a>;
					bias-pull-up;
					drive-strength = <0x0c>;
					input-disable;
					input-schmitt-disable;
					slew-rate = <0x00>;
				};

				mmc-pins {
					pinmux = <0x2c394c09>, <0x2d3a500b>, <0x2e3b540c>, <0x2f3c5807>, <0x303d5c08>;
					bias-pull-up;
					drive-strength = <0x0c>;
					input-enable;
					input-schmitt-enable;
					slew-rate = <0x00>;
				};
			};

			spi0_pins: spi0-0 {
				phandle = <0x15>;

				mosi-pins {
					pinmux = <0xff200034>;
					bias-disable;
					input-disable;
					input-schmitt-disable;
				};

				miso-pins {
					pinmux = <0x1c000435>;
					bias-pull-up;
					input-enable;
					input-schmitt-enable;
				};

				sck-pins {
					pinmux = <0x1a1e0030>;
					bias-disable;
					input-disable;
					input-schmitt-disable;
				};

				ss-pins {
					pinmux = <0x1b1f0030>;
					bias-disable;
					input-disable;
					input-schmitt-disable;
				};
			};

			uart0_pins: uart0-0 {
				phandle = <0x12>;

				tx-pins {
					pinmux = <0xff140005>;
					bias-disable;
					drive-strength = <0x0c>;
					input-disable;
					input-schmitt-disable;
					slew-rate = <0x00>;
				};

				rx-pins {
					pinmux = <0xe000406>;
					bias-disable;
					drive-strength = <0x02>;
					input-enable;
					input-schmitt-enable;
					slew-rate = <0x00>;
				};
			};

			tdm_pins: tdm-0 {
				phandle = <0x18>;

				tx-pins {
					pinmux = <0xff29002c>;
					bias-pull-up;
					drive-strength = <0x02>;
					input-disable;
					input-schmitt-disable;
					slew-rate = <0x00>;
				};

				rx-pins {
					pinmux = <0x2401043d>;
					input-enable;
				};

				sync-pins {
					pinmux = <0x2501043f>;
					input-enable;
				};

				pcmclk-pins {
					pinmux = <0x23010426>;
					input-enable;
				};
			};
		};

		watchdog: watchdog@13070000 {
			compatible = "starfive,jh7110-wdt";
			reg = <0x00 0x13070000 0x00 0x10000>;
			clocks = <&syscrg 0x7a>, <&syscrg 0x7b>;
			clock-names = "apb", "core";
			resets = <&syscrg 0x6d>, <&syscrg 0x6e>;
		};

		crypto: crypto@16000000 {
			compatible = "starfive,jh7110-crypto";
			reg = <0x00 0x16000000 0x00 0x4000>;
			clocks = <&stgcrg 0x0f>, <&stgcrg 0x10>;
			clock-names = "hclk", "ahb";
			interrupts = <0x1c>;
			resets = <&stgcrg 0x03>;
			dmas = <&sdma 0x01 0x02>, <&sdma 0x00 0x02>;
			dma-names = "tx", "rx";
		};

		sdma: dma-controller@16008000 {
			compatible = "arm,pl080", "arm,primecell";
			arm,primecell-periphid = <0x41080>;
			reg = <0x00 0x16008000 0x00 0x4000>;
			interrupts = <0x1d>;
			clocks = <&stgcrg 0x0f>;
			clock-names = "apb_pclk";
			resets = <&stgcrg 0x03>;
			lli-bus-interface-ahb1;
			mem-bus-interface-ahb1;
			memcpy-burst-size = <0x100>;
			memcpy-bus-width = <0x20>;
			#dma-cells = <0x02>;
			phandle = <0x27>;
		};

		rng: rng@1600c000 {
			compatible = "starfive,jh7110-trng";
			reg = <0x00 0x1600c000 0x00 0x4000>;
			clocks = <&stgcrg 0x0f>, <&stgcrg 0x10>;
			clock-names = "hclk", "ahb";
			resets = <&stgcrg 0x03>;
			interrupts = <0x1e>;
		};

		mmc0: mmc@16010000 {
			compatible = "starfive,jh7110-mmc";
			reg = <0x00 0x16010000 0x00 0x10000>;
			clocks = <&syscrg 0x5b>, <&syscrg 0x5d>;
			clock-names = "biu", "ciu";
			resets = <&syscrg 0x40>;
			reset-names = "reset";
			interrupts = <0x4a>;
			fifo-depth = <0x20>;
			fifo-watermark-aligned;
			data-addr = <0x00>;
			starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
			status = "okay";
			max-frequency = <0x5f5e100>;
			bus-width = <0x08>;
			cap-mmc-highspeed;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			non-removable;
			cap-mmc-hw-reset;
			post-power-on-delay-ms = <0xc8>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc0_pins>;
		};

		mmc1: mmc@16020000 {
			compatible = "starfive,jh7110-mmc";
			reg = <0x00 0x16020000 0x00 0x10000>;
			clocks = <&syscrg 0x5c>, <&syscrg 0x5e>;
			clock-names = "biu", "ciu";
			resets = <&syscrg 0x41>;
			reset-names = "reset";
			interrupts = <0x4b>;
			fifo-depth = <0x20>;
			fifo-watermark-aligned;
			data-addr = <0x00>;
			starfive,sysreg = <&sys_syscon 0x9c 0x01 0x3e>;
			status = "okay";
			max-frequency = <0x5f5e100>;
			bus-width = <0x04>;
			no-sdio;
			no-mmc;
			broken-cd;
			cap-sd-highspeed;
			post-power-on-delay-ms = <0xc8>;
			pinctrl-names = "default";
			pinctrl-0 = <&mmc1_pins>;
		};

		gmac0: ethernet@16030000 {
			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20", "snps,dwmac";
			reg = <0x00 0x16030000 0x00 0x10000>;
			clocks = <&aoncrg 0x03>, <&aoncrg 0x02>, <&syscrg 0x6d>, <&aoncrg 0x06>, <&syscrg 0x6f>;
			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
			resets = <&aoncrg 0x00>, <&aoncrg 0x01>;
			reset-names = "stmmaceth", "ahb";
			interrupts = <0x07>, <0x06>, <0x05>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			rx-fifo-depth = <0x800>;
			tx-fifo-depth = <0x800>;
			snps,multicast-filter-bins = <0x40>;
			snps,perfect-filter-entries = <0x100>;
			snps,fixed-burst;
			snps,no-pbl-x8;
			snps,force_thresh_dma_mode;
			snps,axi-config = <&stmmac_axi_setup>;
			snps,tso;
			snps,en-tx-lpi-clockgating;
			snps,txpbl = <0x10>;
			snps,rxpbl = <0x10>;
			starfive,syscon = <&aon_syscon 0x0c 0x12>;
			status = "okay";
			phy-mode = "rgmii-id";
		};

		gmac1: ethernet@16040000 {
			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20", "snps,dwmac";
			reg = <0x00 0x16040000 0x00 0x10000>;
			clocks = <&syscrg 0x62>, <&syscrg 0x61>, <&syscrg 0x66>, <&syscrg 0x6a>, <&syscrg 0x6b>;
			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
			resets = <&syscrg 0x42>, <&syscrg 0x43>;
			reset-names = "stmmaceth", "ahb";
			interrupts = <0x4e>, <0x4d>, <0x4c>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			rx-fifo-depth = <0x800>;
			tx-fifo-depth = <0x800>;
			snps,multicast-filter-bins = <0x40>;
			snps,perfect-filter-entries = <0x100>;
			snps,fixed-burst;
			snps,no-pbl-x8;
			snps,force_thresh_dma_mode;
			snps,axi-config = <&stmmac_axi_setup>;
			snps,tso;
			snps,en-tx-lpi-clockgating;
			snps,txpbl = <0x10>;
			snps,rxpbl = <0x10>;
			starfive,syscon = <&sys_syscon 0x90 0x02>;
			status = "okay";
			phy-mode = "rmii";
			assigned-clocks = <&syscrg 0x69>, <&syscrg 0x67>;
			assigned-clock-parents = <&syscrg 0x65>, <&syscrg 0x65>;
		};

		dma: dma-controller@16050000 {
			compatible = "starfive,jh7110-axi-dma", "snps,dw-axi-dmac";
			reg = <0x00 0x16050000 0x00 0x10000>;
			clocks = <&stgcrg 0x1b>, <&stgcrg 0x1c>;
			clock-names = "core-clk", "cfgr-clk";
			resets = <&stgcrg 0x05>, <&stgcrg 0x06>;
			interrupts = <0x49>;
			#dma-cells = <0x01>;
			dma-channels = <0x04>;
			snps,dma-masters = <0x01>;
			snps,data-width = <0x03>;
			snps,block-size = <0x10000 0x10000 0x10000 0x10000>;
			snps,priority = <0x00 0x01 0x02 0x03>;
			snps,axi-max-burst-len = <0x10>;
			phandle = <0x17>;
		};

		aoncrg: clock-controller@17000000 {
			compatible = "starfive,jh7110-aoncrg";
			reg = <0x00 0x17000000 0x00 0x10000>;
			clocks = <&osc>, <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, <&syscrg 0x08>, <&syscrg 0x0b>, <&syscrg 0x6c>, <&rtc_osc>;
			clock-names = "osc", "gmac0_rmii_refin", "gmac0_rgmii_rxin", "stg_axiahb", "apb_bus", "gmac0_gtxclk", "rtc_osc";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			phandle = <0x2d>;
		};

		aon_syscon: syscon@17010000 {
			compatible = "starfive,jh7110-aon-syscon", "syscon";
			reg = <0x00 0x17010000 0x00 0x1000>;
			#power-domain-cells = <0x01>;
			phandle = <0x2f>;
		};

		aongpio: pinctrl@17020000 {
			compatible = "starfive,jh7110-aon-pinctrl";
			reg = <0x00 0x17020000 0x00 0x10000>;
			resets = <&aoncrg 0x02>;
			interrupts = <0x55>;
			interrupt-controller;
			#interrupt-cells = <0x01>;
			gpio-controller;
			#gpio-cells = <0x02>;
		};

		pwrc: power-controller@17030000 {
			compatible = "starfive,jh7110-pmu";
			reg = <0x00 0x17030000 0x00 0x10000>;
			interrupts = <0x6f>;
			#power-domain-cells = <0x01>;
			phandle = <0x36>;
		};

		ispcrg: clock-controller@19810000 {
			compatible = "starfive,jh7110-ispcrg";
			reg = <0x00 0x19810000 0x00 0x10000>;
			clocks = <&syscrg 0x33>, <&syscrg 0x34>, <&syscrg 0x35>, <&dvp_clk>;
			clock-names = "isp_top_core", "isp_top_axi", "noc_bus_isp_axi", "dvp_clk";
			resets = <&syscrg 0x29>, <&syscrg 0x2a>, <&syscrg 0x1c>;
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			power-domains = <&pwrc 0x05>;
		};

		isp_syscon: syscon@19840000 {
			compatible = "starfive,jh7110-isp-syscon";
			reg = <0x00 0x19840000 0x00 0x10000>;
		};

		vout_syscon: syscon@295b0000 {
			compatible = "starfive,jh7110-vout-syscon";
			reg = <0x00 0x295b0000 0x00 0x10000>;
		};

		voutcrg: clock-controller@295c0000 {
			compatible = "starfive,jh7110-voutcrg";
			reg = <0x00 0x295c0000 0x00 0x10000>;
			clocks = <&syscrg 0x3a>, <&syscrg 0x3d>, <&syscrg 0x3e>, <&syscrg 0x3f>, <&syscrg 0xa5>, <&hdmitx0_pixelclk>;
			clock-names = "vout_src", "vout_top_ahb", "vout_top_axi", "vout_top_hdmitx0_mclk", "i2stx0_bclk", "hdmitx0_pixelclk";
			resets = <&syscrg 0x2b>;
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			power-domains = <&pwrc 0x04>;
		};

		mipitx_dphy: syscon@295e0000 {
			compatible = "starfive,jh7110-mipitx-dphy";
			reg = <0x00 0x295e0000 0x00 0x10000>;
		};
	};
};