StarFive VisionFive 2 v1.2A 0.1 From StarFive VisionFive 2 v1.2A,model device generator 8 32 clint RISC-V CLINT: clint 0x02000000 0x0 0x10000 registers 5 0x4 msip[%s] CLINT MSIP (Machine Software Interrupt) register 0x0 0x20 0x00000000 control [0:0] read-write 5 0x8 mtimecmp[%s] CLINT MTIMECMP (Machine Time Compare) register 0x4000 0x40 0x00000000 cycles [63:0] read-write 0 18446744073709551615 mtime CLINT MTIME (Machine Time) register 0xBFF8 0x40 0x00000000 cycles [63:0] read-write 0 18446744073709551615 l2pm SiFive U74(MC) L2 Performance Monitor: l2pm 0x02010000 0x0 0x4000 registers L2PM 1 L2PM1 2 L2PM2 3 L2PM3 4 cache_control L2 Cache Control registers. 0x0 config L2 Cache Control configuration. 0x0 0x20 0x060A1002 banks Number of banks in the cache. [7:0] read-only ways Number of ways per bank. [15:8] read-only lg_sets Base-2 logarithm of the sets per bank. [23:16] read-only lg_block_bytes Base-2 logarithm of the sets per bank. [31:24] read-only way_enable L2 Cache Control Way Enable register. Determines which ways of the Level 2 Cache Controller are enabled as cache. 0x8 0x20 0x00000000 way_enable The index of the largest way which has been enabled. May only be increased. [7:0] read-write 0 255 ecc_inject_error L2 Cache Control ECC Error Injection register. Can be used to insert an ECC error into either the backing data or metadata SRAM. 0x40 0x20 0x00000000 8 0x1 ecc_toggle_bit[%s] Toggle (corrupt) this bit index on the next cache operation. [0:0] read-write ecc_toggle_type Toggle (corrupt) this bit index on the next cache operation. [16:16] read-write true data ECC `data` type corruption. 0 directory ECC `directory` type corruption. 1 4 0x20 _dir_fix,_dir_fail,_data_fix,_data_fail ecc[%s] L2 Cache Control Directory ECC registers. Types: `dir_fix`: ECC directory fixes, `dir_fail`: ECC directory failures, `data_fix`: ECC data fixes, `data_fail`: ECC data failures. 0x100 2 0x4 _low,_high addr[%s] L2 Cache Control ECC Type Address registers. Contains the low- and high-address bits of the most recent failure. 0x0 0x20 0x00000000 addr ECC type most recent address to fail. [31:0] read-only count L2 Cache Control ECC Type Count register. Reports the number of times an ECC error occured. 0x8 0x20 0x00000000 count Reports the number of times an ECC error occured. [31:0] read-only _ecc_reserved L2 Cache Control ECC Type (`directory`, `data`) reserved register. 0x1C 0x20 0x00000000 flush L2 Cache Control Directory Flush registers. Can be used for flushing specific cache blocks. 0x200 flush64 L2 Cache Control Flush 64-bit register. Flushes the cache block at the 64-bit address written. 0x0 0x40 0x00000000 addr 64-bit address of the cache block to flush. [63:0] write-only 0 18446744073709551615 flush32 L2 Cache Control Flush 32-bit register. Flushes the cache block at the 32-bit address shifted left by 4 bytes. 0x40 0x20 0x00000000 addr 32-bit address of the cache block to flush. [31:0] write-only 0 4294967295 27 0x8 way_mask[%s] L2 Cache Control Way Mask registers. Configures the masks to enable cache bank ways. 0x800 bank L2 Cache Control Way Mask bank registers. Configures the masks to enable cache bank ways. 0x0 0x20 0x00000000 16 0x1 way_mask[%s] Way enable mask. [0:0] read-write _way_mask_reserved L2 Cache Control Way Mask reserved register. 0x4 0x20 0x00000000 event_control L2PM Event Control registers. 0x2000 6 0x8 event_select[%s] L2PM Event Control Event Select configuration. 0x0 0x40 0x00000001 event_class L2PM Event Class. [7:0] read-write true transaction L2PM transaction events. 1 l2_query_result L2PM L2 query result events. 2 l2_request L2PM L2 request events. 3 event_mask L2PM Event Mask for specifying the event type according to its `event_class`. [63:8] read-write 0 72057594037927935 client_filter L2PM Event Control Event Select configuration. 0x800 0x40 0x00000000 debug Disable counter events originating from `Debug` client. [0:0] read-write true enable Enable events from the client 0 disable Disable events from the client 1 4 0x1 axi4_front_port[%s] Disable counter events originating from `Debug` client. [1:1] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart0_fetch_unit Disable counter events originating from `Hart 0 Fetch Unit` client. [5:5] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart0_dcache_mmio Disable counter events originating from `Hart 0 D-Cache MMIO` client. [6:6] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart1_fetch_unit Disable counter events originating from `Hart 1 Fetch Unit` client. [7:7] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart1_icache Disable counter events originating from `Hart 1 I-Cache` client. [8:8] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart1_dcache Disable counter events originating from `Hart 1 D-Cache` client. [9:9] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart1_dcache_mmio Disable counter events originating from `Hart 1 D-Cache MMIO` client. [10:10] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart1_l2_prefetcher Disable counter events originating from `Hart 1 L2 Prefetcher` client. [11:11] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart2_fetch_unit Disable counter events originating from `Hart 2 Fetch Unit` client. [12:12] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart2_icache Disable counter events originating from `Hart 2 I-Cache` client. [13:13] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart2_dcache Disable counter events originating from `Hart 2 D-Cache` client. [14:14] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart2_dcache_mmio Disable counter events originating from `Hart 2 D-Cache MMIO` client. [15:15] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart2_l2_prefetcher Disable counter events originating from `Hart 2 L2 Prefetcher` client. [16:16] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart3_fetch_unit Disable counter events originating from `Hart 3 Fetch Unit` client. [17:17] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart3_icache Disable counter events originating from `Hart 3 I-Cache` client. [18:18] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart3_dcache Disable counter events originating from `Hart 3 D-Cache` client. [19:19] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart3_dcache_mmio Disable counter events originating from `Hart 3 D-Cache MMIO` client. [20:20] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart3_l2_prefetcher Disable counter events originating from `Hart 3 L2 Prefetcher` client. [21:21] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart4_fetch_unit Disable counter events originating from `Hart 4 Fetch Unit` client. [22:22] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart4_icache Disable counter events originating from `Hart 4 I-Cache` client. [23:23] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart4_dcache Disable counter events originating from `Hart 4 D-Cache` client. [24:24] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart4_dcache_mmio Disable counter events originating from `Hart 4 D-Cache MMIO` client. [25:25] read-write true enable Enable events from the client 0 disable Disable events from the client 1 hart4_l2_prefetcher Disable counter events originating from `Hart 4 L2 Prefetcher` client. [26:26] read-write true enable Enable events from the client 0 disable Disable events from the client 1 6 0x8 event_counter[%s] L2PM Event Control Event Select configuration. 0x3000 0x40 0x00000000 counter L2PM Event Counter. [63:0] read-only sram SiFive U74(MC) SRAM (L2 LIM): sram 0x08000000 0x0 0x200000 registers 524288 0x4 word[%s] SiFive U74(MC) SRAM (L2 LIM) word 0x0 0x20 0x00000000 word SiFive U74(MC) SRAM (L2 LIM) word [31:0] read-write 0 4294967295 plic RISC-V PLIC: plic 0x0C000000 0x0 0x4000000 registers 136 0x4 priority[%s] RISC-V PLIC Interrupt Source Priority. 0x4 0x20 0x00000000 priority Represents interrupt source priority: `0` is reserved to mean `never interrupt`, and interrupt priority increases with increasing integer values. [31:0] read-write 0 4294967295 5 0x4 pending[%s] RISC-V PLIC Pending: 32-bit register indicating if there is a pending interrupt, e.g. pending[0][0] is interrupt 0, pending[0][31] is interrupt 31, pending[1][0] is interrupt 32. 0x1000 0x20 0x00000000 32 0x1 pending[%s] Bit index that indicates whether the interrupt source is pending [0:0] read-write true clear The interrupt source has no pending interrupt 0 pending The interrupt source has a pending interrupt 1 5 0x80 enable[%s] PLIC interrupt enable registers (per-HART) 0x2000 5 0x4 enable_bits[%s] Interrupt source enable bits. 0x0 0x20 0x00000000 32 0x1 enable[%s] Enables the interrupt source associated with the bit index. [0:0] read-write _enable_reserved PLIC Enable Reserved register used for alignment. 0x7C 0x20 0x00000000 5 0x1000 threshold_claim[%s] PLIC threshold and claim_complete registers 0x200000 threshold Interrupt priority threshold of each context. 0x0 0x20 0x00000000 threshold The PLIC will mask all PLIC interrupts of a priority less than or equal to `threshold`. [31:0] read-write 0 4294967295 claim_complete Interrupt source `claim` (read) and complete (write) register. The PLIC will write pending interrupt source information to the `claim` register. When the interrupt handler is finished, the interrupt source idendification should be written to the corresponding `complete` register. 0x4 0x20 0x00000000 claim Claim interrupt source ID of highest-priority pending interrupt. Value of `0` indicates no pending interrupt. [31:0] read-only complete Completes handling for interrupt source ID. [31:0] write-only 0 4294967295 _threshold_reserved PLIC Threshold Reserved register used for alignment. 0xFFC 0x20 0x00000000 uart0 Synopsys DesignWare APB UART: uart0 0x10000000 0x0 0x10000 registers UART0 32 rbr Receive Buffer Register 0x0 0x20 0x00000000 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 0x20 0x00000000 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 dll Divisor Latch Low 0x0 0x20 0x00000000 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 dlh Divisor Latch High 0x4 0x20 0x00000000 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 ier Interrupt Enable Register 0x4 0x20 0x00000000 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write true disable Programmable THRE Interrupt Mode disabled 0 enable Programmable THRE Interrupt Mode enabled 1 edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write true disable Modem Status Interrupt disabled 0 enable Modem Status Interrupt enabled 1 elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write true disable Enable Receiver Line Status Interrupt disabled 0 enable Enable Receiver Line Status Interrupt enabled 1 etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write true disable Enable Transmit Holding Register Empty Interrupt disabled 0 enable Enable Transmit Holding Register Empty Interrupt enabled 1 erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write true disable Enable Received Data Available Interrupt disabled 0 enable Enable Received Data Available Interrupt enabled 1 iir Interrupt Identity Register 0x8 0x20 0x00000001 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only true disabled FIFOs are disabled 0 enabled FIFOs are enabled 3 iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only true modem_status Modem status interrupt pending 0 none_pending No interrupt pending 1 thr_empty THR empty 2 data_available Received data available 4 receiver_line_status Receiver line status 6 busy_detect Busy detect 7 character_timeout Character timeout 12 fcr FIFO Control Register 0x8 0x20 0x00000000 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only true near_empty Trigger when 1 character in the FIFO 0 quarter Trigger when FIFO is 1/4 full 1 half Trigger when FIFO is 1/2 full 2 near_full Trigger when FIFO is 2 bytes less than full 3 tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only true empty Trigger FIFO when empty 0 near_empty Trigger when 2 characters in the FIFO 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only true mode0 Mode 0 0 mode1 Mode 1 1 xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xC 0x20 0x00000000 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write true bit1 1 stop bit 0 bit2 1.5 stop bits when LCR is zero, else 2 stop bits 1 dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write true five Data length 5-bits 0 six Data length 6-bits 1 seven Data length 7-bits 2 eight Data length 8-bits 3 mcr Modem Control Register 0x10 0x20 0x00000000 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 0x20 0x00000000 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Modem Status Register 0x18 0x20 0x00000000 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1C 0x20 0x00000000 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write 0 255 lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 0x20 0x00000000 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 0x20 0x00000000 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write 0 255 16 0x4 shadow[%s] This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). 0x30 0x20 0x00000000 srbr Shadow Receive Buffer Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr Shadow Threshold Register: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 far FIFO Access Register 0x70 0x20 0x00000000 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 0x20 0x00000000 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 0x20 0x00000000 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only 0 255 usr UART Status Register 0x7C 0x20 0x00000000 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 0x20 0x00000000 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 0x20 0x00000000 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 0x20 0x00000000 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8C 0x20 0x00000000 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 0x20 0x00000000 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 0x20 0x00000000 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 0x20 0x00000000 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9C 0x20 0x00000000 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write true near_empty Trigger when the FIFO has 1 character left 0 quarter Trigger when the FIFO is 1/4 full 1 half Trigger when the FIFO is 1/2 full 2 near_full Trigger when the FIFO is 2 bytes less than full 3 stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xA0 0x20 0x00000000 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write true empty Trigger when FIFO is empty 0 near_empty Trigger when FIFO has two characters 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 htx Halt TX 0xA4 0x20 0x00000000 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xA8 0x20 0x00000000 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xF4 0x20 0x00000000 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only true bits0 0-bit FIFO mode 0 bits16 16-bit FIFO mode 1 bits32 32-bit FIFO mode 2 bits2048 2048-bit FIFO mode 128 dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only true bits8 8-bit data width 0 bits16 16-bit data width 1 bits32 32-bit data width 2 ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x00000000 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x44570110 ctr This register contains the peripherals identification code. [31:0] read-only uart1 Synopsys DesignWare APB UART: uart1 0x10010000 0x0 0x10000 registers UART1 33 rbr Receive Buffer Register 0x0 0x20 0x00000000 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 0x20 0x00000000 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 dll Divisor Latch Low 0x0 0x20 0x00000000 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 dlh Divisor Latch High 0x4 0x20 0x00000000 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 ier Interrupt Enable Register 0x4 0x20 0x00000000 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write true disable Programmable THRE Interrupt Mode disabled 0 enable Programmable THRE Interrupt Mode enabled 1 edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write true disable Modem Status Interrupt disabled 0 enable Modem Status Interrupt enabled 1 elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write true disable Enable Receiver Line Status Interrupt disabled 0 enable Enable Receiver Line Status Interrupt enabled 1 etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write true disable Enable Transmit Holding Register Empty Interrupt disabled 0 enable Enable Transmit Holding Register Empty Interrupt enabled 1 erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write true disable Enable Received Data Available Interrupt disabled 0 enable Enable Received Data Available Interrupt enabled 1 iir Interrupt Identity Register 0x8 0x20 0x00000001 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only true disabled FIFOs are disabled 0 enabled FIFOs are enabled 3 iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only true modem_status Modem status interrupt pending 0 none_pending No interrupt pending 1 thr_empty THR empty 2 data_available Received data available 4 receiver_line_status Receiver line status 6 busy_detect Busy detect 7 character_timeout Character timeout 12 fcr FIFO Control Register 0x8 0x20 0x00000000 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only true near_empty Trigger when 1 character in the FIFO 0 quarter Trigger when FIFO is 1/4 full 1 half Trigger when FIFO is 1/2 full 2 near_full Trigger when FIFO is 2 bytes less than full 3 tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only true empty Trigger FIFO when empty 0 near_empty Trigger when 2 characters in the FIFO 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only true mode0 Mode 0 0 mode1 Mode 1 1 xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xC 0x20 0x00000000 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write true bit1 1 stop bit 0 bit2 1.5 stop bits when LCR is zero, else 2 stop bits 1 dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write true five Data length 5-bits 0 six Data length 6-bits 1 seven Data length 7-bits 2 eight Data length 8-bits 3 mcr Modem Control Register 0x10 0x20 0x00000000 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 0x20 0x00000000 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Modem Status Register 0x18 0x20 0x00000000 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1C 0x20 0x00000000 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write 0 255 lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 0x20 0x00000000 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 0x20 0x00000000 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write 0 255 16 0x4 shadow[%s] This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). 0x30 0x20 0x00000000 srbr Shadow Receive Buffer Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr Shadow Threshold Register: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 far FIFO Access Register 0x70 0x20 0x00000000 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 0x20 0x00000000 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 0x20 0x00000000 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only 0 255 usr UART Status Register 0x7C 0x20 0x00000000 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 0x20 0x00000000 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 0x20 0x00000000 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 0x20 0x00000000 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8C 0x20 0x00000000 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 0x20 0x00000000 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 0x20 0x00000000 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 0x20 0x00000000 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9C 0x20 0x00000000 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write true near_empty Trigger when the FIFO has 1 character left 0 quarter Trigger when the FIFO is 1/4 full 1 half Trigger when the FIFO is 1/2 full 2 near_full Trigger when the FIFO is 2 bytes less than full 3 stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xA0 0x20 0x00000000 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write true empty Trigger when FIFO is empty 0 near_empty Trigger when FIFO has two characters 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 htx Halt TX 0xA4 0x20 0x00000000 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xA8 0x20 0x00000000 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xF4 0x20 0x00000000 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only true bits0 0-bit FIFO mode 0 bits16 16-bit FIFO mode 1 bits32 32-bit FIFO mode 2 bits2048 2048-bit FIFO mode 128 dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only true bits8 8-bit data width 0 bits16 16-bit data width 1 bits32 32-bit data width 2 ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x00000000 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x44570110 ctr This register contains the peripherals identification code. [31:0] read-only uart2 Synopsys DesignWare APB UART: uart2 0x10020000 0x0 0x10000 registers UART2 34 rbr Receive Buffer Register 0x0 0x20 0x00000000 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 0x20 0x00000000 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 dll Divisor Latch Low 0x0 0x20 0x00000000 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 dlh Divisor Latch High 0x4 0x20 0x00000000 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 ier Interrupt Enable Register 0x4 0x20 0x00000000 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write true disable Programmable THRE Interrupt Mode disabled 0 enable Programmable THRE Interrupt Mode enabled 1 edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write true disable Modem Status Interrupt disabled 0 enable Modem Status Interrupt enabled 1 elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write true disable Enable Receiver Line Status Interrupt disabled 0 enable Enable Receiver Line Status Interrupt enabled 1 etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write true disable Enable Transmit Holding Register Empty Interrupt disabled 0 enable Enable Transmit Holding Register Empty Interrupt enabled 1 erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write true disable Enable Received Data Available Interrupt disabled 0 enable Enable Received Data Available Interrupt enabled 1 iir Interrupt Identity Register 0x8 0x20 0x00000001 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only true disabled FIFOs are disabled 0 enabled FIFOs are enabled 3 iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only true modem_status Modem status interrupt pending 0 none_pending No interrupt pending 1 thr_empty THR empty 2 data_available Received data available 4 receiver_line_status Receiver line status 6 busy_detect Busy detect 7 character_timeout Character timeout 12 fcr FIFO Control Register 0x8 0x20 0x00000000 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only true near_empty Trigger when 1 character in the FIFO 0 quarter Trigger when FIFO is 1/4 full 1 half Trigger when FIFO is 1/2 full 2 near_full Trigger when FIFO is 2 bytes less than full 3 tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only true empty Trigger FIFO when empty 0 near_empty Trigger when 2 characters in the FIFO 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only true mode0 Mode 0 0 mode1 Mode 1 1 xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xC 0x20 0x00000000 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write true bit1 1 stop bit 0 bit2 1.5 stop bits when LCR is zero, else 2 stop bits 1 dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write true five Data length 5-bits 0 six Data length 6-bits 1 seven Data length 7-bits 2 eight Data length 8-bits 3 mcr Modem Control Register 0x10 0x20 0x00000000 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 0x20 0x00000000 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Modem Status Register 0x18 0x20 0x00000000 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1C 0x20 0x00000000 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write 0 255 lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 0x20 0x00000000 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 0x20 0x00000000 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write 0 255 16 0x4 shadow[%s] This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). 0x30 0x20 0x00000000 srbr Shadow Receive Buffer Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr Shadow Threshold Register: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 far FIFO Access Register 0x70 0x20 0x00000000 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 0x20 0x00000000 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 0x20 0x00000000 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only 0 255 usr UART Status Register 0x7C 0x20 0x00000000 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 0x20 0x00000000 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 0x20 0x00000000 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 0x20 0x00000000 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8C 0x20 0x00000000 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 0x20 0x00000000 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 0x20 0x00000000 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 0x20 0x00000000 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9C 0x20 0x00000000 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write true near_empty Trigger when the FIFO has 1 character left 0 quarter Trigger when the FIFO is 1/4 full 1 half Trigger when the FIFO is 1/2 full 2 near_full Trigger when the FIFO is 2 bytes less than full 3 stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xA0 0x20 0x00000000 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write true empty Trigger when FIFO is empty 0 near_empty Trigger when FIFO has two characters 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 htx Halt TX 0xA4 0x20 0x00000000 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xA8 0x20 0x00000000 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xF4 0x20 0x00000000 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only true bits0 0-bit FIFO mode 0 bits16 16-bit FIFO mode 1 bits32 32-bit FIFO mode 2 bits2048 2048-bit FIFO mode 128 dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only true bits8 8-bit data width 0 bits16 16-bit data width 1 bits32 32-bit data width 2 ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x00000000 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x44570110 ctr This register contains the peripherals identification code. [31:0] read-only i2c0 Synopsys DesignWare APB I2C: i2c0 0x10030000 0x0 0x10000 registers I2C0 35 i2c_con DesignWare I2C CON 0x0 0x20 0x00000002 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write true slave I2C slave connection 0 master I2C master connection 1 speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write true standard Standard speed 1 fast Fast speed 2 high High speed 3 slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write true clear Do not enable restart 0 set Enable restart 1 slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write true clear Do not disable 0 set Disable 1 stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write true clear Do not stop DET if addressed 0 set Stop DET if addressed 1 tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write true clear Do not empty TX 0 set Empty TX 1 rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write true clear RX FIFO does not use full HID control 0 set RX FIFO uses full HID control 1 bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write true clear Do not clear the bus 0 set Clear the bus 1 tar DesignWare I2C TAR 0x4 0x20 0x00000000 address_7bit Target address, 7-bit mode [6:0] read-write 0 127 address_10bit Target address, 10-bit mode [9:0] read-write 0 1023 mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write true seven_bit 7-bit address mode 0 ten_bit 10-bit address mode 1 sar DesignWare I2C SAR 0x8 0x20 0x00000000 address_7bit Slave address, 7-bit mode [6:0] read-write 0 127 address_10bit Slave address, 10-bit mode [9:0] read-write 0 1023 data_cmd DesignWare I2C Data Command 0x10 0x20 0x00000000 dat Data Command Data Byte [7:0] read-write 0 255 read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 0x20 0x00000000 ss_scl_hcnt [15:0] read-write 0 65535 ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 0x20 0x00000000 ss_scl_lcnt [15:0] read-write 0 65535 fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1C 0x20 0x00000000 fs_scl_hcnt [15:0] read-write 0 65535 fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 0x20 0x00000000 fs_scl_lcnt [15:0] read-write 0 65535 hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 0x20 0x00000000 hs_scl_hcnt [15:0] read-write 0 65535 hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 0x20 0x00000000 hs_scl_lcnt [15:0] read-write 0 65535 intr_stat DesignWare I2C Interrupt Status 0x2C 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 0x20 0x00000000 rx_tl [7:0] read-write 0 255 tx_tl DesignWare I2C TX TL 0x3C 0x20 0x00000000 tx_tl [7:0] read-write 0 255 clr_intr DesignWare I2C Clear Interrrupt 0x40 0x20 0x00000000 clr_intr [0:0] read-only clr_rx_under DesignWare I2C Clear RX Underrun 0x44 0x20 0x00000000 clr_rx_under [0:0] read-only clr_rx_over DesignWare I2C Clear RX Overrun 0x48 0x20 0x00000000 clr_rx_over [0:0] read-only clr_tx_over DesignWare I2C Clear TX Overrun 0x4C 0x20 0x00000000 clr_tx_over [0:0] read-only clr_rd_req DesignWare I2C Clear Read Request 0x50 0x20 0x00000000 clr_rd_req [0:0] read-only clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 0x20 0x00000000 clr_tx_abrt [0:0] read-only clr_rx_done DesignWare I2C Clear RX Done 0x58 0x20 0x00000000 clr_rx_done [0:0] read-only clr_activity DesignWare I2C Clear Activity 0x5C 0x20 0x00000000 clr_activity [0:0] read-only clr_stop_det DesignWare I2C Clear Stop DET 0x60 0x20 0x00000000 clr_stop_det [0:0] read-only clr_start_det DesignWare I2C Clear Start DET 0x64 0x20 0x00000000 clr_start_det [0:0] read-only clr_gen_call DesignWare I2C Clear General Call 0x68 0x20 0x00000000 clr_gen_call [0:0] read-only enable DesignWare I2C Enable 0x6C 0x20 0x00000000 abort [1:1] read-write status DesignWare I2C Status 0x70 0x20 0x00000000 activity [0:0] read-only tfe [2:2] read-only rfne [3:3] read-only master_activity [5:5] read-only slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 0x20 0x00000000 txflr [31:0] read-only rxflr DesignWare I2C RX Failure 0x78 0x20 0x00000000 rxflr [31:0] read-only sda_hold DesignWare I2C SDA Hold 0x7C 0x20 0x00000000 sda_hold [23:0] read-write 0 16777215 tx_abrt_source DesignWare I2C TX Abort Source 0x80 0x20 0x00000000 b7_addr_noack [0:0] read-only b10_addr1_noack [1:1] read-only b10_addr2_noack [2:2] read-only txdata_noack [3:3] read-only gcall_noack [4:4] read-only gcall_read [5:5] read-only sbyte_ackdet [7:7] read-only sbyte_norstrt [9:9] read-only b10_rd_norstrt [10:10] read-only master_dis [11:11] read-only arb_lost [12:12] read-only slave_flush_txfifo [13:13] read-only slave_arblost [14:14] read-only slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9C 0x20 0x00000000 activity [0:0] read-write tfe [2:2] read-write rfne [3:3] read-write master_activity [5:5] read-write slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xA8 0x20 0x00000000 clr_restart_det [0:0] read-only comp_param_1 DesignWare I2C Compatibility Parameter 1 0xF4 0x20 0x00000000 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only true standard Standard speed 1 full Full speed 2 high High speed 3 comp_version DesignWare I2C Compatibility Version 0xF8 0x20 0x00000000 comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xFC 0x20 0x44570140 comp_type [31:0] read-only i2c1 Synopsys DesignWare APB I2C: i2c1 0x10040000 0x0 0x10000 registers I2C1 36 i2c_con DesignWare I2C CON 0x0 0x20 0x00000002 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write true slave I2C slave connection 0 master I2C master connection 1 speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write true standard Standard speed 1 fast Fast speed 2 high High speed 3 slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write true clear Do not enable restart 0 set Enable restart 1 slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write true clear Do not disable 0 set Disable 1 stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write true clear Do not stop DET if addressed 0 set Stop DET if addressed 1 tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write true clear Do not empty TX 0 set Empty TX 1 rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write true clear RX FIFO does not use full HID control 0 set RX FIFO uses full HID control 1 bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write true clear Do not clear the bus 0 set Clear the bus 1 tar DesignWare I2C TAR 0x4 0x20 0x00000000 address_7bit Target address, 7-bit mode [6:0] read-write 0 127 address_10bit Target address, 10-bit mode [9:0] read-write 0 1023 mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write true seven_bit 7-bit address mode 0 ten_bit 10-bit address mode 1 sar DesignWare I2C SAR 0x8 0x20 0x00000000 address_7bit Slave address, 7-bit mode [6:0] read-write 0 127 address_10bit Slave address, 10-bit mode [9:0] read-write 0 1023 data_cmd DesignWare I2C Data Command 0x10 0x20 0x00000000 dat Data Command Data Byte [7:0] read-write 0 255 read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 0x20 0x00000000 ss_scl_hcnt [15:0] read-write 0 65535 ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 0x20 0x00000000 ss_scl_lcnt [15:0] read-write 0 65535 fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1C 0x20 0x00000000 fs_scl_hcnt [15:0] read-write 0 65535 fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 0x20 0x00000000 fs_scl_lcnt [15:0] read-write 0 65535 hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 0x20 0x00000000 hs_scl_hcnt [15:0] read-write 0 65535 hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 0x20 0x00000000 hs_scl_lcnt [15:0] read-write 0 65535 intr_stat DesignWare I2C Interrupt Status 0x2C 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 0x20 0x00000000 rx_tl [7:0] read-write 0 255 tx_tl DesignWare I2C TX TL 0x3C 0x20 0x00000000 tx_tl [7:0] read-write 0 255 clr_intr DesignWare I2C Clear Interrrupt 0x40 0x20 0x00000000 clr_intr [0:0] read-only clr_rx_under DesignWare I2C Clear RX Underrun 0x44 0x20 0x00000000 clr_rx_under [0:0] read-only clr_rx_over DesignWare I2C Clear RX Overrun 0x48 0x20 0x00000000 clr_rx_over [0:0] read-only clr_tx_over DesignWare I2C Clear TX Overrun 0x4C 0x20 0x00000000 clr_tx_over [0:0] read-only clr_rd_req DesignWare I2C Clear Read Request 0x50 0x20 0x00000000 clr_rd_req [0:0] read-only clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 0x20 0x00000000 clr_tx_abrt [0:0] read-only clr_rx_done DesignWare I2C Clear RX Done 0x58 0x20 0x00000000 clr_rx_done [0:0] read-only clr_activity DesignWare I2C Clear Activity 0x5C 0x20 0x00000000 clr_activity [0:0] read-only clr_stop_det DesignWare I2C Clear Stop DET 0x60 0x20 0x00000000 clr_stop_det [0:0] read-only clr_start_det DesignWare I2C Clear Start DET 0x64 0x20 0x00000000 clr_start_det [0:0] read-only clr_gen_call DesignWare I2C Clear General Call 0x68 0x20 0x00000000 clr_gen_call [0:0] read-only enable DesignWare I2C Enable 0x6C 0x20 0x00000000 abort [1:1] read-write status DesignWare I2C Status 0x70 0x20 0x00000000 activity [0:0] read-only tfe [2:2] read-only rfne [3:3] read-only master_activity [5:5] read-only slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 0x20 0x00000000 txflr [31:0] read-only rxflr DesignWare I2C RX Failure 0x78 0x20 0x00000000 rxflr [31:0] read-only sda_hold DesignWare I2C SDA Hold 0x7C 0x20 0x00000000 sda_hold [23:0] read-write 0 16777215 tx_abrt_source DesignWare I2C TX Abort Source 0x80 0x20 0x00000000 b7_addr_noack [0:0] read-only b10_addr1_noack [1:1] read-only b10_addr2_noack [2:2] read-only txdata_noack [3:3] read-only gcall_noack [4:4] read-only gcall_read [5:5] read-only sbyte_ackdet [7:7] read-only sbyte_norstrt [9:9] read-only b10_rd_norstrt [10:10] read-only master_dis [11:11] read-only arb_lost [12:12] read-only slave_flush_txfifo [13:13] read-only slave_arblost [14:14] read-only slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9C 0x20 0x00000000 activity [0:0] read-write tfe [2:2] read-write rfne [3:3] read-write master_activity [5:5] read-write slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xA8 0x20 0x00000000 clr_restart_det [0:0] read-only comp_param_1 DesignWare I2C Compatibility Parameter 1 0xF4 0x20 0x00000000 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only true standard Standard speed 1 full Full speed 2 high High speed 3 comp_version DesignWare I2C Compatibility Version 0xF8 0x20 0x00000000 comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xFC 0x20 0x44570140 comp_type [31:0] read-only i2c2 Synopsys DesignWare APB I2C: i2c2 0x10050000 0x0 0x10000 registers I2C2 37 i2c_con DesignWare I2C CON 0x0 0x20 0x00000002 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write true slave I2C slave connection 0 master I2C master connection 1 speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write true standard Standard speed 1 fast Fast speed 2 high High speed 3 slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write true clear Do not enable restart 0 set Enable restart 1 slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write true clear Do not disable 0 set Disable 1 stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write true clear Do not stop DET if addressed 0 set Stop DET if addressed 1 tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write true clear Do not empty TX 0 set Empty TX 1 rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write true clear RX FIFO does not use full HID control 0 set RX FIFO uses full HID control 1 bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write true clear Do not clear the bus 0 set Clear the bus 1 tar DesignWare I2C TAR 0x4 0x20 0x00000000 address_7bit Target address, 7-bit mode [6:0] read-write 0 127 address_10bit Target address, 10-bit mode [9:0] read-write 0 1023 mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write true seven_bit 7-bit address mode 0 ten_bit 10-bit address mode 1 sar DesignWare I2C SAR 0x8 0x20 0x00000000 address_7bit Slave address, 7-bit mode [6:0] read-write 0 127 address_10bit Slave address, 10-bit mode [9:0] read-write 0 1023 data_cmd DesignWare I2C Data Command 0x10 0x20 0x00000000 dat Data Command Data Byte [7:0] read-write 0 255 read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 0x20 0x00000000 ss_scl_hcnt [15:0] read-write 0 65535 ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 0x20 0x00000000 ss_scl_lcnt [15:0] read-write 0 65535 fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1C 0x20 0x00000000 fs_scl_hcnt [15:0] read-write 0 65535 fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 0x20 0x00000000 fs_scl_lcnt [15:0] read-write 0 65535 hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 0x20 0x00000000 hs_scl_hcnt [15:0] read-write 0 65535 hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 0x20 0x00000000 hs_scl_lcnt [15:0] read-write 0 65535 intr_stat DesignWare I2C Interrupt Status 0x2C 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 0x20 0x00000000 rx_tl [7:0] read-write 0 255 tx_tl DesignWare I2C TX TL 0x3C 0x20 0x00000000 tx_tl [7:0] read-write 0 255 clr_intr DesignWare I2C Clear Interrrupt 0x40 0x20 0x00000000 clr_intr [0:0] read-only clr_rx_under DesignWare I2C Clear RX Underrun 0x44 0x20 0x00000000 clr_rx_under [0:0] read-only clr_rx_over DesignWare I2C Clear RX Overrun 0x48 0x20 0x00000000 clr_rx_over [0:0] read-only clr_tx_over DesignWare I2C Clear TX Overrun 0x4C 0x20 0x00000000 clr_tx_over [0:0] read-only clr_rd_req DesignWare I2C Clear Read Request 0x50 0x20 0x00000000 clr_rd_req [0:0] read-only clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 0x20 0x00000000 clr_tx_abrt [0:0] read-only clr_rx_done DesignWare I2C Clear RX Done 0x58 0x20 0x00000000 clr_rx_done [0:0] read-only clr_activity DesignWare I2C Clear Activity 0x5C 0x20 0x00000000 clr_activity [0:0] read-only clr_stop_det DesignWare I2C Clear Stop DET 0x60 0x20 0x00000000 clr_stop_det [0:0] read-only clr_start_det DesignWare I2C Clear Start DET 0x64 0x20 0x00000000 clr_start_det [0:0] read-only clr_gen_call DesignWare I2C Clear General Call 0x68 0x20 0x00000000 clr_gen_call [0:0] read-only enable DesignWare I2C Enable 0x6C 0x20 0x00000000 abort [1:1] read-write status DesignWare I2C Status 0x70 0x20 0x00000000 activity [0:0] read-only tfe [2:2] read-only rfne [3:3] read-only master_activity [5:5] read-only slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 0x20 0x00000000 txflr [31:0] read-only rxflr DesignWare I2C RX Failure 0x78 0x20 0x00000000 rxflr [31:0] read-only sda_hold DesignWare I2C SDA Hold 0x7C 0x20 0x00000000 sda_hold [23:0] read-write 0 16777215 tx_abrt_source DesignWare I2C TX Abort Source 0x80 0x20 0x00000000 b7_addr_noack [0:0] read-only b10_addr1_noack [1:1] read-only b10_addr2_noack [2:2] read-only txdata_noack [3:3] read-only gcall_noack [4:4] read-only gcall_read [5:5] read-only sbyte_ackdet [7:7] read-only sbyte_norstrt [9:9] read-only b10_rd_norstrt [10:10] read-only master_dis [11:11] read-only arb_lost [12:12] read-only slave_flush_txfifo [13:13] read-only slave_arblost [14:14] read-only slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9C 0x20 0x00000000 activity [0:0] read-write tfe [2:2] read-write rfne [3:3] read-write master_activity [5:5] read-write slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xA8 0x20 0x00000000 clr_restart_det [0:0] read-only comp_param_1 DesignWare I2C Compatibility Parameter 1 0xF4 0x20 0x00000000 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only true standard Standard speed 1 full Full speed 2 high High speed 3 comp_version DesignWare I2C Compatibility Version 0xF8 0x20 0x00000000 comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xFC 0x20 0x44570140 comp_type [31:0] read-only spi0 ARM pl022 SSP SPI: spi0 0x10060000 0x0 0x10000 registers SPI0 38 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 0x10 0x00000000 dss Data Size Select [3:0] read-write true four Data size select: 4-bit 3 five Data size select: 5-bit 4 six Data size select: 6-bit 5 seven Data size select: 7-bit 6 eight Data size select: 8-bit 7 nine Data size select: 9-bit 8 ten Data size select: 10-bit 9 eleven Data size select: 11-bit 10 twelve Data size select: 12-bit 11 thirteen Data size select: 13-bit 12 fourteen Data size select: 14-bit 13 fifteen Data size select: 15-bit 14 sixteen Data size select: 16-bit 15 frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write true spi Frame format: Motorola SPI 0 sync_serial Frame format: TI synchronous serial 1 microwire Frame format: National Microwire 2 spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write true low SSPCLKOUT polarity: steady state low 0 high SSPCLKOUT polarity: steady state high 1 sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [7:7] read-write true first_edge SSPCLKOUT phase: data captured on first clock edge 0 second_edge SSPCLKOUT phase: data captured on second clock edge 1 scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write 0 255 ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 0x10 0x00000000 lbm Loop back mode [0:0] read-write true normal Loop back mode: normal serial port operation 0 shifter Loop back mode: output of transmit serial shifter is connected to input of receive serial shifter internally 1 sse Synchronous serial port enable [1:1] read-write true disabled Synchronous serial port: disabled 0 enabled Synchronous serial port: enabled 1 ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0. [2:2] read-write true master Mode select: master 0 slave Mode select: slave 1 sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write true drive SSPTXD output disable: SSP can drive the SSPTXD output 0 no_drive SSPTXD output disable: SSP must not drive the SSPTXD output 1 ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 0x10 0x00000000 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write 0 65535 ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xC 0x10 0x00000000 tfe Transmit FIFO empty. [0:0] read-only true not_empty Transmit FIFO is not empty 0 empty Transmit FIFO is empty 1 tnf Transmit FIFO not full. [1:1] read-only true full Transmit FIFO is full 0 not_full Transmit FIFO is not full 1 rne Receive FIFO not empty. [2:2] read-only true empty Receive FIFO is empty 0 not_empty Receive FIFO is not empty 1 rff Receive FIFO full. [3:3] read-only true not_full Receive FIFO is not full 0 full Receive FIFO is full 1 bsy PrimeCell SSP busy flag. [4:4] read-only true idle SSP is idle 0 busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 0x10 0x00000000 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write 2 254 ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 0x10 0x00000000 rorim Receive overrun interrupt mask [0:0] read-write true masked Receive FIFO written to while full condition interrupt is masked 0 not_masked Receive FIFO written to while full condition interrupt is not masked 1 rtim Receive timeout interrupt mask [1:1] read-write true masked Receive FIFO not empty and no read prior to timeout period interrupt is masked 0 not_masked Receive FIFO not empty and no read prior to timeout period interrupt is not masked 1 rxim Receive FIFO interrupt mask [2:2] read-write true masked Receive FIFO half full or less condition interrupt is masked 0 not_masked Receive FIFO half full or less condition interrupt is not masked 1 txim Transmit FIFO interrupt mask [3:3] read-write true masked Transmit FIFO half empty or less condition interrupt is masked 0 not_masked Transmit FIFO half empty or less condition interrupt is not masked 1 ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 0x10 0x00000000 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1C 0x10 0x00000000 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 0x10 0x00000000 roric Clears the SSPRORINTR interrupt [0:0] read-write true nop SSPRORINTR receive interrupt clear: no-op 0 clear SSPRORINTR receive interrupt clear: clear 1 rtic Clears the SSPRTINTR interrupt [1:1] read-write true nop SSPRTINTR transmit interrupt clear: no-op 0 clear SSPRTINTR transmit interrupt clear: clear 1 ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 0x10 0x00000000 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE0 0x10 0x00000000 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE4 0x10 0x00000000 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE8 0x10 0x00000000 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFEC 0x10 0x00000000 configuration These bits read back as 0x80 [7:0] read-only 4 0x4 ssp_pcell_id[%s] The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xFF0 0x10 0x00000000 ssp_pcell_id The bits of the SSPCELLID are read as: [0x0d, 0xf0, 0x05, 0xb1] [7:0] read-only spi1 ARM pl022 SSP SPI: spi1 0x10070000 0x0 0x10000 registers SPI1 39 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 0x10 0x00000000 dss Data Size Select [3:0] read-write true four Data size select: 4-bit 3 five Data size select: 5-bit 4 six Data size select: 6-bit 5 seven Data size select: 7-bit 6 eight Data size select: 8-bit 7 nine Data size select: 9-bit 8 ten Data size select: 10-bit 9 eleven Data size select: 11-bit 10 twelve Data size select: 12-bit 11 thirteen Data size select: 13-bit 12 fourteen Data size select: 14-bit 13 fifteen Data size select: 15-bit 14 sixteen Data size select: 16-bit 15 frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write true spi Frame format: Motorola SPI 0 sync_serial Frame format: TI synchronous serial 1 microwire Frame format: National Microwire 2 spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write true low SSPCLKOUT polarity: steady state low 0 high SSPCLKOUT polarity: steady state high 1 sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [7:7] read-write true first_edge SSPCLKOUT phase: data captured on first clock edge 0 second_edge SSPCLKOUT phase: data captured on second clock edge 1 scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write 0 255 ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 0x10 0x00000000 lbm Loop back mode [0:0] read-write true normal Loop back mode: normal serial port operation 0 shifter Loop back mode: output of transmit serial shifter is connected to input of receive serial shifter internally 1 sse Synchronous serial port enable [1:1] read-write true disabled Synchronous serial port: disabled 0 enabled Synchronous serial port: enabled 1 ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0. [2:2] read-write true master Mode select: master 0 slave Mode select: slave 1 sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write true drive SSPTXD output disable: SSP can drive the SSPTXD output 0 no_drive SSPTXD output disable: SSP must not drive the SSPTXD output 1 ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 0x10 0x00000000 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write 0 65535 ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xC 0x10 0x00000000 tfe Transmit FIFO empty. [0:0] read-only true not_empty Transmit FIFO is not empty 0 empty Transmit FIFO is empty 1 tnf Transmit FIFO not full. [1:1] read-only true full Transmit FIFO is full 0 not_full Transmit FIFO is not full 1 rne Receive FIFO not empty. [2:2] read-only true empty Receive FIFO is empty 0 not_empty Receive FIFO is not empty 1 rff Receive FIFO full. [3:3] read-only true not_full Receive FIFO is not full 0 full Receive FIFO is full 1 bsy PrimeCell SSP busy flag. [4:4] read-only true idle SSP is idle 0 busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 0x10 0x00000000 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write 2 254 ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 0x10 0x00000000 rorim Receive overrun interrupt mask [0:0] read-write true masked Receive FIFO written to while full condition interrupt is masked 0 not_masked Receive FIFO written to while full condition interrupt is not masked 1 rtim Receive timeout interrupt mask [1:1] read-write true masked Receive FIFO not empty and no read prior to timeout period interrupt is masked 0 not_masked Receive FIFO not empty and no read prior to timeout period interrupt is not masked 1 rxim Receive FIFO interrupt mask [2:2] read-write true masked Receive FIFO half full or less condition interrupt is masked 0 not_masked Receive FIFO half full or less condition interrupt is not masked 1 txim Transmit FIFO interrupt mask [3:3] read-write true masked Transmit FIFO half empty or less condition interrupt is masked 0 not_masked Transmit FIFO half empty or less condition interrupt is not masked 1 ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 0x10 0x00000000 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1C 0x10 0x00000000 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 0x10 0x00000000 roric Clears the SSPRORINTR interrupt [0:0] read-write true nop SSPRORINTR receive interrupt clear: no-op 0 clear SSPRORINTR receive interrupt clear: clear 1 rtic Clears the SSPRTINTR interrupt [1:1] read-write true nop SSPRTINTR transmit interrupt clear: no-op 0 clear SSPRTINTR transmit interrupt clear: clear 1 ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 0x10 0x00000000 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE0 0x10 0x00000000 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE4 0x10 0x00000000 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE8 0x10 0x00000000 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFEC 0x10 0x00000000 configuration These bits read back as 0x80 [7:0] read-only 4 0x4 ssp_pcell_id[%s] The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xFF0 0x10 0x00000000 ssp_pcell_id The bits of the SSPCELLID are read as: [0x0d, 0xf0, 0x05, 0xb1] [7:0] read-only spi2 ARM pl022 SSP SPI: spi2 0x10080000 0x0 0x10000 registers SPI2 40 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 0x10 0x00000000 dss Data Size Select [3:0] read-write true four Data size select: 4-bit 3 five Data size select: 5-bit 4 six Data size select: 6-bit 5 seven Data size select: 7-bit 6 eight Data size select: 8-bit 7 nine Data size select: 9-bit 8 ten Data size select: 10-bit 9 eleven Data size select: 11-bit 10 twelve Data size select: 12-bit 11 thirteen Data size select: 13-bit 12 fourteen Data size select: 14-bit 13 fifteen Data size select: 15-bit 14 sixteen Data size select: 16-bit 15 frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write true spi Frame format: Motorola SPI 0 sync_serial Frame format: TI synchronous serial 1 microwire Frame format: National Microwire 2 spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write true low SSPCLKOUT polarity: steady state low 0 high SSPCLKOUT polarity: steady state high 1 sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [7:7] read-write true first_edge SSPCLKOUT phase: data captured on first clock edge 0 second_edge SSPCLKOUT phase: data captured on second clock edge 1 scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write 0 255 ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 0x10 0x00000000 lbm Loop back mode [0:0] read-write true normal Loop back mode: normal serial port operation 0 shifter Loop back mode: output of transmit serial shifter is connected to input of receive serial shifter internally 1 sse Synchronous serial port enable [1:1] read-write true disabled Synchronous serial port: disabled 0 enabled Synchronous serial port: enabled 1 ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0. [2:2] read-write true master Mode select: master 0 slave Mode select: slave 1 sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write true drive SSPTXD output disable: SSP can drive the SSPTXD output 0 no_drive SSPTXD output disable: SSP must not drive the SSPTXD output 1 ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 0x10 0x00000000 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write 0 65535 ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xC 0x10 0x00000000 tfe Transmit FIFO empty. [0:0] read-only true not_empty Transmit FIFO is not empty 0 empty Transmit FIFO is empty 1 tnf Transmit FIFO not full. [1:1] read-only true full Transmit FIFO is full 0 not_full Transmit FIFO is not full 1 rne Receive FIFO not empty. [2:2] read-only true empty Receive FIFO is empty 0 not_empty Receive FIFO is not empty 1 rff Receive FIFO full. [3:3] read-only true not_full Receive FIFO is not full 0 full Receive FIFO is full 1 bsy PrimeCell SSP busy flag. [4:4] read-only true idle SSP is idle 0 busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 0x10 0x00000000 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write 2 254 ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 0x10 0x00000000 rorim Receive overrun interrupt mask [0:0] read-write true masked Receive FIFO written to while full condition interrupt is masked 0 not_masked Receive FIFO written to while full condition interrupt is not masked 1 rtim Receive timeout interrupt mask [1:1] read-write true masked Receive FIFO not empty and no read prior to timeout period interrupt is masked 0 not_masked Receive FIFO not empty and no read prior to timeout period interrupt is not masked 1 rxim Receive FIFO interrupt mask [2:2] read-write true masked Receive FIFO half full or less condition interrupt is masked 0 not_masked Receive FIFO half full or less condition interrupt is not masked 1 txim Transmit FIFO interrupt mask [3:3] read-write true masked Transmit FIFO half empty or less condition interrupt is masked 0 not_masked Transmit FIFO half empty or less condition interrupt is not masked 1 ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 0x10 0x00000000 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1C 0x10 0x00000000 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 0x10 0x00000000 roric Clears the SSPRORINTR interrupt [0:0] read-write true nop SSPRORINTR receive interrupt clear: no-op 0 clear SSPRORINTR receive interrupt clear: clear 1 rtic Clears the SSPRTINTR interrupt [1:1] read-write true nop SSPRTINTR transmit interrupt clear: no-op 0 clear SSPRTINTR transmit interrupt clear: clear 1 ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 0x10 0x00000000 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE0 0x10 0x00000000 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE4 0x10 0x00000000 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE8 0x10 0x00000000 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFEC 0x10 0x00000000 configuration These bits read back as 0x80 [7:0] read-only 4 0x4 ssp_pcell_id[%s] The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xFF0 0x10 0x00000000 ssp_pcell_id The bits of the SSPCELLID are read as: [0x0d, 0xf0, 0x05, 0xb1] [7:0] read-only tdm StarFive JH7110 TDM: tdm 0x10090000 0x0 0x1000 registers pcmgbcr TDM PCM GB Control Register 0x0 0x20 0x00000000 enable PCM GB enable [0:0] read-write ms PCM GB master-slave mode - 0: master, 1: slave [1:1] read-write true master PCM GB master mode 0 slave PCM GB slave mode 1 syncm PCM GB sync mode - 0: short, 1: long. [2:2] read-write true short PCM GB short sync mode 0 long PCM GB long sync mode 1 elm PCM GB early-late mode - 0: late, 1: early. Only works while syncm is 0. [3:3] read-write true late PCM GB late mode 0 early PCM GB early mode 1 clkpol PCM GB clock polarity - 0: TX rising / RX falling, 1: TX falling / RX rising. [5:5] read-write true tx_rising_rx_falling PCM GB clock polarity: TX rising / RX falling 0 tx_falling_rx_rising PCM GB clock polarity: TX falling / RX rising 1 pcmtxcr TDM PCM TX Control Register 0x4 0x20 0x00000000 tx_en TDM TX enable - 0: disable, 1: enable. [0:0] read-write true disable TDM TX disable 0 enable TDM TX enable 1 lrj TDM left-right justify - 0: right-justify, 1: left-justify. [1:1] read-write true right_justify TDM right-justify 0 left_justify TDM left-justify 1 sl TDM slot length - 0: 8-bit, 1: 16-bit, 2: 32-bit. [3:2] read-write true bit8 TDM slot length 8-bit 0 bit16 TDM slot length 16-bit 1 bit32 TDM slot length 32-bit 2 sscale TDM slot scale. [7:4] read-write 0 15 wl TDM word length - 0: 8-bit, 1: 16-bit, 2: 20-bit, 3: 24-bit, 4: 32-bit. [10:8] read-write true bit8 TDM word length 8-bit 0 bit16 TDM word length 16-bit 1 bit20 TDM word length 20-bit 2 bit24 TDM word length 24-bit 3 bit32 TDM word length 32-bit 4 ifl TDM FIFO Length - 0: half, 1: quarter. [11:11] read-write true half TDM FIFO length half 0 quarter TDM FIFO length quarter 1 pcmrxcr TDM PCM RX Control Register 0x8 0x20 0x00000000 rx_en TDM RX enable - 0: disable, 1: enable. [0:0] read-write true disable TDM RX disable 0 enable TDM RX enable 1 pcmdiv TDM PCM Divisor register 0xC 0x20 0x00000000 pcmdiv TDM PCM divisor. [31:0] read-write 0 4294967295 32 0x4 tdm_fifo[%s] TDM FIFO registers 0x7030000 0x20 0x00000000 fifo TDM FIFO [31:0] read-write 0 4294967295 dmc_ctrl OpenEdges Orbit Memory Controller: dmc_ctrl 0x15700000 0x0 0x10000 registers 1024 0x4 csr[%s] DDR Memory Control CSR register 0x0 0x20 0x00000000 csr [31:0] read-write 0 4294967295 2048 0x4 sec[%s] DDR Memory Control SEC register 0x1000 0x20 0x00000000 sec [31:0] read-write 0 4294967295 dmc_phy OpenEdges Orbit Memory Controller: dmc_phy 0x13000000 0x0 0x10000 registers 2048 0x4 csr[%s] DDR Memory Control PHY CSR register 0x0 0x20 0x00000000 csr [31:0] read-write 0 4294967295 2048 0x4 base[%s] DDR Memory Control PHY Base register 0x2000 0x20 0x00000000 base [31:0] read-write 0 4294967295 2048 0x4 ac_base[%s] DDR Memory Control PHY AC Base register 0x4000 0x20 0x00000000 ac_base [31:0] read-write 0 4294967295 usb0 Cadence USB3: usb0 0x10100000 0x0 0x100000 registers HOST0 100 PERIPHERAL0 108 OTG0 110 otg USB3 OTG registers 0x0 did USB3 OTG VID. 0x0 0x20 0x00000000 did USB3 OTG VID. [31:0] read-write 0 4294967295 rid USB3 OTG RID. 0x4 0x20 0x00000000 rid USB3 OTG RID. [15:0] read-write 0 65535 capabilities USB3 OTG capabilities. 0x8 0x20 0x00000000 capabilitites USB3 OTG capabilitites. [31:0] read-write cmd USB3 OTG command. 0x10 0x20 0x00000000 bus_req OTG bus request. [1:0] read-write true none No request for bus mode. 0 dev Request the bus for Device mode. 1 host Request the bus for Host mode. 2 otg OTG control. [3:2] read-write true none OTG none. 0 en OTG enable. 1 dis OTG disable. 2 a_dev Configure OTG as A-device. [5:4] read-write true none No OTG A-device configuration. 0 en Enable OTG configuration as A-device. 1 dis Disable OTG configuration as A-device. 2 bus_drop OTG drop the bus. [9:8] read-write true none No OTG bus drop. 0 dev Drop the OTG bus for Device mode. 1 host Drop the OTG bus for Host mode. 2 power_off OTG power down. [12:11] read-write true none No power down. 0 dev Power down USBSS-DEV. 1 host Power down CDNSXHCI. 2 sts USB3 OTG status. 0x14 0x20 0x00000000 id_value USB3 OTG current value of the ID pin - only valid when idpullup in OTGCTRL1_TYPE set to `1`. [0:0] read-write vbus_valid USB3 OTG current value of the vbus_valid pin. [1:1] read-write session_valid USB3 OTG current value of the b_sess_vld pin. [2:2] read-write active USB3 OTG active mode. [4:3] read-write true none No OTG mode is active. 0 dev OTG Device mode is active. 1 host OTG Host mode is active. 2 otg_nrdy USB3 OTG Controller (not) readiness status. [11:11] read-write true ready OTG Controller is ready. 0 not_ready OTG Controller is not ready. 1 strap USB3 OTG value of the strap pins. [14:12] read-write true no_default_cfg No default configuration. 0 host_otg Initially configured as Host in OTG mode. 1 host Initially configured as Host. 2 gadget Initially configured as Device. 4 ready USB3 OTG readiness status. [27:26] read-write true none OTG is not ready. 0 xhci OTG Host is ready - Host mode turned on. 1 dev OTG Device is ready - Device mode turned on. 2 state USB3 OTG state. 0x18 0x20 0x00000000 dev_state USB3 OTG Device state. [2:0] read-write true idle Bus is idle. 0 host_state USB3 OTG Device state. [5:3] read-write true idle Bus is idle. 0 vbus_fall VBUS fall. 7 2 0x4 _en,_vect int[%s] USB3 OTG interrupt registers - 0: enable, 1: vector status. Write `1` to interrupt vector fields to clear the status. 0x20 0x20 0x00000000 id_change USB3 OTG ID change interrupt. [0:0] read-write 2 0x1 _rise,_fall vbusvalid[%s] USB3 OTG VBUS valid change detected interrupt - 0: rise, 1: fall. [4:4] read-write refclk USB3 OTG reference clock. 0x28 0x20 0x00000000 refclk USB3 OTG reference clock. [31:0] read-write 0 4294967295 tmr USB3 OTG timer. 0x2C 0x20 0x00000000 tmr USB3 OTG timer. [31:0] read-write 0 4294967295 simulate USB3 OTG simulate. 0x40 0x20 0x00000000 power_lost USB3 OTG simulation - indicates if power was lost before. [0:0] read-write over USB3 OTG override. 0x44 0x20 0x00000000 idpullup USB3 OTG override ID pullup pin. [0:0] read-write session_valid_select USB3 OTG override session valid select. [10:10] read-write true vbus VBUS session valid select 0 ses SES session valid select 1 susp_ctrl USB3 OTG suspend control. 0x48 0x20 0x00000000 susp_ctrl USB3 OTG suspend control. [31:0] read-write phyrst_cfg USB3 OTG PHY reset configuration. 0x4C 0x20 0x00000000 a_enable USB3 OTG PHY A-device enable. [0:0] read-write anasts USB3 OTG ANA status. 0x50 0x20 0x00000000 anasts USB3 OTG ANA status. [31:0] read-write 0 4294967295 adp_ramp_time USB3 OTG ADP ramp time. 0x54 0x20 0x00000000 adp_ramp_time USB3 OTG ADP ramp time. [31:0] read-write 0 4294967295 2 0x4 1-2 ctrl[%s] USB3 OTG control registers. 0x58 0x20 0x00000000 ctrl USB3 OTG control. [31:0] read-write xhci USB3 XHCI registers 0x10000 cap USB3 XHCI Capability registers. 0x0 hc_capbase USB3 XHCI host controller capability base - defines the offset of the `op` register cluster. 0x0 0x20 0x00000000 hc_length USB3 XHCI length of the `hc_capbase` register. [7:0] read-only hc_version USB3 XHCI length of the `hc_capbase` register. [31:8] read-only hcs_params1 USB3 XHCI host controller structural parameters 1. 0x4 0x20 0x00000000 max_intrs USB3 XHCI host controller max interrupts. [18:8] read-only hcs_params2 USB3 XHCI host controller structural parameters 2. 0x8 0x20 0x00000000 hcs_params2 USB3 XHCI host controller structural parameters 2. [31:0] read-only hcs_params3 USB3 XHCI host controller structural parameters 3. 0xC 0x20 0x00000000 hcs_params3 USB3 XHCI host controller structural parameters 3. [31:0] read-only hcc_params USB3 XHCI host controller capability parameters. 0x10 0x20 0x00000000 hcc_params USB3 XHCI host controller capability parameters. [31:0] read-only db_off USB3 XHCI host controller doorbell array offset. 0x14 0x20 0x00000000 db_off USB3 XHCI host controller doorbell array offset. [31:0] read-only run_regs_off USB3 XHCI host controller run register cluster offset - runtime register space offset. 0x18 0x20 0x00000000 run_regs_off USB3 XHCI host controller `run` register cluster offset. [31:0] read-only hcc_params2 USB3 XHCI host controller capabilities parameters - XHCI v1.1. 0x1C 0x20 0x00000000 hcc_params2 USB3 XHCI host controller capability parameters. [31:0] read-only device USB3 device registers 0x20000 usb_conf USB3 Global configuration. 0x0 0x20 0x00000000 cfg Reset/Set USB device configuration. [1:0] read-write true none Do not set USB device configuration. 0 rst Reset USB device configuration. 1 set Set configuration. 2 dis Disconnect USB device. [4:3] read-write true none Do not disconnect USB device. 0 usb3 Disconnect USB3 device in SuperSpeed mode. 1 usb2 Disconnect USB2 device in FS/HS mode. 2 endian Endian access. [6:5] read-write true none No endian access setting 0 little Little endian access - default 1 big Big endian access 2 swrst Device software reset. [7:7] read-write dmaoff DMA clock turn-off. [11:10] read-write true none No DMA clock turn-off setting. 0 en DMA clock turn-off enable. 1 ds DMA clock turn-off disable. 2 force_fs Force Full Speed. [13:12] read-write true none No Force Full Speed setting. 0 clear Clear Force Full Speed. 1 set Set Force Full Speed. 2 dev Device enable/disable. [15:14] read-write true none No Device enable/disable setting. 0 en Device enable. 1 ds Device disable. 2 l1 L1 LPM state entry enable/disable (used in HS/FS mode). [17:16] read-write true none No L1 LPM state entry setting. 0 en L1 LPM state entry enable. 1 ds L1 LPM state entry disable. 2 clk2off USB 2.0 clock gate turn-off enable/disable. [19:18] read-write true none No USB 2.0 clock gate turn-off setting. 0 en USB 2.0 clock gate turn-off enable. 1 ds USB 2.0 clock gate turn-off disable. 2 lgo_l0 L0 LPM state entry request (used in HS/FS mode). [20:20] read-write clk3off USB 3.0 clock gate turn-off enable/disable. [22:21] read-write true none USB 3.0 clock gate turn-off setting. 0 en USB 3.0 clock gate turn-off enable. 1 ds USB 3.0 clock gate turn-off disable. 2 u1 U1 state entry enable/disable (used in SS mode). [25:24] read-write true none No U1 state entry setting. 0 en U1 state entry enable. 1 ds U1 state entry disable. 2 u2 U2 state entry enable/disable (used in SS mode). [27:26] read-write true none No U2 state entry setting. 0 en U2 state entry enable 1 ds U2 state entry disable 2 3 0x1 lgo_u[%s] U0-U2 state entry request - used in SS mode. [28:28] read-write lgo_ssinact SS.Inactive state entry request - used in SS mode. [31:31] read-write usb_sts USB3 Global status. 0x4 0x20 0x00000000 cfgsts Device configuration status. [0:0] read-write true not_cfg Device not configured. 0 cfg Device configured. 1 ov On-chip memory overflow. [1:1] read-write true ok On-chip memory status OK. 0 overflow On-chip memory overflow. 1 usb3cons Superspeed connection status. [2:2] read-write true disconnected SuperSpeed mode disconnected. 0 connected SuperSpeed mode connected. 1 dtrans DMA transfer configuration status. [3:3] read-write true single_request Single DMA request. 0 multiple_trb_chain Multiple TRB chain. 1 usbspeed Device speed. [6:4] read-write true undefined Undefined speed - value after reset. 0 low Low speed. 1 full Full speed. 2 high High speed. 3 super Super speed. 4 endian Endianess for SFR access. [7:7] read-write true little Little Endian order - default after hardware reset 0 big Big Endian order 1 clk2off FS/HS clock turn-off status. [8:8] read-write true always_on FS/HS clock is always on 0 turn_off FS/HS clock turn-off in L2 (FS/HS mode) is enabled - default afteer hardware reset 1 clk3off PCLK clock turn-off status. [9:9] read-write true always_on PCLK clock is always on. 0 turn_off PCLK clock turn-off in U3 (SS mode) is enabled - default afteer hardware reset. 1 in_rst Controller in reset state. [10:10] read-write true active Internal reset is active 0 not_active Internal reset is not active and controller is fully operational. 1 tdl_trb_en Status of the `TDL calculation based on TRB` feature. [11:11] read-write true disabled TDL TRB calculation disabled. 0 enabled TDL TRB calculation enabled. 1 devs Device enable status. [14:14] read-write true disabled USB device is disabled - VBUS disconnected from internal logic. 0 enabled USB device is enabled - VBUS connected to internal logic. 1 addressed Address status. [15:15] read-write true default USB device is in the default state. 0 addressed USB device is at least in address state. 1 l1ens L1 LPM state enable status - used in FS/HS mode. [16:16] read-write true disabled Entering into L1 LPM state disabled. 0 enabled Entering into L1 LPM state enabled. 1 vbuss Internal VBUS connection status - used both in FS/HS and SS mode. [17:17] read-write true not_detected Internal VBUS is not detected. 0 detected Internal VBUS is detected. 1 lpmst FS/HS LPM state - used in FS/HS mode. [19:18] read-write true l0 L0 state. 0 l1 L1 state. 1 l2 L2 state. 2 l3 L3 state. 3 usb2cons Disable HS status - used in FS/HS mode. [20:20] read-write true disconnect The disconnect bit for FS/HS mode is set. 0 connect The disconnect bit for FS/HS mode is not set. 1 disable_hs FS/HS mode connection status - used in FS/HS mode. [21:21] read-write true enabled High Speed operations in USB2.0 mode are not disabled. 0 disabled High Speed operations in USB2.0 mode are disabled. 1 2 0x1 1-2 ens_u[%s] U1/2 state enable status - used in SS mode. [24:24] read-write true disabled Entering to U1/2 state disabled. 0 enabled Entering to U1/2 state enabled. 1 lst SuperSpeed Link LTSSM state. [29:26] read-write true u0 U0 link status. 0 u1 U1 link status. 1 u2 U2 link status. 2 u3 U3 link status. 3 disabled Link disabled. 4 rxdetect Link detected receive. 5 inactive Link inactive. 6 polling Link polling. 7 recovery Link is in recovery. 8 hot_reset Link is hot reset. 9 comp_mode Link is in COMP mode. 10 lb_state Link is in LB state. 11 dmaoff DMA clock turn-off status. [30:30] read-write true always_on DMA clock is always on - default after hardware reset. 0 turn_off DMA clock turn-off in U1, U2, and U3 (SS mode) is enabled. 1 endian2 SFR Endian status. [31:31] read-write true little Little Endian order - default after hardware reset. 0 big Big Endian order. 1 usb_cmd USB3 Global command. 0x8 0x20 0x00000000 set_addr Set function address [0:0] read-write faddr Function address - saves the address to the device only when `set_addr` is set to `1`. [7:1] read-write 0 127 sdnfw Send Function Wake Device Notification TP - used only in SS mode. [8:8] read-write stmode Set Test Mode - used only in FS/HS mode. [9:9] read-write tmode_sel Test Mode Selector - used only in FS/HS mode. [11:10] read-write 0 3 sdnltm Send Latency Tolerance Message Device Notification TP - used only in SS mode. [12:12] read-write spkt Send Custom Transaction Packet - used only in SS mode. [13:13] read-write dnfw_int_dnltm_belt Device Notification `Function Wake` Interface Value / Device Notification `Latency Tolerance Message` BELT Value - used only in SS mode. [23:16] read-write 0 255 usb_itpn ITP (SS) / SOF (FS/HS) number - SS: last ITP number, FS/HS: last SOF number. 0xC 0x20 0x00000000 itpn SS: last ITP number, FS/HS: last SOF number. [13:0] read-write 0 16383 usb_lpm Global LPM. 0x10 0x20 0x00000000 hird Host Initiated Resume Duration. [3:0] read-write 0 15 brw Remote Wakeup Enable - `bRemoteWake`. [4:4] read-write usb_int USB Interrupt registers. 0x14 en Global Interrupt Enable. 0x0 0x20 0x0137003F con SS connection interrupt. [0:0] read-write dis SS disconnection interrupt. [1:1] read-write uwres SS warm reset interrupt. [2:2] read-write uhres SS hot reset interrupt. [3:3] read-write u3ent SS link U3 state enter interrupt - suspend. [4:4] read-write u3ext SS link U3 state exit interrupt - wakeup. [5:5] read-write u2ent SS link U2 state enter interrupt. [6:6] read-write u2ext SS link U2 state exit interrupt. [7:7] read-write u1ent SS link U1 state enter interrupt. [8:8] read-write u1ext SS link U1 state exit interrupt. [9:9] read-write itp ITP/SOF packet detected interrupt. [10:10] read-write wake Wakeup interrupt. [11:11] read-write spkt Send Custom Packet interrupt. [12:12] read-write con2 FS/HS mode connection interrupt. [16:16] read-write dis2 FS/HS mode disconnection interrupt. [17:17] read-write u2res USB reset interrupt - FS/HS mode. [18:18] read-write l2ent LPM L2 state enter interrupt. [20:20] read-write l2ext LPM L2 state exit interrupt. [21:21] read-write l1ent LPM L1 state enter interrupt. [24:24] read-write l1ext LPM L1 state exit interrupt. [25:25] read-write cfgres Configuration reset interrupt. [26:26] read-write uwress Start of the USB SS warm reset interrupt. [28:28] read-write uwrese End of the USB SS warm reset interrupt. [29:29] read-write sts Global Interrupt Status. 0x4 0x20 0x00000000 con SS connection interrupt. [0:0] read-write dis SS disconnection interrupt. [1:1] read-write uwres SS warm reset interrupt. [2:2] read-write uhres SS hot reset interrupt. [3:3] read-write u3ent SS link U3 state enter interrupt - suspend. [4:4] read-write u3ext SS link U3 state exit interrupt - wakeup. [5:5] read-write u2ent SS link U2 state enter interrupt. [6:6] read-write u2ext SS link U2 state exit interrupt. [7:7] read-write u1ent SS link U1 state enter interrupt. [8:8] read-write u1ext SS link U1 state exit interrupt. [9:9] read-write itp ITP/SOF packet detected interrupt. [10:10] read-write wake Wakeup interrupt. [11:11] read-write spkt Send Custom Packet interrupt. [12:12] read-write con2 FS/HS mode connection interrupt. [16:16] read-write dis2 FS/HS mode disconnection interrupt. [17:17] read-write u2res USB reset interrupt - FS/HS mode. [18:18] read-write l2ent LPM L2 state enter interrupt. [20:20] read-write l2ext LPM L2 state exit interrupt. [21:21] read-write l1ent LPM L1 state enter interrupt. [24:24] read-write l1ext LPM L1 state exit interrupt. [25:25] read-write cfgres Configuration reset interrupt. [26:26] read-write uwress Start of the USB SS warm reset interrupt. [28:28] read-write uwrese End of the USB SS warm reset interrupt. [29:29] read-write ep_sel USB3 Endpoint select. 0x1C 0x20 0x00000000 epno Endpoint number. [3:0] read-write 0 15 dir Endpoint direction. [7:7] read-write true out OUT direction 0 in IN direction 1 ep_traddr USB3 Endpoint transfer address. 0x20 0x20 0x00000000 ep_traddr Endpoint transfer address [31:0] read-write 0 4294967295 ep_cfg USB3 Endpoint configuration. 0x24 0x20 0x00000000 enable Endpoint enable. [0:0] read-write eptype Endpoint type. [2:1] read-write true isochronous Isochronous endpoint 1 bulk Bulk endpoint 2 interrupt Interrupt endpoint 3 stream_en Stream support enable - only in SS mode. [3:3] read-write tdl_chk TDL check - only in SS mode for BULK EP. [4:4] read-write sid_chk SID check - only in SS mode for BULK OUT EP. [5:5] read-write ependian DMA transfer endianness. [7:7] read-write maxburst Max burst size - used only in SS mode. [11:8] read-write 0 15 mult ISO max burst size. [15:14] read-write true mult0 ISO burst: 0 0 mult1 ISO burst: 1 1 mult2 ISO burst: 2 2 maxpktsize ISO max packet size. [26:16] read-write 0 2047 buffering Max number of buffered packets. [31:27] read-write 0 15 ep_cmd USB3 Endpoint command. 0x28 0x20 0x00000000 eprst Endpoint reset. [0:0] read-write 2 0x1 _set,_clear stall[%s] Endpoint STALL set/clear. [1:1] read-write erdy Send ERDY TP. [3:3] read-write req_cmpl Request complete. [5:5] read-write drdy Transfer descriptor ready. [6:6] read-write dflush Data flush. [7:7] read-write stdl Transfer Descriptor Length write - only for SS mode BULK mode endpoints, removed in `DEV_VER_V3`. [8:8] read-write tdl Transfer Descriptor Length - only for SS mode BULK mode endpoints, removed in `DEV_VER_V3`. [15:9] read-write 0 127 erdy_sid ERDY Stream ID value - used in SS mode. [31:16] read-write 0 65535 ep_sts USB3 Endpoint status registers. 0x2C status USB3 Endpoint status. 0x0 0x20 0x00000000 setup Setup transfer complete. [0:0] read-write stall Endpoint STALL status. [1:1] read-write ioc Interrupt On Complete. [2:2] read-write isp Interrupt on Short Packet. [3:3] read-write descmis Transfer desccriptor missing. [4:4] read-write streamr Stream Rejected - used only in SS mode. [5:5] read-write md_exit EXIT from MOVE DATA State - used only for stream transfers in SS mode. [6:6] read-write trberr TRB error. [7:7] read-write nrdy Not Ready - used only in SS mode. [8:8] read-write dbusy DMA busy. [9:9] read-write buffempty Endpoint Buffer Empty. [10:10] read-write ccs Current Cycle Status. [11:11] read-write prime Prime - used only in SS mode. [12:12] read-write siderr Stream Error - used only in SS mode. [13:13] read-write outsmm OUT size mismatch. [14:14] read-write isoerr ISO transmission error. [15:15] read-write hostpp Host Packet Pending - used only in SS mode. [16:16] read-write spsmst Stream Protocol State Machine State - used only for BULK stream endpoints. [18:17] read-write true disabled Stream State Machine: DISABLED. 0 idle Stream State Machine: IDLE. 1 start_stream Stream State Machine: START STREAM. 2 move_data Stream State Machine: MOVE DATA. 3 iot Interrupt On Transfer complete. [19:19] read-write outq_no OUT queue endpoint number. [27:24] read-write 0 15 outq_val OUT queue valid flag. [28:28] read-write true invalid OUT queue invalid. 0 valid OUT queue valid. 1 stpwait SETUP WAIT. [31:31] read-write sid Endpoint status stream ID - used only in SS mode. 0x4 0x20 0x00000000 sid Stream ID - used only in SS mode. [15:0] read-write 0 65535 en Endpoint status enable. 0x8 0x20 0x00000000 setup Stream SETUP interrupt enable. [0:0] read-write descmis OUT transfer descriptor missing enable. [4:4] read-write streamr Stream Rejected enable. [5:5] read-write md_exit Move Data Exit enable. [6:6] read-write trberr TRB Error enable. [7:7] read-write nrdy Not Ready enable. [8:8] read-write prime Prime enable. [12:12] read-write siderr Stream error enable. [13:13] read-write outsmm OUT size mismatch enable. [14:14] read-write isoerr ISO transmission error enable. [15:15] read-write iot Interrtup On Transmission enable. [19:19] read-write stpwait Setup Wait interrupt enable. [31:31] read-write drbl USB3 doorbell. 0x38 0x20 0x00000000 16 0x1 out_ep[%s] Doorbell OUT. [0:0] read-write 16 0x1 in_ep[%s] Doorbell IN. [16:16] read-write 2 0x4 _en,_sts ep_int[%s] USB3 Endpoint interrupt registers - ep_int0: enable, ep_int1: status. 0x3C 0x20 0x00000000 16 0x1 ep_out[%s] OUT endpoint. [0:0] read-write 16 0x1 ep_in[%s] IN endpoint. [16:16] read-write usb_pwr USB3 Global power. 0x44 0x20 0x00000000 2 0x1 _en,_ds pso[%s] Power Shutoff capability enable/disable - pso0: enable, pso1: disable [0:0] read-write 2 0x1 _en,_done stb_clk_switch[%s] Reference clock switch, only enabled if OTG_READY set to `1` - stb_clk_switch0: enable, stb_clk_switch1: done [8:8] read-write 2 0x1 _stat,_en fast_reg_access[%s] Fast Register Access - fast_reg_access0: status, fast_reg_access1: enable [30:30] read-write usb_conf2 USB3 Global configurartion 2. 0x48 0x20 0x00000000 2 0x1 _dis,_en tdl_trb[%s] TDL calculation based on TRB feature in controller for DMULT mode, only supported in DEV_VER_V2 version - tdl_trb0: disable, tdl_trb1: enable. [1:1] read-write usb_cap USB3 Global Capability registers. 0x4C cap1 USB3 Global capability 1. 0x0 0x20 0x00000000 sfr_type SFR interface type. [3:0] read-write true ocp SFR OCP interface. 0 ahb SFR AHB interface. 1 plb SFR PLB interface. 2 axi SFR AXI interface. 3 sfr_width SFR interface width. [7:4] read-write true bit8 SFR 8-bit interface. 0 bit16 SFR 16-bit interface. 1 bit32 SFR 32-bit interface. 2 bit64 SFR 64-bit interface. 3 dma_type DMA interface type. [11:8] read-write true ocp DMA OCP interface. 0 ahb DMA AHB interface. 1 plb DMA PLB interface. 2 axi DMA AXI interface. 3 dma_width DMA interface width. [15:12] read-write true bit32 DMA 32-bit interface. 2 bit64 DMA 64-bit interface. 3 u3phy_type USB3 PHY interface type. [19:16] read-write true usb_pipe USB PIPE interface. 0 rmmi RMMI interface. 1 u3phy_width USB3 PHY interface width. [23:20] read-write true bit8 USB3 PHY 8-bit interface. 0 bit16 USB3 PHY 16-bit interface. 1 bit32 USB3 PHY 32-bit interface. 2 bit64 USB3 PHY 64-bit interface. 3 u2phy_en USB2 PHY interface enable. [24:24] read-write u2phy_type USB2 PHY interface type. [25:25] read-write true utmi USB2 PHY UTMI interface. 0 ulpi USB2 PHY ULPI interface. 1 u2phy_width USB2 PHY interface width - **NOTE**: The ULPI interface is always 8-bit wide. [26:26] read-write true bit8 USB2 PHY 8-bit interface width. 0 bit16 USB2 PHY 16-bit interface width. 1 otg_ready OTG mode ready. [27:27] read-write true dev_only Pure device mode. 0 otg Some features and ports for CDNS USB OTG controller are implemented. 1 tdl_from_trb Indicates the capability to automatically calculate internal TDL from TRB value for DMULT mode. [28:28] read-write cap2 USB3 Global capability 2. 0x4 0x20 0x00000000 actual_mem_size The actual size of the connnected on-chip RAM memory in kB - 0: 256kB, 1-255: 1-255kB. [7:0] read-write true mem256kb Actual supported memory size: 256kB 0 mem1kb Actual supported memory size: 1kB 1 mem2kb Actual supported memory size: 2kB 2 mem3kb Actual supported memory size: 3kB 3 mem4kb Actual supported memory size: 4kB 4 mem5kb Actual supported memory size: 5kB 5 mem6kb Actual supported memory size: 6kB 6 mem7kb Actual supported memory size: 7kB 7 mem8kb Actual supported memory size: 8kB 8 mem9kb Actual supported memory size: 9kB 9 mem10kb Actual supported memory size: 10kB 10 mem11kb Actual supported memory size: 11kB 11 mem12kb Actual supported memory size: 12kB 12 mem13kb Actual supported memory size: 13kB 13 mem14kb Actual supported memory size: 14kB 14 mem15kb Actual supported memory size: 15kB 15 mem16kb Actual supported memory size: 16kB 16 mem17kb Actual supported memory size: 17kB 17 mem18kb Actual supported memory size: 18kB 18 mem19kb Actual supported memory size: 19kB 19 mem20kb Actual supported memory size: 20kB 20 mem21kb Actual supported memory size: 21kB 21 mem22kb Actual supported memory size: 22kB 22 mem23kb Actual supported memory size: 23kB 23 mem24kb Actual supported memory size: 24kB 24 mem25kb Actual supported memory size: 25kB 25 mem26kb Actual supported memory size: 26kB 26 mem27kb Actual supported memory size: 27kB 27 mem28kb Actual supported memory size: 28kB 28 mem29kb Actual supported memory size: 29kB 29 mem30kb Actual supported memory size: 30kB 30 mem31kb Actual supported memory size: 31kB 31 mem32kb Actual supported memory size: 32kB 32 mem33kb Actual supported memory size: 33kB 33 mem34kb Actual supported memory size: 34kB 34 mem35kb Actual supported memory size: 35kB 35 mem36kb Actual supported memory size: 36kB 36 mem37kb Actual supported memory size: 37kB 37 mem38kb Actual supported memory size: 38kB 38 mem39kb Actual supported memory size: 39kB 39 mem40kb Actual supported memory size: 40kB 40 mem41kb Actual supported memory size: 41kB 41 mem42kb Actual supported memory size: 42kB 42 mem43kb Actual supported memory size: 43kB 43 mem44kb Actual supported memory size: 44kB 44 mem45kb Actual supported memory size: 45kB 45 mem46kb Actual supported memory size: 46kB 46 mem47kb Actual supported memory size: 47kB 47 mem48kb Actual supported memory size: 48kB 48 mem49kb Actual supported memory size: 49kB 49 mem50kb Actual supported memory size: 50kB 50 mem51kb Actual supported memory size: 51kB 51 mem52kb Actual supported memory size: 52kB 52 mem53kb Actual supported memory size: 53kB 53 mem54kb Actual supported memory size: 54kB 54 mem55kb Actual supported memory size: 55kB 55 mem56kb Actual supported memory size: 56kB 56 mem57kb Actual supported memory size: 57kB 57 mem58kb Actual supported memory size: 58kB 58 mem59kb Actual supported memory size: 59kB 59 mem60kb Actual supported memory size: 60kB 60 mem61kb Actual supported memory size: 61kB 61 mem62kb Actual supported memory size: 62kB 62 mem63kb Actual supported memory size: 63kB 63 mem64kb Actual supported memory size: 64kB 64 mem65kb Actual supported memory size: 65kB 65 mem66kb Actual supported memory size: 66kB 66 mem67kb Actual supported memory size: 67kB 67 mem68kb Actual supported memory size: 68kB 68 mem69kb Actual supported memory size: 69kB 69 mem70kb Actual supported memory size: 70kB 70 mem71kb Actual supported memory size: 71kB 71 mem72kb Actual supported memory size: 72kB 72 mem73kb Actual supported memory size: 73kB 73 mem74kb Actual supported memory size: 74kB 74 mem75kb Actual supported memory size: 75kB 75 mem76kb Actual supported memory size: 76kB 76 mem77kb Actual supported memory size: 77kB 77 mem78kb Actual supported memory size: 78kB 78 mem79kb Actual supported memory size: 79kB 79 mem80kb Actual supported memory size: 80kB 80 mem81kb Actual supported memory size: 81kB 81 mem82kb Actual supported memory size: 82kB 82 mem83kb Actual supported memory size: 83kB 83 mem84kb Actual supported memory size: 84kB 84 mem85kb Actual supported memory size: 85kB 85 mem86kb Actual supported memory size: 86kB 86 mem87kb Actual supported memory size: 87kB 87 mem88kb Actual supported memory size: 88kB 88 mem89kb Actual supported memory size: 89kB 89 mem90kb Actual supported memory size: 90kB 90 mem91kb Actual supported memory size: 91kB 91 mem92kb Actual supported memory size: 92kB 92 mem93kb Actual supported memory size: 93kB 93 mem94kb Actual supported memory size: 94kB 94 mem95kb Actual supported memory size: 95kB 95 mem96kb Actual supported memory size: 96kB 96 mem97kb Actual supported memory size: 97kB 97 mem98kb Actual supported memory size: 98kB 98 mem99kb Actual supported memory size: 99kB 99 mem100kb Actual supported memory size: 100kB 100 mem101kb Actual supported memory size: 101kB 101 mem102kb Actual supported memory size: 102kB 102 mem103kb Actual supported memory size: 103kB 103 mem104kb Actual supported memory size: 104kB 104 mem105kb Actual supported memory size: 105kB 105 mem106kb Actual supported memory size: 106kB 106 mem107kb Actual supported memory size: 107kB 107 mem108kb Actual supported memory size: 108kB 108 mem109kb Actual supported memory size: 109kB 109 mem110kb Actual supported memory size: 110kB 110 mem111kb Actual supported memory size: 111kB 111 mem112kb Actual supported memory size: 112kB 112 mem113kb Actual supported memory size: 113kB 113 mem114kb Actual supported memory size: 114kB 114 mem115kb Actual supported memory size: 115kB 115 mem116kb Actual supported memory size: 116kB 116 mem117kb Actual supported memory size: 117kB 117 mem118kb Actual supported memory size: 118kB 118 mem119kb Actual supported memory size: 119kB 119 mem120kb Actual supported memory size: 120kB 120 mem121kb Actual supported memory size: 121kB 121 mem122kb Actual supported memory size: 122kB 122 mem123kb Actual supported memory size: 123kB 123 mem124kb Actual supported memory size: 124kB 124 mem125kb Actual supported memory size: 125kB 125 mem126kb Actual supported memory size: 126kB 126 mem127kb Actual supported memory size: 127kB 127 mem128kb Actual supported memory size: 128kB 128 mem129kb Actual supported memory size: 129kB 129 mem130kb Actual supported memory size: 130kB 130 mem131kb Actual supported memory size: 131kB 131 mem132kb Actual supported memory size: 132kB 132 mem133kb Actual supported memory size: 133kB 133 mem134kb Actual supported memory size: 134kB 134 mem135kb Actual supported memory size: 135kB 135 mem136kb Actual supported memory size: 136kB 136 mem137kb Actual supported memory size: 137kB 137 mem138kb Actual supported memory size: 138kB 138 mem139kb Actual supported memory size: 139kB 139 mem140kb Actual supported memory size: 140kB 140 mem141kb Actual supported memory size: 141kB 141 mem142kb Actual supported memory size: 142kB 142 mem143kb Actual supported memory size: 143kB 143 mem144kb Actual supported memory size: 144kB 144 mem145kb Actual supported memory size: 145kB 145 mem146kb Actual supported memory size: 146kB 146 mem147kb Actual supported memory size: 147kB 147 mem148kb Actual supported memory size: 148kB 148 mem149kb Actual supported memory size: 149kB 149 mem150kb Actual supported memory size: 150kB 150 mem151kb Actual supported memory size: 151kB 151 mem152kb Actual supported memory size: 152kB 152 mem153kb Actual supported memory size: 153kB 153 mem154kb Actual supported memory size: 154kB 154 mem155kb Actual supported memory size: 155kB 155 mem156kb Actual supported memory size: 156kB 156 mem157kb Actual supported memory size: 157kB 157 mem158kb Actual supported memory size: 158kB 158 mem159kb Actual supported memory size: 159kB 159 mem160kb Actual supported memory size: 160kB 160 mem161kb Actual supported memory size: 161kB 161 mem162kb Actual supported memory size: 162kB 162 mem163kb Actual supported memory size: 163kB 163 mem164kb Actual supported memory size: 164kB 164 mem165kb Actual supported memory size: 165kB 165 mem166kb Actual supported memory size: 166kB 166 mem167kb Actual supported memory size: 167kB 167 mem168kb Actual supported memory size: 168kB 168 mem169kb Actual supported memory size: 169kB 169 mem170kb Actual supported memory size: 170kB 170 mem171kb Actual supported memory size: 171kB 171 mem172kb Actual supported memory size: 172kB 172 mem173kb Actual supported memory size: 173kB 173 mem174kb Actual supported memory size: 174kB 174 mem175kb Actual supported memory size: 175kB 175 mem176kb Actual supported memory size: 176kB 176 mem177kb Actual supported memory size: 177kB 177 mem178kb Actual supported memory size: 178kB 178 mem179kb Actual supported memory size: 179kB 179 mem180kb Actual supported memory size: 180kB 180 mem181kb Actual supported memory size: 181kB 181 mem182kb Actual supported memory size: 182kB 182 mem183kb Actual supported memory size: 183kB 183 mem184kb Actual supported memory size: 184kB 184 mem185kb Actual supported memory size: 185kB 185 mem186kb Actual supported memory size: 186kB 186 mem187kb Actual supported memory size: 187kB 187 mem188kb Actual supported memory size: 188kB 188 mem189kb Actual supported memory size: 189kB 189 mem190kb Actual supported memory size: 190kB 190 mem191kb Actual supported memory size: 191kB 191 mem192kb Actual supported memory size: 192kB 192 mem193kb Actual supported memory size: 193kB 193 mem194kb Actual supported memory size: 194kB 194 mem195kb Actual supported memory size: 195kB 195 mem196kb Actual supported memory size: 196kB 196 mem197kb Actual supported memory size: 197kB 197 mem198kb Actual supported memory size: 198kB 198 mem199kb Actual supported memory size: 199kB 199 mem200kb Actual supported memory size: 200kB 200 mem201kb Actual supported memory size: 201kB 201 mem202kb Actual supported memory size: 202kB 202 mem203kb Actual supported memory size: 203kB 203 mem204kb Actual supported memory size: 204kB 204 mem205kb Actual supported memory size: 205kB 205 mem206kb Actual supported memory size: 206kB 206 mem207kb Actual supported memory size: 207kB 207 mem208kb Actual supported memory size: 208kB 208 mem209kb Actual supported memory size: 209kB 209 mem210kb Actual supported memory size: 210kB 210 mem211kb Actual supported memory size: 211kB 211 mem212kb Actual supported memory size: 212kB 212 mem213kb Actual supported memory size: 213kB 213 mem214kb Actual supported memory size: 214kB 214 mem215kb Actual supported memory size: 215kB 215 mem216kb Actual supported memory size: 216kB 216 mem217kb Actual supported memory size: 217kB 217 mem218kb Actual supported memory size: 218kB 218 mem219kb Actual supported memory size: 219kB 219 mem220kb Actual supported memory size: 220kB 220 mem221kb Actual supported memory size: 221kB 221 mem222kb Actual supported memory size: 222kB 222 mem223kb Actual supported memory size: 223kB 223 mem224kb Actual supported memory size: 224kB 224 mem225kb Actual supported memory size: 225kB 225 mem226kb Actual supported memory size: 226kB 226 mem227kb Actual supported memory size: 227kB 227 mem228kb Actual supported memory size: 228kB 228 mem229kb Actual supported memory size: 229kB 229 mem230kb Actual supported memory size: 230kB 230 mem231kb Actual supported memory size: 231kB 231 mem232kb Actual supported memory size: 232kB 232 mem233kb Actual supported memory size: 233kB 233 mem234kb Actual supported memory size: 234kB 234 mem235kb Actual supported memory size: 235kB 235 mem236kb Actual supported memory size: 236kB 236 mem237kb Actual supported memory size: 237kB 237 mem238kb Actual supported memory size: 238kB 238 mem239kb Actual supported memory size: 239kB 239 mem240kb Actual supported memory size: 240kB 240 mem241kb Actual supported memory size: 241kB 241 mem242kb Actual supported memory size: 242kB 242 mem243kb Actual supported memory size: 243kB 243 mem244kb Actual supported memory size: 244kB 244 mem245kb Actual supported memory size: 245kB 245 mem246kb Actual supported memory size: 246kB 246 mem247kb Actual supported memory size: 247kB 247 mem248kb Actual supported memory size: 248kB 248 mem249kb Actual supported memory size: 249kB 249 mem250kb Actual supported memory size: 250kB 250 mem251kb Actual supported memory size: 251kB 251 mem252kb Actual supported memory size: 252kB 252 mem253kb Actual supported memory size: 253kB 253 mem254kb Actual supported memory size: 254kB 254 mem255kb Actual supported memory size: 255kB 255 max_mem_size Max supported memory size. [11:8] read-write true mem4kb Support for 4kB memory. 8 mem8kb Support for 8kB memory. 9 mem16kb Support for 16kB memory. 10 mem32kb Support for 32kB memory. 11 mem64kb Support for 64kB memory. 12 mem128kb Support for 128kB memory. 13 mem256kb Support for 256kB memory. 14 cap3 USB3 Global capability 3. 0x8 0x20 0x00000000 32 0x1 ep_is_implemented[%s] Endpoint is implemented. [0:0] read-write cap4 USB3 Global capability 4. 0xC 0x20 0x00000000 32 0x1 ep_support_iso[%s] Endpoint supports ISO mode. [0:0] read-write cap5 USB3 Global capability 5. 0x10 0x20 0x00000000 32 0x1 ep_support_stream[%s] Endpoint supports streaming mode. [0:0] read-write cap6 USB3 Global capability 6. 0x14 0x20 0x00000000 dev_base_version USBSS-DEV Controller Internal build number. [23:0] read-only true nxp_v1 NXP version 1 148738 ti_v1 TI version 1 148745 v2 Version 2 148748 v3 Version 3 148749 dev_custom_version USBSS-DEV Controller version number. [31:24] read-only 3 0x4 1-3 usb_cpkt[%s] USB3 Global custom packet. 0x64 0x20 0x00000000 cpkt Custom packet. [31:0] read-write 0 4294967295 ep_dma_ext_addr USB3 Endpoint upper address for DMA operations. 0x70 0x20 0x00000000 ep_dma_ext_addr Custom packet. [31:0] read-write 0 4294967295 buf USB3 On-chip buffer registers. 0x74 addr USB3 On-chip buffer address. 0x0 0x20 0x00000000 addr On-chip buffer address. [31:0] read-write 0 4294967295 data USB3 On-chip buffer data. 0x4 0x20 0x00000000 data On-chip buffer data. [31:0] read-write 0 4294967295 ctrl USB3 On-chip buffer control. 0x8 0x20 0x00000000 ctrl On-chip buffer control. [31:0] read-write dtrans USB3 DMA transfer mode. 0x80 0x20 0x00000000 16 0x1 dtrans_out[%s] DMA transfer mode - OUT endpoint. [0:0] read-write 16 0x1 dtrans_in[%s] DMA transfer mode - IN endpoint. [16:16] read-write tdl USB3 Device TDL registers. 0x84 cfg_from_trb TDL configuration source. 0x0 0x20 0x00000000 cfg_from_trb TDL configuration source. [3:0] read-write 0 15 ep_dir TDL configuration source endpoint direction. [4:4] read-write true out Outbound endpoint 0 in Inbound endpoint 1 beh TDL behavior configuration. 0x4 0x20 0x00000000 ep_num TDL behavior configuration endpoint number. [3:0] read-write 0 15 ep_dir TDL behavior configuration endpoint direction. [4:4] read-write true out Outbound endpoint 0 in Inbound endpoint 1 ep TDL endpoint configuration. 0x8 0x20 0x00000000 16 0x1 ep_out[%s] Endpoint TDL - OUT. [0:0] read-write 16 0x1 ep_in[%s] Endpoint TDL - IN. [16:16] read-write beh2 TDL behavior 2 configuration. 0xC 0x20 0x00000000 beh2 TDL behavior 2 configuration endpoint number. [3:0] read-write 0 15 ep_dir TDL behavior 2 configuration endpoint direction. [4:4] read-write true out Outbound endpoint 0 in Inbound endpoint 1 dma_adv TDL DMA Advance configuration. 0x10 0x20 0x00000000 dma_adv TDL DMA advance configuration endpoint number. [3:0] read-write 0 15 ep_dir TDL behavior configuration endpoint direction. [4:4] read-write true out Outbound endpoint 0 in Inbound endpoint 1 cfg1 Device configuration 1. 0x100 0x20 0x00000000 cfg1 Device configuration 1. [31:0] read-write dbg_link1 Device debug link 1. 0x104 0x20 0x00000000 lfps_min_det_u1_exit LFPS_MIN_DET_U1_EXIT value - configures the minimum time required for decoding the received LFPS as an LFPS.U1_Exit. [7:0] read-write 0 255 lfps_gen_u1_exit LFPS_MIN_GEN_U1_EXIT value - configures the minimum time for phytxelecidle deassertion when LFPS.U1_Exit. [15:8] read-write 0 255 rxdet_break_dis RXDET_BREAK_DIS value configures terminating the Far-end Receiver termination detection sequence. [16:16] read-write true possible It is possible that USBSS_DEV will terminate far-end receiver termination detection sequence. 0 not_possible USBSS_DEV will not terminate far-end receiver termination detection sequence. 1 lfps_gen_ping LFPS_GEN_PING value - configures the LFPS.Ping generation. [21:17] read-write 0 31 lfps_min_det_u1_exit_set Set the LFPS_MIN_DET_U1_EXIT value - This bit is automatically cleared, writing `0` has no effect. [24:24] read-write true set Writes the LPFS_MIN_DET_U1_EXIT field value to the device. 1 lfps_min_gen_u1_exit_set Set the LFPS_MIN_GEN_U1_EXIT value - This bit is automatically cleared, writing `0` has no effect. [25:25] write-only true set Writes the LPFS_MIN_GEN_U1_EXIT field value to the device. 1 rxdet_break_dis_set Set the RXDET_BREAK_DIS value - This bit is automatically cleared, writing `0` has no effect. [26:26] write-only true set Writes the RXDET_BREAK_DIS field value to the device. 1 lfps_gen_ping_set Set the LFPS_GEN_PING value - This bit is automatically cleared, writing `0` has no effect. [27:27] write-only true set Writes the LPFS_GEN_PING field value to the device. 1 dbg_link2 Device debug link 2. 0x108 0x20 0x00000000 dbg_link2 Device debug link 2. [31:0] read-write 74 0x4 cfg[%s] Device configuration. 0x10C 0x20 0x00000000 cfg Device configuration. [31:0] read-write dma_axi Device DMA registers. 0x300 ctrl Device DMA AXI control. 0x0 0x20 0x00000000 marprot DMA memory-access read protection. [2:0] read-write true secure Protected access to memory - can cause problem with cache 0 non_secure Unprotected access to memory 2 mawprot DMA memory-access write protection. [18:16] read-write true secure Protected access to memory - can cause problem with cache 0 non_secure Unprotected access to memory 2 id Device DMA AXI ID. 0x4 0x20 0x00000000 id DMA AXI ID. [31:0] read-write 0 4294967295 cap Device DMA AXI capability. 0x8 0x20 0x00000000 cap DMA AXI capability. [31:0] read-write ctrl0 Device DMA AXI control 0: **WARNING** DMA AXI max burst length - In versions preceding DEV_VER_V2, for example, iMX8QM, there exist the bugs in the DMA. These bugs occur when the trb_burst_size exceeds 16 and the address is not aligned to 128 Bytes (which is a product of the 64-bit AXI and AXI maximum burst length of 16 or 0xF+1, dma_axi_ctrl0[3:0]). This results in data corruption when it crosses the 4K border. The corruption specifically occurs from the position (4K - (address & 0x7F)) to 4K. So force trb_burst_size to 16 at such platform. 0xC 0x20 0x00000000 max_burst Device DMA AXI max burst length - length = value + 1? [3:0] read-write 0 15 ctrl1 Device DMA AXI control 1. 0x10 0x20 0x00000000 ctrl1 DMA AXI control 1. [31:0] read-write stgcrg StarFive JH7110 STG CRG: stgcrg 0x10230000 0x0 0x10000 registers clk_hifi4_core Clock HIFI4 Core 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_usb_apb Clock USB APB 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_usb_utmi_apb Clock USB UTMI APB 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_usb_axi Clock USB AXI 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_usb_ipm Clock USB IPM 0x10 0x20 0x00000002 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_usb_stb Clock USB STB 0x14 0x20 0x00000004 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 [23:0] read-write 4 4 clk_usb_app125 Clock USB APP 125 0x18 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_usb_refclk Clock USB REFCLK 0x1C 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 2 0xC _u0,_u1 clk_pcie[%s] Clock PCIe configuration 0x20 axi_mst0 Clock PCIe AXI MST0 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 apb Clock PCIe APB 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 tl Clock PCIe TL 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_pcie_u1_slv_dec_main Clock PCIe01 SLV DEC Main 0x38 0x20 0x00000001 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_sec_hclk Clock SEC HCLK 0x3C 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_sec_ahb Clock SEC AHB 0x40 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0xC _group0,_group1 clk_stg_mtrx[%s] Clock STG Matrix Group configuration 0x44 main Clock STG Matrix Group Main 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 bus Clock STG Matrix Group Bus 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 stg Clock STG Matrix Group STG 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_stg_mtrx_group1_hifi Clock STG Matrix Group 1 HIFI 0x5C 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_e2_rtc Clock E2 RTC 0x60 0x20 0x00000018 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 [23:0] read-write 24 24 clk_e2_core Clock E2 Core 0x64 0x20 0x00000001 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_e2_dbg Clock E2 Debug 0x68 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_dma_axi Clock DMA AXI 0x6C 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_dma_ahb Clock DMA AHB 0x70 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0x4 _soft_addr_sel,_stgcrg_stat rst[%s] STGCRG RESET 0x74 0x20 0x007FFFFE u0_stg_syscon_presetn U0 STG SYSCON Presetn reset. [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_hifi4_core U0 HIFI4 Core reset. [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_hifi4_axi U0 HIFI4 AXI reset. [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_sec_top_hresetn U0 SEC Top HResetn reset. [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_e2_core U0 E2 Core reset. [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_dma_axi U0 DMA AXI reset. [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_dma_ahb U0 DMA AHB reset. [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_usb_axi U0 USB AXI reset. [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_usb_apb U0 USB APB reset. [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_usb_utmi_apb U0 USB UTMI APB reset. [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_usb_pwrup U0 USB Power-up reset. [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pcie_axi_mst0 U0 PCIE AXI MST0 reset. [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pcie_axi_slv0 U0 PCIE AXI SLV0 reset. [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pcie_axi_slv U0 PCIE AXI SLV reset. [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pci_brg U0 PCI BRG reset. [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pcie_pcie U0 PCIE main reset. [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pcie_apb U0 PCIE APB reset. [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_pcie_axi_mst0 U1 PCIE AXI MST0 reset. [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_pcie_axi_slv0 U1 PCIE AXI SLV0 reset. [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_pcie_axi_slv U1 PCIE AXI SLV reset. [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_pcie_brg U1 PCIE BRG reset. [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_pcie_pcie U1 PCIE main reset. [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_pcie_apb U1 PCIE APB reset. [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 stg_syscon StarFive JH7110 STG Syscon: stg_syscon 0x10240000 0x0 0x1000 registers stg_syscfg_0 STG SYSCONSAIF SYSCFG 0 0x0 0x20 0x00000000 scfg_hprot_sd0 [3:0] read-write 0 15 scfg_hprot_sd1 [7:4] read-write 0 15 u0_usb_adp_en [8:8] read-only u0_usb_adp_probe_ana [9:9] read-write u0_usb_adp_probe_en [10:10] read-only u0_usb_adp_sense_ana [11:11] read-write u0_usb_adp_sense_en [12:12] read-only u0_usb_adp_sink_current_en [13:13] read-only u0_usb_adp_source_current_en [14:14] read-only u0_usb_bc_en [15:15] read-only u0_usb_chrg_vbus [16:16] read-write u0_usb_dcd_comp_sts [17:17] read-write u0_usb_dischrg_vbus [18:18] read-write u0_usb_dm_vdat_ref_comp_en [19:19] read-only u0_usb_dm_vdat_ref_comp_sts [20:20] read-write u0_usb_dm_vlgc_comp_en [21:21] read-only u0_usb_dm_vlgc_comp_sts [22:22] read-write u0_usb_dp_vdat_ref_comp_en [23:23] read-only u0_usb_dp_vdat_ref_comp_sts [24:24] read-write u0_usb_host_system_err [25:25] read-write u0_usb_hsystem_err_ext [26:26] read-only u0_usb_idm_sink_en [27:27] read-only u0_usb_idp_sink_en [28:28] read-only u0_usb_idp_src_en [29:29] read-only stg_syscfg_1 STG SYSCONSAIF SYSCFG 4 0x4 0x20 0x00002000 u0_usb_lowest_belt LTM interface to software [11:0] read-only u0_usb_ltm_host_req LTM interface to software [12:12] read-only u0_usb_ltm_host_req_halt LTM interface to software [13:13] read-write u0_usb_mdctrl_clk_sel [14:14] read-write u0_usb_mdctrl_clk_status [15:15] read-only u0_usb_mode_strap Can only be changed when pwrup_rst_n is low [18:16] read-write 0 7 u0_usb_otg_suspendm [19:19] read-write u0_usb_otg_suspendm_byps [20:20] read-write u0_usb_phy_bvalid [21:21] read-only u0_usb_pll_en [22:22] read-write u0_usb_refclk_mode [23:23] read-write u0_cdn_usb_rid_a_comp_sts [24:24] read-write u0_cdn_usb_rid_b_comp_sts [25:25] read-write u0_cdn_usb_rid_c_comp_sts [26:26] read-write u0_usb_rid_float_comp_en [27:27] read-only u0_usb_rid_float_comp_sts [28:28] read-write u0_usb_rid_gnd_comp_sts [29:29] read-write u0_usb_rid_nonfloat_comp_en [30:30] read-only u0_usb_rx_dm [31:31] read-only stg_syscfg_2 STG SYSCONSAIF SYSCFG 8 0x8 0x20 0x00041000 u0_usb_rx_dp [0:0] read-only u0_usb_rx_rcv [1:1] read-only u0_usb_self_test For software bist_test [2:2] read-write u0_usb_sessend [3:3] read-only u0_usb_sessvalid [4:4] read-only u0_usb_sof [5:5] read-only u0_usb_test_bist For software bist_test [6:6] read-only u0_usb_usbdev_main_power_off_ack [7:7] read-only u0_usb_usbdev_main_power_off_ready [8:8] read-only u0_usb_usbdev_main_power_off_req [9:9] read-write u0_usb_usbdev_main_power_on_ready [10:10] read-only u0_usb_usbdev_main_power_on_req [11:11] read-only u0_usb_usbdev_main_power_on_valid [12:12] read-write u0_usb_usbdev_power_off_ack [13:13] read-only u0_usb_usbdev_power_off_ready [14:14] read-only u0_usb_usbdev_power_off_req [15:15] read-write u0_usb_usbdev_power_on_ready [16:16] read-only u0_usb_usbdev_power_on_req [17:17] read-only u0_usb_usbdev_power_on_valid [18:18] read-write u0_usb_utmi_dmpulldown_sit [19:19] read-write u0_usb_utmi_dppulldown_sit [20:20] read-write u0_usb_utmi_fslsserialmode_sit [21:21] read-write u0_usb_utmi_hostdisconnect_sit [22:22] read-only u0_usb_utmi_iddig_sit [23:23] read-only u0_usb_utmi_idpullup_sit [24:24] read-write u0_usb_utmi_linestate_sit [26:25] read-only u0_usb_utmi_opmode_sit [28:27] read-write 0 3 u0_usb_utmi_rxactive_sit [29:29] read-only u0_usb_utmi_rxerror_sit [30:30] read-only u0_usb_utmi_rxvalid_sit [31:31] read-only stg_syscfg_3 STG SYSCONSAIF SYSCFG 12 0xC 0x20 0x00000002 u0_usb_utmi_rxvalidh_sit [0:0] read-only u0_usb_utmi_sessvld [1:1] read-write u0_usb_utmi_termselect_sit [2:2] read-write u0_usb_utmi_tx_dat_sit [3:3] read-write u0_usb_utmi_tx_enable_n_sit [4:4] read-write u0_usb_utmi_tx_se0_sit [5:5] read-write u0_usb_utmi_txbitstuffenable_sit [6:6] read-write u0_usb_utmi_txready_sit [7:7] read-only u0_usb_utmi_txvalid_sit [8:8] read-write u0_usb_utmi_txvalidh_sit [9:9] read-write u0_usb_utmi_vbusvalid_sit [10:10] read-only u0_usb_utmi_xcvrselect_sit [12:11] read-write 0 3 u0_usb_utmi_vdm_src_en [13:13] read-only u0_usb_utmi_vdp_src_en [14:14] read-only u0_usb_wakeup [15:15] read-write u0_usb_xhc_d0_ack [16:16] read-only u0_usb_xhc_d0_req [17:17] read-write stg_syscfg_4 STG SYSCONSAIF SYSCFG 16 0x10 0x20 0x00000000 u0_usb_xhci_debug_bus [31:0] read-only stg_syscfg_5 STG SYSCONSAIF SYSCFG 20 0x14 0x20 0x00000000 u0_usb_xhci_debug_link_state [30:0] read-only stg_syscfg_6 STG SYSCONSAIF SYSCFG 24 0x18 0x20 0x00008200 u0_usb_xhci_debug_sel [4:0] read-write 0 15 u0_usb_xhci_main_power_off_ack [5:5] read-only u0_usb_xhci_main_power_off_req [6:6] read-write u0_usb_xhci_main_power_on_ready [7:7] read-only u0_usb_xhci_main_power_on_req [8:8] read-only u0_usb_xhci_main_power_on_valid [9:9] read-write u0_usb_xhci_power_off_ack [10:10] read-only u0_usb_xhci_power_off_ready [11:11] read-only u0_usb_xhci_power_off_req [12:12] read-write u0_usb_xhci_power_on_ready [13:13] read-only u0_usb_xhci_power_on_req [14:14] read-only u0_usb_xhci_power_on_valid [15:15] read-write u0_e2_cease_from_tile_0 [16:16] read-only u0_e2_debug_from_tile_0 [17:17] read-only u0_e2_halt_from_tile_0 [18:18] read-only stg_syscfg_7 STG SYSCONSAIF SYSCFG 28 0x1C 0x20 0x00000000 u0_e2_nmi_exception_vector [31:0] read-write 0 4294967295 stg_syscfg_8 STG SYSCONSAIF SYSCFG 32 0x20 0x20 0x00000000 u0_e2_nmi_interrupt_vector [31:0] read-write 0 4294967295 stg_syscfg_9 STG SYSCONSAIF SYSCFG 36 0x24 0x20 0x00000000 u0_e2_reset_vector_0 [31:0] read-write 0 4294967295 stg_syscfg_10 STG SYSCONSAIF SYSCFG 40 0x28 0x20 0x00000000 u0_e2_wfi_from_tile_0 [0:0] read-only stg_syscfg_11 STG SYSCONSAIF SYSCFG 44 0x2C 0x20 0x00000000 u0_hifi4_altresetvec Reset Vector Address [31:0] read-write 0 4294967295 stg_syscfg_12 STG SYSCONSAIF SYSCFG 48 0x30 0x20 0x00000000 u0_hifi4_breakin Debug signal [0:0] read-write u0_hifi4_breakinack Debug signal [1:1] read-only u0_hifi4_breakout Debug signal [2:2] read-only u0_hifi4_breakoutack Debug signal [3:3] read-write u0_hifi4_debugmode Debug signal [4:4] read-only u0_hifi4_doubleexceptionerror Fault Handling Signals [5:5] read-only u0_hifi4_iram0loadstore Indicates that iram0 works [6:6] read-only u0_hifi4_iram1loadstore Indicates that iram1 works [7:7] read-only u0_hifi4_ocdhaltonreset Debug signal [8:8] read-write u0_hifi4_pfatalerror Fault Handling Signals [9:9] read-only stg_syscfg_13 STG SYSCONSAIF SYSCFG 52 0x34 0x20 0x00000000 u0_hifi4_pfaultinfo Fault Handling Signals [31:0] read-only stg_syscfg_14 STG SYSCONSAIF SYSCFG 56 0x38 0x20 0x00000000 u0_hifi4_pfaultinfovalid Fault Handling Signals [0:0] read-only u0_hifi4_prid Module ID [16:1] read-write 0 65535 u0_hifi4_pwaitmode Wait Mode [17:17] read-only u0_hifi4_runstall Run Stall [18:18] read-write stg_syscfg_15 STG SYSCONSAIF SYSCFG 60 0x3C 0x20 0x00000000 u0_hifi4_scfg_dsp_mst_offset_master Indicates that master port remap address [11:0] read-write 0 4095 u0_hifi4_scfg_dsp_mst_offset_dma Indicates the DMA port remap address [27:16] read-write 0 4095 stg_syscfg_16 STG SYSCONSAIF SYSCFG 64 0x40 0x20 0x40000000 u0_hifi4_scfg_dsp_slv_offset The value indicates the slave port remap address [31:0] read-write 0 4294967295 stg_syscfg_17 STG SYSCONSAIF SYSCFG 68 0x44 0x20 0x00000D54 u0_hifi4_scfg_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [0:0] read-write u0_hifi4_scfg_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [1:1] read-write u0_hifi4_scfg_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [3:2] read-write u0_hifi4_scfg_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [5:4] read-write u0_hifi4_scfg_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [7:6] read-write u0_hifi4_scfg_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write u0_hifi4_scfg_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write u0_hifi4_scfg_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write u0_hifi4_statvectorsel When the value is 1, it indicates that the AltResetVec is valid [12:12] read-write u0_hifi4_trigin_idma DMA port trigger [13:13] read-write u0_hifi4_trigout_idma DMA port trigger [14:14] read-only u0_hifi4_xocdmode Debug signal [15:15] read-only u0_pcie_align_detect [16:16] read-only stg_syscfg_18 STG SYSCONSAIF SYSCFG 72 0x48 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_31_0 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_19 STG SYSCONSAIF SYSCFG 76 0x4C 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_63_32 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_20 STG SYSCONSAIF SYSCFG 80 0x50 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_95_64 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_21 STG SYSCONSAIF SYSCFG 84 0x54 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_127_96 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_22 STG SYSCONSAIF SYSCFG 88 0x58 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_159_128 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_23 STG SYSCONSAIF SYSCFG 92 0x5C 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_191_160 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_24 STG SYSCONSAIF SYSCFG 96 0x60 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_223_192 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_25 STG SYSCONSAIF SYSCFG 100 0x64 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_255_224 PCIE AXI4 ARATOMOP MST0 (little-endian) [31:0] read-only stg_syscfg_26 STG SYSCONSAIF SYSCFG 104 0x68 0x20 0x00000000 u0_pcie_axi4_mst0_aratomop_257_256 PCIE AXI4 ARATOMOP (little-endian) [1:0] read-only u0_pcie_axi4_mst0_arfunc PCIE AXI4 ARFUNC [16:2] read-only u0_pcie_axi4_mst0_arregion PCIE AXI4 ARREGION [20:17] read-only stg_syscfg_27 STG SYSCONSAIF SYSCFG 108 0x6C 0x20 0x00000000 u0_pcie_axi4_mst0_aruser_31_0 PCIE AXI4 ARUSER (little-endian) [31:0] read-only stg_syscfg_28 STG SYSCONSAIF SYSCFG 112 0x70 0x20 0x00000000 u0_pcie_axi4_mst0_aruser_52_32 PCIE AXI4 ARUSER (little-endian) [20:0] read-only stg_syscfg_29 STG SYSCONSAIF SYSCFG 116 0x74 0x20 0x00000000 u0_pcie_axi4_mst0_awfunc [14:0] read-only u0_pcie_axi4_mst0_awregion [18:15] read-only stg_syscfg_30 STG SYSCONSAIF SYSCFG 120 0x78 0x20 0x00000000 u0_pcie_axi4_mst0_awuser_31_0 PCIE AXI4 AWUSER (little-endian) [31:0] read-only stg_syscfg_31 STG SYSCONSAIF SYSCFG 124 0x7C 0x20 0x00000000 u0_pcie_axi4_mst0_awuser_42_32 PCIE AXI4 MST0 AWUSER [10:0] read-only u0_pcie_axi4_mst0_rderr PCIE AXI4 MST0 RDERR [18:11] read-write 0 255 stg_syscfg_32 STG SYSCONSAIF SYSCFG 128 0x80 0x20 0x00000000 u0_pcie_axi4_mst0_ruser PCIE AXI4 RUSER [31:0] read-write 0 4294967295 stg_syscfg_33 STG SYSCONSAIF SYSCFG 132 0x84 0x20 0x00000000 u0_pcie_axi4_mst0_wderr PCIE AXI4 WDERR [7:0] read-only stg_syscfg_34 STG SYSCONSAIF SYSCFG 136 0x88 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_31_0 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_35 STG SYSCONSAIF SYSCFG 140 0x8C 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_63_32 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_36 STG SYSCONSAIF SYSCFG 144 0x90 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_95_64 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_37 STG SYSCONSAIF SYSCFG 148 0x94 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_127_96 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_38 STG SYSCONSAIF SYSCFG 152 0x98 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_159_128 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_39 STG SYSCONSAIF SYSCFG 156 0x9C 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_191_160 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_40 STG SYSCONSAIF SYSCFG 160 0xA0 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_223_192 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_41 STG SYSCONSAIF SYSCFG 164 0xA4 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_255_224 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_42 STG SYSCONSAIF SYSCFG 168 0xA8 0x20 0x00000000 u0_pcie_axi4_slv0_aratomop_257_256 PCIE AXI4 ARATOMOP SLV0 (little-endian) [1:0] read-write 0 3 u0_pcie_axi4_slv0_arfunc PCIE AXI4 SLV0 ARFUNC [16:2] read-write 0 32767 u0_pcie_axi4_slv0_arregion PCIE AXI4 SLV0 ARREGION [20:17] read-write 0 15 stg_syscfg_43 STG SYSCONSAIF SYSCFG 172 0xAC 0x20 0x00000000 u0_pcie_axi4_slv0_aruser_31_0 PCIE AXI4 SLV0 ARUSER (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_44 STG SYSCONSAIF SYSCFG 176 0xB0 0x20 0x00000000 u0_pcie_axi4_slv0_aruser_40_32 PCIE AXI4 SLV0 ARUSER (little-endian) [8:0] read-write 0 511 u0_pcie_axi4_slv0_awfunc PCIE AXI SLV0 AWFUNC [23:9] read-write 0 32767 u0_pcie_axi4_slv0_awregion PCIE AXI4 SLV0 AWREGION [27:24] read-write 0 15 stg_syscfg_45 STG SYSCONSAIF SYSCFG 180 0xB4 0x20 0x00000000 u0_pcie_axi4_slv0_awuser_31_0 PCIE AXI4 SLV0 AWUSER (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_46 STG SYSCONSAIF SYSCFG 184 0xB8 0x20 0x00000000 u0_pcie_axi4_slv0_awuser_40_32 PCIE AXI4 SLV0 AWUSER (little-endian) [8:0] read-write 0 511 u0_pcie_axi4_slv0_rderr PCIE AXI4 SLV0 RDERR [16:9] read-only stg_syscfg_47 STG SYSCONSAIF SYSCFG 188 0xBC 0x20 0x00000000 u0_pcie_axi4_slv0_ruser PCIE AXI4 SLV0 RUSER [31:0] read-only stg_syscfg_48 STG SYSCONSAIF SYSCFG 192 0xC0 0x20 0x00000000 u0_pcie_axi4_slv0_wderr PCIE AXI4 SLV0 WDERR [7:0] read-write 0 255 u0_pcie_axi4_slvl_arfunc PCIE AXI4 SLV1 ARFUNC [22:8] read-write 0 32767 stg_syscfg_49 STG SYSCONSAIF SYSCFG 196 0xC4 0x20 0x00000000 u0_pcie_axi4_slvl_awfunc PCIE AXI4 SLV1 AWFUNC [14:0] read-write 0 32767 u0_pcie_bus_width_o PCIE Bus width [16:15] read-only u0_pcie_bypass_codec PCIE Bypass Codec [17:17] read-write u0_pcie_ckref_src PCIE Clock Reference Source [19:18] read-write 0 3 u0_pcie_clk_sel PCIE Clock Select [21:20] read-write 0 3 u0_pcie_clkreq PCIE Clock Req [22:22] read-write stg_syscfg_50 STG SYSCONSAIF SYSCFG 200 0xC8 0x20 0x00000000 u0_pcie_k_phyparam_31_0 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_51 STG SYSCONSAIF SYSCFG 204 0xCC 0x20 0x00000000 u0_pcie_k_phyparam_63_32 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_52 STG SYSCONSAIF SYSCFG 208 0xD0 0x20 0x00000000 u0_pcie_k_phyparam_95_64 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_53 STG SYSCONSAIF SYSCFG 212 0xD4 0x20 0x00000000 u0_pcie_k_phyparam_127_96 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_54 STG SYSCONSAIF SYSCFG 216 0xD8 0x20 0x00000000 u0_pcie_k_phyparam_159_128 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_55 STG SYSCONSAIF SYSCFG 220 0xDC 0x20 0x00000000 u0_pcie_k_phyparam_191_160 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_56 STG SYSCONSAIF SYSCFG 224 0xE0 0x20 0x00000000 u0_pcie_k_phyparam_223_192 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_57 STG SYSCONSAIF SYSCFG 228 0xE4 0x20 0x00000000 u0_pcie_k_phyparam_255_224 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_58 STG SYSCONSAIF SYSCFG 232 0xE8 0x20 0x00000000 u0_pcie_k_phyparam_287_256 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_59 STG SYSCONSAIF SYSCFG 236 0xEC 0x20 0x00000000 u0_pcie_k_phyparam_319_288 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_60 STG SYSCONSAIF SYSCFG 240 0xF0 0x20 0x00000000 u0_pcie_k_phyparam_351_320 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_61 STG SYSCONSAIF SYSCFG 244 0xF4 0x20 0x00000000 u0_pcie_k_phyparam_383_352 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_62 STG SYSCONSAIF SYSCFG 248 0xF8 0x20 0x00000000 u0_pcie_k_phyparam_415_384 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_63 STG SYSCONSAIF SYSCFG 252 0xFC 0x20 0x00000000 u0_pcie_k_phyparam_447_416 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_64 STG SYSCONSAIF SYSCFG 256 0x100 0x20 0x00000000 u0_pcie_k_phyparam_479_448 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_65 STG SYSCONSAIF SYSCFG 260 0x104 0x20 0x00000000 u0_pcie_k_phyparam_511_480 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_66 STG SYSCONSAIF SYSCFG 264 0x108 0x20 0x00000000 u0_pcie_k_phyparam_543_512 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_67 STG SYSCONSAIF SYSCFG 268 0x10C 0x20 0x00000000 u0_pcie_k_phyparam_575_544 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_68 STG SYSCONSAIF SYSCFG 272 0x110 0x20 0x00000000 u0_pcie_k_phyparam_607_576 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_69 STG SYSCONSAIF SYSCFG 276 0x114 0x20 0x00000000 u0_pcie_k_phyparam_639_608 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_70 STG SYSCONSAIF SYSCFG 280 0x118 0x20 0x00000000 u0_pcie_k_phyparam_671_640 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_71 STG SYSCONSAIF SYSCFG 284 0x11C 0x20 0x00000000 u0_pcie_k_phyparam_703_672 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_72 STG SYSCONSAIF SYSCFG 288 0x120 0x20 0x00000000 u0_pcie_k_phyparam_735_704 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_73 STG SYSCONSAIF SYSCFG 292 0x124 0x20 0x00000000 u0_pcie_k_phyparam_767_736 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_74 STG SYSCONSAIF SYSCFG 296 0x128 0x20 0x00000000 u0_pcie_k_phyparam_799_768 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_75 STG SYSCONSAIF SYSCFG 300 0x12C 0x20 0x00000000 u0_pcie_k_phyparam_831_800 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_76 STG SYSCONSAIF SYSCFG 304 0x130 0x20 0x00000000 u0_pcie_k_phyparam_839_832 PCIE PHY Parameter (little-endian) [7:0] read-write 0 255 u0_pcie_k_rp_nep PCIE RP NEP [8:8] read-write u0_pcie_l1sub_entack PCIE L1SUB ENTACK [9:9] read-only u0_pcie_l1sub_entreq PCIE L1SUB ENREQ [10:10] read-write stg_syscfg_77 STG SYSCONSAIF SYSCFG 308 0x134 0x20 0x00000000 u0_pcie_local_interrupt_in PCIE Local Interrupt IN [31:0] read-write 0 4294967295 stg_syscfg_78 STG SYSCONSAIF SYSCFG 312 0x138 0x20 0x04800001 u0_pcie_mperstn PCIE MPERSTN [0:0] read-write u0_pcie_ebuf_mode PCIE EBUF Mode [1:1] read-write u0_pcie_phy_test_cfg PCIE PHY Test Config [24:2] read-write 0 8388607 u0_pcie_rx_eq_training PCIE RX EQ Training [25:25] read-write u0_pcie_rxterm_en PCIE RXTERM Enable [26:26] read-write u0_pcie_tx_onezeros PCIE TX One Zeros [27:27] read-write stg_syscfg_79 STG SYSCONSAIF SYSCFG 316 0x13C 0x20 0x00000000 u0_pcie_pf0_offset PCIE PF Offset [19:0] read-write 0 1048575 stg_syscfg_80 STG SYSCONSAIF SYSCFG 320 0x140 0x20 0x00000000 u0_pcie_pf1_offset PCIE PF Offset [19:0] read-write 0 1048575 stg_syscfg_81 STG SYSCONSAIF SYSCFG 324 0x144 0x20 0x00000000 u0_pcie_pf2_offset PCIE PF Offset [19:0] read-write 0 1048575 stg_syscfg_82 STG SYSCONSAIF SYSCFG 328 0x148 0x20 0x00000000 u0_pcie_pf3_offset PCIE PF3 Offset [19:0] read-write 0 1048575 u0_pcie_phy_mode PCIE PHY Mode [21:20] read-write 0 3 u0_pcie_pl_clkrem_allow PCIE PL Clock REM Allow [22:22] read-write u0_pcie_pl_clkreq_oen PCIE PL Clock Request OEN [23:23] read-only u0_pcie_pl_equ_phase PCIE PL EQU Phase [25:24] read-only u0_pcie_pl_ltssm PCIE PL LTSSM [30:26] read-only stg_syscfg_83 STG SYSCONSAIF SYSCFG 332 0x14C 0x20 0x00000000 u0_pcie_pl_pclk_rate PCIE PL PCLK Rate [4:0] read-only stg_syscfg_84 STG SYSCONSAIF SYSCFG 336 0x150 0x20 0x00000000 u0_pcie_pl_sideband_in_31_0 PCIE PL Sideband IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_85 STG SYSCONSAIF SYSCFG 340 0x154 0x20 0x00000000 u0_pcie_pl_sideband_in_63_32 PCIE PL Sideband IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_86 STG SYSCONSAIF SYSCFG 344 0x158 0x20 0x00000000 u0_pcie_pl_sideband_out_31_0 PCIE PL Sideband OUT (little-endian) [31:0] read-only stg_syscfg_87 STG SYSCONSAIF SYSCFG 348 0x15C 0x20 0x00000000 u0_pcie_pl_sideband_out_63_32 PCIE PL Sideband OUT (little-endian) [31:0] read-only stg_syscfg_88 STG SYSCONSAIF SYSCFG 352 0x160 0x20 0x00000001 u0_pcie_pl_wake_in PCIE PL Wake IN [0:0] read-write u0_pcie_pl_wake_oen PCIE PL Wake OEN [1:1] read-only u0_pcie_rx_standby_0 PCIE RX Standby [2:2] read-only stg_syscfg_89 STG SYSCONSAIF SYSCFG 356 0x164 0x20 0x00000000 u0_pcie_test_in_31_0 PCIE Test IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_90 STG SYSCONSAIF SYSCFG 360 0x168 0x20 0x00000000 u0_pcie_test_in_63_32 PCIE Test IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_91 STG SYSCONSAIF SYSCFG 364 0x16C 0x20 0x00000000 u0_pcie_test_out_bridge_31_0 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_92 STG SYSCONSAIF SYSCFG 368 0x170 0x20 0x00000000 u0_pcie_test_out_bridge_63_32 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_93 STG SYSCONSAIF SYSCFG 372 0x174 0x20 0x00000000 u0_pcie_test_out_bridge_95_64 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_94 STG SYSCONSAIF SYSCFG 376 0x178 0x20 0x00000000 u0_pcie_test_out_bridge_127_96 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_95 STG SYSCONSAIF SYSCFG 380 0x17C 0x20 0x00000000 u0_pcie_test_out_bridge_159_128 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_96 STG SYSCONSAIF SYSCFG 384 0x180 0x20 0x00000000 u0_pcie_test_out_bridge_191_160 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_97 STG SYSCONSAIF SYSCFG 388 0x184 0x20 0x00000000 u0_pcie_test_out_bridge_223_192 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_98 STG SYSCONSAIF SYSCFG 392 0x188 0x20 0x00000000 u0_pcie_test_out_bridge_255_224 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_99 STG SYSCONSAIF SYSCFG 396 0x18C 0x20 0x00000000 u0_pcie_test_out_bridge_287_256 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_100 STG SYSCONSAIF SYSCFG 400 0x190 0x20 0x00000000 u0_pcie_test_out_bridge_319_288 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_101 STG SYSCONSAIF SYSCFG 404 0x194 0x20 0x00000000 u0_pcie_test_out_bridge_351_320 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_102 STG SYSCONSAIF SYSCFG 408 0x198 0x20 0x00000000 u0_pcie_test_out_bridge_383_352 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_103 STG SYSCONSAIF SYSCFG 412 0x19C 0x20 0x00000000 u0_pcie_test_out_bridge_415_384 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_104 STG SYSCONSAIF SYSCFG 416 0x1A0 0x20 0x00000000 u0_pcie_test_out_bridge_447_416 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_105 STG SYSCONSAIF SYSCFG 420 0x1A4 0x20 0x00000000 u0_pcie_test_out_bridge_479_448 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_106 STG SYSCONSAIF SYSCFG 424 0x1A8 0x20 0x00000000 u0_pcie_test_out_bridge_511_480 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_107 STG SYSCONSAIF SYSCFG 428 0x1AC 0x20 0x00000000 u0_pcie_test_out_31_0 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_108 STG SYSCONSAIF SYSCFG 432 0x1B0 0x20 0x00000000 u0_pcie_test_out_63_32 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_109 STG SYSCONSAIF SYSCFG 436 0x1B4 0x20 0x00000000 u0_pcie_test_out_95_64 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_110 STG SYSCONSAIF SYSCFG 440 0x1B8 0x20 0x00000000 u0_pcie_test_out_127_96 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_111 STG SYSCONSAIF SYSCFG 444 0x1BC 0x20 0x00000000 u0_pcie_test_out_159_128 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_112 STG SYSCONSAIF SYSCFG 448 0x1C0 0x20 0x00000000 u0_pcie_test_out_191_160 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_113 STG SYSCONSAIF SYSCFG 452 0x1C4 0x20 0x00000000 u0_pcie_test_out_223_192 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_114 STG SYSCONSAIF SYSCFG 456 0x1C8 0x20 0x00000000 u0_pcie_test_out_255_224 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_115 STG SYSCONSAIF SYSCFG 460 0x1CC 0x20 0x00000000 u0_pcie_test_out_287_256 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_116 STG SYSCONSAIF SYSCFG 464 0x1D0 0x20 0x00000000 u0_pcie_test_out_319_288 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_117 STG SYSCONSAIF SYSCFG 468 0x1D4 0x20 0x00000000 u0_pcie_test_out_351_320 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_118 STG SYSCONSAIF SYSCFG 472 0x1D8 0x20 0x00000000 u0_pcie_test_out_383_352 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_119 STG SYSCONSAIF SYSCFG 476 0x1DC 0x20 0x00000000 u0_pcie_test_out_415_384 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_120 STG SYSCONSAIF SYSCFG 480 0x1E0 0x20 0x00000000 u0_pcie_test_out_447_416 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_121 STG SYSCONSAIF SYSCFG 484 0x1E4 0x20 0x00000000 u0_pcie_test_out_479_448 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_122 STG SYSCONSAIF SYSCFG 488 0x1E8 0x20 0x00000000 u0_pcie_test_out_511_480 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_123 STG SYSCONSAIF SYSCFG 492 0x1EC 0x20 0x00000C80 u0_pcie_test_sel PCIE Test Selector [3:0] read-write 0 15 u0_pcie_tl_clock_freq PCIE TL Clock Frequency [25:4] read-write 0 4194303 stg_syscfg_124 STG SYSCONSAIF SYSCFG 496 0x1F0 0x20 0x00000000 u0_pcie_tl_ctrl_hotplug PCIE TL Control Hotplug [15:0] read-only u0_pcie_tl_report_hotplug PCIE TL Report Hotplug [31:16] read-write 0 65535 stg_syscfg_125 STG SYSCONSAIF SYSCFG 500 0x1F4 0x20 0x006AA008 u0_pcie_tx_pattern PCIE TX Pattern [1:0] read-write 0 3 u0_pcie_usb3_bus_width PCIE USB3 Bus Width [3:2] read-write 0 3 u0_pcie_usb3_phy_enable PCIE USB3 PHY Enable [4:4] read-write u0_pcie_usb3_rate PCIE USB3 Rate [6:5] read-write 0 3 u0_pcie_usb3_rx_standby PCIE USB3 RX Standby [7:7] read-write u0_pcie_xwdecerr PCIE XWDECERR [8:8] read-only u0_pcie_xwerrclr PCIE XWERRCLR [9:9] read-write u0_pcie_xwslverr PCIE XWSLVERR [10:10] read-only u0_sec_top_sramcfg_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [11:11] read-write u0_sec_top_sramcfg_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [12:12] read-write u0_sec_top_sramcfg_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [14:13] read-write u0_sec_top_sramcfg_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [16:15] read-write u0_sec_top_sramcfg_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [18:17] read-write u0_sec_top_sramcfg_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [20:19] read-write u0_sec_top_sramcfg_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [21:21] read-write u0_sec_top_sramcfg_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [22:22] read-write u0_pcie_align_detect PCIE Align Detect [23:23] read-only stg_syscfg_126 STG SYSCONSAIF SYSCFG 504 0x1F8 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_31_0 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_127 STG SYSCONSAIF SYSCFG 508 0x1FC 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_63_32 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_128 STG SYSCONSAIF SYSCFG 512 0x200 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_95_64 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_129 STG SYSCONSAIF SYSCFG 516 0x204 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_127_96 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_130 STG SYSCONSAIF SYSCFG 520 0x208 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_159_128 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_131 STG SYSCONSAIF SYSCFG 524 0x20C 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_191_160 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_132 STG SYSCONSAIF SYSCFG 528 0x210 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_223_192 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_133 STG SYSCONSAIF SYSCFG 532 0x214 0x20 0x00000000 u1_pcie_axi4_mst0_aratomap_255_224 PCIE AXI4 MST0 ARATOMAP (little-endian) [31:0] read-only stg_syscfg_134 STG SYSCONSAIF SYSCFG 536 0x218 0x20 0x00000000 u1_pcie_axi4_mst0_aratomop_257_256 PCIE AXI4 ARATOMOP (little-endian) [1:0] read-only u1_pcie_axi4_mst0_arfunc PCIE AXI4 ARFUNC [16:2] read-only u1_pcie_axi4_mst0_arregion PCIE AXI4 ARREGION [20:17] read-only stg_syscfg_135 STG SYSCONSAIF SYSCFG 540 0x21C 0x20 0x00000000 u1_pcie_axi4_mst0_aruser_31_0 PCIE AXI4 ARUSER (little-endian) [31:0] read-only stg_syscfg_136 STG SYSCONSAIF SYSCFG 544 0x220 0x20 0x00000000 u1_pcie_axi4_mst0_aruser_52_32 PCIE AXI4 ARUSER (little-endian) [20:0] read-only stg_syscfg_137 STG SYSCONSAIF SYSCFG 548 0x224 0x20 0x00000000 u1_pcie_axi4_mst0_awfunc [14:0] read-only u1_pcie_axi4_mst0_awregion [18:15] read-only stg_syscfg_138 STG SYSCONSAIF SYSCFG 552 0x228 0x20 0x00000000 u0_pcie_axi4_mst0_awuser_31_0 PCIE AXI4 AWUSER (little-endian) [31:0] read-only stg_syscfg_139 STG SYSCONSAIF SYSCFG 556 0x22C 0x20 0x00000000 u1_pcie_axi4_mst0_awuser_42_32 PCIE AXI4 MST0 AWUSER [10:0] read-only u1_pcie_axi4_mst0_rderr PCIE AXI4 MST0 RDERR [18:11] read-write 0 255 stg_syscfg_140 STG SYSCONSAIF SYSCFG 560 0x230 0x20 0x00000000 u1_pcie_axi4_mst0_ruser PCIE AXI4 RUSER [31:0] read-write 0 4294967295 stg_syscfg_141 STG SYSCONSAIF SYSCFG 564 0x234 0x20 0x00000000 u1_pcie_axi4_mst0_wderr PCIE AXI4 WDERR [7:0] read-only stg_syscfg_142 STG SYSCONSAIF SYSCFG 568 0x238 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_31_0 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_143 STG SYSCONSAIF SYSCFG 572 0x23C 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_63_32 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_144 STG SYSCONSAIF SYSCFG 576 0x240 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_95_64 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_145 STG SYSCONSAIF SYSCFG 580 0x244 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_127_96 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_146 STG SYSCONSAIF SYSCFG 584 0x248 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_159_128 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_147 STG SYSCONSAIF SYSCFG 588 0x24C 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_191_160 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_148 STG SYSCONSAIF SYSCFG 592 0x250 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_223_192 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_149 STG SYSCONSAIF SYSCFG 596 0x254 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_255_224 PCIE AXI4 ARATOMOP SLV0 (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_150 STG SYSCONSAIF SYSCFG 600 0x258 0x20 0x00000000 u1_pcie_axi4_slv0_aratomop_257_256 PCIE AXI4 ARATOMOP SLV0 (little-endian) [1:0] read-write 0 3 u1_pcie_axi4_slv0_arfunc PCIE AXI4 SLV0 ARFUNC [16:2] read-write 0 32767 u1_pcie_axi4_slv0_arregion PCIE AXI4 SLV0 ARREGION [20:17] read-write 0 15 stg_syscfg_151 STG SYSCONSAIF SYSCFG 604 0x25C 0x20 0x00000000 u1_pcie_axi4_slv0_aruser_31_0 PCIE AXI4 SLV0 ARUSER (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_152 STG SYSCONSAIF SYSCFG 608 0x260 0x20 0x00000000 u1_pcie_axi4_slv0_aruser_40_32 PCIE AXI4 SLV0 ARUSER (little-endian) [8:0] read-write 0 511 u1_pcie_axi4_slv0_awfunc PCIE AXI SLV0 AWFUNC [23:9] read-write 0 32767 u1_pcie_axi4_slv0_awregion PCIE AXI4 SLV0 AWREGION [27:24] read-write 0 15 stg_syscfg_153 STG SYSCONSAIF SYSCFG 612 0x264 0x20 0x00000000 u1_pcie_axi4_slv0_awuser_31_0 PCIE AXI4 SLV0 AWUSER (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_154 STG SYSCONSAIF SYSCFG 616 0x268 0x20 0x00000000 u1_pcie_axi4_slv0_awuser_40_32 PCIE AXI4 SLV0 AWUSER (little-endian) [8:0] read-write 0 511 u1_pcie_axi4_slv0_rderr PCIE AXI4 SLV0 RDERR [16:9] read-only stg_syscfg_155 STG SYSCONSAIF SYSCFG 620 0x26C 0x20 0x00000000 u1_pcie_axi4_slv0_ruser PCIE AXI4 SLV0 RUSER [31:0] read-only stg_syscfg_156 STG SYSCONSAIF SYSCFG 624 0x270 0x20 0x00000000 u1_pcie_axi4_slv0_wderr PCIE AXI4 SLV0 WDERR [7:0] read-write 0 255 u1_pcie_axi4_slvl_arfunc PCIE AXI4 SLV1 ARFUNC [22:8] read-write 0 32767 stg_syscfg_157 STG SYSCONSAIF SYSCFG 628 0x274 0x20 0x00000000 u1_pcie_axi4_slvl_awfunc PCIE AXI4 SLV1 AWFUNC [14:0] read-write 0 32767 u1_pcie_bus_width_o PCIE Bus width [16:15] read-only u1_pcie_bypass_codec PCIE Bypass Codec [17:17] read-write u1_pcie_ckref_src PCIE Clock Reference Source [19:18] read-write 0 3 u1_pcie_clk_sel PCIE Clock Select [21:20] read-write 0 3 u1_pcie_clkreq PCIE Clock Req [22:22] read-write stg_syscfg_158 STG SYSCONSAIF SYSCFG 632 0x278 0x20 0x00000000 u1_pcie_k_phyparam_31_0 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_159 STG SYSCONSAIF SYSCFG 636 0x27C 0x20 0x00000000 u1_pcie_k_phyparam_63_32 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_160 STG SYSCONSAIF SYSCFG 640 0x280 0x20 0x00000000 u1_pcie_k_phyparam_95_64 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_161 STG SYSCONSAIF SYSCFG 644 0x284 0x20 0x00000000 u1_pcie_k_phyparam_127_96 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_162 STG SYSCONSAIF SYSCFG 648 0x288 0x20 0x00000000 u1_pcie_k_phyparam_159_128 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_163 STG SYSCONSAIF SYSCFG 652 0x28C 0x20 0x00000000 u1_pcie_k_phyparam_191_160 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_164 STG SYSCONSAIF SYSCFG 656 0x290 0x20 0x00000000 u1_pcie_k_phyparam_223_192 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_165 STG SYSCONSAIF SYSCFG 660 0x294 0x20 0x00000000 u1_pcie_k_phyparam_255_224 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_166 STG SYSCONSAIF SYSCFG 664 0x298 0x20 0x00000000 u1_pcie_k_phyparam_287_256 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_167 STG SYSCONSAIF SYSCFG 668 0x29C 0x20 0x00000000 u1_pcie_k_phyparam_319_288 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_168 STG SYSCONSAIF SYSCFG 672 0x2A0 0x20 0x00000000 u1_pcie_k_phyparam_351_320 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_169 STG SYSCONSAIF SYSCFG 676 0x2A4 0x20 0x00000000 u1_pcie_k_phyparam_383_352 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_170 STG SYSCONSAIF SYSCFG 680 0x2A8 0x20 0x00000000 u1_pcie_k_phyparam_415_384 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_171 STG SYSCONSAIF SYSCFG 684 0x2AC 0x20 0x00000000 u1_pcie_k_phyparam_447_416 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_172 STG SYSCONSAIF SYSCFG 688 0x2B0 0x20 0x00000000 u1_pcie_k_phyparam_479_448 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_173 STG SYSCONSAIF SYSCFG 692 0x2B4 0x20 0x00000000 u1_pcie_k_phyparam_511_480 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_174 STG SYSCONSAIF SYSCFG 696 0x2B8 0x20 0x00000000 u1_pcie_k_phyparam_543_512 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_175 STG SYSCONSAIF SYSCFG 700 0x2BC 0x20 0x00000000 u1_pcie_k_phyparam_575_544 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_176 STG SYSCONSAIF SYSCFG 704 0x2C0 0x20 0x00000000 u1_pcie_k_phyparam_607_576 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_177 STG SYSCONSAIF SYSCFG 708 0x2C4 0x20 0x00000000 u1_pcie_k_phyparam_639_608 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_178 STG SYSCONSAIF SYSCFG 712 0x2C8 0x20 0x00000000 u1_pcie_k_phyparam_671_640 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_179 STG SYSCONSAIF SYSCFG 716 0x2CC 0x20 0x00000000 u1_pcie_k_phyparam_703_672 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_180 STG SYSCONSAIF SYSCFG 720 0x2D0 0x20 0x00000000 u1_pcie_k_phyparam_735_704 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_181 STG SYSCONSAIF SYSCFG 724 0x2D4 0x20 0x00000000 u1_pcie_k_phyparam_767_736 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_182 STG SYSCONSAIF SYSCFG 728 0x2D8 0x20 0x00000000 u1_pcie_k_phyparam_799_768 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_183 STG SYSCONSAIF SYSCFG 732 0x2DC 0x20 0x00000000 u1_pcie_k_phyparam_831_800 PCIE PHY Parameter (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_184 STG SYSCONSAIF SYSCFG 736 0x2E0 0x20 0x00000000 u1_pcie_k_phyparam_839_832 PCIE PHY Parameter (little-endian) [7:0] read-write 0 255 u1_pcie_k_rp_nep PCIE RP NEP [8:8] read-write u1_pcie_l1sub_entack PCIE L1SUB ENTACK [9:9] read-only u1_pcie_l1sub_entreq PCIE L1SUB ENREQ [10:10] read-write stg_syscfg_185 STG SYSCONSAIF SYSCFG 740 0x2E4 0x20 0x00000000 u1_pcie_local_interrupt_in PCIE Local Interrupt IN [31:0] read-write 0 4294967295 stg_syscfg_186 STG SYSCONSAIF SYSCFG 744 0x2E8 0x20 0x04800001 u1_pcie_mperstn PCIE MPERSTN [0:0] read-write u1_pcie_ebuf_mode PCIE EBUF Mode [1:1] read-write u1_pcie_phy_test_cfg PCIE PHY Test Config [24:2] read-write 0 8388607 u1_pcie_rx_eq_training PCIE RX EQ Training [25:25] read-write u1_pcie_rxterm_en PCIE RXTERM Enable [26:26] read-write u1_pcie_tx_onezeros PCIE TX One Zeros [27:27] read-write stg_syscfg_187 STG SYSCONSAIF SYSCFG 748 0x2EC 0x20 0x00000000 u1_pcie_pf0_offset PCIE PF Offset [19:0] read-write 0 1048575 stg_syscfg_188 STG SYSCONSAIF SYSCFG 752 0x2F0 0x20 0x00000000 u1_pcie_pf1_offset PCIE PF Offset [19:0] read-write 0 1048575 stg_syscfg_189 STG SYSCONSAIF SYSCFG 756 0x2F4 0x20 0x00000000 u1_pcie_pf2_offset PCIE PF Offset [19:0] read-write 0 1048575 stg_syscfg_190 STG SYSCONSAIF SYSCFG 760 0x2F8 0x20 0x00000000 u1_pcie_pf3_offset PCIE PF3 Offset [19:0] read-write 0 1048575 u1_pcie_phy_mode PCIE PHY Mode [21:20] read-write 0 3 u1_pcie_pl_clkrem_allow PCIE PL Clock REM Allow [22:22] read-write u1_pcie_pl_clkreq_oen PCIE PL Clock Request OEN [23:23] read-only u0_pcie_pl_equ_phase PCIE PL EQU Phase [25:24] read-only u0_pcie_pl_ltssm PCIE PL LTSSM [30:26] read-only stg_syscfg_191 STG SYSCONSAIF SYSCFG 764 0x2FC 0x20 0x00000000 u1_pcie_pl_pclk_rate PCIE PL PCLK Rate [4:0] read-only stg_syscfg_192 STG SYSCONSAIF SYSCFG 768 0x300 0x20 0x00000000 u1_pcie_pl_sideband_in_31_0 PCIE PL Sideband IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_193 STG SYSCONSAIF SYSCFG 772 0x304 0x20 0x00000000 u1_pcie_pl_sideband_in_63_32 PCIE PL Sideband IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_194 STG SYSCONSAIF SYSCFG 776 0x308 0x20 0x00000000 u1_pcie_pl_sideband_out_31_0 PCIE PL Sideband OUT (little-endian) [31:0] read-only stg_syscfg_195 STG SYSCONSAIF SYSCFG 780 0x30C 0x20 0x00000000 u1_pcie_pl_sideband_out_63_32 PCIE PL Sideband OUT (little-endian) [31:0] read-only stg_syscfg_196 STG SYSCONSAIF SYSCFG 784 0x310 0x20 0x00000001 u1_pcie_pl_wake_in PCIE PL Wake IN [0:0] read-write u1_pcie_pl_wake_oen PCIE PL Wake OEN [1:1] read-only u1_pcie_rx_standby_0 PCIE RX Standby [2:2] read-only stg_syscfg_197 STG SYSCONSAIF SYSCFG 788 0x314 0x20 0x00000000 u1_pcie_test_in_31_0 PCIE Test IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_198 STG SYSCONSAIF SYSCFG 792 0x318 0x20 0x00000000 u1_pcie_test_in_63_32 PCIE Test IN (little-endian) [31:0] read-write 0 4294967295 stg_syscfg_199 STG SYSCONSAIF SYSCFG 796 0x31C 0x20 0x00000000 u1_pcie_test_out_bridge_31_0 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_200 STG SYSCONSAIF SYSCFG 800 0x320 0x20 0x00000000 u1_pcie_test_out_bridge_63_32 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_201 STG SYSCONSAIF SYSCFG 804 0x324 0x20 0x00000000 u1_pcie_test_out_bridge_95_64 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_202 STG SYSCONSAIF SYSCFG 808 0x328 0x20 0x00000000 u1_pcie_test_out_bridge_127_96 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_203 STG SYSCONSAIF SYSCFG 812 0x32C 0x20 0x00000000 u1_pcie_test_out_bridge_159_128 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_204 STG SYSCONSAIF SYSCFG 816 0x330 0x20 0x00000000 u1_pcie_test_out_bridge_191_160 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_205 STG SYSCONSAIF SYSCFG 820 0x334 0x20 0x00000000 u1_pcie_test_out_bridge_223_192 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_206 STG SYSCONSAIF SYSCFG 824 0x338 0x20 0x00000000 u1_pcie_test_out_bridge_255_224 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_207 STG SYSCONSAIF SYSCFG 828 0x33C 0x20 0x00000000 u1_pcie_test_out_bridge_287_256 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_208 STG SYSCONSAIF SYSCFG 832 0x340 0x20 0x00000000 u1_pcie_test_out_bridge_319_288 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_209 STG SYSCONSAIF SYSCFG 836 0x344 0x20 0x00000000 u1_pcie_test_out_bridge_351_320 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_210 STG SYSCONSAIF SYSCFG 840 0x348 0x20 0x00000000 u1_pcie_test_out_bridge_383_352 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_211 STG SYSCONSAIF SYSCFG 844 0x34C 0x20 0x00000000 u1_pcie_test_out_bridge_415_384 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_212 STG SYSCONSAIF SYSCFG 848 0x350 0x20 0x00000000 u1_pcie_test_out_bridge_447_416 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_213 STG SYSCONSAIF SYSCFG 852 0x354 0x20 0x00000000 u1_pcie_test_out_bridge_479_448 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_214 STG SYSCONSAIF SYSCFG 856 0x358 0x20 0x00000000 u1_pcie_test_out_bridge_511_480 PCIE Test OUT Bridge (little-endian) [31:0] read-only stg_syscfg_215 STG SYSCONSAIF SYSCFG 860 0x35C 0x20 0x00000000 u1_pcie_test_out_31_0 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_216 STG SYSCONSAIF SYSCFG 864 0x360 0x20 0x00000000 u1_pcie_test_out_63_32 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_217 STG SYSCONSAIF SYSCFG 868 0x364 0x20 0x00000000 u1_pcie_test_out_95_64 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_218 STG SYSCONSAIF SYSCFG 872 0x368 0x20 0x00000000 u1_pcie_test_out_127_96 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_219 STG SYSCONSAIF SYSCFG 876 0x36C 0x20 0x00000000 u1_pcie_test_out_159_128 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_220 STG SYSCONSAIF SYSCFG 880 0x370 0x20 0x00000000 u1_pcie_test_out_191_160 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_221 STG SYSCONSAIF SYSCFG 884 0x374 0x20 0x00000000 u1_pcie_test_out_223_192 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_222 STG SYSCONSAIF SYSCFG 888 0x378 0x20 0x00000000 u1_pcie_test_out_255_224 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_223 STG SYSCONSAIF SYSCFG 892 0x37C 0x20 0x00000000 u1_pcie_test_out_287_256 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_224 STG SYSCONSAIF SYSCFG 896 0x380 0x20 0x00000000 u1_pcie_test_out_319_288 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_225 STG SYSCONSAIF SYSCFG 900 0x384 0x20 0x00000000 u1_pcie_test_out_351_320 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_226 STG SYSCONSAIF SYSCFG 904 0x388 0x20 0x00000000 u1_pcie_test_out_383_352 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_227 STG SYSCONSAIF SYSCFG 908 0x38C 0x20 0x00000000 u1_pcie_test_out_415_384 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_228 STG SYSCONSAIF SYSCFG 912 0x390 0x20 0x00000000 u1_pcie_test_out_447_416 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_229 STG SYSCONSAIF SYSCFG 916 0x394 0x20 0x00000000 u1_pcie_test_out_479_448 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_230 STG SYSCONSAIF SYSCFG 920 0x398 0x20 0x00000000 u1_pcie_test_out_511_480 PCIE Test OUT (little-endian) [31:0] read-only stg_syscfg_231 STG SYSCONSAIF SYSCFG 924 0x39C 0x20 0x00000C80 u1_pcie_test_sel PCIE Test Selector [3:0] read-write 0 15 u1_pcie_tl_clock_freq PCIE TL Clock Frequency [25:4] read-write 0 4194303 stg_syscfg_232 STG SYSCONSAIF SYSCFG 928 0x3A0 0x20 0x00000000 u1_pcie_tl_ctrl_hotplug PCIE TL Control Hotplug [15:0] read-only u1_pcie_tl_report_hotplug PCIE TL Report Hotplug [31:16] read-write 0 65535 stg_syscfg_233 STG SYSCONSAIF SYSCFG 932 0x3A4 0x20 0x00000008 u1_pcie_tx_pattern PCIE TX Pattern [1:0] read-write 0 3 u1_pcie_usb3_bus_width PCIE USB3 Bus Width [3:2] read-write 0 3 u1_pcie_usb3_phy_enable PCIE USB3 PHY Enable [4:4] read-write u1_pcie_usb3_rate PCIE USB3 Rate [6:5] read-write 0 3 u1_pcie_usb3_rx_standby PCIE USB3 RX Standby [7:7] read-write u1_pcie_xwdecerr PCIE XWDECERR [8:8] read-only u1_pcie_xwerrclr PCIE XWERRCLR [9:9] read-write u1_pcie_xwslverr PCIE XWSLVERR [10:10] read-only uart3 Synopsys DesignWare APB UART: uart3 0x12000000 0x0 0x10000 registers UART3 45 rbr Receive Buffer Register 0x0 0x20 0x00000000 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 0x20 0x00000000 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 dll Divisor Latch Low 0x0 0x20 0x00000000 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 dlh Divisor Latch High 0x4 0x20 0x00000000 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 ier Interrupt Enable Register 0x4 0x20 0x00000000 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write true disable Programmable THRE Interrupt Mode disabled 0 enable Programmable THRE Interrupt Mode enabled 1 edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write true disable Modem Status Interrupt disabled 0 enable Modem Status Interrupt enabled 1 elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write true disable Enable Receiver Line Status Interrupt disabled 0 enable Enable Receiver Line Status Interrupt enabled 1 etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write true disable Enable Transmit Holding Register Empty Interrupt disabled 0 enable Enable Transmit Holding Register Empty Interrupt enabled 1 erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write true disable Enable Received Data Available Interrupt disabled 0 enable Enable Received Data Available Interrupt enabled 1 iir Interrupt Identity Register 0x8 0x20 0x00000001 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only true disabled FIFOs are disabled 0 enabled FIFOs are enabled 3 iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only true modem_status Modem status interrupt pending 0 none_pending No interrupt pending 1 thr_empty THR empty 2 data_available Received data available 4 receiver_line_status Receiver line status 6 busy_detect Busy detect 7 character_timeout Character timeout 12 fcr FIFO Control Register 0x8 0x20 0x00000000 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only true near_empty Trigger when 1 character in the FIFO 0 quarter Trigger when FIFO is 1/4 full 1 half Trigger when FIFO is 1/2 full 2 near_full Trigger when FIFO is 2 bytes less than full 3 tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only true empty Trigger FIFO when empty 0 near_empty Trigger when 2 characters in the FIFO 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only true mode0 Mode 0 0 mode1 Mode 1 1 xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xC 0x20 0x00000000 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write true bit1 1 stop bit 0 bit2 1.5 stop bits when LCR is zero, else 2 stop bits 1 dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write true five Data length 5-bits 0 six Data length 6-bits 1 seven Data length 7-bits 2 eight Data length 8-bits 3 mcr Modem Control Register 0x10 0x20 0x00000000 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 0x20 0x00000000 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Modem Status Register 0x18 0x20 0x00000000 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1C 0x20 0x00000000 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write 0 255 lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 0x20 0x00000000 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 0x20 0x00000000 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write 0 255 16 0x4 shadow[%s] This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). 0x30 0x20 0x00000000 srbr Shadow Receive Buffer Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr Shadow Threshold Register: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 far FIFO Access Register 0x70 0x20 0x00000000 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 0x20 0x00000000 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 0x20 0x00000000 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only 0 255 usr UART Status Register 0x7C 0x20 0x00000000 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 0x20 0x00000000 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 0x20 0x00000000 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 0x20 0x00000000 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8C 0x20 0x00000000 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 0x20 0x00000000 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 0x20 0x00000000 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 0x20 0x00000000 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9C 0x20 0x00000000 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write true near_empty Trigger when the FIFO has 1 character left 0 quarter Trigger when the FIFO is 1/4 full 1 half Trigger when the FIFO is 1/2 full 2 near_full Trigger when the FIFO is 2 bytes less than full 3 stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xA0 0x20 0x00000000 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write true empty Trigger when FIFO is empty 0 near_empty Trigger when FIFO has two characters 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 htx Halt TX 0xA4 0x20 0x00000000 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xA8 0x20 0x00000000 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xF4 0x20 0x00000000 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only true bits0 0-bit FIFO mode 0 bits16 16-bit FIFO mode 1 bits32 32-bit FIFO mode 2 bits2048 2048-bit FIFO mode 128 dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only true bits8 8-bit data width 0 bits16 16-bit data width 1 bits32 32-bit data width 2 ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x00000000 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x44570110 ctr This register contains the peripherals identification code. [31:0] read-only uart4 Synopsys DesignWare APB UART: uart4 0x12010000 0x0 0x10000 registers UART4 46 rbr Receive Buffer Register 0x0 0x20 0x00000000 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 0x20 0x00000000 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 dll Divisor Latch Low 0x0 0x20 0x00000000 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 dlh Divisor Latch High 0x4 0x20 0x00000000 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 ier Interrupt Enable Register 0x4 0x20 0x00000000 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write true disable Programmable THRE Interrupt Mode disabled 0 enable Programmable THRE Interrupt Mode enabled 1 edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write true disable Modem Status Interrupt disabled 0 enable Modem Status Interrupt enabled 1 elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write true disable Enable Receiver Line Status Interrupt disabled 0 enable Enable Receiver Line Status Interrupt enabled 1 etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write true disable Enable Transmit Holding Register Empty Interrupt disabled 0 enable Enable Transmit Holding Register Empty Interrupt enabled 1 erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write true disable Enable Received Data Available Interrupt disabled 0 enable Enable Received Data Available Interrupt enabled 1 iir Interrupt Identity Register 0x8 0x20 0x00000001 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only true disabled FIFOs are disabled 0 enabled FIFOs are enabled 3 iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only true modem_status Modem status interrupt pending 0 none_pending No interrupt pending 1 thr_empty THR empty 2 data_available Received data available 4 receiver_line_status Receiver line status 6 busy_detect Busy detect 7 character_timeout Character timeout 12 fcr FIFO Control Register 0x8 0x20 0x00000000 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only true near_empty Trigger when 1 character in the FIFO 0 quarter Trigger when FIFO is 1/4 full 1 half Trigger when FIFO is 1/2 full 2 near_full Trigger when FIFO is 2 bytes less than full 3 tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only true empty Trigger FIFO when empty 0 near_empty Trigger when 2 characters in the FIFO 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only true mode0 Mode 0 0 mode1 Mode 1 1 xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xC 0x20 0x00000000 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write true bit1 1 stop bit 0 bit2 1.5 stop bits when LCR is zero, else 2 stop bits 1 dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write true five Data length 5-bits 0 six Data length 6-bits 1 seven Data length 7-bits 2 eight Data length 8-bits 3 mcr Modem Control Register 0x10 0x20 0x00000000 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 0x20 0x00000000 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Modem Status Register 0x18 0x20 0x00000000 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1C 0x20 0x00000000 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write 0 255 lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 0x20 0x00000000 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 0x20 0x00000000 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write 0 255 16 0x4 shadow[%s] This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). 0x30 0x20 0x00000000 srbr Shadow Receive Buffer Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr Shadow Threshold Register: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 far FIFO Access Register 0x70 0x20 0x00000000 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 0x20 0x00000000 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 0x20 0x00000000 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only 0 255 usr UART Status Register 0x7C 0x20 0x00000000 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 0x20 0x00000000 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 0x20 0x00000000 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 0x20 0x00000000 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8C 0x20 0x00000000 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 0x20 0x00000000 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 0x20 0x00000000 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 0x20 0x00000000 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9C 0x20 0x00000000 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write true near_empty Trigger when the FIFO has 1 character left 0 quarter Trigger when the FIFO is 1/4 full 1 half Trigger when the FIFO is 1/2 full 2 near_full Trigger when the FIFO is 2 bytes less than full 3 stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xA0 0x20 0x00000000 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write true empty Trigger when FIFO is empty 0 near_empty Trigger when FIFO has two characters 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 htx Halt TX 0xA4 0x20 0x00000000 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xA8 0x20 0x00000000 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xF4 0x20 0x00000000 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only true bits0 0-bit FIFO mode 0 bits16 16-bit FIFO mode 1 bits32 32-bit FIFO mode 2 bits2048 2048-bit FIFO mode 128 dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only true bits8 8-bit data width 0 bits16 16-bit data width 1 bits32 32-bit data width 2 ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x00000000 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x44570110 ctr This register contains the peripherals identification code. [31:0] read-only uart5 Synopsys DesignWare APB UART: uart5 0x12020000 0x0 0x10000 registers UART5 47 rbr Receive Buffer Register 0x0 0x20 0x00000000 rbr Data byte received on the serial input port (sin) in UART mode, or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an over-run error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO is preserved, but any incoming data are lost and an over-run error occurs. [7:0] read-only thr Transmit Holding Register 0x0 0x20 0x00000000 thr Data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 dll Divisor Latch Low 0x0 0x20 0x00000000 dll Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 dlh Divisor Latch High 0x4 0x20 0x00000000 dlh Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0] is zero). The output baud rate is equal to the serial clock (pclk if one clock design, sclk if two clock design (CLOCK_MODE == Enabled)) frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications occur. Also, once the DLH is set, at least 8 clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 ier Interrupt Enable Register 0x4 0x20 0x00000000 ptime Programmable THRE Interrupt Mode Enable that can be written to only when THRE_MODE_USER == Enabled, always readable. This is used to enable/disable the generation of THRE Interrupt. 0 = disabled 1 = enabled [7:7] read-write true disable Programmable THRE Interrupt Mode disabled 0 enable Programmable THRE Interrupt Mode enabled 1 edssi Enable Modem Status Interrupt. This is used to enable/disable the generation of Modem Status Interrupt. This is the fourth highest priority interrupt. 0 = disabled 1 = enabled [3:3] read-write true disable Modem Status Interrupt disabled 0 enable Modem Status Interrupt enabled 1 elsi Enable Receiver Line Status Interrupt. This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt. 0 = disabled 1 = enabled [2:2] read-write true disable Enable Receiver Line Status Interrupt disabled 0 enable Enable Receiver Line Status Interrupt enabled 1 etbei Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt. 0 = disabled 1 = enabled [1:1] read-write true disable Enable Transmit Holding Register Empty Interrupt disabled 0 enable Enable Transmit Holding Register Empty Interrupt enabled 1 erbfi Enable Received Data Available Interrupt. This is used to enable/disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt (if in FIFO mode and FIFOs enabled). These are the second highest priority interrupts. 0 = disabled 1 = enabled [0:0] read-write true disable Enable Received Data Available Interrupt disabled 0 enable Enable Received Data Available Interrupt enabled 1 iir Interrupt Identity Register 0x8 0x20 0x00000001 fifose FIFOs Enabled. This is used to indicate whether the FIFOs are enabled or disabled. 00 = disabled 11 = enabled [7:6] read-only true disabled FIFOs are disabled 0 enabled FIFOs are enabled 3 iid Interrupt ID. This indicates the highest priority pending interrupt which can be one of the following types: 0000 = modem status 0001 = no interrupt pending 0010 = THR empty 0100 = received data available 0110 = receiver line status 0111 = busy detect 1100 = character timeout The interrupt priorities are split into four levels that are detailed in Table 8 on page 97. Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt. [3:0] read-only true modem_status Modem status interrupt pending 0 none_pending No interrupt pending 1 thr_empty THR empty 2 data_available Received data available 4 receiver_line_status Receiver line status 6 busy_detect Busy detect 7 character_timeout Character timeout 12 fcr FIFO Control Register 0x8 0x20 0x00000000 rt RCVR Trigger. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. In auto flow control mode it is used to determine when the rts_n signal is de-asserted. It also determines when the dma_rx_req_n signal is asserted in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [7:6] write-only true near_empty Trigger when 1 character in the FIFO 0 quarter Trigger when FIFO is 1/4 full 1 half Trigger when FIFO is 1/2 full 2 near_full Trigger when FIFO is 2 bytes less than full 3 tet TX Empty Trigger. Writes have no effect when THRE_MODE_USER == Disabled. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. It also determines when the dma_tx_req_n signal is asserted when in certain modes of operation. For details on DMA support, refer to “DMA Support” on page 58. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [5:4] write-only true empty Trigger FIFO when empty 0 near_empty Trigger when 2 characters in the FIFO 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 dmam DMA Mode. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == No). For details on DMA support, refer to “DMA Support” on page 58. 0 = mode 0 1 = mode 1 [3:3] write-only true mode0 Mode 0 0 mode1 Mode 1 1 xfifor XMIT FIFO Reset. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfifor RCVR FIFO Reset. This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only fifoe FIFO Enable. This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. [0:0] write-only lcr Line Control Register 0xC 0x20 0x00000000 dlab Divisor Latch Access Bit. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers. [7:7] read-write bc Break Control Bit.This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low. [6:6] read-write eps Even Parity Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic 1s is transmitted or checked. If set to zero, an odd number of logic 1s is transmitted or checked. [4:4] read-write pen Parity Enable. Writeable only when UART is not busy (USR[0] is zero), always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled [3:3] read-write stop Number of stop bits. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of stop bits per character that the peripheral transmits and receives. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected, the receiver checks only the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit [2:2] read-write true bit1 1 stop bit 0 bit2 1.5 stop bits when LCR is zero, else 2 stop bits 1 dls Data Length Select. Writeable only when UART is not busy (USR[0] is zero), always readable. This is used to select the number of data bits per character that the peripheral transmits and receives. The number of bit that may be selected areas follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits [1:0] read-write true five Data length 5-bits 0 six Data length 6-bits 1 seven Data length 7-bits 2 eight Data length 8-bits 3 mcr Modem Control Register 0x10 0x20 0x00000000 sire SIR Mode Enable. Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/disable the IrDA SIR Mode features as described in “IrDA 1.0 SIR Protocol” on page 47. 0 = IrDA SIR Mode disabled 1 = IrDA SIR Mode enabled [6:6] read-write afce Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are enabled as described in “Auto Flow Control” on page 51. 0 = Auto Flow Control Mode disabled 1 = Auto Flow Control Mode enabled [5:5] read-write lb LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled or not active, MCR[6] set to zero), data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped back to the inputs, internally. If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one), data on the sir_out_n line is held low, while serial data output is inverted and looped back to the sir_in line [4:4] read-write out2 OUT2. This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n, that is: 0 = out2_n de-asserted (logic 1) 1 = out2_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive high while the value of this location is internally looped back to an input. [3:3] read-write out1 OUT1. This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n, that is: 0 = out1_n de-asserted (logic 1) 1 = out1_n asserted (logic 0) Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high while the value of this location is internally looped back to an input. [2:2] read-write rts Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is set low by programming MCR[1] (RTS) to a high.In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFOs enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). The rts_n signal is de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive high while the value of this location is internally looped back to an input. [1:1] read-write dtr Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n, that is: 0 = dtr_n de-asserted (logic 1) 1 = dtr_n asserted (logic 0) The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that in Loopback mode (MCR[4] set to one), the dtr_n output is held inactive high while the value of this location is internally looped back to an input. [0:0] read-write lsr Line Status Register 0x14 0x20 0x00000000 rfe Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFOs are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error, framing error, or break indication in the FIFO. 0 = no error in RX FIFO 1 = error in RX FIFO This bit is cleared when the LSR is read and the character with the error is at the top of the receiver FIFO and there are no subsequent errors in the FIFO. [7:7] read-only temt Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFOs enabled (FCR[0] set to one), this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in non-FIFO mode or FIFOs are disabled, this bit is set whenever the Transmitter Holding Register and the Transmitter Shift Register are both empty. [6:6] read-only thre Transmit Holding Register Empty bit. If THRE_MODE_USER == Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not, this bit indicates that the THR or TX FIFO is empty. This bit is set whenever data is transferred from the THR or TX FIFO to the transmitter shift register and no new data has been written to the THR or TX FIFO. This also causes a THRE Interrupt to occur, if the THRE Interrupt is enabled. If THRE_MODE_USER == Enabled AND FIFO_MODE != NONE and both modes are active (IER[7] set to one and FCR[0] set to one respectively), the functionality is switched to indicate the transmitter FIFO is full, and no longer controls THRE interrupts, which are then controlled by the FCR[5:4] threshold setting. For more details, see “Programmable THRE Interrupt” on page 54. [5:5] read-only bi Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode (SIR_MODE == Disabled), it is set whenever the serial input, sin, is held in a logic '0' state for longer than the sum of start time + data bits + parity + stop bits. If in infrared mode (SIR_MODE == Enabled), it is set whenever the serial input, sir_in, is continuously pulsed to logic '0' for longer than the sum of start time + data bits + parity + stop bits. A break condition on serial input causes one and only one character, consisting of all zeros, to be received by the UART. In the FIFO mode, the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO. Reading the LSR clears the BI bit. In the non-FIFO mode, the BI indication occurs immediately and persists until the LSR is read. [4:4] read-only fe Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode, since the framing error is associated with a character received, it is revealed when the character with the framing error is at the top of the FIFO. When a framing error occurs, the UART tries to resynchronize. It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i.e. data, and/or parity and stop. It should be noted that the Framing Error (FE) bit (LSR[3]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no framing error 1 = framing error Reading the LSR clears the FE bit. [3:3] read-only pe Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode, since the parity error is associated with a character received, it is revealed when the character with the parity error arrives at the top of the FIFO. It should be noted that the Parity Error (PE) bit (LSR[2]) is set if a break interrupt has occurred, as indicated by Break Interrupt (BI) bit (LSR[4]). 0 = no parity error 1 = parity error Reading the LSR clears the PE bit. [2:2] read-only oe Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode, the OE bit is set when a new character arrives in the receiver before the previous character was read from the RBR. When this happens, the data in the RBR is overwritten. In the FIFO mode, an overrun error occurs when the FIFO is full and a new character arrives at the receiver. The data in the FIFO is retained and the data in the receive shift register is lost. 0 = no overrun error 1 = overrun error Reading the LSR clears the OE bit. [1:1] read-only dr Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. 0 = no data ready 1 = data ready This bit is cleared when the RBR is read in non-FIFO mode, or when the receiver FIFO is empty, in FIFO mode. [0:0] read-only msr Modem Status Register 0x18 0x20 0x00000000 dcd Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. This bit is the complement of dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). [7:7] read-only ri Ring Indicator. This is used to indicate the current state of the modem control line ri_n. This bit is the complement of ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). [6:6] read-only dsr Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. This bit is the complement of dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). [5:5] read-only cts Clear to Send. This is used to indicate the current state of the modem control line cts_n. This bit is the complement of cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1] (RTS) [4:4] read-only ddcd Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit is set when the reset is removed if the dcd_n signal remains asserted. [3:3] read-only teri Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active-low to an inactive-high state) has occurred since the last time the MSR was read. 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] = 1), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. [2:2] read-only ddsr Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted. [1:1] read-only dcts Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. 0 = no change on ctsdsr_n since last read of MSR 1 = change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n signal remains asserted. [0:0] read-only scr Scratch Pad Register 0x1C 0x20 0x00000000 scr This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. [7:0] read-write 0 255 lpdll Low Power Divisor Latch Low Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x20 0x20 0x00000000 lpdll This register makes up the lower 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLL is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data. [7:0] read-write 0 255 lpdlh Low Power Divisor Latch High Register: This register is only valid when the DW_apb_uart is configured to have SIR low-power reception capabilities implemented (SIR_LP_RX = Yes). If SIR low-power reception capabilities are not implemented, this register does not exist and reading from thsi register address returns zero. 0x24 0x20 0x00000000 lpdlh This register makes up the upper 8-bits of a 16-bit, read/write, Low Power Divisor Latch register that contains the baud rate divisor for the UART, which must give a baud rate of 115.2K. This is required for SIR Low Power (minimum pulse width) detection at the receiver. This register may only be accessed when the DLAB bit (LCR[7]) is set and the UART is not busy (USR[0]) is 0). The output low-power baud rate is equal to the serial clock (sclk) frequency divided by sixteen times the value of the baud rate divisor, as follows: Low power baud rate = (serial clock frequency)/(16* divisor) Therefore, a divisor must be selected to give a baud rate of 115.2K. NOTE: When the Low Power Divisor Latch registers (LPDLL and LPDLH) are set to 0, the low-power baud clock is disabled and no low-power pulse detection (or any pulse detection) occurs at the receiver. Also, once the LPDLH is set, at least eight clock cycles of the slowest DW_apb_uart clock should be allowed to pass before transmitting or receiving data [7:0] read-write 0 255 16 0x4 shadow[%s] This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). 0x30 0x20 0x00000000 srbr Shadow Receive Buffer Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero.This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs. [7:0] read-only sthr Shadow Threshold Register: This is a shadow register for the THR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost. [7:0] write-only 0 255 far FIFO Access Register 0x70 0x20 0x00000000 far Writes have no effect when FIFO_ACCESS == No, always readable. This register is use to enable a FIFO access mode for testing, so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFOs are implemented and enabled. When FIFOs are not implemented or not enabled it allows the RBR to be written by the master and the THR to be read by the master. 0 = FIFO access mode disabled 1 = FIFO access mode enabled Note, that when the FIFO access mode is enabled/disabled, the control portion of the receive FIFO and transmit FIFO is reset and the FIFOs are treated as empty. [0:0] read-write tfr Transmit FIFO Read 0x74 0x20 0x00000000 tfr Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFOs are not implemented or not enabled, reading this register gives the data in the THR. [7:0] read-only rfw Receive FIFO Write 0x78 0x20 0x00000000 rffe Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write framing error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write framing error detection information to the RBR. [9:9] write-only rfpe Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, this bit is used to write parity error detection information to the receive FIFO. When FIFOs are not implemented or not enabled, this bit is used to write parity error detection information to the RBR. [8:8] write-only rfwd Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFOs are implemented and enabled, the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes the new data to the next write location in the receive FIFO. When FIFOs are not implemented or not enabled, the data that is written to the RFWD is pushed into the RBR. [7:0] write-only 0 255 usr UART Status Register 0x7C 0x20 0x00000000 rff Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. 0 = Receive FIFO not full 1 = Receive FIFO Full This bit is cleared when the RX FIFO is no longer full. [4:4] read-only rfne Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty This bit is cleared when the RX FIFO is empty. [3:3] read-only tfe Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. 0 = Transmit FIFO is not empty 1 = Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer empty. [2:2] read-only tfnf Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full This bit is cleared when the TX FIFO is full. [1:1] read-only busy UART Busy. This is indicates that a serial transfer is in progress, when cleared indicates that the DW_apb_uart is idle or inactive. 0 = DW_apb_uart is idle or inactive 1 = DW_apb_uart is busy (actively transferring data) NOTE: It is possible for the UART Busy bit to be cleared even though a new character may have been sent from another device. That is, if the DW_apb_uart has no data in THR and RBR and there is no transmission in progress and a start bit of a new character has just reached the DW_apb_uart. This is due to the fact that a valid start is not seen until the middle of the bit period and this duration is dependent on the baud divisor that has been programmed. If a second system clock has been implemented (CLOCK_MODE == Enabled), the assertion of this bit is also delayed by several cycles of the slower clock. [0:0] read-only tfl Transmit FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x80 0x20 0x00000000 tfl Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. [31:0] read-only rfl Receive FIFO Level: This register is only valid when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT == YES). If status registers are not implemented, this register does not exist and reading from this register address returns zero. 0x84 0x20 0x00000000 rfl Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. [31:0] read-only srr Software Reset Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x88 0x20 0x00000000 xfr XMIT FIFO Reset. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This also de-asserts the DMA TX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [2:2] write-only rfr RCVR FIFO Reset. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO This resets the control portion of the receive FIFO and treats the FIFO as empty. This also de-asserts the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [1:1] write-only ur UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains are reset. [0:0] write-only srts Shadow Request to Send: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x8C 0x20 0x00000000 srts Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the burden of having to performing a read-modify-write on the MCR. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the DW_apb_uart is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] = 0), the rts_n signal is set low by programming MCR[1] (RTS) to a high. In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] = 1) and FIFOs enable (FCR[0] = 1), the rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high when above the threshold). Note that in Loopback mode (MCR[4] = 1), the rts_n output is held inactive-high while the value of this location is internally looped back to an input. [0:0] read-write sbcr Shadow Break Control Register: This register is only valid when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW == YES). If shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0x90 0x20 0x00000000 sbcr Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]), this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] = 1) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver. [0:0] read-write sdmam Shadow DMA Mode: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x94 0x20 0x00000000 sdmam Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets updated. This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals when additional DMA handshaking signals are not selected (DMA_EXTRA == NO). 0 = mode 0 1 = mode 1 [0:0] read-write sfe Shadow FIFO Enable: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x98 0x20 0x00000000 sfe Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit gets updated.This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. If this bit is set to zero (disabled) after being enabled then both the XMIT and RCVR controller portion of FIFOs are reset. [0:0] read-write srt Shadow RCVR Trigger: This register is only valid when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW == YES). If these registers are not implemented, this register does not exist and reading from this register address returns zero. 0x9C 0x20 0x00000000 srt Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR trigger bit gets updated. This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated. It also determines when the dma_rx_req_n signal is asserted when DMA Mode (FCR[3]) = 1. The following trigger levels are supported: 00 = 1 character in the FIFO 01 = FIFO ¼ full 10 = FIFO ½ full 11 = FIFO 2 less than full [1:0] read-write true near_empty Trigger when the FIFO has 1 character left 0 quarter Trigger when the FIFO is 1/4 full 1 half Trigger when the FIFO is 1/2 full 2 near_full Trigger when the FIFO is 2 bytes less than full 3 stet Shadow TX Empty Trigger: This register is only valid when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER == Enabled) and additional shadow registers implemented (SHADOW == YES). If FIFOs are not implemented or THRE interrupt support is not implemented or shadow registers are not implemented, this register does not exist and reading from this register address returns zero. 0xA0 0x20 0x00000000 stet Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX empty trigger bit gets updated. This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active. The following trigger levels are supported: 00 = FIFO empty 01 = 2 characters in the FIFO 10 = FIFO ¼ full 11 = FIFO ½ full [1:0] read-write true empty Trigger when FIFO is empty 0 near_empty Trigger when FIFO has two characters 1 quarter Trigger when FIFO is 1/4 full 2 half Trigger when FIFO is 1/2 full 3 htx Halt TX 0xA4 0x20 0x00000000 htx This register is use to halt transmissions for testing, so that the transmit FIFO can be filled by the master when FIFOs are implemented and enabled. 0 = Halt TX disabled 1 = Halt TX enabled Note, if FIFOs are implemented and not enabled, the setting of the halt TX register has no effect on operation. [0:0] read-write dmasa DMA Software Acknowledge 0xA8 0x20 0x00000000 dmasa This register is use to perform a DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the DW_apb_uart should clear its request. This causes the TX request, TX single, RX request and RX single signals to de-assert. Note that this bit is 'self-clearing'. It is not necessary to clear this bit. [0:0] write-only cpr Component Parameter Register: This register is only valid when the DW_apb_uart is configured to have the Component Parameter register implemented (UART_ADD_ENCODED_PARAMS == YES). If the Component Parameter register is not implemented, this register does not exist and reading from this register address returns zero. 0xF4 0x20 0x00000000 fifo_mode 0x00 = 0 0x01 = 16 0x02 = 32 to 0x80 = 2048 0x81 - 0xff = reserved [23:16] read-only true bits0 0-bit FIFO mode 0 bits16 16-bit FIFO mode 1 bits32 32-bit FIFO mode 2 bits2048 2048-bit FIFO mode 128 dma_extra 0 = false 1 = true [13:13] read-only uart_add_encoded_params 0 = false 1 = true [12:12] read-only shadow 0 = false 1 = true [11:11] read-only fifo_stat 0 = false 1 = true [10:10] read-only fifo_access 0 = false 1 = true [9:9] read-only additional_feat 0 = false 1 = true [8:8] read-only sir_lp_mode 0 = false 1 = true [7:7] read-only sir_mode 0 = false 1 = true [6:6] read-only thre_mode 0 = false 1 = true [5:5] read-only afce_mode 0 = false 1 = true [4:4] read-only apb_data_width 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved [1:0] read-only true bits8 8-bit data width 0 bits16 16-bit data width 1 bits32 32-bit data width 2 ucv UART Component Version: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x00000000 ucv ASCII value for each number in the version, followed by *. For example 32_30_31_2A represents the version 2.01* [31:0] read-only ctr Component Type Register: This register is only valid when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES == YES). If additional features are not implemented, this register does not exist and reading from this register address returns zero. 0xF8 0x20 0x44570110 ctr This register contains the peripherals identification code. [31:0] read-only i2c3 Synopsys DesignWare APB I2C: i2c3 0x12030000 0x0 0x10000 registers I2C3 48 i2c_con DesignWare I2C CON 0x0 0x20 0x00000002 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write true slave I2C slave connection 0 master I2C master connection 1 speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write true standard Standard speed 1 fast Fast speed 2 high High speed 3 slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write true clear Do not enable restart 0 set Enable restart 1 slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write true clear Do not disable 0 set Disable 1 stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write true clear Do not stop DET if addressed 0 set Stop DET if addressed 1 tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write true clear Do not empty TX 0 set Empty TX 1 rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write true clear RX FIFO does not use full HID control 0 set RX FIFO uses full HID control 1 bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write true clear Do not clear the bus 0 set Clear the bus 1 tar DesignWare I2C TAR 0x4 0x20 0x00000000 address_7bit Target address, 7-bit mode [6:0] read-write 0 127 address_10bit Target address, 10-bit mode [9:0] read-write 0 1023 mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write true seven_bit 7-bit address mode 0 ten_bit 10-bit address mode 1 sar DesignWare I2C SAR 0x8 0x20 0x00000000 address_7bit Slave address, 7-bit mode [6:0] read-write 0 127 address_10bit Slave address, 10-bit mode [9:0] read-write 0 1023 data_cmd DesignWare I2C Data Command 0x10 0x20 0x00000000 dat Data Command Data Byte [7:0] read-write 0 255 read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 0x20 0x00000000 ss_scl_hcnt [15:0] read-write 0 65535 ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 0x20 0x00000000 ss_scl_lcnt [15:0] read-write 0 65535 fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1C 0x20 0x00000000 fs_scl_hcnt [15:0] read-write 0 65535 fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 0x20 0x00000000 fs_scl_lcnt [15:0] read-write 0 65535 hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 0x20 0x00000000 hs_scl_hcnt [15:0] read-write 0 65535 hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 0x20 0x00000000 hs_scl_lcnt [15:0] read-write 0 65535 intr_stat DesignWare I2C Interrupt Status 0x2C 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 0x20 0x00000000 rx_tl [7:0] read-write 0 255 tx_tl DesignWare I2C TX TL 0x3C 0x20 0x00000000 tx_tl [7:0] read-write 0 255 clr_intr DesignWare I2C Clear Interrrupt 0x40 0x20 0x00000000 clr_intr [0:0] read-only clr_rx_under DesignWare I2C Clear RX Underrun 0x44 0x20 0x00000000 clr_rx_under [0:0] read-only clr_rx_over DesignWare I2C Clear RX Overrun 0x48 0x20 0x00000000 clr_rx_over [0:0] read-only clr_tx_over DesignWare I2C Clear TX Overrun 0x4C 0x20 0x00000000 clr_tx_over [0:0] read-only clr_rd_req DesignWare I2C Clear Read Request 0x50 0x20 0x00000000 clr_rd_req [0:0] read-only clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 0x20 0x00000000 clr_tx_abrt [0:0] read-only clr_rx_done DesignWare I2C Clear RX Done 0x58 0x20 0x00000000 clr_rx_done [0:0] read-only clr_activity DesignWare I2C Clear Activity 0x5C 0x20 0x00000000 clr_activity [0:0] read-only clr_stop_det DesignWare I2C Clear Stop DET 0x60 0x20 0x00000000 clr_stop_det [0:0] read-only clr_start_det DesignWare I2C Clear Start DET 0x64 0x20 0x00000000 clr_start_det [0:0] read-only clr_gen_call DesignWare I2C Clear General Call 0x68 0x20 0x00000000 clr_gen_call [0:0] read-only enable DesignWare I2C Enable 0x6C 0x20 0x00000000 abort [1:1] read-write status DesignWare I2C Status 0x70 0x20 0x00000000 activity [0:0] read-only tfe [2:2] read-only rfne [3:3] read-only master_activity [5:5] read-only slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 0x20 0x00000000 txflr [31:0] read-only rxflr DesignWare I2C RX Failure 0x78 0x20 0x00000000 rxflr [31:0] read-only sda_hold DesignWare I2C SDA Hold 0x7C 0x20 0x00000000 sda_hold [23:0] read-write 0 16777215 tx_abrt_source DesignWare I2C TX Abort Source 0x80 0x20 0x00000000 b7_addr_noack [0:0] read-only b10_addr1_noack [1:1] read-only b10_addr2_noack [2:2] read-only txdata_noack [3:3] read-only gcall_noack [4:4] read-only gcall_read [5:5] read-only sbyte_ackdet [7:7] read-only sbyte_norstrt [9:9] read-only b10_rd_norstrt [10:10] read-only master_dis [11:11] read-only arb_lost [12:12] read-only slave_flush_txfifo [13:13] read-only slave_arblost [14:14] read-only slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9C 0x20 0x00000000 activity [0:0] read-write tfe [2:2] read-write rfne [3:3] read-write master_activity [5:5] read-write slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xA8 0x20 0x00000000 clr_restart_det [0:0] read-only comp_param_1 DesignWare I2C Compatibility Parameter 1 0xF4 0x20 0x00000000 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only true standard Standard speed 1 full Full speed 2 high High speed 3 comp_version DesignWare I2C Compatibility Version 0xF8 0x20 0x00000000 comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xFC 0x20 0x44570140 comp_type [31:0] read-only i2c4 Synopsys DesignWare APB I2C: i2c4 0x12040000 0x0 0x10000 registers I2C4 49 i2c_con DesignWare I2C CON 0x0 0x20 0x00000002 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write true slave I2C slave connection 0 master I2C master connection 1 speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write true standard Standard speed 1 fast Fast speed 2 high High speed 3 slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write true clear Do not enable restart 0 set Enable restart 1 slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write true clear Do not disable 0 set Disable 1 stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write true clear Do not stop DET if addressed 0 set Stop DET if addressed 1 tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write true clear Do not empty TX 0 set Empty TX 1 rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write true clear RX FIFO does not use full HID control 0 set RX FIFO uses full HID control 1 bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write true clear Do not clear the bus 0 set Clear the bus 1 tar DesignWare I2C TAR 0x4 0x20 0x00000000 address_7bit Target address, 7-bit mode [6:0] read-write 0 127 address_10bit Target address, 10-bit mode [9:0] read-write 0 1023 mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write true seven_bit 7-bit address mode 0 ten_bit 10-bit address mode 1 sar DesignWare I2C SAR 0x8 0x20 0x00000000 address_7bit Slave address, 7-bit mode [6:0] read-write 0 127 address_10bit Slave address, 10-bit mode [9:0] read-write 0 1023 data_cmd DesignWare I2C Data Command 0x10 0x20 0x00000000 dat Data Command Data Byte [7:0] read-write 0 255 read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 0x20 0x00000000 ss_scl_hcnt [15:0] read-write 0 65535 ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 0x20 0x00000000 ss_scl_lcnt [15:0] read-write 0 65535 fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1C 0x20 0x00000000 fs_scl_hcnt [15:0] read-write 0 65535 fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 0x20 0x00000000 fs_scl_lcnt [15:0] read-write 0 65535 hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 0x20 0x00000000 hs_scl_hcnt [15:0] read-write 0 65535 hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 0x20 0x00000000 hs_scl_lcnt [15:0] read-write 0 65535 intr_stat DesignWare I2C Interrupt Status 0x2C 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 0x20 0x00000000 rx_tl [7:0] read-write 0 255 tx_tl DesignWare I2C TX TL 0x3C 0x20 0x00000000 tx_tl [7:0] read-write 0 255 clr_intr DesignWare I2C Clear Interrrupt 0x40 0x20 0x00000000 clr_intr [0:0] read-only clr_rx_under DesignWare I2C Clear RX Underrun 0x44 0x20 0x00000000 clr_rx_under [0:0] read-only clr_rx_over DesignWare I2C Clear RX Overrun 0x48 0x20 0x00000000 clr_rx_over [0:0] read-only clr_tx_over DesignWare I2C Clear TX Overrun 0x4C 0x20 0x00000000 clr_tx_over [0:0] read-only clr_rd_req DesignWare I2C Clear Read Request 0x50 0x20 0x00000000 clr_rd_req [0:0] read-only clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 0x20 0x00000000 clr_tx_abrt [0:0] read-only clr_rx_done DesignWare I2C Clear RX Done 0x58 0x20 0x00000000 clr_rx_done [0:0] read-only clr_activity DesignWare I2C Clear Activity 0x5C 0x20 0x00000000 clr_activity [0:0] read-only clr_stop_det DesignWare I2C Clear Stop DET 0x60 0x20 0x00000000 clr_stop_det [0:0] read-only clr_start_det DesignWare I2C Clear Start DET 0x64 0x20 0x00000000 clr_start_det [0:0] read-only clr_gen_call DesignWare I2C Clear General Call 0x68 0x20 0x00000000 clr_gen_call [0:0] read-only enable DesignWare I2C Enable 0x6C 0x20 0x00000000 abort [1:1] read-write status DesignWare I2C Status 0x70 0x20 0x00000000 activity [0:0] read-only tfe [2:2] read-only rfne [3:3] read-only master_activity [5:5] read-only slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 0x20 0x00000000 txflr [31:0] read-only rxflr DesignWare I2C RX Failure 0x78 0x20 0x00000000 rxflr [31:0] read-only sda_hold DesignWare I2C SDA Hold 0x7C 0x20 0x00000000 sda_hold [23:0] read-write 0 16777215 tx_abrt_source DesignWare I2C TX Abort Source 0x80 0x20 0x00000000 b7_addr_noack [0:0] read-only b10_addr1_noack [1:1] read-only b10_addr2_noack [2:2] read-only txdata_noack [3:3] read-only gcall_noack [4:4] read-only gcall_read [5:5] read-only sbyte_ackdet [7:7] read-only sbyte_norstrt [9:9] read-only b10_rd_norstrt [10:10] read-only master_dis [11:11] read-only arb_lost [12:12] read-only slave_flush_txfifo [13:13] read-only slave_arblost [14:14] read-only slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9C 0x20 0x00000000 activity [0:0] read-write tfe [2:2] read-write rfne [3:3] read-write master_activity [5:5] read-write slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xA8 0x20 0x00000000 clr_restart_det [0:0] read-only comp_param_1 DesignWare I2C Compatibility Parameter 1 0xF4 0x20 0x00000000 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only true standard Standard speed 1 full Full speed 2 high High speed 3 comp_version DesignWare I2C Compatibility Version 0xF8 0x20 0x00000000 comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xFC 0x20 0x44570140 comp_type [31:0] read-only i2c5 Synopsys DesignWare APB I2C: i2c5 0x12050000 0x0 0x10000 registers I2C5 50 i2c_con DesignWare I2C CON 0x0 0x20 0x00000002 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write true slave I2C slave connection 0 master I2C master connection 1 speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write true standard Standard speed 1 fast Fast speed 2 high High speed 3 slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write true clear Do not enable restart 0 set Enable restart 1 slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write true clear Do not disable 0 set Disable 1 stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write true clear Do not stop DET if addressed 0 set Stop DET if addressed 1 tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write true clear Do not empty TX 0 set Empty TX 1 rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write true clear RX FIFO does not use full HID control 0 set RX FIFO uses full HID control 1 bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write true clear Do not clear the bus 0 set Clear the bus 1 tar DesignWare I2C TAR 0x4 0x20 0x00000000 address_7bit Target address, 7-bit mode [6:0] read-write 0 127 address_10bit Target address, 10-bit mode [9:0] read-write 0 1023 mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write true seven_bit 7-bit address mode 0 ten_bit 10-bit address mode 1 sar DesignWare I2C SAR 0x8 0x20 0x00000000 address_7bit Slave address, 7-bit mode [6:0] read-write 0 127 address_10bit Slave address, 10-bit mode [9:0] read-write 0 1023 data_cmd DesignWare I2C Data Command 0x10 0x20 0x00000000 dat Data Command Data Byte [7:0] read-write 0 255 read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 0x20 0x00000000 ss_scl_hcnt [15:0] read-write 0 65535 ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 0x20 0x00000000 ss_scl_lcnt [15:0] read-write 0 65535 fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1C 0x20 0x00000000 fs_scl_hcnt [15:0] read-write 0 65535 fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 0x20 0x00000000 fs_scl_lcnt [15:0] read-write 0 65535 hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 0x20 0x00000000 hs_scl_hcnt [15:0] read-write 0 65535 hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 0x20 0x00000000 hs_scl_lcnt [15:0] read-write 0 65535 intr_stat DesignWare I2C Interrupt Status 0x2C 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 0x20 0x00000000 rx_tl [7:0] read-write 0 255 tx_tl DesignWare I2C TX TL 0x3C 0x20 0x00000000 tx_tl [7:0] read-write 0 255 clr_intr DesignWare I2C Clear Interrrupt 0x40 0x20 0x00000000 clr_intr [0:0] read-only clr_rx_under DesignWare I2C Clear RX Underrun 0x44 0x20 0x00000000 clr_rx_under [0:0] read-only clr_rx_over DesignWare I2C Clear RX Overrun 0x48 0x20 0x00000000 clr_rx_over [0:0] read-only clr_tx_over DesignWare I2C Clear TX Overrun 0x4C 0x20 0x00000000 clr_tx_over [0:0] read-only clr_rd_req DesignWare I2C Clear Read Request 0x50 0x20 0x00000000 clr_rd_req [0:0] read-only clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 0x20 0x00000000 clr_tx_abrt [0:0] read-only clr_rx_done DesignWare I2C Clear RX Done 0x58 0x20 0x00000000 clr_rx_done [0:0] read-only clr_activity DesignWare I2C Clear Activity 0x5C 0x20 0x00000000 clr_activity [0:0] read-only clr_stop_det DesignWare I2C Clear Stop DET 0x60 0x20 0x00000000 clr_stop_det [0:0] read-only clr_start_det DesignWare I2C Clear Start DET 0x64 0x20 0x00000000 clr_start_det [0:0] read-only clr_gen_call DesignWare I2C Clear General Call 0x68 0x20 0x00000000 clr_gen_call [0:0] read-only enable DesignWare I2C Enable 0x6C 0x20 0x00000000 abort [1:1] read-write status DesignWare I2C Status 0x70 0x20 0x00000000 activity [0:0] read-only tfe [2:2] read-only rfne [3:3] read-only master_activity [5:5] read-only slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 0x20 0x00000000 txflr [31:0] read-only rxflr DesignWare I2C RX Failure 0x78 0x20 0x00000000 rxflr [31:0] read-only sda_hold DesignWare I2C SDA Hold 0x7C 0x20 0x00000000 sda_hold [23:0] read-write 0 16777215 tx_abrt_source DesignWare I2C TX Abort Source 0x80 0x20 0x00000000 b7_addr_noack [0:0] read-only b10_addr1_noack [1:1] read-only b10_addr2_noack [2:2] read-only txdata_noack [3:3] read-only gcall_noack [4:4] read-only gcall_read [5:5] read-only sbyte_ackdet [7:7] read-only sbyte_norstrt [9:9] read-only b10_rd_norstrt [10:10] read-only master_dis [11:11] read-only arb_lost [12:12] read-only slave_flush_txfifo [13:13] read-only slave_arblost [14:14] read-only slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9C 0x20 0x00000000 activity [0:0] read-write tfe [2:2] read-write rfne [3:3] read-write master_activity [5:5] read-write slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xA8 0x20 0x00000000 clr_restart_det [0:0] read-only comp_param_1 DesignWare I2C Compatibility Parameter 1 0xF4 0x20 0x00000000 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only true standard Standard speed 1 full Full speed 2 high High speed 3 comp_version DesignWare I2C Compatibility Version 0xF8 0x20 0x00000000 comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xFC 0x20 0x44570140 comp_type [31:0] read-only i2c6 Synopsys DesignWare APB I2C: i2c6 0x12060000 0x0 0x10000 registers I2C6 51 i2c_con DesignWare I2C CON 0x0 0x20 0x00000002 master I2C Master Connection - 0: Slave, 1: Master [0:0] read-write true slave I2C slave connection 0 master I2C master connection 1 speed I2C Speed - 01: Standard, 10: Fast, 11: High [2:1] read-write true standard Standard speed 1 fast Fast speed 2 high High speed 3 slave_10bitaddr I2C Slave 10-bit Address - 0: False, 1: True [3:3] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 master_10bitaddr I2C Master 10-bit Address - 0: False, 1: True [4:4] read-write true clear Does not use 10-bit addresses 0 set Uses 10-bit addresses 1 restart_en I2C Restart Enable - 0: False, 1: True [5:5] read-write true clear Do not enable restart 0 set Enable restart 1 slave_disable I2C Slave Disable - 0: False, 1: True [6:6] read-write true clear Do not disable 0 set Disable 1 stop_det_ifaddressed I2C Stop DET If Addressed - 0: False, 1: True [7:7] read-write true clear Do not stop DET if addressed 0 set Stop DET if addressed 1 tx_empty_ctrl I2C TX Empty Control - 0: False, 1: True [8:8] read-write true clear Do not empty TX 0 set Empty TX 1 rx_fifo_full_hld_ctrl I2C RX FIFO Full Hold Control - 0: False, 1: True [9:9] read-write true clear RX FIFO does not use full HID control 0 set RX FIFO uses full HID control 1 bus_clear_ctrl I2C Bus Clear Control - 0: False, 1: True [11:11] read-write true clear Do not clear the bus 0 set Clear the bus 1 tar DesignWare I2C TAR 0x4 0x20 0x00000000 address_7bit Target address, 7-bit mode [6:0] read-write 0 127 address_10bit Target address, 10-bit mode [9:0] read-write 0 1023 mode Target addressing mode - 0: 7-bit, 1: 10-bit [12:12] read-write true seven_bit 7-bit address mode 0 ten_bit 10-bit address mode 1 sar DesignWare I2C SAR 0x8 0x20 0x00000000 address_7bit Slave address, 7-bit mode [6:0] read-write 0 127 address_10bit Slave address, 10-bit mode [9:0] read-write 0 1023 data_cmd DesignWare I2C Data Command 0x10 0x20 0x00000000 dat Data Command Data Byte [7:0] read-write 0 255 read Data Command READ Bit - 0: Write, 1: Read [8:8] read-write stop Data Command STOP Bit - 0: Non-terminal DATA command byte, 1: Terminal DATA command byte [9:9] read-write restart Data Command RESTART Bit - 0: Do not restart the transfer, 1: Restart the transfer [10:10] read-write first_data_byte Data Command First Data Byte - 0: False, 1: True [11:11] read-write ss_scl_hcnt DesignWare I2C SS SCL HCNT 0x14 0x20 0x00000000 ss_scl_hcnt [15:0] read-write 0 65535 ss_scl_lcnt DesignWare I2C SS SCL LCNT 0x18 0x20 0x00000000 ss_scl_lcnt [15:0] read-write 0 65535 fs_scl_hcnt DesignWare I2C FS SCL HCNT 0x1C 0x20 0x00000000 fs_scl_hcnt [15:0] read-write 0 65535 fs_scl_lcnt DesignWare I2C FS SCL LCNT 0x20 0x20 0x00000000 fs_scl_lcnt [15:0] read-write 0 65535 hs_scl_hcnt DesignWare I2C HS SCL HCNT 0x24 0x20 0x00000000 hs_scl_hcnt [15:0] read-write 0 65535 hs_scl_lcnt DesignWare I2C HS SCL LCNT 0x28 0x20 0x00000000 hs_scl_lcnt [15:0] read-write 0 65535 intr_stat DesignWare I2C Interrupt Status 0x2C 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only intr_mask DesignWare I2C Interrupt Mask 0x30 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-write rx_over RX FIFO Overrun [1:1] read-write rx_full RX FIFO Full [2:2] read-write tx_over TX FIFO Overrun [3:3] read-write tx_empty TX FIFO Empty [4:4] read-write rd_req Read Request [5:5] read-write tx_abrt TX Abort [6:6] read-write rx_done RX Done [7:7] read-write activity Activity [8:8] read-write stop_det Stop DET [9:9] read-write start_det Start DET [10:10] read-write gen_call General Call [11:11] read-write restart_det Restart DET [12:12] read-write mst_on_hold Master on Hold [13:13] read-write raw_intr_stat DesignWare I2C Raw Interrupt Status 0x34 0x20 0x00000000 rx_under RX FIFO Underrun [0:0] read-only rx_over RX FIFO Overrun [1:1] read-only rx_full RX FIFO Full [2:2] read-only tx_over TX FIFO Overrun [3:3] read-only tx_empty TX FIFO Empty [4:4] read-only rd_req Read Request [5:5] read-only tx_abrt TX Abort [6:6] read-only rx_done RX Done [7:7] read-only activity Activity [8:8] read-only stop_det Stop DET [9:9] read-only start_det Start DET [10:10] read-only gen_call General Call [11:11] read-only restart_det Restart DET [12:12] read-only mst_on_hold Master on Hold [13:13] read-only rx_tl DesignWare I2C RX TL 0x38 0x20 0x00000000 rx_tl [7:0] read-write 0 255 tx_tl DesignWare I2C TX TL 0x3C 0x20 0x00000000 tx_tl [7:0] read-write 0 255 clr_intr DesignWare I2C Clear Interrrupt 0x40 0x20 0x00000000 clr_intr [0:0] read-only clr_rx_under DesignWare I2C Clear RX Underrun 0x44 0x20 0x00000000 clr_rx_under [0:0] read-only clr_rx_over DesignWare I2C Clear RX Overrun 0x48 0x20 0x00000000 clr_rx_over [0:0] read-only clr_tx_over DesignWare I2C Clear TX Overrun 0x4C 0x20 0x00000000 clr_tx_over [0:0] read-only clr_rd_req DesignWare I2C Clear Read Request 0x50 0x20 0x00000000 clr_rd_req [0:0] read-only clr_tx_abrt DesignWare I2C Clear TX Abort 0x54 0x20 0x00000000 clr_tx_abrt [0:0] read-only clr_rx_done DesignWare I2C Clear RX Done 0x58 0x20 0x00000000 clr_rx_done [0:0] read-only clr_activity DesignWare I2C Clear Activity 0x5C 0x20 0x00000000 clr_activity [0:0] read-only clr_stop_det DesignWare I2C Clear Stop DET 0x60 0x20 0x00000000 clr_stop_det [0:0] read-only clr_start_det DesignWare I2C Clear Start DET 0x64 0x20 0x00000000 clr_start_det [0:0] read-only clr_gen_call DesignWare I2C Clear General Call 0x68 0x20 0x00000000 clr_gen_call [0:0] read-only enable DesignWare I2C Enable 0x6C 0x20 0x00000000 abort [1:1] read-write status DesignWare I2C Status 0x70 0x20 0x00000000 activity [0:0] read-only tfe [2:2] read-only rfne [3:3] read-only master_activity [5:5] read-only slave_activity [6:6] read-only txflr DesignWare I2C TX Failure 0x74 0x20 0x00000000 txflr [31:0] read-only rxflr DesignWare I2C RX Failure 0x78 0x20 0x00000000 rxflr [31:0] read-only sda_hold DesignWare I2C SDA Hold 0x7C 0x20 0x00000000 sda_hold [23:0] read-write 0 16777215 tx_abrt_source DesignWare I2C TX Abort Source 0x80 0x20 0x00000000 b7_addr_noack [0:0] read-only b10_addr1_noack [1:1] read-only b10_addr2_noack [2:2] read-only txdata_noack [3:3] read-only gcall_noack [4:4] read-only gcall_read [5:5] read-only sbyte_ackdet [7:7] read-only sbyte_norstrt [9:9] read-only b10_rd_norstrt [10:10] read-only master_dis [11:11] read-only arb_lost [12:12] read-only slave_flush_txfifo [13:13] read-only slave_arblost [14:14] read-only slave_rd_intx [15:15] read-only enable_status DesignWare I2C Enable Status 0x9C 0x20 0x00000000 activity [0:0] read-write tfe [2:2] read-write rfne [3:3] read-write master_activity [5:5] read-write slave_activity [6:6] read-write clr_restart_det DesignWare I2C Clear Restart DET 0xA8 0x20 0x00000000 clr_restart_det [0:0] read-only comp_param_1 DesignWare I2C Compatibility Parameter 1 0xF4 0x20 0x00000000 speed Speed mask - 01: Standard, 10: Full, 11: High [3:2] read-only true standard Standard speed 1 full Full speed 2 high High speed 3 comp_version DesignWare I2C Compatibility Version 0xF8 0x20 0x00000000 comp_version [31:0] read-only comp_type DesignWare I2C Compatibility Type 0xFC 0x20 0x44570140 comp_type [31:0] read-only spi3 ARM pl022 SSP SPI: spi3 0x12070000 0x0 0x10000 registers SPI3 52 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 0x10 0x00000000 dss Data Size Select [3:0] read-write true four Data size select: 4-bit 3 five Data size select: 5-bit 4 six Data size select: 6-bit 5 seven Data size select: 7-bit 6 eight Data size select: 8-bit 7 nine Data size select: 9-bit 8 ten Data size select: 10-bit 9 eleven Data size select: 11-bit 10 twelve Data size select: 12-bit 11 thirteen Data size select: 13-bit 12 fourteen Data size select: 14-bit 13 fifteen Data size select: 15-bit 14 sixteen Data size select: 16-bit 15 frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write true spi Frame format: Motorola SPI 0 sync_serial Frame format: TI synchronous serial 1 microwire Frame format: National Microwire 2 spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write true low SSPCLKOUT polarity: steady state low 0 high SSPCLKOUT polarity: steady state high 1 sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [7:7] read-write true first_edge SSPCLKOUT phase: data captured on first clock edge 0 second_edge SSPCLKOUT phase: data captured on second clock edge 1 scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write 0 255 ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 0x10 0x00000000 lbm Loop back mode [0:0] read-write true normal Loop back mode: normal serial port operation 0 shifter Loop back mode: output of transmit serial shifter is connected to input of receive serial shifter internally 1 sse Synchronous serial port enable [1:1] read-write true disabled Synchronous serial port: disabled 0 enabled Synchronous serial port: enabled 1 ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0. [2:2] read-write true master Mode select: master 0 slave Mode select: slave 1 sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write true drive SSPTXD output disable: SSP can drive the SSPTXD output 0 no_drive SSPTXD output disable: SSP must not drive the SSPTXD output 1 ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 0x10 0x00000000 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write 0 65535 ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xC 0x10 0x00000000 tfe Transmit FIFO empty. [0:0] read-only true not_empty Transmit FIFO is not empty 0 empty Transmit FIFO is empty 1 tnf Transmit FIFO not full. [1:1] read-only true full Transmit FIFO is full 0 not_full Transmit FIFO is not full 1 rne Receive FIFO not empty. [2:2] read-only true empty Receive FIFO is empty 0 not_empty Receive FIFO is not empty 1 rff Receive FIFO full. [3:3] read-only true not_full Receive FIFO is not full 0 full Receive FIFO is full 1 bsy PrimeCell SSP busy flag. [4:4] read-only true idle SSP is idle 0 busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 0x10 0x00000000 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write 2 254 ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 0x10 0x00000000 rorim Receive overrun interrupt mask [0:0] read-write true masked Receive FIFO written to while full condition interrupt is masked 0 not_masked Receive FIFO written to while full condition interrupt is not masked 1 rtim Receive timeout interrupt mask [1:1] read-write true masked Receive FIFO not empty and no read prior to timeout period interrupt is masked 0 not_masked Receive FIFO not empty and no read prior to timeout period interrupt is not masked 1 rxim Receive FIFO interrupt mask [2:2] read-write true masked Receive FIFO half full or less condition interrupt is masked 0 not_masked Receive FIFO half full or less condition interrupt is not masked 1 txim Transmit FIFO interrupt mask [3:3] read-write true masked Transmit FIFO half empty or less condition interrupt is masked 0 not_masked Transmit FIFO half empty or less condition interrupt is not masked 1 ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 0x10 0x00000000 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1C 0x10 0x00000000 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 0x10 0x00000000 roric Clears the SSPRORINTR interrupt [0:0] read-write true nop SSPRORINTR receive interrupt clear: no-op 0 clear SSPRORINTR receive interrupt clear: clear 1 rtic Clears the SSPRTINTR interrupt [1:1] read-write true nop SSPRTINTR transmit interrupt clear: no-op 0 clear SSPRTINTR transmit interrupt clear: clear 1 ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 0x10 0x00000000 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE0 0x10 0x00000000 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE4 0x10 0x00000000 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE8 0x10 0x00000000 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFEC 0x10 0x00000000 configuration These bits read back as 0x80 [7:0] read-only 4 0x4 ssp_pcell_id[%s] The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xFF0 0x10 0x00000000 ssp_pcell_id The bits of the SSPCELLID are read as: [0x0d, 0xf0, 0x05, 0xb1] [7:0] read-only spi4 ARM pl022 SSP SPI: spi4 0x12080000 0x0 0x10000 registers SPI4 53 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 0x10 0x00000000 dss Data Size Select [3:0] read-write true four Data size select: 4-bit 3 five Data size select: 5-bit 4 six Data size select: 6-bit 5 seven Data size select: 7-bit 6 eight Data size select: 8-bit 7 nine Data size select: 9-bit 8 ten Data size select: 10-bit 9 eleven Data size select: 11-bit 10 twelve Data size select: 12-bit 11 thirteen Data size select: 13-bit 12 fourteen Data size select: 14-bit 13 fifteen Data size select: 15-bit 14 sixteen Data size select: 16-bit 15 frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write true spi Frame format: Motorola SPI 0 sync_serial Frame format: TI synchronous serial 1 microwire Frame format: National Microwire 2 spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write true low SSPCLKOUT polarity: steady state low 0 high SSPCLKOUT polarity: steady state high 1 sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [7:7] read-write true first_edge SSPCLKOUT phase: data captured on first clock edge 0 second_edge SSPCLKOUT phase: data captured on second clock edge 1 scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write 0 255 ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 0x10 0x00000000 lbm Loop back mode [0:0] read-write true normal Loop back mode: normal serial port operation 0 shifter Loop back mode: output of transmit serial shifter is connected to input of receive serial shifter internally 1 sse Synchronous serial port enable [1:1] read-write true disabled Synchronous serial port: disabled 0 enabled Synchronous serial port: enabled 1 ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0. [2:2] read-write true master Mode select: master 0 slave Mode select: slave 1 sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write true drive SSPTXD output disable: SSP can drive the SSPTXD output 0 no_drive SSPTXD output disable: SSP must not drive the SSPTXD output 1 ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 0x10 0x00000000 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write 0 65535 ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xC 0x10 0x00000000 tfe Transmit FIFO empty. [0:0] read-only true not_empty Transmit FIFO is not empty 0 empty Transmit FIFO is empty 1 tnf Transmit FIFO not full. [1:1] read-only true full Transmit FIFO is full 0 not_full Transmit FIFO is not full 1 rne Receive FIFO not empty. [2:2] read-only true empty Receive FIFO is empty 0 not_empty Receive FIFO is not empty 1 rff Receive FIFO full. [3:3] read-only true not_full Receive FIFO is not full 0 full Receive FIFO is full 1 bsy PrimeCell SSP busy flag. [4:4] read-only true idle SSP is idle 0 busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 0x10 0x00000000 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write 2 254 ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 0x10 0x00000000 rorim Receive overrun interrupt mask [0:0] read-write true masked Receive FIFO written to while full condition interrupt is masked 0 not_masked Receive FIFO written to while full condition interrupt is not masked 1 rtim Receive timeout interrupt mask [1:1] read-write true masked Receive FIFO not empty and no read prior to timeout period interrupt is masked 0 not_masked Receive FIFO not empty and no read prior to timeout period interrupt is not masked 1 rxim Receive FIFO interrupt mask [2:2] read-write true masked Receive FIFO half full or less condition interrupt is masked 0 not_masked Receive FIFO half full or less condition interrupt is not masked 1 txim Transmit FIFO interrupt mask [3:3] read-write true masked Transmit FIFO half empty or less condition interrupt is masked 0 not_masked Transmit FIFO half empty or less condition interrupt is not masked 1 ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 0x10 0x00000000 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1C 0x10 0x00000000 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 0x10 0x00000000 roric Clears the SSPRORINTR interrupt [0:0] read-write true nop SSPRORINTR receive interrupt clear: no-op 0 clear SSPRORINTR receive interrupt clear: clear 1 rtic Clears the SSPRTINTR interrupt [1:1] read-write true nop SSPRTINTR transmit interrupt clear: no-op 0 clear SSPRTINTR transmit interrupt clear: clear 1 ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 0x10 0x00000000 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE0 0x10 0x00000000 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE4 0x10 0x00000000 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE8 0x10 0x00000000 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFEC 0x10 0x00000000 configuration These bits read back as 0x80 [7:0] read-only 4 0x4 ssp_pcell_id[%s] The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xFF0 0x10 0x00000000 ssp_pcell_id The bits of the SSPCELLID are read as: [0x0d, 0xf0, 0x05, 0xb1] [7:0] read-only spi5 ARM pl022 SSP SPI: spi5 0x12090000 0x0 0x10000 registers SPI5 54 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 0x10 0x00000000 dss Data Size Select [3:0] read-write true four Data size select: 4-bit 3 five Data size select: 5-bit 4 six Data size select: 6-bit 5 seven Data size select: 7-bit 6 eight Data size select: 8-bit 7 nine Data size select: 9-bit 8 ten Data size select: 10-bit 9 eleven Data size select: 11-bit 10 twelve Data size select: 12-bit 11 thirteen Data size select: 13-bit 12 fourteen Data size select: 14-bit 13 fifteen Data size select: 15-bit 14 sixteen Data size select: 16-bit 15 frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write true spi Frame format: Motorola SPI 0 sync_serial Frame format: TI synchronous serial 1 microwire Frame format: National Microwire 2 spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write true low SSPCLKOUT polarity: steady state low 0 high SSPCLKOUT polarity: steady state high 1 sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [7:7] read-write true first_edge SSPCLKOUT phase: data captured on first clock edge 0 second_edge SSPCLKOUT phase: data captured on second clock edge 1 scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write 0 255 ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 0x10 0x00000000 lbm Loop back mode [0:0] read-write true normal Loop back mode: normal serial port operation 0 shifter Loop back mode: output of transmit serial shifter is connected to input of receive serial shifter internally 1 sse Synchronous serial port enable [1:1] read-write true disabled Synchronous serial port: disabled 0 enabled Synchronous serial port: enabled 1 ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0. [2:2] read-write true master Mode select: master 0 slave Mode select: slave 1 sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write true drive SSPTXD output disable: SSP can drive the SSPTXD output 0 no_drive SSPTXD output disable: SSP must not drive the SSPTXD output 1 ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 0x10 0x00000000 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write 0 65535 ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xC 0x10 0x00000000 tfe Transmit FIFO empty. [0:0] read-only true not_empty Transmit FIFO is not empty 0 empty Transmit FIFO is empty 1 tnf Transmit FIFO not full. [1:1] read-only true full Transmit FIFO is full 0 not_full Transmit FIFO is not full 1 rne Receive FIFO not empty. [2:2] read-only true empty Receive FIFO is empty 0 not_empty Receive FIFO is not empty 1 rff Receive FIFO full. [3:3] read-only true not_full Receive FIFO is not full 0 full Receive FIFO is full 1 bsy PrimeCell SSP busy flag. [4:4] read-only true idle SSP is idle 0 busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 0x10 0x00000000 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write 2 254 ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 0x10 0x00000000 rorim Receive overrun interrupt mask [0:0] read-write true masked Receive FIFO written to while full condition interrupt is masked 0 not_masked Receive FIFO written to while full condition interrupt is not masked 1 rtim Receive timeout interrupt mask [1:1] read-write true masked Receive FIFO not empty and no read prior to timeout period interrupt is masked 0 not_masked Receive FIFO not empty and no read prior to timeout period interrupt is not masked 1 rxim Receive FIFO interrupt mask [2:2] read-write true masked Receive FIFO half full or less condition interrupt is masked 0 not_masked Receive FIFO half full or less condition interrupt is not masked 1 txim Transmit FIFO interrupt mask [3:3] read-write true masked Transmit FIFO half empty or less condition interrupt is masked 0 not_masked Transmit FIFO half empty or less condition interrupt is not masked 1 ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 0x10 0x00000000 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1C 0x10 0x00000000 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 0x10 0x00000000 roric Clears the SSPRORINTR interrupt [0:0] read-write true nop SSPRORINTR receive interrupt clear: no-op 0 clear SSPRORINTR receive interrupt clear: clear 1 rtic Clears the SSPRTINTR interrupt [1:1] read-write true nop SSPRTINTR transmit interrupt clear: no-op 0 clear SSPRTINTR transmit interrupt clear: clear 1 ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 0x10 0x00000000 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE0 0x10 0x00000000 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE4 0x10 0x00000000 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE8 0x10 0x00000000 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFEC 0x10 0x00000000 configuration These bits read back as 0x80 [7:0] read-only 4 0x4 ssp_pcell_id[%s] The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xFF0 0x10 0x00000000 ssp_pcell_id The bits of the SSPCELLID are read as: [0x0d, 0xf0, 0x05, 0xb1] [7:0] read-only spi6 ARM pl022 SSP SPI: spi6 0x120A0000 0x0 0x10000 registers SPI6 55 ssp_cr0 SSPCR0 is control register 0 and contains five bit fields that control various functions within the PrimeCell SSP. 0x0 0x10 0x00000000 dss Data Size Select [3:0] read-write true four Data size select: 4-bit 3 five Data size select: 5-bit 4 six Data size select: 6-bit 5 seven Data size select: 7-bit 6 eight Data size select: 8-bit 7 nine Data size select: 9-bit 8 ten Data size select: 10-bit 9 eleven Data size select: 11-bit 10 twelve Data size select: 12-bit 11 thirteen Data size select: 13-bit 12 fourteen Data size select: 14-bit 13 fifteen Data size select: 15-bit 14 sixteen Data size select: 16-bit 15 frf Frame format - 00: Motorola SPI frame format, 01: TI synchronous serial frame format, 10: National Microwire frame format, 11: Reserved [5:4] read-write true spi Frame format: Motorola SPI 0 sync_serial Frame format: TI synchronous serial 1 microwire Frame format: National Microwire 2 spo SSPCLKOUT polarity, applicable to Motorola SPI frame format only. [6:6] read-write true low SSPCLKOUT polarity: steady state low 0 high SSPCLKOUT polarity: steady state high 1 sph SSPCLKOUT phase, applicable to Motorola SPI frame format only. [7:7] read-write true first_edge SSPCLKOUT phase: data captured on first clock edge 0 second_edge SSPCLKOUT phase: data captured on second clock edge 1 scr Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: (F[sspclk] / (CPSDVR * (1 + SCR))), where CPSDVSR is an even value from [2:254], programmed through the SSPCPSR register and SCR is a value from [0:255] [15:8] read-write 0 255 ssp_cr1 SSPCR1 is the control register 1 and contains four different bit fields, that control various functions within the PrimeCell SSP. 0x4 0x10 0x00000000 lbm Loop back mode [0:0] read-write true normal Loop back mode: normal serial port operation 0 shifter Loop back mode: output of transmit serial shifter is connected to input of receive serial shifter internally 1 sse Synchronous serial port enable [1:1] read-write true disabled Synchronous serial port: disabled 0 enabled Synchronous serial port: enabled 1 ms Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0. [2:2] read-write true master Mode select: master 0 slave Mode select: slave 1 sod Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line - 0: SSP can drive the SSPTXD output in slave mode, 1: SSP must not drive the SSPTXD output in slave mode [3:3] read-write true drive SSPTXD output disable: SSP can drive the SSPTXD output 0 no_drive SSPTXD output disable: SSP must not drive the SSPTXD output 1 ssp_dr SSPDR is the data register and is 16-bits wide. When SSPDR is read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the PrimeCell SSP receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When SSPDR is written to, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSPTXD pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. 0x8 0x10 0x00000000 data Transmit/Receive FIFO - Read: Receive FIFO, Write: Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write 0 65535 ssp_sr SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. 0xC 0x10 0x00000000 tfe Transmit FIFO empty. [0:0] read-only true not_empty Transmit FIFO is not empty 0 empty Transmit FIFO is empty 1 tnf Transmit FIFO not full. [1:1] read-only true full Transmit FIFO is full 0 not_full Transmit FIFO is not full 1 rne Receive FIFO not empty. [2:2] read-only true empty Receive FIFO is empty 0 not_empty Receive FIFO is not empty 1 rff Receive FIFO full. [3:3] read-only true not_full Receive FIFO is not full 0 full Receive FIFO is full 1 bsy PrimeCell SSP busy flag. [4:4] read-only true idle SSP is idle 0 busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 ssp_cpsr SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between [2:254]. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. 0x10 0x10 0x00000000 cpsdvsr Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write 2 254 ssp_imsc The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset. 0x14 0x10 0x00000000 rorim Receive overrun interrupt mask [0:0] read-write true masked Receive FIFO written to while full condition interrupt is masked 0 not_masked Receive FIFO written to while full condition interrupt is not masked 1 rtim Receive timeout interrupt mask [1:1] read-write true masked Receive FIFO not empty and no read prior to timeout period interrupt is masked 0 not_masked Receive FIFO not empty and no read prior to timeout period interrupt is not masked 1 rxim Receive FIFO interrupt mask [2:2] read-write true masked Receive FIFO half full or less condition interrupt is masked 0 not_masked Receive FIFO half full or less condition interrupt is not masked 1 txim Transmit FIFO interrupt mask [3:3] read-write true masked Transmit FIFO half empty or less condition interrupt is masked 0 not_masked Transmit FIFO half empty or less condition interrupt is not masked 1 ssp_ris The SSPRIS register is the raw interrupt status register. It is a RO register. On a read this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. 0x18 0x10 0x00000000 rorris Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only rtris Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only rxris Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only txris Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only ssp_mis The SSPMIS register is the masked interrupt status register. It is a RO register. On a read this register gives the current masked status value of the corresponding interrupt. A write has no effect. 0x1C 0x10 0x00000000 rormis Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only rtmis Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only rxmis Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only txmis Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only ssp_icr The SSPICR register is the interrupt clear register and is write-only. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. 0x20 0x10 0x00000000 roric Clears the SSPRORINTR interrupt [0:0] read-write true nop SSPRORINTR receive interrupt clear: no-op 0 clear SSPRORINTR receive interrupt clear: clear 1 rtic Clears the SSPRTINTR interrupt [1:1] read-write true nop SSPRTINTR transmit interrupt clear: no-op 0 clear SSPRTINTR transmit interrupt clear: clear 1 ssp_dmacr The SSPDMACR register is the DMA control register. It is a RW register. All the bits are cleared to 0 on reset. 0x24 0x10 0x00000000 rxdmae Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write txdmae Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write ssp_periph_id0 The SSPPeriphID0 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE0 0x10 0x00000000 part_number0 These bits read back as 0x22 [7:0] read-only ssp_periph_id1 The SSPPeriphID1 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE4 0x10 0x00000000 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only ssp_periph_id2 The SSPPeriphID2 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFE8 0x10 0x00000000 designer1 These bits read back as 0x4 [3:0] read-only revision These bits return the peripheral revision [7:4] read-only ssp_periph_id3 The SSPPeriphID3 register is hard-coded and the fields within the register determine reset value. The SSPPeriphID0-3 registers are four 8-bit registers, that span address locations 0xFE0 to 0xFEC. The registers can conceptually be treated as a single 32-bit register. 0xFEC 0x10 0x00000000 configuration These bits read back as 0x80 [7:0] read-only 4 0x4 ssp_pcell_id[%s] The SSPPCellID0-3 registers are four 8-bit wide registers, that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a 32-bit register. The register is used as a standard cross-peripheral identification system. The SSPPCellID register is set to 0xB105F00D. 0xFF0 0x10 0x00000000 ssp_pcell_id The bits of the SSPCELLID are read as: [0x0d, 0xf0, 0x05, 0xb1] [7:0] read-only qspi Cadence QSPI NOR: qspi 0x13010000 0x0 0x10000 registers QSPI0 25 config Cadence QSPI Configuration 0x0 0x20 0x00000000 enable Enable the QSPI controller [0:0] read-write enb_dir_acc_ctrl Enable direct access controller [7:7] read-write decode Enable the QSPI decoder [9:9] read-write chipselect Chip select - CS0: 0b1110, CS1: 0b1101, CS2: 0b1011, CS3: 0b0111 [13:10] read-write true cs0 Chip select 0 14 cs1 Chip select 1 13 cs2 Chip select 2 11 cs3 Chip select 3 7 dma Enable Direct Memory Access [15:15] read-write baud Set the QSPI BAUD rate divisor [22:19] read-write 0 15 dtr_proto Enable DTR Protocol [24:24] read-write dual_opcode Enable Dual Opcode Mode [30:30] read-write idle Set Idle [31:31] read-write rd_instr Cadence QSPI Read Instruction 0x4 0x20 0x00000000 opcode Instruction Opcode [7:0] read-write 0 255 type_instr Type of Instruction [9:8] read-write 0 3 type_addr Type of Address [13:12] read-write 0 3 type_data [17:16] read-write 0 3 mode_en Mode enable [20:20] read-write dummy Send dummy signal to stall the device [28:24] read-write 0 31 wr_instr Cadence QSPI Write Instruction 0x8 0x20 0x00000000 opcode Instruction Opcode [7:0] read-write 0 255 type_addr Type of Address [13:12] read-write 0 3 type_data [17:16] read-write 0 3 delay Cadence QSPI Delay 0xC 0x20 0x00000000 tslch TSLCH Delay Value [7:0] read-write 0 255 tchsh TCHSH Delay Value [15:8] read-write 0 255 tsd2d TSD2D Delay Value [23:16] read-write 0 255 tshsl TSHSL Delay Value [31:24] read-write 0 255 read_capture Cadence QSPI Read Capture 0x10 0x20 0x00000000 bypass Bypass the Read Capture [0:0] read-write delay Read Capture Delay Value [4:1] read-write 0 15 size Cadence QSPI Size Configuration 0x14 0x20 0x00000000 address Address Size in Bytes [3:0] read-write 0 15 page Page Size in Bytes [15:4] read-write 0 4095 block Block Size in Bytes [21:16] read-write 0 63 sram_partition Cadence QSPI SRAM Partition Size 0x18 0x20 0x00000000 size Partition size in bytes [31:0] read-write 0 4294967295 indirect_trigger Cadence QSPI Indirect Trigger Address 0x1C 0x20 0x00000000 address [31:0] read-write 0 4294967295 dma Cadence QSPI Direct Memory Access 0x20 0x20 0x00000000 single [7:0] read-write 0 255 burst [15:8] read-write 0 255 remap Cadence QSPI Remap Address 0x24 0x20 0x00000000 address [31:0] read-write 0 4294967295 mode_bit Cadence QSPI Mode Bit(s) 0x28 0x20 0x00000000 mode [31:0] read-write 0 4294967295 sdram_level Cadence QSPI SDRAM Level 0x2C 0x20 0x00000000 rd SDRAM Read Level [15:0] read-only wr SDRAM Write Level [31:16] read-only wr_completion_ctrl Cadence QSPI Write Completion Control 0x38 0x20 0x00000000 disable_auto_poll SPI NAND flashes require the address of the status register to be passed in the Read SR command. Also, some SPI NOR flashes like the Cypress Semper flash expect a 4-byte dummy address in the Read SR command in DTR mode. But this controller does not support address phase in the Read SR command when doing auto-HW polling. So, disable write completion polling on the controller's side. spi-nand and spi-nor will take care of polling the status register. [14:14] read-write irq_status Cadence QSPI IRQ Status 0x40 0x20 0x0001FFFF mode_err Mode error interrupt [0:0] read-write underflow Buffer underflow interrupt [1:1] read-write ind_comp Indirect computation interrupt [2:2] read-write ind_rd_reject Indirect read rejection interrupt [3:3] read-write wr_protected_err Write protected error interrupt [4:4] read-write illegal_ahb_err Illegal AHB clock error interrupt [5:5] read-write watermark Watermark interrupt [6:6] read-write ind_sram_full Indirect SRAM full interrupt [12:12] read-write irq_mask Cadence QSPI IRQ Mask 0x44 0x20 0x00000046 mode_err Mode error interrupt [0:0] read-write underflow Buffer underflow interrupt [1:1] read-write ind_comp Indirect computation interrupt [2:2] read-write ind_rd_reject Indirect read rejection interrupt [3:3] read-write wr_protected_err Write protected error interrupt [4:4] read-write illegal_ahb_err Illegal AHB clock error interrupt [5:5] read-write watermark Watermark interrupt [6:6] read-write ind_sram_full Indirect SRAM full interrupt [12:12] read-write indirect_rd Cadence QSPI Indirect Read 0x60 0x20 0x00000000 start Start indirect read [0:0] read-write cancel Cancel indirect read [1:1] read-write done Indirect read done [5:5] read-write indirect_wr Cadence QSPI Indirect Write 0x70 0x20 0x00000000 start Start indirect write [0:0] read-write cancel Cancel indirect write [1:1] read-write done Indirect write done [5:5] read-write indirect_wr_watermark Cadence QSPI Indirect Write Watermark 0x74 0x20 0x00000000 watermark [31:0] read-write 0 4294967295 indirect_wr_start_addr Cadence QSPI Indirect Write Start Address 0x78 0x20 0x00000000 address [31:0] read-write 0 4294967295 indirect_wr_bytes Cadence QSPI Indirect Write Bytes 0x7C 0x20 0x00000000 bytes [31:0] read-write 0 4294967295 cmd_ctrl Cadence QSPI Command Control 0x90 0x20 0x00000000 execute Execute-in-Place (XIP) [0:0] read-write in_progress Command in progress [1:1] read-write dummy Dummy command [11:7] read-write 0 31 wr_bytes Write bytes [14:12] read-write 0 3 wr_en Write enable [15:15] read-write add_bytes Add command bytes [17:16] read-write 0 3 addr_en Address enable [19:19] read-write rd_bytes Read bytes [22:20] read-write 0 7 rd_en Read enable [23:23] read-write opcode Command opcode [31:24] read-write 0 255 cmd_address Cadence QSPI Command Address 0x94 0x20 0x00000000 address [31:0] read-write 0 4294967295 cmd_read_at_lower Cadence QSPI Command Read at Lower 0xA0 0x20 0x00000000 read_at_lower [31:0] read-write 0 4294967295 cmd_read_at_upper Cadence QSPI Command Read at Upper 0xA4 0x20 0x00000000 read_at_upper [31:0] read-write 0 4294967295 cmd_write_at_lower Cadence QSPI Command Write at Lower 0xA8 0x20 0x00000000 write_at_lower [31:0] read-write 0 4294967295 cmd_write_at_upper Cadence QSPI Command Write at Upper 0xAC 0x20 0x00000000 write_at_upper [31:0] read-write 0 4294967295 polling_status Cadence QSPI Polling Status 0xB0 0x20 0x00000000 status [15:0] read-write 0 65535 dummy [20:16] read-write 0 31 ext_lower Cadence QSPI Extension Lower 0xE0 0x20 0x00000000 stig [15:0] read-write 0 65535 write [23:16] read-write 0 255 read [31:24] read-write 0 255 xspi Cadence XSPI NOR (XIP Flash region): xspi 0x21000000 0x0 0x400000 registers 1048576 0x4 word[%s] Cadence XSPI NOR Flash word 0x0 0x20 0x00000000 word Cadence XSPI NOR Flash word [31:0] read-write 0 4294967295 pwm Opencores PTC PWM v1: pwm 0x120D0000 0x0 0x10000 registers cntr Opencores PTC PWM v1 CNTR is the actual counter register. It is incremented at every counter/timer clock cycle. Source clock is either system clock or ptc_ecgt eclk/gate input. Selection between both clocks is performed with the RPTC_CTRL[ECLK]. Active edge of external clock is selected with the RPTC_CTRL[NEC]. In order to count, RPTC_CNTR must first be enabled with the RPTC_CTRL[EN]. RPTC_CNTR can be reset with the RPTC_CTRL[RST]. RPTC_CNTR can operate in either single-run mode or continues mode. Mode is selected with the RPTC_CTRL[SINGLE]. 0x0 0x20 0x00000000 cntr [31:0] read-write 0 4294967295 hrc Opencores PTC PWM v1 HRC register is a 2nd out of two reference/capture registers. It has two functions: - In reference mode it is used to assert high PWM output or to generate an interrupt - In capture mode it captures RPTC_CNTR value on high value of ptc_capt signal. The RPTC_HRC should have lower value than RPTC_LRC. This is because PWM output goes first high and later low. 0x4 0x20 0x00000000 hrc [31:0] read-write 0 4294967295 lrc Opencores PTC PWM v1 RPTC_LRC register is a 1st out of two reference/capture registers. It has two functions: - In reference mode it is used to assert low PWM output or to generate an interrupt - In capture mode it captures RPTC_CNTR value on low value of ptc_capt signal. The RPTC_LRC should have higher value than RPTC_HRC. This is because PWM output goes first high and later low. 0x8 0x20 0x00000000 lrc [31:0] read-write 0 4294967295 ctrl Opencores PTC PWM v1 RPTC_CTRL register control operation of PTC core. 0xC 0x9 0x00000000 en When set, RPTC_CNTR can be incremented. [0:0] read-write true no_increment RPTC_CNTR cannot be incremented. 0 increment RPTC_CNTR can be incremented. 1 eclk When set, ptc_ecgt signal is used to increment RPTC_CNTR. When cleared, system clock is used instead. [1:1] read-write true sys_clock System clock is used to increment the RPTC_CNTR. 0 ptc_ecgt `ptc_ecgt` signal is used to increment the RPTC_CNTR. 1 nec When set, ptc_ecgt increments on negative edge and gates on low period. When cleared, ptc_ecgt increments on positive edge and gates on high period. This bit has effect only on `gating` function of ptc_ecgt when RPTC_CTRL[ECLK] bit is cleared. [2:2] read-write true pos_edge `ptc_ecgt` increments on positive edge, and gates on high period. 0 neg_edge `ptc_ecgt` increments on negative edge, and gates on low period. 1 oe Inverted value of this bit is reflected on the ptc_oen signal. It is used to enable PWM output driver. [3:3] read-write true ptc_oen_high `ptc_oen` signal is set high. 0 ptc_oen_low `ptc_oen` signal is set low. 1 single When set, RPTC_CNTR is not incremented anymore after it reaches value equal to the RPTC_LRC value. When cleared, RPTC_CNTR is restarted after it reaches value in the RPTC_LCR register. [4:4] read-write true reset RPTC_CNTR is restarted after it reaches value in RPTC_LCR register. 0 no_reset RPTC_CNTR is not incremented after it reaches value in RPTC_LCR register. 1 inte When set, PTC asserts an interrupt when RPTC_CNTR value is equal to the value of RPTC_LRC or RPTC_HRC. When cleared, interrupts are masked. [5:5] read-write true mask PTC interrupts are masked. 0 interrupt PTC asserts an interrupt when RPTC_CNTR value is equal to the value of RPTC_LRC or RPTC_HRC. 1 int When read, this bit represents pending interrupt. When it is set, an interrupt is pending. When this bit is written with `1`, interrupt request is cleared. [6:6] read-write true no_interrupt No interrupt is pending on read, no effect on write. 0 pending_clear Pending interrupt on read, clears interrupt request on write. 1 cntrrst When set, RPTC_CNTR is under reset. When cleared, normal operation of the counter is allowed. [7:7] read-write true normal Normal operation of the counter is allowed. 0 reset RPTC_CNTR is under reset. 1 capte When set, ptc_capt signal can be used to capture RPTC_CNTR into RPTC_LRC or RPTC_HRC registers. Into which reference/capture register capture occurs depends on edge of the ptc_capt signal. When cleared, capture function is masked. [8:8] read-write true masked Capture function is masked. 0 capture `ptc_capt` signal can be used to capture RPTC_CNTR into RPTC_LRC or RPTC_HRC registers. 1 syscrg StarFive JH7110 SYS CRG: syscrg 0x13020000 0x0 0x10000 registers clk_cpu Clock CPU registers 0x0 root Clock CPU Root 0x0 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_osc, clk_pll0 [29:24] read-write true clk_osc Select `clk_osc` as the CPU Root clock. 0 clk_pll0 Select `clk_pll0` as the CPU Root clock. 1 core Clock CPU Core 0x4 0x20 0x00000001 clk_divcfg Clock divider coefficient: Max=7, Default=1, Min=1, Typical=1 [23:0] read-write 1 7 bus Clock CPU Bus 0x8 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_gpu Clock GPU registers 0xC root Clock GPU Root 0x0 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_pll2, clk_pll1 [29:24] read-write true clk_pll2 Select `clk_pll2` as the GPU Root clock. 0 clk_pll1 Select `clk_pll1` as the GPU Root clock. 1 clk_peripheral Clock Peripheral registers 0x10 root Clock Peripheral Root 0x0 0x20 0x00000002 clk_mux_sel Clock multiplexing selector: clk_pll2, clk_pll1 [29:24] read-write true clk_pll2 Select `clk_pll2` as the Peripheral Root clock 0 clk_pll1 Select `clk_pll1` as the Peripheral Root clock 1 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_bus Clock Bus registers 0x14 root Clock Bus Root 0x0 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_osc, clk_pll2 [29:24] read-write true clk_osc Select `clk_osc` as the Bus Root clock. 0 clk_pll2 Select `clk_pll2` as the Bus Root clock. 1 clk_nocstg_bus Clock NOC STG Bus 0x18 0x20 0x00000003 clk_divcfg Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 [23:0] read-write 3 3 clk_axi_cfg0 Clock AXI Configuration 0x1C 0x20 0x00000003 clk_divcfg Clock divider coefficient: Max=3, Default=3, Min=3, Typical=3 [23:0] read-write 3 3 clk_stg_axiahb Clock STG AXI AHB 0x20 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 2 0x4 clk_ahb[%s] Clock AHB 0x24 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_apb_bus Clock APB Bus 0x2C 0x20 0x00000004 clk_divcfg Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4 [23:0] read-write 4 8 clk_apb0 Clock APB 0x30 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 3 0x4 0_div2,1_div2,2_div2 clk_pll[%s] Clock PLL Divider 2 0x34 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_audio Clock Audio registers 0x40 root Clock Audio Root 0x0 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 [23:0] read-write 2 8 clk_mclk Clock MCLK registers 0x44 inner Clock MCLK Inner 0x0 0x20 0x0000000C clk_divcfg Clock divider coefficient: Max=64, Default=12, Min=12, Typical=12 [23:0] read-write 12 64 mclk Clock MCLK 0x4 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_mclk_inner, clk_mclk_ext [29:24] read-write true clk_mclk_inner Select `clk_mclk_inner` as the MCLK clock. 0 clk_mclk_ext Select `clk_mclk_ext` as the MCLK clock. 1 out Clock MCLK Out 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_isp Clock ISP registers 0x50 isp_2x Clock ISP 2x 0x0 0x20 0x00000002 clk_mux_sel Clock multiplexing selector: clk_pll2, clk_pll1 [29:24] read-write true clk_pll2 Select `clk_pll2` as the ISP 2x clock. 0 clk_pll1 Select `clk_pll1` as the ISP 2x clock. 1 clk_divcfg Clock divider coefficient: Max=8, Default=2, Min=2, Typical=2 [23:0] read-write 2 8 axi Clock ISP AXI 0x4 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=4, Default=2, Min=2, Typical=2 [23:0] read-write 2 4 clk_gclk Clock GCLK registers 0x58 clk_gclk0 Clock GCLK 0 0x0 0x20 0x80000014 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=62, Default=20, Min=16, Typical=20 [23:0] read-write 16 62 clk_gclk1 Clock GCLK 1 0x4 0x20 0x80000010 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=62, Default=16, Min=16, Typical=16 [23:0] read-write 16 62 clk_gclk2 Clock GCLK 2 0x8 0x20 0x8000000C clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=62, Default=12, Min=12, Typical=12 [23:0] read-write 12 62 clk_u7mc Clock U7MC registers 0x64 5 0x4 core[%s] Clock U7MC Core 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 debug Clock U7MC Debug 0x14 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 rtc_toggle Clock U7MC RTC Toggle 0x18 0x20 0x00000006 clk_divcfg Clock divider coefficient: Max=6, Default=6, Min=6, Typical=6 [23:0] read-write 6 6 5 0x4 trace[%s] Clock U7MC Trace 0x1C 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 trace_com Clock U7MC Trace 0x30 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_noc_bus Clock NOC Bus registers 0x98 cpu_axi clk_u0_sft7110_noc_bus_clk_cpu_axi 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 axicfg0_axi clk_u0_sft7110_noc_bus_clk_axicfg0_axi 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_osc_div2 clk_osc_div2 0xA0 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_pll1_div4 clk_pll1_div4 0xA4 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_pll1_div8 clk_pll1_div8 0xA8 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_ddr Clock DDR registers 0xAC bus clk_ddr_bus 0x0 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_osc_div2, clk_pll1_div2, clk_pll1_div4, clk_pll1_div8 [29:24] read-write true clk_osc_div2 Select `clk_osc_div2` as the DDR Bus clock. 0 clk_pll1_div2 Select `clk_pll1_div2` as the DDR Bus clock. 1 clk_pll1_div4 Select `clk_pll1_div4` as the DDR Bus clock. 2 clk_pll1_div8 Select `clk_pll1_div8` as the DDR Bus clock. 3 axi clk_ddr_axi 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_img_gpu Clock IMG GPU registers 0xB4 divcfg Clock IMG GPU Core DIVCFG 0x0 0x20 0x00000003 clk_divcfg Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 [23:0] read-write 3 7 core clk_gpu_core 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 sys clk_u0_img_gpu_sys_clk 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 apb clk_u0_img_gpu_apb_clk 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 rtc_toggle clk_u0_img_gpu_rtc_toggle 0x10 0x20 0x0000000C clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=12, Default=12, Min=12, Typical=12 [23:0] read-write 12 12 noc_bus_axi clk_u0_sft7110_noc_bus_clk_gpu_axi 0x14 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_isp_dom Clock ISP DOM registers 0xCC ispcore_2x clk_u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 axi clk_u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 noc_bus_axi clk_u0_sft7110_noc_bus_clk_isp_axi 0x8 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_hifi4 Clock HIFI4 registers 0xD8 core clk_hifi4_core 0x0 0x20 0x00000003 clk_divcfg Clock divider coefficient: Max=15, Default=3, Min=3, Typical=3 [23:0] read-write 3 15 axi clk_hifi4_axi 0x4 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_axi_cfg1_dec Clock AXI CFG 1 DEC registers 0xE0 dec_main clk_u0_axi_cfg1_dec_clk_main 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 ahb clk_u0_axi_cfg1_dec_clk_ahb 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_vout Clock Video Output registers 0xE8 src clk_u0_dom_vout_top_clk_dom_vout_top_clk_vout_src 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 axi_divcfg Clock Video Output AXI DIVCFG 0x4 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 [23:0] read-write 2 7 noc_diplay_axi Clock NOC Display AXI 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 ahb Clock Video Output AHB 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 hdmi_tx0_mclk Clock Video Output HDMI TX0 MCLK 0x14 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 mipi_phy Clock Video Output MIPI PHY Reference 0x18 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=2, Default=2, Min=2, Typical=2 [23:0] read-write 2 2 clk_jpeg Clock CODAJ12 registers 0x104 codec_axi Clock JPEG Codec AXI 0x0 0x20 0x00000006 clk_divcfg Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 [23:0] read-write 6 16 codaj12_axi Clock CODAJ12 AXI 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 codaj12_core Clock CODAJ12 Core 0x8 0x20 0x00000006 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=16, Default=6, Min=6, Typical=6 [23:0] read-write 6 16 codaj12_apb Clock CODAJ12 APB 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_vdec Clock Video Decoder registers 0x114 axi Clock Video Decoder AXI 0x0 0x20 0x00000003 clk_divcfg Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 [23:0] read-write 3 7 wave511 Clock Video Decoder WAVE511 registers 0x4 axi Clock WAVE511 AXI 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 bpu Clock WAVE511 BPU 0x4 0x20 0x00000003 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=7, Default=3, Min=3, Typical=3 [23:0] read-write 3 7 vce Clock WAVE511 VCE 0x8 0x20 0x00000002 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=7, Default=2, Min=3, Typical=2 [23:0] read-write 3 7 apb Clock WAVE511 APB 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 jpg Clock Video Decoder JPG registers 0x14 arb Clock Video Decoder JPG ARB 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 main Clock Video Decoder JPG Main 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 noc_axi Clock Video Decoder NOC AXI 0x1C 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_venc Clock Video Encoder registers 0x134 axi Clock Video Encoder AXI 0x0 0x20 0x00000005 clk_divcfg Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 [23:0] read-write 5 15 wave420l Clock Video Encoder WAVE420L registers 0x4 axi Clock WAVE420L AXI 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 bpu Clock WAVE420L BPU 0x4 0x20 0x00000005 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 [23:0] read-write 5 15 wave420l_vce Clock WAVE420L VCE 0x8 0x20 0x00000005 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=15, Default=5, Min=5, Typical=5 [23:0] read-write 5 15 apb Clock WAVE420L APB 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 noc_axi Clock Video Encoder NOC AXI 0x14 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_axi_cfg0_dec Clock AXI CFG 0 DEC registers 0x14C main_div Clock AXI Config 0 DEC Main Divider 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 dec_main Clock AXI Config 0 DEC Main 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 hifi4 Clock AXI Config 0 DEC HIFI4 0x8 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_aximem_128b_axi Clock AXIMEM 128B AXI 0x158 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_qspi Clock QSPI registers 0x15C ahb Clock QSPI AHB 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 apb Clock QSPI APB 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_ref_src Clock QSPI Reference Source 0x8 0x20 0x0000000A clk_divcfg Clock divider coefficient: Max=16, Default=10, Min=10, Typical=10 [23:0] read-write 10 16 clk_ref Clock QSPI Reference 0xC 0x20 0x80000000 clk_mux_sel Clock multiplexing selector: clk_osc, clk_qspi_ref_src [29:24] read-write true clk_osc Select `clk_osc` as the QSPI Reference clock. 0 clk_qspi_ref_src Select `clk_qspi_ref_src` as the QSPI Reference clock. 1 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_sd Clock SD registers 0x16C 2 0x4 _u0,_u1 ahb[%s] Clock SD AHB 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0x4 _u0,_u1 clk_sd_card[%s] Clock SD Card 0x8 0x20 0x80000002 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=15, Default=2, Min=2, Typical=2 [23:0] read-write 2 15 clk_usb_125m Clock USB 125M 0x17C 0x20 0x00000008 clk_divcfg Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write 12 15 clk_noc_stg_axi Clock NOC STG AXI 0x180 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_gmac Clock GMAC registers 0x184 2 0x4 _ahb,_axi gmac5_axi64[%s] Clock GMAC5 AXI64 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 gmac_src Clock GMAC Source 0x8 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=7, Default=2, Min=2, Typical=2 [23:0] read-write 2 7 gmac1_gtx Clock GMAC1 GTX 0xC 0x20 0x00000008 clk_divcfg Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write 12 15 gmac1_rmii_rtx Clock GMAC RMII RTX 0x10 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 [23:0] read-write 2 30 gmac5_axi64_ptp Clock GMAC AXI64 PTP 0x14 0x20 0x0000000A clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=31, Default=10, Min=15, Typical=10 [23:0] read-write 15 31 gmac5_axi64_rx Clock GMAC5 AXI64 RX 0x18 0x20 0x00000000 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write gmac5_axi64_rxi Clock GMAC5 AXI64 RX Inverter 0x1C 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 gmac5_axi64_tx Clock GMAC5 AXI64 TX 0x20 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_gmac1_gtx_clk, clk_gmac1_rmii_rtx [29:24] read-write true clk_gmac1_gtx_clk Select `clk_gmac1_gtx_clk` as the GMAC5 AXI64 TX clock. 0 clk_gmac1_rmii_rtx Select `clk_gmac1_rmii_rtx` as the GMAC5 AXI64 TX clock. 1 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 gmac5_axi64_txi Clock GMAC5 AXI64 TX Inverter 0x24 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 gmac1_gtxc Clock GMAC1 GTXC 0x28 0x20 0x00000000 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write gmac0_gtx Clock GMAC0 GTX 0x2C 0x20 0x00000008 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=15, Default=8, Min=12, Typical=10 [23:0] read-write 12 15 gmac0_ptp Clock GMAC0 PTP 0x30 0x20 0x0000000A clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 [23:0] read-write 15 31 gmac_phy Clock GMAC PHY 0x34 0x20 0x0000000A clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=31, Default=10, Min=15, Typical=25 [23:0] read-write 15 31 gmac0_gtxc Clock GMAC0 GTXC 0x38 0x20 0x00000000 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write clk_pclk Clock PCLK 0x1C0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_mbox_apb Clock Mailbox APB 0x1C4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_internal_ctrl_apb Clock Internal Controller APB 0x1C8 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0xC _u0,_u1 clk_can_ctrl[%s] Clock CAN Controller 0x1CC apb Clock Internal Controller APB 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 tim Clock Internal Controller Timer 0x4 0x20 0x00000018 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=24, Default=24, Min=6, Typical=24 [23:0] read-write 6 24 can Clock Internal Controller CAN 0x8 0x20 0x00000008 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=63, Default=8, Min=8, Typical=8 [23:0] read-write 8 63 clk_pwm_apb Clock PWM APB 0x1E4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_wdt Clock WDT registers 0x1E8 apb Clock WDT APB 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 wdt Clock WDT 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_tim Clock Timer 0x1F0 apb Clock Timer APB 0x0 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0x4 _0,_1 tim01[%s] Clock Timer 0-1 0x4 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0x4 _2,_3 tim23[%s] Clock Timer: 2-3 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_temp_sensor Clock Temperature registers 0x204 apb Clock Temperature Sensor APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 temp_sensor Clock Temperature Sensor 0x4 0x20 0x00000018 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=24, Default=24, Min=24, Typical=24 [23:0] read-write 24 24 clk_spi Clock SPI registers 0x20C 7 0x4 _u0,_u1,_u2,_u3,_u4,_u5,_u6 apb[%s] Clock SPI APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_i2c Clock I2C registers 0x228 7 0x4 _u0,_u1,_u2,_u3,_u4,_u5,_u6 apb[%s] Clock I2C APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_uart Clock UART 0x244 3 0x8 _u0,_u1,_u2 uart02[%s] Clock UART U0-U2 0x0 apb Clock UART APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 core Clock UART Core 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 3 0x8 _u3,_u4,_u5 uart35[%s] Clock UART U3-U5 0x18 apb Clock UART APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 core Clock UART Core 0x4 0x20 0x00000A00 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=131071, Default=2560, Min=2560, Typical=2560 [23:0] read-write 2560 131071 clk_pwmdac Clock PWMDAC registers 0x274 apb Clock PWMDAC APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 core Clock PWMDAC Core 0x4 0x20 0x0000000C clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=256, Default=12, Min=12, Typical=12 [23:0] read-write 12 256 clk_spdif Clock SPDIF registers 0x27C apb Clock SPDIF APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 core Clock SPDIF Core 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 3 0x1C tx_u0,tx_u1,rx clk_i2s[%s] Clock I2S 0x284 apb Clock I2S APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 bclk_mst Clock I2S BCLK MST 0x4 0x20 0x00000004 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=32, Default=4, Min=4, Typical=4 [23:0] read-write 4 32 bclk_mst_inv U0 Clock I2S BCLK MST Inverter 0x8 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 lrck_mst Clock I2S LRCK MST 0xC 0x20 0x00000040 clk_mux_sel Clock multiplexing selector: clk_i2stx_bclk_mst_inv, clk_i2stx_bclk_mst [29:24] read-write true clk_i2stx_bclk_mst_inv Select `clk_i2stx_bclk_mst_inv` as the I2S LRCK MST clock. 0 clk_i2stx_bclk_mst Select `clk_i2stx_bclk_mst` as the I2S LRCK MST clock. 1 clk_divcfg Clock divider coefficient: Max=64, Default=64, Min=64, Typical=64 [23:0] read-write 64 64 bclk Clock I2S BCLK 0x10 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_i2s_bclk_mst, clk_i2s_bclk_ext [29:24] read-write true clk_i2s_bclk_mst Select `clk_i2s_bclk_mst` as the I2S BCLK clock. 0 clk_i2s_bclk_ext Select `clk_i2s_bclk_ext` as the I2S BCLK clock. 1 bclk_neg Clock I2S BCLK Negative 0x14 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 lrck Clock I2S LRCK 0x18 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_i2s_lrck_mst, clk_i2s_lrck_ext [29:24] read-write true clk_i2s_lrck_mst Select `clk_i2s_lrck_mst` as the I2S LRCK clock. 0 clk_i2s_lrck_ext Select `clk_i2s_lrck_ext` as the I2S LRCK clock. 1 clk_pdm Clock PDM 0x2D8 dmic Clock PDM DMIC 0x0 0x20 0x00000008 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=64, Default=8, Min=8, Typical=8 [23:0] read-write 8 64 apb Clock PDM APB 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_tdm Clock TDM 0x2E0 ahb Clock TDM AHB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 apb Clock TDM APB 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 internal Clock TDM Internal 0x8 0x20 0x00000001 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_divcfg Clock divider coefficient: Max=61, Default=1, Min=1, Typical=1 [23:0] read-write 1 61 tdm Clock TDM (clock selector) 0xC 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_tdm_internal, clk_tdm_ext [29:24] read-write true clk_tdm_internal Select `clk_tdm_internal` as the TDM clock. 0 clk_tdm_ext Select `clk_tdm_ext` as the TDM clock. 1 tdm_neg Clock TDM Negative 0x10 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 clk_jtag_trng Clock JTAG TRNG 0x2F4 0x20 0x00000004 clk_divcfg Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 [23:0] read-write 4 4 rst SYSCRG RESET registers 0x2F8 software_address_selector Software RESET Address Selector 0x0 rst0 RESET 0 0x0 0x20 0x00600000 u0_jtag2apb_presetn Reset selector: u0_jtag2apb_presetn [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_sys_syscon_presetn Reset selector: u0_sys_syscon_presetn [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_sys_iomux_presetn Reset selector: u0_sys_iomux_presetn [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_bus Reset selector: u0_bus [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_debug Reset selector: u0_debug [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_0 Reset selector: u0_core_0 [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_1 Reset selector: u0_core_1 [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_2 Reset selector: u0_core_2 [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_3 Reset selector: u0_core_3 [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_4 Reset selector: u0_core_4 [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_0 Reset selector: u0_core_st_0 [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_1 Reset selector: u0_core_st_1 [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_2 Reset selector: u0_core_st_2 [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_3 Reset selector: u0_core_st_3 [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_4 Reset selector: u0_core_st_4 [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_0 Reset selector: u0_trace_0 [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_1 Reset selector: u0_trace_1 [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_2 Reset selector: u0_trace_2 [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_3 Reset selector: u0_trace_3 [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_4 Reset selector: u0_trace_4 [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_com Reset selector: u0_trace_com [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_img_gpu_apb Reset selector: u0_img_gpu_apb [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_img_gpu_doma Reset selector: u0_img_gpu_doma [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_apb Reset selector: u0_noc_bus_apb [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_axicfg0 Reset selector: u0_noc_bus_axicfg0 [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_cpu_axi Reset selector: u0_noc_bus_cpu_axi [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_disp_axi Reset selector: u0_noc_bus_disp_axi [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_gpu_axi Reset selector: u0_noc_bus_gpu_axi [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_isp_axi Reset selector: u0_noc_bus_isp_axi [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_ddrc Reset selector: u0_noc_bus_ddrc [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_stg_axi Reset selector: u0_noc_bus_stg_axi [30:30] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_vdec_axi Reset selector: u0_noc_bus_vdec_axi [31:31] read-write true none De-assert reset. 0 reset Assert reset. 1 rst1 RESET 1 0x4 0x20 0x07E7FE00 u0_noc_bus_venc_axi Reset selector: u0_noc_bus_venc_axi [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg1_dec_ahb Reset selector: u0_axi_cfg1_dec_ahb [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg1_dec_main Reset selector: u0_axi_cfg1_dec_main [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg0_dec_main Reset selector: u0_axi_cfg0_dec_main [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg0_dec_main_div Reset selector: u0_axi_cfg0_dec_main_div [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg0_dec_hifi4 Reset selector: u0_axi_cfg0_dec_hifi4 [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_ddr_axi Reset selector: u0_ddr_axi [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_ddr_osc Reset selector: u0_ddr_osc [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_ddr_apb Reset selector: u0_ddr_apb [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_isp_top Reset selector: u0_isp_top [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_isp_axi Reset selector: u0_isp_axi [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_vout_src Reset selector: u0_vout_src [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_codaj12_axi Reset selector: u0_codaj12_axi [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_codaj12_core Reset selector: u0_codaj12_core [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_codaj12_apb Reset selector: u0_codaj12_apb [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_axi Reset selector: u0_wave511_axi [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_bpu Reset selector: u0_wave511_bpu [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_vce Reset selector: u0_wave511_vce [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_apb Reset selector: u0_wave511_apb [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_vdec_jpg_arb Reset selector: u0_vdec_jpg_arb [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_vdec_jpg_arb_main Reset selector: u0_vdec_jpg_arb_main [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_aximem_128b_axi Reset selector: u0_aximem_128b_axi [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_axi Reset selector: u0_wave420l_axi [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_bpu Reset selector: u0_wave420l_bpu [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_vce Reset selector: u0_wave420l_vce [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_apb Reset selector: u0_wave420l_apb [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_aximem Reset selector: u1_aximem [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_aximem Reset selector: u2_aximem [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_intmem_rom_sram Reset selector: u0_intmem_rom_sram [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_qspi_ahb Reset selector: u0_qspi_ahb [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_qspi_apb Reset selector: u0_qspi_apb [30:30] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_qspi_ref Reset selector: u0_qspi_ref [31:31] read-write true none De-assert reset. 0 reset Assert reset. 1 rst2 RESET 2 0x8 0x20 0xFFE7EFCC u0_sdio_ahb Reset selector: u0_sdio_ahb [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_sdi_ahb Reset selector: u1_sdi_ahb [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_gmac5_axi64 Reset selector: u1_gmac5_axi64 [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_gmac5_axi64_hresetn Reset selector: u1_gmac5_axi64_hresetn [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_mailbox_presetn Reset selector: u0_mailbox_presetn [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_spi_apb Reset selector: u0_spi_apb [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_spi_apb Reset selector: u1_spi_apb [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_spi_apb Reset selector: u2_spi_apb [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_spi_apb Reset selector: u3_spi_apb [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_spi_apb Reset selector: u4_spi_apb [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u5_spi_apb Reset selector: u5_spi_apb [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u6_spi_apb Reset selector: u6_spi_apb [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2c_apb Reset selector: u0_i2c_apb [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_i2c_apb Reset selector: u1_i2c_apb [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_i2c_apb Reset selector: u2_i2c_apb [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_i2c_apb Reset selector: u3_i2c_apb [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_i2c_apb Reset selector: u4_i2c_apb [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u5_i2c_apb Reset selector: u5_i2c_apb [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u6_i2c_apb Reset selector: u6_i2c_apb [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_uart_apb Reset selector: u0_uart_apb [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_uart_core Reset selector: u0_uart_core [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_uart_apb Reset selector: u1_uart_apb [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_uart_core Reset selector: u1_uart_core [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_uart_apb Reset selector: u2_uart_apb [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_uart_core Reset selector: u2_uart_core [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_uart_apb Reset selector: u3_uart_apb [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_uart_core Reset selector: u3_uart_core [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_uart_apb Reset selector: u4_uart_apb [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_uart_core Reset selector: u4_uart_core [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u5_uart_apb Reset selector: u5_uart_apb [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 u6_uart_core Reset selector: u6_uart_core [30:30] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_spdif_apb Reset selector: u0_spdif_apb [31:31] read-write true none De-assert reset. 0 reset Assert reset. 1 rst3 RESET 3 0xC 0x20 0x07FFFFFF u0_pwmdac_apb Reset selector: u0_pwmdac_apb [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pdm_4mic_dmic Reset selector: u0_pdm_4mic_dmic [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pdm_4mic_apb Reset selector: u0_pdm_4mic_apb [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2srx_apb Reset selector: u0_i2srx_apb [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2srx_bclk Reset selector: u0_i2srx_bclk [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2stx_apb Reset selector: u0_i2stx_apb [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2stx_bclk Reset selector: u0_i2stx_bclk [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_i2stx_apb Reset selector: u1_i2stx_apb [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_i2stx_bclk Reset selector: u1_i2stx_bclk [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_tdm16slot_ahb Reset selector: u0_tdm16slot_ahb [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_tdm16slot_tdm Reset selector: u0_tdm16slot_tdm [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_tdm16slot_apb Reset selector: u0_tdm16slot_apb [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pwm_apb Reset selector: u0_pwm_apb [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_dskit_wdt_rstn_apb Reset selector: u0_dskit_wdt_rstn_apb [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_dskit_wdt Reset selector: u0_dskit_wdt [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_can_ctrl_apb Reset selector: u0_can_ctrl_apb [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_can_ctrl Reset selector: u0_can_ctrl [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_can_ctrl_timer Reset selector: u0_can_ctrl_timer [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_can_ctrl_apb Reset selector: u1_can_ctrl_apb [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_can_ctrl_can Reset selector: u1_can_ctrl_can [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_can_ctrl_timer Reset selector: u1_can_ctrl_timer [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_apb Reset selector: u0_si5_timer_apb [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_0 Reset selector: u0_si5_timer_0 [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_1 Reset selector: u0_si5_timer_1 [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_2 Reset selector: u0_si5_timer_2 [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_3 Reset selector: u0_si5_timer_3 [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_int_ctrl_apb Reset selector: u0_int_ctrl_apb [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_temp_sensor_apb Reset selector: u0_temp_sensor_apb [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_temp_sensor Reset selector: u0_temp_sensor [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_jtag_rst Reset selector: u0_jtag_rst [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 syscrg_status SYSCRG RESET Status 0x10 rst0 RESET 0 0x0 0x20 0x00600001 u0_jtag2apb_presetn Reset selector: u0_jtag2apb_presetn [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_sys_syscon_presetn Reset selector: u0_sys_syscon_presetn [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_sys_iomux_presetn Reset selector: u0_sys_iomux_presetn [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_bus Reset selector: u0_bus [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_debug Reset selector: u0_debug [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_0 Reset selector: u0_core_0 [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_1 Reset selector: u0_core_1 [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_2 Reset selector: u0_core_2 [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_3 Reset selector: u0_core_3 [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_4 Reset selector: u0_core_4 [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_0 Reset selector: u0_core_st_0 [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_1 Reset selector: u0_core_st_1 [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_2 Reset selector: u0_core_st_2 [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_3 Reset selector: u0_core_st_3 [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_core_st_4 Reset selector: u0_core_st_4 [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_0 Reset selector: u0_trace_0 [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_1 Reset selector: u0_trace_1 [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_2 Reset selector: u0_trace_2 [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_3 Reset selector: u0_trace_3 [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_4 Reset selector: u0_trace_4 [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_trace_com Reset selector: u0_trace_com [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_img_gpu_apb Reset selector: u0_img_gpu_apb [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_img_gpu_doma Reset selector: u0_img_gpu_doma [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_apb Reset selector: u0_noc_bus_apb [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_axicfg0 Reset selector: u0_noc_bus_axicfg0 [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_cpu_axi Reset selector: u0_noc_bus_cpu_axi [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_disp_axi Reset selector: u0_noc_bus_disp_axi [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_gpu_axi Reset selector: u0_noc_bus_gpu_axi [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_isp_axi Reset selector: u0_noc_bus_isp_axi [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_ddrc Reset selector: u0_noc_bus_ddrc [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_stg_axi Reset selector: u0_noc_bus_stg_axi [30:30] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_noc_bus_vdec_axi Reset selector: u0_noc_bus_vdec_axi [31:31] read-write true none De-assert reset. 0 reset Assert reset. 1 rst1 RESET 1 0x4 0x20 0x07E7FE00 u0_noc_bus_venc_axi Reset selector: u0_noc_bus_venc_axi [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg1_dec_ahb Reset selector: u0_axi_cfg1_dec_ahb [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg1_dec_main Reset selector: u0_axi_cfg1_dec_main [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg0_dec_main Reset selector: u0_axi_cfg0_dec_main [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg0_dec_main_div Reset selector: u0_axi_cfg0_dec_main_div [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_axi_cfg0_dec_hifi4 Reset selector: u0_axi_cfg0_dec_hifi4 [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_ddr_axi Reset selector: u0_ddr_axi [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_ddr_osc Reset selector: u0_ddr_osc [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_ddr_apb Reset selector: u0_ddr_apb [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_isp_top Reset selector: u0_isp_top [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_isp_axi Reset selector: u0_isp_axi [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_vout_src Reset selector: u0_vout_src [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_codaj12_axi Reset selector: u0_codaj12_axi [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_codaj12_core Reset selector: u0_codaj12_core [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_codaj12_apb Reset selector: u0_codaj12_apb [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_axi Reset selector: u0_wave511_axi [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_bpu Reset selector: u0_wave511_bpu [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_vce Reset selector: u0_wave511_vce [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave511_apb Reset selector: u0_wave511_apb [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_vdec_jpg_arb Reset selector: u0_vdec_jpg_arb [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_vdec_jpg_arb_main Reset selector: u0_vdec_jpg_arb_main [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_aximem_128b_axi Reset selector: u0_aximem_128b_axi [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_axi Reset selector: u0_wave420l_axi [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_bpu Reset selector: u0_wave420l_bpu [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_vce Reset selector: u0_wave420l_vce [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_wave420l_apb Reset selector: u0_wave420l_apb [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_aximem Reset selector: u1_aximem [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_aximem Reset selector: u2_aximem [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_intmem_rom_sram Reset selector: u0_intmem_rom_sram [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_qspi_ahb Reset selector: u0_qspi_ahb [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_qspi_apb Reset selector: u0_qspi_apb [30:30] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_qspi_ref Reset selector: u0_qspi_ref [31:31] read-write true none De-assert reset. 0 reset Assert reset. 1 rst2 RESET 2 0x8 0x20 0xFFE7EFCC u0_sdio_ahb Reset selector: u0_sdio_ahb [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_sdi_ahb Reset selector: u1_sdi_ahb [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_gmac5_axi64 Reset selector: u1_gmac5_axi64 [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_gmac5_axi64_hresetn Reset selector: u1_gmac5_axi64_hresetn [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_mailbox_presetn Reset selector: u0_mailbox_presetn [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_spi_apb Reset selector: u0_spi_apb [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_spi_apb Reset selector: u1_spi_apb [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_spi_apb Reset selector: u2_spi_apb [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_spi_apb Reset selector: u3_spi_apb [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_spi_apb Reset selector: u4_spi_apb [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u5_spi_apb Reset selector: u5_spi_apb [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u6_spi_apb Reset selector: u6_spi_apb [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2c_apb Reset selector: u0_i2c_apb [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_i2c_apb Reset selector: u1_i2c_apb [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_i2c_apb Reset selector: u2_i2c_apb [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_i2c_apb Reset selector: u3_i2c_apb [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_i2c_apb Reset selector: u4_i2c_apb [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u5_i2c_apb Reset selector: u5_i2c_apb [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u6_i2c_apb Reset selector: u6_i2c_apb [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_uart_apb Reset selector: u0_uart_apb [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_uart_core Reset selector: u0_uart_core [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_uart_apb Reset selector: u1_uart_apb [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_uart_core Reset selector: u1_uart_core [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_uart_apb Reset selector: u2_uart_apb [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u2_uart_core Reset selector: u2_uart_core [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_uart_apb Reset selector: u3_uart_apb [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u3_uart_core Reset selector: u3_uart_core [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_uart_apb Reset selector: u4_uart_apb [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u4_uart_core Reset selector: u4_uart_core [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u5_uart_apb Reset selector: u5_uart_apb [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 u6_uart_core Reset selector: u6_uart_core [30:30] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_spdif_apb Reset selector: u0_spdif_apb [31:31] read-write true none De-assert reset. 0 reset Assert reset. 1 rst3 RESET 3 0xC 0x20 0x07FFFFFF u0_pwmdac_apb Reset selector: u0_pwmdac_apb [0:0] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pdm_4mic_dmic Reset selector: u0_pdm_4mic_dmic [1:1] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pdm_4mic_apb Reset selector: u0_pdm_4mic_apb [2:2] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2srx_apb Reset selector: u0_i2srx_apb [3:3] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2srx_bclk Reset selector: u0_i2srx_bclk [4:4] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2stx_apb Reset selector: u0_i2stx_apb [5:5] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_i2stx_bclk Reset selector: u0_i2stx_bclk [6:6] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_i2stx_apb Reset selector: u1_i2stx_apb [7:7] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_i2stx_bclk Reset selector: u1_i2stx_bclk [8:8] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_tdm16slot_ahb Reset selector: u0_tdm16slot_ahb [9:9] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_tdm16slot_tdm Reset selector: u0_tdm16slot_tdm [10:10] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_tdm16slot_apb Reset selector: u0_tdm16slot_apb [11:11] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_pwm_apb Reset selector: u0_pwm_apb [12:12] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_dskit_wdt_rstn_apb Reset selector: u0_dskit_wdt_rstn_apb [13:13] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_dskit_wdt Reset selector: u0_dskit_wdt [14:14] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_can_ctrl_apb Reset selector: u0_can_ctrl_apb [15:15] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_can_ctrl Reset selector: u0_can_ctrl [16:16] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_can_ctrl_timer Reset selector: u0_can_ctrl_timer [17:17] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_can_ctrl_apb Reset selector: u1_can_ctrl_apb [18:18] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_can_ctrl_can Reset selector: u1_can_ctrl_can [19:19] read-write true none De-assert reset. 0 reset Assert reset. 1 u1_can_ctrl_timer Reset selector: u1_can_ctrl_timer [20:20] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_apb Reset selector: u0_si5_timer_apb [21:21] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_0 Reset selector: u0_si5_timer_0 [22:22] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_1 Reset selector: u0_si5_timer_1 [23:23] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_2 Reset selector: u0_si5_timer_2 [24:24] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_si5_timer_3 Reset selector: u0_si5_timer_3 [25:25] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_int_ctrl_apb Reset selector: u0_int_ctrl_apb [26:26] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_temp_sensor_apb Reset selector: u0_temp_sensor_apb [27:27] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_temp_sensor Reset selector: u0_temp_sensor [28:28] read-write true none De-assert reset. 0 reset Assert reset. 1 u0_jtag_rst Reset selector: u0_jtag_rst [29:29] read-write true none De-assert reset. 0 reset Assert reset. 1 sys_syscon StarFive JH7110 SYS Syscon: sys_syscon 0x13030000 0x0 0x1000 registers sys_syscfg0 SYS SYSCONSAIF SYSCFG 0 0x0 0x20 0x00000000 e24_remap_haddr [3:0] read-write 0 15 hifi4_idma_remap_araddr [7:4] read-write 0 15 hifi4_idma_remap_awaddr [11:8] read-write 0 15 hifi4_sys_remap_araddr [15:12] read-write 0 15 hifi4_sys_remap_awaddr [19:16] read-write 0 15 jpg_remap_araddr [23:20] read-write 0 15 jpg_remap_awaddr [27:24] read-write 0 15 sd0_remap_araddr [31:28] read-write 0 15 sys_syscfg1 SYS SYSCONSAIF SYSCFG 4 0x4 0x20 0x00000000 sd1_remap_awaddr [3:0] read-write 0 15 sec_haddr_remap [7:4] read-write 0 15 usb_araddr_remap [11:8] read-write 0 15 usb_awaddr_remap [15:12] read-write 0 15 vdec_remap_awaddr [19:16] read-write 0 15 venc_remap_araddr [23:20] read-write 0 15 venc_remap_awaddr [27:24] read-write 0 15 vout0_remap_araddr [31:28] read-write 0 15 sys_syscfg2 SYS SYSCONSAIF SYSCFG 8 0x8 0x20 0x00000000 vout0_remap_awaddr [3:0] read-write 0 15 vout1_remap_araddr [7:4] read-write 0 15 vout1_remap_awaddr [11:8] read-write 0 15 sys_syscfg3 SYS SYSCONSAIF SYSCFG 12 0xC 0x20 0x00000000 vout0_remap_awaddr_gpio0 GPIO Group 0 (GPIO21-35) voltage select [0:0] read-write true select_33v GPIO Group 0 (GPIO21-35) voltage select 3.3V 0 select_18v GPIO Group 0 (GPIO21-35) voltage select 1.8V 1 vout0_remap_awaddr_gpio1 GPIO Group 1 (GPIO36-63) voltage select [1:1] read-write true select_33v GPIO Group 1 (GPIO36-63) voltage select 3.3V 0 select_18v GPIO Group 1 (GPIO36-63) voltage select 1.8V 1 vout0_remap_awaddr_gpio2 GPIO Group 2 (GPIO0-6) voltage select [2:2] read-write true select_33v GPIO Group 2 (GPIO0-6) voltage select 3.3V 0 select_18v GPIO Group 2 (GPIO0-6) voltage select 1.8V 1 vout0_remap_awaddr_gpio3 GPIO Group 3 (GPIO7-20) voltage select [3:3] read-write true select_33v GPIO Group 3 (GPIO7-20) voltage select 3.3V 0 select_18v GPIO Group 3 (GPIO7-20) voltage select 1.8V 1 sys_syscfg4 SYS SYSCONSAIF SYSCFG 16 0x10 0x20 0x00000000 coda12_cur_inst Tie 0 in JPU internal, do not care [1:0] read-only wave511_vpu_idle VPU monitoring signal [2:2] read-only can_ctrl_fd_enable_0 [3:3] read-write can_ctrl_host_ecc_disable_0 [4:4] read-write can_ctrl_host_if_0 [23:5] read-only qspi_sclk_dlychain_sel des_qspi_sclk_dla: clock delay [28:24] read-only sys_syscfg5 SYS SYSCONSAIF SYSCFG 20 0x14 0x20 0x00D54D54 u0_cdns_qspi_scfg_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [0:0] read-write u0_cdns_qspi_scfg_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [1:1] read-write u0_cdns_qspi_scfg_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [3:2] read-write u0_cdns_qspi_scfg_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [5:4] read-write u0_cdns_qspi_scfg_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [7:6] read-write u0_cdns_qspi_scfg_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write u0_cdns_qspi_scfg_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write u0_cdns_qspi_scfg_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write u0_cdns_spdif_scfg_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [12:12] read-write u0_cdns_spdif_scfg_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [13:13] read-write u0_cdns_spdif_scfg_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [15:14] read-write u0_cdns_spdif_scfg_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [17:16] read-write u0_cdns_spdif_scfg_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [19:18] read-write u0_cdns_spdif_scfg_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [21:20] read-write u0_cdns_spdif_scfg_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [22:22] read-write u0_cdns_spdif_scfg_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [23:23] read-write spdif_trmodeo SPDIF transfer mode [24:24] read-only true receiver SPDIF mode: receiver 0 transmitter SPDIF mode: transmitter 1 i2c_ic_en I2C interface enable [25:25] read-only sdio_data_strobe_phase_ctrl Data strobe delay chain select [30:26] read-write 0 31 sdio_hbig_endian AHB bus interface endianness [31:31] read-write true little_endian Little-endian AHB bus interface 0 big_endian Big-endian AHB bus interface 1 sys_syscfg6 SYS SYSCONSAIF SYSCFG 24 0x18 0x20 0x004DEA80 sdio_m_hbig_endian AHB master bus interface endianess [0:0] read-write true little_endian Little-endian AHB bus interface. 0 big_endian Big-endian AHB bus interface. 1 i2srx_adc_en I2S RX ADC enable [1:1] read-write intmem_rom_sram_scfg_disable_rom Internal Memory ROM SRAM SCFG Disable ROM [2:2] read-write intmem_rom_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [3:3] read-write intmem_rom_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [4:4] read-write intmem_rom_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [6:5] read-write intmem_rom_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [8:7] read-write intmem_rom_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [10:9] read-write intmem_rom_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [12:11] read-write intmem_rom_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [13:13] read-write intmem_rom_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [14:14] read-write 2 0x1 jtag_en[%s] JTAG daisy-chain enable [15:15] read-write pdrstn_split_sw_usbpipe_plugen PD RSTN Split Software USB Pipe Plug enable [17:17] read-write pll0_cpi_bias PLL0 CPI bias [20:18] read-write pll0_cpp_bias PLL0 CPP bias [23:21] read-write pll0_dacpd PLL0 DACPD. [24:24] read-write true off Disable PLL0 DACPD. 0 on Enable PLL0 DACPD. 1 pll0_dsmpd PLL0 DSMPD. [25:25] read-write true off Disable PLL0 DSMPD. 0 on Enable PLL0 DSMPD. 1 sys_syscfg7 SYS SYSCONSAIF SYSCFG 28 0x1C 0x20 0x00000053 pll0_fbdiv [11:0] read-write 0 4095 sys_syscfg8 SYS SYSCONSAIF SYSCFG 32 0x20 0x20 0x51555555 pll0_frac PLL0 frac value. [23:0] read-write 0 16777215 pll0_gvco_bias PLL0 GVCO bias. [25:24] read-write 0 3 pll0_lock PLL0 lock. [26:26] read-only pll0_pd PLL0 PD enable setting - driving the register low turns PD `on`. [27:27] read-write true on Enable the PLL0 PD. 0 off Disable the PLL0 PD. 1 pll0_postdiv1 PLL0 postdiv1 value. [29:28] read-write 0 3 pll0_postdiv2 PLL0 postdiv2 value. [31:30] read-write 0 3 sys_syscfg9 SYS SYSCONSAIF SYSCFG 36 0x24 0x20 0x00B02601 pll0_prediv [5:0] read-write 0 63 pll0_testen [6:6] read-write pll0_testsel [8:7] read-write 0 3 pll1_cpi_bias [11:9] read-write 0 7 pll1_cpp_bias [14:12] read-write 0 7 pll1_dacpd PLL1 DACPD. [15:15] read-write true off Disable PLL1 DACPD. 0 on Enable PLL1 DACPD. 1 pll1_dsmpd PLL1 DSMPD. [16:16] read-write true off Disable PLL1 DSMPD. 0 on Enable PLL1 DSMPD. 1 pll1_fbdiv [28:17] read-write 0 4095 sys_syscfg10 SYS SYSCONSAIF SYSCFG 40 0x28 0x20 0x51E00000 pll1_frac PLL1 frac value. [23:0] read-write 0 16777215 pll1_gvco_bias PLL1 GVCO bias. [25:24] read-write 0 3 pll1_lock PLL1 lock. [26:26] read-only pll1_pd PLL1 PD enable setting - driving the register low turns PD `on`. [27:27] read-write true on Enable the PLL0 PD 0 off Disable the PLL0 PD 1 pll1_postdiv1 PLL1 postdiv1 value. [29:28] read-write 0 3 pll1_postdiv2 PLL1 postdiv2 value. [31:30] read-write 0 3 sys_syscfg11 SYS SYSCONSAIF SYSCFG 44 0x2C 0x20 0x00662601 pll1_prediv PLL1 prediv value. [5:0] read-write 0 63 pll1_testen PLL1 test enable. [6:6] read-write pll1_testsel PLL1 test selector. [8:7] read-write 0 3 pll2_cpi_bias PLL2 CPI bias. [11:9] read-write 0 7 pll2_cpp_bias PLL2 CPP bias. [14:12] read-write 0 7 pll2_dacpd PLL2 DACPD. [15:15] read-write true off Disable PLL2 DACPD. 0 on Enable PLL2 DACPD. 1 pll2_dsmpd PLL2 DSMPD. [16:16] read-write true off Disable PLL2 DSMPD. 0 on Enable PLL2 DSMPD. 1 pll2_fbdiv PLL2 fbdiv value. [28:17] read-write 0 4095 sys_syscfg12 SYS SYSCONSAIF SYSCFG 48 0x30 0x20 0x41333333 pll2_frac PLL2 frac value. [23:0] read-write 0 16777215 pll2_gvco_bias PLL2 GVCO bias. [25:24] read-write 0 3 pll2_lock PLL2 lock. [26:26] read-only pll2_pd PLL2 PD enable setting - driving the register low turns PD `on`. [27:27] read-write true on Enable the PLL2 PD. 0 off Disable the PLL2 PD. 1 pll2_postdiv1 PLL2 postdiv1 value. [29:28] read-write 0 3 pll2_postdiv2 PLL2 postdiv2 value. [31:30] read-write 0 3 sys_syscfg13 SYS SYSCONSAIF SYSCFG 52 0x34 0x20 0x00000001 pll2_prediv [5:0] read-write 0 63 pll2_testen [6:6] read-write pll2_testsel [8:7] read-write 0 3 pll_test_mode PLL test mode, only used for PLL BIST through jtag2apb [9:9] read-write audio_i2sdin_sel [17:10] read-write 0 255 noc_bus_clock_gating_off [18:18] read-write noc_bus_oic_evemon_start0 [19:19] read-write noc_bus_oic_evemon_trigger0 [20:20] read-only noc_bus_oic_evemon_start1 [21:21] read-write noc_bus_oic_evemon_trigger1 [22:22] read-only noc_bus_oic_evemon_start2 [23:23] read-write noc_bus_oic_evemon_trigger2 [24:24] read-only noc_bus_oic_evemon_start3 [25:25] read-write noc_bus_oic_evemon_trigger3 [26:26] read-only noc_bus_oic_evemon_start4 [27:27] read-write noc_bus_oic_evemon_trigger4 [28:28] read-only noc_bus_oic_evemon_start5 [29:29] read-write noc_bus_oic_evemon_trigger5 [30:30] read-only noc_bus_oic_evemon_start6 [31:31] read-write sys_syscfg14 SYS SYSCONSAIF SYSCFG 56 0x38 0x20 0x00000000 noc_bus_oic_evemon_trigger6 [0:0] read-only noc_bus_oic_ignore_modifiable_0 [5:5] read-write noc_bus_oic_ignore_modifiable_1 [6:6] read-write noc_bus_oic_ignore_modifiable_2 [7:7] read-write noc_bus_oic_ignore_modifiable_3 [8:8] read-write noc_bus_oic_ignore_modifiable_4 [9:9] read-write noc_bus_oic_evemon_start7 [15:15] read-write noc_bus_oic_evemon_trigger7 [16:16] read-only noc_bus_oic_evemon_start8 [17:17] read-write noc_bus_oic_evemon_trigger8 [18:18] read-only 9 0x4 sys_syscfg_noc_bus_oic_qch_clock_stop[%s] SYS SYSCONSAIF SYSCFG 60 - 92: NOC Bus OIC QCH Clock Stop Threshold registers. 0x3C 0x20 0x00000000 threshold [31:0] read-write 0 4294967295 sys_syscfg24 SYS SYSCONSAIF SYSCFG 96 0x60 0x20 0x00000000 tdm1616slot_clkpol [0:0] read-only tdm1616slot_pcm_ms [1:1] read-only u0_trace_mtx_in0_c0 [6:2] read-write u0_trace_mtx_in1_c0 [11:7] read-write u0_trace_mtx_in0_c1 [16:12] read-write u0_trace_mtx_in1_c1 [21:17] read-write u0_trace_mtx_in0_c2 [26:22] read-write u0_trace_mtx_in1_c2 [31:27] read-write sys_syscfg25 SYS SYSCONSAIF SYSCFG 96 0x64 0x20 0x00000000 u0_trace_mtx_scfg_in0_c3 [6:2] read-write 0 31 u0_trace_mtx_scfg_in1_c3 [11:7] read-write 0 31 u0_trace_mtx_scfg_in0_c4 [16:12] read-write 0 31 u0_trace_mtx_scfg_in1_c4 [21:17] read-write 0 31 u0_cease_from_tile0 [20:20] read-only u0_cease_from_tile1 [21:21] read-only u0_cease_from_tile2 [22:22] read-only u0_cease_from_tile3 [23:23] read-only u0_cease_from_tile4 [24:24] read-only u0_halt_from_tile0 [25:25] read-only u0_halt_from_tile1 [26:26] read-only u0_halt_from_tile2 [27:27] read-only u0_halt_from_tile3 [28:28] read-only u0_halt_from_tile4 [29:29] read-only sys_syscfg_reset_vector SYS SYSCONSAIF SYSCFG 104 - 128: Reset Vector registers. 0x68 3 0x8 _1,_2,_3 reset_vector_35_0[%s] Reset vector cluster of 36 vector fields 0x0 reset_vector_31_0 Reset vector register with 32 vector fields 0x0 0x20 0x2A000000 vectors Reset vector bits [31:0] read-write 0 4294967295 reset_vector_35_32 Reset vector register with 4 vector fields 0x4 0x20 0x00000000 vectors Reset vector bits [3:0] read-write 0 15 reset_vector_31_0_4 Reset vector register with 32 vector fields 0x18 0x20 0x2A000000 vectors Reset vector bits [31:0] read-write 0 4294967295 sys_syscfg33 SYS SYSCONSAIF SYSCFG 132 0x84 0x20 0x01AA8000 reset_vector_35_32_4 Reset vector bits [3:0] read-write 0 15 u0_suppress_fetch1 [4:4] read-write u0_suppress_fetch2 [5:5] read-write u0_suppress_fetch3 [6:6] read-write u0_suppress_fetch4 [7:7] read-write u0_wfi_from_tile0 [8:8] read-write u0_wfi_from_tile1 [9:9] read-write u0_wfi_from_tile2 [10:10] read-write u0_wfi_from_tile3 [11:11] read-write u0_wfi_from_tile4 [12:12] read-write u0_vdec_int_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [13:13] read-write u0_vdec_int_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [14:14] read-write u0_vdec_int_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [16:15] read-write u0_vdec_int_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [18:17] read-write u0_vdec_int_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [20:19] read-write u0_vdec_int_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [22:21] read-write u0_vdec_int_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [23:23] read-write u0_vdec_int_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [24:24] read-write sys_syscfg34 SYS SYSCONSAIF SYSCFG 136 0x88 0x20 0x00000D54 u0_venc_int_sram_config_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [0:0] read-write u0_venc_int_sram_config_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [1:1] read-write u0_venc_int_sram_config_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [3:2] read-write u0_venc_int_sram_config_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [5:4] read-write u0_venc_int_sram_config_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [7:6] read-write u0_venc_int_sram_config_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write u0_venc_int_sram_config_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write u0_venc_int_sram_config_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write wave420l_ipu_current_buffer This signal indicates which buffer is currently active so that the VPU can correctly use the ipu_end_of_row signal for row counter. [14:12] read-write 0 7 wave420l_ipu_end_of_row This signal is flipped every time when the IPU completes writing a row. [15:15] read-write wave420l_ipu_new_frame This signal is flipped every time when the IPU completes writing a new frame. [16:16] read-write wave420l_vpu_idle VPU monitoring signal. This signal gives out an opposite value of VPU_BUSY register. [17:17] read-only can_ctrl_fd_enable_1 [18:18] read-write can_ctrl_host_ecc_disable_1 [19:19] read-write sys_syscfg35 SYS SYSCONSAIF SYSCFG 140 0x8C 0x20 0x6AA00000 can_ctrl_host_if_1 [18:0] read-only u1_gmac5_axi64_scfg_ram_cfg_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [19:19] read-write u1_gmac5_axi64_scfg_ram_cfg_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [20:20] read-write u1_gmac5_axi64_scfg_ram_cfg_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [22:21] read-write u1_gmac5_axi64_scfg_ram_cfg_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [24:23] read-write u1_gmac5_axi64_scfg_ram_cfg_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [26:25] read-write u1_gmac5_axi64_scfg_ram_cfg_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [28:27] read-write u1_gmac5_axi64_scfg_ram_cfg_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [29:29] read-write u1_gmac5_axi64_scfg_ram_cfg_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [30:30] read-write sys_syscfg36 SYS SYSCONSAIF SYSCFG 144 0x90 0x20 0x00000004 gmac5_axi64_mac_speed [1:0] read-only gmac5_axi64_phy_intf_sel Active PHY Selected | When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. [4:2] read-write true gmii Active PHY Selected: GMII or MII, None 0 rgmii Active PHY Selected: RGMII 1 sgmii Active PHY Selected: SGMII 2 tbi Active PHY Selected: TBI 3 rmii Active PHY Selected: RMII 4 rtbi Active PHY Selected: RTBI 5 smii Active PHY Selected: SMII 6 revmii Active PHY Selected: REVMII 7 sys_syscfg37 SYS SYSCONSAIF SYSCFG 148 0x94 0x20 0x00000000 gmac5_axi64_ptp_timestamp_31_0 [31:0] read-only sys_syscfg38 SYS SYSCONSAIF SYSCFG 152 0x98 0x20 0x00000000 gmac5_axi64_ptp_timestamp_63_32 [31:0] read-only sys_syscfg39 SYS SYSCONSAIF SYSCFG 156 0x9C 0x20 0x00000400 u1_i2c_ic_en I2C interface enable. [0:0] read-only u1_sdio_data_strobe_phase_ctrl Data strobe delay chain select. [5:1] read-write 0 31 u1_sdio_hbig_endian AHB bus interface endianness [6:6] read-write true little_endian Little-endian AHB bus interface 0 big_endian Big-endian AHB bus interface 1 u1_sdio_m_hbig_endian AHB bus interface endianness [7:7] read-write true little_endian Little-endian AHB bus interface 0 big_endian Big-endian AHB bus interface 1 u1_reset_ctrl_clr_reset_status [8:8] read-write u1_reset_ctrl_pll_timecnt_finish [9:9] read-only u1_reset_ctrl_rstn_sw [10:10] read-write u1_reset_ctrl_sys_reset_status [14:11] read-only u2_i2c_ic_en I2C interface enable. [15:15] read-only u3_i2c_ic_en I2C interface enable. [16:16] read-only u4_i2c_ic_en I2C interface enable. [17:17] read-only u5_i2c_ic_en I2C interface enable. [18:18] read-only u6_i2c_ic_en I2C interface enable. [19:19] read-only sys_pinctrl StarFive JH7110 SYS Pinctrl: sys_pinctrl 0x13040000 0x0 0x10000 registers SYS_IOMUX 86 gpo_doen The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. 0x0 gpo_doen0 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOEN 0x0 0x20 0x08010101 doen0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen1 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOEN 0x4 0x20 0x00010001 doen4 The selected OEN signal for GPIO4. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen5 The selected OEN signal for GPIO5. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen6 The selected OEN signal for GPIO6. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen7 The selected OEN signal for GPIO7. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen2 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOEN 0x8 0x20 0x07010100 doen8 The selected OEN signal for GPIO8. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen9 The selected OEN signal for GPIO9. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen10 The selected OEN signal for GPIO10. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen11 The selected OEN signal for GPIO11. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen3 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOEN 0xC 0x20 0x00000101 doen12 The selected OEN signal for GPIO12. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen13 The selected OEN signal for GPIO13. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen14 The selected OEN signal for GPIO14. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen15 The selected OEN signal for GPIO15. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen4 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOEN 0x10 0x20 0x01000000 doen16 The selected OEN signal for GPIO16. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen17 The selected OEN signal for GPIO17. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen18 The selected OEN signal for GPIO18. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen19 The selected OEN signal for GPIO19. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen5 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOEN 0x14 0x20 0x00000000 doen20 The selected OEN signal for GPIO20. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen21 The selected OEN signal for GPIO21. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen22 The selected OEN signal for GPIO22. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen23 The selected OEN signal for GPIO23. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen6 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOEN 0x18 0x20 0x00000000 doen24 The selected OEN signal for GPIO24. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen25 The selected OEN signal for GPIO25. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen26 The selected OEN signal for GPIO26. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen27 The selected OEN signal for GPIO27. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen7 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOEN 0x1C 0x20 0x00000000 doen28 The selected OEN signal for GPIO28. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen29 The selected OEN signal for GPIO29. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen30 The selected OEN signal for GPIO30. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen31 The selected OEN signal for GPIO31. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen8 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOEN 0x20 0x20 0x00000000 doen32 The selected OEN signal for GPIO32. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen33 The selected OEN signal for GPIO33. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen34 The selected OEN signal for GPIO34. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen35 The selected OEN signal for GPIO35. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen9 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOEN 0x24 0x20 0x23220605 doen36 The selected OEN signal for GPIO36. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen37 The selected OEN signal for GPIO37. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen38 The selected OEN signal for GPIO38. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen39 The selected OEN signal for GPIO39. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen10 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOEN 0x28 0x20 0x01000001 doen40 The selected OEN signal for GPIO40. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen41 The selected OEN signal for GPIO41. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen42 The selected OEN signal for GPIO42. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen43 The selected OEN signal for GPIO43. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen11 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOEN 0x2C 0x20 0x01000001 doen44 The selected OEN signal for GPIO44. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen45 The selected OEN signal for GPIO45. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen46 The selected OEN signal for GPIO46. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen47 The selected OEN signal for GPIO47. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen12 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOEN 0x30 0x20 0x0E010D0D doen48 The selected OEN signal for GPIO48. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen49 The selected OEN signal for GPIO49. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen50 The selected OEN signal for GPIO50. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen51 The selected OEN signal for GPIO51. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen13 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOEN 0x34 0x20 0x1D011C1C doen52 The selected OEN signal for GPIO52. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen53 The selected OEN signal for GPIO53. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen54 The selected OEN signal for GPIO54. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen55 The selected OEN signal for GPIO55. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen14 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOEN 0x38 0x20 0x25012424 doen56 The selected OEN signal for GPIO56. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen57 The selected OEN signal for GPIO57. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen58 The selected OEN signal for GPIO58. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen59 The selected OEN signal for GPIO59. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_doen15 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOEN 0x3C 0x20 0x29012828 doen60 The selected OEN signal for GPIO60. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [5:0] read-write 0 63 doen61 The selected OEN signal for GPIO61. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [13:8] read-write 0 63 doen62 The selected OEN signal for GPIO62. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [21:16] read-write 0 63 doen63 The selected OEN signal for GPIO63. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-49. See Table 2-41: GPIO OEN List for SYS_IOMUX (on page 97) for more information. [29:24] read-write 0 63 gpo_dout SYS IOMUX CFG SAIF SYSCFG FMUX GPIO DOUT - The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. 0x40 gpo_dout0 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 0-3 DOUT 0x0 0x20 0x16000000 dout0 The selected output signal for GPIO0. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout1 The selected output signal for GPIO1. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout2 The selected output signal for GPIO2. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout3 The selected output signal for GPIO3. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout1 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 4-7 DOUT 0x4 0x20 0x00001400 dout4 The selected output signal for GPIO4. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout5 The selected output signal for GPIO5. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout6 The selected output signal for GPIO6. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout7 The selected output signal for GPIO7. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout2 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 8-11 DOUT 0x8 0x20 0x15000000 dout8 The selected output signal for GPIO8. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout9 The selected output signal for GPIO9. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout10 The selected output signal for GPIO10. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout11 The selected output signal for GPIO11. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout3 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 12-15 DOUT 0xC 0x20 0x00000000 dout12 The selected output signal for GPIO12. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout13 The selected output signal for GPIO13. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout14 The selected output signal for GPIO14. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout15 The selected output signal for GPIO15. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout4 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 16-19 DOUT 0x10 0x20 0x20000000 dout16 The selected output signal for GPIO16. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout17 The selected output signal for GPIO17. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout18 The selected output signal for GPIO18. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout19 The selected output signal for GPIO19. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout5 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 20-23 DOUT 0x14 0x20 0x00550000 dout20 The selected output signal for GPIO20. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout21 The selected output signal for GPIO21. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout22 The selected output signal for GPIO22. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout23 The selected output signal for GPIO23. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout6 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 24-27 DOUT 0x18 0x20 0x00000000 dout24 The selected output signal for GPIO24. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout25 The selected output signal for GPIO25. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout26 The selected output signal for GPIO26. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout27 The selected output signal for GPIO27. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout7 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 28-31 DOUT 0x1C 0x20 0x00000000 dout28 The selected output signal for GPIO28. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout29 The selected output signal for GPIO29. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout30 The selected output signal for GPIO30. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout31 The selected output signal for GPIO31. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout8 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 32-35 DOUT 0x20 0x20 0x0D000000 dout32 The selected output signal for GPIO32. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout33 The selected output signal for GPIO33. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout34 The selected output signal for GPIO34. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout35 The selected output signal for GPIO35. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout9 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 36-39 DOUT 0x24 0x20 0x54530F0E dout36 The selected output signal for GPIO36. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout37 The selected output signal for GPIO37. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout38 The selected output signal for GPIO38. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout39 The selected output signal for GPIO39. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout10 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 40-43 DOUT 0x28 0x20 0x004E4F00 dout40 The selected output signal for GPIO40. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout41 The selected output signal for GPIO41. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout42 The selected output signal for GPIO42. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout43 The selected output signal for GPIO43. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout11 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 44-47 DOUT 0x2C 0x20 0x005B5C00 dout44 The selected output signal for GPIO44. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout45 The selected output signal for GPIO45. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout46 The selected output signal for GPIO46. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout47 The selected output signal for GPIO47. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout12 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 48-51 DOUT 0x30 0x20 0x20001E1F dout48 The selected output signal for GPIO48. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout49 The selected output signal for GPIO49. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout50 The selected output signal for GPIO50. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout51 The selected output signal for GPIO51. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout13 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 52-55 DOUT 0x34 0x20 0x4B00494A dout52 The selected output signal for GPIO52. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout53 The selected output signal for GPIO53. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout54 The selected output signal for GPIO54. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout55 The selected output signal for GPIO55. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout14 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 56-59 DOUT 0x38 0x20 0x58005657 dout56 The selected output signal for GPIO56. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout57 The selected output signal for GPIO57. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout58 The selected output signal for GPIO58. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout59 The selected output signal for GPIO59. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpo_dout15 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO 60-63 DOUT 0x3C 0x20 0x5F005D5E dout60 The selected output signal for GPIO60. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [6:0] read-write 0 127 dout61 The selected output signal for GPIO61. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [14:8] read-write 0 127 dout62 The selected output signal for GPIO62. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [22:16] read-write 0 127 dout63 The selected output signal for GPIO63. The register value indicates the selected GPIO (Digital Output) DOUT index from GPIO DOUT list 0-49. See Table 2-41: GPIO DOUT List for SYS_IOMUX (on page 97) for more information. [30:24] read-write 0 127 gpi The register can be used to configure the selected GPIO connector number for input signals. The signal name is indicated in the "Name" column of the following table per StarFive naming conventions. For example, name "u0_WAVE511_i_uart_rxsin_cfg" indicates the corresponding input signal is "u0_WAVE511.i_uart_rxsin". See GPIO Input Signals (on page 107) for a complete list of the input GPIO signals. 0x80 gpi0 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [wave511_uart_rxsin, can_rxd_0, usb_over_current, spdif_spdi_fi] 0x0 0x20 0x00000000 wave511_uart_rxsin The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 can_rxd_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 usb_over_current The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 spdif_spdi_fi The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi1 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [jtag_trstn, hdmi_cec_sda, hdmi_ddc_scl, hdmi_ddc_sda] 0x4 0x20 0x00000002 jtag_trstn The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 hdmi_cec_sda The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 hdmi_ddc_scl The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 hdmi_ddc_sda The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi2 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [hdmi_hpd, i2c_clk_0, i2c_data_0, sdio_detect_0] 0x8 0x20 0x00272600 hdmi_hpd The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 i2c_clk_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 i2c_data_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 sdio_detect_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi3 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [sdio_int_0, sdio_write_prt_0, uart_sin_0, hifi4_jtck_0] 0xC 0x20 0x0B080000 sdio_int_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 sdio_write_prt_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 uart_sin_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 hifi4_jtck_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi4 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [hifi4_jtdi, hifi4_jtms, hifi4_jtrstn, jtag_tdi] 0x10 0x20 0x040F0E0C hifi4_jtdi The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 hifi4_jtms The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 hifi4_jtrstn The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 jtag_tdi The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi5 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [jtag_tms, pdm_dmic_0, pdm_dmic_1, audio_i2srx_0] 0x14 0x20 0x00000006 jtag_tms The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 pdm_dmic_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 pdm_dmic_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 audio_i2srx_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi6 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [audio_i2srx_1, audio_i2srx_2, spi_clkin_0, spi_fssin_0] 0x18 0x20 0x32330000 audio_i2srx_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 audio_i2srx_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 spi_clkin_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 spi_fssin_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi7 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [spi_rxd_0, jtag_tck, mclk, i2srx_bclk_slv_0] 0x1C 0x20 0x00000334 spi_rxd_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 jtag_tck The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 mclk The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 i2srx_bclk_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi8 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [i2srx_lrck_slv_0, i2stx_bclk_slv_0, i2stx_lrck_slv_0, tdm_clk_slv_0] 0x20 0x20 0x00000000 i2srx_lrck_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 i2stx_bclk_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 i2stx_lrck_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 tdm_clk_slv_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi9 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [pcm_rxd_0, pcm_synon_0, can_rxd_1, i2c_clk_1] 0x24 0x20 0x00000000 pcm_rxd_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 pcm_synon_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 can_rxd_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 i2c_clk_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi10 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [i2c_data_1, sdio_detect_1, sdio_int_1, sdio_write_prt_1] 0x28 0x20 0x00000000 i2c_data_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 sdio_detect_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 sdio_int_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 sdio_write_prt_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi11 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [sdio_ccmd_1, sdio_cdata_0, sdio_cdata_1, sdio_cdata_2] 0x2C 0x20 0x00000000 sdio_ccmd_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 sdio_cdata_0 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 sdio_cdata_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 sdio_cdata_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi12 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [sdio_cdata_3, sdio_cdata_4, sdio_cdata_5, sdio_cdata_6] 0x30 0x20 0x00000000 sdio_cdata_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 sdio_cdata_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 sdio_cdata_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 sdio_cdata_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi13 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [sdio_cdata_7, sdio_data_strobe, uart_cts_1, uart_sin_1] 0x34 0x20 0x00000000 sdio_cdata_7 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 sdio_data_strobe The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 uart_cts_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 uart_sin_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi14 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [spi_clkin_1, spi_fssin_1, spi_rxd_1, i2c_clk_2] 0x38 0x20 0x00383637 spi_clkin_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 spi_fssin_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 spi_rxd_1 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 i2c_clk_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi15 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [i2c_data_2, uart_cts_2, uart_sin_2, spi_clkin_2] 0x3C 0x20 0x002A2D00 i2c_data_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 uart_cts_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 uart_sin_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 spi_clkin_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi16 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [spi_fssin_2, spi_rxd_2, i2c_clk_3, i2c_data_3] 0x40 0x20 0x29280000 spi_fssin_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 spi_rxd_2 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 i2c_clk_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 i2c_data_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi17 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [uart_sin_3, spi_clkin_3, spi_fssin_3, spi_rxd_3] 0x44 0x20 0x3C3A3B15 uart_sin_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 spi_clkin_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 spi_fssin_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 spi_rxd_3 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi18 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [i2c_clk_4, i2c_data_4, uart_cts_4, uart_sin_4] 0x48 0x20 0x2E310000 i2c_clk_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 i2c_data_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 uart_cts_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 uart_sin_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi19 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [spi_clkin_4, spi_fssin_4, spi_rxd_4, i2c_clk_5] 0x4C 0x20 0x00403E3F spi_clkin_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 spi_fssin_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 spi_rxd_4 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 i2c_clk_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi20 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [i2c_data_5, uart_cts_5, uart_sin_5, spi_clkin_5] 0x50 0x20 0x00000000 i2c_data_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 uart_cts_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 uart_sin_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 spi_clkin_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi21 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [spi_fssin_5, spi_rxd_5, i2c_clk_6, i2c_data_6] 0x54 0x20 0x00000000 spi_fssin_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 spi_rxd_5 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 i2c_clk_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 i2c_data_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [30:24] read-write 0 127 gpi22 SYS IOMUX CFG SAIF SYSCFG FMUX GPIO GPI: [spi_clkin_6, spi_fssin_6, spi_rxd_6] 0x58 0x20 0x00000000 spi_clkin_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [6:0] read-write 0 127 spi_fssin_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [14:8] read-write 0 127 spi_rxd_6 The register value indicates the selected GPIO number + 2 (GPIO2 - GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [22:16] read-write 0 127 ioirq GPIO Interrupt Request configuration 0xDC ioirq0 Enable IRQ function 0x0 0x20 0x00000000 gpen0 1: Enable, 0: Disable [0:0] read-write true disable GPIO IRQ function: disable 0 enable GPIO IRQ function: enable 1 ioirq1 SYS IOMUX CFGSAIF SYSCFG IOIRQ 4: GPIO Interrupt Edge Trigger Selector 0x4 0x20 0x00000000 is0 1: Edge trigger, 0: Level trigger [0:0] read-write true level GPIO interrupt trigger selector: level 0 edge GPIO interrupt trigger selector: edge 1 ioirq2 SYS IOMUX CFGSAIF SYSCFG IOIRQ 8: GPIO Interrupt Edge Trigger Selector 0x8 0x20 0x00000000 is1 1: Edge trigger, 0: Level trigger [0:0] read-write true level GPIO interrupt trigger selector: level 0 edge GPIO interrupt trigger selector: edge 1 ioirq3 SYS IOMUX CFGSAIF SYSCFG IOIRQ 12: GPIO Interrupt Clear 0xC 0x20 0x00000000 ic0 1: Do not clear the register, 0: Clear the register [0:0] read-write true clear GPIO interrupt clear 0 not_clear GPIO interrupt do not clear 1 ioirq4 SYS IOMUX CFGSAIF SYSCFG IOIRQ 16: GPIO Interrupt Clear 0x10 0x20 0x00000000 ic1 1: Do not clear the register, 0: Clear the register [0:0] read-write true clear GPIO interrupt clear 0 not_clear GPIO interrupt do not clear 1 ioirq5 SYS IOMUX CFGSAIF SYSCFG IOIRQ 20: GPIO Interrupt Both Edge Trigger Selector 0x14 0x20 0x00000000 ibe0 1: Trigger on both edges, 0: Trigger on a single edge [0:0] read-write true single_edge GPIO interrupt trigger edge selector: single edge 0 both_edges GPIO interrupt trigger edge selector: both edges 1 ioirq6 SYS IOMUX CFGSAIF SYSCFG IOIRQ 24: GPIO Interrupt Both Edge Trigger Selector 0x18 0x20 0x00000000 ibe1 1: Trigger on both edges, 0: Trigger on a single edge [0:0] read-write true single_edge GPIO interrupt trigger edge selector: single edge 0 both_edges GPIO interrupt trigger edge selector: both edges 1 ioirq7 SYS IOMUX CFGSAIF SYSCFG IOIRQ 28: GPIO Interrupt Edge Value 0x1C 0x20 0x00000000 iev0 1: Positive/Low, 0: Negative/High [0:0] read-write true negative_high GPIO interrupt edge value: negative/high 0 positive_low GPIO interrupt edge value: positive/low 1 ioirq8 SYS IOMUX CFGSAIF SYSCFG IOIRQ 32: GPIO Interrupt Edge Value 0x20 0x20 0x00000000 iev1 1: Positive/Low, 0: Negative/High [0:0] read-write true negative_high GPIO interrupt edge value: negative/high 0 positive_low GPIO interrupt edge value: positive/low 1 ioirq9 SYS IOMUX CFGSAIF SYSCFG IOIRQ 36: GPIO Interrupt Edge Mask Selector 0x24 0x20 0x00000000 ie0 1: Unmask, 0: Mask [0:0] read-write true mask GPIO interrupt edge mask: mask 0 unmask GPIO interrupt edge mask: unmask 1 ioirq10 SYS IOMUX CFGSAIF SYSCFG IOIRQ 40: GPIO Interrupt Edge Mask Selector 0x28 0x20 0x00000000 ie1 1: Unmask, 0: Mask [0:0] read-write true mask GPIO interrupt edge mask: mask 0 unmask GPIO interrupt edge mask: unmask 1 ioirq11 SYS IOMUX CFGSAIF SYSCFG IOIRQ 44: GPIO Register Interrupt Status 0x2C 0x20 0x00000000 32 0x1 _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,_17,_18,_19,_20,_21,_22,_23,_24,_25,_26,_27,_28,_29,_30,_31 ris0[%s] Status of the edge trigger. The register can be cleared by writing gpio ic [0:0] read-only true clear GPIO raw interrupt status: clear 0 set GPIO raw interrupt status: set 1 ioirq12 SYS IOMUX CFGSAIF SYSCFG IOIRQ 48: GPIO Register Interrupt Status 0x30 0x20 0x00000000 32 0x1 _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,_17,_18,_19,_20,_21,_22,_23,_24,_25,_26,_27,_28,_29,_30,_31 ris1[%s] Status of the edge trigger. The register can be cleared by writing gpio ic [0:0] read-only true clear GPIO raw interrupt status: clear 0 set GPIO raw interrupt status: set 1 ioirq13 SYS IOMUX CFGSAIF SYSCFG IOIRQ 52: GPIO Masked Interrupt Status 0x34 0x20 0x00000000 32 0x1 _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,_17,_18,_19,_20,_21,_22,_23,_24,_25,_26,_27,_28,_29,_30,_31 mis0[%s] The masked GPIO IRQ status [0:0] read-only true clear GPIO masked interrupt status: clear 0 set GPIO masked interrupt status: set 1 ioirq14 SYS IOMUX CFGSAIF SYSCFG IOIRQ 56: GPIO Masked Interrupt Status 0x38 0x20 0x00000000 32 0x1 _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,_17,_18,_19,_20,_21,_22,_23,_24,_25,_26,_27,_28,_29,_30,_31 mis1[%s] The masked GPIO IRQ status [0:0] read-only true clear GPIO masked interrupt status: clear 0 set GPIO masked interrupt status: set 1 ioirq15 SYS IOMUX CFGSAIF SYSCFG IOIRQ 60: GPIO Synchronization Status 0x3C 0x20 0x00000000 32 0x1 _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,_17,_18,_19,_20,_21,_22,_23,_24,_25,_26,_27,_28,_29,_30,_31 in_sync2_0[%s] Status of the gpio_in after synchronization [0:0] read-only true not_synced GPIO status of gpio_in after synchonization: not synced 0 synced GPIO status of gpio_in after synchonization: synced 1 ioirq16 SYS IOMUX CFGSAIF SYSCFG IOIRQ 64: GPIO Synchronization Status 0x40 0x20 0x00000000 32 0x1 _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11,_12,_13,_14,_15,_16,_17,_18,_19,_20,_21,_22,_23,_24,_25,_26,_27,_28,_29,_30,_31 in_sync2_1[%s] Status of the gpio_in after synchronization [0:0] read-only true not_synced GPIO status of gpio_in after synchonization: not synced 0 synced GPIO status of gpio_in after synchonization: synced 1 padcfg SYS IOMUX CFG SAIF SYSCFG PADCFG: GPIO pad configuration 0x120 gpio0 SYS IOMUX CFG SAIF SYSCFG PADCFG 288: GPIO0 0x0 0x20 0x00000011 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio1 SYS IOMUX CFG SAIF SYSCFG PADCFG 292: GPIO1 0x4 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio2 SYS IOMUX CFG SAIF SYSCFG PADCFG 296: GPIO2 0x8 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio3 SYS IOMUX CFG SAIF SYSCFG PADCFG 300: GPIO3 0xC 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio4 SYS IOMUX CFG SAIF SYSCFG PADCFG 304: GPIO4 0x10 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio5 SYS IOMUX CFG SAIF SYSCFG PADCFG 308: GPIO5 0x14 0x20 0x00000000 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio6 SYS IOMUX CFG SAIF SYSCFG PADCFG 312: GPIO6 0x18 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio7 SYS IOMUX CFG SAIF SYSCFG PADCFG 316: GPIO7 0x1C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio8 SYS IOMUX CFG SAIF SYSCFG PADCFG 320: GPIO8 0x20 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio9 SYS IOMUX CFG SAIF SYSCFG PADCFG 324: GPIO9 0x24 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio10 SYS IOMUX CFG SAIF SYSCFG PADCFG 328: GPIO10 0x28 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio11 SYS IOMUX CFG SAIF SYSCFG PADCFG 332: GPIO11 0x2C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio12 SYS IOMUX CFG SAIF SYSCFG PADCFG 336: GPIO12 0x30 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio13 SYS IOMUX CFG SAIF SYSCFG PADCFG 340: GPIO13 0x34 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio14 SYS IOMUX CFG SAIF SYSCFG PADCFG 344: GPIO14 0x38 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio15 SYS IOMUX CFG SAIF SYSCFG PADCFG 348: GPIO15 0x3C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio16 SYS IOMUX CFG SAIF SYSCFG PADCFG 352: GPIO16 0x40 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio17 SYS IOMUX CFG SAIF SYSCFG PADCFG 356: GPIO17 0x44 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio18 SYS IOMUX CFG SAIF SYSCFG PADCFG 360: GPIO18 0x48 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio19 SYS IOMUX CFG SAIF SYSCFG PADCFG 364: GPIO19 0x4C 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio20 SYS IOMUX CFG SAIF SYSCFG PADCFG 368: GPIO20 0x50 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio21 SYS IOMUX CFG SAIF SYSCFG PADCFG 372: GPIO21 0x54 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio22 SYS IOMUX CFG SAIF SYSCFG PADCFG 376: GPIO22 0x58 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio23 SYS IOMUX CFG SAIF SYSCFG PADCFG 380: GPIO23 0x5C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio24 SYS IOMUX CFG SAIF SYSCFG PADCFG 384: GPIO24 0x60 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio25 SYS IOMUX CFG SAIF SYSCFG PADCFG 388: GPIO25 0x64 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio26 SYS IOMUX CFG SAIF SYSCFG PADCFG 392: GPIO26 0x68 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio27 SYS IOMUX CFG SAIF SYSCFG PADCFG 396: GPIO27 0x6C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio28 SYS IOMUX CFG SAIF SYSCFG PADCFG 400: GPIO28 0x70 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio29 SYS IOMUX CFG SAIF SYSCFG PADCFG 404: GPIO29 0x74 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio30 SYS IOMUX CFG SAIF SYSCFG PADCFG 408: GPIO30 0x78 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio31 SYS IOMUX CFG SAIF SYSCFG PADCFG 412: GPIO31 0x7C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio32 SYS IOMUX CFG SAIF SYSCFG PADCFG 416: GPIO32 0x80 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio33 SYS IOMUX CFG SAIF SYSCFG PADCFG 420: GPIO33 0x84 0x20 0x00000000 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio34 SYS IOMUX CFG SAIF SYSCFG PADCFG 424: GPIO34 0x88 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio35 SYS IOMUX CFG SAIF SYSCFG PADCFG 428: GPIO35 0x8C 0x20 0x00000011 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio36 SYS IOMUX CFG SAIF SYSCFG PADCFG 432: GPIO36 0x90 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio37 SYS IOMUX CFG SAIF SYSCFG PADCFG 436: GPIO37 0x94 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio38 SYS IOMUX CFG SAIF SYSCFG PADCFG 440: GPIO38 0x98 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio39 SYS IOMUX CFG SAIF SYSCFG PADCFG 444: GPIO39 0x9C 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio40 SYS IOMUX CFG SAIF SYSCFG PADCFG 448: GPIO40 0xA0 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio41 SYS IOMUX CFG SAIF SYSCFG PADCFG 452: GPIO41 0xA4 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio42 SYS IOMUX CFG SAIF SYSCFG PADCFG 456: GPIO42 0xA8 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio43 SYS IOMUX CFG SAIF SYSCFG PADCFG 460: GPIO43 0xAC 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio44 SYS IOMUX CFG SAIF SYSCFG PADCFG 464: GPIO44 0xB0 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio45 SYS IOMUX CFG SAIF SYSCFG PADCFG 468: GPIO45 0xB4 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio46 SYS IOMUX CFG SAIF SYSCFG PADCFG 472: GPIO46 0xB8 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio47 SYS IOMUX CFG SAIF SYSCFG PADCFG 476: GPIO47 0xBC 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio48 SYS IOMUX CFG SAIF SYSCFG PADCFG 480: GPIO48 0xC0 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio49 SYS IOMUX CFG SAIF SYSCFG PADCFG 484: GPIO49 0xC4 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio50 SYS IOMUX CFG SAIF SYSCFG PADCFG 488: GPIO50 0xC8 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio51 SYS IOMUX CFG SAIF SYSCFG PADCFG 492: GPIO51 0xCC 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio52 SYS IOMUX CFG SAIF SYSCFG PADCFG 496: GPIO52 0xD0 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio53 SYS IOMUX CFG SAIF SYSCFG PADCFG 500: GPIO53 0xD4 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio54 SYS IOMUX CFG SAIF SYSCFG PADCFG 504: GPIO54 0xD8 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio55 SYS IOMUX CFG SAIF SYSCFG PADCFG 508: GPIO55 0xDC 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio56 SYS IOMUX CFG SAIF SYSCFG PADCFG 512: GPIO56 0xE0 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio57 SYS IOMUX CFG SAIF SYSCFG PADCFG 516: GPIO57 0xE4 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio58 SYS IOMUX CFG SAIF SYSCFG PADCFG 520: GPIO58 0xE8 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio59 SYS IOMUX CFG SAIF SYSCFG PADCFG 524: GPIO59 0xEC 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio60 SYS IOMUX CFG SAIF SYSCFG PADCFG 528: GPIO60 0xF0 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio61 SYS IOMUX CFG SAIF SYSCFG PADCFG 532: GPIO61 0xF4 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio62 SYS IOMUX CFG SAIF SYSCFG PADCFG 536: GPIO62 0xF8 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 gpio63 SYS IOMUX CFG SAIF SYSCFG PADCFG 540: GPIO63 0xFC 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_clk SYS IOMUX CFG SAIF SYSCFG PADCFG 544: SD0_CLK 0x100 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_cmd SYS IOMUX CFG SAIF SYSCFG PADCFG 548: SD0_CMD 0x104 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data0 SYS IOMUX CFG SAIF SYSCFG PADCFG 552: SD0_DATA0 0x108 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data1 SYS IOMUX CFG SAIF SYSCFG PADCFG 556: SD0_DATA1 0x10C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data2 SYS IOMUX CFG SAIF SYSCFG PADCFG 560: SD0_DATA2 0x110 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data3 SYS IOMUX CFG SAIF SYSCFG PADCFG 564: SD0_DATA3 0x114 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data4 SYS IOMUX CFG SAIF SYSCFG PADCFG 568: SD0_DATA4 0x118 0x20 0x00000009 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data5 SYS IOMUX CFG SAIF SYSCFG PADCFG 572: SD0_DATA5 0x11C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data6 SYS IOMUX CFG SAIF SYSCFG PADCFG 576: SD0_DATA6 0x120 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_data7 SYS IOMUX CFG SAIF SYSCFG PADCFG 580: SD0_DATA7 0x124 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 sd0_strb SYS IOMUX CFG SAIF SYSCFG PADCFG 584: SD0_STRB 0x128 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 14 0x4 _mdc,_mdio,_rxd_0,_rxd_1,_rxd_2,_rxd_3,_rxdv,_rxc,_txd_0,_txd_1,_txd_2,_txd_3,_txen,_txc gmac1[%s] SYS IOMUX CFG SAIF SYSCFG PADCFG: GPIO GMAC1 pads 0x12C 0x20 0x00000002 cfg [1:0] read-write 0 3 qspi_sclk SYS IOMUX CFG SAIF SYSCFG PADCFG 644: QSPI_SCLK 0x164 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 qspi_csn0 SYS IOMUX CFG SAIF SYSCFG PADCFG 648: QSPI_CSN0 0x168 0x20 0x00000008 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 4 0x4 qspi_data[%s] SYS IOMUX CFG SAIF SYSCFG PADCFG 28c-298: QSPI_DATA 0-3 0x16C 0x20 0x00000001 ie Input Enable (IE) Controller [0:0] read-write true disable Disable the receiver 0 enable Enable the receiver 1 ds Output Drive Strength (DS) [2:1] read-write true ma2 The rated output drive strength: 2 mA 0 ma4 The rated output drive strength: 4 mA 1 ma8 The rated output drive strength: 8 mA 2 ma12 The rated output drive strength: 12 mA 3 pu Pull-Up (PU) settings [3:3] read-write true no Pull-up setting: no 0 yes Pull-up setting: yes 1 pd Pull-Down (PD) settings [4:4] read-write true no Pull-down setting: no 0 yes Pull-down setting: yes 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slow rate control: slow (half frequency) 0 fast Slow rate control: fast 1 smt Active high Schmitt (SMT) trigger selector [6:6] read-write true no_hysteresis Active high Schmitt (SMT) trigger selector: no hysteresis 0 schmitt Active high Schmitt (SMT) trigger selector: Schmitt trigger enabled 1 pos Power-on-Start (POS) enabler [7:7] read-write true disable Power-on-Start (POS) active pull down capability for loss of power: disabled 0 enable Power-on-Start (POS) active pull down capability for loss of power: enabled 1 func_sel Registers used to configure the function selector of the system signal indicated by the register name. 0x29C func_sel0 SYS IOMUX CFG SAIF SYSCFG Function Selector 0 0x0 0x20 0x00000000 pad_gmac1_rxc Function selector of GMAC1_RXC: * Function 0: u0_sys_crg.clk_gmac1_rgmii_rx, * Function 1: u0_sys_crg.clk_gmac1_rmii_ref, * Function 2: None, * Function 3: None [1:0] read-write 0 3 pad_gpio10 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [4:2] read-write 0 7 pad_gpio11 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [7:5] read-write 0 7 pad_gpio12 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [10:8] read-write 0 7 pad_gpio13 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [13:11] read-write 0 7 pad_gpio14 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [16:14] read-write 0 7 pad_gpio15 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [19:17] read-write 0 7 pad_gpio16 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [22:20] read-write 0 7 pad_gpio17 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [25:23] read-write 0 7 pad_gpio18 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [28:26] read-write 0 7 pad_gpio19 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [31:29] read-write 0 7 func_sel1 SYS IOMUX CFG SAIF SYSCFG Function Selector 4 0x4 0x20 0x00000000 pad_gpio20 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [2:0] read-write 0 7 pad_gpio21 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:3] read-write 0 7 pad_gpio22 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write 0 7 pad_gpio23 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [11:9] read-write 0 7 pad_gpio24 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write 0 7 pad_gpio25 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write 0 7 pad_gpio26 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write 0 7 pad_gpio27 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write 0 7 pad_gpio28 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write 0 7 pad_gpio29 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write 0 7 func_sel2 SYS IOMUX CFG SAIF SYSCFG Function Selector 8 0x8 0x20 0x00000000 pad_gpio30 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [2:0] read-write 0 7 pad_gpio31 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:3] read-write 0 7 pad_gpio32 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write 0 7 pad_gpio33 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [11:9] read-write 0 7 pad_gpio34 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write 0 7 pad_gpio35 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write 0 7 pad_gpio36 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write 0 7 pad_gpio37 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write 0 7 pad_gpio38 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write 0 7 pad_gpio39 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write 0 7 pad_gpio40 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [32:30] read-write 0 7 func_sel3 SYS IOMUX CFG SAIF SYSCFG Function Selector 12 0xC 0x20 0x00000000 pad_gpio41 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [2:0] read-write 0 7 pad_gpio42 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:3] read-write 0 7 pad_gpio43 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write 0 7 pad_gpio44 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [11:9] read-write 0 7 pad_gpio45 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write 0 7 pad_gpio46 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write 0 7 pad_gpio47 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write 0 7 pad_gpio48 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write 0 7 pad_gpio49 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write 0 7 pad_gpio50 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write 0 7 pad_gpio51 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [32:30] read-write 0 7 func_sel4 SYS IOMUX CFG SAIF SYSCFG Function Selector 16 0x10 0x20 0x00000000 pad_gpio52 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [1:0] read-write 0 3 pad_gpio53 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [3:2] read-write 0 3 pad_gpio54 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [5:4] read-write 0 3 pad_gpio55 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [7:6] read-write 0 3 pad_gpio56 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [14:12] read-write 0 7 pad_gpio57 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [17:15] read-write 0 7 pad_gpio58 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [20:18] read-write 0 7 pad_gpio59 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [23:21] read-write 0 7 pad_gpio60 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [26:24] read-write 0 7 pad_gpio61 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [29:27] read-write 0 7 pad_gpio62 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [32:30] read-write 0 7 pad_gpio63 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [31:30] read-write 0 3 func_sel5 SYS IOMUX CFG SAIF SYSCFG Function Selector 20 0x14 0x20 0x00000000 pad_gpio6 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [1:0] read-write 0 3 pad_gpio7 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [4:2] read-write 0 7 pad_gpio8 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [6:4] read-write 0 7 pad_gpio9 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [8:6] read-write 0 7 pad_gpio0 GPIO function selector: * Function 0: See Function Description no page 84 for more information, * Function 1: See Full Multiplexing for more information, * Function 2: See Function 2 for more information, * Function 3: See Function 3 for more information [10:8] read-write 0 7 vin_dvp_data10 Function Selector of DVP_DATA[idx], see Function 2 for more information [13:11] read-write 0 7 vin_dvp_data11 Function Selector of DVP_DATA[idx], see Function 2 for more information [16:14] read-write 0 7 vin_dvp_data1 Function Selector of DVP_DATA[idx], see Function 2 for more information [19:17] read-write 0 7 vin_dvp_data2 Function Selector of DVP_DATA[idx], see Function 2 for more information [22:20] read-write 0 7 vin_dvp_data3 Function Selector of DVP_DATA[idx], see Function 2 for more information [25:23] read-write 0 7 vin_dvp_data4 Function Selector of DVP_DATA[idx], see Function 2 for more information [28:26] read-write 0 7 func_sel6 SYS IOMUX CFG SAIF SYSCFG Function Selector 24 0x18 0x20 0x00000000 vin_dvp_data5 Function Selector of DVP_DATA[idx], see Function 2 for more information [2:0] read-write 0 7 vin_dvp_data6 Function Selector of DVP_DATA[idx], see Function 2 for more information [5:3] read-write 0 7 vin_dvp_data7 Function Selector of DVP_DATA[idx], see Function 2 for more information [8:6] read-write 0 7 vin_dvp_data8 Function Selector of DVP_DATA[idx], see Function 2 for more information [11:9] read-write 0 7 vin_dvp_data9 Function Selector of DVP_DATA[idx], see Function 2 for more information [14:12] read-write 0 7 vin_dvp_data10 Function Selector of DVP_DATA[idx], see Function 2 for more information [17:15] read-write 0 7 vin_dvp_hvalid Function Selector of DVP_HSYNC, see Function 2 for more information [17:15] read-write 0 7 vin_dvp_vvalid Function Selector of DVP_VSYNC, see Function 2 for more information [20:18] read-write 0 7 wdt StarFive JH7110 WDT: wdt 0x13070000 0x0 0x10000 registers load StarFive JH7110 Watchdog Load register. 0x0 0x20 0x00000000 load Watchdog Load value [31:0] read-write 0 4294967295 value StarFive JH7110 Watchdog Value register. 0x4 0x20 0x00000000 load Current value for the watchdog counter. [31:0] read-only control StarFive JH7110 Watchdog Control register. 0x8 0x20 0x00000000 reset Watchdog reset enable - 0: disable, 1: enable. [0:0] read-write enable Watchdog interrupt enable, WDT enable, reload counter - 0: disable/no-op, 1: enable/reload. [1:1] read-write int_clear StarFive JH7110 Watchdog Interrupt Clear register. 0xC 0x20 0x00000000 int_clear Clear interrupt, and reload the counter - 0: no-op, 1: clear/reload. [0:0] write-only true clear Clear the interrupt, and reload the counter 1 ris StarFive JH7110 Watchdog Raw Interrupt Status register. 0x10 0x20 0x00000000 ris Raw interrupt status from the watchdog counter. [31:0] read-only ims StarFive JH7110 Watchdog Interrupt Masked Status register. 0x14 0x20 0x00000000 ims interrupt masked status from the watchdog counter. [31:0] read-only lock StarFive JH7110 Watchdog Lock register. 0xC00 0x20 0xE5331AAE lock Write magic values to enable/disable writes to other watchdog registers: 0x1acce551: enable writes / unlock, 0xe5331aae: disable writes / lock. Defaults to the 'lock' value. [31:0] read-write true enable_writes Enables writes to other watchdog registers 449635665 disable_writes Disables writes to other watchdog registers 3845331630 itcr StarFive JH7110 Watchdog Integration Test Control register. 0xF00 0x20 0xE5331AAE enable Integration test mode enable - 0: disable, 1: enable [0:0] read-write itop StarFive JH7110 Watchdog Integration Test Operation register. 0xF04 0x20 0xE5331AAE wdogres Integration test value output on WDOGRES in Integration Test mode - 0: disable, 1: enable [0:0] write-only wdogint Integration test value output on WDOGINT in Integration Test mode - 0: disable, 1: enable [1:1] write-only crypto StarFive JH7110 Crypto: crypto 0x16000000 0x0 0x4000 registers CRYPTO 28 alg JH7110 Crypto Algorithm registers 0x0 cr JH7110 Crypto Control 0x0 0x20 0x00000000 start [0:0] read-write aes_dma_en [1:1] read-write des_dma_en [2:2] read-write sha_dma_en [3:3] read-write alg_done [4:4] read-write clear [8:8] read-write fifo JH7110 Crypto Algorithm FIFO 0x4 0x20 0x00000000 fifo [31:0] read-write 0 4294967295 ie JH7110 Crypto Interrupt Enable registers 0x8 mask JH7110 Crypto Interrupt Enable Mask 0x0 0x20 0x00000000 aes_ie_mask AES Interrupt Enable Mask [0:0] read-write des_ie_mask DES Interrupt Enable Mask [1:1] read-write sha_ie_mask SHA Interrupt Enable Mask [2:2] read-write crypto_ie_mask Crypto Interrupt Enable Mask [3:3] read-write flag JH7110 Crypto Interrupt Enable Flag 0x4 0x20 0x00000000 aes_ie_done AES Interrupt Enable Done [0:0] read-write des_ie_done DES Interrupt Enable Done [1:1] read-write sha_ie_done SHA Interrupt Enable Done [2:2] read-write crypto_ie_done Crypto Interrupt Enable Done [3:3] read-write 2 0x4 _in_len,_out_len dma[%s] JH7110 Crypto DMA registers 0x10 0x20 0x00000000 dma_len DMA transfer length [31:0] read-write 0 4294967295 aes JH7110 Crypto AES registers 0x100 aesdio0r JH7110 Crypto AES AESDIO0R 0x0 0x20 0x00000000 aesdio0r [31:0] read-write 0 4294967295 8 0x4 key[%s] JH7110 Crypto AES Key 0x4 0x20 0x00000000 key [31:0] read-write 0 4294967295 csr JH7110 Crypto AES Control Status Register 0x24 0x20 0x00000000 cmode [0:0] read-write keymode AES Key Mode - 0: AES 128, 1: AES 192, 2: AES 256 [2:1] read-write true aes128 AES Key Mode: 128-bit 0 aes192 AES Key Mode: 192-bit 1 aes256 AES Key Mode: 256-bit 2 busy AES Engine Busy [3:3] read-write done AES Engine Done [4:4] read-write krdy AES Key Done [5:5] read-write rst AES Reset [6:6] read-write ie AES Interrupt Enable [7:7] read-write ccm_start AES CCM Start [8:8] read-write mode AES Mode - 0: ECB, 1: CBC, 2: CFB, 3: OFB, 4: CTR, 5: CCM, 6: GCM [11:9] read-write true ecb AES Mode: ECB 0 cbc AES Mode: CBC 1 cfb AES Mode: CFB 2 ofb AES Mode: OFB 3 ctr AES Mode: CTR 4 ccm AES Mode: CCM 5 gcm AES Mode: GCM 6 gcm_start AES GCM Start [12:12] read-write gcm_done AES GCM Done [13:13] read-write delay_aes Delay AES [14:14] read-write vaes_start VAES Start [15:15] read-write stream_mode AES Stream Cipher mode - 0: XFB 1, 5: XFB 128 [26:24] read-write true xfb1 AES Stream Cipher Mode: XFB 1 0 xfb128 AES Stream Cipher Mode: XFB 128 5 4 0x4 iv[%s] JH7110 Crypto AES IV 0x28 0x20 0x00000000 iv [31:0] read-write 0 4294967295 4 0x4 nonce[%s] JH7110 Crypto AES Nonce 0x3C 0x20 0x00000000 nonce [31:0] read-write 0 4294967295 2 0x4 alen[%s] JH7110 Crypto AES ALEN 0x4C 0x20 0x00000000 alen [31:0] read-write 0 4294967295 2 0x4 mlen[%s] JH7110 Crypto AES MLEN 0x54 0x20 0x00000000 mlen [31:0] read-write 0 4294967295 ivlen JH7110 Crypto AES IVLEN 0x5C 0x20 0x00000000 ivlen [31:0] read-write 0 4294967295 sha JH7110 Crypto SHA registers 0x300 csr JH7110 Crypto SHA CSR 0x0 0x20 0x00000000 start SHA CSR Start [0:0] read-write reset SHA Reset [1:1] read-write ie SHA Interrupt Enable [2:2] read-write firstb SHA First B [3:3] read-write mode SHA Mode - 0: SM3, 1: SHA0, 2: SHA1, 3: SHA224, 4: SHA256, 5: SHA384, 6: SHA512 [6:4] read-write true sm3 SHA Mode: SM3 0 sha0 SHA Mode: SHA0 1 sha1 SHA Mode: SHA1 2 sha224 SHA Mode: SHA224 3 sha256 SHA Mode: SHA256 4 sha384 SHA Mode: SHA384 5 sha512 SHA Mode: SHA512 6 sha_final SHA Final [8:8] read-write hmac SHA HMAC [11:11] read-write key_done SHA Key Done [13:13] read-write key_flag SHA Key Flag [14:14] read-write hmac_done SHA HMAC Done [15:15] read-write busy SHA Busy [16:16] read-write shadone SHA Done [17:17] read-write wdr JH7110 Crypto SHA WDR 0x4 0x20 0x00000000 wdr SHA WDR [31:0] read-write 0 4294967295 rdr JH7110 Crypto SHA RDR 0x8 0x20 0x00000000 rdr SHA RDR [31:0] read-write 0 4294967295 wsr JH7110 Crypto SHA WSR 0xC 0x20 0x00000000 wsr SHA WSR [31:0] read-write 0 4294967295 4 0x4 3,2,1,0 wlen[%s] JH7110 Crypto SHA WLEN 0x10 0x20 0x00000000 wlen SHA WLEN [31:0] read-write 0 4294967295 wkr JH7110 Crypto SHA WKR 0x20 0x20 0x00000000 wkr SHA WKR [31:0] read-write 0 4294967295 klen JH7110 Crypto SHA KLEN 0x24 0x20 0x00000000 klen SHA KLEN [31:0] read-write 0 4294967295 crypto JH7110 Crypto CRYPTO registers 0x400 cacr JH7110 Crypto CA Control Register 0x0 0x20 0x00000000 start Crypto Start [0:0] read-write reset Crypto Reset [1:1] read-write ie Crypto Interrupt Enable [2:2] read-write fifo_mode Crypto FIFO Mode [4:4] read-write not_r2 Crypto Not R2 [5:5] read-write ecc_sub Crypto ECC Sub [6:6] read-write pre_expf Crypto Pre EXPF [7:7] read-write cmd Crypto Command - 0: PRE (R^2 mod N and N0'), 1: AAN ((A + A) mod N, ==> A), 2: AMEN (A ^ E mod N ==> A), 3: AAEN (A + E mod N ==> A), 4: ADEN (A - E mod N ==> A), 5: ARN (A * $ mod N ==> A), 6: AERN (A * E * R mod N ==> A), 7: AARN (A * A * R mod N ==> A), 8: ECC2P (ECC2P ==> A), 9: ECCPQ (ECCPQ ==> A) [11:8] read-write true pre PRE (R^2 mod N and N0') 0 aan AAN ((A + A) mod N, ==> A) 1 amen AMEN (A ^ E mod N ==> A) 2 aaen AAEN (A + E mod N ==> A) 3 aden ADEN (A - E mod N ==> A) 4 arn ARN (A * $ mod N ==> A) 5 aern AERN (A * E * R mod N ==> A) 6 aarn AERN (A * A * R mod N ==> A) 7 ecc2p ECC2P (ECC2P ==> A) 8 eccpq ECCPQ (ECCPQ ==> A) 9 ctrl_dummy Crypto Control Dummy [13:13] read-write ctrl_false Crypto Control False [14:14] read-write cln_done Crypto CLN Done [15:15] read-write opsize Crypto OPSIZE [21:16] read-write 0 63 exposize Crypto EXPOSIZE [29:24] read-write 0 63 bigendian Crypto Big Endian [31:31] read-write casr JH7110 Crypto CA Status Register 0x4 0x20 0x00000000 done Crypto Done [0:0] read-only caar JH7110 Crypto CAAR 0x8 0x20 0x00000000 caar Crypto CAAR [31:0] read-write 0 4294967295 caer JH7110 Crypto CAER 0x108 0x20 0x00000000 caer Crypto CAER [31:0] read-write 0 4294967295 canr JH7110 Crypto CANR 0x208 0x20 0x00000000 canr Crypto CANR [31:0] read-write 0 4294967295 caafr JH7110 Crypto CAAFR 0x308 0x20 0x00000000 caafr Crypto CAAFR [31:0] read-write 0 4294967295 caefr JH7110 Crypto CAEFR 0x30C 0x20 0x00000000 caefr Crypto CAEFR [31:0] read-write 0 4294967295 canfr JH7110 Crypto CANFR 0x310 0x20 0x00000000 canfr Crypto CANFR [31:0] read-write 0 4294967295 fifo_counter JH7110 Crypto FIFO Counter 0x314 0x20 0x00000000 fifo_counter Crypto FIFO Counter [31:0] read-write 0 4294967295 sdma ARM PL080 DMA Controller: sdma 0x16008000 0x0 0x4000 registers SDMA 29 int DMAC Interrupt registers 0x0 status Interrupt Status Register - shows the status of the interrupts after masking. A HIGH bit indicates that a specific DMA channel interrupt request is active. You can generate the request from either the error or terminal count interrupt requests. 0x0 0x20 0x00000000 8 0x1 status[%s] Status of the DMA interrupts after masking [0:0] read-only true clear DMA channel interrupt is clear 0 active DMA channel interrupt is active 1 tc_status Interrupt Terminal Count Status Register - indicates the status of the terminal count after masking. You must use this register in conjunction with the DMACIntStatus Register if you use the combined interrupt request, DMACINTR, to request interrupts. If you use the DMACINTTC interrupt request, then you only have to read the DMACIntTCStatus Register to ascertain the source of the interrupt request. 0x4 0x20 0x00000000 8 0x1 tc_status[%s] Interrupt terminal count request status [0:0] read-only true clear Terminal count interrupt is clear 0 active Terminal count interrupt is active 1 tc_clear Interrupt Terminal Count Clear Register - clears a terminal count interrupt request. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the Status Register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the register. 0x8 0x20 0x00000000 8 0x1 tc_clear[%s] Terminal count request clear. [0:0] write-only true clear Clears the terminal count status (`tc_status`) register 1 error_status Interrupt Error Status Register - indicates the status of the error request after masking. You must use this register in conjunction with the DMACIntStatus Register if you use the combined interrupt request, DMACINTR, to request interrupts. If you use the DMACINTERR interrupt request, then only read the DMACIntErrorStatus Register. 0xC 0x20 0x00000000 8 0x1 error_status[%s] Interrupt error status. [0:0] read-only true clear Interrupt error status is clear 0 active Interrupt error status is active 1 error_clear Interrupt Error Clear Register - clears the error interrupt requests. When writing to this register, each data bit that is HIGH causes the corresponding bit in the Status Register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the register. 0x10 0x20 0x00000000 8 0x1 error_clear[%s] Interrupt error clear. [0:0] write-only true clear Clears the error status (`error_status`) register 1 raw_int DMAC Raw Interrupt registers 0x14 tc_status Raw Interrupt Terminal Count Status Register - indicates the DMA channels that are requesting a transfer complete, terminal count interrupt, prior to masking. A HIGH bit indicates that the terminal count interrupt request is active prior to masking. 0x0 0x20 0x00000000 8 0x1 tc_status[%s] Status of the terminal count interrupt prior to masking. [0:0] read-only true clear Terminal count status interrupt is clear 0 active Terminal count status interrupt is active 1 error_status Raw Error Interrupt Status Register - indicates the DMA channels that are requesting an error interrupt prior to masking. A HIGH bit indicates that the error interrupt request is active prior to masking. 0x4 0x20 0x00000000 8 0x1 error_status[%s] Status of the error interrupt prior to masking. [0:0] read-only true clear Error status interrupt is clear 0 active Error status interrupt is active 1 enbld_chns DMA Enabled Channels register - indicates the DMA channels that are enabled, as indicated by the Enable bit in the DMACCxConfiguration Register. A HIGH bit indicates that a DMA channel is enabled. A bit is cleared on completion of the DMA transfer. 0x1C 0x20 0x00000000 8 0x1 channel_status[%s] Channel enable status. [0:0] read-only true disabled DMAC channel is disabled 0 enabled DMAC channel is enabled 1 soft DMAC Software registers 0x20 burst_req Software Burst Request Register - enables DMA burst requests to be generated by software. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting DMA burst transfers. You can generate a request from either a peripheral or the software request register. 0x0 0x20 0x00000000 16 0x1 burst_req[%s] Software burst request. [0:0] read-write true nop Software burst request, read: none, write: no-op 0 generate Software burst request, read: active request, write: generate a request 1 single_req Software Single Request Register - enables DMA single requests to be generated by software. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting single DMA transfers. You can generate a request from either a peripheral or the software request register 0x4 0x20 0x00000000 16 0x1 single_req[%s] Software single request. [0:0] read-write true nop Software single request, read: none, write: no-op 0 generate Software single request, read: active request, write: generate a request 1 last_burst_req Software Last Burst Request Register - enables software to generate DMA last burst requests. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting last burst DMA transfers. You can generate a request from either a peripheral or the software request register. 0x8 0x20 0x00000000 16 0x1 last_burst_req[%s] Software last burst request. [0:0] read-write true nop Software last burst request, read: none, write: no-op 0 generate Software last burst request, read: active request, write: generate a request 1 last_single_req Software Last Single Request Register - enables software to generate DMA last single requests. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting last single DMA transfers. You can generate a request from either a peripheral or the software request register. 0xC 0x20 0x00000000 16 0x1 last_single_req[%s] Software last single request. [0:0] read-write true nop Software last single request, read: none, write: no-op 0 generate Software last single request, read: active request, write: generate a request 1 configuration DMA Configuration register - configures the operation of the DMAC. You can alter the endianness of the individual AHB master interfaces by writing to the M1 and M2 bits of this register. The M1 bit enables you to alter the endianness of AHB master interface 1. The M2 bit enables you to alter the endianness of AHB master interface 2. The AHB master interfaces are set to little-endian mode on reset. 0x30 0x20 0x00000000 e DMAC enable - disabling the DMAC reduces power consumption. [0:0] read-write true disable DMAC disable 0 enable DMAC enable 1 2 0x1 1-2 m[%s] DMAC AHB Master - 0: little-endian mode, 1: big-endian mode. This bit is reset to 0. [1:1] read-write true little_endian DMAC AHB Master endianness: little-endian 0 big_endian DMAC AHB Master endianness: big-endian 1 sync DMA Synchronization register - enables or disables synchronization logic for the DMA request signals. A bit set to 0 enables the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the synchronization logic for a particular group of DMA requests. This register is reset to 0, and synchronization logic enabled. 0x34 0x20 0x00000000 16 0x1 sync[%s] DMAC Sync - synchronization logic for DMA request signals enabled or disabled. A LOW bit indicates that the synchronization logic for the request signals is enabled. A HIGH bit indicates that the synchronization logic is disabled. [0:0] read-write true enable Indicates that the synchronization logic for the request signals is enabled 0 disable Indicates that the synchronization logic for the request signals is disabled 1 8 0x20 channel[%s] DMAC Channel registers 0x100 src_addr DMAC Source Address register - contain the current source address, byte-aligned, of the data to be transferred. Software programs each register directly before the appropriate channel is enabled. 0x0 0x20 0x00000000 src_addr DMA source address. [31:0] read-write 0 4294967295 dst_addr DMA Destination Address register - contain the current destination address, byte-aligned, of the data to be transferred. Software programs each register directly before the channel is enabled. When the DMA channel is enabled, the register is updated as the destination address is incremented and by following the linked list when a complete packet of data has been transferred. Reading the register when the channel is active does not provide useful information. This is because by the time the software has processed the value read, the channel might have progressed. It is intended to be read-only when a channel has stopped. In this case, it shows the destination address of the last item read. 0x4 0x20 0x00000000 dst_addr DMA destination address. [31:0] read-write 0 4294967295 lli DMA Linked List Item register 0x8 0x20 0x00000000 lm AHB master select for loading the next LLI. [0:0] read-write true ahb_master1 Next LLI AHB select: AHB master 1 selected 0 ahb_master2 Next LLI AHB select: AHB master 2 selected 1 lli Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. [31:2] read-write 0 1073741823 control DMA Channel Control register 0xC 0x20 0x00000000 transfer_size Transfer size. A write to this field sets the size of the transfer when the DMAC is the flow controller. This value counts down from the original value to zero, and so its value indicates the number of transfers left to complete. A read from this field provides the number of transfers still to be completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time the software has processed the value read, the channel might have progressed. Only use it when a channel is enabled, and then disabled. The ARM PrimeCell DMA Controller (PL080) Design Manual provides more information about the use of this field. Program the transfer size value to zero if the DMAC is not the flow controller. If you program the TransferSize to a non-zero value, the DMAC might attempt to use this value instead of ignoring the TransferSize. [11:0] read-write 0 4095 sb_size Source burst size - indicates the number of transfers that make up a source burst. You must set this value to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the source peripheral. The burst size is not related to the AHB HBURST signal. [14:12] read-write true burst1 Source burst size: 1 0 burst4 Source burst size: 4 1 burst8 Source burst size: 8 2 burst16 Source burst size: 16 3 burst32 Source burst size: 32 4 burst64 Source burst size: 64 5 burst128 Source burst size: 128 6 burst256 Source burst size: 256 7 db_size Destination burst size - indicates the number of transfers that make up a destination burst transfer request. You must set this value to the burst size of the destination peripheral, or if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the destination peripheral. The burst size is not related to the AHB HBURST signal. [17:15] read-write true burst1 Destination burst size: 1 0 burst4 Destination burst size: 4 1 burst8 Destination burst size: 8 2 burst16 Destination burst size: 16 3 burst32 Destination burst size: 32 4 burst64 Destination burst size: 64 5 burst128 Destination burst size: 128 6 burst256 Destination burst size: 256 7 src_width Source transfer width - transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data when required. [20:18] read-write true bit8 Source transfer width: 8-bit 0 bit16 Source transfer width: 16-bit 1 bit32 Source transfer width: 32-bit 2 dst_width Destination transfer width - transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data when required. [23:21] read-write true bit8 Destination transfer width: 8-bit 0 bit16 Destination transfer width: 16-bit 1 bit32 Destination transfer width: 32-bit 2 src Source AHB master select. [24:24] read-write true ahb1_master Source AHB select: AHB master 1 selected 0 ahb2_master Source AHB select: AHB master 2 selected 1 dst Destination AHB master select. [25:25] read-write true ahb_master1 Destination AHB select: AHB master 1 selected 0 ahb_master2 Destination AHB select: AHB master 2 selected 1 src_inc Source increment. When set, the source address is incremented after each transfer. [26:26] read-write true no_increment Source address is not incremented after each transfer 0 increment Source address is incremented after each transfer 1 dst_inc Destination increment. When set, the destination address is incremented after each transfer. [27:27] read-write true no_increment Destination address is not incremented after each transfer 0 increment Destination address is incremented after each transfer 1 prot_user Protection - indicates whether the access is in User or Privileged mode. This bit controls the AHB HPROT[1] signal. [28:28] read-write true user Protection mode: user 0 privileged Protection mode: privileged 1 prot_buf Protection - indicates whether or not the access can be buffered. This bit indicates whether or not the access is bufferable. For example, you can use this bit to indicate to an AMBA bridge that the read can complete in zero wait states on the source bus without waiting for it to arbitrate for the destination bus and for the slave to accept the data. This bit controls the AHB HPROT[2] signal. [29:29] read-write true non_bufferable Protection buffer mode: non-bufferable 0 bufferable Protection buffer mode: bufferable 1 prot_cache Protection - 0: non-cacheable, 1: cacheable. This bit indicates whether or not the access is cacheable. For example, you can use this bit to indicate to an AMBA bridge that when it saw the first read of a burst of eight it can transfer the whole burst of eight reads on the destination bus, rather than pass the transactions through one at a time. This bit controls the AHB HPROT[3] signal. [30:30] read-write true non_cacheable Protection cache mode: non-cacheable 0 cacheable Protection cache mode: cacheable 1 ie Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count interrupt. [31:31] read-write true disable Terminal count interrupt: disabled 0 enable Terminal count interrupt: enabled 1 configuration DMA Channel Configuration register 0x10 0x20 0x00000000 enable Channel enable. [0:0] read-write true disabled Channel disabled 0 enabled Channel enabled 1 src_peripheral Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. [4:1] read-write 0 15 dst_peripheral Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. [9:6] read-write 0 15 flow_cntrl Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMAC, the source peripheral, or the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. **NOTE**: enum values best-guess, please report errors via an issue and/or pull-request. [13:11] read-write true dmac_mtm Flow Controller: DMAC, Transfer type: memory-to-memory 0 dmac_mtp Flow Controller: DMAC, Transfer type: memory-to-peripheral 1 dmac_ptm Flow Controller: DMAC, Transfer type: peripheral-to-memory 2 dmac_ptp Flow Controller: DMAC, Transfer type: peripheral-to-peripheral 3 source_ptm Flow Controller: source peripheral, Transfer type: peripheral-to-memory 4 source_ptp Flow Controller: source peripheral, Transfer type: peripheral-to-peripheral 5 destination_ptm Flow Controller: destination peripheral, Transfer type: peripheral-to-memory 6 destination_ptp Flow Controller: destination peripheral, Transfer type: peripheral-to-peripheral 7 iem Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. [14:14] read-write itc Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. [15:15] read-write lock Lock. When set, this bit enables locked transfers. For details of how lock control works. [16:16] read-write true unlock Disable locked transfers 0 lock Enable locked transfers 1 active Active channel FIFO data. [17:17] read-only true no_data The channel FIFO has no data 0 data The channel FIFO has data 1 halt Halt - the contents of the channels FIFO are drained. You can use this value with the Active and Channel Enable bits to cleanly disable a DMA channel. [18:18] read-write true enable Enable DMA requests 0 ignore Ignore extra source DMA requests 1 _reserved_channel Reserved Channel - not meant for actual use. 0x1C 0x20 0x00000000 test DMAC Test registers - controls and reads registers used in peripheral integration tests. 0x500 itcr DMA Test Control register - enables you to test the DMAC using TIC block-level tests and Built-In Self-Test (BIST) integration and system level tests. 0x0 0x20 0x00000000 test Test mode enable - multiplex the test registers to control the input and output lines. [0:0] read-write true normal DMA test mode disabled, normal operation 0 test DMA test registers multiplexed onto inputs and outputs 1 itop1 DMA Integration Test Output 1 register - controls and reads the DMACCLR[15:0] output lines in test mode. 0x4 0x20 0x00000000 16 0x1 clr[%s] Controls and reads the DMACCLR output line in test mode. [0:0] read-write true clear DMACCLR test output line is clear 0 active DMACCLR test output line is active 1 itop2 DMA Integration Test Output 2 register - controls and reads the DMACTC[15:0] output lines in test mode. 0x8 0x20 0x00000000 16 0x1 tc[%s] Controls and reads the DMACTC output line in test mode. [0:0] read-write true clear DMACTC test output line is clear 0 active DMACTC test output line is active 1 itop3 DMA Integration Test Output 3 register - controls and reads the interrupt request output lines in test mode. The DMACINTR interrupt request signal combines both interrupt requests, DMACINTTC and DMACINTERR, into one interrupt request signal. Therefore, if you set either the TC or E bits, then DMACINTR is active. 0xC 0x20 0x00000000 tc You can set the DMACINTTC interrupt request to a certain value in test mode by writing to the register. A read returns the value on the output, after the test multiplexor. [0:0] read-write err You can set the DMACINTERR interrupt request to a certain value in test mode by writing to the register. A read returns the value on the output, after the test multiplexor. [1:1] read-write periph_id DMAC Peripheral ID registers - You can treat the registers conceptually as a 32-bit register. These read-only registers provide the following peripheral options :: PartNumber[11:0] This identifies the peripheral. The three digit product code 0x080 is used. :: Designer ID[19:12] This is the identification of the designer. ARM Limited is 0x41, (ASCII A). :: Revision[23:20] This is the revision number of the peripheral. The revision number starts from 0. :: Configuration[31:24] This is the configuration option of the peripheral. 0xFE0 periph_id0 DMA Peripheral ID 0 register - is hard-coded and the fields in the register determine the reset value. 0x0 0x20 0x00000080 part_number0 These bits read back as 0x80 [7:0] read-only periph_id1 DMA Peripheral ID 1 register - is hard-coded and the fields in the register determine the reset value. 0x4 0x20 0x00000010 part_number1 These bits read back as 0x0 [3:0] read-only designer0 These bits read back as 0x1 [7:4] read-only periph_id2 DMA Peripheral ID 2 register - is hard-coded and the fields in the register determine the reset value. 0x8 0x20 0x00000014 designer1 These bits read back as 0x4 [3:0] read-only revision These bits read back as 0x1 [7:4] read-only periph_id3 DMA Peripheral ID 3 register - is hard-coded and the fields in the register determine the reset value. 0xC 0x20 0x00000006 num_chan Indicates the number of channels - this peripheral is set to 8 channels (`0b010`). [2:0] read-only true channels2 Number of channels: 2 0 channels4 Number of channels: 4 1 channels8 Number of channels: 8 2 channels16 Number of channels: 16 3 channels32 Number of channels: 32 4 num_ahb Indicates the number of AHB masters. [3:3] read-only true ahb1 Number of AHB interfaces: 1 0 ahb2 Number of AHB interfaces: 2 1 ahb_bus_width Indicates the AHB bus width - this peripheral is set to 32-bit (`0b000`). [6:4] read-only true bit32 AHB bus width: 32-bit 0 bit64 AHB bus width: 64-bit 1 bit128 AHB bus width: 128-bit 2 bit256 AHB bus width: 256-bit 3 bit512 AHB bus width: 512-bit 4 bit1024 AHB bus width: 1024-bit 5 num_src_req Indicates the number of DMA source requestors for the DMAC configuration - this peripheral is set to 16 requestors (`0`). [7:7] read-only true req16 Number of DMA source requestors: 16 0 req32 Number of DMA source requestors: 32 1 pcell_id DMAC PrimeCell ID registers - You can treat the registers conceptually as a 32-bit register. The register is a standard cross-peripheral identification system. The DMACPCellID Register is set to 0xB105F00D. 0xFF0 pcell_id0 DMA PrimeCell ID 0 register - is hard-coded and the fields in the register determine the reset value. 0x0 0x20 0x0000000D pcell_id These bits read back as 0x0D [7:0] read-only pcell_id1 DMA PrimeCell ID 1 register - is hard-coded and the fields in the register determine the reset value. 0x4 0x20 0x000000F0 pcell_id These bits read back as 0xF0 [7:0] read-only pcell_id2 DMA PrimeCell ID 2 register - is hard-coded and the fields in the register determine the reset value. 0x8 0x20 0x00000005 pcell_id These bits read back as 0x05 [7:0] read-only pcell_id3 DMA PrimeCell ID 3 register - is hard-coded and the fields in the register determine the reset value. 0xC 0x20 0x000000B1 pcell_id These bits read back as 0xB1 [7:0] read-only trng StarFive JH7110 TRNG: trng 0x1600C000 0x0 0x4000 registers TRNG 30 ctrl TRNG Control Register 0x0 0x20 0x00000000 exec_nop Execute a NOP instruction [0:0] read-write gen_rand Generate a random number [1:1] read-write reseed Reseed the TRNG from noise sources [2:2] read-write stat TRNG STAT Register 0x4 0x20 0x00000000 nonce_mode TRNG Nonce operating mode [2:2] read-only r256 TRNG 256-bit random number operating mode [3:3] read-only mission_mode TRNG Mission Mode operating mode [8:8] read-only seeded TRNG Seeded operating mode [9:9] read-only 8 0x1 last_reseed[%s] TRNG Last Reseed status [16:16] read-only srvc_rqst TRNG Service Request [27:27] read-only rand_generating TRNG Random Number Generating Status [30:30] read-only rand_seeding TRNG Random Number Seeding Status [31:31] read-only mode TRNG MODE Register 0x8 0x20 0x00000000 r256 256-bit operation mode: 0 - 128-bit mode, 1 - 256-bit mode [3:3] read-write true bit128 128-bit operation mode 0 bit256 256-bit operation mode 1 smode TRNG SMODE Register 0xC 0x20 0x00000000 nonce_mode Nonce operation mode [2:2] read-write mission_mode Mission operation mode [8:8] read-write max_rejects TRNG Maximum Rejects [31:16] read-write 0 65535 ie TRNG Interrupt Enable Register 0x10 0x20 0x00000000 rand_rdy_en RAND Ready Enable [0:0] read-write seed_done_en Seed Done Enable [1:1] read-write lfsr_lockup_en LFSR Lockup Enable [4:4] read-write glbl_en Global Enable [31:31] read-write istat TRNG Interrupt Status Register 0x14 0x20 0x00000000 rand_rdy RAND Ready Status [0:0] read-only seed_done Seed Done Status [1:1] read-only lfsr_lockup LFSR Lockup Status [4:4] read-only 8 0x4 rand[%s] TRNG RAND Register 0x20 0x20 0x00000000 rand TRNG random number bits [31:0] read-only auto_rqsts Auto-reseeding after random number requests by host reaches specified counter: 0 - disable counter, other - reload value for internal counter 0x60 0x20 0x00000000 rqsts Threshold number of reseed requests for auto-reseed counter [31:0] read-write 0 4294967295 auto_age Auto-reseeding after specified timer countdowns to 0: 0 - disable timer, other - reload value for internal timer 0x64 0x20 0x00000000 age Countdown value for auto-reseed timer [31:0] read-write 0 4294967295 mmc0 Synopsys DesignWare MMC (jh7110): mmc0 0x16010000 0x0 0x10000 registers MMC0 74 ctrl MMC Control 0x0 0x20 0x00000000 3 0x1 _mmc,_fifo,_dma reset[%s] MMC Control Reset [0:0] read-write 2 0x1 _int,_dma enable[%s] MMC Control Enable [4:4] read-write read_wait MMC Control Read Wait [6:6] read-write send_irq_resp MMC Control Send IRQ Response [7:7] read-write abrt_read_data MMC Control Abort Read Data [8:8] read-write 2 0x1 _ccsd,_as_ccsd send[%s] MMC Control Send [9:9] read-write ceata_int_en MMC Control CEATA Interrupt Enable [11:11] read-write use_idmac MMC Control Use IDMAC [25:25] read-write pwren MMC Power Enable 0x4 0x20 0x00000000 pwren MMC Power Enable [31:0] read-write 0 4294967295 clk_ctrl MMC Clock Control registers 0x8 2 0x4 div,src clk[%s] MMC Clock Configuration - 0: clkdiv, 1: clksrc 0x0 0x20 0x00000000 clk MMC Clock Configuration [31:0] read-write 0 4294967295 clken MMC Clock Enable 0x8 0x20 0x00000000 enable MMC Clock Enable [0:0] read-write low_pwr MMC Clock Enable Low Power [16:16] read-write tmout MMC Timeout 0x14 0x20 0x00000000 resp MMC Response Timeout [7:0] read-write 0 255 data MMC Data Timeout [31:8] read-write 0 16777215 ctype MMC card type 0x18 0x20 0x00000000 ctype MMC card type [16:0] read-write true type1 1-bit serial transfer MMC card type. 0 type4 4-bit serial transfer MMC card type. 1 type8 8-bit serial transfer MMC card type. 65536 blksiz MMC block size 0x1C 0x20 0x00000000 blksiz MMC block size [15:0] read-write 0 65535 bytcnt MMC byte count 0x20 0x20 0x00000000 bytcnt MMC byte count [31:0] read-write 0 4294967295 intmask MMC interrupt mask 0x24 0x20 0x00000000 32 0x1 _cd,_resp_err,_cmd_done,_data_over,_txdr,_rxdr,_rcrc,_dcrc,_rto,_drto,_hto_volt_switch,_frun,_hle,_sbe,_acd,_ebe,_sdio0,_sdio1,_sdio2,_sdio3,_sdio4,_sdio5,_sdio6,_sdio7,_sdio8,_sdio9,_sdio10,_sdio11,_sdio12,_sdio13,_sdio14,_sdio15 int[%s] MMC interrupt mask and status [0:0] read-write cmdarg MMC command argument 0x28 0x20 0x00000000 cmdarg MMC command argument [31:0] read-write 0 4294967295 cmd MMC command 0x2C 0x20 0x00000000 indx MMC command index [4:0] read-write 0 31 3 0x1 _exp,_long,_crc resp[%s] MMC command response [6:6] read-write 2 0x1 _exp,_wr dat[%s] MMC command data [9:9] read-write strm_mode MMC command stream mode [11:11] read-write send_stop MMC command send stop [12:12] read-write prv_data_wait MMC command private data wait [13:13] read-write stop MMC command stop [14:14] read-write init MMC command init [15:15] read-write upd_clk MMC command update clock [21:21] read-write ceata_rd MMC command CEATA read [22:22] read-write ccs_exp MMC command CCS EXP [23:23] read-write volt_switch MMC command volt switch [28:28] read-write use_hold_reg MMC command use hold register [29:29] read-write start MMC command start [31:31] read-write 4 0x4 resp[%s] MMC response 0x30 0x20 0x00000000 resp MMC response [31:0] read-write 0 4294967295 mintsts MMC MINT status 0x40 0x20 0x00000000 32 0x1 _cd,_resp_err,_cmd_done,_data_over,_txdr,_rxdr,_rcrc,_dcrc,_rto,_drto,_hto_volt_switch,_frun,_hle,_sbe,_acd,_ebe,_sdio0,_sdio1,_sdio2,_sdio3,_sdio4,_sdio5,_sdio6,_sdio7,_sdio8,_sdio9,_sdio10,_sdio11,_sdio12,_sdio13,_sdio14,_sdio15 int[%s] MMC MINT status [0:0] read-write rintsts MMC RINT status 0x44 0x20 0x00000000 32 0x1 _cd,_resp_err,_cmd_done,_data_over,_txdr,_rxdr,_rcrc,_dcrc,_rto,_drto,_hto_volt_switch,_frun,_hle,_sbe,_acd,_ebe,_sdio0,_sdio1,_sdio2,_sdio3,_sdio4,_sdio5,_sdio6,_sdio7,_sdio8,_sdio9,_sdio10,_sdio11,_sdio12,_sdio13,_sdio14,_sdio15 int[%s] MMC RINT status [0:0] read-write status MMC status 0x48 0x20 0x00000000 busy MMC busy [9:9] read-write fcnt MMC FCNT [29:17] read-write 0 8191 dma_req MMC DMA request [31:31] read-write fifoth MMC FIFOTH 0x4C 0x20 0x00000000 tx_wmark MMC FIFOTH TX watermark [11:0] read-write 0 4095 rx_wmark MMC FIFOTH RX watermark [27:16] read-write 0 4095 msize MMC FIFOTH msize [30:28] read-write 0 7 cdetect MMC card detect 0x50 0x20 0x00000000 32 0x1 slot[%s] MMC card present in slot [0:0] read-write true present MMC card present in slot 0 not_present MMC card not present in slot 1 wrtprt MMC write protect 0x54 0x20 0x00000000 32 0x1 protect[%s] MMC card slot write protect [0:0] read-write true no_protect MMC card slot no write protect 0 protect MMC card slot write protect 1 gpio MMC GPIO 0x58 0x20 0x00000000 gpio MMC GPIO [31:0] read-write 0 4294967295 2 0x4 tcb,tbb cnt[%s] MMC count 0x5C 0x20 0x00000000 cnt MMC count [31:0] read-write 0 4294967295 debnce MMC debounce 0x64 0x20 0x00000000 debnce MMC debounce [31:0] read-write 0 4294967295 id MMC ID registers 0x68 usrid MMC user ID 0x0 0x20 0x00000000 usrid MMC user ID [31:0] read-write 0 4294967295 verid MMC version ID 0x4 0x20 0x00000000 verid MMC version ID [15:0] read-write 0 65535 hcon MMC HCON 0x70 0x20 0x00000000 slot_num MMC slot number [5:1] read-write true slot0 MMC slot 0 0 slot1 MMC slot 1 1 slot2 MMC slot 2 2 slot3 MMC slot 3 3 slot4 MMC slot 4 4 slot5 MMC slot 5 5 slot6 MMC slot 6 6 slot7 MMC slot 7 7 slot8 MMC slot 8 8 slot9 MMC slot 9 9 slot10 MMC slot 10 10 slot11 MMC slot 11 11 slot12 MMC slot 12 12 slot13 MMC slot 13 13 slot14 MMC slot 14 14 slot15 MMC slot 15 15 slot16 MMC slot 16 16 slot17 MMC slot 17 17 slot18 MMC slot 18 18 slot19 MMC slot 19 19 slot20 MMC slot 20 20 slot21 MMC slot 21 21 slot22 MMC slot 22 22 slot23 MMC slot 23 23 slot24 MMC slot 24 24 slot25 MMC slot 25 25 slot26 MMC slot 26 26 slot27 MMC slot 27 27 slot28 MMC slot 28 28 slot29 MMC slot 29 29 slot30 MMC slot 30 30 slot31 MMC slot 31 31 hdata_width MMC HDATA width [9:7] read-write 0 7 trans_mode MMC transfer mode [17:16] read-write true idma No DMA interface - using internal DMA block 0 dwdma DesignWare DMA interface 1 gdma Generic DMA interface 2 nodma Non-DesignWare DMA interface - pio only 3 addr_config MMC address config [27:27] read-write true addr32 IDMAC 32-bit address 0 addr64 IDMAC 64-bit address 1 uhs_reg MMC UHS-1 regulator 0x74 0x20 0x00000000 32 0x1 voltage[%s] MMC slot signal voltage [0:0] read-write true v33 MMC slot 3.3v signal voltage 0 v18 MMC slot 1.8v signal voltage 1 rst_n MMC Reset 0x78 0x20 0x00000000 32 0x1 rst_n[%s] MMC Reset [0:0] read-write true hwinactive MMC hardware inactive 0 hwactive MMC hardware active 1 bmod MMC DMAC bus mode 0x80 0x20 0x00000000 swreset MMC internal DMAC software reset [0:0] read-write fb MMC internal DMAC FB [1:1] read-write enable MMC internal DMAC enable [7:7] read-write pldmnd MMC PLDMND 0x84 0x20 0x00000000 start MMC Internal DMAC start [0:0] read-write idmac_addr MMC Internal DMAC Address registers 0x88 dbaddr_dbaddrl MMC internal DMAC DB address - HCON[ADDR_CONFIG] 32-bit(0): DB address, HCON[ADDR_CONFIG] 64-bit(1): DB address lower 32-bits 0x0 0x20 0x00000000 dbaddr_dbaddrl MMC Internal DMAC DB address [31:0] read-write idsts_dbaddru MMC internal DMAC status / DB address - HCON[ADDR_CONFIG] 32-bit(0): status, HCON[ADDR_CONFIG] 64-bit(1): DB address upper 32-bits 0x4 0x20 0x00000000 idsts_dbaddru MMC Internal DMAC status / DB address [31:0] read-write idinten_idsts64 MMC internal DMAC interrupt enable / status - HCON[ADDR_CONFIG] 32-bit(0): interrupt enable, HCON[ADDR_CONFIG] 64-bit(1): status 0x8 0x20 0x00000000 idinten_idsts64 MMC Internal DMAC interrupt enable / status [31:0] read-write dscaddr_idinten64 MMC internal DMAC DSC address / interrupt enable - HCON[ADDR_CONFIG] 32-bit(0): DSC address, HCON[ADDR_CONFIG] 64-bit(1): interrupt enable 0xC 0x20 0x00000000 dscaddr_idinten64 MMC Internal DMAC DSC address / interrupt enable [31:0] read-write bufaddr_dscaddrl MMC internal DMAC buffer address / DSC address - HCON[ADDR_CONFIG] 32-bit(0): buffer address, HCON[ADDR_CONFIG] 64-bit(1): DSC address lower 32-bits 0x10 0x20 0x00000000 bufaddr_dscaddrl MMC Internal DMAC buffer address / DSC address [31:0] read-write dscaddru MMC internal DMAC reserved / DSC address - HCON[ADDR_CONFIG] 32-bit(0): reserved, HCON[ADDR_CONFIG] 64-bit(1): DSC address upper 32-bits 0x14 0x20 0x00000000 dscaddru MMC Internal DMAC reserved / DSC address [31:0] read-write 2 0x4 l,u bufaddr[%s] MMC internal DMAC reserved / buffer address - HCON[ADDR_CONFIG] 32-bit(0): reserved, HCON[ADDR_CONFIG] 64-bit(1): buffer address lower/upper 32-bits 0x18 0x20 0x00000000 bufaddr MMC Internal DMAC reserved / buffer address [31:0] read-write cdthrctl MMC card detect threshold control 0x100 0x20 0x00000000 rd_thr_en MMC card detect read threshold enable [0:0] read-write wr_thr_en MMC card detect write threshold enable [2:2] read-write thld MMC card detect threshold [27:16] read-write 0 4095 uhs_reg_ext MMC UHS regulator extended 0x108 0x20 0x00000000 smpl_phase MMC drive and sample phase [20:16] read-write 0 31 1024 0x4 data[%s] MMC FIFO data 0x200 0x20 0x00000000 data MMC FIFO data [31:0] read-write 0 4294967295 mmc1 Synopsys DesignWare MMC (jh7110): mmc1 0x16020000 0x0 0x10000 registers MMC1 75 ctrl MMC Control 0x0 0x20 0x00000000 3 0x1 _mmc,_fifo,_dma reset[%s] MMC Control Reset [0:0] read-write 2 0x1 _int,_dma enable[%s] MMC Control Enable [4:4] read-write read_wait MMC Control Read Wait [6:6] read-write send_irq_resp MMC Control Send IRQ Response [7:7] read-write abrt_read_data MMC Control Abort Read Data [8:8] read-write 2 0x1 _ccsd,_as_ccsd send[%s] MMC Control Send [9:9] read-write ceata_int_en MMC Control CEATA Interrupt Enable [11:11] read-write use_idmac MMC Control Use IDMAC [25:25] read-write pwren MMC Power Enable 0x4 0x20 0x00000000 pwren MMC Power Enable [31:0] read-write 0 4294967295 clk_ctrl MMC Clock Control registers 0x8 2 0x4 div,src clk[%s] MMC Clock Configuration - 0: clkdiv, 1: clksrc 0x0 0x20 0x00000000 clk MMC Clock Configuration [31:0] read-write 0 4294967295 clken MMC Clock Enable 0x8 0x20 0x00000000 enable MMC Clock Enable [0:0] read-write low_pwr MMC Clock Enable Low Power [16:16] read-write tmout MMC Timeout 0x14 0x20 0x00000000 resp MMC Response Timeout [7:0] read-write 0 255 data MMC Data Timeout [31:8] read-write 0 16777215 ctype MMC card type 0x18 0x20 0x00000000 ctype MMC card type [16:0] read-write true type1 1-bit serial transfer MMC card type. 0 type4 4-bit serial transfer MMC card type. 1 type8 8-bit serial transfer MMC card type. 65536 blksiz MMC block size 0x1C 0x20 0x00000000 blksiz MMC block size [15:0] read-write 0 65535 bytcnt MMC byte count 0x20 0x20 0x00000000 bytcnt MMC byte count [31:0] read-write 0 4294967295 intmask MMC interrupt mask 0x24 0x20 0x00000000 32 0x1 _cd,_resp_err,_cmd_done,_data_over,_txdr,_rxdr,_rcrc,_dcrc,_rto,_drto,_hto_volt_switch,_frun,_hle,_sbe,_acd,_ebe,_sdio0,_sdio1,_sdio2,_sdio3,_sdio4,_sdio5,_sdio6,_sdio7,_sdio8,_sdio9,_sdio10,_sdio11,_sdio12,_sdio13,_sdio14,_sdio15 int[%s] MMC interrupt mask and status [0:0] read-write cmdarg MMC command argument 0x28 0x20 0x00000000 cmdarg MMC command argument [31:0] read-write 0 4294967295 cmd MMC command 0x2C 0x20 0x00000000 indx MMC command index [4:0] read-write 0 31 3 0x1 _exp,_long,_crc resp[%s] MMC command response [6:6] read-write 2 0x1 _exp,_wr dat[%s] MMC command data [9:9] read-write strm_mode MMC command stream mode [11:11] read-write send_stop MMC command send stop [12:12] read-write prv_data_wait MMC command private data wait [13:13] read-write stop MMC command stop [14:14] read-write init MMC command init [15:15] read-write upd_clk MMC command update clock [21:21] read-write ceata_rd MMC command CEATA read [22:22] read-write ccs_exp MMC command CCS EXP [23:23] read-write volt_switch MMC command volt switch [28:28] read-write use_hold_reg MMC command use hold register [29:29] read-write start MMC command start [31:31] read-write 4 0x4 resp[%s] MMC response 0x30 0x20 0x00000000 resp MMC response [31:0] read-write 0 4294967295 mintsts MMC MINT status 0x40 0x20 0x00000000 32 0x1 _cd,_resp_err,_cmd_done,_data_over,_txdr,_rxdr,_rcrc,_dcrc,_rto,_drto,_hto_volt_switch,_frun,_hle,_sbe,_acd,_ebe,_sdio0,_sdio1,_sdio2,_sdio3,_sdio4,_sdio5,_sdio6,_sdio7,_sdio8,_sdio9,_sdio10,_sdio11,_sdio12,_sdio13,_sdio14,_sdio15 int[%s] MMC MINT status [0:0] read-write rintsts MMC RINT status 0x44 0x20 0x00000000 32 0x1 _cd,_resp_err,_cmd_done,_data_over,_txdr,_rxdr,_rcrc,_dcrc,_rto,_drto,_hto_volt_switch,_frun,_hle,_sbe,_acd,_ebe,_sdio0,_sdio1,_sdio2,_sdio3,_sdio4,_sdio5,_sdio6,_sdio7,_sdio8,_sdio9,_sdio10,_sdio11,_sdio12,_sdio13,_sdio14,_sdio15 int[%s] MMC RINT status [0:0] read-write status MMC status 0x48 0x20 0x00000000 busy MMC busy [9:9] read-write fcnt MMC FCNT [29:17] read-write 0 8191 dma_req MMC DMA request [31:31] read-write fifoth MMC FIFOTH 0x4C 0x20 0x00000000 tx_wmark MMC FIFOTH TX watermark [11:0] read-write 0 4095 rx_wmark MMC FIFOTH RX watermark [27:16] read-write 0 4095 msize MMC FIFOTH msize [30:28] read-write 0 7 cdetect MMC card detect 0x50 0x20 0x00000000 32 0x1 slot[%s] MMC card present in slot [0:0] read-write true present MMC card present in slot 0 not_present MMC card not present in slot 1 wrtprt MMC write protect 0x54 0x20 0x00000000 32 0x1 protect[%s] MMC card slot write protect [0:0] read-write true no_protect MMC card slot no write protect 0 protect MMC card slot write protect 1 gpio MMC GPIO 0x58 0x20 0x00000000 gpio MMC GPIO [31:0] read-write 0 4294967295 2 0x4 tcb,tbb cnt[%s] MMC count 0x5C 0x20 0x00000000 cnt MMC count [31:0] read-write 0 4294967295 debnce MMC debounce 0x64 0x20 0x00000000 debnce MMC debounce [31:0] read-write 0 4294967295 id MMC ID registers 0x68 usrid MMC user ID 0x0 0x20 0x00000000 usrid MMC user ID [31:0] read-write 0 4294967295 verid MMC version ID 0x4 0x20 0x00000000 verid MMC version ID [15:0] read-write 0 65535 hcon MMC HCON 0x70 0x20 0x00000000 slot_num MMC slot number [5:1] read-write true slot0 MMC slot 0 0 slot1 MMC slot 1 1 slot2 MMC slot 2 2 slot3 MMC slot 3 3 slot4 MMC slot 4 4 slot5 MMC slot 5 5 slot6 MMC slot 6 6 slot7 MMC slot 7 7 slot8 MMC slot 8 8 slot9 MMC slot 9 9 slot10 MMC slot 10 10 slot11 MMC slot 11 11 slot12 MMC slot 12 12 slot13 MMC slot 13 13 slot14 MMC slot 14 14 slot15 MMC slot 15 15 slot16 MMC slot 16 16 slot17 MMC slot 17 17 slot18 MMC slot 18 18 slot19 MMC slot 19 19 slot20 MMC slot 20 20 slot21 MMC slot 21 21 slot22 MMC slot 22 22 slot23 MMC slot 23 23 slot24 MMC slot 24 24 slot25 MMC slot 25 25 slot26 MMC slot 26 26 slot27 MMC slot 27 27 slot28 MMC slot 28 28 slot29 MMC slot 29 29 slot30 MMC slot 30 30 slot31 MMC slot 31 31 hdata_width MMC HDATA width [9:7] read-write 0 7 trans_mode MMC transfer mode [17:16] read-write true idma No DMA interface - using internal DMA block 0 dwdma DesignWare DMA interface 1 gdma Generic DMA interface 2 nodma Non-DesignWare DMA interface - pio only 3 addr_config MMC address config [27:27] read-write true addr32 IDMAC 32-bit address 0 addr64 IDMAC 64-bit address 1 uhs_reg MMC UHS-1 regulator 0x74 0x20 0x00000000 32 0x1 voltage[%s] MMC slot signal voltage [0:0] read-write true v33 MMC slot 3.3v signal voltage 0 v18 MMC slot 1.8v signal voltage 1 rst_n MMC Reset 0x78 0x20 0x00000000 32 0x1 rst_n[%s] MMC Reset [0:0] read-write true hwinactive MMC hardware inactive 0 hwactive MMC hardware active 1 bmod MMC DMAC bus mode 0x80 0x20 0x00000000 swreset MMC internal DMAC software reset [0:0] read-write fb MMC internal DMAC FB [1:1] read-write enable MMC internal DMAC enable [7:7] read-write pldmnd MMC PLDMND 0x84 0x20 0x00000000 start MMC Internal DMAC start [0:0] read-write idmac_addr MMC Internal DMAC Address registers 0x88 dbaddr_dbaddrl MMC internal DMAC DB address - HCON[ADDR_CONFIG] 32-bit(0): DB address, HCON[ADDR_CONFIG] 64-bit(1): DB address lower 32-bits 0x0 0x20 0x00000000 dbaddr_dbaddrl MMC Internal DMAC DB address [31:0] read-write idsts_dbaddru MMC internal DMAC status / DB address - HCON[ADDR_CONFIG] 32-bit(0): status, HCON[ADDR_CONFIG] 64-bit(1): DB address upper 32-bits 0x4 0x20 0x00000000 idsts_dbaddru MMC Internal DMAC status / DB address [31:0] read-write idinten_idsts64 MMC internal DMAC interrupt enable / status - HCON[ADDR_CONFIG] 32-bit(0): interrupt enable, HCON[ADDR_CONFIG] 64-bit(1): status 0x8 0x20 0x00000000 idinten_idsts64 MMC Internal DMAC interrupt enable / status [31:0] read-write dscaddr_idinten64 MMC internal DMAC DSC address / interrupt enable - HCON[ADDR_CONFIG] 32-bit(0): DSC address, HCON[ADDR_CONFIG] 64-bit(1): interrupt enable 0xC 0x20 0x00000000 dscaddr_idinten64 MMC Internal DMAC DSC address / interrupt enable [31:0] read-write bufaddr_dscaddrl MMC internal DMAC buffer address / DSC address - HCON[ADDR_CONFIG] 32-bit(0): buffer address, HCON[ADDR_CONFIG] 64-bit(1): DSC address lower 32-bits 0x10 0x20 0x00000000 bufaddr_dscaddrl MMC Internal DMAC buffer address / DSC address [31:0] read-write dscaddru MMC internal DMAC reserved / DSC address - HCON[ADDR_CONFIG] 32-bit(0): reserved, HCON[ADDR_CONFIG] 64-bit(1): DSC address upper 32-bits 0x14 0x20 0x00000000 dscaddru MMC Internal DMAC reserved / DSC address [31:0] read-write 2 0x4 l,u bufaddr[%s] MMC internal DMAC reserved / buffer address - HCON[ADDR_CONFIG] 32-bit(0): reserved, HCON[ADDR_CONFIG] 64-bit(1): buffer address lower/upper 32-bits 0x18 0x20 0x00000000 bufaddr MMC Internal DMAC reserved / buffer address [31:0] read-write cdthrctl MMC card detect threshold control 0x100 0x20 0x00000000 rd_thr_en MMC card detect read threshold enable [0:0] read-write wr_thr_en MMC card detect write threshold enable [2:2] read-write thld MMC card detect threshold [27:16] read-write 0 4095 uhs_reg_ext MMC UHS regulator extended 0x108 0x20 0x00000000 smpl_phase MMC drive and sample phase [20:16] read-write 0 31 1024 0x4 data[%s] MMC FIFO data 0x200 0x20 0x00000000 data MMC FIFO data [31:0] read-write 0 4294967295 gmac0 Synopsys DesignWare Gigabit Ethernet MAC: gmac0 0x16030000 0x0 0x10000 registers MACIRQ0 7 ETH_WAKE_IRQ0 6 ETH_LPI0 5 config MAC Configuration 0x0 0x20 0x00000000 re Receive Enable [0:0] read-write te Transmit Enable [1:1] read-write dcrs DCRS [9:9] read-write lm Loopback Mode [12:12] read-write dm Duplex Mode [13:13] read-write speed Ethernet Speed [15:14] read-write true speed10 Speed 10 Mbits 2 speed100 Speed 100 Mbits 3 speed1000 Speed 1000 Mbits 0 speed2500 Speed 2500 Mbits 1 je JE [16:16] read-write jd JD [17:17] read-write be BE [18:18] read-write acs ACS [20:20] read-write p2k Packet 2KB [22:22] read-write ipg IPG [26:24] read-write 0 7 ipc IPC [27:27] read-write sarc SARC [30:28] read-write 0 7 arpen ARP Enable [31:31] read-write ext_config MAC Extended Configuration 0x4 0x20 0x00000000 hdsms HDSMS [22:20] read-write 0 7 eipg_en EIPG Enable [24:24] read-write eipg EIPG [29:25] read-write 0 31 packet_filter MAC Packet Filter 0x8 0x20 0x00000000 pr PR [0:0] read-write hmc HMC [2:2] read-write pm PM [4:4] read-write pcf PCF [7:7] read-write hpf HPF [10:10] read-write vtfe VTFE [16:16] read-write ipfe IPFE [20:20] read-write ra RA [31:31] read-write 8 0x4 hash_table[%s] MAC Hash Table 0x10 0x20 0x00000000 hash_table MAC Hash Table [31:0] read-write 0 4294967295 vlan_tag MAC VLAN Tag 0x50 0x20 0x00000000 ob VLAN OB [0:0] read-write ct VLAN CT [1:1] read-write ofs VLAN OFS [6:2] read-write 0 31 vid VLAN Tag VID [15:0] read-only etv VLAN Tag ETV [16:16] read-write dovltc VLAN Tag DOVLTC [20:20] read-write evls VLAN EVLS [22:21] read-write true strip_none Strip none 0 strip_pass Strip pass 1 strip_fail Strip fail 2 strip_all Strip all 3 evlrxs VLAN EVLRXS [24:24] read-write vthm VLAN VTHM [25:25] read-write edvlp VLAN EDVLP [26:26] read-write vlan_tag_data MAC VLAN Tag Data 0x54 0x20 0x00000000 vid VLAN Tag Data VID [15:0] read-only ven VLAN Tag Data Enable [16:16] read-write etv VLAN Tag Data ETV [17:17] read-write vlan_hash_table MAC VLAN Hash Table 0x58 0x20 0x00000000 vlht VLAN Hash Table [15:0] read-write 0 65535 vlan MAC VLAN 0x60 0x20 0x00000000 vlht VLAN Hash Table ID [15:0] read-write 0 65535 vlc VLAN VLC [17:16] read-write 0 3 csvl VLAN CSVL [19:19] read-write vlti VLAN VLTI [20:20] read-write 8 0x4 tx_queue_flow_ctrl[%s] MAC TX Queue Flow Control 0x70 0x20 0x00000000 tfe Tranmission Flow Enable [1:1] read-write pt Pause Time [31:16] read-write 0 65535 rx_flow_ctrl MAC RX Flow Control 0x90 0x20 0x00000000 rfe Receive Flow Enable [0:0] read-write vff_queue_ctrl MAC EQoS VLAN Tag Filter Fail Packets Queuing 0x94 0x20 0x00000000 qe VLAN Tag Filter Fail Queue Enable [16:16] read-write vffq VLAN Tag Filter Fail Queue [19:17] read-write 0 7 2 0x4 tx_queue_priority[%s] MAC TX Queue Priority - tx_queue_priority0: queue 0-3, tx_queue_priority1: queue 4-7 0x98 0x20 0x00000000 4 0x8 priority[%s] Tranmission Queue Priority [7:0] read-write 0 255 4 0x4 rx_queue_ctrl[%s] MAC RX Queue Control 0xA0 0x20 0x00000000 avcpq AVCPQ [2:0] read-write 0 7 ptpq PTPQ [6:4] read-write 0 7 dcbcpq DCBCPQ [10:8] read-write 0 7 upq UPQ [14:12] read-write 0 7 mcbcq MCBCQ [18:16] read-write 0 7 mcbcqen MCBCQ Enable [20:20] read-write tacpqe TACPQE [21:21] read-write fprq FPRQ [26:24] read-write 0 7 int MAC Interrupt registers 0xB0 status MAC Interrupt Status 0x0 0x20 0x00000007 rgsmiis RGSMIIS [0:0] read-only pcs_link PCS Link [1:1] read-only pcs_ane PCS ANE [2:2] read-only pcs_phy PCS PHY [3:3] read-only pmt_en PMT Enable [4:4] read-only lpi_en LPI Enable [5:5] read-only tsie TSIE [12:12] read-only enable MAC Interrupt Enable 0x4 0x20 0x00001030 rgsmiis RGSMIIS [0:0] read-write pcs_link PCS Link [1:1] read-write pcs_ane PCS ANE [2:2] read-write pcs_phy PCS PHY [3:3] read-write pmt_en PMT Enable [4:4] read-write lpi_en LPI Enable [5:5] read-write tsie TSIE [12:12] read-write pmt PMT Control and Status 0xC0 0x20 0x00000000 power_event PMT Power Event [31:0] read-write true pointer_reset Pointer reset 2147483648 global_unicast Global Unicast 512 wake_up_rx_frame Wake-up Receive Frame 64 magic_frame Magic Frame 32 wake_up_frame_en Wake-up Frame Enable 4 magic_pkt_en Magic Packet Enable 2 power_down Power Down 1 lpi MAC LPI Energy Efficient Ethernet (EEE) registers 0xD0 ctrl_status MAC LPI Control and Status 0x0 0x20 0x00000000 2 0x1 en,ex tlpi[%s] Transmit LPI - 0: Entry, 1: Exit [0:0] read-write true entry Transmit LPI entry 0 exit Transmit LPI exit 1 2 0x1 en,ex rlpi[%s] Receive LPI - 0: Entry, 1: Exit [2:2] read-write true entry Receive LPI entry 0 exit Receive LPI exit 1 lpien LPI Enable [16:16] read-write pls PHY Link Status [17:17] read-write lpitxa Enable LPI TX Automate [19:19] read-write lpiate LPI Timer Enable [20:20] read-write lpitcse LPI TX Clock Stop Enable [21:21] read-write timer_ctrl MAC LPI Timer Control 0x4 0x20 0x00000000 timer_ctrl LPI Timer Control [31:0] read-write 0 4294967295 entry_timer MAC LPI Entry Timer 0x8 0x20 0x00000000 entry_timer LPI Entry Timer [31:0] read-write 0 4294967295 tic_counter_us MAC TIC Counter 1 microsecond 0xDC 0x20 0x00000000 counter TIC Counter 1 microsecond [31:0] read-write 0 4294967295 pcs PCS (AN/TBI/SGMII/RGMII) registers 0xE0 an_ctrl Auto-Negotiation Control 0x0 0x20 0x00000000 ran Restart Auto-Negotiation [9:9] read-write ane Auto-Negotiation Enable [12:12] read-write ele External Loopback Enable [14:14] read-write ecd Enable Comma Detect [16:16] read-write lr Lock to Reference [17:17] read-write sgmral SGMII RAL Control [18:18] read-write an_status Auto-Negotiation Status 0x4 0x20 0x00000000 ls Link Status - 0: down, 1: up [2:2] read-write ana Auto-Negotiation Ability [3:3] read-write anc Auto-Negotiation Complete [5:5] read-write es Extended Status [8:8] read-write 2 0x4 _adv,_lpa ane[%s] Auto-Negotiation Extend Advertisement and Link Partner Ability 0x8 0x20 0x00000000 fd ANE Full Duplex [5:5] read-write hd ANE Half Duplex [6:6] read-write pse ANE Pause [8:7] read-write rfe ANE RFE [13:12] read-write 0 3 ack ANE ACK [14:14] read-write ane_exp Auto-Negotiation Extend Expansion 0x10 0x20 0x00000000 ane_exp Auto-Negotiation Extend Expansion [31:0] read-write 0 4294967295 tbi TBI Extend Status 0x14 0x20 0x00000000 tbi TBI Extend Status [31:0] read-write 0 4294967295 phyif_ctrl_status PHY Interface Control and Status 0xF8 0x20 0x00000000 tc PHY TC [0:0] read-write lud PHY LUD [1:1] read-write smidrxs PHY SMID RXS [4:4] read-write lnkmod PHY Link Mode [16:16] read-write speed PHY Link Speed [18:17] read-write true speed2_5 PHY Link Speed 2.5 0 speed25 PHY Link Speed 25 1 speed125 PHY Link Speed 125 2 lnksts PHY Link Status [19:19] read-write jabto PHY Jabber TO [20:20] read-write falsecardet PHY False CARDET [21:21] read-write debug MAC Debug 0x114 0x20 0x00000000 rpests Receive PE Status [0:0] read-write rfcfcsts RFCFC Status [2:1] read-write 0 3 tpests Transmission PE Status [16:16] read-write tfcsts Transmission Flow Control Status [18:17] read-write true idle Transmission Flow Control Idle Status 0 wait Transmission Flow Control Wait Status 1 gen_pause Transmission Flow Control Gen Pause Status 2 xfer Transmission Flow Control Transfer Status 3 hw_feat Hardware Feature registers 0x11C features0 Hardware Features 0 0x0 0x20 0x00000000 miisel MII Select [0:0] read-write gmiisel GMII Select [1:1] read-write hdsel HD Select [2:2] read-write pcssel PCS Select [3:3] read-write vlhash VLAN Hash [4:4] read-write smasel SMA Select [5:5] read-write rwksel RWK Select [6:6] read-write mgksel MGK Select [7:7] read-write mmcsel MMC Select [8:8] read-write arpoffsel ARP Off Select [9:9] read-write tssel TS Select [12:12] read-write eeesel Energy Efficient Ethernet Select [13:13] read-write txcosel TX CO Select [14:14] read-write rxcoesel RX COE Select [16:16] read-write addmac ADD MAC [18:18] read-write savlanins SAVLANINS [27:27] read-write features1 Hardware Features 1 0x4 0x20 0x00000000 rxfifosize RX FIFO Size [4:0] read-write 0 31 txfifosize TX FIFO Size [10:6] read-write 0 31 addr64 Address 64 [15:14] read-write 0 3 sphen SPH Enable [17:17] read-write tsoen TSO Enable [18:18] read-write avsel AV Select [20:20] read-write hash_tb_sz Hash Table Size [25:24] read-write 0 3 l3l4fnum L3 L4 FNUM [30:27] read-write 0 15 features2 Hardware Features 2 0x8 0x20 0x00000000 rxqcnt RX Queue Count [3:0] read-write 0 15 txqcnt TX Queue Count [9:6] read-write 0 15 rxchcnt RX Channel Count [15:12] read-write 0 15 txchcnt TX Channel Count [21:18] read-write 0 15 ppsoutnum PPS Out Number [26:24] read-write 0 7 auxsnapnum AUX Snap Number [30:28] read-write 0 7 features3 Hardware Features 3 0xC 0x20 0x00000000 nrvf NRVF [2:0] read-write 0 7 dvlan DVLAN [5:5] read-write frpsel FRP Select [10:10] read-write frpbs FRP BS [12:11] read-write 0 3 frpes FRP ES [14:13] read-write 0 3 estsel EST Select [16:16] read-write estdep EST DEP [19:17] read-write 0 7 estwid EST WID [21:20] read-write 0 3 fpesel FPE Select [26:26] read-write tbssel TBS Select [27:27] read-write asp ASP [29:28] read-write 0 3 mdio MDIO registers 0x200 data MDIO Data 0x0 0x20 0x00000000 data MDIO Data [31:0] read-write 0 4294967295 addr MDIO Address 0x4 0x20 0x00000000 addr MDIO Address [31:0] read-write 0 4294967295 gpio_status MAC GPIO Status 0x20C 0x20 0x00000000 4 0x1 gpo[%s] MAC GPIO GPO Status [16:16] read-write arp_addr MAC ARP Address 0x210 0x20 0x00000000 arp_addr MAC ARP Address [31:0] read-write 0 4294967295 128 0x8 addr[%s] Hardware Address registers 0x300 high Hardware Address High 0x0 0x20 0x00000000 addr Hardware Address High [15:0] read-write 0 65535 dcs Hardware Address High DCS [18:16] read-write 0 7 ae Hardware Address High Address Enable [31:31] read-write low Hardware Address Low 0x4 0x20 0x00000000 addr Hardware Address Low [31:0] read-write 0 4294967295 8 0x30 l3l4[%s] MAC L3/L4 Filter registers 0x900 l3l4_ctrl L3/L4 Filter Control 0x0 0x20 0x00000000 l3pen L3 Filter PEN [0:0] read-write l3sam L3 Filter SAM [2:2] read-write l3saim L3 Filter SAIM [3:3] read-write l3dam L3 Filter DAM [4:4] read-write l3daim L3 Filter DAIM [5:5] read-write l4pen L4 Filter PEN [16:16] read-write l4spm L4 Filter SPM [18:18] read-write l4spim L4 Filter SPIM [19:19] read-write l4dpm L4 Filter DPM [20:20] read-write l4dpim L4 Filter DPIM [21:21] read-write l4_addr L4 Filter Address 0x4 0x20 0x00000000 sp L4 Filter Address SP [15:0] read-write 0 65535 dp L4 Filter Address DP [31:16] read-write 0 65535 2 0x4 l3_addr[%s] L3 Filter Address 0x10 0x20 0x00000000 addr L3 Filter Address [31:0] read-write 0 4294967295 _reserved_l3l4 Reserved 0x2C 0x20 0x00000000 timestamp MAC Timestamp 0xB20 0x20 0x00000000 auxtstrig AUX Timestamp Trigger [2:2] read-write atsns AUX Timestamp Nanosecond [29:25] read-write 0 31 2 0x4 pps_ctrl[%s] MTL PPS Control and Status - pps_ctrl0: channel 0-3 control, pps_ctrl1: channel 4-7 control 0xB70 0x20 0x00000000 cmd0 MTL PPS CMD [3:0] read-write 0 15 en0 MTL PPS EN [4:4] read-write tgtmodsel0 MTL PPS Target Mode Select [6:5] read-write 0 3 mcgren0 MTL PPS MCGR Enable [7:7] read-write cmd1 MTL PPS CMD [11:8] read-write 0 15 en1 MTL PPS EN [12:12] read-write tgtmodsel1 MTL PPS Target Mode Select [14:13] read-write 0 3 mcgren1 MTL PPS MCGR Enable [15:15] read-write cmd2 MTL PPS CMD [19:16] read-write 0 15 en2 MTL PPS EN [20:20] read-write tgtmodsel2 MTL PPS Target Mode Select [22:21] read-write 0 3 mcgren2 MTL PPS MCGR Enable [23:23] read-write cmd3 MTL PPS CMD [27:24] read-write 0 15 en3 MTL PPS EN [28:28] read-write tgtmodsel3 MTL PPS Target Mode Select [30:29] read-write 0 3 mcgren3 MTL PPS MCGR Enable [31:31] read-write 8 0x10 pps[%s] PPS registers 0xB80 target_time_sec PPS Target Time - Seconds 0x0 0x20 0x00000000 time Target Time - Seconds [31:0] read-write 0 4294967295 target_time_nsec PPS Target Time - Nanoseconds 0x4 0x20 0x00000000 time Target Time - Nanoseconds [30:0] read-write 0 2147483647 busy Target Busy [31:31] read-write interval PPS Interval 0x8 0x20 0x00000000 interval PPS Interval [31:0] read-write 0 4294967295 width PPS Width 0xC 0x20 0x00000000 width PPS Width [31:0] read-write 0 4294967295 mtl MTL registers 0xC00 operation_mode MTL Operation Mode 0x0 0x20 0x00000000 raa RAA [2:2] read-write true sp RAA SP 0 wsp RAA SP 1 schalg Scheduling Algorithm [6:5] read-write true wrr Schedule Algorithm WRR 0 wfq Schedule Algorithm WFQ 1 dwrr Schedule Algorithm DWRR 2 sp Schedule Algorithm SP 3 frpe FRPE [15:15] read-write int_status MTL Interrupt Status 0x20 0x20 0x00000000 32 0x1 queue[%s] MTL Interrupt Queue [0:0] read-write 2 0x4 rx_queue_dma[%s] MTL RX Queue DMA - rx_queue_dma0: channel 0-3, rx_queue_dma1: channel 4-7 0x30 0x20 0x00000000 4 0x8 channel[%s] RX DMA Channel [3:0] read-write 0 15 rxp MTL RXP registers 0xA0 rxp_ctrl_status MTL RXP Control and Status 0x0 0x20 0x00000000 nve MTL RXP NVE [7:0] read-write 0 255 npe MTL RXP NPE [23:16] read-write 0 255 rxpi MTL RXP Interrupt [31:31] read-write iacc MTL RXP IACC registers 0x10 ctrl_status MTL RXP IACC Control and Status 0x0 0x20 0x00000000 addr MTL IACC Address [15:0] read-write 0 65535 wrrdn MTL IACC WRRDN [16:16] read-write rxpeiee MTL IACC RXP EIEE [20:20] read-write rxpeiec MTL IACC RXP EIEC [22:21] read-write 0 3 startbusy MTL IACC Start Busy [31:31] read-write data MTL RXP IACC Data 0x4 0x20 0x00000000 data MTL RXP IACC Data [31:0] read-write 0 4294967295 ecc_ctrl MTL ECC Control 0xC0 0x20 0x00000000 mtxee MTL ECC MTX EE [0:0] read-write mrxee MTL ECC MRX EE [1:1] read-write mestee MTL ECC MEST EE [2:2] read-write mrxpee MTL ECC MRXP EE [3:3] read-write tsoee MTL ECC TSO EE [4:4] read-write meeao MTL ECC MEE AO [8:8] read-write safety_int_status MTL Safety Interrupt Status 0xC4 0x20 0x00000000 mecis MTL MEC Interrupt Status - Write 1 to clear interrupt [0:0] read-write meuis MTL MEU Interrupt Status - Write 1 to clear interrupt [1:1] read-write mcsis MTL MCS Interrupt Status - Write 1 to clear interrupt [31:31] read-write ecc_int MTL ECC Interrupt registers 0xC8 enable MTL ECC Interrupt Enable 0x0 0x20 0x00000000 txceie MTL ECC TXCE Interrupt Enable [0:0] read-write rxceie MTL ECC RXCE Interrupt Enable [4:4] read-write eceie MTL ECC ECE Interrupt Enable [8:8] read-write rpceie MTL ECC RPCE Interrupt Enable [12:12] read-write status MTL ECC Interrupt Status 0x4 0x20 0x00000000 txceis MTL ECC TXCE Interrupt Status - Write 1 to clear interrupt [0:0] read-write rxceis MTL ECC RXCE Interrupt Status - Write 1 to clear interrupt [4:4] read-write eceis MTL ECC ECE Interrupt Status - Write 1 to clear interrupt [8:8] read-write rpceis MTL ECC RPCE Interrupt Status - Write 1 to clear interrupt [12:12] read-write dpp_ctrl MTL DPP Control 0xE0 0x20 0x00000000 edpp MTL DPP EDPP [0:0] read-write ope MTL DPP OPE [1:1] read-write epsi MTL DPP EPSI [2:2] read-write 8 0x40 chan[%s] MTL Channel registers 0x100 tx_op_mode MTL Channel TX OP Mode 0x0 0x20 0x00000000 tsf MTL Channel TSF [1:1] read-write txqen_av MTL Channel TXQEN AV [2:2] read-write txqen MTL Channel TXQEN [3:3] read-write ttc MTL Channel TTC [6:4] read-write true ttc32 MTL Channel TTC 32 0 ttc64 MTL Channel TTC 64 1 ttc96 MTL Channel TTC 96 2 ttc128 MTL Channel TTC 128 3 ttc192 MTL Channel TTC 192 4 ttc256 MTL Channel TTC 256 5 ttc384 MTL Channel TTC 384 6 ttc512 MTL Channel TTC 512 7 tqs MTL Channel TQS [24:16] read-write tx_debug MTL TX Debug 0x8 0x20 0x00000000 paused MTL TX Paused [0:0] read-write trcsts MTL Debug TX FIFO Read Controller Status [2:1] read-write true idle MTL TX FIFO Idle 0 read MTL TX FIFO Read 1 wait MTL TX FIFO Wait 2 write MTL TX FIFO Write 3 ets_ctrl MTL Channel ETS Control 0x10 0x20 0x00000000 avalg MTL Channel ETS AV Algorithm [2:2] read-write cc MTL Channel ETS CC [3:3] read-write tx_queue_weight MTL Channel TX Queue Weight 0x18 0x20 0x00000000 iscqw MTL Channel ISC Queue Weight [20:0] read-write 0 2097151 send_slope_credit MTL Channel Send Slope Credit 0x1C 0x20 0x00000000 ssc MTL Channel Send Slope Credit [13:0] read-write 0 16383 2 0x4 _high,_low credit[%s] MTL Channel Credit - credit0: High, credit1: Low 0x20 0x20 0x00000000 credit MTL Channel Credit [28:0] read-write 0 536870911 int_ctrl MTL Channel Interrupt Control 0x2C 0x20 0x00000000 rx_overflow_int MTL RX Overflow Interrupt [16:16] read-write rx_overflow_int_en MTL RX Overflow Interrupt Enable [24:24] read-write rx_op_mode MTL Channel RX OP Mode 0x30 0x20 0x00000000 rsf MTL Channel RSF [5:5] read-write rfa MTL Channel RX RFA [13:8] read-write 0 63 rfd MTL Channel RX RFD [19:14] read-write 0 63 rtc MTL Channel RTC [4:3] read-write true rtc64 MTL Channel RTC 64 0 rtc32 MTL Channel RTC 32 1 rtc96 MTL Channel RTC 96 2 rtc128 MTL Channel RTC 128 3 rqs MTL Channel RQS [29:20] read-write 0 1023 rx_debug MTL RX Debug - GMII or MII Transmit Protocol Engine Status 0x38 0x20 0x00000000 rwcsts MTL RX Rreceive Write Controller Status [0:0] read-write rrcsts MTL Debug RX FIFO Read Controller Status [2:1] read-write true idle MTL RX Controller Idle 0 rdata MTL RX Controller Read Data 1 rstat MTL RX Controller Read Status 2 flush MTL RX Controller Flush 3 rxfsts MTL Debug RX FIFO Status [5:4] read-write true empty MTL RX FIFO Empty 0 bt MTL RX FIFO Below Threshold 1 at MTL RX FIFO At/Above Threshold 2 full MTL RX FIFO Full 3 _reserved_chan MTL Channel Reserved 0x3C 0x20 0x00000000 dma DMA registers 0x1080 safety_int_status DMA Safety Interrupt Status 0x0 0x20 0x00000000 decis DMA DEC Interrupt Status - Write 1 to clear interrupt [0:0] read-write deuis DMA MEU Interrupt Status - Write 1 to clear interrupt [1:1] read-write mscis DMA MSC Interrupt Status - Write 1 to clear interrupt [28:28] read-write msuis DMA MSU Interrupt Status - Write 1 to clear interrupt [29:29] read-write ecc_int DMA ECC Interrupt registers 0x4 enable DMA ECC Interrupt Enable 0x0 0x20 0x00000000 tceie MTL ECC TCE Interrupt Enable [0:0] read-write status DMA ECC Interrupt Status 0x4 0x20 0x00000000 tceis MTL ECC TCE Interrupt Status - Write 1 to clear interrupt [0:0] read-write gmac1 Synopsys DesignWare Gigabit Ethernet MAC: gmac1 0x16040000 0x0 0x10000 registers MACIRQ1 78 ETH_WAKE_IRQ1 77 ETH_LPI1 76 config MAC Configuration 0x0 0x20 0x00000000 re Receive Enable [0:0] read-write te Transmit Enable [1:1] read-write dcrs DCRS [9:9] read-write lm Loopback Mode [12:12] read-write dm Duplex Mode [13:13] read-write speed Ethernet Speed [15:14] read-write true speed10 Speed 10 Mbits 2 speed100 Speed 100 Mbits 3 speed1000 Speed 1000 Mbits 0 speed2500 Speed 2500 Mbits 1 je JE [16:16] read-write jd JD [17:17] read-write be BE [18:18] read-write acs ACS [20:20] read-write p2k Packet 2KB [22:22] read-write ipg IPG [26:24] read-write 0 7 ipc IPC [27:27] read-write sarc SARC [30:28] read-write 0 7 arpen ARP Enable [31:31] read-write ext_config MAC Extended Configuration 0x4 0x20 0x00000000 hdsms HDSMS [22:20] read-write 0 7 eipg_en EIPG Enable [24:24] read-write eipg EIPG [29:25] read-write 0 31 packet_filter MAC Packet Filter 0x8 0x20 0x00000000 pr PR [0:0] read-write hmc HMC [2:2] read-write pm PM [4:4] read-write pcf PCF [7:7] read-write hpf HPF [10:10] read-write vtfe VTFE [16:16] read-write ipfe IPFE [20:20] read-write ra RA [31:31] read-write 8 0x4 hash_table[%s] MAC Hash Table 0x10 0x20 0x00000000 hash_table MAC Hash Table [31:0] read-write 0 4294967295 vlan_tag MAC VLAN Tag 0x50 0x20 0x00000000 ob VLAN OB [0:0] read-write ct VLAN CT [1:1] read-write ofs VLAN OFS [6:2] read-write 0 31 vid VLAN Tag VID [15:0] read-only etv VLAN Tag ETV [16:16] read-write dovltc VLAN Tag DOVLTC [20:20] read-write evls VLAN EVLS [22:21] read-write true strip_none Strip none 0 strip_pass Strip pass 1 strip_fail Strip fail 2 strip_all Strip all 3 evlrxs VLAN EVLRXS [24:24] read-write vthm VLAN VTHM [25:25] read-write edvlp VLAN EDVLP [26:26] read-write vlan_tag_data MAC VLAN Tag Data 0x54 0x20 0x00000000 vid VLAN Tag Data VID [15:0] read-only ven VLAN Tag Data Enable [16:16] read-write etv VLAN Tag Data ETV [17:17] read-write vlan_hash_table MAC VLAN Hash Table 0x58 0x20 0x00000000 vlht VLAN Hash Table [15:0] read-write 0 65535 vlan MAC VLAN 0x60 0x20 0x00000000 vlht VLAN Hash Table ID [15:0] read-write 0 65535 vlc VLAN VLC [17:16] read-write 0 3 csvl VLAN CSVL [19:19] read-write vlti VLAN VLTI [20:20] read-write 8 0x4 tx_queue_flow_ctrl[%s] MAC TX Queue Flow Control 0x70 0x20 0x00000000 tfe Tranmission Flow Enable [1:1] read-write pt Pause Time [31:16] read-write 0 65535 rx_flow_ctrl MAC RX Flow Control 0x90 0x20 0x00000000 rfe Receive Flow Enable [0:0] read-write vff_queue_ctrl MAC EQoS VLAN Tag Filter Fail Packets Queuing 0x94 0x20 0x00000000 qe VLAN Tag Filter Fail Queue Enable [16:16] read-write vffq VLAN Tag Filter Fail Queue [19:17] read-write 0 7 2 0x4 tx_queue_priority[%s] MAC TX Queue Priority - tx_queue_priority0: queue 0-3, tx_queue_priority1: queue 4-7 0x98 0x20 0x00000000 4 0x8 priority[%s] Tranmission Queue Priority [7:0] read-write 0 255 4 0x4 rx_queue_ctrl[%s] MAC RX Queue Control 0xA0 0x20 0x00000000 avcpq AVCPQ [2:0] read-write 0 7 ptpq PTPQ [6:4] read-write 0 7 dcbcpq DCBCPQ [10:8] read-write 0 7 upq UPQ [14:12] read-write 0 7 mcbcq MCBCQ [18:16] read-write 0 7 mcbcqen MCBCQ Enable [20:20] read-write tacpqe TACPQE [21:21] read-write fprq FPRQ [26:24] read-write 0 7 int MAC Interrupt registers 0xB0 status MAC Interrupt Status 0x0 0x20 0x00000007 rgsmiis RGSMIIS [0:0] read-only pcs_link PCS Link [1:1] read-only pcs_ane PCS ANE [2:2] read-only pcs_phy PCS PHY [3:3] read-only pmt_en PMT Enable [4:4] read-only lpi_en LPI Enable [5:5] read-only tsie TSIE [12:12] read-only enable MAC Interrupt Enable 0x4 0x20 0x00001030 rgsmiis RGSMIIS [0:0] read-write pcs_link PCS Link [1:1] read-write pcs_ane PCS ANE [2:2] read-write pcs_phy PCS PHY [3:3] read-write pmt_en PMT Enable [4:4] read-write lpi_en LPI Enable [5:5] read-write tsie TSIE [12:12] read-write pmt PMT Control and Status 0xC0 0x20 0x00000000 power_event PMT Power Event [31:0] read-write true pointer_reset Pointer reset 2147483648 global_unicast Global Unicast 512 wake_up_rx_frame Wake-up Receive Frame 64 magic_frame Magic Frame 32 wake_up_frame_en Wake-up Frame Enable 4 magic_pkt_en Magic Packet Enable 2 power_down Power Down 1 lpi MAC LPI Energy Efficient Ethernet (EEE) registers 0xD0 ctrl_status MAC LPI Control and Status 0x0 0x20 0x00000000 2 0x1 en,ex tlpi[%s] Transmit LPI - 0: Entry, 1: Exit [0:0] read-write true entry Transmit LPI entry 0 exit Transmit LPI exit 1 2 0x1 en,ex rlpi[%s] Receive LPI - 0: Entry, 1: Exit [2:2] read-write true entry Receive LPI entry 0 exit Receive LPI exit 1 lpien LPI Enable [16:16] read-write pls PHY Link Status [17:17] read-write lpitxa Enable LPI TX Automate [19:19] read-write lpiate LPI Timer Enable [20:20] read-write lpitcse LPI TX Clock Stop Enable [21:21] read-write timer_ctrl MAC LPI Timer Control 0x4 0x20 0x00000000 timer_ctrl LPI Timer Control [31:0] read-write 0 4294967295 entry_timer MAC LPI Entry Timer 0x8 0x20 0x00000000 entry_timer LPI Entry Timer [31:0] read-write 0 4294967295 tic_counter_us MAC TIC Counter 1 microsecond 0xDC 0x20 0x00000000 counter TIC Counter 1 microsecond [31:0] read-write 0 4294967295 pcs PCS (AN/TBI/SGMII/RGMII) registers 0xE0 an_ctrl Auto-Negotiation Control 0x0 0x20 0x00000000 ran Restart Auto-Negotiation [9:9] read-write ane Auto-Negotiation Enable [12:12] read-write ele External Loopback Enable [14:14] read-write ecd Enable Comma Detect [16:16] read-write lr Lock to Reference [17:17] read-write sgmral SGMII RAL Control [18:18] read-write an_status Auto-Negotiation Status 0x4 0x20 0x00000000 ls Link Status - 0: down, 1: up [2:2] read-write ana Auto-Negotiation Ability [3:3] read-write anc Auto-Negotiation Complete [5:5] read-write es Extended Status [8:8] read-write 2 0x4 _adv,_lpa ane[%s] Auto-Negotiation Extend Advertisement and Link Partner Ability 0x8 0x20 0x00000000 fd ANE Full Duplex [5:5] read-write hd ANE Half Duplex [6:6] read-write pse ANE Pause [8:7] read-write rfe ANE RFE [13:12] read-write 0 3 ack ANE ACK [14:14] read-write ane_exp Auto-Negotiation Extend Expansion 0x10 0x20 0x00000000 ane_exp Auto-Negotiation Extend Expansion [31:0] read-write 0 4294967295 tbi TBI Extend Status 0x14 0x20 0x00000000 tbi TBI Extend Status [31:0] read-write 0 4294967295 phyif_ctrl_status PHY Interface Control and Status 0xF8 0x20 0x00000000 tc PHY TC [0:0] read-write lud PHY LUD [1:1] read-write smidrxs PHY SMID RXS [4:4] read-write lnkmod PHY Link Mode [16:16] read-write speed PHY Link Speed [18:17] read-write true speed2_5 PHY Link Speed 2.5 0 speed25 PHY Link Speed 25 1 speed125 PHY Link Speed 125 2 lnksts PHY Link Status [19:19] read-write jabto PHY Jabber TO [20:20] read-write falsecardet PHY False CARDET [21:21] read-write debug MAC Debug 0x114 0x20 0x00000000 rpests Receive PE Status [0:0] read-write rfcfcsts RFCFC Status [2:1] read-write 0 3 tpests Transmission PE Status [16:16] read-write tfcsts Transmission Flow Control Status [18:17] read-write true idle Transmission Flow Control Idle Status 0 wait Transmission Flow Control Wait Status 1 gen_pause Transmission Flow Control Gen Pause Status 2 xfer Transmission Flow Control Transfer Status 3 hw_feat Hardware Feature registers 0x11C features0 Hardware Features 0 0x0 0x20 0x00000000 miisel MII Select [0:0] read-write gmiisel GMII Select [1:1] read-write hdsel HD Select [2:2] read-write pcssel PCS Select [3:3] read-write vlhash VLAN Hash [4:4] read-write smasel SMA Select [5:5] read-write rwksel RWK Select [6:6] read-write mgksel MGK Select [7:7] read-write mmcsel MMC Select [8:8] read-write arpoffsel ARP Off Select [9:9] read-write tssel TS Select [12:12] read-write eeesel Energy Efficient Ethernet Select [13:13] read-write txcosel TX CO Select [14:14] read-write rxcoesel RX COE Select [16:16] read-write addmac ADD MAC [18:18] read-write savlanins SAVLANINS [27:27] read-write features1 Hardware Features 1 0x4 0x20 0x00000000 rxfifosize RX FIFO Size [4:0] read-write 0 31 txfifosize TX FIFO Size [10:6] read-write 0 31 addr64 Address 64 [15:14] read-write 0 3 sphen SPH Enable [17:17] read-write tsoen TSO Enable [18:18] read-write avsel AV Select [20:20] read-write hash_tb_sz Hash Table Size [25:24] read-write 0 3 l3l4fnum L3 L4 FNUM [30:27] read-write 0 15 features2 Hardware Features 2 0x8 0x20 0x00000000 rxqcnt RX Queue Count [3:0] read-write 0 15 txqcnt TX Queue Count [9:6] read-write 0 15 rxchcnt RX Channel Count [15:12] read-write 0 15 txchcnt TX Channel Count [21:18] read-write 0 15 ppsoutnum PPS Out Number [26:24] read-write 0 7 auxsnapnum AUX Snap Number [30:28] read-write 0 7 features3 Hardware Features 3 0xC 0x20 0x00000000 nrvf NRVF [2:0] read-write 0 7 dvlan DVLAN [5:5] read-write frpsel FRP Select [10:10] read-write frpbs FRP BS [12:11] read-write 0 3 frpes FRP ES [14:13] read-write 0 3 estsel EST Select [16:16] read-write estdep EST DEP [19:17] read-write 0 7 estwid EST WID [21:20] read-write 0 3 fpesel FPE Select [26:26] read-write tbssel TBS Select [27:27] read-write asp ASP [29:28] read-write 0 3 mdio MDIO registers 0x200 data MDIO Data 0x0 0x20 0x00000000 data MDIO Data [31:0] read-write 0 4294967295 addr MDIO Address 0x4 0x20 0x00000000 addr MDIO Address [31:0] read-write 0 4294967295 gpio_status MAC GPIO Status 0x20C 0x20 0x00000000 4 0x1 gpo[%s] MAC GPIO GPO Status [16:16] read-write arp_addr MAC ARP Address 0x210 0x20 0x00000000 arp_addr MAC ARP Address [31:0] read-write 0 4294967295 128 0x8 addr[%s] Hardware Address registers 0x300 high Hardware Address High 0x0 0x20 0x00000000 addr Hardware Address High [15:0] read-write 0 65535 dcs Hardware Address High DCS [18:16] read-write 0 7 ae Hardware Address High Address Enable [31:31] read-write low Hardware Address Low 0x4 0x20 0x00000000 addr Hardware Address Low [31:0] read-write 0 4294967295 8 0x30 l3l4[%s] MAC L3/L4 Filter registers 0x900 l3l4_ctrl L3/L4 Filter Control 0x0 0x20 0x00000000 l3pen L3 Filter PEN [0:0] read-write l3sam L3 Filter SAM [2:2] read-write l3saim L3 Filter SAIM [3:3] read-write l3dam L3 Filter DAM [4:4] read-write l3daim L3 Filter DAIM [5:5] read-write l4pen L4 Filter PEN [16:16] read-write l4spm L4 Filter SPM [18:18] read-write l4spim L4 Filter SPIM [19:19] read-write l4dpm L4 Filter DPM [20:20] read-write l4dpim L4 Filter DPIM [21:21] read-write l4_addr L4 Filter Address 0x4 0x20 0x00000000 sp L4 Filter Address SP [15:0] read-write 0 65535 dp L4 Filter Address DP [31:16] read-write 0 65535 2 0x4 l3_addr[%s] L3 Filter Address 0x10 0x20 0x00000000 addr L3 Filter Address [31:0] read-write 0 4294967295 _reserved_l3l4 Reserved 0x2C 0x20 0x00000000 timestamp MAC Timestamp 0xB20 0x20 0x00000000 auxtstrig AUX Timestamp Trigger [2:2] read-write atsns AUX Timestamp Nanosecond [29:25] read-write 0 31 2 0x4 pps_ctrl[%s] MTL PPS Control and Status - pps_ctrl0: channel 0-3 control, pps_ctrl1: channel 4-7 control 0xB70 0x20 0x00000000 cmd0 MTL PPS CMD [3:0] read-write 0 15 en0 MTL PPS EN [4:4] read-write tgtmodsel0 MTL PPS Target Mode Select [6:5] read-write 0 3 mcgren0 MTL PPS MCGR Enable [7:7] read-write cmd1 MTL PPS CMD [11:8] read-write 0 15 en1 MTL PPS EN [12:12] read-write tgtmodsel1 MTL PPS Target Mode Select [14:13] read-write 0 3 mcgren1 MTL PPS MCGR Enable [15:15] read-write cmd2 MTL PPS CMD [19:16] read-write 0 15 en2 MTL PPS EN [20:20] read-write tgtmodsel2 MTL PPS Target Mode Select [22:21] read-write 0 3 mcgren2 MTL PPS MCGR Enable [23:23] read-write cmd3 MTL PPS CMD [27:24] read-write 0 15 en3 MTL PPS EN [28:28] read-write tgtmodsel3 MTL PPS Target Mode Select [30:29] read-write 0 3 mcgren3 MTL PPS MCGR Enable [31:31] read-write 8 0x10 pps[%s] PPS registers 0xB80 target_time_sec PPS Target Time - Seconds 0x0 0x20 0x00000000 time Target Time - Seconds [31:0] read-write 0 4294967295 target_time_nsec PPS Target Time - Nanoseconds 0x4 0x20 0x00000000 time Target Time - Nanoseconds [30:0] read-write 0 2147483647 busy Target Busy [31:31] read-write interval PPS Interval 0x8 0x20 0x00000000 interval PPS Interval [31:0] read-write 0 4294967295 width PPS Width 0xC 0x20 0x00000000 width PPS Width [31:0] read-write 0 4294967295 mtl MTL registers 0xC00 operation_mode MTL Operation Mode 0x0 0x20 0x00000000 raa RAA [2:2] read-write true sp RAA SP 0 wsp RAA SP 1 schalg Scheduling Algorithm [6:5] read-write true wrr Schedule Algorithm WRR 0 wfq Schedule Algorithm WFQ 1 dwrr Schedule Algorithm DWRR 2 sp Schedule Algorithm SP 3 frpe FRPE [15:15] read-write int_status MTL Interrupt Status 0x20 0x20 0x00000000 32 0x1 queue[%s] MTL Interrupt Queue [0:0] read-write 2 0x4 rx_queue_dma[%s] MTL RX Queue DMA - rx_queue_dma0: channel 0-3, rx_queue_dma1: channel 4-7 0x30 0x20 0x00000000 4 0x8 channel[%s] RX DMA Channel [3:0] read-write 0 15 rxp MTL RXP registers 0xA0 rxp_ctrl_status MTL RXP Control and Status 0x0 0x20 0x00000000 nve MTL RXP NVE [7:0] read-write 0 255 npe MTL RXP NPE [23:16] read-write 0 255 rxpi MTL RXP Interrupt [31:31] read-write iacc MTL RXP IACC registers 0x10 ctrl_status MTL RXP IACC Control and Status 0x0 0x20 0x00000000 addr MTL IACC Address [15:0] read-write 0 65535 wrrdn MTL IACC WRRDN [16:16] read-write rxpeiee MTL IACC RXP EIEE [20:20] read-write rxpeiec MTL IACC RXP EIEC [22:21] read-write 0 3 startbusy MTL IACC Start Busy [31:31] read-write data MTL RXP IACC Data 0x4 0x20 0x00000000 data MTL RXP IACC Data [31:0] read-write 0 4294967295 ecc_ctrl MTL ECC Control 0xC0 0x20 0x00000000 mtxee MTL ECC MTX EE [0:0] read-write mrxee MTL ECC MRX EE [1:1] read-write mestee MTL ECC MEST EE [2:2] read-write mrxpee MTL ECC MRXP EE [3:3] read-write tsoee MTL ECC TSO EE [4:4] read-write meeao MTL ECC MEE AO [8:8] read-write safety_int_status MTL Safety Interrupt Status 0xC4 0x20 0x00000000 mecis MTL MEC Interrupt Status - Write 1 to clear interrupt [0:0] read-write meuis MTL MEU Interrupt Status - Write 1 to clear interrupt [1:1] read-write mcsis MTL MCS Interrupt Status - Write 1 to clear interrupt [31:31] read-write ecc_int MTL ECC Interrupt registers 0xC8 enable MTL ECC Interrupt Enable 0x0 0x20 0x00000000 txceie MTL ECC TXCE Interrupt Enable [0:0] read-write rxceie MTL ECC RXCE Interrupt Enable [4:4] read-write eceie MTL ECC ECE Interrupt Enable [8:8] read-write rpceie MTL ECC RPCE Interrupt Enable [12:12] read-write status MTL ECC Interrupt Status 0x4 0x20 0x00000000 txceis MTL ECC TXCE Interrupt Status - Write 1 to clear interrupt [0:0] read-write rxceis MTL ECC RXCE Interrupt Status - Write 1 to clear interrupt [4:4] read-write eceis MTL ECC ECE Interrupt Status - Write 1 to clear interrupt [8:8] read-write rpceis MTL ECC RPCE Interrupt Status - Write 1 to clear interrupt [12:12] read-write dpp_ctrl MTL DPP Control 0xE0 0x20 0x00000000 edpp MTL DPP EDPP [0:0] read-write ope MTL DPP OPE [1:1] read-write epsi MTL DPP EPSI [2:2] read-write 8 0x40 chan[%s] MTL Channel registers 0x100 tx_op_mode MTL Channel TX OP Mode 0x0 0x20 0x00000000 tsf MTL Channel TSF [1:1] read-write txqen_av MTL Channel TXQEN AV [2:2] read-write txqen MTL Channel TXQEN [3:3] read-write ttc MTL Channel TTC [6:4] read-write true ttc32 MTL Channel TTC 32 0 ttc64 MTL Channel TTC 64 1 ttc96 MTL Channel TTC 96 2 ttc128 MTL Channel TTC 128 3 ttc192 MTL Channel TTC 192 4 ttc256 MTL Channel TTC 256 5 ttc384 MTL Channel TTC 384 6 ttc512 MTL Channel TTC 512 7 tqs MTL Channel TQS [24:16] read-write tx_debug MTL TX Debug 0x8 0x20 0x00000000 paused MTL TX Paused [0:0] read-write trcsts MTL Debug TX FIFO Read Controller Status [2:1] read-write true idle MTL TX FIFO Idle 0 read MTL TX FIFO Read 1 wait MTL TX FIFO Wait 2 write MTL TX FIFO Write 3 ets_ctrl MTL Channel ETS Control 0x10 0x20 0x00000000 avalg MTL Channel ETS AV Algorithm [2:2] read-write cc MTL Channel ETS CC [3:3] read-write tx_queue_weight MTL Channel TX Queue Weight 0x18 0x20 0x00000000 iscqw MTL Channel ISC Queue Weight [20:0] read-write 0 2097151 send_slope_credit MTL Channel Send Slope Credit 0x1C 0x20 0x00000000 ssc MTL Channel Send Slope Credit [13:0] read-write 0 16383 2 0x4 _high,_low credit[%s] MTL Channel Credit - credit0: High, credit1: Low 0x20 0x20 0x00000000 credit MTL Channel Credit [28:0] read-write 0 536870911 int_ctrl MTL Channel Interrupt Control 0x2C 0x20 0x00000000 rx_overflow_int MTL RX Overflow Interrupt [16:16] read-write rx_overflow_int_en MTL RX Overflow Interrupt Enable [24:24] read-write rx_op_mode MTL Channel RX OP Mode 0x30 0x20 0x00000000 rsf MTL Channel RSF [5:5] read-write rfa MTL Channel RX RFA [13:8] read-write 0 63 rfd MTL Channel RX RFD [19:14] read-write 0 63 rtc MTL Channel RTC [4:3] read-write true rtc64 MTL Channel RTC 64 0 rtc32 MTL Channel RTC 32 1 rtc96 MTL Channel RTC 96 2 rtc128 MTL Channel RTC 128 3 rqs MTL Channel RQS [29:20] read-write 0 1023 rx_debug MTL RX Debug - GMII or MII Transmit Protocol Engine Status 0x38 0x20 0x00000000 rwcsts MTL RX Rreceive Write Controller Status [0:0] read-write rrcsts MTL Debug RX FIFO Read Controller Status [2:1] read-write true idle MTL RX Controller Idle 0 rdata MTL RX Controller Read Data 1 rstat MTL RX Controller Read Status 2 flush MTL RX Controller Flush 3 rxfsts MTL Debug RX FIFO Status [5:4] read-write true empty MTL RX FIFO Empty 0 bt MTL RX FIFO Below Threshold 1 at MTL RX FIFO At/Above Threshold 2 full MTL RX FIFO Full 3 _reserved_chan MTL Channel Reserved 0x3C 0x20 0x00000000 dma DMA registers 0x1080 safety_int_status DMA Safety Interrupt Status 0x0 0x20 0x00000000 decis DMA DEC Interrupt Status - Write 1 to clear interrupt [0:0] read-write deuis DMA MEU Interrupt Status - Write 1 to clear interrupt [1:1] read-write mscis DMA MSC Interrupt Status - Write 1 to clear interrupt [28:28] read-write msuis DMA MSU Interrupt Status - Write 1 to clear interrupt [29:29] read-write ecc_int DMA ECC Interrupt registers 0x4 enable DMA ECC Interrupt Enable 0x0 0x20 0x00000000 tceie MTL ECC TCE Interrupt Enable [0:0] read-write status DMA ECC Interrupt Status 0x4 0x20 0x00000000 tceis MTL ECC TCE Interrupt Status - Write 1 to clear interrupt [0:0] read-write dma Synopsys DesignWare AXI DMAC: dma 0x16050000 0x0 0x10000 registers DMA 73 dmac DesignWare DMAC registers 0x0 id DMAC ID register contains the 64-bit identification value. 0x0 0x40 0x00000000 id DMAC ID value [63:0] read-only compver DMAC Component Version register contains the 32-bit component version. 0x8 0x40 0x00000000 compver DMAC Component Version value [31:0] read-only cfg DMAC Configuration register contains the DMAC config settings. 0x10 0x40 0x00000000 en DMAC Enable value - 0: disable DMAC, 1: enable DMAC [0:0] read-write ie DMAC Interrupt Enable value - 0: disable interrupt, 1: enable interrupt [1:1] read-write chen DMAC Channel Enable register contains the DMAC channel enable settings. Only exists when DMAX_NUM_CHANNELS <= 8. 0x18 0x40 0x00000000 4 0x1 1-4 en_ch[%s] DMAC Channel Enable - 0: disable DMAC channel, 1: enable DMAC channel [0:0] read-write 4 0x1 1-4 en_we_ch[%s] DMAC Channel Enable Write-enable - 0: disable write to DMAC channel enable bit, 1: enable write to DMAC channel enable bit [8:8] write-only 4 0x1 1-4 susp_ch[%s] DMAC Channel Suspend - 0: no DMAC channel suspend request, 1: DMAC channel suspend request [16:16] read-write 4 0x1 1-4 susp_we_ch[%s] DMAC Channel Suspend Write-enable - 0: disable write to DMAC channel suspend bit, 1: enable write to DMAC channel suspend bit [24:24] write-only 4 0x1 1-4 abort_ch[%s] DMAC Channel Abort - 0: no DMAC channel abort request, 1: request DMAC channel abort. Memory access depends on DMAX_CH_ABORT_EN configuration setting - 0: read-only, 1: read-write [32:32] read-write 4 0x1 1-4 abort_we_ch[%s] DMAC Channel Abort Write-enable - 0: disable write to DMAC channel abort bit, 1: enable write DMAC channel abort. Memory access depends on DMAX_CH_ABORT_EN configuration setting - 0: read-only, 1: write-only [40:40] read-write chsusp DMAC Channel Suspend register contains the DMAC channel suspend settings. Only exists when DMAX_NUM_CHANNELS > 8 0x20 0x40 0x00000000 chabort DMAC Channel Abort register contains the DMAC channel abort settings. Only exists when DMAX_NUM_CHANNELS > 8 0x28 0x40 0x00000000 intstatus DMAC Interrupt Status register contains the DMAC interrupt status. Only exists when DMAX_NUM_CHANNELS <= 8 0x30 0x40 0x00000000 4 0x1 1-4 intstat_ch[%s] DMAC Channel Interrupt Status - 0: interrupt inactive, 1: interrupt active [0:0] read-only common_intstat DMAC Common Interrupt Status - 0: interrupt inactive, 1: interrupt active [16:16] read-only common DesignWare DMAC Common registers 0x38 intclear DMAC Interrupt Clear register contains the DMAC interrupt clear settings. 0x0 0x40 0x00000000 9 0x1 _dec_err,_wr2_ro_err,_rd2_wo_err,_wron_hold_err,_rsvd0,_rsvd1,_rsvd2,_rsvd3,_undef_reg_dec_err slv_if[%s] DMAC Channel Interrupt Clear Slave Interface - 0: no-op, 1: clear interrupt [0:0] write-only intstatus_enable DMAC Interrupt Status Enable register contains the DMAC interrupt status enable settings. 0x8 0x40 0x00000000 9 0x1 _dec_err,_wr2_ro_err,_rd2_wo_err,_wron_hold_err,_rsvd0,_rsvd1,_rsvd2,_rsvd3,_undef_reg_dec_err slv_if[%s] DMAC Channel Interrupt Status Enable Slave Interface - 0: disable interrupt status, 1: enable interrupt status [0:0] read-write intsignal_enable DMAC Interrupt Signal Enable register contains the DMAC interrupt signal enable settings. 0x10 0x40 0x00000000 9 0x1 _dec_err,_wr2_ro_err,_rd2_wo_err,_wron_hold_err,_rsvd0,_rsvd1,_rsvd2,_rsvd3,_undef_reg_dec_err slv_if[%s] DMAC Channel Interrupt Signal Enable Slave Interface - 0: disable interrupt signal, 1: enable interrupt signal [0:0] read-write intstatus DMAC Interrupt Status register contains the DMAC interrupt status. 0x18 0x40 0x00000000 9 0x1 _dec_err,_wr2_ro_err,_rd2_wo_err,_wron_hold_err,_rsvd0,_rsvd1,_rsvd2,_rsvd3,_undef_reg_dec_err slv_if[%s] DMAC Channel Interrupt Status Slave Interface - 0: no interrupt, 1: interrupt active [0:0] read-only reset DMAC Channel Interrupt Status register contains the DMAC channel interrupt status 0x58 0x40 0x00000000 rst DMAC Reset - 0: no-op, 1: request reset. **NOTE** Software is not allowed to write 0 to this bit. [0:0] read-write lowpower_cfg DMAC Low Power Configuration register. 0x60 0x40 0x00000000 4 0x1 _gbl,_chnl,_sbiu,_mxif clsp_en[%s] DMAC Context Sensitive Low Power feature enable - 0: disable, 1: enable. GBL: Global, CHNL: Channel, SBIU: SBIU, MXI: AXI Master Interface [0:0] read-write 3 0x8 _glch,_sbiu,_mxif lpdly[%s] DMAC Low Power Delay counter. GLCH: Global and DMA channel, SBIU: SBIU, MXI: AXI Master Interface [39:32] read-write 0 255 _reserved_dmac DMAC Reserved register. 0xF8 0x40 0x00000000 4 0x100 1-4 ch[%s] DesignWare DMAC Channel registers 0x100 sar DMAC Channel Source address of DMA transfer. 0x0 0x40 0x00000000 sar Source address of DMA transfer [63:0] read-write 0 18446744073709551615 dar DMAC Channel Destination address of DMA transfer. 0x8 0x40 0x00000000 dar Destination address of DMA transfer [63:0] read-write 0 18446744073709551615 block_ts DMAC Block transfer size. 0x10 0x40 0x00000000 block_ts Block transfer size of DMA transfer [21:0] read-write 0 4194303 ctl DMAC Channel Control. 0x18 0x40 0x00000000 sms Source Master Select - 0: AXI Master 1, 1: AXI Master 2 [0:0] read-write true axi_master1 Select AXI master 1 0 axi_master2 Select AXI master 2 1 dms Destination Master Select - 0: AXI Master 1, 1: AXI Master 2 [2:2] read-write true axi_master1 Select AXI master 1 0 axi_master2 Select AXI master 2 1 sinc Source address increment - 0: increment, 1: no change. Indicates whether to increment the address on every transfer. [4:4] read-write true increment Enable source address increment on every transfer 0 no_change Do not enable source address increment on every transfer 1 dinc Destination address increment - 0: increment, 1: no change. Indicates whether to increment the address on every transfer. [6:6] read-write true increment Enable source address increment on every transfer 0 no_change Do not enable source address increment on every transfer 1 2 0x3 _src,_dst tr_width[%s] Transfer width - 0: 8-bits, 1: 16-bits, 2: 32-bits, 3: 64-bits, 4: 128-bits, 5: 256-bits, 6: 512-bits. [10:8] read-write true bits8 8-bit transfer width 0 bits16 16-bit transfer width 1 bits32 32-bit transfer width 2 bits64 64-bit transfer width 3 bits128 128-bit transfer width 4 bits256 256-bit transfer width 5 bits512 512-bit transfer width 6 2 0x4 _src,_dst msize[%s] Burst transaction length - 0: 1 data item, 1: 4 data items, 2: 8 data items, 3: 16 data items, 4: 32 data items, 5: 64 data items, 6: 128 data items, 7: 256 data items, 8: 512 data items, 9: 1024 data items. [17:14] read-write true items1 1 data item 0 items4 4 data items 1 items8 8 data items 2 items16 16 data items 3 items32 32 data items 4 items64 64 data items 5 items128 128 data items 6 items256 256 data items 7 items512 512 data items 8 items1024 1024 data items 9 2 0x4 _ar,_aw cache[%s] AXI cache signal [25:22] read-write 0 15 non_posted_last_write_en Non-posted Last Write Enable - 0: posted writes can be used throughout the block transfer, 1: posted writes can be used up to the last write, the last write must be non-posted. [30:30] read-write true disable Posted writes can be used throughout the block transfer 0 enable Posted writes can be used up to the last write, the last write must be non-posted 1 2 0x3 _ar,_aw prot[%s] AXI prot signal [34:32] read-write 0 7 arlen_en Source burst length enable - 0: disable, 1: enable [38:38] read-write arlen Source burst length [46:39] read-write 0 255 awlen_en Destination burst length enable - 0: disable, 1: enable [47:47] read-write awlen Destination burst length [55:48] read-write 0 255 2 0x1 _src,_dst stat_en[%s] Status enable [56:56] read-write ioc_block_tr Interrupt-on-completion block transfer - 0: disable, 1: enable [58:58] read-write 2 0x1 _last,_valid shadow_or_lli[%s] Shadow or Linked List Item - 0: not last/valid, 1: last/valid [62:62] read-write cfg DMAC Channel Configuration register (only exists for DMAX_NUM_CHANNELS <= 8). 0x20 0x40 0x00000000 2 0x2 _src,_dst multblk_type[%s] Source Multi Block Transfer Type - 0b00: Contiguous, 0b01: Reload, 0b10: Shadow Register, 0b11: Linked List [1:0] read-write true contiguous Contiguous multi-block transfer type 0 reload Reload multi-block transfer type 1 shadow Shadow register multi-block transfer type 2 linked_list Linked-list register multi-block transfer type 3 tt_fc Transfer Type and Flow Control - 0: tt=mem-to-mem, fc=dw_axi_dmac, 1: tt=mem-to-per, fc=dw_axi_dmac, 2: tt=per-to-mem, fc=dw_axi_dmac, 3: tt=per-to-per, fc=dw_axi_dmac, 4: tt=per-to-mem, fc=source-peripheral, 5: tt=per-to-per, fc=source-peripheral, 6: tt=mem-to-per, fc=destination-peripheral, 7: tt=per-to-per, fc=destination-peripheral [34:32] read-write true tt_mtm_fc_dmac Transfer type: mem-to-mem, Flow Control: dw_axi_dmac 0 tt_mtp_fc_dmac Transfer type: mem-to-per, Flow Control: dw_axi_dmac 1 tt_ptm_fc_dmac Transfer type: per-to-mem, Flow Control: dw_axi_dmac 2 tt_ptp_fc_dmac Transfer type: per-to-per, Flow Control: dw_axi_dmac 3 tt_ptm_fc_srcp Transfer type: per-to-mem, Flow Control: source-peripheral 4 tt_ptp_fc_srcp Transfer type: per-to-per, Flow Control: source-peripheral 5 tt_mtp_fc_dstp Transfer type: mem-to-per, Flow Control: destination-peripheral 6 tt_ptp_fc_dstp Transfer type: per-to-per, Flow Control: destination-peripheral 7 2 0x1 _src,_dst hs_sel[%s] Source Software or Hardware Handshaking Select - 0: hardware handshake, 1: software handshake [35:35] read-write true hardware Hardware handshake 0 software Software handshake 1 2 0x1 _src,_dst hwhs_pol[%s] Hardware Handshaking Polarity - 0: active high, 1: active low [37:37] read-write true active_high Hardware handshaking polarity active high 0 active_low Hardware handshaking polarity active low 1 2 0x5 _src,_dst per[%s] Assigns a hardware handshaking interface - **NOTE** for proper operation, only one peripheral should be assigned to the same handshaking interface. [43:39] read-write 0 31 ch_prior Channel priority - 0: lowest, NUM_CHAN - 1: highest. **NOTE** a value outside this range leads to undefined behavior. [51:49] read-write 0 3 lock_ch Lock Channel - 0: no lock, 1: lock. [52:52] read-write true no_lock No channel lock 0 lock Channel lock 1 ch_lock_lvl Channel Lock Level - 0: entire transfer, 1: current block. [53:53] read-write true entire_transfer Channel lock for the entire transfer 0 current_block Channel lock for the current block 1 2 0x4 _src,_dst osr_lmt[%s] Outstanding Request Limit. **NOTE** Maximum outstanding request limit is 16. [58:55] read-write 0 15 llp Linked list pointer register. 0x28 0x40 0x00000000 lms LLI master select - 0: AXI Master 1, 1: AXI Master 2. [0:0] read-write true axi_master1 Select LLI AXI master 1 0 axi_master2 Select LLI AXI master 2 1 loc Starting address memory of LLI block - **NOTE** the lower six bits are unassigned because addresses are assumed to be 64-byte aligned. [63:6] read-write 0 288230376151711743 status DMAC Channel Status register. 0x30 0x40 0x00000000 cmpltd_blk_tr_size Completed Block Transfer Size. [21:0] read-only data_left_in_fifo Data left in FIFO [46:32] read-only 2 0x8 _src,_dst swhs[%s] Software Handshake register. 0x38 0x40 0x00000000 req_src Software Handshake Request signal configuration: register source. [0:0] read-write req_src_we Software Handshake Request signal configuration: register source write-enable. [1:1] write-only req_sgl_src Software Handshake Request signal configuration: register scatter-gather source. [2:2] read-write req_sgl_src_we Software Handshake Request signal configuration: register scatter-gather source write-enable. [3:3] write-only req_lst_src Software Handshake Request signal configuration: register list source. [4:4] read-write req_lst_src_we Software Handshake Request signal configuration: register list source write-enable. [5:5] write-only blk_tr_resume_req Block Transfer Resume Request register. 0x48 0x40 0x00000000 blk_tr_resume_req Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer - 0: no request, 1: request [0:0] write-only axi_id Channel AXI ID register. 0x50 0x40 0x00000000 2 0x10 _read,_write suffix[%s] AXI ID suffix [15:0] read-write 0 65535 axi_qos Channel AXI QOS register - **NOTE** this register is only allowed to be modified when the channel is disabled. 0x58 0x40 0x00000000 2 0x4 _aw,_ar qos[%s] AXI QOS suffix [3:0] read-write 0 15 2 0x8 _src,_dst stat[%s] Channel Status register. 0x60 0x40 0x00000000 stat Channel Status [31:0] read-only 2 0x8 _src,_dst statar[%s] Channel Status Fetch Address register. 0x70 0x40 0x00000000 statar Channel Status [63:0] read-only int Channel Interrupt registers. 0x80 status_enable Channel Interrupt Status Enable 0x0 0x40 0xFFFFFFFFFFFFFFFF blk_tr_done Channel Block Transfer Done - 0: disabled, 1: enabled [0:0] read-write dma_tr_done Channel DMA Transfer Done - 0: disabled, 1: enabled [1:1] read-write 2 0x1 _src,_dst transcomp[%s] Channel Transfer Complete - 0: disabled, 1: enabled [3:3] read-write 2 0x1 _src,_dst dec_err[%s] Channel Decoding Error - 0: disabled, 1: enabled [5:5] read-write 2 0x1 _src,_dst slv_err[%s] Channel Slave Error - 0: disabled, 1: enabled [7:7] read-write 2 0x1 _rd,_wr lli_dec_err[%s] Channel Linked List Item Decoding Error - 0: disabled, 1: enabled [9:9] read-write 2 0x1 _rd,_wr lli_slv_err[%s] Channel Linked List Item Slave Error - 0: disabled, 1: enabled [11:11] read-write shadow_or_invalid_lli_err Channel Shadow Register or Linked List Item Invalid Error - 0: disabled, 1: enabled [13:13] read-write slvif_multiblktype_err Channel Slave Interface Multi Block Type Error - 0: disabled, 1: enabled [14:14] read-write slvif_dec_err Channel Slave Interface Decoding Error - 0: disabled, 1: enabled [16:16] read-write slvif_wr2ro_err Channel Slave Interface Write to Read-only Error - 0: disabled, 1: enabled [17:17] read-write slvif_r2wro_err Channel Slave Interface Read to Write-only Error - 0: disabled, 1: enabled [18:18] read-write slvif_wronchen_err Channel Slave Interface Write On Channel Enabled Error - 0: disabled, 1: enabled [19:19] read-write slvif_shadow_wron_valid_err Channel Slave Interface Shadow Register Write On Valid Error - 0: disabled, 1: enabled [20:20] read-write slvif_wron_hold_err Channel Slave Interface Write On Hold Error - 0: disabled, 1: enabled [21:21] read-write ch_lock_cleared Channel Lock Cleared - 0: disabled, 1: enabled [27:27] read-write ch_src_suspended Channel Source Suspended - 0: disabled, 1: enabled [28:28] read-write ch_suspended Channel Suspended - 0: disabled, 1: enabled [29:29] read-write ch_disabled Channel Disabled - 0: disabled, 1: enabled [30:30] read-write ch_aborted Channel Aborted - 0: disabled, 1: enabled [31:31] read-write status Channel Interrupt Status 0x8 0x40 0xFFFFFFFFFFFFFFFF blk_tr_done Channel Block Transfer Done - 0: disabled, 1: enabled [0:0] read-only dma_tr_done Channel DMA Transfer Done - 0: disabled, 1: enabled [1:1] read-only 2 0x1 _src,_dst transcomp[%s] Channel Transfer Complete - 0: disabled, 1: enabled [3:3] read-only 2 0x1 _src,_dst dec_err[%s] Channel Decoding Error - 0: disabled, 1: enabled [5:5] read-only 2 0x1 _src,_dst slv_err[%s] Channel Slave Error - 0: disabled, 1: enabled [7:7] read-only 2 0x1 _rd,_wr lli_dec_err[%s] Channel Linked List Item Decoding Error - 0: disabled, 1: enabled [9:9] read-only 2 0x1 _rd,_wr lli_slv_err[%s] Channel Linked List Item Slave Error - 0: disabled, 1: enabled [11:11] read-only shadow_or_invalid_lli_err Channel Shadow Register or Linked List Item Invalid Error - 0: disabled, 1: enabled [13:13] read-only slvif_multiblktype_err Channel Slave Interface Multi Block Type Error - 0: disabled, 1: enabled [14:14] read-only slvif_dec_err Channel Slave Interface Decoding Error - 0: disabled, 1: enabled [16:16] read-only slvif_wr2ro_err Channel Slave Interface Write to Read-only Error - 0: disabled, 1: enabled [17:17] read-only slvif_r2wro_err Channel Slave Interface Read to Write-only Error - 0: disabled, 1: enabled [18:18] read-only slvif_wronchen_err Channel Slave Interface Write On Channel Enabled Error - 0: disabled, 1: enabled [19:19] read-only slvif_shadow_wron_valid_err Channel Slave Interface Shadow Register Write On Valid Error - 0: disabled, 1: enabled [20:20] read-only slvif_wron_hold_err Channel Slave Interface Write On Hold Error - 0: disabled, 1: enabled [21:21] read-only ch_lock_cleared Channel Lock Cleared - 0: disabled, 1: enabled [27:27] read-only ch_src_suspended Channel Source Suspended - 0: disabled, 1: enabled [28:28] read-only ch_suspended Channel Suspended - 0: disabled, 1: enabled [29:29] read-only ch_disabled Channel Disabled - 0: disabled, 1: enabled [30:30] read-only ch_aborted Channel Aborted - 0: disabled, 1: enabled [31:31] read-only signal_enable Channel Interrupt Signal Enable 0x10 0x40 0xFFFFFFFFFFFFFFFF blk_tr_done Channel Block Transfer Done - 0: disabled, 1: enabled [0:0] read-write dma_tr_done Channel DMA Transfer Done - 0: disabled, 1: enabled [1:1] read-write 2 0x1 _src,_dst transcomp[%s] Channel Transfer Complete - 0: disabled, 1: enabled [3:3] read-write 2 0x1 _src,_dst dec_err[%s] Channel Decoding Error - 0: disabled, 1: enabled [5:5] read-write 2 0x1 _src,_dst slv_err[%s] Channel Slave Error - 0: disabled, 1: enabled [7:7] read-write 2 0x1 _rd,_wr lli_dec_err[%s] Channel Linked List Item Decoding Error - 0: disabled, 1: enabled [9:9] read-write 2 0x1 _rd,_wr lli_slv_err[%s] Channel Linked List Item Slave Error - 0: disabled, 1: enabled [11:11] read-write shadow_or_invalid_lli_err Channel Shadow Register or Linked List Item Invalid Error - 0: disabled, 1: enabled [13:13] read-write slvif_multiblktype_err Channel Slave Interface Multi Block Type Error - 0: disabled, 1: enabled [14:14] read-write slvif_dec_err Channel Slave Interface Decoding Error - 0: disabled, 1: enabled [16:16] read-write slvif_wr2ro_err Channel Slave Interface Write to Read-only Error - 0: disabled, 1: enabled [17:17] read-write slvif_r2wro_err Channel Slave Interface Read to Write-only Error - 0: disabled, 1: enabled [18:18] read-write slvif_wronchen_err Channel Slave Interface Write On Channel Enabled Error - 0: disabled, 1: enabled [19:19] read-write slvif_shadow_wron_valid_err Channel Slave Interface Shadow Register Write On Valid Error - 0: disabled, 1: enabled [20:20] read-write slvif_wron_hold_err Channel Slave Interface Write On Hold Error - 0: disabled, 1: enabled [21:21] read-write ch_lock_cleared Channel Lock Cleared - 0: disabled, 1: enabled [27:27] read-write ch_src_suspended Channel Source Suspended - 0: disabled, 1: enabled [28:28] read-write ch_suspended Channel Suspended - 0: disabled, 1: enabled [29:29] read-write ch_disabled Channel Disabled - 0: disabled, 1: enabled [30:30] read-write ch_aborted Channel Aborted - 0: disabled, 1: enabled [31:31] read-write clear Channel Interrupt Clear 0x18 0x40 0xFFFFFFFFFFFFFFFF blk_tr_done Channel Block Transfer Done - 0: disabled, 1: enabled [0:0] write-only dma_tr_done Channel DMA Transfer Done - 0: disabled, 1: enabled [1:1] write-only 2 0x1 _src,_dst transcomp[%s] Channel Transfer Complete - 0: disabled, 1: enabled [3:3] write-only 2 0x1 _src,_dst dec_err[%s] Channel Decoding Error - 0: disabled, 1: enabled [5:5] write-only 2 0x1 _src,_dst slv_err[%s] Channel Slave Error - 0: disabled, 1: enabled [7:7] write-only 2 0x1 _rd,_wr lli_dec_err[%s] Channel Linked List Item Decoding Error - 0: disabled, 1: enabled [9:9] write-only 2 0x1 _rd,_wr lli_slv_err[%s] Channel Linked List Item Slave Error - 0: disabled, 1: enabled [11:11] write-only shadow_or_invalid_lli_err Channel Shadow Register or Linked List Item Invalid Error - 0: disabled, 1: enabled [13:13] write-only slvif_multiblktype_err Channel Slave Interface Multi Block Type Error - 0: disabled, 1: enabled [14:14] write-only slvif_dec_err Channel Slave Interface Decoding Error - 0: disabled, 1: enabled [16:16] write-only slvif_wr2ro_err Channel Slave Interface Write to Read-only Error - 0: disabled, 1: enabled [17:17] write-only slvif_r2wro_err Channel Slave Interface Read to Write-only Error - 0: disabled, 1: enabled [18:18] write-only slvif_wronchen_err Channel Slave Interface Write On Channel Enabled Error - 0: disabled, 1: enabled [19:19] write-only slvif_shadow_wron_valid_err Channel Slave Interface Shadow Register Write On Valid Error - 0: disabled, 1: enabled [20:20] write-only slvif_wron_hold_err Channel Slave Interface Write On Hold Error - 0: disabled, 1: enabled [21:21] write-only ch_lock_cleared Channel Lock Cleared - 0: disabled, 1: enabled [27:27] write-only ch_src_suspended Channel Source Suspended - 0: disabled, 1: enabled [28:28] write-only ch_suspended Channel Suspended - 0: disabled, 1: enabled [29:29] write-only ch_disabled Channel Disabled - 0: disabled, 1: enabled [30:30] write-only ch_aborted Channel Aborted - 0: disabled, 1: enabled [31:31] write-only _reserved_channel DMAC Reserved register. 0xF8 0x40 0x00000000 aoncrg StarFive JH7110 AON CRG: aoncrg 0x17000000 0x0 0x10000 registers clk_osc Oscillator Clock 0x0 0x20 0x00000004 clk_divcfg Clock divider coefficient: Max=4, Default=4, Min=4, Typical=4 [23:0] read-write 4 4 clk_aon_apb AON APB Function Clock 0x4 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_osc_div4, clk_osc [29:24] read-write true clk_osc_div4 Select `clk_osc_div4` as AON APB clock. 0 clk_osc Select `clk_osc` as AON APB clock. 1 clk_ahb_gmac5 AHB GMAC5 Clock 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_axi_gmac5 AXI GMAC5 Clock 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_gmac0_rmii_rtx GMAC0 RMII RTX Clock 0x10 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=30, Default=2, Min=2, Typical=2 [23:0] read-write 2 30 clk_gmac5_axi64_tx GMAC5 AXI64 Clock Transmitter 0x14 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: u0_sys_crg_clk_gmac0_gtxclk, clk_gmac0_rmii_rtx [29:24] read-write true u0_sys_crg_clk_gmac0_gtxclk Select `u0_sys_crg_clk_gmac0_gtxclk` as the GMAC5 AXI64 TX clock. 0 clk_gmac0_rmii_rtx Select `clk_gmac0_rmii_rtx` as the GMAC5 AXI64 TX clock. 1 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_gmac5_axi64_txi GMAC5 AXI64 Clock Transmission Inverter 0x18 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 clk_gmac5_axi64_rx GMAC5 AXI64 Clock Receiver 0x1C 0x20 0x00000000 dly_chain_sel Selector delay chain stage number, totally 32 stages, -50 ps each stage. The register value indicates the delay chain stage number. For example, diy_chain_sel=1 means to delay 1 stage. [23:0] read-write clk_gmac5_axi64_rxi GMAC5 AXI64 Clock Receiving Inverter 0x20 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 clk_optc_apb OPTC APB Clock 0x24 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_rtc_hms_apb RTC HMS APB Clock 0x28 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_rtc_internal RTC Internal Clock 0x2C 0x20 0x000002EE clk_divcfg Clock divider coefficient: Max=1022, Default=750, Min=750, Typical=750 [23:0] read-write 750 1022 clk_rtc_hms_osc32k RTC HMS Clock Oscillator 32K 0x30 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_rtc, clk_rtc_internal [29:24] read-write true clk_rtc Select `clk_rtc` as the RTC HMC Oscillator 32K clock. 0 clk_rtc_internal Select `clk_rtc_internal` as the RTC HMC Oscillator 32K clock. 1 clk_rtc_hms_cal RTC HMS Clock Calculator 0x34 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 soft_rst_addr_sel Software RESET Address Selector 0x38 0x20 0x000000E3 gmac5_axi64_axi GMAC5 AXI64 AXI reset. [0:0] read-write true none De-assert the reset. 0 reset Assert the reset. 1 gmac5_axi64_ahb GMAC5 AXI64 AHB reset. [1:1] read-write true none De-assert the reset. 0 reset Assert the reset. 1 aon_iomux_presetn AON IOMUX Presetn reset. [2:2] read-write true none De-assert the reset. 0 reset Assert the reset. 1 pmu_apb PMU APB reset. [3:3] read-write true none De-assert the reset. 0 reset Assert the reset. 1 pmu_wkup PMU Wake-up reset. [4:4] read-write true none De-assert the reset. 0 reset Assert the reset. 1 rtc_hms_apb RTC HMS APB reset. [5:5] read-write true none De-assert the reset. 0 reset Assert the reset. 1 rtc_hms_cal RTC HMS CAL reset. [6:6] read-write true none De-assert the reset. 0 reset Assert the reset. 1 rtc_hms_osc32k RTC HMS Oscillator 32k reset. [7:7] read-write true none De-assert the reset. 0 reset Assert the reset. 1 aoncrg_rst_status AONCRG RESET Status 0x3C 0x20 0x000000E3 gmac5_axi64_axi GMAC5 AXI64 AXI reset. [0:0] read-write true none De-assert the reset. 0 reset Assert the reset. 1 gmac5_axi64_ahb GMAC5 AXI64 AHB reset. [1:1] read-write true none De-assert the reset. 0 reset Assert the reset. 1 aon_iomux_presetn AON IOMUX Presetn reset. [2:2] read-write true none De-assert the reset. 0 reset Assert the reset. 1 pmu_apb PMU APB reset. [3:3] read-write true none De-assert the reset. 0 reset Assert the reset. 1 pmu_wkup PMU Wake-up reset. [4:4] read-write true none De-assert the reset. 0 reset Assert the reset. 1 rtc_hms_apb RTC HMS APB reset. [5:5] read-write true none De-assert the reset. 0 reset Assert the reset. 1 rtc_hms_cal RTC HMS CAL reset. [6:6] read-write true none De-assert the reset. 0 reset Assert the reset. 1 rtc_hms_osc32k RTC HMS Oscillator 32k reset. [7:7] read-write true none De-assert the reset. 0 reset Assert the reset. 1 aon_syscon StarFive JH7110 AON Syscon: aon_syscon 0x17010000 0x0 0x1000 registers aon_syscfg_0 AON SYSCONSAIF SYSCFG 0 0x0 0x20 0x00000000 aon_gp_reg [31:0] read-write 0 4294967295 aon_syscfg_1 AON SYSCONSAIF SYSCFG 4 0x4 0x20 0x00000000 u0_boot_ctrl_boot_status [3:0] read-only aon_syscfg_2 AON SYSCONSAIF SYSCFG 8 0x8 0x20 0x00000000 u0_boot_ctrl_boot_vector_0_31 Boot vectors 0-31 (little-endian) [31:0] read-only aon_syscfg_3 AON SYSCONSAIF SYSCFG 12 0xC 0x20 0x0004D540 u0_boot_ctrl_boot_vector_32_35 Boot vectors 32-35 (little-endian) [3:0] read-only gmac5_axi64_scfg_ram_cfg_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [4:4] read-write gmac5_axi64_scfg_ram_cfg_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [5:5] read-write gmac5_axi64_scfg_ram_cfg_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [7:6] read-write 0 3 gmac5_axi64_scfg_ram_cfg_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write 0 3 gmac5_axi64_scfg_ram_cfg_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [11:10] read-write 0 3 gmac5_axi64_scfg_ram_cfg_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [13:12] read-write 0 3 gmac5_axi64_scfg_ram_cfg_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [14:14] read-write gmac5_axi64_scfg_ram_cfg_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [15:15] read-write gmac5_axi64_mac_speed_o [17:16] read-only gmac5_axi64_phy_intf_sel_i Active PHY Selected. When you have multiple GMAC PHY interfaces in your configuration, this field indicates the sampled value of the PHY selector during reset de-assertion. Values: 0x0 - GMII or MII, 0x1 - RGMII, 0x2 - SGMII, 0x3 - TBI, 0x4 - RMII, 0x5 - RTBI, 0x6 - SMII, 0x7 - REVMII [20:18] read-write true gmii_mii GMII or MII configuration 0 rgmii RGMII configuration 1 sgmii SGMII configuration 2 tbi TBI configuration 3 rmii RMII configuration 4 rtbi RTBI configuration 5 smii SMII configuration 6 revmii REVMII configuration 7 aon_syscfg_4 AON SYSCONSAIF SYSCFG 16 0x10 0x20 0x00000000 gmac5_axi64_ptp_timestamp_o_0_31 GMAC5 PTP timestamps 0-31 (little-endian) [31:0] read-only aon_syscfg_5 AON SYSCONSAIF SYSCFG 20 0x14 0x20 0x00000000 gmac5_axi64_ptp_timestamp_o_32_63 GMAC5 PTP timestamps 32-63 (little-endian) [31:0] read-only aon_syscfg_6 AON SYSCONSAIF SYSCFG 24 0x18 0x20 0x00000000 u0_otpc_chip_mode [0:0] read-only u0_otpc_crc_pass [1:1] read-only u0_otpc_dbg_enable [2:2] read-only aon_syscfg_7 AON SYSCONSAIF SYSCFG 28 0x1C 0x20 0x00000000 u0_otpc_fl_func_lock [31:0] read-only aon_syscfg_8 AON SYSCONSAIF SYSCFG 32 0x20 0x20 0x00000000 u0_otpc_fl_pll0_lock [31:0] read-only aon_syscfg_9 AON SYSCONSAIF SYSCFG 36 0x24 0x20 0x00000000 u0_otpc_fl_pll1_lock [31:0] read-only aon_syscfg_10 AON SYSCONSAIF SYSCFG 40 0x28 0x20 0x00000020 u0_otpc_fl_sec_boot_lmt [0:0] read-only u0_otpc_fl_xip [1:1] read-only u0_otpc_load_busy [2:2] read-only u0_reset_ctrl_clr_reset_status [3:3] read-write u0_reset_ctrl_pll_timecnt_finish [4:4] read-only u0_reset_ctrl_rstn_sw [5:5] read-write u0_reset_ctrl_sys_reset_status [9:6] read-only aon_pinctrl StarFive JH7110 AON Pinctrl: aon_pinctrl 0x17020000 0x0 0x10000 registers AON_IOMUX 85 fmux_gpo_doen The register can be used to configure the selected (Output Enable) OEN signal for GPIO0 - GPIO3. 0x0 0x20 0x01010101 gpo_doen0 The selected OEN signal for GPIO0. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [2:0] read-write 0 7 gpo_doen1 The selected OEN signal for GPIO1. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [10:8] read-write 0 7 gpo_doen2 The selected OEN signal for GPIO2. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [18:16] read-write 0 7 gpo_doen3 The selected OEN signal for GPIO3. The register value indicates the selected GPIO (Output Enable) OEN index from GPIO OEN list 0-5. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [26:24] read-write 0 7 fmux_gpo_dout The register can be used to configure the selected (Digital Output) DOUT signal for GPIO0 - GPIO3. 0x4 0x20 0x00000000 gpo_dout0 The selected DOUT signal for GPIO0. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [3:0] read-write 0 15 gpo_dout1 The selected DOUT signal for GPIO1. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [11:8] read-write 0 15 gpo_dout2 The selected DOUT signal for GPIO2. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [19:16] read-write 0 15 gpo_dout3 The selected DOUT signal for GPIO3. The register value indicates the selected GPIO output signal list 0-9. See Table 2-42: GPIO OEN List for AON_IOMUX for more information. [27:24] read-write 0 15 fmux_gpi The register can be used to configure the selected GPIO connector number for input signals. 0x8 0x20 0x05040302 gpi_pmu_wakeup0 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [2:0] read-write 0 7 gpi_pmu_wakeup1 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [10:8] read-write 0 7 gpi_pmu_wakeup2 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [18:16] read-write 0 7 gpi_pmu_wakeup3 The register value indicates the selected GPIO number + 2 (GPIO2-GPIO63, GPIO0 and GPIO1 are not available) for the input signal. [26:24] read-write 0 7 fmux_gpen Enable always-on GPIO IRQ function. 0xC 0x20 0x00000000 gpen0 Enable GPIO IRQ function. [0:0] read-write ioirq Always-on GPIO IO IRQ configuration 0x10 is Always-on GPIO IO IRQ configuration: IS. 0x0 0x20 0x00000000 is_field 0: Level trigger, 1: Edge trigger [3:0] read-write true level_trigger IO IRQ level trigger 0 edge_trigger IO IRQ edge trigger 1 ic Always-on GPIO IO IRQ configuration: IC. 0x4 0x20 0x00000000 ic_field 0: Clear the register, 1: Do not clear the register [3:0] read-write true clear IO IRQ clear the register 0 no_clear IO IRQ do not clear the register 1 ibe Always-on GPIO IO IRQ configuration: IBE. 0x8 0x20 0x00000000 ibe_field 0: Trigger on a single edge, 1: Trigger on both edges [3:0] read-write true single_edge IO IRQ trigger on a single edge 0 both_edges IO IRQ trigger on both edges 1 iev Always-on GPIO IO IRQ configuration: IEV. 0xC 0x20 0x00000000 iev_field 0: Negative/High, 1: Positive/Low [3:0] read-write true negative_high IO IRQ negative/high 0 positive_low IO IRQ positive/low 1 ie Always-on GPIO IO IRQ configuration: IE. 0x10 0x20 0x00000000 ie_field 0: Mask, 1: Unmask [3:0] read-write true mask IO IRQ mask 0 unmask IO IRQ unmask 1 3 0x4 _ris,_mis,_in_sync2 ioirq_status[%s] Always-on GPIO IO IRQ configuration. 0x24 0x20 0x00000000 ioirq ris - Status of the edge trigger, can be cleared by writing gpioic. mis - The masked GPIO IRQ status. in_sync2 - Status of gpio_in after synchronization. [3:0] read-only testen AON IOMUX CFG SAIF SYSCFG 48 - Enable test Power-on-Start (POS) 0x30 0x20 0x00000000 pos Power-on-Start (POS) enabler - 0: Active pull-down capability disabled, 1: Enable active pull down for loss of core power. [0:0] read-write true disabled Power-on-Start active pull-down is disabled 0 enabled Power-on-Start active pull-down is enabled 1 4 0x4 rgpio[%s] AON IOMUX CFG SAIF SYSCFG - RGPIO 0x34 0x20 0x00000001 ie Input Enable (IE) Controller - 1: Enable the receiver, 0: Disable the receiver [0:0] read-write true enable Enable the receiver 0 disable Disable the receiver 1 ds Output Drive Strength (DS) - 00: The rated drive strength is 2 mA, 01: The rated drive strength is 4 mA, 10: The rated drive strength is 8 mA, 11: The rated drive strength is 12 mA [2:1] read-write true ma2 The rated drive strength is 2 mA 0 ma4 The rated drive strength is 4 mA 1 ma8 The rated drive strength is 8 mA 2 ma12 The rated drive strength is 12 mA 3 pu Pull-Up (PU) settings - 1: Yes, 0: No [3:3] read-write true clear Pull-up setting is clear 0 set Pull-up setting is set 1 pd Pull-Down (PD) settings - 1: Yes, 0: No [4:4] read-write true clear Pull-down setting is clear 0 set Pull-down setting is set 1 slew Slew Rate Control - 0: Slow (Half frequency), 1: Fast [5:5] read-write true slow Slew rate control is slow (half frequency) 0 fast Slew rate control is fast 1 smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled [6:6] read-write true disabled Active high Schmitt (SMT) trigger is configured for no hysteresis 0 enabled Active high Schmitt (SMT) trigger is enabled 1 pos Power-on-Start (POS) enabler - 1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled [7:7] read-write true disabled Power-on-Start active pull-down is disabled 0 enabled Power-on-Start active pull-down is enabled 1 rstn AON IOMUX CFG SAIF SYSCFG 68 - RSTN 0x44 0x20 0x00000001 smt Active high Schmitt (SMT) trigger selector - 0: No hysteresis, 1: Schmitt trigger enabled [0:0] read-write true disabled Active high Schmitt (SMT) trigger is configured for no hysteresis 0 enabled Active high Schmitt (SMT) trigger is enabled 1 pos Power-on-Start (POS) enabler - 1: Enable active pull-down for loss of core power, 0: Active pull-down capability disabled [1:1] read-write true disabled Power-on-Start active pull-down is disabled 0 enabled Power-on-Start active pull-down is enabled 1 rtc AON IOMUX CFG SAIF SYSCFG 76 - RTC 0x4C 0x20 0x00000002 ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write true ma2 The rated drive strength is 2 mA 0 ma4 The rated drive strength is 4 mA 1 ma8 The rated drive strength is 8 mA 2 ma12 The rated drive strength is 12 mA 3 osc AON IOMUX CFG SAIF SYSCFG 76 - OSC 0x54 0x20 0x00000002 ds Output Drive Strength (DS): * 00: The rated drive strength is 2 mA. * 01: The rated drive strength is 4 mA. * 10: The rated drive strength is 8 mA. * 11: The rated drive strength is 12 mA. [1:0] read-write true ma2 The rated drive strength is 2 mA 0 ma4 The rated drive strength is 4 mA 1 ma8 The rated drive strength is 8 mA 2 ma12 The rated drive strength is 12 mA 3 15 0x4 _mdc,_mdio,_rxd0,_rxd1,_rxd2,_rxd3,_rxdv,_rxc,_txd0,_txd1,_txd2,_txd3,_txen,_txc,_rxc_func_sel gmac0[%s] AON IOMUX CFG SAIF SYSCFG - GMAC0 0x58 0x20 0x00000002 cfg rxd0 - 0: GMAC0 IO voltage select 3.3V, 1: GMAC0 IO voltage select 2.5V, 2: GMAC0 IO voltage select 1.8V rxc_func_sel - Function selector of GMAC0_RXC: * Function 0: u0_aon_crg_clk_gmac0_rgmii_rx, * Function 1: u0_aon_crg_clk_gmac0_rmii_ref, * Function 2: None, * Function 3: None [1:0] read-write true v3_3 GMAC IO voltage select 3.3V 0 v2_5 GMAC IO voltage select 2.5V 1 v1_8 GMAC IO voltage select 1.8V 2 pmu StarFive JH7110 PMU: pmu 0x17030000 0x0 0x10000 registers PMU 111 hard_event_turn_on_mask Hardware Event Turn-On Mask 0x4 0x20 0x00000000 hard_event_rtc_on_mask RTC event encourage turn-on sequence, 0: enable hardware event, 1: mask hardware event [0:0] read-write hard_event_gmac_on_mask GMAC event encourage turn-on sequence, 0: enable hardware event, 1: mask hardware event [1:1] read-write hard_event_rfu_on_mask RFU, 0: enable hardware event, 1: mask hardware event [2:2] read-write hard_event_rgpio0_on_mask RGPIO0 event encourage turn-on sequence, 0: enable hardware event, 1: mask hardware event [3:3] read-write hard_event_rgpio1_on_mask RGPIO1 event encourage turn-on sequence, 0: enable hardware event, 1: mask hardware event [4:4] read-write hard_event_rgpio2_on_mask RGPIO2 event encourage turn-on sequence, 0: enable hardware event, 1: mask hardware event [5:5] read-write hard_event_rgpio3_on_mask RGPIO3 event encourage turn-on sequence, 0: enable hardware event, 1: mask hardware event [6:6] read-write hard_event_gpu_on_mask GPU event, 0: enable hardware event, 1: mask hardware event [7:7] read-write soft_turn_on_power_mode Software Turn-On Power Mode 0xC 0x20 0x00000000 systop_power_mode SYSTOP turn-on power mode [0:0] read-write cpu_power_mode CPU turn-on power mode [1:1] read-write gpua_power_mode GPUA turn-on power mode [2:2] read-write vdec_power_mode VDEC turn-on power mode [3:3] read-write vout_power_mode VOUT turn-on power mode [4:4] read-write isp_power_mode ISP turn-on power mode [5:5] read-write venc_power_mode VENC turn-on power mode [6:6] read-write soft_turn_off_power_mode Software Turn-Off Power Mode 0x10 0x20 0x00000000 systop_power_mode SYSTOP turn-off power mode [0:0] read-write cpu_power_mode CPU turn-off power mode [1:1] read-write gpua_power_mode GPUA turn-off power mode [2:2] read-write vdec_power_mode VDEC turn-off power mode [3:3] read-write vout_power_mode VOUT turn-off power mode [4:4] read-write isp_power_mode ISP turn-off power mode [5:5] read-write venc_power_mode VENC turn-off power mode [6:6] read-write timeout_seq_thd Timeout Sequence Threshold 0x14 0x20 0x00000000 timeout_seq_thd [15:0] read-write 0 65535 3 0x4 pdc[%s] Power Domain Cascade register 0x18 0x20 0x00000000 pd0_off_cas Power domain 0 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7 any other value is invalid. [4:0] read-write 0 7 pd0_on_cas Power domain 0 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7 any other value is invalid. [9:5] read-write 0 7 pd1_off_cas Power domain 1 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7 any other value is invalid. [14:10] read-write 0 7 pd1_on_cas Power domain 1 turn-off cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7 any other value is invalid. [19:15] read-write 0 7 pd2_off_cas Power domain 2 turn-off cascade. The register value indicates the power-off sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7 any other value is invalid. [24:20] read-write 0 7 pd2_on_cas Power domain 1 turn-on cascade. The register value indicates the power-on sequence of this domain. 0 means the highest priority. System only accepts value from 0 to 7 any other value is invalid. [29:25] read-write 0 7 sw_encourage Software encouragement register 0x44 0x20 0x00000000 sw_encourage Software encouragement variants. [7:0] read-write true off Disable Software Encourage. 0 en_lo Enable LO Software Encourage. 5 dis_lo Disable LO Software Encourage. 10 en_hi Enable HI Software Encourage. 80 dis_hi Disable HI Software Encourage. 160 on Enable Software Encourage. 255 tim Timer Interrupt Mask register 0x48 0x20 0x00000000 seq_done_mask Mask the sequence complete event. 0: mask, 1: unmask [0:0] read-write true mask Mask the sequence complete event 0 unmask Unmask the sequence complete event 1 hw_req_mask Mask the hardware encouragement request. 0: mask, 1: unmask [1:1] read-write true mask Mask the hardware encouragement request 0 unmask Unmask the hardware encouragement request 1 sw_fail_mask Mask the software encouragement failure event. 0: mask, 1: unmask [3:2] read-write true mask Mask the software encouragement failure event 0 unmask Unmask the software encouragement failure event 1 hw_fail_mask Mask the hardware encouragement failure event. 0: mask, 1: unmask [5:4] read-write true mask Mask the hardware encouragement failure event 0 unmask Unmask the hardware encouragement failure event 1 pch_fail_mask Mask the P-channel encouragement failure event. 0: mask, 1: unmask [8:6] read-write true mask Mask the P-channel encouragement failure event 0 unmask Unmask the P-channel encouragement failure event 1 pch_bypass P-channel Bypass register 0x4C 0x20 0x00000000 pch_bypass Bypass P-channel. 0: enable p-channel, 1: bypass p-channel [0:0] read-write pch_pstate P-channel PSTATE register 0x50 0x20 0x00000000 pch_pstate P-channel state set. [4:0] read-write 0 31 pch_timeout P-channel waiting device acknowledge timeout. 0x54 0x20 0x00000000 pch_timeout [7:0] read-write 0 255 lp_timeout LP Cell Control Timeout Threshold register 0x58 0x20 0x00000000 lp_timeout [7:0] read-write 0 255 hard_turn_on_power_mode Hardware Turn-On Power Mode register 0x5C 0x20 0x00000000 systop_power_mode SYSTOP turn-on power mode [0:0] read-write cpu_power_mode CPU turn-on power mode [1:1] read-write gpua_power_mode GPUA turn-on power mode [2:2] read-write vdec_power_mode VDEC turn-on power mode [3:3] read-write vout_power_mode VOUT turn-on power mode [4:4] read-write isp_power_mode ISP turn-on power mode [5:5] read-write venc_power_mode VENC turn-on power mode [6:6] read-write current_power_mode Current Power Mode register 0x80 0x20 0x00000000 systop_power_mode SYSTOP turn-on power mode [0:0] read-write cpu_power_mode CPU turn-on power mode [1:1] read-write gpua_power_mode GPUA turn-on power mode [2:2] read-write vdec_power_mode VDEC turn-on power mode [3:3] read-write vout_power_mode VOUT turn-on power mode [4:4] read-write isp_power_mode ISP turn-on power mode [5:5] read-write venc_power_mode VENC turn-on power mode [6:6] read-write 2 0x4 _event,_interrupt status[%s] Event and Interrupt Status registers 0x88 0x20 0x00000000 seq_done_event Sequence complete. [0:0] read-only hw_req_event Hardware encouragement request. [1:1] read-only sw_fail_event Software encouragement failure. [3:2] read-only hw_fail_event Hardware encouragement failure. [5:4] read-only pch_fail_event P-channel failure. [8:6] read-only hw_event_crd Hardware Event Record register 0x90 0x20 0x00000000 hw_event_crd [7:0] read-only encourage_type_crd Hardware Event Type Record register 0x94 0x20 0x00000000 hw_event_crd Hardware/Software encouragement type record. 0: Software, 1: Hardware. [0:0] read-only pch_active P-channel PACTIVE Status register 0x98 0x20 0x00000000 pch_active [10:0] read-only ispcrg StarFive JH7110 ISP CRG: ispcrg 0x19810000 0x0 0x10000 registers clk_dom4_apb_func Clock DOM4 APB Function 0x0 0x20 0x00000006 clk_divcfg Clock divider coefficient: Max=15, Default=6, Min=6, Typical=6 [23:0] read-write 6 15 clk_mipi_rx0_pxl Clock MIPI RX 0 Pixel 0x4 0x20 0x00000003 clk_divcfg Clock divider coefficient: Max=8, Default=3, Min=2, Typical=3 [23:0] read-write 2 8 clk_dvp_inv Clock DVP Inverter 0x8 0x20 0x40000000 clk_polarity Clock polarity settings. [30:30] read-write true buffer Set the clock polarity to use the clock buffer. 0 inverter Set the clock polarity to use the clock inverter. 1 clk_u0_m31dphy_cfgclk_in Clock U0 M31 DPHY Config In 0xC 0x20 0x00000006 clk_divcfg Clock divider coefficient: Max=16, Default=6, Min=4, Typical=6 [23:0] read-write 4 16 clk_u0_m31dphy_refclk_in Clock U0 M31 DPHY Reference In 0x10 0x20 0x0000000C clk_divcfg Clock divider coefficient: Max=16, Default=12, Min=6, Typical=12 [23:0] read-write 6 16 clk_u0_m31dphy_txclkesc_lan0 Clock U0 M31 DPHY TX Clock Escape LAN0 0x14 0x20 0x0000001E clk_divcfg Clock divider coefficient: Max=60, Default=30, Min=15, Typical=30 [23:0] read-write 15 60 clk_u0_vin_pclk Clock U0 Video In PCLK 0x18 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_u0_vin_sys_clk Clock U0 Video In SYSCLK 0x1C 0x20 0x00000002 clk_divcfg Clock divider coefficient: Max=8, Default=2, Min=1, Typical=2 [23:0] read-write 1 8 4 0x4 clk_u0_vin_pixel_clk_if[%s] Clock Video In Pixel Clock Interfaces 0x20 0x20 0x80000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_u0_vin_p_axiwr Clock U0 Video In P AXIWR 0x30 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_mipi_rx0_pxl, clk_dvp_inv [29:24] read-write true clk_mipi_rx0_pxl Select `clk_mipi_rx0_pxl` as the U0 Video In P AXIWR clock. 0 clk_dvp_inv Select `clk_dvp_inv` as the U0 Video In P AXIWR clock. 1 clk_ispv2_top_wrapper Clock ISPv2 Top Wrapper Clock C: clk_ispv2_top_wrapper_clk_c 0x34 0x20 0x80000000 clk_mux_sel Clock multiplexing selector: clk_mipi_rx0_pxl, clk_dvp_inv [29:24] read-write true clk_mipi_rx0_pxl Select `clk_mipi_rx0_pxl` as the ISPv2 Top Wrapper clock. 0 clk_dvp_inv Select `clk_dvp_inv` as the ISPv2 Top Wrapper clock. 1 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0x4 _software_assert0_addr_assert_sel,_ispcrg_status reset[%s] ISPCRG Reset registers 0x38 0x20 0x00000FFF rst_u0_ispv2_top_wrapper_rst_p 0: De-assert reset, 1: Assert reset [0:0] read-write rst_u0_ispv2_top_wrapper_rst_c 0: De-assert reset, 1: Assert reset [1:1] read-write rstn_u0_m31dphy_hw_rstn 0: De-assert reset, 1: Assert reset [2:2] read-write rstn_u0_m31dphy_rstb09_aon 0: De-assert reset, 1: Assert reset [3:3] read-write rstn_u0_vin_rst_n_pclk 0: De-assert reset, 1: Assert reset [4:4] read-write rstn_u0_vin_rst_n_pixel_clk_if0 0: De-assert reset, 1: Assert reset [5:5] read-write rstn_u0_vin_rst_n_pixel_clk_if1 0: De-assert reset, 1: Assert reset [6:6] read-write rstn_u0_vin_rst_n_pixel_clk_if2 0: De-assert reset, 1: Assert reset [7:7] read-write rstn_u0_vin_rst_n_pixel_clk_if3 0: De-assert reset, 1: Assert reset [8:8] read-write rstn_u0_vin_rst_n_sys_clk 0: De-assert reset, 1: Assert reset [9:9] read-write rstn_u0_vin_rst_p_axird 0: De-assert reset, 1: Assert reset [10:10] read-write rstn_u0_vin_rst_p_axiwr 0: De-assert reset, 1: Assert reset [11:11] read-write isp_syscon StarFive JH7110 ISP SYSCON: isp_syscon 0x19840000 0x0 0x10000 registers isp_syscfg0 ISP SYSCFG 0: isp_sysconsaif_syscfg_0 0x0 0x20 0x00000000 u0_vin_scfg_sram_config [1:0] read-write 0 3 u0_vin_cfg_axi_dvp_en 0: Output to AXI is DVP, 1: Output to AXI is MIPI [2:2] read-write u0_vin_cfg_axird_axi_cnt_end The valid pixel of the AXI image. 1 pixel equals 64 bit. [13:3] read-write 0 2047 isp_syscfg1 ISP SYSCFG 1: isp_sysconsaif_syscfg_4 0x4 0x20 0x00000000 u0_vin_cfg_axird_end_addr the start address of the next frame [31:0] read-write 0 4294967295 isp_syscfg2 ISP SYSCFG 2: isp_sysconsaif_syscfg_8 0x8 0x20 0x00000000 u0_vin_cfg_axird_intr_clean Use this bit to clean the AXI output interrupt. Write 1 then write 0 to execute the cleaning. [0:0] read-write u0_vin_cfg_axird_intr_mask Use this bit to mask the AXI output interrupt. [1:1] read-write u0_vin_cfg_axird_line_cnt_end This bit represents the valid end pixel of the AXI input test image line. [13:2] read-write 0 4095 u0_vin_cfg_axird_line_cnt_start This bit represents the valid start pixel of the AXI input test image line. [25:14] read-write 0 4095 isp_syscfg3 ISP SYSCFG 3: isp_sysconsaif_syscfg_12 0xC 0x20 0x00000000 u0_vin_cfg_axird_pix_cnt_end This bit represents the valid end pixel of the AXI input test image line. [12:0] read-write 0 8191 u0_vin_cfg_axird_pix_cnt_start This bit represents the valid start pixel of the AXI input test image line. [25:13] read-write 0 8191 u0_vin_cfg_axird_pix_ct 00: 1 64-bit equals to 2 pixels, 01: 1 64-bit equals to 4 pixels, 10: 1 64-bit equals to 8 pixels [27:26] read-write true two 1 64-bit equals to 2 pixels 0 four 1 64-bit equals to 4 pixels 1 eight 1 64-bit equals to 8 pixels 2 isp_syscfg4 ISP SYSCFG 4: isp_sysconsaif_syscfg_16 0x10 0x20 0x00000000 u0_vin_cfg_axird_start_addr This bit represents the valid start address of the AXI input test image's first line. [31:0] read-write 0 4294967295 isp_syscfg5 ISP SYSCFG 5: isp_sysconsaif_syscfg_20 0x14 0x20 0x00000000 u0_vin_cfg_axiwr0_channel_sel Select 1 channel output of the 8 MIPI channels [3:0] read-write 0 15 u0_vin_cfg_axiwr0_en Set this bit to 1 to enable the image output to AXI. [4:4] read-write isp_syscfg6 ISP SYSCFG 6: isp_sysconsaif_syscfg_24 0x18 0x20 0x00000000 u0_vin_cfg_axiwr0_end_addr This bit represents the start address of the next frame. [31:0] read-write 0 4294967295 isp_syscfg7 ISP SYSCFG 7: isp_sysconsaif_syscfg_28 0x1C 0x20 0x00000000 u0_vin_cfg_axiwr0_intr_clean Use this bit to clean the AXI output interrupt. Write 1 then write 0 to execute the cleaning. [0:0] read-write u0_vin_cfg_axiwr0_intr_mask Use this bit to mask the AXI output interrupt. [1:1] read-write u0_vin_cfg_axiwr0_pix_cnt_end This bit represents the valid end pixel of the AXI input test image line. [12:2] read-write 0 2047 u0_vin_cfg_axiwr0_pix_ct 00: 1 64-bit equals to 2 pixels, 01: 1 64-bit equals to 4 pixels, 10: 1 64-bit equals to 8 pixels [14:13] read-write true two 1 64-bit equals to 2 pixels 0 four 1 64-bit equals to 4 pixels 1 eight 1 64-bit equals to 8 pixels 2 u0_vin_cfg_axiwr0_pixel_high_bit_sel When you configure the above bit as '10' - 1 64-bit equals to 8 pixels, the 8 pixels will use some of the RAW data - 00: 1 64-bit pix_data[7:0], 01: 1 pix_data[9:2], 10: pix_data[11:4], 11: pix_data[13:6] [16:15] read-write true data0_7 1 64-bit pix_data[7:0] 0 data2_9 1 64-bit pix_data[9:2] 1 data4_11 1 64-bit pix_data[11:4] 2 data6_13 1 64-bit pix_data[13:6] 3 isp_syscfg8 ISP SYSCFG 8: isp_sysconsaif_syscfg_32 0x20 0x20 0x00000000 u0_vin_cfg_axiwr0_start_addr This bit represents the start address of the AXI output image. [31:0] read-write 0 4294967295 isp_syscfg9 ISP SYSCFG 9: isp_sysconsaif_syscfg_36 0x24 0x20 0x00000000 u0_vin_cfg_color_bar_en Set this bit to 1 to use the color bar for test. [0:0] read-write u0_vin_cfg_dvp_hs_pos Use DVP to AXI - 0: HS is low valid, 1: HS is high valid. [1:1] read-write u0_vin_cfg_dvp_swap_en Set this bit to 1 to enable DVP swap. [2:2] read-write u0_vin_cfg_dvp_vs_pos Use DVP to AXI - 0: VS is low valid, 1: VS is high valid. [3:3] read-write true low_valid VS is low valid 0 high_valid VS is high valid 1 u0_vin_cfg_gen_en_axird Set this bit to use AXI input for ISP and generate test image. [4:4] read-write u0_vin_cfg_isp_dvp_en0 Set this bit to use DVP input for ISP. [5:5] read-write u0_vin_cfg_mipi_byte_en_isp0 Set to 1 for dvp_clk_inv, the DVP clock inverter register. [7:6] read-write 0 3 u0_vin_cfg_mipi_channel_sel0 Select 1 channel output of the 8 MIPI channels. [11:8] read-write 0 15 u0_vin_cfg_mipi_header_en0 Set this bit to 1 to add 10 bits to bit 2, so 1 pixel equals 12 bits. [12:12] read-write u0_vin_cfg_pix_num VIN AXI to ISP MIPI port, 12-bit data configuration - 00: axi_data[11:0], 01: axi_data[9:0], 10: axi_data[7:0], 11: axi_data[5:0] [16:13] read-write true axi_data0_11 12-bit data configuration: axi_data[11:0] 0 axi_data0_9 12-bit data configuration: axi_data[9:0] 1 axi_data0_7 12-bit data configuration: axi_data[7:0] 2 axi_data0_5 12-bit data configuration: axi_data[5:0] 3 u0_vin_generic_sp This configuration is not used by JH7110. [26:17] read-only isp_syscfg10 ISP SYSCFG 10: isp_sysconsaif_syscfg_40 0x28 0x20 0x00000000 u0_vin_test_generic_ctrl This configuration is not used by JH7110. [15:0] read-only u0_vin_test_generic_status This configuration is not used by JH7110. [31:16] read-write 0 65535 vout_syscon StarFive JH7110 VOUT SYSCON: vout_syscon 0x295B0000 0x0 0x10000 registers syscfg0 VOUT SYSCFG 0: dom_vout_sysconsaif_0 0x0 0x20 0x00000000 u0_cdns_dsitx_slp SRAM/ROM configuration. SLP: sleep enable, high active, default is low. [0:0] read-write u0_cdns_dsitx_sd SRAM/ROM configuration. SD: shutdown enable, high active, default is low. [1:1] read-write u0_cdns_dsitx_rtsel SRAM/ROM configuration. RTSEL: timing setting for debug purpose, default is 2'b01. [3:2] read-write u0_cdns_dsitx_ptsel SRAM/ROM configuration. PTSEL: timing setting for debug purpose, default is 2'b01. [5:4] read-write u0_cdns_dsitx_trb SRAM/ROM configuration. TRB: timing setting for debug purpose, default is 2'b01. [7:6] read-write u0_cdns_dsitx_wtsel SRAM/ROM configuration. WTSEL: timing setting for debug purpose, default is 2'b01. [9:8] read-write u0_cdns_dsitx_vs SRAM/ROM configuration. VS: timing setting for debug purpose, default is 1'b1. [10:10] read-write u0_cdns_dsitx_vg SRAM/ROM configuration. VG: timing setting for debug purpose, default is 1'b1. [11:11] read-write u0_cdns_dsitx_dsi_test_generic_ctrl [23:8] read-only syscfg1 VOUT SYSCFG 1: dom_vout_sysconsaif_4 0x4 0x20 0x00080000 u0_cdns_dsitx_dsi_test_generic_status [15:0] read-write 0 65535 u0_dc8200_cactive [16:16] read-only u0_dc8200_csysack [17:17] read-only u0_dc8200_csysreq [18:18] read-write u0_dc8200_disable_ram_clock_gating [19:19] read-write u0_display_panel_mux_panel_sel DC8200 Panel - 0: Panel 0, 1: Panel 1 [20:20] read-write true panel0 DC8200 panel 0 0 panel1 DC8200 panel 1 1 u0_dsitx_data_mapping_dp_mode DP color mode - 0: YUV420 CFG1, 1: YUV420 CFG3, 2: YUV422 CFG1 (Reserved), 3: RGB888, 4: RGB666, 5: RGB565 [23:21] read-write true yuv420_cfg1 DP color mode: YUV420 CFG1 0 yuv420_cfg3 DP color mode: YUV420 CFG3 1 rgb888 DP color mode: RGB888 3 rgb666 DP color mode: RGB666 4 rgb565 DP color mode: RGB565 5 u0_dsitx_data_mapping_dpi_dp_sel DC8200 DP/DPI interface for dsiTx - 0: DPI, 1: DP [24:24] read-write true dpi DC8200 DP/DPI interface for dsiTX: DPI 0 dp DC8200 DP/DPI interface for dsiTX: DP 1 u0_hdmi_data_mapping_dp_bit_depth DP Bit Depth - 0: 8-bit, 1: 10-bit [25:25] read-write true bit8 DP Bit Depth: 8-bit 0 bit10 DP Bit Depth: 10-bit 1 u0_hdmi_data_mapping_dp_yuv_mode DP YUV Mode - 0: YUV420, 1: YUV422, 2: YUV444, 3: RGB [27:26] read-write true yuv420 DP YUV Mode: YUV420 0 yuv422 DP YUV Mode: YUV422 1 yuv444 DP YUV Mode: YUV444 2 rgb DP YUV Mode: RGB 3 u0_hdmi_data_mapping_dpi_bit_depth DPI Bit Depth - 0: 8-bit, 1: 10-bit, 2: 6-bit CFG1 in DC8200, 3: RGB565 CFG1 in DC8200 [29:28] read-write true bit8 DPI Bit Depth: 8-bit 0 bit10 DPI Bit Depth: 10-bit 1 bit6 DPI Bit Depth: 6-bit CFG1 in DC8200 2 rgb565 DPI Bit Depth: RGB565 CFG1 in DC8200 3 u0_hdmi_data_mapping_dpi_dp_sel DC8200 DP/DPI interface - 0: DPI, 1: DP [30:30] read-write true dpi DC8200 DP/DPI interface: DPI 0 dp DC8200 DP/DPI interface: DP 1 syscfg2 VOUT SYSCFG 2: dom_vout_sysconsaif_8 0x8 0x20 0x00000000 u0_lcd_data_mapping_dp_rgb_fmt RGB format in DP data - 0: RGB888, 1: RGB666, 2: RGB565 [1:0] read-write true rgb888 RGB format in DP data: RGB888 0 rgb666 RGB format in DP data: RGB666 1 rgb565 RGB format in DP data: RGB565 2 u0_lcd_data_mapping_dpi_dp_sel DPI or DP - 0: DPI, 1: DP [2:2] read-write true dpi ICD data mapping selection: DPI 0 dp ICD data mapping selection: DP 1 u1_display_panel_sel DC8200 panel - 0: Panel 0, 1: Panel 1 [3:3] read-write true panel0 DC8200 panel: 0 0 panel1 DC8200 panel: 1 1 u2_display_panel_sel DC8200 panel - 0: Panel 0, 1: Panel 1 [4:4] read-write true panel0 DC8200 panel: 0 0 panel1 DC8200 panel: 1 1 4 0x4 test[%s] VOUT SYSCFG 3-6: dom_vout_sysconsaif_12 - dom_vout_sysonsaif_24 0xC 0x20 0x00000000 test [31:0] read-write voutcrg StarFive JH7110 VOUT CRG: voutcrg 0x295C0000 0x0 0x10000 registers clk_apb Clock APB 0x0 0x20 0x00000004 clk_divcfg Clock divider coefficient: Max=8, Default=4, Min=4, Typical=4 [23:0] read-write 4 8 clk_dc8200_pix0 Clock DC8200 Pixel 0 0x4 0x20 0x00000004 clk_divcfg Clock divider coefficient: Max=63, Default=4, Min=4, Typical=4 [23:0] read-write 4 63 clk_dsi_sys Clock DSI System 0x8 0x20 0x00000004 clk_divcfg Clock divider coefficient: Max=31, Default=4, Min=4, Typical=4 [23:0] read-write 4 31 clk_tx_esc Clock Transmit Escape 0xC 0x20 0x0000000C clk_divcfg Clock divider coefficient: Max=31, Default=12, Min=10, Typical=12 [23:0] read-write 10 31 clk_u0_dc8200 Clock U0 DC8200 registers 0x10 axi Clock U0 DC8200 AXI 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 core Clock U0 DC8200 Core 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 ahb Clock U0 DC8200 AHB 0x8 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0x4 pix[%s] Clock U0 DC8200 Pixel Clock selector 0xC 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_dc8200_pix[n], clk_hdmitx0_pixelclk [29:24] read-write true clk_dc8200_pix Select `clk_dc8200_pix` as the U0 DC8200 clock. 0 clk_hdmitx0_pixelclk Select `clk_hdmitx0_pixelclk` as the U0 DC8200 clock. 1 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_dom_vout_top_lcd Clock DOM VOUT Top LCD 0x24 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_dc8200_pix0_out, clk_dc8200_pix1_out [29:24] read-write true clk_dc8200_pix0_out Select `clk_dc8200_pix0_out` as the DOM VOUT Top LCD clock. 0 clk_dc8200_pix1_out Select `clk_dc8200_pix1_out` as the DOM VOUT Top LCD clock. 1 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_u0_cdns_dsitx Clock U0 Cadence DSI Transmit registers 0x28 apb Clock U0 Cadence DSI Transmit APB 0x0 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 sys Clock U0 Cadence DSI Transmit SYS 0x4 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 dpi Clock U0 Cadence DSI Transmit DPI 0x8 0x20 0x00000000 clk_mux_sel Clock multiplexing selector: clk_dc8200_pix0, clk_hdmitx0_pixelclk [29:24] read-write true clk_dc8200_pix0 Select `clk_dc8200_pix0` as the U0 Cadence DSI Transmit DPI clock. 0 clk_hdmitx0_pixelclk Select `clk_hdmitx0_pixelclk` as the U0 Cadence DSI Transmit DPI clock. 1 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 txesc Clock U0 Cadence DSI Transmit TXESC 0xC 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 clk_u0_mipitx_dphy_txesc Clock U0 MIPI Transmit DPHY Transmit Escape 0x38 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 3 0x4 _mclk,_bclk,_sys clk_u0_hdmi_tx[%s] Clock U0 HDMI Transmit registers 0x3C 0x20 0x00000000 clk_icg Clock ICG enable. [31:31] read-write true disable Disable the clock. 0 enable Enable the clock. 1 2 0x4 _software_assert0_addr_assert_sel,_voutcrg_status rst[%s] VOUT CRG RESET register 0x48 0x20 0x00000FFF rstn_u0_dc8200_axi 0: De-assert reset, 1: Assert reset [0:0] read-write rstn_u0_dc8200_ahb 0: De-assert reset, 1: Assert reset [1:1] read-write rstn_u0_dc8200_core 0: De-assert reset, 1: Assert reset [2:2] read-write rstn_u0_cdns_dsitx_dpi 0: De-assert reset, 1: Assert reset [3:3] read-write rstn_u0_cdns_dsitx_apb 0: De-assert reset, 1: Assert reset [4:4] read-write rstn_u0_cdns_dsitx_rxesc 0: De-assert reset, 1: Assert reset [5:5] read-write rstn_u0_cdns_dsitx_sys 0: De-assert reset, 1: Assert reset [6:6] read-write rstn_u0_cdns_dsitx_txbytehs 0: De-assert reset, 1: Assert reset [7:7] read-write rstn_u0_cdns_dsitx_txesc 0: De-assert reset, 1: Assert reset [8:8] read-write rstn_u0_hdmi_tx_hdmi 0: De-assert reset, 1: Assert reset [9:9] read-write rstn_u0_mipitx_dphy_sys 0: De-assert reset, 1: Assert reset [10:10] read-write rstn_u0_mipitx_dphy_txbytehs 0: De-assert reset, 1: Assert reset [11:11] read-write mipitx_dphy StarFive JH7110 MIPI TX DPHY: mipitx_dphy 0x295E0000 0x0 0x10000 registers syscfg0 MIPITX DPHY SYSCFG 0: mipitx_apbifsaif_syscfg_0 0x0 0x20 0x0111A021 aon_power_ready_n Always-on Power Ready: u0_mipitx_dphy_AON_POWER_READY_N [0:0] read-write cklan Configure CKLAN: u0_mipitx_dphy_CFG_CKLANE_SET [5:1] read-write 0 31 databus16_sel Configure DATABUS16_SEL: u0_mipitx_dphy_CFG_DATABUS16_SEL [6:6] read-write dpdn_swap Configure DPDN_SWAP: u0_mipitx_dphy_CFG_DPDN_SWAP [11:7] read-write 0 31 5 0x3 _l0,_l1,_l2,_l3,_l4 swap_sel[%s] Configure SWAP_SEL: u0_mipitx_dphy_CFG_L[n]_SWAP_SEL [14:12] read-write 0 7 syscfg1 MIPITX DPHY SYSCFG 1: mipitx_apbifsaif_syscfg_4 0x4 0x20 0x00000000 32 0x1 mposv[%s] MPOSV: u0_mipitx_dphy_MPOSVn [0:0] read-only syscfg2 MIPITX DPHY SYSCFG 2: mipitx_apbifsaif_syscfg_8 0x8 0x20 0x10800000 15 0x1 32-46 mposv[%s] MPOSV: u0_mipitx_dphy_MPOSVn [0:0] read-only 4 0x1 _pll_fm_cplt,_pll_fm_over,_pll_fm_under,_pll_unlock rgs_cdtx[%s] RGS CDTX: u0_mipitx_dphy_RGS_CDTX [15:15] read-only 2 0x5 _l0n_hstx_res,_l0p_hstx_res rg_cdtx[%s] RG CDTX: u0_mipitx_dphy_RG_CDTX [23:19] read-write 0 31 syscfg3 MIPITX DPHY SYSCFG 3: mipitx_apbifsaif_syscfg_12 0xC 0x20 0x21084210 6 0x5 _l1n_hstx_res,_l1p_hstx_res,_l2n_hstx_res,_l2p_hstx_res,_l3n_hstx_res,_l3p_hstx_res rg_cdtx[%s] RG CDTX L1-L3: u0_mipitx_dphy_RG_CDTX [4:0] read-write 0 31 syscfg4 MIPITX DPHY SYSCFG 4: mipitx_apbifsaif_syscfg_16 0x10 0x20 0x00000210 2 0x5 _l4n_hstx_res,_l4p_hstx_res rg_cdtx[%s] RG CDTX: u0_mipitx_dphy_RG_CDTX [4:0] read-write 0 31 syscfg5 MIPITX DPHY SYSCFG 5: mipitx_apbifsaif_syscfg_20 0x14 0x20 0x00000000 rg_cdtx_pll_fbk_fra RG CDTX PLL FBK FRA: u0_mipitx_dphy_RG_CDTX_PLL_FBK_FRA [23:0] read-write 0 16777215 syscfg6 MIPITX DPHY SYSCFG 6: mipitx_apbifsaif_syscfg_24 0x18 0x20 0x00000864 rg_cdtx_pll_fbk_int RG CDTX PLL FBK INT: u0_mipitx_dphy_RG_CDTX_PLL_FBK_INT [8:0] read-write 0 511 rg_cdtx_pll_fm_en RG CDTX PLL FM EM: u0_mipitx_dphy_RG_CDTX_PLL_FM_EN [9:9] read-write rg_cdtx_pll_ldo_stb_x2_en RG CDTX PLL LDO STB X2 EN: u0_mipitx_dphy_RG_CDTX_PLL_LDO_STB_X2_EN [10:10] read-write rg_cdtx_pll_pre_div RG CDTX PLL PRE DIV: u0_mipitx_dphy_RG_CDTX_PLL_PRE_DIV [12:11] read-write 0 3 rg_cdtx_pll_ssc_delta RG CDTX PLL SSC DELTA: u0_mipitx_dphy_RG_CDTX_PLL_SSC_DELTA [30:13] read-write 0 262143 syscfg7 MIPITX DPHY SYSCFG 7: mipitx_apbifsaif_syscfg_28 0x1C 0x20 0x00000000 rg_cdtx_pll_ssc_delta_init RG CDTX PLL SSC DELTA INIT: u0_mipitx_dphy_RG_CDTX_PLL_SSC_DELTA_INIT [17:0] read-write 0 262143 rg_cdtx_pll_ssc_en RG CDTX PLL SSC EN: u0_mipitx_dphy_RG_CDTX_PLL_SSC_EN [18:18] read-write rg_cdtx_pll_ssc_prd RG CDTX PLL SSC PRD: u0_mipitx_dphy_RG_CDTX_PLL_SSC_PRD [28:19] read-write 0 1023 syscfg8 MIPITX DPHY CLANE: mipitx_apbifsaif_syscfg_32 0x20 0x20 0x530B0000 4 0x8 _hs_clk_post_time,_hs_clk_pre_time,_hs_pre_time,_hs_trail_time rg_clane[%s] RG CLANE: u0_mipitx_dphy_RG_CLANE [7:0] read-write 0 255 syscfg9 MIPITX DPHY CLANE and DLANE: mipitx_apbifsaif_syscfg_36 0x24 0x20 0x21160E16 4 0x8 _clane_hs_zero_time,_dlane_hs_pre_time,_dlane_hs_trail_time,_dlane_hs_zero_tim rg[%s] RG CLANE and DLANE TIME: u0_mipitx_dphy_RG_CLANE and u0_mipitx_dphy_RG_DLANE [7:0] read-write 0 255 syscfg10 MIPITX DPHY SYSCFG 10: mipitx_apbifsaif_syscfg_40 0x28 0x20 0x00000000 rg_extd_cycle_sel RG EXTD Cycle Select: u0_mipitx_dphy_RG_EXTD_CYCLE_SEL [2:0] read-write 0 7 syscfg11 MIPITX DPHY SYSCFG 11: mipitx_apbifsaif_syscfg_44 0x2C 0x20 0x00000000 scfg_c_hs_pre_zero_time SCFG C HS Pre Zero Time: u0_mipitx_dphy_SCFG_c_hs_pre_zero_time [31:0] read-write 0 4294967295 syscfg12 MIPITX DPHY SYSCFG 12: mipitx_apbifsaif_syscfg_48 0x30 0x20 0x00000000 scfg_dphy_src_sel SCFG DPHY Source Select: u0_mipitx_dphy_SCFG_dphy_src_sel [0:0] read-write scfg_dsi_txready_esc_sel SCFG DSI TX Ready Escape Select: u0_mipitx_dphy_SCFG_dsi_txready_esc_sel [2:1] read-write 0 3 scfg_ppi_c_ready_sel SCFG PPI C Ready Select: u0_mipitx_dphy_SCFG_ppi_c_ready_sel [4:3] read-write 0 3 vcontrol VCONTROL: u0_mipitx_dphy_VCONTROL [9:5] read-write 0 31 12 0x4 00,01,02,03,04,05,06,07,08,09,0A,0B syscfg_xcfgi[%s] MIPITX DPHY SYSCFG 13-24: mipitx_apbifsaif_syscfg_52-96 0x34 0x20 0x00000000 dw XCFGI DW: u0_mipitx_dphy_XCFGI_DW [31:0] read-write 0 4294967295 syscfg25 MIPITX DPHY SYSCFG 25: mipitx_apbifsaif_syscfg_100 0x64 0x20 0x00000000 dbg1_mux_dout DBG1 Mux DOUT: u0_mipitx_dphy_dbg1_mux_dout [7:0] read-only dbg1_mux_sel DBG1 Mux Select: u0_mipitx_dphy_dbg1_mux_sel [12:8] read-write 0 31 dbg2_mux_dout DBG2 Mux DOUT: u0_mipitx_dphy_dbg2_mux_dout [20:13] read-only dbg2_mux_sel DBG2 Mux Select: u0_mipitx_dphy_dbg2_mux_sel [25:21] read-write 0 31 refclk_in_sel Reference Clock In Select: u0_mipitx_dphy_refclk_in_sel [28:26] read-write 0 7 resetb Reset B: u0_mipitx_dphy_resetb [29:29] read-write