#[doc = "Register `ssp_imsc` reader"]
pub type R = crate::R<SspImscSpec>;
#[doc = "Register `ssp_imsc` writer"]
pub type W = crate::W<SspImscSpec>;
#[doc = "Receive overrun interrupt mask\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Rorim {
    #[doc = "0: Receive FIFO written to while full condition interrupt is masked"]
    Masked = 0,
    #[doc = "1: Receive FIFO written to while full condition interrupt is not masked"]
    NotMasked = 1,
}
impl From<Rorim> for bool {
    #[inline(always)]
    fn from(variant: Rorim) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `rorim` reader - Receive overrun interrupt mask"]
pub type RorimR = crate::BitReader<Rorim>;
impl RorimR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Rorim {
        match self.bits {
            false => Rorim::Masked,
            true => Rorim::NotMasked,
        }
    }
    #[doc = "Receive FIFO written to while full condition interrupt is masked"]
    #[inline(always)]
    pub fn is_masked(&self) -> bool {
        *self == Rorim::Masked
    }
    #[doc = "Receive FIFO written to while full condition interrupt is not masked"]
    #[inline(always)]
    pub fn is_not_masked(&self) -> bool {
        *self == Rorim::NotMasked
    }
}
#[doc = "Field `rorim` writer - Receive overrun interrupt mask"]
pub type RorimW<'a, REG> = crate::BitWriter<'a, REG, Rorim>;
impl<'a, REG> RorimW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    #[doc = "Receive FIFO written to while full condition interrupt is masked"]
    #[inline(always)]
    pub fn masked(self) -> &'a mut crate::W<REG> {
        self.variant(Rorim::Masked)
    }
    #[doc = "Receive FIFO written to while full condition interrupt is not masked"]
    #[inline(always)]
    pub fn not_masked(self) -> &'a mut crate::W<REG> {
        self.variant(Rorim::NotMasked)
    }
}
#[doc = "Receive timeout interrupt mask\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Rtim {
    #[doc = "0: Receive FIFO not empty and no read prior to timeout period interrupt is masked"]
    Masked = 0,
    #[doc = "1: Receive FIFO not empty and no read prior to timeout period interrupt is not masked"]
    NotMasked = 1,
}
impl From<Rtim> for bool {
    #[inline(always)]
    fn from(variant: Rtim) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `rtim` reader - Receive timeout interrupt mask"]
pub type RtimR = crate::BitReader<Rtim>;
impl RtimR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Rtim {
        match self.bits {
            false => Rtim::Masked,
            true => Rtim::NotMasked,
        }
    }
    #[doc = "Receive FIFO not empty and no read prior to timeout period interrupt is masked"]
    #[inline(always)]
    pub fn is_masked(&self) -> bool {
        *self == Rtim::Masked
    }
    #[doc = "Receive FIFO not empty and no read prior to timeout period interrupt is not masked"]
    #[inline(always)]
    pub fn is_not_masked(&self) -> bool {
        *self == Rtim::NotMasked
    }
}
#[doc = "Field `rtim` writer - Receive timeout interrupt mask"]
pub type RtimW<'a, REG> = crate::BitWriter<'a, REG, Rtim>;
impl<'a, REG> RtimW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    #[doc = "Receive FIFO not empty and no read prior to timeout period interrupt is masked"]
    #[inline(always)]
    pub fn masked(self) -> &'a mut crate::W<REG> {
        self.variant(Rtim::Masked)
    }
    #[doc = "Receive FIFO not empty and no read prior to timeout period interrupt is not masked"]
    #[inline(always)]
    pub fn not_masked(self) -> &'a mut crate::W<REG> {
        self.variant(Rtim::NotMasked)
    }
}
#[doc = "Receive FIFO interrupt mask\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Rxim {
    #[doc = "0: Receive FIFO half full or less condition interrupt is masked"]
    Masked = 0,
    #[doc = "1: Receive FIFO half full or less condition interrupt is not masked"]
    NotMasked = 1,
}
impl From<Rxim> for bool {
    #[inline(always)]
    fn from(variant: Rxim) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `rxim` reader - Receive FIFO interrupt mask"]
pub type RximR = crate::BitReader<Rxim>;
impl RximR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Rxim {
        match self.bits {
            false => Rxim::Masked,
            true => Rxim::NotMasked,
        }
    }
    #[doc = "Receive FIFO half full or less condition interrupt is masked"]
    #[inline(always)]
    pub fn is_masked(&self) -> bool {
        *self == Rxim::Masked
    }
    #[doc = "Receive FIFO half full or less condition interrupt is not masked"]
    #[inline(always)]
    pub fn is_not_masked(&self) -> bool {
        *self == Rxim::NotMasked
    }
}
#[doc = "Field `rxim` writer - Receive FIFO interrupt mask"]
pub type RximW<'a, REG> = crate::BitWriter<'a, REG, Rxim>;
impl<'a, REG> RximW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    #[doc = "Receive FIFO half full or less condition interrupt is masked"]
    #[inline(always)]
    pub fn masked(self) -> &'a mut crate::W<REG> {
        self.variant(Rxim::Masked)
    }
    #[doc = "Receive FIFO half full or less condition interrupt is not masked"]
    #[inline(always)]
    pub fn not_masked(self) -> &'a mut crate::W<REG> {
        self.variant(Rxim::NotMasked)
    }
}
#[doc = "Transmit FIFO interrupt mask\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Txim {
    #[doc = "0: Transmit FIFO half empty or less condition interrupt is masked"]
    Masked = 0,
    #[doc = "1: Transmit FIFO half empty or less condition interrupt is not masked"]
    NotMasked = 1,
}
impl From<Txim> for bool {
    #[inline(always)]
    fn from(variant: Txim) -> Self {
        variant as u8 != 0
    }
}
#[doc = "Field `txim` reader - Transmit FIFO interrupt mask"]
pub type TximR = crate::BitReader<Txim>;
impl TximR {
    #[doc = "Get enumerated values variant"]
    #[inline(always)]
    pub const fn variant(&self) -> Txim {
        match self.bits {
            false => Txim::Masked,
            true => Txim::NotMasked,
        }
    }
    #[doc = "Transmit FIFO half empty or less condition interrupt is masked"]
    #[inline(always)]
    pub fn is_masked(&self) -> bool {
        *self == Txim::Masked
    }
    #[doc = "Transmit FIFO half empty or less condition interrupt is not masked"]
    #[inline(always)]
    pub fn is_not_masked(&self) -> bool {
        *self == Txim::NotMasked
    }
}
#[doc = "Field `txim` writer - Transmit FIFO interrupt mask"]
pub type TximW<'a, REG> = crate::BitWriter<'a, REG, Txim>;
impl<'a, REG> TximW<'a, REG>
where
    REG: crate::Writable + crate::RegisterSpec,
{
    #[doc = "Transmit FIFO half empty or less condition interrupt is masked"]
    #[inline(always)]
    pub fn masked(self) -> &'a mut crate::W<REG> {
        self.variant(Txim::Masked)
    }
    #[doc = "Transmit FIFO half empty or less condition interrupt is not masked"]
    #[inline(always)]
    pub fn not_masked(self) -> &'a mut crate::W<REG> {
        self.variant(Txim::NotMasked)
    }
}
impl R {
    #[doc = "Bit 0 - Receive overrun interrupt mask"]
    #[inline(always)]
    pub fn rorim(&self) -> RorimR {
        RorimR::new((self.bits & 1) != 0)
    }
    #[doc = "Bit 1 - Receive timeout interrupt mask"]
    #[inline(always)]
    pub fn rtim(&self) -> RtimR {
        RtimR::new(((self.bits >> 1) & 1) != 0)
    }
    #[doc = "Bit 2 - Receive FIFO interrupt mask"]
    #[inline(always)]
    pub fn rxim(&self) -> RximR {
        RximR::new(((self.bits >> 2) & 1) != 0)
    }
    #[doc = "Bit 3 - Transmit FIFO interrupt mask"]
    #[inline(always)]
    pub fn txim(&self) -> TximR {
        TximR::new(((self.bits >> 3) & 1) != 0)
    }
}
impl W {
    #[doc = "Bit 0 - Receive overrun interrupt mask"]
    #[inline(always)]
    #[must_use]
    pub fn rorim(&mut self) -> RorimW<SspImscSpec> {
        RorimW::new(self, 0)
    }
    #[doc = "Bit 1 - Receive timeout interrupt mask"]
    #[inline(always)]
    #[must_use]
    pub fn rtim(&mut self) -> RtimW<SspImscSpec> {
        RtimW::new(self, 1)
    }
    #[doc = "Bit 2 - Receive FIFO interrupt mask"]
    #[inline(always)]
    #[must_use]
    pub fn rxim(&mut self) -> RximW<SspImscSpec> {
        RximW::new(self, 2)
    }
    #[doc = "Bit 3 - Transmit FIFO interrupt mask"]
    #[inline(always)]
    #[must_use]
    pub fn txim(&mut self) -> TximW<SspImscSpec> {
        TximW::new(self, 3)
    }
}
#[doc = "The SSPIMSC register is the interrupt mask set or clear register. It is a RW register. On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. All the bits are cleared to 0 when reset.\n\nYou can [`read`](crate::Reg::read) this register and get [`ssp_imsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssp_imsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SspImscSpec;
impl crate::RegisterSpec for SspImscSpec {
    type Ux = u16;
}
#[doc = "`read()` method returns [`ssp_imsc::R`](R) reader structure"]
impl crate::Readable for SspImscSpec {}
#[doc = "`write(|w| ..)` method takes [`ssp_imsc::W`](W) writer structure"]
impl crate::Writable for SspImscSpec {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
}
#[doc = "`reset()` method sets ssp_imsc to value 0"]
impl crate::Resettable for SspImscSpec {
    const RESET_VALUE: u16 = 0;
}