NIIET K1921VK035 K1921VKx 2.10 Tiny motor control MCU ARM Limited (ARM) is supplying this software for use with Cortex-M\n processor based microcontroller, but can be equally used for other\n suitable processor architectures. This file can be freely distributed.\n Modifications to this file shall be clearly marked.\n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM4 r0p1 little true true 3 false 8 32 32 read-write 0x00000000 0xFFFFFFFF SIU 1.0 System integration unit registers SIU 0x40040000 32 read-write 0 0x1000 registers FPU FPU exception interrupt 69 PWMSYNC PWM syncronization control register 0x0010 32 read-write 0x00000000 0xFFFFFFFF PRESCRST PWM prescalers reset control [10:8] read-write SERVCTL Service mode control register 0x0014 32 read-write 0x00000000 0xFFFFFFFF CHIPCLR On-chip memories full clear task start [0:0] read-write DONE Status of clear task [1:1] read-only SERVEN [31:31] read-only CLKOUTCTL Clock out control register 0x0018 32 read-write 0x00000000 0xFFFFFFFF CLKOUTEN Enable clockout pin [0:0] read-write REMAPAF QEP altfunc control 0x001C 32 read-write 0x00000000 0xFFFFFFFF QEPEN Enable QEP altfunc [0:0] read-write ECAP0EN Enable ECAP0 altfunc [1:1] read-write ECAP1EN Enable ECAP1 altfunc [2:2] read-write ECAP2EN Enable ECAP2 altfunc [3:3] read-write DMAMUX DMA external requests mux control register 0x0020 32 read-write 0x00000000 0xFFFFFFFF SRCSEL8 Request source select for DMA channel 8 [0:0] read-write read-write QEP request by QEP 0 GPIOA request by GPIOA 1 SRCSEL9 Request source select for DMA channel 9 [4:4] read-write read-write TMR0 request by TMR0 0 GPIOB request by GPIOB 1 SRCSEL10 Request source select for DMA channel 10 [8:8] read-write read-write TMR1 request by TMR1 0 PWM0B request by PWM0B 1 SRCSEL11 Request source select for DMA channel 11 [12:12] read-write read-write TMR2 request by TMR2 0 PWM1B request by PWM1B 1 SRCSEL12 Request source select for DMA channel 12 [16:16] read-write read-write TMR3 request by TMR3 0 PWM2B request by PWM2B 1 SRCSEL13 Request source select for DMA channel 13 [20:20] read-write read-write PWM0A request by PWM0A 0 Reserved no source 1 SRCSEL14 Request source select for DMA channel 14 [24:24] read-write read-write PWM1A request by PWM1A 0 Reserved no source 1 SRCSEL15 Request source select for DMA channel 15 [28:28] read-write read-write PWM2A request by PWM2A 0 Reserved no source 1 CHIPID Chip identifier 0x0FFC 32 read-only 0x00000000 0xFFFFFFFF REV Revision number [3:0] read-only ID Model ID [31:4] read-only RCU 1.0 Reset and clock unit registers RCU 0x40041000 32 read-write 0 0x108 registers RCU Reset and clock unit interrupt 1 OSICFG Internal oscillator configuration register 0x0000 32 read-write 0x00000000 0xFFFFFFFF EN Oscillator 8MHz enable [0:0] read-write CAL Oscillator 8MHz calibration value [25:16] read-write OSECFG External oscillator configuration register 0x0004 32 read-write 0x00000000 0xFFFFFFFF XOEN Enable output XO_OSC from external oscillator [0:0] read-write EN Enable external oscallator [1:1] read-write PLLCFG PLL configuration register 0x0008 32 read-write 0x00000000 0xFFFFFFFF M PLL M Coefficient [5:0] read-write N PLL N Coefficient [13:8] read-write OD PLL OD Coefficient [17:16] read-write read-write Disable disabled 0 Div2 divide by 2 1 Div4 divide by 4 2 Div8 divide by 8 3 REFSRC PLL Reference source select bit [20:20] read-write read-write OSECLK external oscillator 0 OSICLK internal oscillator 1 BYPASS PLL Bypass enable [24:24] read-write OUTEN Enable PLL out [26:26] read-write LOCK PLL status lock [28:28] read-only PLLDIV PLL divider register 0x000C 32 read-write 0x00000000 0xFFFFFFFF DIVEN PLL Divider enable bit [0:0] read-write DIV PLL divider coefficent [13:8] read-write SYSCLKCFG System clock configuration register 0x0010 32 read-write 0x00000000 0xFFFFFFFF SYSSEL System clock source selection [1:0] read-write read-write OSICLK internal oscillator 0 OSECLK external oscillator 1 PLLCLK PLL output clock 2 PLLDIVCLK PLL divided clock 3 SECEN Enable clock security system [16:16] read-write SYSCLKSTAT System clock status register 0x0014 32 read-only 0x00000000 0xFFFFFFFF SYSSTAT Current system source clock [1:0] read-only read OSICLK internal oscillator 0 OSECLK external oscillator 1 PLLCLK PLL output clock 2 PLLDIVCLK PLL divided clock 3 BUSY Clock manager is busy, for example, when change clock source [4:4] read-only SYSFAIL Error in current clock was detected [8:8] read-only OSECLKERR External oscillator clock fail [17:17] read-only PLLCLKERR PLL source clock fail [18:18] read-only PLLDIVCLKERR PLL divided clock fail [19:19] read-only OSECLKOK External oscillator clock good [25:25] read-only PLLCLKOK PLL clock good [26:26] read-only PLLDIVCLKOK PLL divided clock good [27:27] read-only SECPRD Security sysytem clock period register 0x0018 32 read-write 0x00000000 0xFFFFFFFF OSECLK Max counter value for external oscillator clock fail detection [15:8] read-write PLLCLK Max counter value for PLL clock fail detection [23:16] read-write PLLDIVCLK Max counter value for PLL clock fail detection [31:24] read-write SYSRSTCFG System reset configuration register 0x001C 32 read-write 0x00000000 0xFFFFFFFF LOCKUPEN Enable reset when processor in LOCKUP state [0:0] read-write SYSRSTSTAT Reset status register 0x0020 32 read-write 0x00000000 0xFFFFFFFF POR PowerOn Reset status [0:0] read-write WDOG WatchDog Reset status [1:1] read-write SYSRST System Reset Status [2:2] read-write LOCKUP Lockup Reset Status [3:3] read-write INTEN Interrupt enable register 0x0024 32 read-write 0x00000000 0xFFFFFFFF OSECLKERR Enable OSECLK fail interrupt [1:1] read-write PLLCLKERR Enable PLLCLK fail interrupt [2:2] read-write PLLDIVCLKERR Enable PLLDIVCLK fail interrupt [3:3] read-write OSECLKOK Enable OSECLK good interrupt [9:9] read-write PLLCLKOK Enable PLLCLK good interrupt [10:10] read-write PLLDIVCLKOK Enable PLLDIVCLK good interrupt [11:11] read-write PLLLOCK Enable int from pll lock signal [16:16] read-write INTSTAT Interrupt status register 0x0028 32 read-write 0x00000000 0xFFFFFFFF OSECLKERR Status external oscillator clock fail signal [1:1] read-write PLLCLKERR Status PLL clock fail signal [2:2] read-write PLLDIVCLKERR Status PLLDIV clock fail signal [3:3] read-write OSECLKOK Status external oscillator clock good signal [9:9] read-write PLLCLKOK Status PLL clock good signal [10:10] read-write PLLDIVCLKOK Status PLLDIV clock good signal [11:11] read-write PLLLOCK Status pll lock signal [16:16] read-write SYSFAIL Current clock failed status [20:20] read-write TRACECFG Trace clock configuration register 0x002C 32 read-write 0x00000000 0xFFFFFFFF CLKEN Clock enable [0:0] read-write CLKSEL Clock source select [9:8] read-write read-write OSICLK internal oscillator 0 OSECLK external oscillator 1 PLLCLK PLL output clock 2 PLLDIVCLK PLL divided clock 3 DIVEN Enable divider [16:16] read-write DIVN Divider coefficient [29:24] read-write CLKOUTCFG Clockout configuration register 0x0030 32 read-write 0x00000000 0xFFFFFFFF CLKEN Clock enable [0:0] read-write CLKSEL Clock source select [9:8] read-write read-write OSICLK internal oscillator 0 OSECLK external oscillator 1 PLLCLK PLL output clock 2 PLLDIVCLK PLL divided clock 3 DIVEN Enable divider [16:16] read-write DIVN Divider coefficient [26:24] read-write WDTCFG WatchDog configuration register 0x0034 32 read-write 0x00000000 0xFFFFFFFF CLKEN Clock enable [0:0] read-write RSTDIS Reset disable [4:4] read-write CLKSEL Clock source select [9:8] read-write read-write OSICLK internal oscillator 0 OSECLK external oscillator 1 PLLCLK PLL output clock 2 PLLDIVCLK PLL divided clock 3 DIVEN Enable divider [16:16] read-write DIVN Divider coefficient [29:24] read-write 2 4 0-1 UARTCFG[%s] UARTCFG 0x060 UARTCFG UART clock and reset configuration register 0x00 32 read-write 0x00000000 0xFFFFFFFF CLKEN Clock enable [0:0] read-write RSTDIS Reset disable [4:4] read-write CLKSEL Clock source select [9:8] read-write read-write OSECLK external oscillator 0 PLLCLK PLL output clock 1 PLLDIVCLK PLL divided clock 2 OSICLK internal oscillator 3 DIVEN Enable divider [16:16] read-write DIVN Divider coefficient [29:24] read-write SPICFG SPI clock and reset configuration register 0x0080 32 read-write 0x00000000 0xFFFFFFFF CLKEN Clock enable [0:0] read-write RSTDIS Reset disable [4:4] read-write CLKSEL Clock source select [9:8] read-write read-write OSECLK external oscillator 0 PLLCLK PLL output clock 1 PLLDIVCLK PLL divided clock 2 OSICLK internal oscillator 3 DIVEN Enable divider [16:16] read-write DIVN Divider coefficient [29:24] read-write ADCCFG ADC clock and reset configuration register 0x00A0 32 read-write 0x00000000 0xFFFFFFFF CLKEN Clock enable [0:0] read-write RSTDIS Reset disable [4:4] read-write CLKSEL Clock source select [9:8] read-write read-write OSECLK external oscillator 0 PLLCLK PLL output clock 1 PLLDIVCLK PLL divided clock 2 OSICLK internal oscillator 3 DIVEN Enable divider [16:16] read-write DIVN Divider coefficient [29:24] read-write PCLKCFG APB clock configuration register 0x00E0 32 read-write 0x00000000 0xFFFFFFFF TMR0EN Enable clock for TMR0 [0:0] read-write TMR1EN Enable clock for TMR1 [1:1] read-write TMR2EN Enable clock for TMR2 [2:2] read-write TMR3EN Enable clock for TMR3 [3:3] read-write PWM0EN Enable clock for PWM0 [4:4] read-write PWM1EN Enable clock for PWM1 [5:5] read-write PWM2EN Enable clock for PWM2 [6:6] read-write I2CEN Enable clock for I2C [7:7] read-write QEPEN Enable clock for QEP [8:8] read-write ECAP0EN Enable clock for ECAP0 [9:9] read-write ECAP1EN Enable clock for ECAP1 [10:10] read-write ECAP2EN Enable clock for ECAP2 [11:11] read-write PRSTCFG APB reset configuration register 0x00F0 32 read-write 0x00000000 0xFFFFFFFF TMR0EN Disable reset from TMR0 [0:0] read-write TMR1EN Disable reset from TMR1 [1:1] read-write TMR2EN Disable reset from TMR2 [2:2] read-write TMR3EN Disable reset from TMR3 [3:3] read-write PWM0EN Disable reset from PWM0 [4:4] read-write PWM1EN Disable reset from PWM1 [5:5] read-write PWM2EN Disable reset from PWM2 [6:6] read-write I2CEN Disable reset from I2C [7:7] read-write QEPEN Disable reset from QEP [8:8] read-write ECAP0EN Disable reset from ECAP0 [9:9] read-write ECAP1EN Disable reset from ECAP1 [10:10] read-write ECAP2EN Disable reset from ECAP2 [11:11] read-write HCLKCFG AHB clock configuration register 0x0100 32 read-write 0x00000000 0xFFFFFFFF GPIOAEN Enable clock for GPIOA port [0:0] read-write GPIOBEN Enable clock for GPIOB port [1:1] read-write CANEN Enable clock for CAN [2:2] read-write HRSTCFG AHB reset configuration register 0x0104 32 read-write 0x00000000 0xFFFFFFFF GPIOAEN Disable reset from GPIOA port [0:0] read-write GPIOBEN Disable reset from GPIOB port [1:1] read-write CANEN Disable reset from CAN [2:2] read-write PMU 1.0 Power management unit registers PMU 0x40042000 32 read-write 0 0x010 registers CFG PMU Configuration Register 0x0000 32 read-write 0x00000000 0xFFFFFFFF EN Enable PMU [0:0] read-write PUDEL PMU Powerup Delay Value 0x0004 32 read-write 0x00000000 0xFFFFFFFF VAL Delay value for powerup peripheral blocks (in OSICLK ticks) [15:0] read-write PDEN PMU Enable Powerdown for peripheral 0x0008 32 read-write 0x00000000 0xFFFFFFFF PLLPD Enable powerdown for PLL [0:0] read-write MFLASHPD Enable powerdown for MFLASH [1:1] read-write OSEPD Enable powerdown for external oscillator [2:2] read-write RXEVEN PMU RX Event generation enable register 0x000C 32 read-write 0x00000000 0xFFFFFFFF GPIOAEV Enable RX event from GPIOA pins [0:0] read-write GPIOBEV Enable RX event from GPIOB pins [1:1] read-write WDT 1.0 Watchdog control registers WDT 0x40043000 32 read-write 0 0xC04 registers WDT Watchdog timer interrupt 0 LOAD Watchdog Load Register 0x0000 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write VALUE Watchdog Value Register 0x0004 32 read-only 0x00000000 0xFFFFFFFF VAL [31:0] read-only CTRL Watchdog Control Register 0x0008 32 read-write 0x00000000 0xFFFFFFFF INTEN Enable the interrupt event [0:0] read-write RESEN Enable watchdog reset output [1:1] read-write INTCLR Watchdog Clear Interrupt Register 0x000C 32 write-only 0x00000000 0xFFFFFFFF WDTCLR [31:0] write-only RIS Watchdog Raw Interrupt Status Register 0x0010 32 read-only 0x00000000 0xFFFFFFFF RAWWDTINT Raw interrupt status from the counter [0:0] read-only MIS Watchdog Interrupt Status Register 0x0014 32 read-only 0x00000000 0xFFFFFFFF WDTINT Enabled interrupt status from the counter [0:0] read-only LOCK Watchdog Lock Register 0x0C00 32 write-only 0x00000000 0xFFFFFFFF REGWRDIS Disable write to all registers Watchdog [0:0] write-only TMR0 1.0 TMR controller registers 4TMR 0x40048000 32 read-write 0 0x018 registers TMR0 Timer 0 interrupt 21 CTRL Control Timer register 0x0000 32 read-write 0x00000000 0xFFFFFFFF ON Enable Timer [0:0] read-write EXTINEN Enable external input as ENABLE [1:1] read-write EXTINCLK Enable external input as CLK [2:2] read-write INTEN Enable Timer interrupt [3:3] read-write VALUE Current value timer register 0x0004 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write LOAD Reload value timer register 0x0008 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write INTSTATUS Interrupt status register 0x000C 32 read-write 0x00000000 0xFFFFFFFF INT Timer interrupt flag [0:0] read-write DMAREQ DMA request register 0x0010 32 read-write 0x00000000 0xFFFFFFFF EN [0:0] read-write ADCSOC ADC start of conversion register 0x0014 32 read-write 0x00000000 0xFFFFFFFF EN [0:0] read-write TMR1 0x40049000 TMR1 Timer 1 interrupt 22 TMR2 0x4004A000 TMR2 Timer 2 interrupt 23 TMR3 0x4004B000 TMR3 Timer 3 interrupt 24 ADC 1.0 ADC control registers ADC 0x40000000 32 read-write 0 0x514 registers ADC_SEQ0 ADC Sequencer 0 interrupt 50 ADC_SEQ1 ADC Sequencer 1 interrupt 51 ADC_DC ADC Digital Comparator interrupt 52 SEQEN Enable sequencer register 0x0000 32 read-write 0x00000000 0xFFFFFFFF SEQEN0 Enable sequencer 0 [0:0] read-write SEQEN1 Enable sequencer 1 [1:1] read-write SEQSYNC Sequencer sync register 0x0004 32 read-write 0x00000000 0xFFFFFFFF SYNC0 Enable sequencer 0 software sync [0:0] read-write SYNC1 Enable sequencer 1 software sync [1:1] read-write GSYNC Sync all sequencers [31:31] write-only FSTAT FIFO overflow status register 0x0008 32 read-write 0x00000000 0xFFFFFFFF OV0 Sequencer 0 FIFO overflow [0:0] read-write OV1 Sequencer 1 FIFO overflow [1:1] read-write UN0 Sequencer 0 FIFO underflow [8:8] read-write UN1 Sequencer 1 FIFO underflow [9:9] read-write DOV0 Sequencer 0 FIFO DMA request overflow [16:16] read-write DOV1 Sequencer 1 FIFO DMA request overflow [17:17] read-write BSTAT Busy status register 0x000C 32 read-only 0x00000000 0xFFFFFFFF SEQBUSY0 Sequencer 0 busy [0:0] read-only SEQBUSY1 Sequencer 1 busy [1:1] read-only ADCBUSY ADC module conversion busy [16:16] read-only DCTRIG Digital comparator output trigger status register 0x0010 32 read-write 0x00000000 0xFFFFFFFF TOS0 DC 0 output trigger status [0:0] read-write TOS1 DC 1 output trigger status [1:1] read-write TOS2 DC 2 output trigger status [2:2] read-write TOS3 DC 3 output trigger status [3:3] read-write DCEV0 Digital compare event 0 [16:16] read-write DCEV1 Digital compare event 1 [17:17] read-write DCEV2 Digital compare event 2 [18:18] read-write DCEV3 Digital compare event 3 [19:19] read-write CICNT Interrupt counter clear control 0x0014 32 read-write 0x00000000 0xFFFFFFFF ICNT0 Clear interrupt counter on sequencer 0 start [0:0] read-write ICNT1 Clear interrupt counter on sequencer 1 start [1:1] read-write EMUX Sequencer start event selection register 0x0018 32 read-write 0x00000000 0xFFFFFFFF EM0 Select start event for sequencer 0 [3:0] read-write read-write SwReq software request by GSYNC bit 0 GPIOA GPIOA interrupt 1 GPIOB GPIOB interrupt 2 TMR0 Timer 0 request 3 TMR1 Timer 1 request 4 TMR2 Timer 2 request 5 TMR3 Timer 3 request 6 PWM012A PWM0,1,2 A channel request 7 PWM012B PWM0,1,2 B channel request 8 Cycle Cycle mode 15 EM1 Select start event for sequencer 1 [7:4] read-write read-write SwReq software request by GSYNC bit 0 GPIOA GPIOA interrupt 1 GPIOB GPIOB interrupt 2 TMR0 Timer 0 request 3 TMR1 Timer 1 request 4 TMR2 Timer 2 request 5 TMR3 Timer 3 request 6 PWM012A PWM0,1,2 A channel request 7 PWM012B PWM0,1,2 B channel request 8 Cycle Cycle mode 15 RIS Raw interrupt status register 0x001C 32 read-only 0x00000000 0xFFFFFFFF SEQRIS0 Sequencer 0 raw interrupt status [0:0] read-only SEQRIS1 Sequencer 1 raw interrupt status [1:1] read-only DCRIS0 Raw interrupt status of Digital Comparator 0 [8:8] read-only DCRIS1 Raw interrupt status of Digital Comparator 1 [9:9] read-only DCRIS2 Raw interrupt status of Digital Comparator 2 [10:10] read-only DCRIS3 Raw interrupt status of Digital Comparator 3 [11:11] read-only IM Interrupt mask register 0x0020 32 read-write 0x00000000 0xFFFFFFFF SEQIM0 Sequencer 0 interrupt mask [0:0] read-write SEQIM1 Sequencer 1 interrupt mask [1:1] read-write DCIM0 Interrupt mask of Digital Comparator 0 [8:8] read-write DCIM1 Interrupt mask of Digital Comparator 1 [9:9] read-write DCIM2 Interrupt mask of Digital Comparator 2 [10:10] read-write DCIM3 Interrupt mask of Digital Comparator 3 [11:11] read-write MIS Masked interrupt status and clear register 0x0024 32 read-only 0x00000000 0xFFFFFFFF SEQMIS0 Sequencer 0 masked interrupt status [0:0] read-only SEQMIS1 Sequencer 1 masked interrupt status [1:1] read-only DCMIS0 DC 0 masked interrupt status [8:8] read-only DCMIS1 DC 1 masked interrupt status [9:9] read-only DCMIS2 DC 2 masked interrupt status [10:10] read-only DCMIS3 DC 3 masked interrupt status [11:11] read-only IC Interrupt clear register 0x0028 32 write-only 0x00000000 0xFFFFFFFF SEQIC0 Sequencer 0 interrupt status clear [0:0] write-only SEQIC1 Sequencer 1 interrupt status clear [1:1] write-only DCIC0 DC 0 interrupt status clear [8:8] write-only DCIC1 DC 1 interrupt status clear [9:9] write-only DCIC2 DC 2 interrupt status clear [10:10] write-only DCIC3 DC 3 interrupt status clear [11:11] write-only 2 52 0-1 SEQ[%s] SEQ 0x040 SRQSEL Sequencer request ADC channels selection register 0x00 32 read-write 0x00000000 0xFFFFFFFF RQ0 Select ADC channel for request 0 [1:0] read-write RQ1 Select ADC channel for request 1 [5:4] read-write RQ2 Select ADC channel for request 2 [9:8] read-write RQ3 Select ADC channel for request 3 [13:12] read-write SRQCTL Sequencer request control register 0x10 32 read-write 0x00000000 0xFFFFFFFF RQMAX Request queue max depth [1:0] read-write QAVGEN Queue avearage (scanning) enable [8:8] read-write QAVGVAL Queue average value [11:9] read-write read-write Disable Average disabled 0 Average2 Average with 2 measures 1 Average4 Average with 4 measures 2 Average8 Average with 8 measures 3 Average16 Average with 16 measures 4 Average32 Average with 32 measures 5 Average64 Average with 64 measures 6 SRQSTAT Sequencer request status register 0x14 32 read-only 0x00000000 0xFFFFFFFF RQPTR Pointer to queue current request [1:0] read-only RQBUSY Active request status [8:8] read-only SDMACTL Sequencer DMA control register 0x18 32 read-write 0x00000000 0xFFFFFFFF DMAEN Enable DMA use [0:0] read-write WMARK FIFO load threshold for DMA request generation [10:8] read-write read-write Level1 1 measure for dma request 1 Level2 2 measures for dma request 2 Level4 4 measures for dma request 3 Level8 8 measures for dma request 4 Level16 16 measures for dma request 5 Level32 32 measures for dma request 6 SCCTL Sequencer ADC interrupt and restart counter control register 0x1C 32 read-write 0x00000000 0xFFFFFFFF RCNT Current number of ADC restarts by sequencer [7:0] read-write RAVGEN Average of ADC restarts enable [8:8] read-write ICNT Number of ADC requests for interrupt generation [23:16] read-write SCVAL Sequencer ADC interrupt and restart counter current value register 0x20 32 read-write 0x00000000 0xFFFFFFFF RCNT Current number of ADC restarts by sequencer [7:0] read-only ICNT Current number of ADC requests for interrupt generation [23:16] read-only ICLR Clear interrupt counter [24:24] write-only SDC Sequencer digital comparator selection register 0x24 32 read-write 0x00000000 0xFFFFFFFF DC0 Enable DC 0 [0:0] read-write DC1 Enable DC 1 [1:1] read-write DC2 Enable DC 2 [2:2] read-write DC3 Enable DC 3 [3:3] read-write SRTMR Sequencer ADC restart timer register 0x28 32 read-write 0x00000000 0xFFFFFFFF VAL Sequencer ADC restart timer value [23:0] read-write NOWAIT Timer update with no waiting the end of current seq task [31:31] read-write SFLOAD Sequencer FIFO load status register 0x2C 32 read-only 0x00000000 0xFFFFFFFF VAL Sequencer FIFO current load value [5:0] read-only SFIFO Sequencer FIFO register 0x30 32 read-only 0x00000000 0xFFFFFFFF DATA AD conversion value [11:0] read-only 4 12 0-3 DC[%s] DC 0x200 DCTL Digital comparator control register 0x00 32 read-write 0x00000000 0xFFFFFFFF CIM DC interrupt generation mode [1:0] read-write read-write Multiple multiple trigger mode 0 Single single trigger mode 1 MultipleHyst multiple trigger mode with hysteresis 2 SingleHyst single trigger mode with hysteresis 3 CIC DC interrupt generation compare conditions [3:2] read-write read-write Low result lower or equal COMP0 0 Window result between COMP0 and COMP1 or equal any of them 1 High result higher or equal COMP1 2 CIE Enable DC interrupt generation [4:4] read-write CTM DC output trigger mode [9:8] read-write read-write Multiple multiple trigger mode 0 Single single trigger mode 1 MultipleHyst multiple trigger mode with hysteresis 2 SingleHyst single trigger mode with hysteresis 3 CTC DC output trigger compare conditions [11:10] read-write read-write Low result lower or equal COMP0 0 Window result between COMP0 and COMP1 or equal any of them 1 High result higher or equal COMP1 2 CTE Enable DC output trigger [12:12] read-write CHNL ADC channel selection [17:16] read-write SRC Select data source for comparation: ADC module (0) or sequencer(1) [24:24] read-write DCMP Digital comparator range register 0x04 32 read-write 0x00000000 0xFFFFFFFF CMPL Low threshold compare value [11:0] read-write CMPH High threshold compare value [27:16] read-write DDATA Digital comparator last compared data register 0x08 32 read-only 0x00000000 0xFFFFFFFF VAL Value of last compared AD conversion result [11:0] read-only ACTL ADC module control register 0x0400 32 read-write 0x00000000 0xFFFFFFFF ADCEN Enable ADC module [0:0] read-write ADCRDY ADC ready for conversions [1:1] read-only 4 4 0-3 CHCTL[%s] CHCTL 0x500 CHCTL ADC channel control register 0x00 32 read-write 0x00000000 0xFFFFFFFF OFFTRIM ADC channel offset trimm value [8:0] read-write GAINTRIM ADC channel gain trimm value [24:16] read-write PRIORITY ADC channel priority level [28:28] read-write GPIOA 1.0 GPIO control registers 2GPIO 0x40010000 32 read-write 0 0xC04 registers GPIOA GPIO A interrupt 3 DATA Data Input register 0x0000 32 read-write 0x00000000 0xFFFFFFFF VAL [15:0] read-write DATAOUT Data output register 0x0004 32 read-write 0x00000000 0xFFFFFFFF VAL [15:0] read-write DATAOUTSET Data output set bits register 0x0008 32 read-write 0x00000000 0xFFFFFFFF PIN0 Data output set bit 0 [0:0] read-write PIN1 Data output set bit 1 [1:1] read-write PIN2 Data output set bit 2 [2:2] read-write PIN3 Data output set bit 3 [3:3] read-write PIN4 Data output set bit 4 [4:4] read-write PIN5 Data output set bit 5 [5:5] read-write PIN6 Data output set bit 6 [6:6] read-write PIN7 Data output set bit 7 [7:7] read-write PIN8 Data output set bit 8 [8:8] read-write PIN9 Data output set bit 9 [9:9] read-write PIN10 Data output set bit 10 [10:10] read-write PIN11 Data output set bit 11 [11:11] read-write PIN12 Data output set bit 12 [12:12] read-write PIN13 Data output set bit 13 [13:13] read-write PIN14 Data output set bit 14 [14:14] read-write PIN15 Data output set bit 15 [15:15] read-write DATAOUTCLR Data output clear bits register 0x000C 32 read-write 0x00000000 0xFFFFFFFF PIN0 Data output clear bit 0 [0:0] read-write PIN1 Data output clear bit 1 [1:1] read-write PIN2 Data output clear bit 2 [2:2] read-write PIN3 Data output clear bit 3 [3:3] read-write PIN4 Data output clear bit 4 [4:4] read-write PIN5 Data output clear bit 5 [5:5] read-write PIN6 Data output clear bit 6 [6:6] read-write PIN7 Data output clear bit 7 [7:7] read-write PIN8 Data output clear bit 8 [8:8] read-write PIN9 Data output clear bit 9 [9:9] read-write PIN10 Data output clear bit 10 [10:10] read-write PIN11 Data output clear bit 11 [11:11] read-write PIN12 Data output clear bit 12 [12:12] read-write PIN13 Data output clear bit 13 [13:13] read-write PIN14 Data output clear bit 14 [14:14] read-write PIN15 Data output clear bit 15 [15:15] read-write DATAOUTTGL Data output toogle bits register 0x0010 32 read-write 0x00000000 0xFFFFFFFF PIN0 Data output toogle bit 0 [0:0] read-write PIN1 Data output toogle bit 1 [1:1] read-write PIN2 Data output toogle bit 2 [2:2] read-write PIN3 Data output toogle bit 3 [3:3] read-write PIN4 Data output toogle bit 4 [4:4] read-write PIN5 Data output toogle bit 5 [5:5] read-write PIN6 Data output toogle bit 6 [6:6] read-write PIN7 Data output toogle bit 7 [7:7] read-write PIN8 Data output toogle bit 8 [8:8] read-write PIN9 Data output toogle bit 9 [9:9] read-write PIN10 Data output toogle bit 10 [10:10] read-write PIN11 Data output toogle bit 11 [11:11] read-write PIN12 Data output toogle bit 12 [12:12] read-write PIN13 Data output toogle bit 13 [13:13] read-write PIN14 Data output toogle bit 14 [14:14] read-write PIN15 Data output toogle bit 15 [15:15] read-write DENSET Digital function (PAD) enable register 0x0014 32 read-write 0x00000000 0xFFFFFFFF PIN0 Digital function (PAD) enable on pin 0 [0:0] read-write PIN1 Digital function (PAD) enable on pin 1 [1:1] read-write PIN2 Digital function (PAD) enable on pin 2 [2:2] read-write PIN3 Digital function (PAD) enable on pin 3 [3:3] read-write PIN4 Digital function (PAD) enable on pin 4 [4:4] read-write PIN5 Digital function (PAD) enable on pin 5 [5:5] read-write PIN6 Digital function (PAD) enable on pin 6 [6:6] read-write PIN7 Digital function (PAD) enable on pin 7 [7:7] read-write PIN8 Digital function (PAD) enable on pin 8 [8:8] read-write PIN9 Digital function (PAD) enable on pin 9 [9:9] read-write PIN10 Digital function (PAD) enable on pin 10 [10:10] read-write PIN11 Digital function (PAD) enable on pin 11 [11:11] read-write PIN12 Digital function (PAD) enable on pin 12 [12:12] read-write PIN13 Digital function (PAD) enable on pin 13 [13:13] read-write PIN14 Digital function (PAD) enable on pin 14 [14:14] read-write PIN15 Digital function (PAD) enable on pin 15 [15:15] read-write DENCLR Digital function (PAD) disable register 0x0018 32 read-write 0x00000000 0xFFFFFFFF PIN0 Digital function (PAD) disable on pin 0 [0:0] read-write PIN1 Digital function (PAD) disable on pin 1 [1:1] read-write PIN2 Digital function (PAD) disable on pin 2 [2:2] read-write PIN3 Digital function (PAD) disable on pin 3 [3:3] read-write PIN4 Digital function (PAD) disable on pin 4 [4:4] read-write PIN5 Digital function (PAD) disable on pin 5 [5:5] read-write PIN6 Digital function (PAD) disable on pin 6 [6:6] read-write PIN7 Digital function (PAD) disable on pin 7 [7:7] read-write PIN8 Digital function (PAD) disable on pin 8 [8:8] read-write PIN9 Digital function (PAD) disable on pin 9 [9:9] read-write PIN10 Digital function (PAD) disable on pin 10 [10:10] read-write PIN11 Digital function (PAD) disable on pin 11 [11:11] read-write PIN12 Digital function (PAD) disable on pin 12 [12:12] read-write PIN13 Digital function (PAD) disable on pin 13 [13:13] read-write PIN14 Digital function (PAD) disable on pin 14 [14:14] read-write PIN15 Digital function (PAD) disable on pin 15 [15:15] read-write INMODE Select input mode register 0x001C 32 read-write 0x00000000 0xFFFFFFFF PIN0 Select input mode for pin 0 [1:0] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN1 Select input mode for pin 1 [3:2] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN2 Select input mode for pin 2 [5:4] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN3 Select input mode for pin 3 [7:6] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN4 Select input mode for pin 4 [9:8] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN5 Select input mode for pin 5 [11:10] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN6 Select input mode for pin 6 [13:12] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN7 Select input mode for pin 7 [15:14] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN8 Select input mode for pin 8 [17:16] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN9 Select input mode for pin 9 [19:18] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN10 Select input mode for pin 10 [21:20] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN11 Select input mode for pin 11 [23:22] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN12 Select input mode for pin 12 [25:24] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN13 Select input mode for pin 13 [27:26] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN14 Select input mode for pin 14 [29:28] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PIN15 Select input mode for pin 15 [31:30] read-write read-write Schmitt Scmitt buffer 0 CMOS CMOS buffer 1 Disable Input buffer disabled 3 PULLMODE Select pull mode register 0x0020 32 read-write 0x00000000 0xFFFFFFFF PIN0 Select pull mode for pin 0 [1:0] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN1 Select pull mode for pin 1 [3:2] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN2 Select pull mode for pin 2 [5:4] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN3 Select pull mode for pin 3 [7:6] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN4 Select pull mode for pin 4 [9:8] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN5 Select pull mode for pin 5 [11:10] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN6 Select pull mode for pin 6 [13:12] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN7 Select pull mode for pin 7 [15:14] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN8 Select pull mode for pin 8 [17:16] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN9 Select pull mode for pin 9 [19:18] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN10 Select pull mode for pin 10 [21:20] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN11 Select pull mode for pin 11 [23:22] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN12 Select pull mode for pin 12 [25:24] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN13 Select pull mode for pin 13 [27:26] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN14 Select pull mode for pin 14 [29:28] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 PIN15 Select pull mode for pin 15 [31:30] read-write read-write Disable Pull disabled 0 PU Pull-up 1 PD Pull-down 2 OUTMODE Select output mode register 0x0024 32 read-write 0x00000000 0xFFFFFFFF PIN0 Select output mode for pin 0 [1:0] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN1 Select output mode for pin 1 [3:2] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN2 Select output mode for pin 2 [5:4] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN3 Select output mode for pin 3 [7:6] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN4 Select output mode for pin 4 [9:8] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN5 Select output mode for pin 5 [11:10] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN6 Select output mode for pin 6 [13:12] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN7 Select output mode for pin 7 [15:14] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN8 Select output mode for pin 8 [17:16] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN9 Select output mode for pin 9 [19:18] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN10 Select output mode for pin 10 [21:20] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN11 Select output mode for pin 11 [23:22] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN12 Select output mode for pin 12 [25:24] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN13 Select output mode for pin 13 [27:26] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN14 Select output mode for pin 14 [29:28] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 PIN15 Select output mode for pin 15 [31:30] read-write read-write PP Push-pull output 0 OD Open drain output 1 OS Open source output 2 DRIVEMODE Select drive mode register 0x0028 32 read-write 0x00000000 0xFFFFFFFF PIN0 Select drive mode for pin 0 [1:0] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN1 Select drive mode for pin 1 [3:2] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN2 Select drive mode for pin 2 [5:4] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN3 Select drive mode for pin 3 [7:6] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN4 Select drive mode for pin 4 [9:8] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN5 Select drive mode for pin 5 [11:10] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN6 Select drive mode for pin 6 [13:12] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN7 Select drive mode for pin 7 [15:14] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN8 Select drive mode for pin 8 [17:16] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN9 Select drive mode for pin 9 [19:18] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN10 Select drive mode for pin 10 [21:20] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN11 Select drive mode for pin 11 [23:22] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN12 Select drive mode for pin 12 [25:24] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN13 Select drive mode for pin 13 [27:26] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN14 Select drive mode for pin 14 [29:28] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 PIN15 Select drive mode for pin 15 [31:30] read-write read-write HF High strength and Fast rate 0 HS High strength and Slow rate 1 LF Low strength and Fast rate 2 LS Low strength and Slow rate 3 OUTENSET Output enable register 0x002C 32 read-write 0x00000000 0xFFFFFFFF PIN0 Output enable for pin 0 [0:0] read-write PIN1 Output enable for pin 1 [1:1] read-write PIN2 Output enable for pin 2 [2:2] read-write PIN3 Output enable for pin 3 [3:3] read-write PIN4 Output enable for pin 4 [4:4] read-write PIN5 Output enable for pin 5 [5:5] read-write PIN6 Output enable for pin 6 [6:6] read-write PIN7 Output enable for pin 7 [7:7] read-write PIN8 Output enable for pin 8 [8:8] read-write PIN9 Output enable for pin 9 [9:9] read-write PIN10 Output enable for pin 10 [10:10] read-write PIN11 Output enable for pin 11 [11:11] read-write PIN12 Output enable for pin 12 [12:12] read-write PIN13 Output enable for pin 13 [13:13] read-write PIN14 Output enable for pin 14 [14:14] read-write PIN15 Output enable for pin 15 [15:15] read-write OUTENCLR Output disable register 0x0030 32 read-write 0x00000000 0xFFFFFFFF PIN0 Output disable for pin 0 [0:0] read-write PIN1 Output disable for pin 1 [1:1] read-write PIN2 Output disable for pin 2 [2:2] read-write PIN3 Output disable for pin 3 [3:3] read-write PIN4 Output disable for pin 4 [4:4] read-write PIN5 Output disable for pin 5 [5:5] read-write PIN6 Output disable for pin 6 [6:6] read-write PIN7 Output disable for pin 7 [7:7] read-write PIN8 Output disable for pin 8 [8:8] read-write PIN9 Output disable for pin 9 [9:9] read-write PIN10 Output disable for pin 10 [10:10] read-write PIN11 Output disable for pin 11 [11:11] read-write PIN12 Output disable for pin 12 [12:12] read-write PIN13 Output disable for pin 13 [13:13] read-write PIN14 Output disable for pin 14 [14:14] read-write PIN15 Output disable for pin 15 [15:15] read-write ALTFUNCSET Alternative function enable register 0x0034 32 read-write 0x00000000 0xFFFFFFFF PIN0 Alternative function enable for pin 0 [0:0] read-write PIN1 Alternative function enable for pin 1 [1:1] read-write PIN2 Alternative function enable for pin 2 [2:2] read-write PIN3 Alternative function enable for pin 3 [3:3] read-write PIN4 Alternative function enable for pin 4 [4:4] read-write PIN5 Alternative function enable for pin 5 [5:5] read-write PIN6 Alternative function enable for pin 6 [6:6] read-write PIN7 Alternative function enable for pin 7 [7:7] read-write PIN8 Alternative function enable for pin 8 [8:8] read-write PIN9 Alternative function enable for pin 9 [9:9] read-write PIN10 Alternative function enable for pin 10 [10:10] read-write PIN11 Alternative function enable for pin 11 [11:11] read-write PIN12 Alternative function enable for pin 12 [12:12] read-write PIN13 Alternative function enable for pin 13 [13:13] read-write PIN14 Alternative function enable for pin 14 [14:14] read-write PIN15 Alternative function enable for pin 15 [15:15] read-write ALTFUNCCLR Alternative function disable register 0x0038 32 read-write 0x00000000 0xFFFFFFFF PIN0 Alternative function disable for pin 0 [0:0] read-write PIN1 Alternative function disable for pin 1 [1:1] read-write PIN2 Alternative function disable for pin 2 [2:2] read-write PIN3 Alternative function disable for pin 3 [3:3] read-write PIN4 Alternative function disable for pin 4 [4:4] read-write PIN5 Alternative function disable for pin 5 [5:5] read-write PIN6 Alternative function disable for pin 6 [6:6] read-write PIN7 Alternative function disable for pin 7 [7:7] read-write PIN8 Alternative function disable for pin 8 [8:8] read-write PIN9 Alternative function disable for pin 9 [9:9] read-write PIN10 Alternative function disable for pin 10 [10:10] read-write PIN11 Alternative function disable for pin 11 [11:11] read-write PIN12 Alternative function disable for pin 12 [12:12] read-write PIN13 Alternative function disable for pin 13 [13:13] read-write PIN14 Alternative function disable for pin 14 [14:14] read-write PIN15 Alternative function disable for pin 15 [15:15] read-write SYNCSET Additional double flip-flop syncronization enable register 0x0044 32 read-write 0x00000000 0xFFFFFFFF PIN0 Additional double flip-flop syncronization buffer enable for pin 0 [0:0] read-write PIN1 Additional double flip-flop syncronization buffer enable for pin 1 [1:1] read-write PIN2 Additional double flip-flop syncronization buffer enable for pin 2 [2:2] read-write PIN3 Additional double flip-flop syncronization buffer enable for pin 3 [3:3] read-write PIN4 Additional double flip-flop syncronization buffer enable for pin 4 [4:4] read-write PIN5 Additional double flip-flop syncronization buffer enable for pin 5 [5:5] read-write PIN6 Additional double flip-flop syncronization buffer enable for pin 6 [6:6] read-write PIN7 Additional double flip-flop syncronization buffer enable for pin 7 [7:7] read-write PIN8 Additional double flip-flop syncronization buffer enable for pin 8 [8:8] read-write PIN9 Additional double flip-flop syncronization buffer enable for pin 9 [9:9] read-write PIN10 Additional double flip-flop syncronization buffer enable for pin 10 [10:10] read-write PIN11 Additional double flip-flop syncronization buffer enable for pin 11 [11:11] read-write PIN12 Additional double flip-flop syncronization buffer enable for pin 12 [12:12] read-write PIN13 Additional double flip-flop syncronization buffer enable for pin 13 [13:13] read-write PIN14 Additional double flip-flop syncronization buffer enable for pin 14 [14:14] read-write PIN15 Additional double flip-flop syncronization buffer enable for pin 15 [15:15] read-write SYNCCLR Additional double flip-flop syncronization disable register 0x0048 32 read-write 0x00000000 0xFFFFFFFF PIN0 Additional double flip-flop syncronization disable for pin 0 [0:0] read-write PIN1 Additional double flip-flop syncronization disable for pin 1 [1:1] read-write PIN2 Additional double flip-flop syncronization disable for pin 2 [2:2] read-write PIN3 Additional double flip-flop syncronization disable for pin 3 [3:3] read-write PIN4 Additional double flip-flop syncronization disable for pin 4 [4:4] read-write PIN5 Additional double flip-flop syncronization disable for pin 5 [5:5] read-write PIN6 Additional double flip-flop syncronization disable for pin 6 [6:6] read-write PIN7 Additional double flip-flop syncronization disable for pin 7 [7:7] read-write PIN8 Additional double flip-flop syncronization disable for pin 8 [8:8] read-write PIN9 Additional double flip-flop syncronization disable for pin 9 [9:9] read-write PIN10 Additional double flip-flop syncronization disable for pin 10 [10:10] read-write PIN11 Additional double flip-flop syncronization disable for pin 11 [11:11] read-write PIN12 Additional double flip-flop syncronization disable for pin 12 [12:12] read-write PIN13 Additional double flip-flop syncronization disable for pin 13 [13:13] read-write PIN14 Additional double flip-flop syncronization disable for pin 14 [14:14] read-write PIN15 Additional double flip-flop syncronization disable for pin 15 [15:15] read-write QUALSET Qualifier enable register 0x004C 32 read-write 0x00000000 0xFFFFFFFF PIN0 Qualifier enable for pin 0 [0:0] read-write PIN1 Qualifier enable for pin 1 [1:1] read-write PIN2 Qualifier enable for pin 2 [2:2] read-write PIN3 Qualifier enable for pin 3 [3:3] read-write PIN4 Qualifier enable for pin 4 [4:4] read-write PIN5 Qualifier enable for pin 5 [5:5] read-write PIN6 Qualifier enable for pin 6 [6:6] read-write PIN7 Qualifier enable for pin 7 [7:7] read-write PIN8 Qualifier enable for pin 8 [8:8] read-write PIN9 Qualifier enable for pin 9 [9:9] read-write PIN10 Qualifier enable for pin 10 [10:10] read-write PIN11 Qualifier enable for pin 11 [11:11] read-write PIN12 Qualifier enable for pin 12 [12:12] read-write PIN13 Qualifier enable for pin 13 [13:13] read-write PIN14 Qualifier enable for pin 14 [14:14] read-write PIN15 Qualifier enable for pin 15 [15:15] read-write QUALCLR Qualifier disable register 0x0050 32 read-write 0x00000000 0xFFFFFFFF PIN0 Qualifier disable for pin 0 [0:0] read-write PIN1 Qualifier disable for pin 1 [1:1] read-write PIN2 Qualifier disable for pin 2 [2:2] read-write PIN3 Qualifier disable for pin 3 [3:3] read-write PIN4 Qualifier disable for pin 4 [4:4] read-write PIN5 Qualifier disable for pin 5 [5:5] read-write PIN6 Qualifier disable for pin 6 [6:6] read-write PIN7 Qualifier disable for pin 7 [7:7] read-write PIN8 Qualifier disable for pin 8 [8:8] read-write PIN9 Qualifier disable for pin 9 [9:9] read-write PIN10 Qualifier disable for pin 10 [10:10] read-write PIN11 Qualifier disable for pin 11 [11:11] read-write PIN12 Qualifier disable for pin 12 [12:12] read-write PIN13 Qualifier disable for pin 13 [13:13] read-write PIN14 Qualifier disable for pin 14 [14:14] read-write PIN15 Qualifier disable for pin 15 [15:15] read-write QUALMODESET Qualifier mode set register 0x0054 32 read-write 0x00000000 0xFFFFFFFF PIN0 Qualifier mode set for pin 0 [0:0] read-write PIN1 Qualifier mode set for pin 1 [1:1] read-write PIN2 Qualifier mode set for pin 2 [2:2] read-write PIN3 Qualifier mode set for pin 3 [3:3] read-write PIN4 Qualifier mode set for pin 4 [4:4] read-write PIN5 Qualifier mode set for pin 5 [5:5] read-write PIN6 Qualifier mode set for pin 6 [6:6] read-write PIN7 Qualifier mode set for pin 7 [7:7] read-write PIN8 Qualifier mode set for pin 8 [8:8] read-write PIN9 Qualifier mode set for pin 9 [9:9] read-write PIN10 Qualifier mode set for pin 10 [10:10] read-write PIN11 Qualifier mode set for pin 11 [11:11] read-write PIN12 Qualifier mode set for pin 12 [12:12] read-write PIN13 Qualifier mode set for pin 13 [13:13] read-write PIN14 Qualifier mode set for pin 14 [14:14] read-write PIN15 Qualifier mode set for pin 15 [15:15] read-write QUALMODECLR Qualifier mode clear register 0x0058 32 read-write 0x00000000 0xFFFFFFFF PIN0 Qualifier mode clear for pin 0 [0:0] read-write PIN1 Qualifier mode clear for pin 1 [1:1] read-write PIN2 Qualifier mode clear for pin 2 [2:2] read-write PIN3 Qualifier mode clear for pin 3 [3:3] read-write PIN4 Qualifier mode clear for pin 4 [4:4] read-write PIN5 Qualifier mode clear for pin 5 [5:5] read-write PIN6 Qualifier mode clear for pin 6 [6:6] read-write PIN7 Qualifier mode clear for pin 7 [7:7] read-write PIN8 Qualifier mode clear for pin 8 [8:8] read-write PIN9 Qualifier mode clear for pin 9 [9:9] read-write PIN10 Qualifier mode clear for pin 10 [10:10] read-write PIN11 Qualifier mode clear for pin 11 [11:11] read-write PIN12 Qualifier mode clear for pin 12 [12:12] read-write PIN13 Qualifier mode clear for pin 13 [13:13] read-write PIN14 Qualifier mode clear for pin 14 [14:14] read-write PIN15 Qualifier mode clear for pin 15 [15:15] read-write QUALSAMPLE Qualifier sample period register 0x005C 32 read-write 0x00000000 0xFFFFFFFF VAL Qualifier sample period [7:0] read-write INTENSET Interrupt enable register 0x0060 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt enable for pin 0 [0:0] read-write PIN1 Interrupt enable for pin 1 [1:1] read-write PIN2 Interrupt enable for pin 2 [2:2] read-write PIN3 Interrupt enable for pin 3 [3:3] read-write PIN4 Interrupt enable for pin 4 [4:4] read-write PIN5 Interrupt enable for pin 5 [5:5] read-write PIN6 Interrupt enable for pin 6 [6:6] read-write PIN7 Interrupt enable for pin 7 [7:7] read-write PIN8 Interrupt enable for pin 8 [8:8] read-write PIN9 Interrupt enable for pin 9 [9:9] read-write PIN10 Interrupt enable for pin 10 [10:10] read-write PIN11 Interrupt enable for pin 11 [11:11] read-write PIN12 Interrupt enable for pin 12 [12:12] read-write PIN13 Interrupt enable for pin 13 [13:13] read-write PIN14 Interrupt enable for pin 14 [14:14] read-write PIN15 Interrupt enable for pin 15 [15:15] read-write INTENCLR Interrupt disable register 0x0064 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt disable for pin 0 [0:0] read-write PIN1 Interrupt disable for pin 1 [1:1] read-write PIN2 Interrupt disable for pin 2 [2:2] read-write PIN3 Interrupt disable for pin 3 [3:3] read-write PIN4 Interrupt disable for pin 4 [4:4] read-write PIN5 Interrupt disable for pin 5 [5:5] read-write PIN6 Interrupt disable for pin 6 [6:6] read-write PIN7 Interrupt disable for pin 7 [7:7] read-write PIN8 Interrupt disable for pin 8 [8:8] read-write PIN9 Interrupt disable for pin 9 [9:9] read-write PIN10 Interrupt disable for pin 10 [10:10] read-write PIN11 Interrupt disable for pin 11 [11:11] read-write PIN12 Interrupt disable for pin 12 [12:12] read-write PIN13 Interrupt disable for pin 13 [13:13] read-write PIN14 Interrupt disable for pin 14 [14:14] read-write PIN15 Interrupt disable for pin 15 [15:15] read-write INTTYPESET Interrupt type set register 0x0068 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt type set for pin 0 [0:0] read-write PIN1 Interrupt type set for pin 1 [1:1] read-write PIN2 Interrupt type set for pin 2 [2:2] read-write PIN3 Interrupt type set for pin 3 [3:3] read-write PIN4 Interrupt type set for pin 4 [4:4] read-write PIN5 Interrupt type set for pin 5 [5:5] read-write PIN6 Interrupt type set for pin 6 [6:6] read-write PIN7 Interrupt type set for pin 7 [7:7] read-write PIN8 Interrupt type set for pin 8 [8:8] read-write PIN9 Interrupt type set for pin 9 [9:9] read-write PIN10 Interrupt type set for pin 10 [10:10] read-write PIN11 Interrupt type set for pin 11 [11:11] read-write PIN12 Interrupt type set for pin 12 [12:12] read-write PIN13 Interrupt type set for pin 13 [13:13] read-write PIN14 Interrupt type set for pin 14 [14:14] read-write PIN15 Interrupt type set for pin 15 [15:15] read-write INTTYPECLR Interrupt type clear register 0x006C 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt type clear for pin 0 [0:0] read-write PIN1 Interrupt type clear for pin 1 [1:1] read-write PIN2 Interrupt type clear for pin 2 [2:2] read-write PIN3 Interrupt type clear for pin 3 [3:3] read-write PIN4 Interrupt type clear for pin 4 [4:4] read-write PIN5 Interrupt type clear for pin 5 [5:5] read-write PIN6 Interrupt type clear for pin 6 [6:6] read-write PIN7 Interrupt type clear for pin 7 [7:7] read-write PIN8 Interrupt type clear for pin 8 [8:8] read-write PIN9 Interrupt type clear for pin 9 [9:9] read-write PIN10 Interrupt type clear for pin 10 [10:10] read-write PIN11 Interrupt type clear for pin 11 [11:11] read-write PIN12 Interrupt type clear for pin 12 [12:12] read-write PIN13 Interrupt type clear for pin 13 [13:13] read-write PIN14 Interrupt type clear for pin 14 [14:14] read-write PIN15 Interrupt type clear for pin 15 [15:15] read-write INTPOLSET Interrupt polarity set register 0x0070 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt polarity set for pin 0 [0:0] read-write PIN1 Interrupt polarity set for pin 1 [1:1] read-write PIN2 Interrupt polarity set for pin 2 [2:2] read-write PIN3 Interrupt polarity set for pin 3 [3:3] read-write PIN4 Interrupt polarity set for pin 4 [4:4] read-write PIN5 Interrupt polarity set for pin 5 [5:5] read-write PIN6 Interrupt polarity set for pin 6 [6:6] read-write PIN7 Interrupt polarity set for pin 7 [7:7] read-write PIN8 Interrupt polarity set for pin 8 [8:8] read-write PIN9 Interrupt polarity set for pin 9 [9:9] read-write PIN10 Interrupt polarity set for pin 10 [10:10] read-write PIN11 Interrupt polarity set for pin 11 [11:11] read-write PIN12 Interrupt polarity set for pin 12 [12:12] read-write PIN13 Interrupt polarity set for pin 13 [13:13] read-write PIN14 Interrupt polarity set for pin 14 [14:14] read-write PIN15 Interrupt polarity set for pin 15 [15:15] read-write INTPOLCLR Interrupt polarity clear register 0x0074 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt polarity clear for pin 0 [0:0] read-write PIN1 Interrupt polarity clear for pin 1 [1:1] read-write PIN2 Interrupt polarity clear for pin 2 [2:2] read-write PIN3 Interrupt polarity clear for pin 3 [3:3] read-write PIN4 Interrupt polarity clear for pin 4 [4:4] read-write PIN5 Interrupt polarity clear for pin 5 [5:5] read-write PIN6 Interrupt polarity clear for pin 6 [6:6] read-write PIN7 Interrupt polarity clear for pin 7 [7:7] read-write PIN8 Interrupt polarity clear for pin 8 [8:8] read-write PIN9 Interrupt polarity clear for pin 9 [9:9] read-write PIN10 Interrupt polarity clear for pin 10 [10:10] read-write PIN11 Interrupt polarity clear for pin 11 [11:11] read-write PIN12 Interrupt polarity clear for pin 12 [12:12] read-write PIN13 Interrupt polarity clear for pin 13 [13:13] read-write PIN14 Interrupt polarity clear for pin 14 [14:14] read-write PIN15 Interrupt polarity clear for pin 15 [15:15] read-write INTEDGESET Interrupt every edge set register 0x0078 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt every edge set for pin 0 [0:0] read-write PIN1 Interrupt every edge set for pin 1 [1:1] read-write PIN2 Interrupt every edge set for pin 2 [2:2] read-write PIN3 Interrupt every edge set for pin 3 [3:3] read-write PIN4 Interrupt every edge set for pin 4 [4:4] read-write PIN5 Interrupt every edge set for pin 5 [5:5] read-write PIN6 Interrupt every edge set for pin 6 [6:6] read-write PIN7 Interrupt every edge set for pin 7 [7:7] read-write PIN8 Interrupt every edge set for pin 8 [8:8] read-write PIN9 Interrupt every edge set for pin 9 [9:9] read-write PIN10 Interrupt every edge set for pin 10 [10:10] read-write PIN11 Interrupt every edge set for pin 11 [11:11] read-write PIN12 Interrupt every edge set for pin 12 [12:12] read-write PIN13 Interrupt every edge set for pin 13 [13:13] read-write PIN14 Interrupt every edge set for pin 14 [14:14] read-write PIN15 Interrupt every edge set for pin 15 [15:15] read-write INTEDGECLR Interrupt every edge clear register 0x007C 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt every edge clear for pin 0 [0:0] read-write PIN1 Interrupt every edge clear for pin 1 [1:1] read-write PIN2 Interrupt every edge clear for pin 2 [2:2] read-write PIN3 Interrupt every edge clear for pin 3 [3:3] read-write PIN4 Interrupt every edge clear for pin 4 [4:4] read-write PIN5 Interrupt every edge clear for pin 5 [5:5] read-write PIN6 Interrupt every edge clear for pin 6 [6:6] read-write PIN7 Interrupt every edge clear for pin 7 [7:7] read-write PIN8 Interrupt every edge clear for pin 8 [8:8] read-write PIN9 Interrupt every edge clear for pin 9 [9:9] read-write PIN10 Interrupt every edge clear for pin 10 [10:10] read-write PIN11 Interrupt every edge clear for pin 11 [11:11] read-write PIN12 Interrupt every edge clear for pin 12 [12:12] read-write PIN13 Interrupt every edge clear for pin 13 [13:13] read-write PIN14 Interrupt every edge clear for pin 14 [14:14] read-write PIN15 Interrupt every edge clear for pin 15 [15:15] read-write INTSTATUS Interrupt status 0x0080 32 read-write 0x00000000 0xFFFFFFFF PIN0 Interrupt status of pin 0 [0:0] read-write PIN1 Interrupt status of pin 1 [1:1] read-write PIN2 Interrupt status of pin 2 [2:2] read-write PIN3 Interrupt status of pin 3 [3:3] read-write PIN4 Interrupt status of pin 4 [4:4] read-write PIN5 Interrupt status of pin 5 [5:5] read-write PIN6 Interrupt status of pin 6 [6:6] read-write PIN7 Interrupt status of pin 7 [7:7] read-write PIN8 Interrupt status of pin 8 [8:8] read-write PIN9 Interrupt status of pin 9 [9:9] read-write PIN10 Interrupt status of pin 10 [10:10] read-write PIN11 Interrupt status of pin 11 [11:11] read-write PIN12 Interrupt status of pin 12 [12:12] read-write PIN13 Interrupt status of pin 13 [13:13] read-write PIN14 Interrupt status of pin 14 [14:14] read-write PIN15 Interrupt status of pin 15 [15:15] read-write DMAREQSET DMA request enable register 0x0084 32 read-write 0x00000000 0xFFFFFFFF PIN0 DMA request enable for pin 0 [0:0] read-write PIN1 DMA request enable for pin 1 [1:1] read-write PIN2 DMA request enable for pin 2 [2:2] read-write PIN3 DMA request enable for pin 3 [3:3] read-write PIN4 DMA request enable for pin 4 [4:4] read-write PIN5 DMA request enable for pin 5 [5:5] read-write PIN6 DMA request enable for pin 6 [6:6] read-write PIN7 DMA request enable for pin 7 [7:7] read-write PIN8 DMA request enable for pin 8 [8:8] read-write PIN9 DMA request enable for pin 9 [9:9] read-write PIN10 DMA request enable for pin 10 [10:10] read-write PIN11 DMA request enable for pin 11 [11:11] read-write PIN12 DMA request enable for pin 12 [12:12] read-write PIN13 DMA request enable for pin 13 [13:13] read-write PIN14 DMA request enable for pin 14 [14:14] read-write PIN15 DMA request enable for pin 15 [15:15] read-write DMAREQCLR DMA request disable register 0x0088 32 read-write 0x00000000 0xFFFFFFFF PIN0 DMA request disable for pin 0 [0:0] read-write PIN1 DMA request disable for pin 1 [1:1] read-write PIN2 DMA request disable for pin 2 [2:2] read-write PIN3 DMA request disable for pin 3 [3:3] read-write PIN4 DMA request disable for pin 4 [4:4] read-write PIN5 DMA request disable for pin 5 [5:5] read-write PIN6 DMA request disable for pin 6 [6:6] read-write PIN7 DMA request disable for pin 7 [7:7] read-write PIN8 DMA request disable for pin 8 [8:8] read-write PIN9 DMA request disable for pin 9 [9:9] read-write PIN10 DMA request disable for pin 10 [10:10] read-write PIN11 DMA request disable for pin 11 [11:11] read-write PIN12 DMA request disable for pin 12 [12:12] read-write PIN13 DMA request disable for pin 13 [13:13] read-write PIN14 DMA request disable for pin 14 [14:14] read-write PIN15 DMA request disable for pin 15 [15:15] read-write ADCSOCSET ADC Start Of Conversion enable register 0x008C 32 read-write 0x00000000 0xFFFFFFFF PIN0 ADC SOC enable for pin 0 [0:0] read-write PIN1 ADC SOC enable for pin 1 [1:1] read-write PIN2 ADC SOC enable for pin 2 [2:2] read-write PIN3 ADC SOC enable for pin 3 [3:3] read-write PIN4 ADC SOC enable for pin 4 [4:4] read-write PIN5 ADC SOC enable for pin 5 [5:5] read-write PIN6 ADC SOC enable for pin 6 [6:6] read-write PIN7 ADC SOC enable for pin 7 [7:7] read-write PIN8 ADC SOC enable for pin 8 [8:8] read-write PIN9 ADC SOC enable for pin 9 [9:9] read-write PIN10 ADC SOC enable for pin 10 [10:10] read-write PIN11 ADC SOC enable for pin 11 [11:11] read-write PIN12 ADC SOC enable for pin 12 [12:12] read-write PIN13 ADC SOC enable for pin 13 [13:13] read-write PIN14 ADC SOC enable for pin 14 [14:14] read-write PIN15 ADC SOC enable for pin 15 [15:15] read-write ADCSOCCLR ADC Start Of Conversion disable register 0x0090 32 read-write 0x00000000 0xFFFFFFFF PIN0 ADC SOC disable for pin 0 [0:0] read-write PIN1 ADC SOC disable for pin 1 [1:1] read-write PIN2 ADC SOC disable for pin 2 [2:2] read-write PIN3 ADC SOC disable for pin 3 [3:3] read-write PIN4 ADC SOC disable for pin 4 [4:4] read-write PIN5 ADC SOC disable for pin 5 [5:5] read-write PIN6 ADC SOC disable for pin 6 [6:6] read-write PIN7 ADC SOC disable for pin 7 [7:7] read-write PIN8 ADC SOC disable for pin 8 [8:8] read-write PIN9 ADC SOC disable for pin 9 [9:9] read-write PIN10 ADC SOC disable for pin 10 [10:10] read-write PIN11 ADC SOC disable for pin 11 [11:11] read-write PIN12 ADC SOC disable for pin 12 [12:12] read-write PIN13 ADC SOC disable for pin 13 [13:13] read-write PIN14 ADC SOC disable for pin 14 [14:14] read-write PIN15 ADC SOC disable for pin 15 [15:15] read-write RXEVSET Core RXEV request enable register 0x0094 32 read-write 0x00000000 0xFFFFFFFF PIN0 RXEV enable for pin 0 [0:0] read-write PIN1 RXEV enable for pin 1 [1:1] read-write PIN2 RXEV enable for pin 2 [2:2] read-write PIN3 RXEV enable for pin 3 [3:3] read-write PIN4 RXEV enable for pin 4 [4:4] read-write PIN5 RXEV enable for pin 5 [5:5] read-write PIN6 RXEV enable for pin 6 [6:6] read-write PIN7 RXEV enable for pin 7 [7:7] read-write PIN8 RXEV enable for pin 8 [8:8] read-write PIN9 RXEV enable for pin 9 [9:9] read-write PIN10 RXEV enable for pin 10 [10:10] read-write PIN11 RXEV enable for pin 11 [11:11] read-write PIN12 RXEV enable for pin 12 [12:12] read-write PIN13 RXEV enable for pin 13 [13:13] read-write PIN14 RXEV enable for pin 14 [14:14] read-write PIN15 RXEV enable for pin 15 [15:15] read-write RXEVCLR Core RXEV request disable register 0x0098 32 read-write 0x00000000 0xFFFFFFFF PIN0 RXEV disable for pin 0 [0:0] read-write PIN1 RXEV disable for pin 1 [1:1] read-write PIN2 RXEV disable for pin 2 [2:2] read-write PIN3 RXEV disable for pin 3 [3:3] read-write PIN4 RXEV disable for pin 4 [4:4] read-write PIN5 RXEV disable for pin 5 [5:5] read-write PIN6 RXEV disable for pin 6 [6:6] read-write PIN7 RXEV disable for pin 7 [7:7] read-write PIN8 RXEV disable for pin 8 [8:8] read-write PIN9 RXEV disable for pin 9 [9:9] read-write PIN10 RXEV disable for pin 10 [10:10] read-write PIN11 RXEV disable for pin 11 [11:11] read-write PIN12 RXEV disable for pin 12 [12:12] read-write PIN13 RXEV disable for pin 13 [13:13] read-write PIN14 RXEV disable for pin 14 [14:14] read-write PIN15 RXEV disable for pin 15 [15:15] read-write LOCKKEY Key register to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) 0x009C 32 write-only 0x00000000 0xFFFFFFFF VAL Key to unlock LOCKSET/LOCKCLR registers for write (KEY=0xADEADBEE) [31:0] write-only write LOCK 0xEEEEEEEE, key to lock registers 4008636142 UNLOCK 0xADEADBEE, key to unlock registers 2917850094 LOCKSTAT LOCKKEY LOCKSET/LOCKCLR write enable status register 0x009C 32 read-only 0x00000000 0xFFFFFFFF WREN LOCKSET/LOCKCLR write enable status [0:0] read-only LOCKSET Lock pins configuration enable register 0x00A0 32 read-write 0x00000000 0xFFFFFFFF PIN0 Lock configuration enable for pin 0 [0:0] read-write PIN1 Lock configuration enable for pin 1 [1:1] read-write PIN2 Lock configuration enable for pin 2 [2:2] read-write PIN3 Lock configuration enable for pin 3 [3:3] read-write PIN4 Lock configuration enable for pin 4 [4:4] read-write PIN5 Lock configuration enable for pin 5 [5:5] read-write PIN6 Lock configuration enable for pin 6 [6:6] read-write PIN7 Lock configuration enable for pin 7 [7:7] read-write PIN8 Lock configuration enable for pin 8 [8:8] read-write PIN9 Lock configuration enable for pin 9 [9:9] read-write PIN10 Lock configuration enable for pin 10 [10:10] read-write PIN11 Lock configuration enable for pin 11 [11:11] read-write PIN12 Lock configuration enable for pin 12 [12:12] read-write PIN13 Lock configuration enable for pin 13 [13:13] read-write PIN14 Lock configuration enable for pin 14 [14:14] read-write PIN15 Lock configuration enable for pin 15 [15:15] read-write LOCKCLR Lock pins configuration disable register 0x00A4 32 read-write 0x00000000 0xFFFFFFFF PIN0 Lock configuration disable for pin 0 [0:0] read-write PIN1 Lock configuration disable for pin 1 [1:1] read-write PIN2 Lock configuration disable for pin 2 [2:2] read-write PIN3 Lock configuration disable for pin 3 [3:3] read-write PIN4 Lock configuration disable for pin 4 [4:4] read-write PIN5 Lock configuration disable for pin 5 [5:5] read-write PIN6 Lock configuration disable for pin 6 [6:6] read-write PIN7 Lock configuration disable for pin 7 [7:7] read-write PIN8 Lock configuration disable for pin 8 [8:8] read-write PIN9 Lock configuration disable for pin 9 [9:9] read-write PIN10 Lock configuration disable for pin 10 [10:10] read-write PIN11 Lock configuration disable for pin 11 [11:11] read-write PIN12 Lock configuration disable for pin 12 [12:12] read-write PIN13 Lock configuration disable for pin 13 [13:13] read-write PIN14 Lock configuration disable for pin 14 [14:14] read-write PIN15 Lock configuration disable for pin 15 [15:15] read-write 256 4 0-255 MASKLB[%s] MASKLB 0x400 MASKLB Mask register low byte of port 0x00 32 read-write 0x00000000 0xFFFFFFFF VAL Mask low byte [7:0] read-write 256 4 0-255 MASKHB[%s] MASKHB 0x800 MASKHB Mask register High byte of port 0x00 32 read-write 0x00000000 0xFFFFFFFF VAL Mask high byte [15:8] read-write GPIOB 0x40011000 GPIOB GPIO B interrupt 4 UART0 1.0 UART control registers 2UART 0x40045000 32 read-write 0 0x04C registers UART0_TD UART0 Transmit Done interrupt 25 UART0_RX UART0 Recieve interrupt 26 UART0_TX UART0 Transmit interrupt 27 UART0_E_RT UART0 Error and Receive Timeout interrupt 28 DR Data Register 0x0000 32 read-write 0x00000000 0xFFFFFFFF DATA [7:0] read-write FE Framing error [8:8] read-only PE Parity error [9:9] read-only BE Break error [10:10] read-only OE Overrun error [11:11] read-only RSR Receive Status Register/Error Clear Register 0x0004 32 read-write 0x00000000 0xFFFFFFFF FE Framing error [0:0] read-write PE Parity error [1:1] read-write BE Break error [2:2] read-write OE Overrun error [3:3] read-write FR Flag Register 0x0018 32 read-only 0x00000000 0xFFFFFFFF BUSY UART busy [3:3] read-only RXFE Receive FIFO empty [4:4] read-only TXFF Transmit FIFO full [5:5] read-only RXFF Receive FIFO full [6:6] read-only TXFE Transmit FIFO empty [7:7] read-only IBRD Integer Baud Rate Register 0x0024 32 read-write 0x00000000 0xFFFFFFFF DIVINT [15:0] read-write FBRD Fractional Baud Rate Register 0x0028 32 read-write 0x00000000 0xFFFFFFFF DIVFRAC [5:0] read-write LCRH Line Control Register 0x002C 32 read-write 0x00000000 0xFFFFFFFF BRK Send break [0:0] read-write PEN Parity enable [1:1] read-write EPS Even parity select [2:2] read-write STP2 Two stop bits select [3:3] read-write FEN Enable FIFOs [4:4] read-write WLEN [6:5] read-write read-write 5bit 5 bit in informational word 0 6bit 6 bit in informational word 1 7bit 7 bit in informational word 2 8bit 8 bit in informational word 3 SPS Stick parity select [7:7] read-write CR Control Register 0x0030 32 read-write 0x00000000 0xFFFFFFFF UARTEN UART enable [0:0] read-write TXE Transmit enable [8:8] read-write RXE Receive enable [9:9] read-write IFLS Interrupt FIFO Level Select Register 0x0034 32 read-write 0x00000000 0xFFFFFFFF TXIFLSEL [2:0] read-write read-write Lvl18 interrupt on 1/8 0 Lvl14 interrupt on 1/4 1 Lvl12 interrupt on 1/2 2 Lvl34 interrupt on 3/4 3 Lvl78 interrupt on 7/8 4 RXIFLSEL [5:3] read-write read-write Lvl18 interrupt on 1/8 0 Lvl14 interrupt on 1/4 1 Lvl12 interrupt on 1/2 2 Lvl34 interrupt on 3/4 3 Lvl78 interrupt on 7/8 4 IMSC Interrupt Mask Set/Clear Register 0x0038 32 read-write 0x00000000 0xFFFFFFFF RXIM Receive interrupt mask [4:4] read-write TXIM Transmit interrupt mask [5:5] read-write RTIM Receive timeout interrupt mask [6:6] read-write FEIM Framing error interrupt mask [7:7] read-write PEIM Parity error interrupt mask [8:8] read-write BEIM Break error interrupt mask [9:9] read-write OEIM Overrun error interrupt mask [10:10] read-write TDIM Transmit done interrupt mask [11:11] read-write RIS Raw Interrupt Status Register 0x003C 32 read-write 0x00000000 0xFFFFFFFF RXRIS Receive interrupt status [4:4] read-only TXRIS Transmit interrupt status [5:5] read-only RTRIS Receive timeout interrupt status [6:6] read-only FERIS Framing error interrupt status [7:7] read-only PERIS Parity error interrupt status [8:8] read-only BERIS Break error interrupt status [9:9] read-only OERIS Overrun error interrupt status [10:10] read-only TDRIS Transmit done raw interrupt status [11:11] read-write MIS Masked Interrupt Status Register 0x0040 32 read-write 0x00000000 0xFFFFFFFF RXMIS Receive masked interrupt status [4:4] read-only TXMIS Transmit masked interrupt status [5:5] read-only RTMIS Receive timeout masked interrupt status [6:6] read-only FEMIS Framing error masked interrupt status [7:7] read-only PEMIS Parity error masked interrupt status [8:8] read-only BEMIS Break error masked interrupt status [9:9] read-only OEMIS Overrun error masked interrupt status [10:10] read-only TDMIS Transmit done masked interrupt status [11:11] read-write ICR Interrupt Clear Register 0x0044 32 read-write 0x00000000 0xFFFFFFFF RXIC Receive interrupt clear [4:4] write-only TXIC Transmit interrupt clear [5:5] write-only RTIC Receive timeout interrupt clear [6:6] write-only FEIC Framing error interrupt clear [7:7] write-only PEIC Parity error interrupt clear [8:8] write-only BEIC Break error interrupt clear [9:9] write-only OEIC Overrun error interrupt clear [10:10] write-only TDIC Transmit done interrupt clear [11:11] read-write DMACR DMA Control Register 0x0048 32 read-write 0x00000000 0xFFFFFFFF RXDMAE Receive DMA enable [0:0] read-write TXDMAE Transmit DMA enable [1:1] read-write DMAONERR DMA on error [2:2] read-write UART1 0x40046000 UART1_TD UART1 Transmit Done interrupt 29 UART1_RX UART1 Recieve interrupt 30 UART1_TX UART1 Transmit interrupt 31 UART1_E_RT UART1 Error and Receive Timeout interrupt 32 DMA 1.0 DMA control registers DMA 0x40044000 32 read-write 0 0x050 registers DMA_CH0 DMA channel 0 interrupt 5 DMA_CH1 DMA channel 1 interrupt 6 DMA_CH2 DMA channel 2 interrupt 7 DMA_CH3 DMA channel 3 interrupt 8 DMA_CH4 DMA channel 4 interrupt 9 DMA_CH5 DMA channel 5 interrupt 10 DMA_CH6 DMA channel 6 interrupt 11 DMA_CH7 DMA channel 7 interrupt 12 DMA_CH8 DMA channel 8 interrupt 13 DMA_CH9 DMA channel 9 interrupt 14 DMA_CH10 DMA channel 10 interrupt 15 DMA_CH11 DMA channel 11 interrupt 16 DMA_CH12 DMA channel 12 interrupt 17 DMA_CH13 DMA channel 13 interrupt 18 DMA_CH14 DMA channel 14 interrupt 19 DMA_CH15 DMA channel 15 interrupt 20 STATUS Status DMA register 0x0000 32 read-only 0x00000000 0xFFFFFFFF MASTEREN Indicate enable DMA [0:0] read-only STATE State of DMA [7:4] read-only read Free At rest 0 ReadConfigData Reading the config data structure 1 ReadSrcDataEndPtr Reading sourse data end pointer 2 ReadDstDataEndPtr Reading destination data end pointer 3 ReadSrcData Reading source data 4 WrireDstData Writing data to the destination 5 WaitReq Waiting for a request 6 WriteConfigData Write config structure of the channel 7 Pause Suspended 8 Done Executed 9 PeriphScatGath mode "peripheral scather-gather" 10 CHNLS Number channel DMA (write: N-1) [20:16] read-only CFG DMA configuration register 0x0004 32 write-only 0x00000000 0xFFFFFFFF MASTEREN Enable DMA [0:0] write-only CHPROT Sets the AHB-Lite protection [7:5] write-only BASEPTR Channel control data base pointer 0x0008 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write ALTBASEPTR Channel alternate control data base pointer 0x000C 32 read-only 0x00000000 0xFFFFFFFF VAL [31:0] read-only WAITONREQ Channel wait on request status 0x0010 32 read-only 0x00000000 0xFFFFFFFF CH0 Returns the status of the DMA request signals [0:0] read-only CH1 Returns the status of the DMA request signals [1:1] read-only CH2 Returns the status of the DMA request signals [2:2] read-only CH3 Returns the status of the DMA request signals [3:3] read-only CH4 Returns the status of the DMA request signals [4:4] read-only CH5 Returns the status of the DMA request signals [5:5] read-only CH6 Returns the status of the DMA request signals [6:6] read-only CH7 Returns the status of the DMA request signals [7:7] read-only CH8 Returns the status of the DMA request signals [8:8] read-only CH9 Returns the status of the DMA request signals [9:9] read-only CH10 Returns the status of the DMA request signals [10:10] read-only CH11 Returns the status of the DMA request signals [11:11] read-only CH12 Returns the status of the DMA request signals [12:12] read-only CH13 Returns the status of the DMA request signals [13:13] read-only CH14 Returns the status of the DMA request signals [14:14] read-only CH15 Returns the status of the DMA request signals [15:15] read-only SWREQ Channel software request 0x0014 32 write-only 0x00000000 0xFFFFFFFF CH0 Set software request on channel [0:0] write-only CH1 Set software request on channel [1:1] write-only CH2 Set software request on channel [2:2] write-only CH3 Set software request on channel [3:3] write-only CH4 Set software request on channel [4:4] write-only CH5 Set software request on channel [5:5] write-only CH6 Set software request on channel [6:6] write-only CH7 Set software request on channel [7:7] write-only CH8 Set software request on channel [8:8] write-only CH9 Set software request on channel [9:9] write-only CH10 Set software request on channel [10:10] write-only CH11 Set software request on channel [11:11] write-only CH12 Set software request on channel [12:12] write-only CH13 Set software request on channel [13:13] write-only CH14 Set software request on channel [14:14] write-only CH15 Set software request on channel [15:15] write-only USEBURSTSET Channel useburst set 0x0018 32 read-write 0x00000000 0xFFFFFFFF CH0 Enable single requests [0:0] read-write CH1 Enable single requests [1:1] read-write CH2 Enable single requests [2:2] read-write CH3 Enable single requests [3:3] read-write CH4 Enable single requests [4:4] read-write CH5 Enable single requests [5:5] read-write CH6 Enable single requests [6:6] read-write CH7 Enable single requests [7:7] read-write CH8 Enable single requests [8:8] read-write CH9 Enable single requests [9:9] read-write CH10 Enable single requests [10:10] read-write CH11 Enable single requests [11:11] read-write CH12 Enable single requests [12:12] read-write CH13 Enable single requests [13:13] read-write CH14 Enable single requests [14:14] read-write CH15 Enable single requests [15:15] read-write USEBURSTCLR Channel useburst clear 0x001C 32 write-only 0x00000000 0xFFFFFFFF CH0 Disable single requests [0:0] write-only CH1 Disable single requests [1:1] write-only CH2 Disable single requests [2:2] write-only CH3 Disable single requests [3:3] write-only CH4 Disable single requests [4:4] write-only CH5 Disable single requests [5:5] write-only CH6 Disable single requests [6:6] write-only CH7 Disable single requests [7:7] write-only CH8 Disable single requests [8:8] write-only CH9 Disable single requests [9:9] write-only CH10 Disable single requests [10:10] write-only CH11 Disable single requests [11:11] write-only CH12 Disable single requests [12:12] write-only CH13 Disable single requests [13:13] write-only CH14 Disable single requests [14:14] write-only CH15 Disable single requests [15:15] write-only REQMASKSET Channel request mask set 0x0020 32 read-write 0x00000000 0xFFFFFFFF CH0 External requests are enabled for channel [0:0] read-write CH1 External requests are enabled for channel [1:1] read-write CH2 External requests are enabled for channel [2:2] read-write CH3 External requests are enabled for channel [3:3] read-write CH4 External requests are enabled for channel [4:4] read-write CH5 External requests are enabled for channel [5:5] read-write CH6 External requests are enabled for channel [6:6] read-write CH7 External requests are enabled for channel [7:7] read-write CH8 External requests are enabled for channel [8:8] read-write CH9 External requests are enabled for channel [9:9] read-write CH10 External requests are enabled for channel [10:10] read-write CH11 External requests are enabled for channel [11:11] read-write CH12 External requests are enabled for channel [12:12] read-write CH13 External requests are enabled for channel [13:13] read-write CH14 External requests are enabled for channel [14:14] read-write CH15 External requests are enabled for channel [15:15] read-write REQMASKCLR Channel request mask clear 0x0024 32 write-only 0x00000000 0xFFFFFFFF CH0 External requests are disabled for channel [0:0] write-only CH1 External requests are disabled for channel [1:1] write-only CH2 External requests are disabled for channel [2:2] write-only CH3 External requests are disabled for channel [3:3] write-only CH4 External requests are disabled for channel [4:4] write-only CH5 External requests are disabled for channel [5:5] write-only CH6 External requests are disabled for channel [6:6] write-only CH7 External requests are disabled for channel [7:7] write-only CH8 External requests are disabled for channel [8:8] write-only CH9 External requests are disabled for channel [9:9] write-only CH10 External requests are disabled for channel [10:10] write-only CH11 External requests are disabled for channel [11:11] write-only CH12 External requests are disabled for channel [12:12] write-only CH13 External requests are disabled for channel [13:13] write-only CH14 External requests are disabled for channel [14:14] write-only CH15 External requests are disabled for channel [15:15] write-only ENSET Channel enable set 0x0028 32 read-write 0x00000000 0xFFFFFFFF CH0 Enable channel [0:0] read-write CH1 Enable channel [1:1] read-write CH2 Enable channel [2:2] read-write CH3 Enable channel [3:3] read-write CH4 Enable channel [4:4] read-write CH5 Enable channel [5:5] read-write CH6 Enable channel [6:6] read-write CH7 Enable channel [7:7] read-write CH8 Enable channel [8:8] read-write CH9 Enable channel [9:9] read-write CH10 Enable channel [10:10] read-write CH11 Enable channel [11:11] read-write CH12 Enable channel [12:12] read-write CH13 Enable channel [13:13] read-write CH14 Enable channel [14:14] read-write CH15 Enable channel [15:15] read-write ENCLR Channel enable clear 0x002C 32 write-only 0x00000000 0xFFFFFFFF CH0 Disable channel [0:0] write-only CH1 Disable channel [1:1] write-only CH2 Disable channel [2:2] write-only CH3 Disable channel [3:3] write-only CH4 Disable channel [4:4] write-only CH5 Disable channel [5:5] write-only CH6 Disable channel [6:6] write-only CH7 Disable channel [7:7] write-only CH8 Disable channel [8:8] write-only CH9 Disable channel [9:9] write-only CH10 Disable channel [10:10] write-only CH11 Disable channel [11:11] write-only CH12 Disable channel [12:12] write-only CH13 Disable channel [13:13] write-only CH14 Disable channel [14:14] write-only CH15 Disable channel [15:15] write-only PRIALTSET Channel primary-alternate set 0x0030 32 read-write 0x00000000 0xFFFFFFFF CH0 Set primary / alternate channel control data structure [0:0] read-write CH1 Set primary / alternate channel control data structure [1:1] read-write CH2 Set primary / alternate channel control data structure [2:2] read-write CH3 Set primary / alternate channel control data structure [3:3] read-write CH4 Set primary / alternate channel control data structure [4:4] read-write CH5 Set primary / alternate channel control data structure [5:5] read-write CH6 Set primary / alternate channel control data structure [6:6] read-write CH7 Set primary / alternate channel control data structure [7:7] read-write CH8 Set primary / alternate channel control data structure [8:8] read-write CH9 Set primary / alternate channel control data structure [9:9] read-write CH10 Set primary / alternate channel control data structure [10:10] read-write CH11 Set primary / alternate channel control data structure [11:11] read-write CH12 Set primary / alternate channel control data structure [12:12] read-write CH13 Set primary / alternate channel control data structure [13:13] read-write CH14 Set primary / alternate channel control data structure [14:14] read-write CH15 Set primary / alternate channel control data structure [15:15] read-write PRIALTCLR Channel primary-alternate clear 0x0034 32 write-only 0x00000000 0xFFFFFFFF CH0 Clear primary / alternate channel control data structure [0:0] write-only CH1 Clear primary / alternate channel control data structure [1:1] write-only CH2 Clear primary / alternate channel control data structure [2:2] write-only CH3 Clear primary / alternate channel control data structure [3:3] write-only CH4 Clear primary / alternate channel control data structure [4:4] write-only CH5 Clear primary / alternate channel control data structure [5:5] write-only CH6 Clear primary / alternate channel control data structure [6:6] write-only CH7 Clear primary / alternate channel control data structure [7:7] write-only CH8 Clear primary / alternate channel control data structure [8:8] write-only CH9 Clear primary / alternate channel control data structure [9:9] write-only CH10 Clear primary / alternate channel control data structure [10:10] write-only CH11 Clear primary / alternate channel control data structure [11:11] write-only CH12 Clear primary / alternate channel control data structure [12:12] write-only CH13 Clear primary / alternate channel control data structure [13:13] write-only CH14 Clear primary / alternate channel control data structure [14:14] write-only CH15 Clear primary / alternate channel control data structure [15:15] write-only PRIORITYSET Channel priority set 0x0038 32 read-write 0x00000000 0xFFFFFFFF CH0 Set the priority of channel [0:0] read-write CH1 Set the priority of channel [1:1] read-write CH2 Set the priority of channel [2:2] read-write CH3 Set the priority of channel [3:3] read-write CH4 Set the priority of channel [4:4] read-write CH5 Set the priority of channel [5:5] read-write CH6 Set the priority of channel [6:6] read-write CH7 Set the priority of channel [7:7] read-write CH8 Set the priority of channel [8:8] read-write CH9 Set the priority of channel [9:9] read-write CH10 Set the priority of channel [10:10] read-write CH11 Set the priority of channel [11:11] read-write CH12 Set the priority of channel [12:12] read-write CH13 Set the priority of channel [13:13] read-write CH14 Set the priority of channel [14:14] read-write CH15 Set the priority of channel [15:15] read-write PRIORITYCLR Channel priority clear 0x003C 32 write-only 0x00000000 0xFFFFFFFF CH0 Clear the priority [0:0] write-only CH1 Clear the priority [1:1] write-only CH2 Clear the priority [2:2] write-only CH3 Clear the priority [3:3] write-only CH4 Clear the priority [4:4] write-only CH5 Clear the priority [5:5] write-only CH6 Clear the priority [6:6] write-only CH7 Clear the priority [7:7] write-only CH8 Clear the priority [8:8] write-only CH9 Clear the priority [9:9] write-only CH10 Clear the priority [10:10] write-only CH11 Clear the priority [11:11] write-only CH12 Clear the priority [12:12] write-only CH13 Clear the priority [13:13] write-only CH14 Clear the priority [14:14] write-only CH15 Clear the priority [15:15] write-only ERRCLR Bus error register 0x004C 32 read-write 0x00000000 0xFFFFFFFF VAL Indicate Error on bus AHB-Lite [0:0] read-write MFLASH 1.0 Mainflash control registers MFLASH 0x40030000 32 read-write 0 0x07C registers MFLASH MFLASH interrupt 2 ADDR Address Register 0x0000 32 read-write 0x00000000 0xFFFFFFFF VAL Address value for flash operations [31:0] read-write 2 4 0-1 DATA[%s] DATA 0x004 DATA Data Register 0x00 32 read-write 0x00000000 0xFFFFFFFF VAL Data register value for flash operations [31:0] read-write CMD Command Register 0x0024 32 read-write 0x00000000 0xFFFFFFFF RD Read enable command [0:0] read-write WR Write enable command [1:1] read-write ERSEC Erase sector enable command [2:2] read-write ERALL Erase all enable command [3:3] read-write NVRON NVR access bit [8:8] read-write KEY Magic Key for flash access "C0DE" [31:16] read-write read-write Access magic Key for flash access 49374 STAT Status Register 0x0028 32 read-write 0x00000000 0xFFFFFFFF BUSY Busy status bit when command is processing [0:0] read-only IRQF IRQ Flag set when command done. Set by hardware only if IRQEN bit is set. [1:1] read-write CTRL Control Register 0x002C 32 read-write 0x00000000 0xFFFFFFFF PEN Prefetch enable bit [0:0] read-write ICEN I-Cache enable bit [1:1] read-write DCEN D-Cache enable bit [2:2] read-write IRQEN Interrupt enable bit [4:4] read-write IFLUSH Flush I-Cache request bit [8:8] write-only DFLUSH Flush D-Cache request bit [9:9] write-only LAT Flash latency [19:16] read-write ICSTAT ICACHE Status Register 0x0034 32 read-only 0x00000000 0xFFFFFFFF BUSY Busy flag for I-Cache flush/test system [0:0] read-only DCSTAT DCACHE Status Register 0x0038 32 read-only 0x00000000 0xFFFFFFFF BUSY Busy flag for D-Cache flush/test system [0:0] read-only BDIS Boot Mode Disable register 0x0078 32 read-write 0x00000000 0xFFFFFFFF BMDIS Disable boot mode after system reset command [0:0] read-write QEP 1.0 QEP controller registers QEP 0x4004F000 32 read-write 0 0x074 registers QEP QEP interrupt 49 QPOSCNT Position Counter register 0x0000 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QPOSINIT Position Counter Initialization register 0x0004 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QPOSMAX Maximum Position Count register 0x0008 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QPOSCMP Position-compare register 0x000C 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QPOSILAT Index Position Latch register 0x0010 32 read-only 0x00000000 0xFFFFFFFF VAL [31:0] read-only QPOSSLAT Strobe Position Latch register 0x0014 32 read-only 0x00000000 0xFFFFFFFF VAL [31:0] read-only QPOSLAT Position Counter Latch register 0x0018 32 read-only 0x00000000 0xFFFFFFFF VAL [31:0] read-only QUTMR Unit Timer register 0x001C 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QUPRD Unit Period register 0x0020 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QWDTMR Watchdog Timer register 0x0024 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QWDPRD Watchdog Period register 0x0028 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QDECCTL Decoder Control register 0x002C 32 read-write 0x00000000 0xFFFFFFFF QSP QEPS input polarity [5:5] read-write QIP QEPI input polarity [6:6] read-write QBP QEPB input polarity [7:7] read-write QAP QEPA input polarity [8:8] read-write IGATE Index pulse gating option [9:9] read-write SWAP Swap quadrature clock inputs [10:10] read-write XCR External clock rate [11:11] read-write SPSEL Sync output pin selection [12:12] read-write SOEN Sync output-enable [13:13] read-write QSRC [15:14] read-write read-write Quad quadrature mode 0 CountDir count/direction mode 1 Up count up 2 Down count down 3 QEPCTL Control register 0x0030 32 read-write 0x00000000 0xFFFFFFFF WDE QEP watchdog enable [0:0] read-write UTE QEP unit timer enable [1:1] read-write QCLM QEP capture latch mode [2:2] read-write QPEN Quadrature position counter enable/software reset [3:3] read-write IEL [5:4] read-write read-write NoLatch no position counter latch 0 IndPos latch on index signal posedge 1 IndNeg latch on index signal negedge 2 IndMark latch on index marker 3 SEL Strobe event latch of position counter [6:6] read-write SWI Software initialization of position counter [7:7] read-write IEI [9:8] read-write read-write NoInit no initialization 0 QEPIPos init on posedge QEPI 2 QEPINeg init on negedge QEPI 3 SEI [11:10] read-write read-write NoInit no initialization 0 QEPSPos init on posedge QEPI 2 QEPSDir init depends on direction - on posedge if direction is up, on negedge if direction is down 3 PCRM [13:12] read-write read-write Ind reset on index 0 PosMax reset on max position count 1 FirstInd reset on the first index 2 Time reset on time counter 3 FREESOFT [15:14] read-write read-write Stop counters are blocked 0 StopAtOvf stop after overflow 1 Free no count stop in debug mode 2 QCAPCTL Capture Control register 0x0034 32 read-write 0x00000000 0xFFFFFFFF UPPS [3:0] read-write read-write Disable quad signal not divided 0 Div2 quad signal divided by 2 1 Div4 quad signal divided by 4 2 Div8 quad signal divided by 8 3 Div16 quad signal divided by 16 4 Div32 quad signal divided by 32 5 Div64 quad signal divided by 64 6 Div128 quad signal divided by 128 7 Div256 quad signal divided by 256 8 Div512 quad signal divided by 512 9 Div1024 quad signal divided by 1024 10 Div2048 quad signal divided by 2048 11 CCPS [6:4] read-write read-write Disable no divider 0 Div2 sysclk divided by 2 1 Div4 sysclk divided by 4 2 Div8 sysclk divided by 8 3 Div16 sysclk divided by 16 4 Div32 sysclk divided by 32 5 Div64 sysclk divided by 64 6 Div128 sysclk divided by 128 7 SELEVENT Reset timer control [7:7] read-write CEN Enable eQEP capture [15:15] read-write EPSLD Enhanced prescalers load [16:16] read-write QPOSCTL Position-compare Control register 0x0038 32 read-write 0x00000000 0xFFFFFFFF PCSPW [11:0] read-write PCE Position-compare enable/disable [12:12] read-write PCPOL Polarity of sync output [13:13] read-write PCLOAD Position-compare shadow load mode [14:14] read-write PCSHDW Position-compare shadow enable [15:15] read-write QEINT Interrupt Enable register 0x3C 32 read-write 0x00000000 0xFFFFFFFF PCE Position counter error interrupt enable [1:1] read-write QPE Quadrature phase error interrupt enable [2:2] read-write QDC Quadrature direction change interrupt enable [3:3] read-write WTO Watchdog time out interrupt enable [4:4] read-write PCU Position counter underflow interrupt enable [5:5] read-write PCO Position counter overflow interrupt enable [6:6] read-write PCR Position-compare ready interrupt enable [7:7] read-write PCM Position-compare match interrupt enable [8:8] read-write SEL Strobe event latch interrupt enable [9:9] read-write IEL Index event latch interrupt enable [10:10] read-write UTO Unit time out interrupt enable [11:11] read-write QFLG Interrupt Flag register 0x40 32 read-only 0x00000000 0xFFFFFFFF INT Global interrupt status flag [0:0] read-only PCE Position counter error interrupt flag [1:1] read-only QPE Quadrature phase error interrupt flag [2:2] read-only QDC Quadrature direction change interrupt flag [3:3] read-only WTO Watchdog timeout interrupt flag [4:4] read-only PCU Position counter underflow interrupt flag [5:5] read-only PCO Position counter overflow interrupt flag [6:6] read-only PCR Position-compare ready interrupt flag [7:7] read-only PCM QEP compare match event interrupt flag [8:8] read-only SEL Strobe event latch interrupt flag [9:9] read-only IEL Index event latch interrupt flag [10:10] read-only UTO Unit time out interrupt flag [11:11] read-only QFLGLAT Latches QFLG[11:0] on every QPOSCNT read [27:16] read-only QCLR Interrupt Clear register 0x44 32 read-write 0x00000000 0xFFFFFFFF INT Global interrupt clear flag [0:0] read-write PCE Clear position counter error interrupt flag [1:1] read-write QPE Clear quadrature phase error interrupt flag [2:2] read-write QDC Clear quadrature direction change interrupt flag [3:3] read-write WTO Clear watchdog timeout interrupt flag [4:4] read-write PCU Clear position counter underflow interrupt flag [5:5] read-write PCO Clear position counter overflow interrupt flag [6:6] read-write PCR Clear position-compare ready interrupt flag [7:7] read-write PCM Clear eQEP compare match event interrupt flag [8:8] read-write SEL Clear strobe event latch interrupt flag [9:9] read-write IEL Clear index event latch interrupt flag [10:10] read-write UTO Clear unit time out interrupt flag [11:11] read-write QFRC Interrupt Force register 0x48 32 read-write 0x00000000 0xFFFFFFFF PCE Force position counter error interrupt [1:1] read-write QPE Force quadrature phase error interrupt [2:2] read-write QDC Force quadrature direction change interrupt [3:3] read-write WTO Force watchdog time out interrupt [4:4] read-write PCU Force position counter underflow interrupt [5:5] read-write PCO Force position counter overflow interrupt [6:6] read-write PCR Force position-compare ready interrupt [7:7] read-write PCM Force position-compare match interrupt [8:8] read-write SEL Force strobe event latch interrupt [9:9] read-write IEL Force index event latch interrupt [10:10] read-write UTO Force unit time out interrupt [11:11] read-write QEPSTS Status register 0x004C 32 read-write 0x00000000 0xFFFFFFFF PCEF Position counter error flag [0:0] read-write FIMF First index marker flag [1:1] read-write CDEF Capture direction error flag [2:2] read-write COEF Capture overflow error flag [3:3] read-write QDLF QEP direction latch flag [4:4] read-write QDF Quadrature direction flag [5:5] read-write FIDF Direction on the first index marker [6:6] read-write UPEVNT Unit position event flag [7:7] read-write DCF Direction change flag [8:8] read-write QCTMR Capture Timer register 0x0050 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QCPRD Capture Period register 0x0054 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write QCTMRLAT Capture Timer Latch register 0x0058 32 read-only 0x00000000 0xFFFFFFFF VAL [31:0] read-only QCPRDLAT Capture Period Latch register 0x005C 32 read-only 0x00000000 0xFFFFFFFF VAL [31:0] read-only DMAREQ DMA request register 0x0060 32 read-write 0x00000000 0xFFFFFFFF DMAEN DMA request enable [0:0] read-write INTCLR Clear active interrupt register 0x0070 32 read-write 0x00000000 0xFFFFFFFF INT Active interrupt by read, write 1 to clear interrupt [0:0] read-write ECAP0 1.0 ECAP controller registers 3ECAP 0x40051000 32 read-write 0 0x044 registers ECAP0 ECAP0 interrupt 37 TSCTR Counter register 0x0000 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write CTRPHS Counter Phase Sync register 0x0004 32 read-write 0x00000000 0xFFFFFFFF VAL [31:0] read-write CAP0 Capture register 0 0x0008 32 read-write 0x00000000 0xFFFFFFFF VAL Capture 0 value in CAP mode [31:0] read-write PRD CAP0 Period register 0x0008 32 read-write 0x00000000 0xFFFFFFFF VAL Period value in APWM mode [31:0] read-write CAP1 Capture register 1 0x000C 32 read-write 0x00000000 0xFFFFFFFF VAL Capture 1 value in CAP mode [31:0] read-write CMP CAP1 Compare register 0x000C 32 read-write 0x00000000 0xFFFFFFFF VAL Compare value in APWM mode [31:0] read-write CAP2 Capture register 2 0x0010 32 read-write 0x00000000 0xFFFFFFFF VAL Capture 2 value in CAP mode [31:0] read-write PRDSHDW CAP2 Period shadow register 0x0010 32 read-write 0x00000000 0xFFFFFFFF VAL Period shadow value in APWM mode [31:0] read-write CAP3 Capture register 3 0x0014 32 read-write 0x00000000 0xFFFFFFFF VAL Capture 3 value in CAP mode [31:0] read-write CMPSHDW CAP3 Compare shadow register 0x0014 32 read-write 0x00000000 0xFFFFFFFF VAL Compare shadow value in APWM mode [31:0] read-write ECCTL0 Capture control register 0 0x0028 32 read-write 0x00000000 0xFFFFFFFF CAP0POL Polarity select for capture 0 [0:0] read-write CTRRST0 Reset counter after event 0 [1:1] read-write CAP1POL Polarity select for capture 1 [2:2] read-write CTRRST1 Reset counter after event 1 [3:3] read-write CAP2POL Polarity select for capture 2 [4:4] read-write CTRRST2 Reset counter after event 2 [5:5] read-write CAP3POL Polarity select for capture 3 [6:6] read-write CTRRST3 Reset counter after event 3 [7:7] read-write CAPLDEN enable capture [8:8] read-write PRESCALE [13:9] read-write FREESOFT [15:14] read-write read-write Stop stop timer immedeatelly 0 StopAtZero stop timer when reach zero 1 Free normal work 2 ECCTL1 Capture control register 1 0x002C 32 read-write 0x00000000 0xFFFFFFFF CONTOST Capture mode [0:0] read-write STOPWRAP [2:1] read-write REARM Reset and enable controller, capture reg load [3:3] read-write TSCTRSTOP Enable Timer [4:4] read-write SYNCIEN Sync in enable [5:5] read-write SYNCOSEL [7:6] read-write read-write Bypass sync in connected with sync out 0 CTREqPrd sync out generated when CTR = PRD 1 Disable sync out generate disabled 2 SWSYNC Software timers sync [8:8] read-write CAPAPWM Capture mode or APWM mode [9:9] read-write APWMPOL High/low level APWM [10:10] read-write ECEINT Interrupt mask register 0x0030 32 read-write 0x00000000 0xFFFFFFFF CEVT0 enable int CEVT0 [1:1] read-write CEVT1 enable int CEVT1 [2:2] read-write CEVT2 enable int CEVT2 [3:3] read-write CEVT3 enable int CEVT3 [4:4] read-write CTROVF enable int CTR_OVF [5:5] read-write CTRPRD enable int CTR=PRD [6:6] read-write CTRCMP enable int CTR=CMP [7:7] read-write ECFLG Interrupt status register 0x0034 32 read-only 0x00000000 0xFFFFFFFF INT indicate global interrupt [0:0] read-only CEVT0 Hap interrupt CEVT0 [1:1] read-only CEVT1 Hap interrupt CEVT1 [2:2] read-only CEVT2 Hap interrupt CEVT2 [3:3] read-only CEVT3 Hap interrupt CEVT3 [4:4] read-only CTROVF Hap interrupt CTROVF [5:5] read-only CTRPRD Hap interrupt CTR=PRD [6:6] read-only CTRCMP Hap interrupt CTR=CMP [7:7] read-only ECCLR Clear interrupt register 0x0038 32 read-write 0x00000000 0xFFFFFFFF INT reset global interrupt [0:0] read-write CEVT0 reset intstatus [1:1] read-write CEVT1 reset intstatus [2:2] read-write CEVT2 reset intstatus [3:3] read-write CEVT3 reset intstatus [4:4] read-write CTROVF reset intstatus [5:5] read-write CTRPRD reset intstatus [6:6] read-write CTRCMP reset intstatus [7:7] read-write ECFRC Force interrupt register 0x003C 32 read-write 0x00000000 0xFFFFFFFF CEVT0 gen test interrupt [1:1] read-write CEVT1 gen test interrupt [2:2] read-write CEVT2 gen test interrupt [3:3] read-write CEVT3 gen test interrupt [4:4] read-write CTROVF gen test interrupt [5:5] read-write CTRPRD gen test interrupt [6:6] read-write CTRCMP gen test interrupt [7:7] read-write PEINT Active interrupt status register 0x0040 32 read-write 0x00000000 0xFFFFFFFF PEINT active interrupt flag [0:0] read-write ECAP1 0x40052000 ECAP1 ECAP1 interrupt 38 ECAP2 0x40053000 ECAP2 ECAP2 interrupt 39 PWM0 1.0 PWM controller registers 3PWM 0x4004C000 32 read-write 0 0x0AC registers PWM0 PWM0 interrupt 40 PWM0_HD PWM0 HD interrupt 41 PWM0_TZ PWM0 TZ interrupt 42 TBCTL Time-Base Control Register 0x0000 32 read-write 0x00000000 0xFFFFFFFF CTRMODE [1:0] read-write read-write Up count direction up 0 Down count direction down 1 UpDown count direction up-down 2 Stop counter stopped 3 PHSEN Counter register load from phase register enable [2:2] read-write PRDLD Active period register load from shadow register select [3:3] read-write SYNCOSEL [5:4] read-write read-write SYNCI PWM_SYNCI is source for PWM_SYNCO 0 CTREqZero CTR = 0000h is source for PWM_SYNCO 1 CTREqCMPB CTR = CMPB is source for PWM_SYNCO 2 Disable PWM_SYNCO generation disabled 3 SWFSYNC Software forced synchronization pulse [6:6] read-write HSPCLKDIV [9:7] read-write read-write Div1 clock not divided 0 Div2 clock divided by 2 1 Div4 clock divided by 4 2 Div6 clock divided by 6 3 Div8 clock divided by 8 4 Div10 clock divided by 10 5 Div12 clock divided by 12 6 Div14 clock divided by 14 7 CLKDIV [12:10] read-write read-write Div1 clock not divided 0 Div2 clock divided by 2 1 Div4 clock divided by 4 2 Div8 clock divided by 8 3 Div16 clock divided by 16 4 Div32 clock divided by 32 5 Div64 clock divided by 64 6 Div128 clock divided by 128 7 PHSDIR Phase direction bit [13:13] read-write FREESOFT [15:14] read-write read-write StopAtTBCLK stop timer at next TBCLK tact 0 StopAtPeriod stop timer when period ends 1 FreeRun free run mode 2 SHDWGLOB Global enable for all shadow loads [16:16] read-write TBSTS Time-Base Status Register 0x0004 32 read-write 0x00000000 0xFFFFFFFF CTRDIR Time-Base counter direction status bit [0:0] read-write SYNCI Input synchronization latched status bit [1:1] read-write CTRMAX Time-Base counter max latched status bit [2:2] read-only TBPHS Time-Base Phase Register 0x0008 32 read-write 0x00000000 0xFFFFFFFF TBPHS [31:16] read-write TBCTR Time-Base Counter Register 0x000C 32 read-write 0x00000000 0xFFFFFFFF VAL [15:0] read-write TBPRD Time-Base Period Register 0x0010 32 read-write 0x00000000 0xFFFFFFFF VAL [15:0] read-write CMPCTL Counter-Compare Control Register 0x0014 32 read-write 0x00000000 0xFFFFFFFF LOADAMODE [1:0] read-write read-write CTREqZero shadow load for CMPx (x=A,B) when CTR = 0 0 CTREqPRD shadow load for CMPx (x=A,B) when CTR = PRD 1 CTREqZeroPRD shadow load for CMPx (x=A,B) when CTR = 0 or CTR = PRD 2 Disable shadow load for CMPx (x=A,B) disabled 3 LOADBMODE [3:2] read-write read-write CTREqZero shadow load for CMPx (x=A,B) when CTR = 0 0 CTREqPRD shadow load for CMPx (x=A,B) when CTR = PRD 1 CTREqZeroPRD shadow load for CMPx (x=A,B) when CTR = 0 or CTR = PRD 2 Disable shadow load for CMPx (x=A,B) disabled 3 SHDWAMODE CMPA register operating mode [4:4] read-write SHDWBMODE CMPB register operating mode [6:6] read-write SHDWAFULL CMPA shadow register full status flag [8:8] read-only SHDWBFULL CMPB shadow register full status flag [9:9] read-only CMPA Counter-Compare A Register 0x0018 32 read-write 0x00000000 0xFFFFFFFF CMPA [31:16] read-write CMPB Counter-Compare B Register 0x001C 32 read-write 0x00000000 0xFFFFFFFF CMPB [31:16] read-write AQCTLA Action-Qualifier Output A Control Register 0x0020 32 read-write 0x00000000 0xFFFFFFFF ZRO [1:0] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 PRD [3:2] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CAU [5:4] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CAD [7:6] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CBU [9:8] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CBD [11:10] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 AQCTLB Action-Qualifier Output B Control Register 0x0024 32 read-write 0x00000000 0xFFFFFFFF ZRO [1:0] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 PRD [3:2] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CAU [5:4] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CAD [7:6] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CBU [9:8] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 CBD [11:10] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 AQSFRC Action-Qualifier Software Force Register 0x0028 32 read-write 0x00000000 0xFFFFFFFF ACTSFA [1:0] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 OTSFA One-time software forced event on output A [2:2] read-write ACTSFB [4:3] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 Toggle inverse PWMA/PWMB 3 OTSFB One-time software forced event on output B [5:5] read-write RLDCSF [7:6] read-write read-write CTREqZero load when CTR = 0 0 CTREqPRD load when CTR = PRD 1 CTREqZeroPRD load when CTR = 0 or CTR = PRD 2 NoShadow load immediatelly 3 AQCSFRC Action-Qualifier Continuous Software Force Register 0x002C 32 read-write 0x00000000 0xFFFFFFFF CSFA [1:0] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 CSFB [3:2] read-write read-write NoAction no action 0 Clear clear PWMA/PWMB 1 Set set PWMA/PWMB 2 DBCTL Dead-Band Generator Control Register 0x0030 32 read-write 0x00000000 0xFFFFFFFF OUTMODE [1:0] read-write read-write NoSpec edge for deadtime is no specified 0 BNeg deadtime on PWMB negedge 1 APos deadtime on PWMA posedge 2 Apos_BNeg deadtime on PWMA posedge and PWMB negedge 3 POLSEL [3:2] read-write read-write InvDisable inverse disabled 0 InvA inverse on PWMA 1 InvB inverse on PWMB 2 InvAB inverse on PWMA and PWMB 3 INMODE [5:4] read-write read-write APosNeg PWMA is used for posedge and negedge control 0 ANeg_BPos PWMA is used for negedge and PWMB is used for posedge control 1 APos_BNeg PWMA is used for posedge and PWMB is used for negedge control 2 BPosNeg PWMB is used for posedge and negedge control 3 DBRED Dead-Band Generator Rising Edge Delay Register 0x0034 32 read-write 0x00000000 0xFFFFFFFF DEL [9:0] read-write DBFED Dead-Band Generator Falling Edge Delay Register 0x0038 32 read-write 0x00000000 0xFFFFFFFF DEL [9:0] read-write TZSEL Trip-Zone Select Register 0x003C 32 read-write 0x00000000 0xFFFFFFFF CBC Cycle-by-Cycle trip-zone 0 enable [0:0] read-write OST One-Shot trip-zone 0 enable [8:8] read-write TZCTL Trip-Zone Control Register 0x0040 32 read-write 0x00000000 0xFFFFFFFF TZA [1:0] read-write read-write Z PWMA/PWMB go to Z on failture 0 Set PWMA/PWMB go to 1 on failture 1 Clear PWMA/PWMB go to 0 on failture 2 NoAction no action on failture 3 TZB [3:2] read-write read-write Z PWMA/PWMB go to Z on failture 0 Set PWMA/PWMB go to 1 on failture 1 Clear PWMA/PWMB go to 0 on failture 2 NoAction no action on failture 3 TZEINT Trip-Zone Enable Interrupt Register 0x0044 32 read-write 0x00000000 0xFFFFFFFF CBC Trip-zone Cycle-by-Cycle interrupt enable [1:1] read-write OST Trip-zone One-Shot interrupt enable [2:2] read-write TZFLG Trip-Zone Flag Register 0x0048 32 read-only 0x00000000 0xFFFFFFFF INT Latched trip interrupt status flag [0:0] read-only CBC Latched status flag for Cycle-By-Cycle trip event [1:1] read-only OST Latched status flag for a One-Shot trip event [2:2] read-only TZCLR Trip-Zone Clear Register 0x004C 32 read-write 0x00000000 0xFFFFFFFF INT Clear trip-zone interrupt flag [0:0] read-write CBC Clear flag for Cycle-By-Cycle trip latch [1:1] read-write OST Clear flag for One-Shot trip latch [2:2] read-write TZFRC Trip-Zone Force Register 0x0050 32 read-write 0x00000000 0xFFFFFFFF CBC Force a Cycle-by-Cycle trip event via software [1:1] read-write OST Force a One-Shot trip event via software [2:2] read-write ETSEL Event-Trigger Selection Register 0x0054 32 read-write 0x00000000 0xFFFFFFFF INTSEL [2:0] read-write read-write CTREqZero generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 1 CTREqPRD generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD 2 CTREqCMPA_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up 4 CTREqCMPA_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down 5 CTREqCMPB_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up 6 CTREqCMPB_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down 7 INTEN Enable PWM_INT interrupt generation [3:3] read-write SOCASEL [10:8] read-write read-write CTREqZero generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 1 CTREqPRD generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD 2 CTREqCMPA_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up 4 CTREqCMPA_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down 5 CTREqCMPB_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up 6 CTREqCMPB_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down 7 SOCAEN Enable the ADC start of conversion A PWM_SOCA pulse [11:11] read-write SOCBSEL [14:12] read-write read-write CTREqZero generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 1 CTREqPRD generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD 2 CTREqCMPA_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up 4 CTREqCMPA_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down 5 CTREqCMPB_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up 6 CTREqCMPB_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down 7 SOCBEN Enable the ADC start of conversion B PWM_SOCB pulse [15:15] read-write DRQASEL [18:16] read-write read-write CTREqZero generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 1 CTREqPRD generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD 2 CTREqCMPA_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up 4 CTREqCMPA_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down 5 CTREqCMPB_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up 6 CTREqCMPB_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down 7 DRQAEN Enable the DMA request from PWM A [19:19] read-write DRQBSEL [22:20] read-write read-write CTREqZero generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = 0 1 CTREqPRD generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = PRD 2 CTREqCMPA_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count up 4 CTREqCMPA_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPA when count down 5 CTREqCMPB_OnUp generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count up 6 CTREqCMPB_OnDown generate PWM_SOCA/PWM_SOCB/PWN_INT impulse on CTR = CMPB when count down 7 DRQBEN Enable the DMA request from PWM B [23:23] read-write ETPS Event-Trigger Prescale Register 0x0058 32 read-write 0x00000000 0xFFFFFFFF INTPRD [1:0] read-write INTCNT [3:2] read-only SOCAPRD [9:8] read-write SOCACNT [11:10] read-only SOCBPRD [13:12] read-write SOCBCNT [15:14] read-only DRQAPRD [17:16] read-write DRQACNT [19:18] read-only DRQBPRD [21:20] read-write DRQBCNT [23:22] read-only ETFLG Event-Trigger Flag Register 0x005C 32 read-only 0x00000000 0xFFFFFFFF INT Latched PWM Interrupt (PWM_INT) status flag [0:0] read-only SOCA Latched PWM ADC Start-of-Conversion A (PWM_SOCA) status flag [2:2] read-only SOCB Latched PWM ADC Start-of-Conversion B (PWM_SOCB) status flag [3:3] read-only DRQA Latched PWM DMA request A status flag [4:4] read-only DRQB Latched PWM DMA request B status flag [5:5] read-only ETCLR Event-Trigger Clear Register 0x0060 32 read-write 0x00000000 0xFFFFFFFF INT Latched PWM Interrupt (PWM_INT) flag clear bit [0:0] read-write SOCA Latched PWM ADC Start-of-Conversion A (PWM_SOCA) flag clear bit [2:2] read-write SOCB Latched PWM ADC Start-of-Conversion B (PWM_SOCB) flag clear bit [3:3] read-write DRQA Latched PWM DMA request A flag clear bit [4:4] read-write DRQB Latched PWM DMA request B flag clear bit [5:5] read-write ETFRC Event-Trigger Force Register 0x0064 32 read-write 0x00000000 0xFFFFFFFF INT PWM_INT force bit. [0:0] read-write SOCA PWM_SOCA force bit [2:2] read-write SOCB PWM_SOCB force bit [3:3] read-write DRQA PWM DMA request A force bit [4:4] read-write DRQB PWM DMA request B force bit [5:5] read-write PCCTL PWM-Chopper Control Register 0x0068 32 read-write 0x00000000 0xFFFFFFFF CHPEN PWM-chopping enable [0:0] read-write OSTWTH [4:1] read-write CHPFREQ [7:5] read-write read-write Div1 sync frequency divide by 1 0 Div2 sync frequency divide by 2 1 Div3 sync frequency divide by 3 2 Div4 sync frequency divide by 4 3 Div5 sync frequency divide by 5 4 Div6 sync frequency divide by 6 5 Div7 sync frequency divide by 7 6 Div8 sync frequency divide by 8 7 CHPDUTY [10:8] read-write read-write Duty_1_8 duty 1/8 0 Duty_2_8 duty 2/8 1 Duty_3_8 duty 3/8 2 Duty_4_8 duty 4/8 3 Duty_5_8 duty 5/8 4 Duty_6_8 duty 6/8 5 Duty_7_8 duty 7/8 6 FWDTH Filter Width select Register 0x0070 32 read-write 0x00000000 0xFFFFFFFF VAL [7:0] read-write HDSEL Hold Detector event Select Register 0x0088 32 read-write 0x00000000 0xFFFFFFFF ADCDC0 Hold detector event by ADC Digital Comparator 0 enable [0:0] read-write ADCDC1 Hold detector event by ADC Digital Comparator 1 enable [1:1] read-write ADCDC2 Hold detector event by ADC Digital Comparator 2 enable [2:2] read-write ADCDC3 Hold detector event by ADC Digital Comparator 3 enable [3:3] read-write CBC Cycle-by-Cycle hold detector enable [28:28] read-write OST One-Shot hold detector enable [31:31] read-write HDCTL Hold Detector Control register 0x008C 32 read-write 0x00000000 0xFFFFFFFF HDA [1:0] read-write read-write Set PWMA/PWMB go to 1 on failture 1 Clear PWMA/PWMB go to 0 on failture 2 NoAction no action on failture 3 HDB [3:2] read-write read-write Set PWMA/PWMB go to 1 on failture 1 Clear PWMA/PWMB go to 0 on failture 2 NoAction no action on failture 3 HDEINT Hold Detector Enable Interrupt Register 0x0090 32 read-write 0x00000000 0xFFFFFFFF CBC Hold detector Cycle-by-Cycle interrupt enable [1:1] read-write OST Hold detector One-Shot interrupt enable [2:2] read-write HDFLG Hold Detector Flag Register 0x0094 32 read-only 0x00000000 0xFFFFFFFF INT Latched hold detector interrupt status flag [0:0] read-only CBC Latched status flag for hold detector Cycle-by-Cycle event [1:1] read-only OST Latched status flag for hold detector One-Shot event [2:2] read-only HDCLR Register clear HD flag 0x0098 32 read-write 0x00000000 0xFFFFFFFF INT Clear hold detector interrupt flag [0:0] read-write CBC Clear flag for Cycle-By-Cycle hold detector latch [1:1] read-write OST Clear flag for One-Shot hold detector latch [2:2] read-write HDFRC Hold Detector Force Register 0x009C 32 read-write 0x00000000 0xFFFFFFFF CBC Force a Cycle-by-Cycle hold detector event via software [1:1] read-write OST Force a One-Shot hold detector event via software [2:2] read-write HDINTCLR Hold Detector Interrupt pending Clear Register 0x00A0 32 write-only 0x00000000 0xFFFFFFFF INT Clear HD interrupt pending [0:0] write-only TZINTCLR Trip-Zone Interrupt pending Clear Register 0x00A4 32 write-only 0x00000000 0xFFFFFFFF INT Clear TZ interrupt pending [0:0] write-only INTCLR PWM Interrupt pending Clear Register 0x00A8 32 write-only 0x00000000 0xFFFFFFFF INT Clear interrupt pending [0:0] write-only PWM1 0x4004D000 PWM1 PWM1 interrupt 43 PWM1_HD PWM1 HD interrupt 44 PWM1_TZ PWM1 TZ interrupt 45 PWM2 0x4004E000 PWM2 PWM2 interrupt 46 PWM2_HD PWM2 HD interrupt 47 PWM2_TZ PWM2 TZ interrupt 48 SPI 1.0 SPI control registers SPI 0x40047000 32 read-write 0 0x028 registers SPI_RO_RT SPI RX FIFO overrun and Receive Timeout interrupt 33 SPI_RX SPI Receive interrupt 34 SPI_TX SPI Transmit interrupt 35 CR0 Control register 0 0x0000 32 read-write 0x00000000 0xFFFFFFFF DSS [3:0] read-write read-write 4bit data size 4 bit 3 5bit data size 5 bit 4 6bit data size 6 bit 5 7bit data size 7 bit 6 8bit data size 8 bit 7 9bit data size 9 bit 8 10bit data size 10 bit 9 11bit data size 11 bit 10 12bit data size 12 bit 11 13bit data size 13 bit 12 14bit data size 14 bit 13 15bit data size 15 bit 14 16bit data size 16 bit 15 FRF [5:4] read-write read-write SPI SPI of Motorola 0 SSI SSI of Texas Instruments 1 Microwire Microwire of National Semiconductor 2 SPO Polarity SSPCLKOUT [6:6] read-write SPH Phase SSPCLKOUT [7:7] read-write SCR [15:8] read-write CR1 Control register 1 0x0004 32 read-write 0x00000000 0xFFFFFFFF SSE Enable transceiver [1:1] read-write MS Select mode [2:2] read-write SOD Disable bit data [3:3] read-write RXIFLSEL [11:8] read-write TXIFLSEL [15:12] read-write DR Data register 0x0008 32 read-write 0x00000000 0xFFFFFFFF DATA [15:0] read-write SR State register 0x000C 32 read-only 0x00000000 0xFFFFFFFF TFE FIFO buffer empty flag transmitter [0:0] read-only TNF Indicator the transmitter FIFO buffer is not full [1:1] read-only RNE Indicate not empty receive buffer [2:2] read-only RFF Indicate full receive buffer [3:3] read-only BSY Activity flag [4:4] read-only CPSR Clock division factor register 0x0010 32 read-write 0x00000000 0xFFFFFFFF CPSDVSR [7:0] read-only IMSC Mask interrupt register 0x0014 32 read-write 0x00000000 0xFFFFFFFF RORIM Interrupt mask bit SSPRORINTR buffer overflow receiver [0:0] read-write RTIM Interrupt mask bit SSPRTINTR timeout receiver [1:1] read-write RXIM SSPRXINTR interrupt mask bit to fill 50% or less of the receiver FIFO buffer [2:2] read-write TXIM SSPTXINTR interrupt mask bit to fill 50% or less of the FIFO buffer of the transmitter [3:3] read-write RIS Status register interrupt without mask 0x0018 32 read-only 0x00000000 0xFFFFFFFF RORRIS Interrupt status before masking SSPRORINTR [0:0] read-only RTRIS Interrupt status before masking SSPRTINTR [1:1] read-only RXRIS Interrupt status before masking SSPRXINTR [2:2] read-only TXRIS Interrupt status before masking SSPTXINTR [3:3] read-only MIS Status register interrupt masking account 0x001C 32 read-only 0x00000000 0xFFFFFFFF RORRIS Masked interrupt status SSPRORINTR [0:0] read-only RTRIS Masked interrupt status SSPRTINTR [1:1] read-only RXRIS Masked interrupt status SSPRXINTR [2:2] read-only TXRIS Masked interrupt status SSPTXINTR [3:3] read-only ICR Register reset interrupt 0x0020 32 write-only 0x00000000 0xFFFFFFFF RORIC Reset interrupt SSPRORINTR [0:0] write-only RTIC Reset interrupt SSPRTINTR [1:1] write-only DMACR Control register DMA 0x0024 32 read-write 0x00000000 0xFFFFFFFF RXDMAE DMA enable bit at reception [0:0] read-write TXDMAE DMA enable bit transmission [1:1] read-write I2C 1.0 I2C controller registers I2C 0x40050000 32 read-write 0 0x028 registers I2C I2C interrupt 36 SDA Data register 0x0000 32 read-write 0x00000000 0xFFFFFFFF DATA [7:0] read-write ST Status register 0x0004 32 read-only 0x00000000 0xFFFFFFFF MODE [5:0] read-only read IDLE General - Idle, no valid status information available 0 STDONE FS master - Start condition generated 1 RSDONE FS master - Repeated start condition generated 2 IDLARL FS master - Arbitration lost, unaddressed slave mode entered 3 MTADPA FS master transmit - Slave address sent, positive ACK 4 MTADNA FS master transmit - Slave address sent, negative ACK 5 MTDAPA FS master transmit - Data byte sent, positive ACK 6 MTDANA FS master transmit - Data byte sent, negative ACK 7 MRADPA FS master receive - Slave addres sent, positive ACK 8 MRADNA FS master receive - Slave addres sent, negative ACK 9 MRDAPA FS master receive - Data byte received, positive ACK 10 MRDANA FS master receive - Data byte received, negative ACK 11 MTMCER FS master - Mastercode transmitted, error detected (positive ACK) 12 SRADPA FS slave receive - Slave address received, positive ACK 16 SRAAPA FS slave receive - Slave address received after arbitration loss, positive ACK 17 SRDAPA FS slave receive - Data byte received, positive ACK 18 SRDANA FS slave receive - Data byte received, negative ACK 19 STADPA FS slave transmit - Slave address received, positive ACK 20 STAAPA FS slave transmit - Slave address received, negative ACK 21 STDAPA FS slave transmit - Data byte sent, positive ACK 22 STDANA FS slave transmit - Data byte sent, negative ACK 23 SATADP FS slave transmit alert response - Alert response address received, positive ACK 24 SATAAP FS slave transmit alert response - Alert response address received after arbitration loss, positive ACK 25 SATDAP FS slave transmit alert response - Alert response data byte sent, positive ACK 26 SATDAN FS slave transmit alert response - Alert response data byte sent, negative ACK 27 SSTOP FS slave - Slave mode stop condition detected 28 SGADPA FS slave - Global call address received, positive ACK 29 SDAAPA FS slave - Global call address received after arbitration loss, positive ACK 30 BERROR General - Bus error detected (invalid start or stop condition 31 HMTMCOK HS master - Master code transmitted OK - switched to HS mode 33 HRSDONE HS master - Repeated start condition generated 34 HIDLARL HS master - Arbitration lost, HS unaddressed slave mode entered 35 HMTADPA HS master transmit - Slave address sent, positive ACK 36 HMTADNA HS master transmit - Slave address sent, negative ACK 37 HMTDAPA HS master transmit - Data byte sent, positive ACK 38 HMTDANA HS master transmit - Data byte sent, negative ACK 39 HMRADPA HS master receive - Slave address sent, positive ACK 40 HMRADNA HS master receive - Slave address sent, negative ACK 41 HMRDAPA HS master receive - Data byte received, positive ACK 42 HMRDANA HS master receive - Data byte received, negative ACK 43 HSRADPA HS slave receive - Slave address received, positive ACK 48 HSRDAPA HS slave receive - Data byte received, positive ACK 50 HSRDANA HS slave receive - Data byte received, negative ACK 51 HSTADPA HS slave transmit - Slave address received, positive ACK 52 HSTDAPA HS slave transmit - Data byte sent, positive ACK 54 HSTDANA HS slave transmit - Data byte sent, negative ACK 55 INT Interrupt flag [7:7] read-only CST Status and control register 0x0008 32 read-write 0x00000000 0xFFFFFFFF BB Bus Busy [0:0] read-write TOCDIV [2:1] read-write read-write Disable disable clock 0 Div4 clock divided by 4 1 Div8 clock divided by 8 2 Div16 clock divided by 16 3 TOERR SMBus Timeout Error [3:3] read-write TSDA Bit test SDA [4:4] read-write TGSCL Toggle SCL [5:5] read-write PECNEXT PEC Next [6:6] read-write PECFAULT Packet Error Fault [7:7] read-write CTL0 Control register 0 0x000C 32 read-write 0x00000000 0xFFFFFFFF START Start bit [0:0] read-write STOP Stop bit [1:1] read-write INTEN Interrupt enable bit [2:2] read-write ACK Acknowledge bit [4:4] read-write GCMEN Global call match enable [5:5] read-write SMBARE SMBus Alert Response Match Enable [6:6] read-write CLRST Clear interrupt status [7:7] read-write ADDR Register own address 0x0010 32 read-write 0x00000000 0xFFFFFFFF ADDR [6:0] read-write SAEN Enable address recognition [7:7] read-write CTL1 Control register 1 0x0014 32 read-write 0x00000000 0xFFFFFFFF ENABLE Enable I2C [0:0] read-write SCLFRQ [7:1] read-write TOPR Prescaler load register 0x0018 32 read-write 0x00000000 0xFFFFFFFF SMBTOPR [7:0] read-write CTL2 Control register 2 0x001C 32 read-write 0x00000000 0xFFFFFFFF S10ADR [2:0] read-write S10EN Enabled 10-bit slave address [3:3] read-write HSDIV [7:4] read-write CTL3 Control register 3 0x0020 32 read-write 0x00000000 0xFFFFFFFF SCLFRQ SCL frequency (bits [14:7]) [7:0] read-write CTL4 Control Register 4 0x0024 32 read-write 0x00000000 0xFFFFFFFF HSDIV SCL frequency select in HS master mode (bits [11:4]) [7:0] read-write CAN 1.0 CAN controller registers CAN 0x40020000 32 read-write 0 0x3004 registers CAN0 CAN0 interrupt 53 CAN1 CAN1 interrupt 54 CAN2 CAN2 interrupt 55 CAN3 CAN3 interrupt 56 CAN4 CAN4 interrupt 57 CAN5 CAN5 interrupt 58 CAN6 CAN6 interrupt 59 CAN7 CAN7 interrupt 60 CAN8 CAN8 interrupt 61 CAN9 CAN9 interrupt 62 CAN10 CAN10 interrupt 63 CAN11 CAN11 interrupt 64 CAN12 CAN12 interrupt 65 CAN13 CAN13 interrupt 66 CAN14 CAN14 interrupt 67 CAN15 CAN15 interrupt 68 CLC CAN Clock Control Register 0x0000 32 read-write 0x00000000 0xFFFFFFFF DISR Module Disable Request bit [0:0] read-write DISS Module Disable Status Bit [1:1] read-only ID Module Identification Register 0x0008 32 read-write 0x00000000 0xFFFFFFFF MODREV Module Revision Number [7:0] read-write MODTYPE Module type [15:8] read-only MODNUM Module Number Value [31:16] read-only FDR Fractional Divider Register 0x000C 32 read-write 0x00000000 0xFFFFFFFF STEP Step Value [9:0] read-write SM Suspend Mode [11:11] read-write SC Suspend Control [13:12] read-write DM [15:14] read-write read-write Disable counter disabled 0 NormalMode normal operation mode 1 DividerMode divider operation mode 2 RESULT Result Value [25:16] read-only SUSACK Suspend Mode Acknowledge [28:28] read-only SUSREQ Suspend Mode Request [29:29] read-only ENHW Enable Hardware Clock Control [30:30] read-write DISCLK Disable Clock [31:31] read-write 8 4 0-7 LIST[%s] LIST 0x100 LIST List Register0 0x00 32 read-only 0x00000000 0xFFFFFFFF BEGIN List Begin [7:0] read-only END List End [15:8] read-only SIZE List Size [23:16] read-only EMPTY List Empty Indication [24:24] read-only 4 4 0-3 MSPND[%s] MSPND 0x140 MSPND Message Pending Register0 0x00 32 read-write 0x00000000 0xFFFFFFFF PND Message Pending [31:0] read-write 4 4 0-3 MSID[%s] MSID 0x180 MSID Message Index Register0 0x00 32 read-only 0x00000000 0xFFFFFFFF INDEX Message Pending Index [7:0] read-only MSIMASK Message Index Mask Register 0x01C0 32 read-write 0x00000000 0xFFFFFFFF IM Message Index Mask [31:0] read-write PANCTR Panel Control Register 0x01C4 32 read-write 0x00000000 0xFFFFFFFF PANCMD Panel Command [7:0] read-write BUSY Panel Busy Flag [8:8] read-only RBUSY Result Busy Flag [9:9] read-only PANAR1 Panel argument 1 [23:16] read-write PANAR2 Panel argument 2 [31:24] read-write MCR No description 0x01C8 32 read-write 0x00000000 0xFFFFFFFF MPSEL Message Pending Selector [15:12] read-write MITR Module Interrupt Trigger Register 0x01CC 32 write-only 0x00000000 0xFFFFFFFF IT Interrupt Trigger [15:0] write-only 2 256 0-1 Node[%s] Node 0x200 NCR Node control register0 0x00 32 read-write 0x00000000 0xFFFFFFFF INIT Node Initialization [0:0] read-write TRIE Transfer Interrupt Enable [1:1] read-write LECIE LEC Indicated Error Interrupt Enable [2:2] read-write ALIE Alert Interrupt Enable [3:3] read-write CANDIS CAN Disable [4:4] read-write CCE Configuration Change Enable [6:6] read-write CALM CAN Analyzer Mode [7:7] read-write SUSEN Suspend Enable [8:8] read-write NSR Node Status Register0 0x04 32 read-write 0x00000000 0xFFFFFFFF LEC Last Error Code [2:0] read-write read-write NoErr no error 0 StuffErr stuff error 1 FormErr form error 2 AckErr acknowlegment error 3 Bit1Err bit 1 error 4 Bit0Err bit 0 error 5 CRCErr CRC error 6 WriteEn enable hardware write 7 TXOK Message Transmitted Successfully [3:3] read-write RXOK Message Received Successfully [4:4] read-write ALERT Alert Warning [5:5] read-write EWRN Error Warning Status [6:6] read-only BOFF Bus-Off Status [7:7] read-only LLE List Length Error [8:8] read-write LOE List Object Error [9:9] read-write SUSACK Suspend Acknowledge [10:10] read-only NIPR Node Interrupt Pointer Register0 0x08 32 read-write 0x00000000 0xFFFFFFFF ALINP Alert Interrupt Node Pointer [3:0] read-write LECINP Last Error Code Interrupt Node Pointer [7:4] read-write TRINP Transfer OK Interrupt Node Pointer [11:8] read-write CFCINP Frame Counter Interrupt Node Pointer [15:12] read-write NPCR Node Port Control Register0 0x0C 32 read-write 0x00000000 0xFFFFFFFF RXSEL Receive Select [2:0] read-write LBM Loop-Back Mode [8:8] read-write NBTR Node Bit Timing Register0 0x10 32 read-write 0x00000000 0xFFFFFFFF BRP Baud Rate Prescaler [5:0] read-write SJW [7:6] read-write TSEG1 Time Segment Before Sample Point [11:8] read-write TSEG2 Time Segment After Sample Point [14:12] read-write DIV8 Divide Prescaler Clock by 8 [15:15] read-write NECNT Node Error Counter Register0 0x14 32 read-write 0x00000000 0xFFFFFFFF REC Receive Error Counter [7:0] read-write TEC Transmit Error Counter [15:8] read-write EWRNLVL Error Warning Level [23:16] read-write LETD Last Error Transfer Direction [24:24] read-only LEINC Last Error Increment [25:25] read-only NFCR Node Frame Counter Register0 0x18 32 read-write 0x00000000 0xFFFFFFFF CFC CAN Frame Counter [15:0] read-write CFSEL CAN Frame Count Selection [18:16] read-write CFMOD CAN Frame Counter Mode [20:19] read-write CFCIE CAN Frame Counter Interrupt Enable [22:22] read-write CFCOV CAN Frame Counter Overflow Flag [23:23] read-write Reserved No description 0xFC 32 0x00000000 0xFFFFFFFF CANMSG 1.0 CAN Msg registers CANMSG 0x40021000 32 read-write 0 0x804 registers 64 32 0-63 Msg[%s] Msg 0x0 MOFCR Message Object Function Control Register0 0x00 32 read-write 0x00000000 0xFFFFFFFF MMC Message Mode Control [3:0] read-write read-write MsgObj message object 0 RXObj receiver FIFO structure object 1 TXObj transmitter FIFO structure object 2 SlaveTXObj transmitter FIFO structure slave object 3 SrcObj gateway source object 4 GDFS Gateway Data Frame Selected [8:8] read-write IDC Identifier Copy [9:9] read-write DLCC Data Lengh Code Copy [10:10] read-write DATC Data Copy [11:11] read-write RXIE Receive Interrupt Enable [16:16] read-write TXIE Transmit Interrupt Enable [17:17] read-write OVIE Overflow Interrupt Enable [18:18] read-write FRREN Foreign Remote Request Enable [20:20] read-write RMM Transmit Object Remote Monitoring [21:21] read-write SDT Single Data Transfer [22:22] read-write STT Single Transmit Trial [23:23] read-write DLC Data Length Code [27:24] read-write MOFGPR Message Object FIFO/Gateway Pointer Register0 0x04 32 read-write 0x00000000 0xFFFFFFFF BOT Botom Pointer [7:0] read-write TOP Top Pointer [15:8] read-write CUR Current Object Pointer [23:16] read-write SEL Object Select Pointer [31:24] read-write MOIPR Message Object Interrupt Pointer Register0 0x08 32 read-write 0x00000000 0xFFFFFFFF RXINP Receive Interrupt Node Pointer [3:0] read-write TXINP Transmit Interrupt Node Pointer [7:4] read-write MPN Message Pending Number [15:8] read-write CFCVAL CAN Frame Counter Value [31:16] read-write MOAMR Message Object Acceptance Mask Register0 0x0C 32 read-write 0x00000000 0xFFFFFFFF AM Acceptance Mask for Message Identifier [28:0] read-write MIDE Acceptance Mask Bit for Message IDE Bit [29:29] read-write MODATAL Message Object Data Register Low0 0x10 32 read-write 0x00000000 0xFFFFFFFF DB0 Data byte 0 of message object [7:0] read-write DB1 Data byte 1 of message object [15:8] read-write DB2 Data byte 2 of message object [23:16] read-write DB3 Data byte 3 of message object [31:24] read-write MODATAH Message Object Data Register High0 0x14 32 read-write 0x00000000 0xFFFFFFFF DB4 Data byte 4 of message object [7:0] read-write DB5 Data byte 5 of message object [15:8] read-write DB6 Data byte 6 of message object [23:16] read-write DB7 Data byte 7 of message object [31:24] read-write MOAR Message Object Arbitration Register0 0x18 32 read-write 0x00000000 0xFFFFFFFF ID CAN identifier of Message Object [28:0] read-write IDE Identifier Extension Bit of Messgae Object [29:29] read-write PRI Priority Class [31:30] read-write MOCTR Message Object Control Register0 0x1C 32 write-only 0x00000000 0xFFFFFFFF RESRXPND Reset Receive Pending [0:0] write-only RESTXPND Reset Transmit Pending [1:1] write-only RESRXUPD Reset Receive Updating [2:2] write-only RESNEWDAT Reset New Data [3:3] write-only RESMSGLST Reset Message Lost [4:4] write-only RESMSGVAL Reset Message Valid [5:5] write-only RESRTSEL Reset Receive/Transmit Selected [6:6] write-only RESRXEN Reset Receive Enable [7:7] write-only RESTXRQ Reset Transmit Request [8:8] write-only RESTXEN0 Reset Transmit Enable 0 [9:9] write-only RESTXEN1 Reset Transmit Enable 1 [10:10] write-only RESDIR Reset Message Direction [11:11] write-only SETRXPND Set Receive Pending [16:16] write-only SETTXPND Set Transmit Pending [17:17] write-only SETRXUPD Set Receive Updating [18:18] write-only SETNEWDAT Set New Data [19:19] write-only SETMSGLST Set Message Lost [20:20] write-only SETMSGVAL Set Message Valid [21:21] write-only SETRTSEL Set Receive/Transmit Selected [22:22] write-only SETRXEN Set Receive Enable [23:23] write-only SETTXRQ Set Transmit Request [24:24] write-only SETTXEN0 Set Transmit Enable 0 [25:25] write-only SETTXEN1 Set Transmit Enable 1 [26:26] write-only SETDIR Set Message Direction [27:27] write-only MOSTAT MOFCR Message Object Status Register 0 0x1C 32 read-only 0x00000000 0xFFFFFFFF RXPND Receive Pending [0:0] read-only TXPND Transmit Pending [1:1] read-only RXUPD Receive Updating [2:2] read-only NEWDAT New Data [3:3] read-only MSGLST Message Lost [4:4] read-only MSGVAL Message Valid [5:5] read-only RTSEL Receive/Transmit Selected [6:6] read-only RXEN Receive Enable [7:7] read-only TXRQ Transmit Request [8:8] read-only TXEN0 Transmit Enable 0 [9:9] read-only TXEN1 Transmit Enable 1 [10:10] read-only DIR Message Direction [11:11] read-only LIST List Allocation [15:12] read-only PPREV Pointer To Previous Message Object [23:16] read-only PNEXT Pointer to Next Message Object [31:24] read-only