Canaan Inc. K210 1.0 Kendryte K210 64-bit RISC-V CPU 8 64 32 read-write 0x00000000 0xFFFFFFFF CLINT Core Local Interruptor CLINT 0x02000000 2 0x04 msip[%s] Hart software interrupt register 0x0000 0 1 64 2 0x08 mtimecmp[%s] Hart time comparator register 0x4000 64 mtime Timer register 0xBFF8 PLIC Platform-Level Interrupt Controller PLIC 0x0C000000 1024 0x04 priority[%s] Interrupt Source Priority Register 0x000000 32 0x04 pending[%s] Interrupt Pending Register 0x001000 target_enables[%s] Target Interrupt Enables 0x002000 4 0x80 32 0x04 enable[%s] Interrupt Enable Register 0 targets[%s] Target Configuration 0x200000 4 0x1000 threshold Priority Threshold Register 0x0 priority 20 Priority Never Never interrupt 0 P1 Priority 1 1 P2 Priority 2 2 P3 Priority 3 3 P4 Priority 4 4 P5 Priority 5 5 P6 Priority 6 6 P7 Priority 7 7 claim Claim/Complete Register 0x4 0x00000000 0xFFFFFFFF _reserved Padding to make sure targets is an array 0xffc UARTHS High-speed UART UARTHS 0x38000000 txdata Transmit Data Register 0x00 data Transmit data [7:0] full Transmit FIFO full [31:31] rxdata Receive Data Register 0x04 data Received data [7:0] empty Receive FIFO empty [31:31] txctrl Transmit Control Register 0x08 txen Transmit enable [0:0] nstop Number of stop bits [1:1] txcnt Transmit watermark level [18:16] rxctrl Receive Control Register 0x0C rxen Receive enable [0:0] rxcnt Receive watermark level [18:16] ie Interrupt Enable Register 0x10 txwm Transmit watermark interrupt enable [0:0] rxwm Receive watermark interrupt enable [1:1] ip Interrupt Pending Register 0x14 txwm Transmit watermark interrupt pending [0:0] rxwm Receive watermark interrupt pending [1:1] div Baud Rate Divisor Register 0x18 div Baud rate divisor [15:0] UARTHS 33 GPIOHS High-speed GPIO GPIOHS 0x38001000 input_val Input Value Register 0x000 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 input_en Pin Input Enable Register 0x004 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 output_en Pin Output Enable Register 0x008 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 output_val Output Value Register 0x00C pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 pullup_en Internal Pull-Up Enable Register 0x010 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 drive Drive Strength Register 0x014 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 rise_ie Rise Interrupt Enable Register 0x018 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 rise_ip Rise Interrupt Pending Register 0x01C pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 fall_ie Fall Interrupt Enable Register 0x020 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 fall_ip Fall Interrupt Pending Register 0x024 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 high_ie High Interrupt Enable Register 0x028 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 high_ip High Interrupt Pending Register 0x02C pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 low_ie Low Interrupt Enable Register 0x030 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 low_ip Low Interrupt Pending Register 0x034 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 iof_en HW I/O Function Enable Register 0x038 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 iof_sel HW I/O Function Select Register 0x03C pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 output_xor Output XOR (invert) Register 0x040 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 pin888 pin999 pin101010 pin111111 pin121212 pin131313 pin141414 pin151515 pin161616 pin171717 pin181818 pin191919 pin202020 pin212121 pin222222 pin232323 pin242424 pin252525 pin262626 pin272727 pin282828 pin292929 pin303030 pin313131 GPIOHS0 34 GPIOHS1 35 GPIOHS2 36 GPIOHS3 37 GPIOHS4 38 GPIOHS5 39 GPIOHS6 40 GPIOHS7 41 GPIOHS8 42 GPIOHS9 43 GPIOHS10 44 GPIOHS11 45 GPIOHS12 46 GPIOHS13 47 GPIOHS14 48 GPIOHS15 49 GPIOHS16 50 GPIOHS17 51 GPIOHS18 52 GPIOHS19 53 GPIOHS20 54 GPIOHS21 55 GPIOHS22 56 GPIOHS23 57 GPIOHS24 58 GPIOHS25 59 GPIOHS26 60 GPIOHS27 61 GPIOHS28 62 GPIOHS29 63 GPIOHS30 64 GPIOHS31 65 KPU Neural Network Accelerator KPU 0x40800000 layer_argument_fifo Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register 0x00 64 interrupt_status Interrupt status 0x08 64 calc_done Interrupt raised when calculation is done [0:0] layer_cfg_almost_empty Interrupt raised when layer arguments FIFO almost empty [1:1] layer_cfg_almost_full Interrupt raised when layer arguments FIFO almost full [2:2] interrupt_raw Interrupt raw 0x10 64 interrupt_mask Interrupt mask: 0 enables the interrupt, 1 masks the interrupt 0x18 64 interrupt_clear Interrupt clear: write 1 to a bit to clear interrupt 0x20 64 fifo_threshold FIFO threshold 0x28 64 full_threshold FIFO full threshold [3:0] empty_threshold FIFO empty threshold [7:4] fifo_data_out FIFO data output 0x30 64 fifo_ctrl FIFO control 0x38 64 dma_fifo_flush_n Flush DMA FIFO [0:0] gs_fifo_flush_n Flush GS FIFO [1:1] cfg_fifo_flush_n Flush configuration FIFO [2:2] cmd_fifo_flush_n Flush command FIFO [3:3] resp_fifo_flush_n Flush response FIFO [4:4] eight_bit_mode Eight bit mode 0x40 64 eight_bit_mode Use 8-bit instead of 16-bit precision if set [0:0] KPU 25 FFT Fast Fourier Transform Accelerator FFT 0x42000000 input_fifo FFT input data fifo 0x00 64 ctrl FFT control register 0x08 64 point FFT calculation data length [2:0] p512 512 point 0 p256 256 point 1 p128 128 point 2 p64 64 point 3 mode FFT mode [3:3] fft FFT mode 0 ifft Inverse FFT mode 1 shift Corresponding to the nine layer butterfly shift operation, 0x0: does not shift; 0x1: shift 1st layer. ... [12:4] enable FFT enable [13:13] dma_send FFT DMA enable [14:14] input_mode Input data arrangement [16:15] riri RIRI (real imaginary interleaved) 0 rrrr RRRR (only real part) 1 rrii First input the real part and then input the imaginary part 2 data_mode Effective width of input data [17:17] width_64 64 bit effective 0 width_128 128 bit effective 1 fifo_ctrl FIFO control 0x10 64 resp_fifo_flush Response memory initialization flag [0:0] cmd_fifo_flush Command memory initialization flag [1:1] gs_fifo_flush Output interface memory initialization flag [2:2] interrupt mask intr_mask 0x18 64 fft_done FFT done [0:0] intr_clear Interrupt clear 0x20 64 fft_done FFT done [0:0] status FFT status register 0x28 64 fft_done FFT done [0:0] status_raw FFT status raw 0x30 64 fft_done FFT done [0:0] fft_work FFT work [1:1] output_fifo FFT output FIFO 0x38 64 FFT 26 DMAC Direct Memory Access Controller DMAC 0x50000000 id ID Register 0x00 64 compver COMPVER Register 0x08 64 cfg Configure Register 0x10 64 dmac_en Enable DMAC [0:0] int_en Globally enable interrupt generation [1:1] chen Channel Enable Register 0x18 64 ch1_en Enable channel 1 [0:0] ch2_en Enable channel 2 [1:1] ch3_en Enable channel 3 [2:2] ch4_en Enable channel 4 [3:3] ch5_en Enable channel 5 [4:4] ch6_en Enable channel 6 [5:5] ch1_en_we Write enable channel 1 [8:8] ch2_en_we Write enable channel 2 [9:9] ch3_en_we Write enable channel 3 [10:10] ch4_en_we Write enable channel 4 [11:11] ch5_en_we Write enable channel 5 [12:12] ch6_en_we Write enable channel 6 [13:13] ch1_susp Suspend request channel 1 [16:16] ch2_susp Suspend request channel 2 [17:17] ch3_susp Suspend request channel 3 [18:18] ch4_susp Suspend request channel 4 [19:19] ch5_susp Suspend request channel 5 [20:20] ch6_susp Suspend request channel 6 [21:21] ch1_susp_we Enable write to ch1_susp bit [24:24] ch2_susp_we Enable write to ch2_susp bit [25:25] ch3_susp_we Enable write to ch3_susp bit [26:26] ch4_susp_we Enable write to ch4_susp bit [27:27] ch5_susp_we Enable write to ch5_susp bit [28:28] ch6_susp_we Enable write to ch6_susp bit [29:29] ch1_abort Abort request channel 1 [32:32] ch2_abort Abort request channel 2 [33:33] ch3_abort Abort request channel 3 [34:34] ch4_abort Abort request channel 4 [35:35] ch5_abort Abort request channel 5 [36:36] ch6_abort Abort request channel 6 [37:37] ch1_abort_we Enable write to ch1_abort bit [40:40] ch2_abort_we Enable write to ch2_abort bit [41:41] ch3_abort_we Enable write to ch3_abort bit [42:42] ch4_abort_we Enable write to ch4_abort bit [43:43] ch5_abort_we Enable write to ch5_abort bit [44:44] ch6_abort_we Enable write to ch6_abort bit [45:45] intstatus Interrupt Status Register 0x30 64 ch1_intstat Channel 1 interrupt bit [0:0] ch2_intstat Channel 2 interrupt bit [1:1] ch3_intstat Channel 3 interrupt bit [2:2] ch4_intstat Channel 4 interrupt bit [3:3] ch5_intstat Channel 5 interrupt bit [4:4] ch6_intstat Channel 6 interrupt bit [5:5] commonreg_intstat Common register status bit [16:16] com_intclear Common Interrupt Clear Register 0x38 64 slvif_dec_err Clear slvif_dec_err interrupt in com_intstatus [0:0] slvif_wr2ro_err Clear slvif_wr2ro_err interrupt in com_intstatus [1:1] slvif_rd2wo_err Clear slvif_rd2wo_err interrupt in com_intstatus [2:2] slvif_wronhold_err Clear slvif_wronhold_err interrupt in com_intstatus [3:3] slvif_undefinedreg_dec_err Clear slvif_undefinedreg_dec_err in com_intstatus [8:8] com_intstatus_en Common Interrupt Status Enable Register 0x40 64 slvif_dec_err Slave Interface Common Register Decode Error [0:0] slvif_wr2ro_err Slave Interface Common Register Write to Read only Error [1:1] slvif_rd2wo_err Slave Interface Common Register Read to Write-only Error [2:2] slvif_wronhold_err Slave Interface Common Register Write On Hold Error [3:3] slvif_undefinedreg_dec_err Slave Interface Undefined Register Decode Error [8:8] com_intsignal_en Common Interrupt Signal Enable Register 0x48 64 slvif_dec_err Slave Interface Common Register Decode Error [0:0] slvif_wr2ro_err Slave Interface Common Register Write to Read only Error [1:1] slvif_rd2wo_err Slave Interface Common Register Read to Write-only Error [2:2] slvif_wronhold_err Slave Interface Common Register Write On Hold Error [3:3] slvif_undefinedreg_dec_err Slave Interface Undefined Register Decode Error [8:8] com_intstatus Common Interrupt Status 0x50 64 slvif_dec_err Slave Interface Common Register Decode Error [0:0] slvif_wr2ro_err Slave Interface Common Register Write to Read only Error [1:1] slvif_rd2wo_err Slave Interface Common Register Read to Write-only Error [2:2] slvif_wronhold_err Slave Interface Common Register Write On Hold Error [3:3] slvif_undefinedreg_dec_err Slave Interface Undefined Register Decode Error [8:8] reset Reset register 0x58 64 rst DMAC reset request bit [0:0] channel[%s] Channel configuration 6 0x100 0x100 64 sar SAR Address Register 0x00 dar DAR Address Register 0x08 block_ts Block Transfer Size Register 0x10 block_ts Block transfer size [21:0] ctl Control Register 0x18 sms Source master select [0:0] MASTER_SELECT axi_master_1 AXI master 1 0 axi_master_2 AXI master 2 1 dms Destination master select [2:2] sinc Source address increment [4:4] INCREMENT increment Increment address 0 nochange Don't increment address 1 dinc Destination address increment [6:6] src_tr_width Source transfer width [10:8] TRANSFER_WIDTH width_8 8 bits 0 width_16 16 bits 1 width_32 32 bits 2 width_64 64 bits 3 width_128 128 bits 4 width_256 256 bits 5 width_512 512 bits 6 dst_tr_width Destination transfer width [13:11] src_msize Source burst transaction length [17:14] BURST_LENGTH length_1 1 data item 0 length_4 4 data items 1 length_8 8 data items 2 length_16 16 data items 3 length_32 32 data items 4 length_64 64 data items 5 length_128 128 data items 6 length_256 256 data items 7 length_512 512 data items 8 length_1024 1024 data items 9 dst_msize Destination burst transaction length [21:18] nonposted_lastwrite_en Non Posted Last Write Enable (posted writes may be used till the end of the block) [30:30] arlen_en Source burst length enable [38:38] arlen Source burst length [46:39] awlen_en Destination burst length enable [47:47] awlen Destination burst length [55:48] src_stat_en Source status enable [56:56] dst_stat_en Destination status enable [57:57] ioc_blktfr Interrupt completion of block transfer [58:58] shadowreg_or_lli_last Last shadow linked list item (indicates shadowreg/LLI content is the last one) [62:62] shadowreg_or_lli_valid last shadow linked list item valid (indicate shadowreg/LLI content is valid) [63:63] cfg Configure Register 0x20 src_multblk_type Source multi-block transfer type [1:0] MULTIBLK_TRANSFER_TYPE contiguous Continuous multi-block type 0 reload Reload multi-block type 1 shadow_register Shadow register based multi-block type 2 linked_list Linked list based multi-block type 3 dst_multblk_type Destination multi-block transfer type [3:2] tt_fc Transfer type and flow control [34:32] mem2mem_dma Transfer memory to memory and flow controller is DMAC 0 mem2prf_dma Transfer memory to peripheral and flow controller is DMAC 1 prf2mem_dma Transfer peripheral to memory and flow controller is DMAC 2 prf2prf_dma Transfer peripheral to peripheral and flow controller is DMAC 3 prf2mem_prf Transfer peripheral to memory and flow controller is source peripheral 4 prf2prf_srcprf Transfer peripheral to peripheral and flow controller is source peripheral 5 mem2prf_prf Transfer memory to peripheral and flow controller is destination peripheral 6 prf2prf_dstprf Transfer peripheral to peripheral and flow controller is destination peripheral 7 hs_sel_src Source software or hardware handshaking select [35:35] HANDSHAKING hardware Hardware handshaking is used 0 software Software handshaking is used 1 hs_sel_dst Destination software or hardware handshaking select [36:36] src_hwhs_pol Source hardware handshaking interface polarity [37:37] POLARITY active_high Active high 0 active_low Active low 1 dst_hwhs_pol Destination hardware handshaking interface polarity [38:38] src_per Assign a hardware handshaking interface to source of channel [42:39] dst_per Assign a hardware handshaking interface to destination of channel [47:44] ch_prior Channel priority (7 is highest, 0 is lowest) [51:49] lock_ch Channel lock bit [52:52] lock_ch_l Channel lock level [54:53] dma_transfer Duration of channel is locked for entire DMA transfer 0 block_transfer Duration of channel is locked for current block transfer 1 transaction Duration of channel is locked for current transaction 2 src_osr_lmt Source outstanding request limit [58:55] dst_osr_lmt Destination outstanding request limit [62:59] llp Linked List Pointer register 0x28 lms LLI master select [0:0] loc Starting address memeory of LLI block [63:6] status Channel Status Register 0x30 cmpltd_blk_size Completed block transfer size [21:0] swhssrc Channel Software handshake Source Register 0x38 req Software handshake request for channel source [0:0] req_we Write enable bit for software handshake request [1:1] sglreq Software handshake single request for channel source [2:2] sglreq_we Write enable bit for software handshake [3:3] lst Software handshake last request for channel source [4:4] lst_we Write enable bit for software handshake last request [5:5] swhsdst Channel Software handshake Destination Register 0x40 req Software handshake request for channel destination [0:0] req_we Write enable bit for software handshake request [1:1] sglreq Software handshake single request for channel destination [2:2] sglreq_we Write enable bit for software handshake [3:3] lst Software handshake last request for channel destination [4:4] lst_we Write enable bit for software handshake last request [5:5] blk_tfr Channel Block Transfer Resume Request Register 0x48 resumereq Block transfer resume request [0:0] axi_id Channel AXI ID Register 0x50 axi_qos AXI QOS Register 0x58 intstatus_en Interrupt Status Enable Register 0x80 block_tfr_done Block transfer done [0:0] tfr_done Transfer done [1:1] src_transcomp Source transaction complete [3:3] dst_transcomp Destination transaction complete [4:4] src_dec_err Source Decode Error [5:5] dst_dec_err Destination Decode Error [6:6] src_slv_err Source Slave Error [7:7] dst_slv_err Destination Slave Error [8:8] lli_rd_dec_err LLI Read Decode Error Status Enable [9:9] lli_wr_dec_err LLI WRITE Decode Error [10:10] lli_rd_slv_err LLI Read Slave Error [11:11] lli_wr_slv_err LLI WRITE Slave Error [12:12] intstatus Channel Interrupt Status Register 0x88 block_tfr_done Block transfer done [0:0] tfr_done Transfer done [1:1] src_transcomp Source transaction complete [3:3] dst_transcomp Destination transaction complete [4:4] src_dec_err Source Decode Error [5:5] dst_dec_err Destination Decode Error [6:6] src_slv_err Source Slave Error [7:7] dst_slv_err Destination Slave Error [8:8] lli_rd_dec_err LLI Read Decode Error Status Enable [9:9] lli_wr_dec_err LLI WRITE Decode Error [10:10] lli_rd_slv_err LLI Read Slave Error [11:11] lli_wr_slv_err LLI WRITE Slave Error [12:12] intsignal_en Interrupt Signal Enable Register 0x90 block_tfr_done Block transfer done [0:0] tfr_done Transfer done [1:1] src_transcomp Source transaction complete [3:3] dst_transcomp Destination transaction complete [4:4] src_dec_err Source Decode Error [5:5] dst_dec_err Destination Decode Error [6:6] src_slv_err Source Slave Error [7:7] dst_slv_err Destination Slave Error [8:8] lli_rd_dec_err LLI Read Decode Error Status Enable [9:9] lli_wr_dec_err LLI WRITE Decode Error [10:10] lli_rd_slv_err LLI Read Slave Error [11:11] lli_wr_slv_err LLI WRITE Slave Error [12:12] intclear Interrupt Clear Register 0x98 block_tfr_done Block transfer done [0:0] tfr_done Transfer done [1:1] src_transcomp Source transaction complete [3:3] dst_transcomp Destination transaction complete [4:4] src_dec_err Source Decode Error [5:5] dst_dec_err Destination Decode Error [6:6] src_slv_err Source Slave Error [7:7] dst_slv_err Destination Slave Error [8:8] lli_rd_dec_err LLI Read Decode Error Status Enable [9:9] lli_wr_dec_err LLI WRITE Decode Error [10:10] lli_rd_slv_err LLI Read Slave Error [11:11] lli_wr_slv_err LLI WRITE Slave Error [12:12] _reserved Padding to make structure size 256 bytes so that channels[] is an array 0xf8 DMA0 27 DMA1 28 DMA2 29 DMA3 30 DMA4 31 DMA5 32 GPIO General Purpose Input/Output Interface GPIO 0x50200000 data_output Data (output) registers 0x00 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 direction Data direction registers 0x04 pin0 0 0 DIRECTION input Pin is input 0 output Pin is output 1 pin111 pin222 pin333 pin444 pin555 pin666 pin777 source Data source registers 0x08 interrupt_enable Interrupt enable/disable registers 0x30 interrupt_mask Interrupt mask registers 0x34 interrupt_level Interrupt level registers 0x38 interrupt_polarity Interrupt polarity registers 0x3c interrupt_status Interrupt status registers 0x40 interrupt_status_raw Raw interrupt status registers 0x44 interrupt_debounce Interrupt debounce registers 0x48 interrupt_clear Registers for clearing interrupts 0x4c data_input External port (data input) registers 0x50 pin000 pin111 pin222 pin333 pin444 pin555 pin666 pin777 sync_level Sync level registers 0x60 id_code ID code 0x64 interrupt_bothedge Interrupt both edge type 0x68 APB_GPIO 23 UART1 Universal Asynchronous Receiver-Transmitter 1 UART 0x50210000 rbr_dll_thr Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W) 0x00 dlh_ier Divisor Latch (High) / Interrupt Enable Register 0x04 fcr_iir FIFO Control Register / Interrupt Identification Register 0x08 lcr Line Control Register 0x0c mcr Modem Control Register 0x10 lsr Line Status Register 0x14 msr Modem Status Register 0x18 scr Scratchpad Register 0x1c lpdll Low Power Divisor Latch (Low) Register 0x20 lpdlh Low Power Divisor Latch (High) Register 0x24 srbr_sthr[%s] 16 4 Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W) 0x30 far FIFO Access Register 0x70 tfr Transmit FIFO Read Register 0x74 rfw Receive FIFO Write Register 0x78 usr UART Status Register 0x7c tfl Transmit FIFO Level 0x80 rfl Receive FIFO Level 0x84 srr Software Reset Register 0x88 srts Shadow Request to Send Register 0x8c sbcr Shadow Break Control Register 0x90 sdmam Shadow DMA Mode 0x94 sfe Shadow FIFO Enable 0x98 srt Shadow RCVR Trigger Register 0x9c stet Shadow TX Empty Trigger Register 0xa0 htx Halt TX Regster 0xa4 dmasa DMA Software Acknowledge Register 0xa8 tcr Transfer Control Register 0xac de_en DE Enable Register 0xb0 re_en RE Enable Register 0xb4 det DE Assertion Time Register 0xb8 tat Turn-Around Time Register 0xbc dlf Divisor Latch (Fractional) Register 0xc0 rar Receive-Mode Address Register 0xc4 tar Transmit-Mode Address Register 0xc8 lcr_ext Line Control Register (Extended) 0xcc cpr Component Parameter Register 0xf4 ucv UART Component Version 0xf8 ctr Component Type Register 0xfc UART1 11 UART2 Universal Asynchronous Receiver-Transmitter 2 0x50220000 UART2 12 UART3 Universal Asynchronous Receiver-Transmitter 3 0x50230000 UART3 13 SPI0 Serial Peripheral Interface 0 (master) SPI 0x52000000 ctrlr0 Control Register 0 0x00 work_mode WORK_MODE [7:6] mode0 MODE_0 0 mode1 MODE_1 1 mode2 MODE_2 2 mode3 MODE_3 3 tmod TRANSFER_MODE [9:8] trans_recv TRANS_RECV 0 trans TRANS 1 recv RECV 2 eerom EEROM 3 frame_format FRAME_FORMAT [22:21] standard STANDARD 0 dual DUAL 1 quad QUAD 2 octal OCTAL 3 data_length DATA_BIT_LENGTH [20:16] 331 ctrlr1 Control Register 1 0x04 ssienr Enable Register 0x08 mwcr Microwire Control Register 0x0c ser Slave Enable Register 0x10 baudr Baud Rate Select 0x14 txftlr Transmit FIFO Threshold Level 0x18 rxftlr Receive FIFO Threshold Level 0x1c txflr Transmit FIFO Level Register 0x20 rxflr Receive FIFO Level Register 0x24 sr Status Register 0x28 imr Interrupt Mask Register 0x2c isr Interrupt Status Register 0x30 risr Raw Interrupt Status Register 0x34 txoicr Transmit FIFO Overflow Interrupt Clear Register 0x38 rxoicr Receive FIFO Overflow Interrupt Clear Register 0x3c rxuicr Receive FIFO Underflow Interrupt Clear Register 0x40 msticr Multi-Master Interrupt Clear Register 0x44 icr Interrupt Clear Register 0x48 dmacr DMA Control Register 0x4c dmatdlr DMA Transmit Data Level 0x50 dmardlr DMA Receive Data Level 0x54 idr Identification Register 0x58 ssic_version_id DWC_ssi component version 0x5c dr%s Data Register 0x60 36 0-35 0x4 rx_sample_delay RX Sample Delay Register 0xf0 spi_ctrlr0 SPI Control Register 0xf4 aitm instruction_address_trans_mode [1:0] standard STANDARD 0 addr_standard ADDR_STANDARD 1 as_frame_format AS_FRAME_FORMAT 2 addr_length ADDR_LENGTH [5:2] inst_length INSTRUCTION_LENGTH [9:8] wait_cycles WAIT_CYCLES [15:11] 031 xip_mode_bits XIP Mode bits 0xfc xip_incr_inst XIP INCR transfer opcode 0x100 xip_wrap_inst XIP WRAP transfer opcode 0x104 xip_ctrl XIP Control Register 0x108 xip_ser XIP Slave Enable Register 0x10c xrxoicr XIP Receive FIFO Overflow Interrupt Clear Register 0x110 xip_cnt_time_out XIP time out register for continuous transfers 0x114 endian ENDIAN 0x118 SPI0 1 SPI1 Serial Peripheral Interface 1 (master) 0x53000000 SPI1 2 SPI2 Serial Peripheral Interface 2 (slave) 0x50240000 dummy Dummy register: this peripheral is not implemented yet 0x00 SPI_SLAVE 3 SPI3 Serial Peripheral Interface 3 (master) 0x54000000 ctrlr0 Control Register 0 0x00 data_length DATA_BIT_LENGTH [4:0] 331 work_mode WORK_MODE [9:8] mode0 MODE_0 0 mode1 MODE_1 1 mode2 MODE_2 2 mode3 MODE_3 3 tmod TRANSFER_MODE [11:10] trans_recv TRANS_RECV 0 trans TRANS 1 recv RECV 2 eerom EEROM 3 frame_format FRAME_FORMAT [23:22] standard STANDARD 0 dual DUAL 1 quad QUAD 2 octal OCTAL 3 ctrlr1 Control Register 1 0x04 ssienr Enable Register 0x08 mwcr Microwire Control Register 0x0c ser Slave Enable Register 0x10 baudr Baud Rate Select 0x14 txftlr Transmit FIFO Threshold Level 0x18 rxftlr Receive FIFO Threshold Level 0x1c txflr Transmit FIFO Level Register 0x20 rxflr Receive FIFO Level Register 0x24 sr Status Register 0x28 imr Interrupt Mask Register 0x2c isr Interrupt Status Register 0x30 risr Raw Interrupt Status Register 0x34 txoicr Transmit FIFO Overflow Interrupt Clear Register 0x38 rxoicr Receive FIFO Overflow Interrupt Clear Register 0x3c rxuicr Receive FIFO Underflow Interrupt Clear Register 0x40 msticr Multi-Master Interrupt Clear Register 0x44 icr Interrupt Clear Register 0x48 dmacr DMA Control Register 0x4c dmatdlr DMA Transmit Data Level 0x50 dmardlr DMA Receive Data Level 0x54 idr Identification Register 0x58 ssic_version_id DWC_ssi component version 0x5c dr%s Data Register 0x60 36 0-35 0x4 rx_sample_delay RX Sample Delay Register 0xf0 spi_ctrlr0 SPI Control Register 0xf4 aitm instruction_address_trans_mode [1:0] standard STANDARD 0 addr_standard ADDR_STANDARD 1 as_frame_format AS_FRAME_FORMAT 2 addr_length ADDR_LENGTH [5:2] inst_length INSTRUCTION_LENGTH [9:8] wait_cycles WAIT_CYCLES [15:11] 031 xip_mode_bits XIP Mode bits 0xfc xip_incr_inst XIP INCR transfer opcode 0x100 xip_wrap_inst XIP WRAP transfer opcode 0x104 xip_ctrl XIP Control Register 0x108 xip_ser XIP Slave Enable Register 0x10c xrxoicr XIP Receive FIFO Overflow Interrupt Clear Register 0x110 xip_cnt_time_out XIP time out register for continuous transfers 0x114 endian ENDIAN 0x118 SPI3 4 I2S0 Inter-Integrated Sound Interface 0 I2S 0x50250000 ier Enable Register 0x00 ien I2S Enable [0:0] irer Receiver Block Enable Register 0x04 rxen Receiver block enable [0:0] iter Transmitter Block Enable Register 0x08 txen Transmitter block enable [0:0] cer Clock Generation enable 0x0c clken Transmitter block enable [0:0] ccr Clock Configuration Register 0x10 clk_gate Gating of sclk [2:0] no Clock gating is disabled 0 cycles12 Gating after 12 sclk cycles 1 cycles16 Gating after 16 sclk cycles 2 cycles20 Gating after 20 sclk cycles 3 cycles24 Gating after 24 sclk cycles 4 clk_word_size The number of sclk cycles for which the word select line stayd in the left aligned or right aligned mode [4:3] cycles16 16 sclk cycles 0 cycles24 24 sclk cycles 1 cycles32 32 sclk cycles 2 align_mode Alignment mode setting [7:5] standard Standard I2S format 1 right Right aligned format 2 left Left aligned format 4 dma_tx_en DMA transmit enable control [8:8] dma_rx_en DMA receive enable control [9:9] dma_divide_16 Split 32bit data to two 16 bit data and filled in left and right channel. Used with dma_tx_en or dma_rx_en [10:10] sign_expand_en SIGN_EXPAND_EN [11:11] rxffr Receiver Block FIFO Reset Register 0x14 rxffr Receiver FIFO reset [0:0] FLUSH not_flush Not flush FIFO 0 flush Flush FIFO 1 txffr Transmitter Block FIFO Reset Register 0x18 rxffr Transmitter FIFO reset [0:0] channel%s Channel cluster 0x20 4 0-3 0x40 left_rxtx Left Receive or Left Transmit Register 0x00 right_rxtx Right Receive or Right Transmit Register 0x04 rer Receive Enable Register 0x08 rxchenx Receive channel enable/disable [0:0] ter Transmit Enable Register 0x0c txchenx Transmit channel enable/disable [0:0] rcr Receive Configuration Register 0x10 wlen Desired data resolution of receiver [2:0] WLEN ignore Ignore the word length 0 resolution12 12-bit data resolution of the receiver 1 resolution16 16-bit data resolution of the receiver 2 resolution20 20-bit data resolution of the receiver 3 resolution24 24-bit data resolution of the receiver 4 resolution32 32-bit data resolution of the receiver 5 tcr Transmit Configuration Register 0x14 wlen Desired data resolution of transmitter [2:0] isr Interrupt Status Register 0x18 read-only rxda Status of receiver data avaliable interrupt [0:0] rxfo Status of data overrun interrupt for RX channel [1:1] txfe Status of transmit empty triger interrupt [4:4] txfo Status of data overrun interrupt for the TX channel [5:5] imr Interrupt Mask Register 0x1c rxdam Mask RX FIFO data avaliable interrupt [0:0] rxfom Mask RX FIFO overrun interrupt [1:1] txfem Mask TX FIFO empty interrupt [4:4] txfom Mask TX FIFO overrun interrupt [5:5] ror Receive Overrun Register 0x20 read-only rxcho Read this bit to clear RX FIFO data overrun interrupt. 0x0 for RX FIFO write valid, 0x1 for RX FIFO write overrun [0:0] tor Transmit Overrun Register 0x24 read-only txcho Read this bit to clear TX FIFO data overrun interrupt. 0x0 for TX FIFO write valid, 0x1 for TX FIFO write overrun [0:0] rfcr Receive FIFO Configuration Register 0x28 rxchdt Trigger level in the RX FIFO at which the receiver data available interrupt generate [3:0] LEVEL level1 Interrupt trigger when FIFO level is 1 0 level2 Interrupt trigger when FIFO level is 2 1 level3 Interrupt trigger when FIFO level is 3 2 level4 Interrupt trigger when FIFO level is 4 3 level5 Interrupt trigger when FIFO level is 5 4 level6 Interrupt trigger when FIFO level is 6 5 level7 Interrupt trigger when FIFO level is 7 6 level8 Interrupt trigger when FIFO level is 8 7 level9 Interrupt trigger when FIFO level is 9 8 level10 Interrupt trigger when FIFO level is 10 9 level11 Interrupt trigger when FIFO level is 11 10 level12 Interrupt trigger when FIFO level is 12 11 level13 Interrupt trigger when FIFO level is 13 12 level14 Interrupt trigger when FIFO level is 14 13 level15 Interrupt trigger when FIFO level is 15 14 level16 Interrupt trigger when FIFO level is 16 15 tfcr Transmit FIFO Configuration Register 0x2c txchet Trigger level in the TX FIFO at which the transmitter data available interrupt generate [3:0] rff Receive FIFO Flush Register 0x30 rxchfr Receiver channel FIFO reset [0:0] FLUSH not_flush Not flush an individual FIFO 0 flush Flush an indiviadual FIFO 1 tff Transmit FIFO Flush Register 0x34 rtxchfr Transmit channel FIFO reset [0:0] _reserved%s _RESERVED0 0x38 2 0-1 0x4 rxdma Receiver Block DMA Register 0x1c0 rrxdma Reset Receiver Block DMA Register 0x1c4 txdma Transmitter Block DMA Register 0x1c8 rtxdma Reset Transmitter Block DMA Register 0x1cc i2s_comp_param_2 Component Parameter Register 2 0x1f0 i2s_comp_param_1 Component Parameter Register 1 0x1f4 i2s_comp_version_1 Component Version Register 0x1f8 i2s_comp_type Component Type Register 0x1fc I2S0 5 APU Audio Processor APU 0x50250200 ch_cfg Channel Config Register 0x00 sound_ch_en BF unit sound channel enable control bits [7:0] target_dir Target direction select for valid voice output [11:8] audio_gain Audio sample gain factor [22:12] data_src_mode Audio data source configure parameter [24:24] we_sound_ch_en Write enable for sound_ch_en parameter [28:28] write-only we_target_dir Write enable for target_dir parameter [29:29] write-only we_audio_gain Write enable for audio_gain parameter [30:30] write-only we_data_src_mode Write enable for data_out_mode parameter [31:31] write-only ctl Control Register 0x04 dir_search_en Sound direction searching enable bit [0:0] search_path_reset Reset all control logic on direction search processing path [1:1] stream_gen_en Valid voice sample stream generation enable bit [4:4] voice_gen_path_reset Reset all control logic on voice stream generating path [5:5] update_voice_dir Switch to a new voice source direction [6:6] we_dir_search_en Write enable for we_dir_search_en parameter [8:8] write-only we_search_path_rst Write enable for we_search_path_rst parameter [9:9] write-only we_stream_gen Write enable for we_stream_gen parameter [10:10] write-only we_voice_gen_path_rst Write enable for we_voice_gen_path_rst parameter [11:11] write-only we_update_voice_dir Write enable for we_update_voice_dir parameter [12:12] write-only dir_bidx[%s] Direction Sample Buffer Read Index Configure Register (16 directions * 2 values * 4 indices) 0x08 32 0x04 rd_idx0 rd_idx0 [5:0] rd_idx1 rd_idx1 [13:8] rd_idx2 rd_idx2 [21:16] rd_idx3 rd_idx3 [29:24] pre_fir0_coef[%s] FIR0 pre-filter coefficients 0x88 9 0x04 tap0 Tap 0 [15:0] tap1 Tap 1 [31:16] post_fir0_coef[%s] FIR0 post-filter coefficients 0xac 9 0x04 tap0 Tap 0 [15:0] tap1 Tap 1 [31:16] pre_fir1_coef[%s] FIR1 pre-filter coeffecients 0xd0 9 0x04 tap0 Tap 0 [15:0] tap1 Tap 1 [31:16] post_fir1_coef[%s] FIR1 post-filter coefficients 0xf4 9 0x04 tap0 Tap 0 [15:0] tap1 Tap 1 [31:16] dwsz_cfg Downsize Config Register 0x118 dir_dwn_siz_rate Down-sizing ratio used for direction searching [3:0] voc_dwn_siz_rate Down-sizing ratio used for voice stream generation [7:4] smpl_shift_bits Sample precision reduction when the source sound sample precision is 20/24/32 bits [12:8] fft_cfg FFT Config Register 0x11c fft_shift_factor FFT shift factor [8:0] fft_enable FFT enable [12:12] sobuf_dma_rdata Read register for DMA to sample-out buffers 0x120 vobuf_dma_rdata Read register for DMA to voice-out buffers 0x124 int_stat Interrupt Status Register 0x128 dir_search_data_rdy Sound direction searching data ready interrupt event [0:0] voc_buf_data_rdy Voice output stream buffer data ready interrupt event [1:1] int_mask Interrupt Mask Register 0x12c dir_search_data_rdy Sound direction searching data ready interrupt event [0:0] voc_buf_data_rdy Voice output stream buffer data ready interrupt event [1:1] sat_counter Saturation Counter 0x130 counter Counter [15:0] total Total [31:16] sat_limits Saturation Limits 0x134 upper Upper limit [15:0] bottom Bottom limit [31:16] I2S1 Inter-Integrated Sound Interface 1 0x50260000 I2S1 6 I2S2 Inter-Integrated Sound Interface 2 0x50270000 I2S2 7 I2C0 Inter-Integrated Circuit Bus 0 I2C 0x50280000 con Control Register 0x00 master_mode Master Mode [0:0] speed Speed [2:1] standard STANDARD 0 fast FAST 1 highspeed HIGHSPEED 2 addr_slave_width Slave address width [3:3] b7 7-bit address 0 b10 10-bit address 1 restart_en Enable Restart [5:5] slave_disable Disable Slave [6:6] stop_det STOP_DET_IFADDRESSED [7:7] tx_empty TX_EMPTY_CTRL [8:8] tar Target Address Register 0x04 address Target Address [9:0] gc GC_OR_START [10:10] special SPECIAL [11:11] addr_master_width Master Address [12:12] b7 7-bit address 0 b10 10-bit address 1 sar Slave Address Register 0x08 address Slave Address [9:0] data_cmd Data Buffer and Command Register 0x10 cmd CMD [8:8] data Data [7:0] ss_scl_hcnt Standard Speed Clock SCL High Count Register 0x14 count COUNT [15:0] ss_scl_lcnt Standard Speed Clock SCL Low Count Register 0x18 count COUNT [15:0] intr_stat Interrupt Status Register 0x2c read-only rx_under RX_UNDER [0:0] rx_over RX_OVER [1:1] rx_full RX_FULL [2:2] tx_over TX_OVER [3:3] tx_empty TX_EMPTY [4:4] rd_req RD_REQ [5:5] tx_abrt TX_ABRT [6:6] rx_done RX_DONE [7:7] activity ACTIVITY [8:8] stop_det STOP_DET [9:9] start_det START_DET [10:10] gen_call GEN_CALL [11:11] intr_mask Interrupt Mask Register 0x30 rx_under RX_UNDER [0:0] rx_over RX_OVER [1:1] rx_full RX_FULL [2:2] tx_over TX_OVER [3:3] tx_empty TX_EMPTY [4:4] rd_req RD_REQ [5:5] tx_abrt TX_ABRT [6:6] rx_done RX_DONE [7:7] activity ACTIVITY [8:8] stop_det STOP_DET [9:9] start_det START_DET [10:10] gen_call GEN_CALL [11:11] raw_intr_stat Raw Interrupt Status Register 0x34 rx_under RX_UNDER [0:0] rx_over RX_OVER [1:1] rx_full RX_FULL [2:2] tx_over TX_OVER [3:3] tx_empty TX_EMPTY [4:4] rd_req RD_REQ [5:5] tx_abrt TX_ABRT [6:6] rx_done RX_DONE [7:7] activity ACTIVITY [8:8] stop_det STOP_DET [9:9] start_det START_DET [10:10] gen_call GEN_CALL [11:11] rx_tl Receive FIFO Threshold Register 0x38 value VALUE [2:0] tx_tl Transmit FIFO Threshold Register 0x3c value VALUE [2:0] clr_intr Clear Combined and Individual Interrupt Register 0x40 read-only clr CLR [0:0] clr_rx_under Clear RX_UNDER Interrupt Register 0x44 read-only clr CLR [0:0] clr_rx_over Clear RX_OVER Interrupt Register 0x48 read-only clr CLR [0:0] clr_tx_over Clear TX_OVER Interrupt Register 0x4c read-only clr CLR [0:0] clr_rd_req Clear RD_REQ Interrupt Register 0x50 read-only clr CLR [0:0] clr_tx_abrt Clear TX_ABRT Interrupt Register 0x54 read-only clr CLR [0:0] clr_rx_done Clear RX_DONE Interrupt Register 0x58 read-only clr CLR [0:0] clr_activity Clear ACTIVITY Interrupt Register 0x5c read-only clr CLR [0:0] clr_stop_det Clear STOP_DET Interrupt Register 0x60 read-only clr CLR [0:0] clr_start_det Clear START_DET Interrupt Register 0x64 read-only clr CLR [0:0] clr_gen_call I2C Clear GEN_CALL Interrupt Register 0x68 read-only clr CLR [0:0] enable Enable Register 0x6c enable ENABLE [0:0] abort ABORT [1:1] tx_cmd_block TX_CMD_BLOCK [2:2] status Status Register 0x70 read-only activity ACTIVITY [0:0] tfnf TFNF [1:1] tfe TFE [2:2] rfne RFNE [3:3] rff RFF [4:4] mst_activity MST_ACTIVITY [5:5] slv_activity SLV_ACTIVITY [6:6] txflr Transmit FIFO Level Register 0x74 value VALUE [2:0] rxflr Receive FIFO Level Register 0x78 value VALUE [2:0] sda_hold SDA Hold Time Length Register 0x7c tx TX [15:0] rx RX [23:16] tx_abrt_source Transmit Abort Source Register 0x80 addr7_noack 7B_ADDR_NOACK [0:0] addr1_10_noack 10B_ADDR1_NOACK [1:1] addr2_10_noack 10B_ADDR2_NOACK [2:2] txdata_noack TXDATA_NOACK [3:3] gcall_noack GCALL_NOACK [4:4] gcall_read GCALL_READ [5:5] hs_ackdet HS_ACKDET [6:6] sbyte_ackdet SBYTE_ACKDET [7:7] hs_norstrt HS_NORSTRT [8:8] sbyte_norstrt SBYTE_NORSTRT [9:9] rd_10_norstrt 10B_RD_NORSTRT [10:10] master_dis MASTER_DIS [11:11] mst_arblost MST_ARBLOST [12:12] slvflush_txfifo SLVFLUSH_TXFIFO [13:13] slv_arblost SLV_ARBLOST [14:14] slvrd_intx SLVRD_INTX [15:15] user_abrt USER_ABRT [16:16] dma_cr I2C DMA Control Register 0x88 RDMAE RDMAE [0:0] TDMAE TDMAE [1:1] dma_tdlr DMA Transmit Data Level Register 0x8c value VALUE [2:0] dma_rdlr DMA Receive Data Level Register 0x90 value VALUE [2:0] sda_setup SDA Setup Register 0x94 value VALUE [7:0] general_call ACK General Call Register 0x98 call_enable CALL_ENABLE [0:0] enable_status Enable Status Register 0x9c read-only ic_enable IC_ENABLE [0:0] slv_dis_busy SLV_DIS_BUSY [1:1] slv_rx_data_lost SLV_RX_DATA_LOST [2:2] fs_spklen SS, FS or FM+ spike suppression limit 0xa0 value VALUE [7:0] comp_param_1 Component Parameter Register 1 0xf4 read-only apb_data_width APB_DATA_WIDTH [1:0] max_speed_mode MAX_SPEED_MODE [3:2] hc_count_values HC_COUNT_VALUES [4:4] intr_io INTR_IO [5:5] has_dma HAS_DMA [6:6] encoded_params ENCODED_PARAMS [7:7] rx_buffer_depth RX_BUFFER_DEPTH [15:8] tx_buffer_depth TX_BUFFER_DEPTH [23:16] comp_version Component Version Register 0xf8 read-only value VALUE [31:0] comp_type Component Type Register 0xfc read-only value VALUE [31:0] I2C0 8 I2C1 Inter-Integrated Circuit Bus 1 0x50290000 I2C1 9 I2C2 Inter-Integrated Circuit Bus 2 0x502A0000 I2C2 10 FPIOA Field Programmable IO Array FPIOA 0x502B0000 48 0x04 io[%s] FPIOA GPIO multiplexer io array 0x00 ch_sel Channel select from 256 input [7:0] ds Driving selector [11:8] oe_en Static output enable, will AND with OE_INV [12:12] oe_inv Invert output enable [13:13] do_sel Data output select: 0 for DO, 1 for OE [14:14] do_inv Invert the result of data output select (DO_SEL) [15:15] pu Pull up enable. 0 for nothing, 1 for pull up [16:16] pd Pull down enable. 0 for nothing, 1 for pull down [17:17] sl Slew rate control enable [19:19] ie_en Static input enable, will AND with IE_INV [20:20] ie_inv Invert input enable [21:21] di_inv Invert Data input [22:22] st Schmitt trigger [23:23] pad_di Read current IO's data input [31:31] 8 0x04 tie_en[%s] FPIOA GPIO multiplexer tie enable array 0xC0 8 0x04 tie_val[%s] FPIOA GPIO multiplexer tie value array 0xE0 SHA256 SHA256 Accelerator SHA256 0x502C0000 8 0x4 result[%s] Calculated SHA256 return value 0x00 data_in SHA256 input data is written to this register 0x20 num_reg Counters register 0x28 data_cnt The total amount of data calculated by SHA256 is set by this register, and the smallest unit is 512bit [15:0] data_num Currently calculated block number. 512bit=1block [31:16] function_reg_0 Function configuration register 0 0x2C en write:SHA256 enable register. read:Calculation completed flag [0:0] overflow SHA256 calculation overflow flag [8:8] endian Endian setting [16:16] le Little endian 0 be Big endian 1 function_reg_1 Function configuration register 1 0x34 dma_en SHA and DMA handshake signals enable. 1:enable; 0:disable [0:0] fifo_in_full 1:SHA256 input fifo is full; 0:not full [8:8] TIMER0 Timer 0 TIMER 0x502D0000 channel%s Channel cluster: load_count, current_value, control, eoi and intr_stat registers 0x0 4 0-3 0x14 load_count Load Count Register 0x00 current_value Current Value Register 0x04 control Control Register 0x08 enable ENABLE [0:0] mode MODE [1:1] free FREE_MODE 0 user USER_MODE 1 interrupt INTERRUPT_MASK [2:2] pwm_enable PWM_ENABLE [3:3] eoi Interrupt Clear Register 0x0c intr_stat Interrupt Status Register 0x10 intr_stat Interrupt Status Register 0xa0 eoi Interrupt Clear Register 0xa4 raw_intr_stat Raw Interrupt Status Register 0xa8 comp_version Component Version Register 0xac load_count2%s Load Count2 Register 0xb0 4 0-3 0x4 TIMER0A 14 TIMER0 channel 0 or 1 interrupt TIMER0B 15 TIMER0 channel 2 or 3 interrupt TIMER1 Timer 1 0x502E0000 TIMER1A 16 TIMER1 channel 0 or 1 interrupt TIMER1B 17 TIMER1 channel 2 or 3 interrupt TIMER2 Timer 2 0x502F0000 TIMER2A 18 TIMER2 channel 0 or 1 interrupt TIMER2B 19 TIMER2 channel 2 or 3 interrupt WDT0 Watchdog Timer 0 WDT 0x50400000 cr Control Register 0x00 enable enable [0:0] rmod rmod [1:1] reset RESET 0 interrupt INTERRUPT 1 rpl rpl [4:2] torr Timeout Range Register 0x04 top0 top (lower half) [3:0] top1 top (upper half) [7:4] ccvr Current Counter Value Register 0x08 crr Counter Restart Register 0x0c stat Interrupt Status Register 0x10 stat stat [0:0] eoi Interrupt Clear Register 0x14 eoi eoi [0:0] prot_level Protection level Register 0x1c prot_level prot_level [2:0] comp_param_5 Component Parameters Register 5 0xe4 user_top_max user_top_max [31:0] comp_param_4 Component Parameters Register 4 0xe8 user_top_init_max user_top_init_max [31:0] comp_param_3 Component Parameters Register 3 0xec top_rst top_rst [31:0] comp_param_2 Component Parameters Register 2 0xf0 cnt_rst cnt_rst [31:0] comp_param_1 Component Parameters Register 1 0xf4 always_en always_en [0:0] dflt_rmod dflt_rmod [1:1] dual_top dual_top [2:2] hc_rmod hc_rmod [3:3] hc_rpl hc_rpl [4:4] hc_top hc_top [5:5] use_fix_top use_fix_top [6:6] pause pause [7:7] apb_data_width apb_data_width [9:8] dflt_rpl dflt_rpl [12:10] dflt_top dflt_top [19:16] dflt_top_init dflt_top_init [23:20] cnt_width cnt_width [28:24] comp_version Component Version Register 0xf8 comp_type Component Type Register 0xfc WDT0 21 WDT1 Watchdog Timer 1 0x50410000 WDT1 22 OTP One-Time Programmable Memory Controller OTP 0x50420000 dummy Dummy register: this peripheral is not implemented yet 0x00 DVP Digital Video Port DVP 0x50430000 dvp_cfg Config Register 0x00 start_int_enable START_INT_ENABLE [0:0] finish_int_enable FINISH_INT_ENABLE [1:1] ai_output_enable AI_OUTPUT_ENABLE [2:2] display_output_enable DISPLAY_OUTPUT_ENABLE [3:3] auto_enable AUTO_ENABLE [4:4] burst_size_4beats BURST_SIZE_4BEATS [8:8] format FORMAT [10:9] rgb RGB_FORMAT 0 yuv YUV_FORMAT 1 y Y_FORMAT 3 href_burst_num HREF_BURST_NUM [19:12] line_num LINE_NUM [29:20] r_addr R_ADDR 0x04 g_addr G_ADDR 0x08 b_addr B_ADDR 0x0c cmos_cfg CMOS Config Register 0x10 clk_div CLK_DIV [7:0] clk_enable CLK_ENABLE [8:8] reset RESET [16:16] power_down POWER_DOWN [24:24] sccb_cfg SCCB Config Register 0x14 byte_num BYTE_NUM [1:0] num2 BYTE_NUM_2 1 num3 BYTE_NUM_3 2 num4 BYTE_NUM_4 3 scl_lcnt SCL_LCNT [15:8] scl_hcnt SCL_HCNT [23:16] rdata RDATA [31:24] read-only sccb_ctl SCCB Control Register 0x18 device_address DEVICE_ADDRESS [7:0] reg_address REG_ADDRESS [15:8] wdata_byte0 WDATA_BYTE0 [23:16] wdata_byte1 WDATA_BYTE1 [31:24] axi AXI Register 0x1c gm_mlen GM_MLEN [7:0] byte1 GM_MLEN_1BYTE 0 byte4 GM_MLEN_4BYTE 3 sts STS Register 0x20 frame_start FRAME_START [0:0] frame_start_we FRAME_START_WE [1:1] frame_finish FRAME_FINISH [8:8] frame_finish_we FRAME_FINISH_WE [9:9] dvp_en DVP_EN [16:16] dvp_en_we DVP_EN_WE [17:17] sccb_en SCCB_EN [24:24] sccb_en_we SCCB_EN_WE [25:25] reverse REVERSE 0x24 rgb_addr RGB_ADDR 0x28 DVP 24 SYSCTL System Controller SYSCTL 0x50440000 git_id Git short commit id 0x00 clk_freq System clock base frequency 0x04 pll0 PLL0 controller 0x08 clkr [3:0] clkf [9:4] clkod [13:10] bwadj [19:14] reset [20:20] pwrd [21:21] intfb [22:22] bypass [23:23] test [24:24] out_en [25:25] test_en [26:26] pll1 PLL1 controller 0x0c clkr [3:0] clkf [9:4] clkod [13:10] bwadj [19:14] reset [20:20] pwrd [21:21] intfb [22:22] bypass [23:23] test [24:24] out_en [25:25] pll2 PLL2 controller 0x10 clkr [3:0] clkf [9:4] clkod [13:10] bwadj [19:14] reset [20:20] pwrd [21:21] intfb [22:22] bypass [23:23] test [24:24] out_en [25:25] ckin_sel [27:26] pll_lock PLL lock tester 0x18 pll_lock0 [1:0] pll_slip_clear0 [2:2] test_clk_out0 [3:3] pll_lock1 [9:8] pll_slip_clear1 [10:10] test_clk_out1 [11:11] pll_lock2 [17:16] pll_slip_clear2 [18:18] test_clk_out2 [19:19] rom_error AXI ROM detector 0x1c rom_mul_error [0:0] rom_one_error [1:1] clk_sel0 Clock select controller 0 0x20 aclk_sel [0:0] aclk_divider_sel [2:1] apb0_clk_sel [5:3] apb1_clk_sel [8:6] apb2_clk_sel [11:9] spi3_clk_sel [12:12] timer0_clk_sel [13:13] timer1_clk_sel [14:14] timer2_clk_sel [15:15] clk_sel1 Clock select controller 1 0x24 spi3_sample_clk_sel [0:0] clk_en_cent Central clock enable 0x28 cpu_clk_en [0:0] sram0_clk_en [1:1] sram1_clk_en [2:2] apb0_clk_en [3:3] apb1_clk_en [4:4] apb2_clk_en [5:5] clk_en_peri Peripheral clock enable 0x2c rom_clk_en [0:0] dma_clk_en [1:1] ai_clk_en [2:2] dvp_clk_en [3:3] fft_clk_en [4:4] gpio_clk_en [5:5] spi0_clk_en [6:6] spi1_clk_en [7:7] spi2_clk_en [8:8] spi3_clk_en [9:9] i2s0_clk_en [10:10] i2s1_clk_en [11:11] i2s2_clk_en [12:12] i2c0_clk_en [13:13] i2c1_clk_en [14:14] i2c2_clk_en [15:15] uart1_clk_en [16:16] uart2_clk_en [17:17] uart3_clk_en [18:18] aes_clk_en [19:19] fpioa_clk_en [20:20] timer0_clk_en [21:21] timer1_clk_en [22:22] timer2_clk_en [23:23] wdt0_clk_en [24:24] wdt1_clk_en [25:25] sha_clk_en [26:26] otp_clk_en [27:27] rtc_clk_en [29:29] soft_reset Soft reset ctrl 0x30 soft_reset [0:0] peri_reset Peripheral reset controller 0x34 rom_reset [0:0] dma_reset [1:1] ai_reset [2:2] dvp_reset [3:3] fft_reset [4:4] gpio_reset [5:5] spi0_reset [6:6] spi1_reset [7:7] spi2_reset [8:8] spi3_reset [9:9] i2s0_reset [10:10] i2s1_reset [11:11] i2s2_reset [12:12] i2c0_reset [13:13] i2c1_reset [14:14] i2c2_reset [15:15] uart1_reset [16:16] uart2_reset [17:17] uart3_reset [18:18] aes_reset [19:19] fpioa_reset [20:20] timer0_reset [21:21] timer1_reset [22:22] timer2_reset [23:23] wdt0_reset [24:24] wdt1_reset [25:25] sha_reset [26:26] rtc_reset [29:29] clk_th0 Clock threshold controller 0 0x38 sram0_gclk [3:0] sram1_gclk [7:4] ai_gclk [11:8] dvp_gclk [15:12] rom_gclk [19:16] clk_th1 Clock threshold controller 1 0x3c spi0_clk [7:0] spi1_clk [15:8] spi2_clk [23:16] spi3_clk [31:24] clk_th2 Clock threshold controller 2 0x40 timer0_clk [7:0] timer1_clk [15:8] timer2_clk [23:16] clk_th3 Clock threshold controller 3 0x44 i2s0_clk [15:0] i2s1_clk [31:16] clk_th4 Clock threshold controller 4 0x48 i2s2_clk [15:0] i2s0_mclk [23:16] i2s1_mclk [31:24] clk_th5 Clock threshold controller 5 0x4c i2s2_mclk [7:0] i2c0_clk [15:8] i2c1_clk [23:16] i2c2_clk [31:24] clk_th6 Clock threshold controller 6 0x50 wdt0_clk [7:0] wdt1_clk [15:8] misc Miscellaneous controller 0x54 debug_sel [5:0] spi_dvp_data_enable [10:10] peri Peripheral controller 0x58 timer0_pause [0:0] timer1_pause [1:1] timer2_pause [2:2] timer3_pause [3:3] timer4_pause [4:4] timer5_pause [5:5] timer6_pause [6:6] timer7_pause [7:7] timer8_pause [8:8] timer9_pause [9:9] timer10_pause [10:10] timer11_pause [11:11] spi0_xip_en [12:12] spi1_xip_en [13:13] spi2_xip_en [14:14] spi3_xip_en [15:15] spi0_clk_bypass [16:16] spi1_clk_bypass [17:17] spi2_clk_bypass [18:18] i2s0_clk_bypass [19:19] i2s1_clk_bypass [20:20] i2s2_clk_bypass [21:21] jtag_clk_bypass [22:22] dvp_clk_bypass [23:23] debug_clk_bypass [24:24] spi_sleep SPI sleep controller 0x5c ssi0_sleep [0:0] ssi1_sleep [1:1] ssi2_sleep [2:2] ssi3_sleep [3:3] reset_status Reset source status 0x60 reset_sts_clr [0:0] pin_reset_sts [1:1] wdt0_reset_sts [2:2] wdt1_reset_sts [3:3] soft_reset_sts [4:4] dma_sel0 DMA handshake selector 0x64 dma_sel0 [5:0] DMASELECT ssi0_rx_req0 ssi0_tx_req1 ssi1_rx_req2 ssi1_tx_req3 ssi2_rx_req4 ssi2_tx_req5 ssi3_rx_req6 ssi3_tx_req7 i2c0_rx_req8 i2c0_tx_req9 i2c1_rx_req10 i2c1_tx_req11 i2c2_rx_req12 i2c2_tx_req13 uart1_rx_req14 uart1_tx_req15 uart2_rx_req16 uart2_tx_req17 uart3_rx_req18 uart3_tx_req19 aes_req20 sha_rx_req21 ai_rx_req22 fft_rx_req23 fft_tx_req24 i2s0_tx_req25 i2s0_rx_req26 i2s1_tx_req27 i2s1_rx_req28 i2s2_tx_req29 i2s2_rx_req30 i2s0_bf_dir_req31 i2s0_bf_voice_req32 dma_sel1 [11:6] dma_sel2 [17:12] dma_sel3 [23:18] dma_sel4 [29:24] dma_sel1 DMA handshake selector 0x68 dma_sel5 [5:0] power_sel IO Power Mode Select controller 0x6c power_mode_sel0 [0:0] power_mode_sel1 [1:1] power_mode_sel2 [2:2] power_mode_sel3 [3:3] power_mode_sel4 [4:4] power_mode_sel5 [5:5] power_mode_sel6 [6:6] power_mode_sel7 [7:7] AES AES Accelerator AES 0x50450000 4 0x04 key[%s] 1st-4th word of key 0x00 encrypt_sel Encryption or decryption select 0x10 encrypt_sel Select encryption or decryption mode [0:0] encryption Sets encryption mode 0 decryption Sets decryption mode 1 mode_ctl AES mode register 0x14 cipher_mode Cipher mode [2:0] ECB Electronic Codebook 0 CBC Cipher Block Chaining 1 GCM Galois/Counter Mode 2 key_mode Key mode [4:3] AES128 AES-128 0 AES192 AES-192 1 AES256 AES-256 2 key_order Input key order [5:5] ENDIAN be Big Endian 0 le Little Endian 1 input_order Input data order [7:7] output_order Output data order [9:9] 4 0x04 iv[%s] Initialisation Vector (96 bit for GCM, 128 bit for CBC) 0x18 endian Endian control 0x28 endian Input data endian [0:0] finish Finished status 0x2C finish AES operation finished status [0:0] not_finished Operation not finished 0 finished Operation finished 1 dma_sel DMA select 0x30 dma_sel Output to DMA if set, to CPU otherwise [0:0] aad_num GCM additional authenticated data count in bytes, minus one 0x34 pc_num Plaintext/ciphertext input data count in bytes, minus one 0x3c text_data Plaintext/ciphertext input data 0x40 aad_data Additional authenticated data 0x44 tag_chk Tag check status 0x48 tag_chk Tag check status [1:0] busy Check not finished 0 fail Check failed 1 success Check success 2 data_in_flag Data can input flag 0x4c data_in_flag Data can be written to text_data or aad_data when this flag is set [0:0] CAN_INPUT cannot_input Cannot input 0 can_input Can input 1 4 0x04 gcm_in_tag[%s] GCM input tag for comparison with the calculated tag 0x50 out_data Plaintext/ciphertext output data 0x60 en AES module enable 0x64 en AES module enable [0:0] disable Disable module 0 enable Enable module 1 data_out_flag Data can output flag 0x68 data_out_flag Data can be read from out_data when this flag is set [0:0] cannot_output Data cannot output 0 can_output Data can output 1 tag_in_flag Can input tag (when using GCM) 0x6c tag_in_flag GCM tag can be written to gcm_in_tag when this flag is set [0:0] tag_clear Tag clear (a write to this register clears the tag_chk status) 0x70 4 0x04 gcm_out_tag[%s] Computed GCM output tag 0x74 4 0x04 key_ext[%s] 5th-8th word of key 0x84 RTC Real Time Clock RTC 0x50460000 date Timer date information 0x00 week Week. Range [0,6]. 0 is Sunday. [2:0] 06 day Day. Range [1,31] or [1,30] or [1,29] or [1,28] [12:8] 131 month Month. Range [1,12] [19:16] 112 year Year. Range [0,99] [31:20] 099 time Timer time information 0x04 second Second. Range [0,59] [15:10] 059 minute Minute. Range [0,59] [21:16] 059 hour Hour. Range [0,23] [28:24] 023 alarm_date Alarm date information 0x08 week Week. Range [0,6]. 0 is Sunday. [2:0] 06 day Day. Range [1,31] or [1,30] or [1,29] or [1,28] [12:8] 131 month Month. Range [1,12] [19:16] 112 year Year. Range [0,99] [31:20] 099 alarm_time Alarm time information 0x0c second Second. Range [0,59] [15:10] 059 minute Minute. Range [0,59] [21:16] 059 hour Hour. Range [0,23] [28:24] 023 initial_count Timer counter initial value 0x10 count RTC counter initial value [31:0] current_count Timer counter current value 0x14 count RTC counter current value [31:0] interrupt_ctrl RTC interrupt settings 0x18 tick_enable TICK_ENABLE [0:0] alarm_enable Alarm interrupt enable [1:1] tick_int_mode Tick interrupt enable [3:2] alarm_compare_mask Alarm compare mask for interrupt [31:24] register_ctrl RTC register settings 0x1c read_enable RTC timer read enable [0:0] write_enable RTC timer write enable [1:1] timer_mask RTC timer mask [20:13] alarm_mask RTC alarm mask [28:21] initial_count_mask RTC counter initial count value mask [29:29] interrupt_register_mask RTC interrupt register mask [30:30] extended Timer extended information 0x28 century Century. Range [0,31] [4:0] 031 leap_year Is leap year. 1 is leap year, 0 is not leap year [5:5] not_leap 0 is not leap year 0 leap 1 is leap year 1 RTC 20