(kicad_pcb (version 4) (host pcbnew "(2017-01-31 revision 99d7a3579)-4.0")

  (general
    (links 0)
    (no_connects 0)
    (area 0 0 0 0)
    (thickness 1.6)
    (drawings 0)
    (tracks 0)
    (zones 0)
    (modules 1)
    (nets 3)
  )

  (page A4)
  (layers
    (0 F.Cu signal)
    (1 In1.Cu signal)
    (2 In2.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user hide)
    (33 F.Adhes user hide)
    (34 B.Paste user hide)
    (35 F.Paste user hide)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user hide)
    (39 F.Mask user hide)
    (40 Dwgs.User user)
    (41 Cmts.User user hide)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.2032)
    (trace_clearance 0.1524)
    (zone_clearance 0.2032)
    (zone_45_only no)
    (trace_min 0.1524)
    (segment_width 0.2)
    (edge_width 0.1)
    (via_size 0.675)
    (via_drill 0.25)
    (via_min_size 0.625)
    (via_min_drill 0.25)
    (uvia_size 0.508)
    (uvia_drill 0.127)
    (uvias_allowed no)
    (uvia_min_size 0.508)
    (uvia_min_drill 0.127)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 2.2 2.2)
    (pad_drill 1.5)
    (pad_to_mask_clearance 0)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFF7F)
    (pcbplotparams
      (layerselection 0x010fc_80000007)
      (usegerberextensions true)
      (excludeedgelayer false)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory /tmp))
  )

  (net 0 "")
  (net 1 "Net-(C1-Pad1)")
  (net 2 "Net-(C1-Pad2)")

  (net_class Default "This is the default net class."
    (clearance 0.1524)
    (trace_width 0.2032)
    (via_dia 0.675)
    (via_drill 0.25)
    (uvia_dia 0.508)
    (uvia_drill 0.127)
    (add_net "Net-(C1-Pad1)")
    (add_net "Net-(C1-Pad2)")
  )

  (net_class 50Ohm ""
    (clearance 0.1524)
    (trace_width 0.5)
    (via_dia 0.675)
    (via_drill 0.25)
    (uvia_dia 0.508)
    (uvia_drill 0.127)
  )

  (net_class High-Power ""
    (clearance 0.1524)
    (trace_width 0.2794)
    (via_dia 0.675)
    (via_drill 0.25)
    (uvia_dia 0.508)
    (uvia_drill 0.127)
  )

  (net_class Power ""
    (clearance 0.1524)
    (trace_width 0.2032)
    (via_dia 0.675)
    (via_drill 0.25)
    (uvia_dia 0.508)
    (uvia_drill 0.127)
  )

  (net_class pull ""
    (clearance 0.1524)
    (trace_width 0.1524)
    (via_dia 0.675)
    (via_drill 0.25)
    (uvia_dia 0.508)
    (uvia_drill 0.127)
  )

  (module passive:0402_C (layer F.Cu) (tedit 566EEB37) (tstamp 58A1B3CA)
    (at 100 100)
    (descr "Generic 0402 footprint, extra small\nused for resistor and capacitor")
    (path /58A1B133/58A1B14A)
    (fp_text reference C1 (at 1.9 0) (layer F.SilkS)
      (effects (font (size 0.625 0.625) (thickness 0.1)))
    )
    (fp_text value C (at 0.1 0.9) (layer F.SilkS) hide
      (effects (font (size 0.625 0.625) (thickness 0.1)))
    )
    (fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
    (fp_line (start 0.8 -0.4) (end 0.8 0.3) (layer F.SilkS) (width 0.15))
    (fp_line (start 0.8 0.3) (end -0.8 0.3) (layer F.SilkS) (width 0.15))
    (fp_line (start -0.8 0.3) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
    (fp_line (start -0.35 -0.2) (end 0.35 -0.2) (layer Dwgs.User) (width 0.1))
    (fp_line (start -0.35 0.2) (end 0.35 0.2) (layer Dwgs.User) (width 0.1))
    (fp_poly (pts (xy -0.5 -0.25) (xy -0.5 0.25) (xy -0.15 0.25) (xy -0.15 -0.25)
      (xy -0.5 -0.25)) (layer Dwgs.User) (width 0.15))
    (fp_poly (pts (xy 0.15 -0.25) (xy 0.15 0.25) (xy 0.5 0.25) (xy 0.5 -0.25)
      (xy 0.15 -0.25)) (layer Dwgs.User) (width 0.15))
    (pad 1 smd rect (at -0.5 0) (size 0.625 0.7) (layers F.Cu F.Paste F.Mask)
      (net 1 "Net-(C1-Pad1)"))
    (pad 2 smd rect (at 0.5 0) (size 0.625 0.7) (layers F.Cu F.Paste F.Mask)
      (net 2 "Net-(C1-Pad2)"))
    (model external/kicad-library/modules/packages3d/Capacitors_SMD.3dshapes/C_0402.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

)