library ("sky130_fd_sc_hd__ff_n40C_1v95") {
    technology("cmos");
    delay_model : "table_lookup";
    bus_naming_style : "%s[%d]";
    time_unit : "1ns";
    voltage_unit : "1V";
    leakage_power_unit : "1nW";
    current_unit : "1mA";
    pulling_resistance_unit : "1kohm";
    capacitive_load_unit(1.0000000000, "pf");
    revision : 1.0000000000;

    driver_model : "ramp";
    in_place_swap_mode : "match_footprint";
    input_threshold_pct_fall : 51.000000000;
    input_threshold_pct_rise : 52.000000000;
    min_pulse_width_mode : "max";
    nom_process : 1.0000000000;
    nom_temperature : -40.000000000;
    nom_voltage : 1.9500000000;
    output_threshold_pct_fall : 53.000000000;
    output_threshold_pct_rise : 54.000000000;
    simulation : "true";
    /* original: 1.0. modified to test the parser by zz */
    slew_derate_from_library : 0.98;
    slew_lower_threshold_pct_fall : 21.000000000;
    slew_lower_threshold_pct_rise : 19.000000000;
    slew_upper_threshold_pct_fall :  79.00000000;
    slew_upper_threshold_pct_rise :  78.00000000;
    switching_power_split_model : "true";

    cell ("sky130_fd_sc_hd__a211oi_1") {
        pin ("A1") {
            clock : "false";
            direction : "input";
        }
        pin ("A2") {
            clock : "false";
            direction : "input";
        }
        pin ("B1") {
            clock : "false";
            direction : "input";
        }
        pin ("C1") {
            clock : "false";
            direction : "input";
        }
        pin ("Y") {
            direction : "output";
            function : "(!A1&!B1&!C1) | (!A2&!B1&!C1)";
            power_down_function : "(!VPWR + VGND)";
            related_ground_pin : "VGND";
            related_power_pin : "VPWR";
        }
    }


    cell ("sky130_fd_sc_hd__dfbbn_1") {
        area : 32.531200000;
        ff ("IQ","IQ_N") {
            clear : "!RESET_B";
            clear_preset_var1 : "H";
            clear_preset_var2 : "L";
            clocked_on : "!CLK_N";
            next_state : "D";
            preset : "!SET_B";
        }
        pin ("CLK_N") {
            input_voltage : "GENERAL";
            capacitance : 0.0018590000;
            clock : "true";
            direction : "input";
        }
        pin ("D") {
            input_voltage : "GENERAL";
            capacitance : 0.0016840000;
            clock : "false";
            direction : "input";
            fall_capacitance : 0.0016310000;
            max_transition : 1.5000000000;
            related_ground_pin : "VGND";
            related_power_pin : "VPWR";
            rise_capacitance : 0.0017360000;
        }
        pin ("Q") {
            output_voltage : "GENERAL";
            direction : "output";
            function : "IQ";
            power_down_function : "(!VPWR + VGND)";
            related_ground_pin : "VGND";
            related_power_pin : "VPWR";
        }
        pin ("Q_N") {
            direction : "output";
            function : "IQ_N";
            max_capacitance : 0.2014260000;
            max_transition : 1.5011450000;
            power_down_function : "(!VPWR + VGND)";
            related_ground_pin : "VGND";
            related_power_pin : "VPWR";
        }
        pin ("RESET_B") {
            input_voltage : "GENERAL";
            capacitance : 0.0017000000;
            clock : "false";
            direction : "input";
        }
        pin ("SET_B") {
            input_voltage : "GENERAL";
            capacitance : 0.0036160000;
            clock : "false";
            direction : "input";
        }
    }


    cell ("sky130_fd_sc_hd__sdlclkp_4") {
        clock_gating_integrated_cell : "latch_posedge_precontrol";
        area : 22.521600000;
        cell_footprint : "sky130_fd_sc_hd__sdlclkp";
        cell_leakage_power : 0.0355517100;
        driver_waveform_fall : "ramp";
        driver_waveform_rise : "ramp";
        pg_pin ("VGND") {
            pg_type : "primary_ground";
            related_bias_pin : "VPB";
            voltage_name : "VGND";
        }
        pg_pin ("VNB") {
            pg_type : "nwell";
            physical_connection : "device_layer";
            voltage_name : "VNB";
        }
        pg_pin ("VPB") {
            pg_type : "pwell";
            physical_connection : "device_layer";
            voltage_name : "VPB";
        }
        pg_pin ("VPWR") {
            pg_type : "primary_power";
            related_bias_pin : "VNB";
            voltage_name : "VPWR";
        }
        pin ("CLK") {
            clock_gate_clock_pin : "true";
            input_voltage : "GENERAL";
            capacitance : 0.0043680000;
            clock : "true";
            direction : "input";
            fall_capacitance : 0.0041440000;
        }
        pin ("GATE") {
            clock_gate_enable_pin : "true";
            input_voltage : "GENERAL";
            capacitance : 0.0020110000;
            clock : "false";
            direction : "input";
            fall_capacitance : 0.0018330000;
        }
        pin ("GCLK") {
            clock_gate_out_pin : "true";
            output_voltage : "GENERAL";
            direction : "output";
            max_capacitance : 0.7058810000;
            max_transition : 1.5078330000;
            power_down_function : "(!VPWR + VGND)";
            related_ground_pin : "VGND";
            related_power_pin : "VPWR";
            state_function : "(CLK*M0)";
        }
        pin ("M0") {
            direction : "internal";
            internal_node : "M0";
            related_ground_pin : "VNB";
            related_power_pin : "VPWR";
        }
        pin ("SCE") {
            clock_gate_test_pin : "true";
            input_voltage : "GENERAL";
            capacitance : 0.0018980000;
            clock : "false";
            direction : "input";
            fall_capacitance : 0.0018080000;
        }
        statetable ("CLK GATE SCE","M0") {
            table : "L L L : - : L,L L H : - : H,L H L : - : H,L H H : - : H,H - - : - : N";
        }
    }
}